1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 #include "amdgpu_aca.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 47 48 #define GFX9_MEC_HPD_SIZE 4096 49 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 50 51 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 52 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 53 54 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 55 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 56 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 57 58 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 59 60 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 61 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 62 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 63 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 64 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 65 struct amdgpu_cu_info *cu_info); 66 67 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 68 uint64_t queue_mask) 69 { 70 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 71 amdgpu_ring_write(kiq_ring, 72 PACKET3_SET_RESOURCES_VMID_MASK(0) | 73 /* vmid_mask:0* queue_type:0 (KIQ) */ 74 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 75 amdgpu_ring_write(kiq_ring, 76 lower_32_bits(queue_mask)); /* queue mask lo */ 77 amdgpu_ring_write(kiq_ring, 78 upper_32_bits(queue_mask)); /* queue mask hi */ 79 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 80 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 81 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 82 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 83 } 84 85 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 86 struct amdgpu_ring *ring) 87 { 88 struct amdgpu_device *adev = kiq_ring->adev; 89 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 90 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 91 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 92 93 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 94 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 95 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 96 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 97 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 98 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 99 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 100 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 101 /*queue_type: normal compute queue */ 102 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 103 /* alloc format: all_on_one_pipe */ 104 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 105 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 106 /* num_queues: must be 1 */ 107 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 108 amdgpu_ring_write(kiq_ring, 109 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 110 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 111 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 112 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 113 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 114 } 115 116 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 117 struct amdgpu_ring *ring, 118 enum amdgpu_unmap_queues_action action, 119 u64 gpu_addr, u64 seq) 120 { 121 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 122 123 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 124 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 125 PACKET3_UNMAP_QUEUES_ACTION(action) | 126 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 127 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 128 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 129 amdgpu_ring_write(kiq_ring, 130 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 131 132 if (action == PREEMPT_QUEUES_NO_UNMAP) { 133 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 134 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 135 amdgpu_ring_write(kiq_ring, seq); 136 } else { 137 amdgpu_ring_write(kiq_ring, 0); 138 amdgpu_ring_write(kiq_ring, 0); 139 amdgpu_ring_write(kiq_ring, 0); 140 } 141 } 142 143 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 144 struct amdgpu_ring *ring, 145 u64 addr, 146 u64 seq) 147 { 148 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 149 150 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 151 amdgpu_ring_write(kiq_ring, 152 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 153 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 154 PACKET3_QUERY_STATUS_COMMAND(2)); 155 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 156 amdgpu_ring_write(kiq_ring, 157 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 158 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 159 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 160 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 161 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 162 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 163 } 164 165 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 166 uint16_t pasid, uint32_t flush_type, 167 bool all_hub) 168 { 169 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 170 amdgpu_ring_write(kiq_ring, 171 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 172 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 173 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 174 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 175 } 176 177 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 178 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 179 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 180 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 181 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 182 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 183 .set_resources_size = 8, 184 .map_queues_size = 7, 185 .unmap_queues_size = 6, 186 .query_status_size = 7, 187 .invalidate_tlbs_size = 2, 188 }; 189 190 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 191 { 192 int i, num_xcc; 193 194 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 195 for (i = 0; i < num_xcc; i++) 196 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 197 } 198 199 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 200 { 201 int i, num_xcc, dev_inst; 202 203 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 204 for (i = 0; i < num_xcc; i++) { 205 dev_inst = GET_INST(GC, i); 206 207 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 208 GOLDEN_GB_ADDR_CONFIG); 209 /* Golden settings applied by driver for ASIC with rev_id 0 */ 210 if (adev->rev_id == 0) { 211 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 212 REDUCE_FIFO_DEPTH_BY_2, 2); 213 } else { 214 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 215 SPARE, 0x1); 216 } 217 } 218 } 219 220 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 221 bool wc, uint32_t reg, uint32_t val) 222 { 223 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 224 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 225 WRITE_DATA_DST_SEL(0) | 226 (wc ? WR_CONFIRM : 0)); 227 amdgpu_ring_write(ring, reg); 228 amdgpu_ring_write(ring, 0); 229 amdgpu_ring_write(ring, val); 230 } 231 232 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 233 int mem_space, int opt, uint32_t addr0, 234 uint32_t addr1, uint32_t ref, uint32_t mask, 235 uint32_t inv) 236 { 237 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 238 amdgpu_ring_write(ring, 239 /* memory (1) or register (0) */ 240 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 241 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 242 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 243 WAIT_REG_MEM_ENGINE(eng_sel))); 244 245 if (mem_space) 246 BUG_ON(addr0 & 0x3); /* Dword align */ 247 amdgpu_ring_write(ring, addr0); 248 amdgpu_ring_write(ring, addr1); 249 amdgpu_ring_write(ring, ref); 250 amdgpu_ring_write(ring, mask); 251 amdgpu_ring_write(ring, inv); /* poll interval */ 252 } 253 254 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 255 { 256 uint32_t scratch_reg0_offset, xcc_offset; 257 struct amdgpu_device *adev = ring->adev; 258 uint32_t tmp = 0; 259 unsigned i; 260 int r; 261 262 /* Use register offset which is local to XCC in the packet */ 263 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 264 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 265 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 266 tmp = RREG32(scratch_reg0_offset); 267 268 r = amdgpu_ring_alloc(ring, 3); 269 if (r) 270 return r; 271 272 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 273 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 274 amdgpu_ring_write(ring, 0xDEADBEEF); 275 amdgpu_ring_commit(ring); 276 277 for (i = 0; i < adev->usec_timeout; i++) { 278 tmp = RREG32(scratch_reg0_offset); 279 if (tmp == 0xDEADBEEF) 280 break; 281 udelay(1); 282 } 283 284 if (i >= adev->usec_timeout) 285 r = -ETIMEDOUT; 286 return r; 287 } 288 289 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 290 { 291 struct amdgpu_device *adev = ring->adev; 292 struct amdgpu_ib ib; 293 struct dma_fence *f = NULL; 294 295 unsigned index; 296 uint64_t gpu_addr; 297 uint32_t tmp; 298 long r; 299 300 r = amdgpu_device_wb_get(adev, &index); 301 if (r) 302 return r; 303 304 gpu_addr = adev->wb.gpu_addr + (index * 4); 305 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 306 memset(&ib, 0, sizeof(ib)); 307 308 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 309 if (r) 310 goto err1; 311 312 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 313 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 314 ib.ptr[2] = lower_32_bits(gpu_addr); 315 ib.ptr[3] = upper_32_bits(gpu_addr); 316 ib.ptr[4] = 0xDEADBEEF; 317 ib.length_dw = 5; 318 319 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 320 if (r) 321 goto err2; 322 323 r = dma_fence_wait_timeout(f, false, timeout); 324 if (r == 0) { 325 r = -ETIMEDOUT; 326 goto err2; 327 } else if (r < 0) { 328 goto err2; 329 } 330 331 tmp = adev->wb.wb[index]; 332 if (tmp == 0xDEADBEEF) 333 r = 0; 334 else 335 r = -EINVAL; 336 337 err2: 338 amdgpu_ib_free(adev, &ib, NULL); 339 dma_fence_put(f); 340 err1: 341 amdgpu_device_wb_free(adev, index); 342 return r; 343 } 344 345 346 /* This value might differs per partition */ 347 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 348 { 349 uint64_t clock; 350 351 mutex_lock(&adev->gfx.gpu_clock_mutex); 352 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 353 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 354 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 355 mutex_unlock(&adev->gfx.gpu_clock_mutex); 356 357 return clock; 358 } 359 360 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 361 { 362 amdgpu_ucode_release(&adev->gfx.pfp_fw); 363 amdgpu_ucode_release(&adev->gfx.me_fw); 364 amdgpu_ucode_release(&adev->gfx.ce_fw); 365 amdgpu_ucode_release(&adev->gfx.rlc_fw); 366 amdgpu_ucode_release(&adev->gfx.mec_fw); 367 amdgpu_ucode_release(&adev->gfx.mec2_fw); 368 369 kfree(adev->gfx.rlc.register_list_format); 370 } 371 372 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 373 const char *chip_name) 374 { 375 int err; 376 const struct rlc_firmware_header_v2_0 *rlc_hdr; 377 uint16_t version_major; 378 uint16_t version_minor; 379 380 381 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 382 "amdgpu/%s_rlc.bin", chip_name); 383 if (err) 384 goto out; 385 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 386 387 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 388 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 389 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 390 out: 391 if (err) 392 amdgpu_ucode_release(&adev->gfx.rlc_fw); 393 394 return err; 395 } 396 397 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 398 { 399 return true; 400 } 401 402 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 403 { 404 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 405 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 406 } 407 408 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 409 const char *chip_name) 410 { 411 int err; 412 413 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 414 "amdgpu/%s_mec.bin", chip_name); 415 if (err) 416 goto out; 417 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 418 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 419 420 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 421 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 422 423 gfx_v9_4_3_check_if_need_gfxoff(adev); 424 425 out: 426 if (err) 427 amdgpu_ucode_release(&adev->gfx.mec_fw); 428 return err; 429 } 430 431 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 432 { 433 char ucode_prefix[15]; 434 int r; 435 436 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 437 438 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 439 if (r) 440 return r; 441 442 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 443 if (r) 444 return r; 445 446 return r; 447 } 448 449 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 450 { 451 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 452 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 453 } 454 455 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 456 { 457 int r, i, num_xcc; 458 u32 *hpd; 459 const __le32 *fw_data; 460 unsigned fw_size; 461 u32 *fw; 462 size_t mec_hpd_size; 463 464 const struct gfx_firmware_header_v1_0 *mec_hdr; 465 466 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 467 for (i = 0; i < num_xcc; i++) 468 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 469 AMDGPU_MAX_COMPUTE_QUEUES); 470 471 /* take ownership of the relevant compute queues */ 472 amdgpu_gfx_compute_queue_acquire(adev); 473 mec_hpd_size = 474 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 475 if (mec_hpd_size) { 476 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 477 AMDGPU_GEM_DOMAIN_VRAM | 478 AMDGPU_GEM_DOMAIN_GTT, 479 &adev->gfx.mec.hpd_eop_obj, 480 &adev->gfx.mec.hpd_eop_gpu_addr, 481 (void **)&hpd); 482 if (r) { 483 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 484 gfx_v9_4_3_mec_fini(adev); 485 return r; 486 } 487 488 if (amdgpu_emu_mode == 1) { 489 for (i = 0; i < mec_hpd_size / 4; i++) { 490 memset((void *)(hpd + i), 0, 4); 491 if (i % 50 == 0) 492 msleep(1); 493 } 494 } else { 495 memset(hpd, 0, mec_hpd_size); 496 } 497 498 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 499 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 500 } 501 502 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 503 504 fw_data = (const __le32 *) 505 (adev->gfx.mec_fw->data + 506 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 507 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 508 509 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 511 &adev->gfx.mec.mec_fw_obj, 512 &adev->gfx.mec.mec_fw_gpu_addr, 513 (void **)&fw); 514 if (r) { 515 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 516 gfx_v9_4_3_mec_fini(adev); 517 return r; 518 } 519 520 memcpy(fw, fw_data, fw_size); 521 522 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 523 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 524 525 return 0; 526 } 527 528 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 529 u32 sh_num, u32 instance, int xcc_id) 530 { 531 u32 data; 532 533 if (instance == 0xffffffff) 534 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 535 INSTANCE_BROADCAST_WRITES, 1); 536 else 537 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 538 INSTANCE_INDEX, instance); 539 540 if (se_num == 0xffffffff) 541 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 542 SE_BROADCAST_WRITES, 1); 543 else 544 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 545 546 if (sh_num == 0xffffffff) 547 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 548 SH_BROADCAST_WRITES, 1); 549 else 550 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 551 552 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 553 } 554 555 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 556 { 557 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 558 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 559 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 560 (address << SQ_IND_INDEX__INDEX__SHIFT) | 561 (SQ_IND_INDEX__FORCE_READ_MASK)); 562 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 563 } 564 565 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 566 uint32_t wave, uint32_t thread, 567 uint32_t regno, uint32_t num, uint32_t *out) 568 { 569 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 570 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 571 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 572 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 573 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 574 (SQ_IND_INDEX__FORCE_READ_MASK) | 575 (SQ_IND_INDEX__AUTO_INCR_MASK)); 576 while (num--) 577 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 578 } 579 580 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 581 uint32_t xcc_id, uint32_t simd, uint32_t wave, 582 uint32_t *dst, int *no_fields) 583 { 584 /* type 1 wave data */ 585 dst[(*no_fields)++] = 1; 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 596 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 597 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 598 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 599 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 600 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 601 } 602 603 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 604 uint32_t wave, uint32_t start, 605 uint32_t size, uint32_t *dst) 606 { 607 wave_read_regs(adev, xcc_id, simd, wave, 0, 608 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 609 } 610 611 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 612 uint32_t wave, uint32_t thread, 613 uint32_t start, uint32_t size, 614 uint32_t *dst) 615 { 616 wave_read_regs(adev, xcc_id, simd, wave, thread, 617 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 618 } 619 620 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 621 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 622 { 623 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 624 } 625 626 627 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 628 int num_xccs_per_xcp) 629 { 630 int ret, i, num_xcc; 631 u32 tmp = 0; 632 633 if (adev->psp.funcs) { 634 ret = psp_spatial_partition(&adev->psp, 635 NUM_XCC(adev->gfx.xcc_mask) / 636 num_xccs_per_xcp); 637 if (ret) 638 return ret; 639 } else { 640 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 641 642 for (i = 0; i < num_xcc; i++) { 643 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 644 num_xccs_per_xcp); 645 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 646 i % num_xccs_per_xcp); 647 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 648 tmp); 649 } 650 ret = 0; 651 } 652 653 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 654 655 return ret; 656 } 657 658 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 659 { 660 int xcc; 661 662 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 663 if (!xcc) { 664 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 665 return -EINVAL; 666 } 667 668 return xcc - 1; 669 } 670 671 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 672 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 673 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 674 .read_wave_data = &gfx_v9_4_3_read_wave_data, 675 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 676 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 677 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 678 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 679 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 680 }; 681 682 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 683 struct aca_bank *bank, enum aca_smu_type type, 684 void *data) 685 { 686 struct aca_bank_info info; 687 u64 misc0; 688 u32 instlo; 689 int ret; 690 691 ret = aca_bank_info_decode(bank, &info); 692 if (ret) 693 return ret; 694 695 /* NOTE: overwrite info.die_id with xcd id for gfx */ 696 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 697 instlo &= GENMASK(31, 1); 698 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 699 700 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 701 702 switch (type) { 703 case ACA_SMU_TYPE_UE: 704 ret = aca_error_cache_log_bank_error(handle, &info, 705 ACA_ERROR_TYPE_UE, 1ULL); 706 break; 707 case ACA_SMU_TYPE_CE: 708 ret = aca_error_cache_log_bank_error(handle, &info, 709 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 710 break; 711 default: 712 return -EINVAL; 713 } 714 715 return ret; 716 } 717 718 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 719 enum aca_smu_type type, void *data) 720 { 721 u32 instlo; 722 723 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 724 instlo &= GENMASK(31, 1); 725 switch (instlo) { 726 case mmSMNAID_XCD0_MCA_SMU: 727 case mmSMNAID_XCD1_MCA_SMU: 728 case mmSMNXCD_XCD0_MCA_SMU: 729 return true; 730 default: 731 break; 732 } 733 734 return false; 735 } 736 737 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 738 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 739 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 740 }; 741 742 static const struct aca_info gfx_v9_4_3_aca_info = { 743 .hwip = ACA_HWIP_TYPE_SMU, 744 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 745 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 746 }; 747 748 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 749 { 750 u32 gb_addr_config; 751 752 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 753 adev->gfx.ras = &gfx_v9_4_3_ras; 754 755 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 756 case IP_VERSION(9, 4, 3): 757 case IP_VERSION(9, 4, 4): 758 adev->gfx.config.max_hw_contexts = 8; 759 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 760 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 761 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 762 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 763 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 764 break; 765 default: 766 BUG(); 767 break; 768 } 769 770 adev->gfx.config.gb_addr_config = gb_addr_config; 771 772 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 773 REG_GET_FIELD( 774 adev->gfx.config.gb_addr_config, 775 GB_ADDR_CONFIG, 776 NUM_PIPES); 777 778 adev->gfx.config.max_tile_pipes = 779 adev->gfx.config.gb_addr_config_fields.num_pipes; 780 781 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 782 REG_GET_FIELD( 783 adev->gfx.config.gb_addr_config, 784 GB_ADDR_CONFIG, 785 NUM_BANKS); 786 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 787 REG_GET_FIELD( 788 adev->gfx.config.gb_addr_config, 789 GB_ADDR_CONFIG, 790 MAX_COMPRESSED_FRAGS); 791 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 792 REG_GET_FIELD( 793 adev->gfx.config.gb_addr_config, 794 GB_ADDR_CONFIG, 795 NUM_RB_PER_SE); 796 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 797 REG_GET_FIELD( 798 adev->gfx.config.gb_addr_config, 799 GB_ADDR_CONFIG, 800 NUM_SHADER_ENGINES); 801 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 802 REG_GET_FIELD( 803 adev->gfx.config.gb_addr_config, 804 GB_ADDR_CONFIG, 805 PIPE_INTERLEAVE_SIZE)); 806 807 return 0; 808 } 809 810 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 811 int xcc_id, int mec, int pipe, int queue) 812 { 813 unsigned irq_type; 814 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 815 unsigned int hw_prio; 816 uint32_t xcc_doorbell_start; 817 818 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 819 ring_id]; 820 821 /* mec0 is me1 */ 822 ring->xcc_id = xcc_id; 823 ring->me = mec + 1; 824 ring->pipe = pipe; 825 ring->queue = queue; 826 827 ring->ring_obj = NULL; 828 ring->use_doorbell = true; 829 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 830 xcc_id * adev->doorbell_index.xcc_doorbell_range; 831 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 832 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 833 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 834 GFX9_MEC_HPD_SIZE; 835 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 836 sprintf(ring->name, "comp_%d.%d.%d.%d", 837 ring->xcc_id, ring->me, ring->pipe, ring->queue); 838 839 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 840 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 841 + ring->pipe; 842 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 843 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 844 /* type-2 packets are deprecated on MEC, use type-3 instead */ 845 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 846 hw_prio, NULL); 847 } 848 849 static int gfx_v9_4_3_sw_init(void *handle) 850 { 851 int i, j, k, r, ring_id, xcc_id, num_xcc; 852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 853 854 adev->gfx.mec.num_mec = 2; 855 adev->gfx.mec.num_pipe_per_mec = 4; 856 adev->gfx.mec.num_queue_per_pipe = 8; 857 858 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 859 860 /* EOP Event */ 861 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 862 if (r) 863 return r; 864 865 /* Privileged reg */ 866 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 867 &adev->gfx.priv_reg_irq); 868 if (r) 869 return r; 870 871 /* Privileged inst */ 872 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 873 &adev->gfx.priv_inst_irq); 874 if (r) 875 return r; 876 877 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 878 879 r = adev->gfx.rlc.funcs->init(adev); 880 if (r) { 881 DRM_ERROR("Failed to init rlc BOs!\n"); 882 return r; 883 } 884 885 r = gfx_v9_4_3_mec_init(adev); 886 if (r) { 887 DRM_ERROR("Failed to init MEC BOs!\n"); 888 return r; 889 } 890 891 /* set up the compute queues - allocate horizontally across pipes */ 892 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 893 ring_id = 0; 894 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 895 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 896 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 897 k++) { 898 if (!amdgpu_gfx_is_mec_queue_enabled( 899 adev, xcc_id, i, k, j)) 900 continue; 901 902 r = gfx_v9_4_3_compute_ring_init(adev, 903 ring_id, 904 xcc_id, 905 i, k, j); 906 if (r) 907 return r; 908 909 ring_id++; 910 } 911 } 912 } 913 914 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 915 if (r) { 916 DRM_ERROR("Failed to init KIQ BOs!\n"); 917 return r; 918 } 919 920 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 921 if (r) 922 return r; 923 924 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 925 r = amdgpu_gfx_mqd_sw_init(adev, 926 sizeof(struct v9_mqd_allocation), xcc_id); 927 if (r) 928 return r; 929 } 930 931 r = gfx_v9_4_3_gpu_early_init(adev); 932 if (r) 933 return r; 934 935 r = amdgpu_gfx_ras_sw_init(adev); 936 if (r) 937 return r; 938 939 940 if (!amdgpu_sriov_vf(adev)) 941 r = amdgpu_gfx_sysfs_init(adev); 942 943 return r; 944 } 945 946 static int gfx_v9_4_3_sw_fini(void *handle) 947 { 948 int i, num_xcc; 949 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 950 951 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 952 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 953 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 954 955 for (i = 0; i < num_xcc; i++) { 956 amdgpu_gfx_mqd_sw_fini(adev, i); 957 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 958 amdgpu_gfx_kiq_fini(adev, i); 959 } 960 961 gfx_v9_4_3_mec_fini(adev); 962 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 963 gfx_v9_4_3_free_microcode(adev); 964 if (!amdgpu_sriov_vf(adev)) 965 amdgpu_gfx_sysfs_fini(adev); 966 967 return 0; 968 } 969 970 #define DEFAULT_SH_MEM_BASES (0x6000) 971 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 972 int xcc_id) 973 { 974 int i; 975 uint32_t sh_mem_config; 976 uint32_t sh_mem_bases; 977 uint32_t data; 978 979 /* 980 * Configure apertures: 981 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 982 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 983 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 984 */ 985 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 986 987 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 988 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 989 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 990 991 mutex_lock(&adev->srbm_mutex); 992 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 993 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 994 /* CP and shaders */ 995 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 997 998 /* Enable trap for each kfd vmid. */ 999 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1000 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1001 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1002 } 1003 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1004 mutex_unlock(&adev->srbm_mutex); 1005 1006 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1007 acccess. These should be enabled by FW for target VMIDs. */ 1008 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1009 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1010 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1011 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1012 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1013 } 1014 } 1015 1016 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1017 { 1018 int vmid; 1019 1020 /* 1021 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1022 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1023 * the driver can enable them for graphics. VMID0 should maintain 1024 * access so that HWS firmware can save/restore entries. 1025 */ 1026 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1027 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1028 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1029 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1030 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1031 } 1032 } 1033 1034 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1035 int xcc_id) 1036 { 1037 u32 tmp; 1038 int i; 1039 1040 /* XXX SH_MEM regs */ 1041 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1042 mutex_lock(&adev->srbm_mutex); 1043 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1044 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1045 /* CP and shaders */ 1046 if (i == 0) { 1047 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1048 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1049 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1050 !!adev->gmc.noretry); 1051 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1052 regSH_MEM_CONFIG, tmp); 1053 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1054 regSH_MEM_BASES, 0); 1055 } else { 1056 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1057 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1058 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1059 !!adev->gmc.noretry); 1060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1061 regSH_MEM_CONFIG, tmp); 1062 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1063 (adev->gmc.private_aperture_start >> 1064 48)); 1065 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1066 (adev->gmc.shared_aperture_start >> 1067 48)); 1068 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1069 regSH_MEM_BASES, tmp); 1070 } 1071 } 1072 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1073 1074 mutex_unlock(&adev->srbm_mutex); 1075 1076 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1077 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1078 } 1079 1080 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1081 { 1082 int i, num_xcc; 1083 1084 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1085 1086 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1087 adev->gfx.config.db_debug2 = 1088 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1089 1090 for (i = 0; i < num_xcc; i++) 1091 gfx_v9_4_3_xcc_constants_init(adev, i); 1092 } 1093 1094 static void 1095 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1096 int xcc_id) 1097 { 1098 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1099 } 1100 1101 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1102 { 1103 /* 1104 * Rlc save restore list is workable since v2_1. 1105 * And it's needed by gfxoff feature. 1106 */ 1107 if (adev->gfx.rlc.is_rlc_v2_1) 1108 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1109 } 1110 1111 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1112 { 1113 uint32_t data; 1114 1115 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1116 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1117 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1118 } 1119 1120 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1121 { 1122 uint32_t rlc_setting; 1123 1124 /* if RLC is not enabled, do nothing */ 1125 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1126 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1127 return false; 1128 1129 return true; 1130 } 1131 1132 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1133 { 1134 uint32_t data; 1135 unsigned i; 1136 1137 data = RLC_SAFE_MODE__CMD_MASK; 1138 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1139 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1140 1141 /* wait for RLC_SAFE_MODE */ 1142 for (i = 0; i < adev->usec_timeout; i++) { 1143 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1144 break; 1145 udelay(1); 1146 } 1147 } 1148 1149 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1150 int xcc_id) 1151 { 1152 uint32_t data; 1153 1154 data = RLC_SAFE_MODE__CMD_MASK; 1155 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1156 } 1157 1158 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1159 { 1160 int xcc_id, num_xcc; 1161 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1162 1163 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1164 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1165 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1166 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1167 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1168 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1169 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1170 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1171 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1172 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1173 } 1174 adev->gfx.rlc.rlcg_reg_access_supported = true; 1175 } 1176 1177 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1178 { 1179 /* init spm vmid with 0xf */ 1180 if (adev->gfx.rlc.funcs->update_spm_vmid) 1181 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1182 1183 return 0; 1184 } 1185 1186 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1187 int xcc_id) 1188 { 1189 u32 i, j, k; 1190 u32 mask; 1191 1192 mutex_lock(&adev->grbm_idx_mutex); 1193 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1194 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1195 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1196 xcc_id); 1197 for (k = 0; k < adev->usec_timeout; k++) { 1198 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1199 break; 1200 udelay(1); 1201 } 1202 if (k == adev->usec_timeout) { 1203 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1204 0xffffffff, 1205 0xffffffff, xcc_id); 1206 mutex_unlock(&adev->grbm_idx_mutex); 1207 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1208 i, j); 1209 return; 1210 } 1211 } 1212 } 1213 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1214 xcc_id); 1215 mutex_unlock(&adev->grbm_idx_mutex); 1216 1217 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1218 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1219 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1220 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1221 for (k = 0; k < adev->usec_timeout; k++) { 1222 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1223 break; 1224 udelay(1); 1225 } 1226 } 1227 1228 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1229 bool enable, int xcc_id) 1230 { 1231 u32 tmp; 1232 1233 /* These interrupts should be enabled to drive DS clock */ 1234 1235 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1236 1237 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1238 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1239 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1240 1241 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1242 } 1243 1244 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1245 { 1246 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1247 RLC_ENABLE_F32, 0); 1248 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1249 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1250 } 1251 1252 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1253 { 1254 int i, num_xcc; 1255 1256 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1257 for (i = 0; i < num_xcc; i++) 1258 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1259 } 1260 1261 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1262 { 1263 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1264 SOFT_RESET_RLC, 1); 1265 udelay(50); 1266 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1267 SOFT_RESET_RLC, 0); 1268 udelay(50); 1269 } 1270 1271 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1272 { 1273 int i, num_xcc; 1274 1275 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1276 for (i = 0; i < num_xcc; i++) 1277 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1278 } 1279 1280 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1281 { 1282 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1283 RLC_ENABLE_F32, 1); 1284 udelay(50); 1285 1286 /* carrizo do enable cp interrupt after cp inited */ 1287 if (!(adev->flags & AMD_IS_APU)) { 1288 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1289 udelay(50); 1290 } 1291 } 1292 1293 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1294 { 1295 #ifdef AMDGPU_RLC_DEBUG_RETRY 1296 u32 rlc_ucode_ver; 1297 #endif 1298 int i, num_xcc; 1299 1300 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1301 for (i = 0; i < num_xcc; i++) { 1302 gfx_v9_4_3_xcc_rlc_start(adev, i); 1303 #ifdef AMDGPU_RLC_DEBUG_RETRY 1304 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1305 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1306 if (rlc_ucode_ver == 0x108) { 1307 dev_info(adev->dev, 1308 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1309 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1310 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1311 * default is 0x9C4 to create a 100us interval */ 1312 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1313 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1314 * to disable the page fault retry interrupts, default is 1315 * 0x100 (256) */ 1316 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1317 } 1318 #endif 1319 } 1320 } 1321 1322 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1323 int xcc_id) 1324 { 1325 const struct rlc_firmware_header_v2_0 *hdr; 1326 const __le32 *fw_data; 1327 unsigned i, fw_size; 1328 1329 if (!adev->gfx.rlc_fw) 1330 return -EINVAL; 1331 1332 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1333 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1334 1335 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1336 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1337 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1338 1339 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1340 RLCG_UCODE_LOADING_START_ADDRESS); 1341 for (i = 0; i < fw_size; i++) { 1342 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1343 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1344 msleep(1); 1345 } 1346 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1347 } 1348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1349 1350 return 0; 1351 } 1352 1353 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1354 { 1355 int r; 1356 1357 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1358 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1359 /* legacy rlc firmware loading */ 1360 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1361 if (r) 1362 return r; 1363 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1364 } 1365 1366 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1367 /* disable CG */ 1368 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1369 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1370 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1371 1372 return 0; 1373 } 1374 1375 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1376 { 1377 int r, i, num_xcc; 1378 1379 if (amdgpu_sriov_vf(adev)) 1380 return 0; 1381 1382 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1383 for (i = 0; i < num_xcc; i++) { 1384 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1385 if (r) 1386 return r; 1387 } 1388 1389 return 0; 1390 } 1391 1392 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1393 unsigned vmid) 1394 { 1395 u32 reg, pre_data, data; 1396 1397 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1398 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1399 pre_data = RREG32_NO_KIQ(reg); 1400 else 1401 pre_data = RREG32(reg); 1402 1403 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1404 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1405 1406 if (pre_data != data) { 1407 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1408 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1409 } else 1410 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1411 } 1412 } 1413 1414 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1415 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1416 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1417 }; 1418 1419 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1420 uint32_t offset, 1421 struct soc15_reg_rlcg *entries, int arr_size) 1422 { 1423 int i, inst; 1424 uint32_t reg; 1425 1426 if (!entries) 1427 return false; 1428 1429 for (i = 0; i < arr_size; i++) { 1430 const struct soc15_reg_rlcg *entry; 1431 1432 entry = &entries[i]; 1433 inst = adev->ip_map.logical_to_dev_inst ? 1434 adev->ip_map.logical_to_dev_inst( 1435 adev, entry->hwip, entry->instance) : 1436 entry->instance; 1437 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1438 entry->reg; 1439 if (offset == reg) 1440 return true; 1441 } 1442 1443 return false; 1444 } 1445 1446 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1447 { 1448 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1449 (void *)rlcg_access_gc_9_4_3, 1450 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1451 } 1452 1453 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1454 bool enable, int xcc_id) 1455 { 1456 if (enable) { 1457 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1458 } else { 1459 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1460 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1461 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1462 } 1463 udelay(50); 1464 } 1465 1466 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1467 int xcc_id) 1468 { 1469 const struct gfx_firmware_header_v1_0 *mec_hdr; 1470 const __le32 *fw_data; 1471 unsigned i; 1472 u32 tmp; 1473 u32 mec_ucode_addr_offset; 1474 u32 mec_ucode_data_offset; 1475 1476 if (!adev->gfx.mec_fw) 1477 return -EINVAL; 1478 1479 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1480 1481 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1482 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1483 1484 fw_data = (const __le32 *) 1485 (adev->gfx.mec_fw->data + 1486 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1487 tmp = 0; 1488 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1489 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1490 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1491 1492 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1493 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1494 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1495 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1496 1497 mec_ucode_addr_offset = 1498 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1499 mec_ucode_data_offset = 1500 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1501 1502 /* MEC1 */ 1503 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1504 for (i = 0; i < mec_hdr->jt_size; i++) 1505 WREG32(mec_ucode_data_offset, 1506 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1507 1508 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1509 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1510 1511 return 0; 1512 } 1513 1514 /* KIQ functions */ 1515 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1516 { 1517 uint32_t tmp; 1518 struct amdgpu_device *adev = ring->adev; 1519 1520 /* tell RLC which is KIQ queue */ 1521 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1522 tmp &= 0xffffff00; 1523 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1524 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1525 tmp |= 0x80; 1526 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1527 } 1528 1529 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1530 { 1531 struct amdgpu_device *adev = ring->adev; 1532 1533 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1534 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1535 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1536 mqd->cp_hqd_queue_priority = 1537 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1538 } 1539 } 1540 } 1541 1542 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1543 { 1544 struct amdgpu_device *adev = ring->adev; 1545 struct v9_mqd *mqd = ring->mqd_ptr; 1546 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1547 uint32_t tmp; 1548 1549 mqd->header = 0xC0310800; 1550 mqd->compute_pipelinestat_enable = 0x00000001; 1551 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1552 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1553 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1554 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1555 mqd->compute_misc_reserved = 0x00000003; 1556 1557 mqd->dynamic_cu_mask_addr_lo = 1558 lower_32_bits(ring->mqd_gpu_addr 1559 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1560 mqd->dynamic_cu_mask_addr_hi = 1561 upper_32_bits(ring->mqd_gpu_addr 1562 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1563 1564 eop_base_addr = ring->eop_gpu_addr >> 8; 1565 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1566 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1567 1568 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1569 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1570 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1571 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1572 1573 mqd->cp_hqd_eop_control = tmp; 1574 1575 /* enable doorbell? */ 1576 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1577 1578 if (ring->use_doorbell) { 1579 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1580 DOORBELL_OFFSET, ring->doorbell_index); 1581 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1582 DOORBELL_EN, 1); 1583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1584 DOORBELL_SOURCE, 0); 1585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1586 DOORBELL_HIT, 0); 1587 } else { 1588 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1589 DOORBELL_EN, 0); 1590 } 1591 1592 mqd->cp_hqd_pq_doorbell_control = tmp; 1593 1594 /* disable the queue if it's active */ 1595 ring->wptr = 0; 1596 mqd->cp_hqd_dequeue_request = 0; 1597 mqd->cp_hqd_pq_rptr = 0; 1598 mqd->cp_hqd_pq_wptr_lo = 0; 1599 mqd->cp_hqd_pq_wptr_hi = 0; 1600 1601 /* set the pointer to the MQD */ 1602 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1603 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1604 1605 /* set MQD vmid to 0 */ 1606 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1607 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1608 mqd->cp_mqd_control = tmp; 1609 1610 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1611 hqd_gpu_addr = ring->gpu_addr >> 8; 1612 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1613 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1614 1615 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1616 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1617 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1618 (order_base_2(ring->ring_size / 4) - 1)); 1619 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1620 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1621 #ifdef __BIG_ENDIAN 1622 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1623 #endif 1624 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1626 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1628 mqd->cp_hqd_pq_control = tmp; 1629 1630 /* set the wb address whether it's enabled or not */ 1631 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1632 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1633 mqd->cp_hqd_pq_rptr_report_addr_hi = 1634 upper_32_bits(wb_gpu_addr) & 0xffff; 1635 1636 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1637 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1638 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1639 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1640 1641 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1642 ring->wptr = 0; 1643 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1644 1645 /* set the vmid for the queue */ 1646 mqd->cp_hqd_vmid = 0; 1647 1648 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1649 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1650 mqd->cp_hqd_persistent_state = tmp; 1651 1652 /* set MIN_IB_AVAIL_SIZE */ 1653 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1654 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1655 mqd->cp_hqd_ib_control = tmp; 1656 1657 /* set static priority for a queue/ring */ 1658 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1659 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1660 1661 /* map_queues packet doesn't need activate the queue, 1662 * so only kiq need set this field. 1663 */ 1664 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1665 mqd->cp_hqd_active = 1; 1666 1667 return 0; 1668 } 1669 1670 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1671 int xcc_id) 1672 { 1673 struct amdgpu_device *adev = ring->adev; 1674 struct v9_mqd *mqd = ring->mqd_ptr; 1675 int j; 1676 1677 /* disable wptr polling */ 1678 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1679 1680 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1681 mqd->cp_hqd_eop_base_addr_lo); 1682 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1683 mqd->cp_hqd_eop_base_addr_hi); 1684 1685 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1686 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1687 mqd->cp_hqd_eop_control); 1688 1689 /* enable doorbell? */ 1690 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1691 mqd->cp_hqd_pq_doorbell_control); 1692 1693 /* disable the queue if it's active */ 1694 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1695 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1696 for (j = 0; j < adev->usec_timeout; j++) { 1697 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1698 break; 1699 udelay(1); 1700 } 1701 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1702 mqd->cp_hqd_dequeue_request); 1703 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1704 mqd->cp_hqd_pq_rptr); 1705 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1706 mqd->cp_hqd_pq_wptr_lo); 1707 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1708 mqd->cp_hqd_pq_wptr_hi); 1709 } 1710 1711 /* set the pointer to the MQD */ 1712 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1713 mqd->cp_mqd_base_addr_lo); 1714 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1715 mqd->cp_mqd_base_addr_hi); 1716 1717 /* set MQD vmid to 0 */ 1718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1719 mqd->cp_mqd_control); 1720 1721 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1722 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1723 mqd->cp_hqd_pq_base_lo); 1724 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1725 mqd->cp_hqd_pq_base_hi); 1726 1727 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1729 mqd->cp_hqd_pq_control); 1730 1731 /* set the wb address whether it's enabled or not */ 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1733 mqd->cp_hqd_pq_rptr_report_addr_lo); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1735 mqd->cp_hqd_pq_rptr_report_addr_hi); 1736 1737 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1738 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1739 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1741 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1742 1743 /* enable the doorbell if requested */ 1744 if (ring->use_doorbell) { 1745 WREG32_SOC15( 1746 GC, GET_INST(GC, xcc_id), 1747 regCP_MEC_DOORBELL_RANGE_LOWER, 1748 ((adev->doorbell_index.kiq + 1749 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1750 2) << 2); 1751 WREG32_SOC15( 1752 GC, GET_INST(GC, xcc_id), 1753 regCP_MEC_DOORBELL_RANGE_UPPER, 1754 ((adev->doorbell_index.userqueue_end + 1755 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1756 2) << 2); 1757 } 1758 1759 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1760 mqd->cp_hqd_pq_doorbell_control); 1761 1762 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1763 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1764 mqd->cp_hqd_pq_wptr_lo); 1765 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1766 mqd->cp_hqd_pq_wptr_hi); 1767 1768 /* set the vmid for the queue */ 1769 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1770 1771 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1772 mqd->cp_hqd_persistent_state); 1773 1774 /* activate the queue */ 1775 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1776 mqd->cp_hqd_active); 1777 1778 if (ring->use_doorbell) 1779 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1780 1781 return 0; 1782 } 1783 1784 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1785 int xcc_id) 1786 { 1787 struct amdgpu_device *adev = ring->adev; 1788 int j; 1789 1790 /* disable the queue if it's active */ 1791 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1792 1793 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1794 1795 for (j = 0; j < adev->usec_timeout; j++) { 1796 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1797 break; 1798 udelay(1); 1799 } 1800 1801 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1802 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1803 1804 /* Manual disable if dequeue request times out */ 1805 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1806 } 1807 1808 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1809 0); 1810 } 1811 1812 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1813 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1814 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1815 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1816 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1817 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1818 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1819 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1820 1821 return 0; 1822 } 1823 1824 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1825 { 1826 struct amdgpu_device *adev = ring->adev; 1827 struct v9_mqd *mqd = ring->mqd_ptr; 1828 struct v9_mqd *tmp_mqd; 1829 1830 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1831 1832 /* GPU could be in bad state during probe, driver trigger the reset 1833 * after load the SMU, in this case , the mqd is not be initialized. 1834 * driver need to re-init the mqd. 1835 * check mqd->cp_hqd_pq_control since this value should not be 0 1836 */ 1837 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1838 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1839 /* for GPU_RESET case , reset MQD to a clean status */ 1840 if (adev->gfx.kiq[xcc_id].mqd_backup) 1841 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1842 1843 /* reset ring buffer */ 1844 ring->wptr = 0; 1845 amdgpu_ring_clear_ring(ring); 1846 mutex_lock(&adev->srbm_mutex); 1847 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1848 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1849 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1850 mutex_unlock(&adev->srbm_mutex); 1851 } else { 1852 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1853 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1854 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1855 mutex_lock(&adev->srbm_mutex); 1856 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1857 amdgpu_ring_clear_ring(ring); 1858 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1859 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1860 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1861 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1862 mutex_unlock(&adev->srbm_mutex); 1863 1864 if (adev->gfx.kiq[xcc_id].mqd_backup) 1865 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1866 } 1867 1868 return 0; 1869 } 1870 1871 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1872 { 1873 struct amdgpu_device *adev = ring->adev; 1874 struct v9_mqd *mqd = ring->mqd_ptr; 1875 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1876 struct v9_mqd *tmp_mqd; 1877 1878 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1879 * is not be initialized before 1880 */ 1881 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1882 1883 if (!tmp_mqd->cp_hqd_pq_control || 1884 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1885 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1886 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1887 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1888 mutex_lock(&adev->srbm_mutex); 1889 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1890 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1891 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1892 mutex_unlock(&adev->srbm_mutex); 1893 1894 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1895 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1896 } else { 1897 /* restore MQD to a clean status */ 1898 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1899 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1900 /* reset ring buffer */ 1901 ring->wptr = 0; 1902 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1903 amdgpu_ring_clear_ring(ring); 1904 } 1905 1906 return 0; 1907 } 1908 1909 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1910 { 1911 struct amdgpu_ring *ring; 1912 int j; 1913 1914 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1915 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1916 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1917 mutex_lock(&adev->srbm_mutex); 1918 soc15_grbm_select(adev, ring->me, 1919 ring->pipe, 1920 ring->queue, 0, GET_INST(GC, xcc_id)); 1921 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1922 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1923 mutex_unlock(&adev->srbm_mutex); 1924 } 1925 } 1926 1927 return 0; 1928 } 1929 1930 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1931 { 1932 struct amdgpu_ring *ring; 1933 int r; 1934 1935 ring = &adev->gfx.kiq[xcc_id].ring; 1936 1937 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1938 if (unlikely(r != 0)) 1939 return r; 1940 1941 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1942 if (unlikely(r != 0)) { 1943 amdgpu_bo_unreserve(ring->mqd_obj); 1944 return r; 1945 } 1946 1947 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1948 amdgpu_bo_kunmap(ring->mqd_obj); 1949 ring->mqd_ptr = NULL; 1950 amdgpu_bo_unreserve(ring->mqd_obj); 1951 return 0; 1952 } 1953 1954 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1955 { 1956 struct amdgpu_ring *ring = NULL; 1957 int r = 0, i; 1958 1959 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1960 1961 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1962 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1963 1964 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1965 if (unlikely(r != 0)) 1966 goto done; 1967 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1968 if (!r) { 1969 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1970 amdgpu_bo_kunmap(ring->mqd_obj); 1971 ring->mqd_ptr = NULL; 1972 } 1973 amdgpu_bo_unreserve(ring->mqd_obj); 1974 if (r) 1975 goto done; 1976 } 1977 1978 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1979 done: 1980 return r; 1981 } 1982 1983 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1984 { 1985 struct amdgpu_ring *ring; 1986 int r, j; 1987 1988 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1989 1990 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1991 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1992 1993 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1994 if (r) 1995 return r; 1996 } 1997 1998 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1999 if (r) 2000 return r; 2001 2002 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2003 if (r) 2004 return r; 2005 2006 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2007 ring = &adev->gfx.compute_ring 2008 [j + xcc_id * adev->gfx.num_compute_rings]; 2009 r = amdgpu_ring_test_helper(ring); 2010 if (r) 2011 return r; 2012 } 2013 2014 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2015 2016 return 0; 2017 } 2018 2019 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2020 { 2021 int r = 0, i, num_xcc; 2022 2023 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2024 AMDGPU_XCP_FL_NONE) == 2025 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2026 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2027 amdgpu_user_partt_mode); 2028 2029 if (r) 2030 return r; 2031 2032 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2033 for (i = 0; i < num_xcc; i++) { 2034 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2035 if (r) 2036 return r; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 2043 int xcc_id) 2044 { 2045 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 2046 } 2047 2048 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2049 { 2050 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2051 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2052 2053 if (amdgpu_sriov_vf(adev)) { 2054 /* must disable polling for SRIOV when hw finished, otherwise 2055 * CPC engine may still keep fetching WB address which is already 2056 * invalid after sw finished and trigger DMAR reading error in 2057 * hypervisor side. 2058 */ 2059 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2060 return; 2061 } 2062 2063 /* Use deinitialize sequence from CAIL when unbinding device 2064 * from driver, otherwise KIQ is hanging when binding back 2065 */ 2066 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2067 mutex_lock(&adev->srbm_mutex); 2068 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2069 adev->gfx.kiq[xcc_id].ring.pipe, 2070 adev->gfx.kiq[xcc_id].ring.queue, 0, 2071 GET_INST(GC, xcc_id)); 2072 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2073 xcc_id); 2074 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2075 mutex_unlock(&adev->srbm_mutex); 2076 } 2077 2078 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2079 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2080 } 2081 2082 static int gfx_v9_4_3_hw_init(void *handle) 2083 { 2084 int r; 2085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2086 2087 if (!amdgpu_sriov_vf(adev)) 2088 gfx_v9_4_3_init_golden_registers(adev); 2089 2090 gfx_v9_4_3_constants_init(adev); 2091 2092 r = adev->gfx.rlc.funcs->resume(adev); 2093 if (r) 2094 return r; 2095 2096 r = gfx_v9_4_3_cp_resume(adev); 2097 if (r) 2098 return r; 2099 2100 return r; 2101 } 2102 2103 static int gfx_v9_4_3_hw_fini(void *handle) 2104 { 2105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2106 int i, num_xcc; 2107 2108 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2109 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2110 2111 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2112 for (i = 0; i < num_xcc; i++) { 2113 gfx_v9_4_3_xcc_fini(adev, i); 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int gfx_v9_4_3_suspend(void *handle) 2120 { 2121 return gfx_v9_4_3_hw_fini(handle); 2122 } 2123 2124 static int gfx_v9_4_3_resume(void *handle) 2125 { 2126 return gfx_v9_4_3_hw_init(handle); 2127 } 2128 2129 static bool gfx_v9_4_3_is_idle(void *handle) 2130 { 2131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2132 int i, num_xcc; 2133 2134 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2135 for (i = 0; i < num_xcc; i++) { 2136 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2137 GRBM_STATUS, GUI_ACTIVE)) 2138 return false; 2139 } 2140 return true; 2141 } 2142 2143 static int gfx_v9_4_3_wait_for_idle(void *handle) 2144 { 2145 unsigned i; 2146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2147 2148 for (i = 0; i < adev->usec_timeout; i++) { 2149 if (gfx_v9_4_3_is_idle(handle)) 2150 return 0; 2151 udelay(1); 2152 } 2153 return -ETIMEDOUT; 2154 } 2155 2156 static int gfx_v9_4_3_soft_reset(void *handle) 2157 { 2158 u32 grbm_soft_reset = 0; 2159 u32 tmp; 2160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2161 2162 /* GRBM_STATUS */ 2163 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2164 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2165 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2166 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2167 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2168 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2169 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2170 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2171 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2172 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2173 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2174 } 2175 2176 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2177 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2178 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2179 } 2180 2181 /* GRBM_STATUS2 */ 2182 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2183 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2184 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2185 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2186 2187 2188 if (grbm_soft_reset) { 2189 /* stop the rlc */ 2190 adev->gfx.rlc.funcs->stop(adev); 2191 2192 /* Disable MEC parsing/prefetching */ 2193 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2194 2195 if (grbm_soft_reset) { 2196 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2197 tmp |= grbm_soft_reset; 2198 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2199 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2200 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2201 2202 udelay(50); 2203 2204 tmp &= ~grbm_soft_reset; 2205 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2206 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2207 } 2208 2209 /* Wait a little for things to settle down */ 2210 udelay(50); 2211 } 2212 return 0; 2213 } 2214 2215 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2216 uint32_t vmid, 2217 uint32_t gds_base, uint32_t gds_size, 2218 uint32_t gws_base, uint32_t gws_size, 2219 uint32_t oa_base, uint32_t oa_size) 2220 { 2221 struct amdgpu_device *adev = ring->adev; 2222 2223 /* GDS Base */ 2224 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2225 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2226 gds_base); 2227 2228 /* GDS Size */ 2229 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2230 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2231 gds_size); 2232 2233 /* GWS */ 2234 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2235 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2236 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2237 2238 /* OA */ 2239 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2240 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2241 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2242 } 2243 2244 static int gfx_v9_4_3_early_init(void *handle) 2245 { 2246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2247 2248 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2249 AMDGPU_MAX_COMPUTE_RINGS); 2250 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2251 gfx_v9_4_3_set_ring_funcs(adev); 2252 gfx_v9_4_3_set_irq_funcs(adev); 2253 gfx_v9_4_3_set_gds_init(adev); 2254 gfx_v9_4_3_set_rlc_funcs(adev); 2255 2256 /* init rlcg reg access ctrl */ 2257 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2258 2259 return gfx_v9_4_3_init_microcode(adev); 2260 } 2261 2262 static int gfx_v9_4_3_late_init(void *handle) 2263 { 2264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2265 int r; 2266 2267 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2268 if (r) 2269 return r; 2270 2271 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2272 if (r) 2273 return r; 2274 2275 if (adev->gfx.ras && 2276 adev->gfx.ras->enable_watchdog_timer) 2277 adev->gfx.ras->enable_watchdog_timer(adev); 2278 2279 return 0; 2280 } 2281 2282 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2283 bool enable, int xcc_id) 2284 { 2285 uint32_t def, data; 2286 2287 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2288 return; 2289 2290 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2291 regRLC_CGTT_MGCG_OVERRIDE); 2292 2293 if (enable) 2294 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2295 else 2296 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2297 2298 if (def != data) 2299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2300 regRLC_CGTT_MGCG_OVERRIDE, data); 2301 2302 } 2303 2304 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2305 bool enable, int xcc_id) 2306 { 2307 uint32_t def, data; 2308 2309 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2310 return; 2311 2312 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2313 regRLC_CGTT_MGCG_OVERRIDE); 2314 2315 if (enable) 2316 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2317 else 2318 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2319 2320 if (def != data) 2321 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2322 regRLC_CGTT_MGCG_OVERRIDE, data); 2323 } 2324 2325 static void 2326 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2327 bool enable, int xcc_id) 2328 { 2329 uint32_t data, def; 2330 2331 /* It is disabled by HW by default */ 2332 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2333 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2334 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2335 2336 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2337 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2338 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2339 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2340 2341 if (def != data) 2342 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2343 2344 /* MGLS is a global flag to control all MGLS in GFX */ 2345 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2346 /* 2 - RLC memory Light sleep */ 2347 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2348 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2349 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2350 if (def != data) 2351 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2352 } 2353 /* 3 - CP memory Light sleep */ 2354 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2355 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2356 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2357 if (def != data) 2358 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2359 } 2360 } 2361 } else { 2362 /* 1 - MGCG_OVERRIDE */ 2363 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2364 2365 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2366 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2367 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2368 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2369 2370 if (def != data) 2371 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2372 2373 /* 2 - disable MGLS in RLC */ 2374 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2375 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2376 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2377 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2378 } 2379 2380 /* 3 - disable MGLS in CP */ 2381 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2382 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2383 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2384 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2385 } 2386 } 2387 2388 } 2389 2390 static void 2391 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2392 bool enable, int xcc_id) 2393 { 2394 uint32_t def, data; 2395 2396 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2397 2398 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2399 /* unset CGCG override */ 2400 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2401 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2402 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2403 else 2404 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2405 /* update CGCG and CGLS override bits */ 2406 if (def != data) 2407 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2408 2409 /* CGCG Hysteresis: 400us */ 2410 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2411 2412 data = (0x2710 2413 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2414 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2415 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2416 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2417 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2418 if (def != data) 2419 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2420 2421 /* set IDLE_POLL_COUNT(0x33450100)*/ 2422 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2423 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2424 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2425 if (def != data) 2426 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2427 } else { 2428 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2429 /* reset CGCG/CGLS bits */ 2430 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2431 /* disable cgcg and cgls in FSM */ 2432 if (def != data) 2433 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2434 } 2435 2436 } 2437 2438 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2439 bool enable, int xcc_id) 2440 { 2441 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2442 2443 if (enable) { 2444 /* FGCG */ 2445 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2446 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2447 2448 /* CGCG/CGLS should be enabled after MGCG/MGLS 2449 * === MGCG + MGLS === 2450 */ 2451 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2452 xcc_id); 2453 /* === CGCG + CGLS === */ 2454 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2455 xcc_id); 2456 } else { 2457 /* CGCG/CGLS should be disabled before MGCG/MGLS 2458 * === CGCG + CGLS === 2459 */ 2460 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2461 xcc_id); 2462 /* === MGCG + MGLS === */ 2463 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2464 xcc_id); 2465 2466 /* FGCG */ 2467 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2468 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2469 } 2470 2471 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2472 2473 return 0; 2474 } 2475 2476 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2477 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2478 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2479 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2480 .init = gfx_v9_4_3_rlc_init, 2481 .resume = gfx_v9_4_3_rlc_resume, 2482 .stop = gfx_v9_4_3_rlc_stop, 2483 .reset = gfx_v9_4_3_rlc_reset, 2484 .start = gfx_v9_4_3_rlc_start, 2485 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2486 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2487 }; 2488 2489 static int gfx_v9_4_3_set_powergating_state(void *handle, 2490 enum amd_powergating_state state) 2491 { 2492 return 0; 2493 } 2494 2495 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2496 enum amd_clockgating_state state) 2497 { 2498 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2499 int i, num_xcc; 2500 2501 if (amdgpu_sriov_vf(adev)) 2502 return 0; 2503 2504 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2505 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2506 case IP_VERSION(9, 4, 3): 2507 case IP_VERSION(9, 4, 4): 2508 for (i = 0; i < num_xcc; i++) 2509 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2510 adev, state == AMD_CG_STATE_GATE, i); 2511 break; 2512 default: 2513 break; 2514 } 2515 return 0; 2516 } 2517 2518 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2519 { 2520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2521 int data; 2522 2523 if (amdgpu_sriov_vf(adev)) 2524 *flags = 0; 2525 2526 /* AMD_CG_SUPPORT_GFX_MGCG */ 2527 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2528 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2529 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2530 2531 /* AMD_CG_SUPPORT_GFX_CGCG */ 2532 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2533 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2534 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2535 2536 /* AMD_CG_SUPPORT_GFX_CGLS */ 2537 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2538 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2539 2540 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2541 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2542 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2543 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2544 2545 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2546 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2547 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2548 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2549 } 2550 2551 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2552 { 2553 struct amdgpu_device *adev = ring->adev; 2554 u32 ref_and_mask, reg_mem_engine; 2555 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2556 2557 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2558 switch (ring->me) { 2559 case 1: 2560 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2561 break; 2562 case 2: 2563 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2564 break; 2565 default: 2566 return; 2567 } 2568 reg_mem_engine = 0; 2569 } else { 2570 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2571 reg_mem_engine = 1; /* pfp */ 2572 } 2573 2574 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2575 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2576 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2577 ref_and_mask, ref_and_mask, 0x20); 2578 } 2579 2580 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2581 struct amdgpu_job *job, 2582 struct amdgpu_ib *ib, 2583 uint32_t flags) 2584 { 2585 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2586 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2587 2588 /* Currently, there is a high possibility to get wave ID mismatch 2589 * between ME and GDS, leading to a hw deadlock, because ME generates 2590 * different wave IDs than the GDS expects. This situation happens 2591 * randomly when at least 5 compute pipes use GDS ordered append. 2592 * The wave IDs generated by ME are also wrong after suspend/resume. 2593 * Those are probably bugs somewhere else in the kernel driver. 2594 * 2595 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2596 * GDS to 0 for this ring (me/pipe). 2597 */ 2598 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2599 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2600 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2601 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2602 } 2603 2604 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2605 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2606 amdgpu_ring_write(ring, 2607 #ifdef __BIG_ENDIAN 2608 (2 << 0) | 2609 #endif 2610 lower_32_bits(ib->gpu_addr)); 2611 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2612 amdgpu_ring_write(ring, control); 2613 } 2614 2615 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2616 u64 seq, unsigned flags) 2617 { 2618 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2619 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2620 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2621 2622 /* RELEASE_MEM - flush caches, send int */ 2623 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2624 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2625 EOP_TC_NC_ACTION_EN) : 2626 (EOP_TCL1_ACTION_EN | 2627 EOP_TC_ACTION_EN | 2628 EOP_TC_WB_ACTION_EN | 2629 EOP_TC_MD_ACTION_EN)) | 2630 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2631 EVENT_INDEX(5))); 2632 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2633 2634 /* 2635 * the address should be Qword aligned if 64bit write, Dword 2636 * aligned if only send 32bit data low (discard data high) 2637 */ 2638 if (write64bit) 2639 BUG_ON(addr & 0x7); 2640 else 2641 BUG_ON(addr & 0x3); 2642 amdgpu_ring_write(ring, lower_32_bits(addr)); 2643 amdgpu_ring_write(ring, upper_32_bits(addr)); 2644 amdgpu_ring_write(ring, lower_32_bits(seq)); 2645 amdgpu_ring_write(ring, upper_32_bits(seq)); 2646 amdgpu_ring_write(ring, 0); 2647 } 2648 2649 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2650 { 2651 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2652 uint32_t seq = ring->fence_drv.sync_seq; 2653 uint64_t addr = ring->fence_drv.gpu_addr; 2654 2655 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2656 lower_32_bits(addr), upper_32_bits(addr), 2657 seq, 0xffffffff, 4); 2658 } 2659 2660 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2661 unsigned vmid, uint64_t pd_addr) 2662 { 2663 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2664 } 2665 2666 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2667 { 2668 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2669 } 2670 2671 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2672 { 2673 u64 wptr; 2674 2675 /* XXX check if swapping is necessary on BE */ 2676 if (ring->use_doorbell) 2677 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2678 else 2679 BUG(); 2680 return wptr; 2681 } 2682 2683 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2684 { 2685 struct amdgpu_device *adev = ring->adev; 2686 2687 /* XXX check if swapping is necessary on BE */ 2688 if (ring->use_doorbell) { 2689 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2690 WDOORBELL64(ring->doorbell_index, ring->wptr); 2691 } else { 2692 BUG(); /* only DOORBELL method supported on gfx9 now */ 2693 } 2694 } 2695 2696 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2697 u64 seq, unsigned int flags) 2698 { 2699 struct amdgpu_device *adev = ring->adev; 2700 2701 /* we only allocate 32bit for each seq wb address */ 2702 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2703 2704 /* write fence seq to the "addr" */ 2705 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2706 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2707 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2708 amdgpu_ring_write(ring, lower_32_bits(addr)); 2709 amdgpu_ring_write(ring, upper_32_bits(addr)); 2710 amdgpu_ring_write(ring, lower_32_bits(seq)); 2711 2712 if (flags & AMDGPU_FENCE_FLAG_INT) { 2713 /* set register to trigger INT */ 2714 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2715 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2716 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2717 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2718 amdgpu_ring_write(ring, 0); 2719 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2720 } 2721 } 2722 2723 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2724 uint32_t reg_val_offs) 2725 { 2726 struct amdgpu_device *adev = ring->adev; 2727 2728 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2729 amdgpu_ring_write(ring, 0 | /* src: register*/ 2730 (5 << 8) | /* dst: memory */ 2731 (1 << 20)); /* write confirm */ 2732 amdgpu_ring_write(ring, reg); 2733 amdgpu_ring_write(ring, 0); 2734 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2735 reg_val_offs * 4)); 2736 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2737 reg_val_offs * 4)); 2738 } 2739 2740 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2741 uint32_t val) 2742 { 2743 uint32_t cmd = 0; 2744 2745 switch (ring->funcs->type) { 2746 case AMDGPU_RING_TYPE_GFX: 2747 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2748 break; 2749 case AMDGPU_RING_TYPE_KIQ: 2750 cmd = (1 << 16); /* no inc addr */ 2751 break; 2752 default: 2753 cmd = WR_CONFIRM; 2754 break; 2755 } 2756 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2757 amdgpu_ring_write(ring, cmd); 2758 amdgpu_ring_write(ring, reg); 2759 amdgpu_ring_write(ring, 0); 2760 amdgpu_ring_write(ring, val); 2761 } 2762 2763 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2764 uint32_t val, uint32_t mask) 2765 { 2766 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2767 } 2768 2769 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2770 uint32_t reg0, uint32_t reg1, 2771 uint32_t ref, uint32_t mask) 2772 { 2773 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2774 ref, mask); 2775 } 2776 2777 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2778 struct amdgpu_device *adev, int me, int pipe, 2779 enum amdgpu_interrupt_state state, int xcc_id) 2780 { 2781 u32 mec_int_cntl, mec_int_cntl_reg; 2782 2783 /* 2784 * amdgpu controls only the first MEC. That's why this function only 2785 * handles the setting of interrupts for this specific MEC. All other 2786 * pipes' interrupts are set by amdkfd. 2787 */ 2788 2789 if (me == 1) { 2790 switch (pipe) { 2791 case 0: 2792 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2793 break; 2794 case 1: 2795 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2796 break; 2797 case 2: 2798 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2799 break; 2800 case 3: 2801 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2802 break; 2803 default: 2804 DRM_DEBUG("invalid pipe %d\n", pipe); 2805 return; 2806 } 2807 } else { 2808 DRM_DEBUG("invalid me %d\n", me); 2809 return; 2810 } 2811 2812 switch (state) { 2813 case AMDGPU_IRQ_STATE_DISABLE: 2814 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2815 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2816 TIME_STAMP_INT_ENABLE, 0); 2817 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2818 break; 2819 case AMDGPU_IRQ_STATE_ENABLE: 2820 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2821 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2822 TIME_STAMP_INT_ENABLE, 1); 2823 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2824 break; 2825 default: 2826 break; 2827 } 2828 } 2829 2830 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2831 struct amdgpu_irq_src *source, 2832 unsigned type, 2833 enum amdgpu_interrupt_state state) 2834 { 2835 int i, num_xcc; 2836 2837 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2838 switch (state) { 2839 case AMDGPU_IRQ_STATE_DISABLE: 2840 case AMDGPU_IRQ_STATE_ENABLE: 2841 for (i = 0; i < num_xcc; i++) 2842 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2843 PRIV_REG_INT_ENABLE, 2844 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2845 break; 2846 default: 2847 break; 2848 } 2849 2850 return 0; 2851 } 2852 2853 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2854 struct amdgpu_irq_src *source, 2855 unsigned type, 2856 enum amdgpu_interrupt_state state) 2857 { 2858 int i, num_xcc; 2859 2860 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2861 switch (state) { 2862 case AMDGPU_IRQ_STATE_DISABLE: 2863 case AMDGPU_IRQ_STATE_ENABLE: 2864 for (i = 0; i < num_xcc; i++) 2865 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2866 PRIV_INSTR_INT_ENABLE, 2867 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2868 break; 2869 default: 2870 break; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2877 struct amdgpu_irq_src *src, 2878 unsigned type, 2879 enum amdgpu_interrupt_state state) 2880 { 2881 int i, num_xcc; 2882 2883 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2884 for (i = 0; i < num_xcc; i++) { 2885 switch (type) { 2886 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2887 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2888 adev, 1, 0, state, i); 2889 break; 2890 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2891 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2892 adev, 1, 1, state, i); 2893 break; 2894 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2895 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2896 adev, 1, 2, state, i); 2897 break; 2898 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2899 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2900 adev, 1, 3, state, i); 2901 break; 2902 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2903 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2904 adev, 2, 0, state, i); 2905 break; 2906 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2907 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2908 adev, 2, 1, state, i); 2909 break; 2910 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2911 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2912 adev, 2, 2, state, i); 2913 break; 2914 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2915 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2916 adev, 2, 3, state, i); 2917 break; 2918 default: 2919 break; 2920 } 2921 } 2922 2923 return 0; 2924 } 2925 2926 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2927 struct amdgpu_irq_src *source, 2928 struct amdgpu_iv_entry *entry) 2929 { 2930 int i, xcc_id; 2931 u8 me_id, pipe_id, queue_id; 2932 struct amdgpu_ring *ring; 2933 2934 DRM_DEBUG("IH: CP EOP\n"); 2935 me_id = (entry->ring_id & 0x0c) >> 2; 2936 pipe_id = (entry->ring_id & 0x03) >> 0; 2937 queue_id = (entry->ring_id & 0x70) >> 4; 2938 2939 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2940 2941 if (xcc_id == -EINVAL) 2942 return -EINVAL; 2943 2944 switch (me_id) { 2945 case 0: 2946 case 1: 2947 case 2: 2948 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2949 ring = &adev->gfx.compute_ring 2950 [i + 2951 xcc_id * adev->gfx.num_compute_rings]; 2952 /* Per-queue interrupt is supported for MEC starting from VI. 2953 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2954 */ 2955 2956 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2957 amdgpu_fence_process(ring); 2958 } 2959 break; 2960 } 2961 return 0; 2962 } 2963 2964 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2965 struct amdgpu_iv_entry *entry) 2966 { 2967 u8 me_id, pipe_id, queue_id; 2968 struct amdgpu_ring *ring; 2969 int i, xcc_id; 2970 2971 me_id = (entry->ring_id & 0x0c) >> 2; 2972 pipe_id = (entry->ring_id & 0x03) >> 0; 2973 queue_id = (entry->ring_id & 0x70) >> 4; 2974 2975 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2976 2977 if (xcc_id == -EINVAL) 2978 return; 2979 2980 switch (me_id) { 2981 case 0: 2982 case 1: 2983 case 2: 2984 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2985 ring = &adev->gfx.compute_ring 2986 [i + 2987 xcc_id * adev->gfx.num_compute_rings]; 2988 if (ring->me == me_id && ring->pipe == pipe_id && 2989 ring->queue == queue_id) 2990 drm_sched_fault(&ring->sched); 2991 } 2992 break; 2993 } 2994 } 2995 2996 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2997 struct amdgpu_irq_src *source, 2998 struct amdgpu_iv_entry *entry) 2999 { 3000 DRM_ERROR("Illegal register access in command stream\n"); 3001 gfx_v9_4_3_fault(adev, entry); 3002 return 0; 3003 } 3004 3005 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3006 struct amdgpu_irq_src *source, 3007 struct amdgpu_iv_entry *entry) 3008 { 3009 DRM_ERROR("Illegal instruction in command stream\n"); 3010 gfx_v9_4_3_fault(adev, entry); 3011 return 0; 3012 } 3013 3014 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3015 { 3016 const unsigned int cp_coher_cntl = 3017 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3018 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3019 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3020 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3021 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3022 3023 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3024 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3025 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3026 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3027 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3028 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3029 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3030 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3031 } 3032 3033 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3034 uint32_t pipe, bool enable) 3035 { 3036 struct amdgpu_device *adev = ring->adev; 3037 uint32_t val; 3038 uint32_t wcl_cs_reg; 3039 3040 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3041 val = enable ? 0x1 : 0x7f; 3042 3043 switch (pipe) { 3044 case 0: 3045 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3046 break; 3047 case 1: 3048 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3049 break; 3050 case 2: 3051 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3052 break; 3053 case 3: 3054 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3055 break; 3056 default: 3057 DRM_DEBUG("invalid pipe %d\n", pipe); 3058 return; 3059 } 3060 3061 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3062 3063 } 3064 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3065 { 3066 struct amdgpu_device *adev = ring->adev; 3067 uint32_t val; 3068 int i; 3069 3070 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3071 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3072 * around 25% of gpu resources. 3073 */ 3074 val = enable ? 0x1f : 0x07ffffff; 3075 amdgpu_ring_emit_wreg(ring, 3076 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3077 val); 3078 3079 /* Restrict waves for normal/low priority compute queues as well 3080 * to get best QoS for high priority compute jobs. 3081 * 3082 * amdgpu controls only 1st ME(0-3 CS pipes). 3083 */ 3084 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3085 if (i != ring->pipe) 3086 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3087 3088 } 3089 } 3090 3091 enum amdgpu_gfx_cp_ras_mem_id { 3092 AMDGPU_GFX_CP_MEM1 = 1, 3093 AMDGPU_GFX_CP_MEM2, 3094 AMDGPU_GFX_CP_MEM3, 3095 AMDGPU_GFX_CP_MEM4, 3096 AMDGPU_GFX_CP_MEM5, 3097 }; 3098 3099 enum amdgpu_gfx_gcea_ras_mem_id { 3100 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3101 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3102 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3103 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3104 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3105 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3106 AMDGPU_GFX_GCEA_MAM_DMEM0, 3107 AMDGPU_GFX_GCEA_MAM_DMEM1, 3108 AMDGPU_GFX_GCEA_MAM_DMEM2, 3109 AMDGPU_GFX_GCEA_MAM_DMEM3, 3110 AMDGPU_GFX_GCEA_MAM_AMEM0, 3111 AMDGPU_GFX_GCEA_MAM_AMEM1, 3112 AMDGPU_GFX_GCEA_MAM_AMEM2, 3113 AMDGPU_GFX_GCEA_MAM_AMEM3, 3114 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3115 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3116 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3117 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3118 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3119 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3120 }; 3121 3122 enum amdgpu_gfx_gc_cane_ras_mem_id { 3123 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3124 }; 3125 3126 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3127 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3128 }; 3129 3130 enum amdgpu_gfx_gds_ras_mem_id { 3131 AMDGPU_GFX_GDS_MEM0 = 0, 3132 }; 3133 3134 enum amdgpu_gfx_lds_ras_mem_id { 3135 AMDGPU_GFX_LDS_BANK0 = 0, 3136 AMDGPU_GFX_LDS_BANK1, 3137 AMDGPU_GFX_LDS_BANK2, 3138 AMDGPU_GFX_LDS_BANK3, 3139 AMDGPU_GFX_LDS_BANK4, 3140 AMDGPU_GFX_LDS_BANK5, 3141 AMDGPU_GFX_LDS_BANK6, 3142 AMDGPU_GFX_LDS_BANK7, 3143 AMDGPU_GFX_LDS_BANK8, 3144 AMDGPU_GFX_LDS_BANK9, 3145 AMDGPU_GFX_LDS_BANK10, 3146 AMDGPU_GFX_LDS_BANK11, 3147 AMDGPU_GFX_LDS_BANK12, 3148 AMDGPU_GFX_LDS_BANK13, 3149 AMDGPU_GFX_LDS_BANK14, 3150 AMDGPU_GFX_LDS_BANK15, 3151 AMDGPU_GFX_LDS_BANK16, 3152 AMDGPU_GFX_LDS_BANK17, 3153 AMDGPU_GFX_LDS_BANK18, 3154 AMDGPU_GFX_LDS_BANK19, 3155 AMDGPU_GFX_LDS_BANK20, 3156 AMDGPU_GFX_LDS_BANK21, 3157 AMDGPU_GFX_LDS_BANK22, 3158 AMDGPU_GFX_LDS_BANK23, 3159 AMDGPU_GFX_LDS_BANK24, 3160 AMDGPU_GFX_LDS_BANK25, 3161 AMDGPU_GFX_LDS_BANK26, 3162 AMDGPU_GFX_LDS_BANK27, 3163 AMDGPU_GFX_LDS_BANK28, 3164 AMDGPU_GFX_LDS_BANK29, 3165 AMDGPU_GFX_LDS_BANK30, 3166 AMDGPU_GFX_LDS_BANK31, 3167 AMDGPU_GFX_LDS_SP_BUFFER_A, 3168 AMDGPU_GFX_LDS_SP_BUFFER_B, 3169 }; 3170 3171 enum amdgpu_gfx_rlc_ras_mem_id { 3172 AMDGPU_GFX_RLC_GPMF32 = 1, 3173 AMDGPU_GFX_RLC_RLCVF32, 3174 AMDGPU_GFX_RLC_SCRATCH, 3175 AMDGPU_GFX_RLC_SRM_ARAM, 3176 AMDGPU_GFX_RLC_SRM_DRAM, 3177 AMDGPU_GFX_RLC_TCTAG, 3178 AMDGPU_GFX_RLC_SPM_SE, 3179 AMDGPU_GFX_RLC_SPM_GRBMT, 3180 }; 3181 3182 enum amdgpu_gfx_sp_ras_mem_id { 3183 AMDGPU_GFX_SP_SIMDID0 = 0, 3184 }; 3185 3186 enum amdgpu_gfx_spi_ras_mem_id { 3187 AMDGPU_GFX_SPI_MEM0 = 0, 3188 AMDGPU_GFX_SPI_MEM1, 3189 AMDGPU_GFX_SPI_MEM2, 3190 AMDGPU_GFX_SPI_MEM3, 3191 }; 3192 3193 enum amdgpu_gfx_sqc_ras_mem_id { 3194 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3195 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3196 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3197 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3198 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3199 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3200 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3201 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3202 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3203 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3204 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3205 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3206 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3207 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3208 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3209 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3210 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3211 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3212 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3213 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3214 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3215 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3216 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3217 }; 3218 3219 enum amdgpu_gfx_sq_ras_mem_id { 3220 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3221 AMDGPU_GFX_SQ_SGPR_MEM1, 3222 AMDGPU_GFX_SQ_SGPR_MEM2, 3223 AMDGPU_GFX_SQ_SGPR_MEM3, 3224 }; 3225 3226 enum amdgpu_gfx_ta_ras_mem_id { 3227 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3228 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3229 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3230 AMDGPU_GFX_TA_FSX_LFIFO, 3231 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3232 }; 3233 3234 enum amdgpu_gfx_tcc_ras_mem_id { 3235 AMDGPU_GFX_TCC_MEM1 = 1, 3236 }; 3237 3238 enum amdgpu_gfx_tca_ras_mem_id { 3239 AMDGPU_GFX_TCA_MEM1 = 1, 3240 }; 3241 3242 enum amdgpu_gfx_tci_ras_mem_id { 3243 AMDGPU_GFX_TCIW_MEM = 1, 3244 }; 3245 3246 enum amdgpu_gfx_tcp_ras_mem_id { 3247 AMDGPU_GFX_TCP_LFIFO0 = 1, 3248 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3249 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3250 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3251 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3252 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3253 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3254 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3255 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3256 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3257 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3258 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3259 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3260 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3261 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3262 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3263 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3264 AMDGPU_GFX_TCP_VM_FIFO, 3265 AMDGPU_GFX_TCP_DB_TAGRAM0, 3266 AMDGPU_GFX_TCP_DB_TAGRAM1, 3267 AMDGPU_GFX_TCP_DB_TAGRAM2, 3268 AMDGPU_GFX_TCP_DB_TAGRAM3, 3269 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3270 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3271 AMDGPU_GFX_TCP_CMD_FIFO, 3272 }; 3273 3274 enum amdgpu_gfx_td_ras_mem_id { 3275 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3276 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3277 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3278 }; 3279 3280 enum amdgpu_gfx_tcx_ras_mem_id { 3281 AMDGPU_GFX_TCX_FIFOD0 = 0, 3282 AMDGPU_GFX_TCX_FIFOD1, 3283 AMDGPU_GFX_TCX_FIFOD2, 3284 AMDGPU_GFX_TCX_FIFOD3, 3285 AMDGPU_GFX_TCX_FIFOD4, 3286 AMDGPU_GFX_TCX_FIFOD5, 3287 AMDGPU_GFX_TCX_FIFOD6, 3288 AMDGPU_GFX_TCX_FIFOD7, 3289 AMDGPU_GFX_TCX_FIFOB0, 3290 AMDGPU_GFX_TCX_FIFOB1, 3291 AMDGPU_GFX_TCX_FIFOB2, 3292 AMDGPU_GFX_TCX_FIFOB3, 3293 AMDGPU_GFX_TCX_FIFOB4, 3294 AMDGPU_GFX_TCX_FIFOB5, 3295 AMDGPU_GFX_TCX_FIFOB6, 3296 AMDGPU_GFX_TCX_FIFOB7, 3297 AMDGPU_GFX_TCX_FIFOA0, 3298 AMDGPU_GFX_TCX_FIFOA1, 3299 AMDGPU_GFX_TCX_FIFOA2, 3300 AMDGPU_GFX_TCX_FIFOA3, 3301 AMDGPU_GFX_TCX_FIFOA4, 3302 AMDGPU_GFX_TCX_FIFOA5, 3303 AMDGPU_GFX_TCX_FIFOA6, 3304 AMDGPU_GFX_TCX_FIFOA7, 3305 AMDGPU_GFX_TCX_CFIFO0, 3306 AMDGPU_GFX_TCX_CFIFO1, 3307 AMDGPU_GFX_TCX_CFIFO2, 3308 AMDGPU_GFX_TCX_CFIFO3, 3309 AMDGPU_GFX_TCX_CFIFO4, 3310 AMDGPU_GFX_TCX_CFIFO5, 3311 AMDGPU_GFX_TCX_CFIFO6, 3312 AMDGPU_GFX_TCX_CFIFO7, 3313 AMDGPU_GFX_TCX_FIFO_ACKB0, 3314 AMDGPU_GFX_TCX_FIFO_ACKB1, 3315 AMDGPU_GFX_TCX_FIFO_ACKB2, 3316 AMDGPU_GFX_TCX_FIFO_ACKB3, 3317 AMDGPU_GFX_TCX_FIFO_ACKB4, 3318 AMDGPU_GFX_TCX_FIFO_ACKB5, 3319 AMDGPU_GFX_TCX_FIFO_ACKB6, 3320 AMDGPU_GFX_TCX_FIFO_ACKB7, 3321 AMDGPU_GFX_TCX_FIFO_ACKD0, 3322 AMDGPU_GFX_TCX_FIFO_ACKD1, 3323 AMDGPU_GFX_TCX_FIFO_ACKD2, 3324 AMDGPU_GFX_TCX_FIFO_ACKD3, 3325 AMDGPU_GFX_TCX_FIFO_ACKD4, 3326 AMDGPU_GFX_TCX_FIFO_ACKD5, 3327 AMDGPU_GFX_TCX_FIFO_ACKD6, 3328 AMDGPU_GFX_TCX_FIFO_ACKD7, 3329 AMDGPU_GFX_TCX_DST_FIFOA0, 3330 AMDGPU_GFX_TCX_DST_FIFOA1, 3331 AMDGPU_GFX_TCX_DST_FIFOA2, 3332 AMDGPU_GFX_TCX_DST_FIFOA3, 3333 AMDGPU_GFX_TCX_DST_FIFOA4, 3334 AMDGPU_GFX_TCX_DST_FIFOA5, 3335 AMDGPU_GFX_TCX_DST_FIFOA6, 3336 AMDGPU_GFX_TCX_DST_FIFOA7, 3337 AMDGPU_GFX_TCX_DST_FIFOB0, 3338 AMDGPU_GFX_TCX_DST_FIFOB1, 3339 AMDGPU_GFX_TCX_DST_FIFOB2, 3340 AMDGPU_GFX_TCX_DST_FIFOB3, 3341 AMDGPU_GFX_TCX_DST_FIFOB4, 3342 AMDGPU_GFX_TCX_DST_FIFOB5, 3343 AMDGPU_GFX_TCX_DST_FIFOB6, 3344 AMDGPU_GFX_TCX_DST_FIFOB7, 3345 AMDGPU_GFX_TCX_DST_FIFOD0, 3346 AMDGPU_GFX_TCX_DST_FIFOD1, 3347 AMDGPU_GFX_TCX_DST_FIFOD2, 3348 AMDGPU_GFX_TCX_DST_FIFOD3, 3349 AMDGPU_GFX_TCX_DST_FIFOD4, 3350 AMDGPU_GFX_TCX_DST_FIFOD5, 3351 AMDGPU_GFX_TCX_DST_FIFOD6, 3352 AMDGPU_GFX_TCX_DST_FIFOD7, 3353 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3354 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3355 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3356 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3357 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3358 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3359 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3360 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3361 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3362 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3363 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3364 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3365 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3366 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3367 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3368 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3369 }; 3370 3371 enum amdgpu_gfx_atc_l2_ras_mem_id { 3372 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3373 }; 3374 3375 enum amdgpu_gfx_utcl2_ras_mem_id { 3376 AMDGPU_GFX_UTCL2_MEM0 = 0, 3377 }; 3378 3379 enum amdgpu_gfx_vml2_ras_mem_id { 3380 AMDGPU_GFX_VML2_MEM0 = 0, 3381 }; 3382 3383 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3384 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3385 }; 3386 3387 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3388 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3389 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3390 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3391 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3392 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3393 }; 3394 3395 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3396 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3397 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3398 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3399 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3400 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3401 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3402 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3403 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3404 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3405 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3406 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3407 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3408 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3409 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3410 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3411 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3412 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3413 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3414 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3415 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3416 }; 3417 3418 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3419 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3420 }; 3421 3422 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3423 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3424 }; 3425 3426 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3427 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3428 }; 3429 3430 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3431 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3432 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3433 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3434 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3435 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3436 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3437 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3438 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3439 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3440 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3441 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3442 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3443 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3444 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3445 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3446 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3447 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3448 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3449 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3450 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3451 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3452 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3453 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3454 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3455 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3456 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3457 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3458 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3459 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3460 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3461 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3462 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3463 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3464 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3465 }; 3466 3467 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3468 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3469 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3470 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3471 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3472 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3473 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3474 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3475 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3476 }; 3477 3478 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3479 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3480 }; 3481 3482 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3483 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3484 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3485 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3486 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3487 }; 3488 3489 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3490 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3491 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3492 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3493 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3494 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3495 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3496 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3497 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3498 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3499 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3500 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3501 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3502 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3503 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3504 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3505 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3506 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3507 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3508 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3509 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3510 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3511 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3512 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3513 }; 3514 3515 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3516 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3517 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3518 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3519 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3520 }; 3521 3522 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3523 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3524 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3525 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3526 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3527 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3528 }; 3529 3530 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3531 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3532 }; 3533 3534 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3535 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3536 }; 3537 3538 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3539 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3540 }; 3541 3542 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3543 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3544 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3545 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3546 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3547 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3548 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3549 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3550 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3551 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3552 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3553 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3554 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3555 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3556 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3557 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3558 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3559 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3560 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3561 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3562 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3563 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3564 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3565 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3566 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3567 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3568 }; 3569 3570 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3571 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3572 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3573 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3574 }; 3575 3576 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3577 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3578 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3579 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3580 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3581 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3582 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3583 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3584 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3585 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3586 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3587 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3588 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3589 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3590 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3591 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3592 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3593 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3594 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3595 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3596 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3597 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3598 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3599 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3600 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3601 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3602 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3603 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3604 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3605 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3606 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3607 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3608 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3609 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3610 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3611 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3612 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3613 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3614 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3615 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3616 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3617 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3618 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3619 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3620 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3621 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3622 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3623 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3624 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3625 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3626 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3627 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3628 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3629 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3630 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3631 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3632 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3633 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3634 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3635 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3636 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3637 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3638 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3639 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3640 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3641 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3642 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3643 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3644 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3645 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3646 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3647 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3648 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3649 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3650 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3651 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3652 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3653 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3654 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3655 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3656 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3657 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3658 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3659 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3660 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3661 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3662 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3663 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3664 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3665 }; 3666 3667 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3668 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3669 }; 3670 3671 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3672 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3673 }; 3674 3675 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3676 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3677 }; 3678 3679 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3680 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3681 }; 3682 3683 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3684 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3685 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3686 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3687 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3688 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3689 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3690 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3691 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3692 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3693 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3694 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3695 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3696 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3697 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3698 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3699 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3700 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3701 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3702 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3703 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3704 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3705 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3706 }; 3707 3708 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3709 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3710 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3711 AMDGPU_GFX_RLC_MEM, 1}, 3712 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3713 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3714 AMDGPU_GFX_CP_MEM, 1}, 3715 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3716 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3717 AMDGPU_GFX_CP_MEM, 1}, 3718 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3719 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3720 AMDGPU_GFX_CP_MEM, 1}, 3721 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3722 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3723 AMDGPU_GFX_GDS_MEM, 1}, 3724 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3725 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3726 AMDGPU_GFX_GC_CANE_MEM, 1}, 3727 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3728 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3729 AMDGPU_GFX_SPI_MEM, 1}, 3730 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3731 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3732 AMDGPU_GFX_SP_MEM, 4}, 3733 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3734 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3735 AMDGPU_GFX_SP_MEM, 4}, 3736 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3737 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3738 AMDGPU_GFX_SQ_MEM, 4}, 3739 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3740 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3741 AMDGPU_GFX_SQC_MEM, 4}, 3742 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3743 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3744 AMDGPU_GFX_TCX_MEM, 1}, 3745 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3746 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3747 AMDGPU_GFX_TCC_MEM, 1}, 3748 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3749 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3750 AMDGPU_GFX_TA_MEM, 4}, 3751 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3752 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3753 AMDGPU_GFX_TCI_MEM, 1}, 3754 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3755 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3756 AMDGPU_GFX_TCP_MEM, 4}, 3757 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3758 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3759 AMDGPU_GFX_TD_MEM, 4}, 3760 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3761 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3762 AMDGPU_GFX_GCEA_MEM, 1}, 3763 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3764 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3765 AMDGPU_GFX_LDS_MEM, 4}, 3766 }; 3767 3768 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3769 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3770 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3771 AMDGPU_GFX_RLC_MEM, 1}, 3772 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3773 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3774 AMDGPU_GFX_CP_MEM, 1}, 3775 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3776 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3777 AMDGPU_GFX_CP_MEM, 1}, 3778 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3779 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3780 AMDGPU_GFX_CP_MEM, 1}, 3781 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3782 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3783 AMDGPU_GFX_GDS_MEM, 1}, 3784 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3785 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3786 AMDGPU_GFX_GC_CANE_MEM, 1}, 3787 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3788 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3789 AMDGPU_GFX_SPI_MEM, 1}, 3790 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3791 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3792 AMDGPU_GFX_SP_MEM, 4}, 3793 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3794 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3795 AMDGPU_GFX_SP_MEM, 4}, 3796 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3797 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3798 AMDGPU_GFX_SQ_MEM, 4}, 3799 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3800 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3801 AMDGPU_GFX_SQC_MEM, 4}, 3802 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3803 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3804 AMDGPU_GFX_TCX_MEM, 1}, 3805 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3806 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3807 AMDGPU_GFX_TCC_MEM, 1}, 3808 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3809 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3810 AMDGPU_GFX_TA_MEM, 4}, 3811 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3812 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3813 AMDGPU_GFX_TCI_MEM, 1}, 3814 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3815 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3816 AMDGPU_GFX_TCP_MEM, 4}, 3817 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3818 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3819 AMDGPU_GFX_TD_MEM, 4}, 3820 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3821 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3822 AMDGPU_GFX_TCA_MEM, 1}, 3823 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3824 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3825 AMDGPU_GFX_GCEA_MEM, 1}, 3826 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3827 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3828 AMDGPU_GFX_LDS_MEM, 4}, 3829 }; 3830 3831 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3832 void *ras_error_status, int xcc_id) 3833 { 3834 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3835 unsigned long ce_count = 0, ue_count = 0; 3836 uint32_t i, j, k; 3837 3838 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 3839 struct amdgpu_smuio_mcm_config_info mcm_info = { 3840 .socket_id = adev->smuio.funcs->get_socket_id(adev), 3841 .die_id = xcc_id & 0x01 ? 1 : 0, 3842 }; 3843 3844 mutex_lock(&adev->grbm_idx_mutex); 3845 3846 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3847 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3848 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3849 /* no need to select if instance number is 1 */ 3850 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3851 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3852 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3853 3854 amdgpu_ras_inst_query_ras_error_count(adev, 3855 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3856 1, 3857 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3858 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3859 GET_INST(GC, xcc_id), 3860 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3861 &ce_count); 3862 3863 amdgpu_ras_inst_query_ras_error_count(adev, 3864 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3865 1, 3866 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3867 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3868 GET_INST(GC, xcc_id), 3869 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3870 &ue_count); 3871 } 3872 } 3873 } 3874 3875 /* handle extra register entries of UE */ 3876 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3877 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3878 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3879 /* no need to select if instance number is 1 */ 3880 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3881 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3882 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3883 3884 amdgpu_ras_inst_query_ras_error_count(adev, 3885 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3886 1, 3887 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3888 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3889 GET_INST(GC, xcc_id), 3890 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3891 &ue_count); 3892 } 3893 } 3894 } 3895 3896 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3897 xcc_id); 3898 mutex_unlock(&adev->grbm_idx_mutex); 3899 3900 /* the caller should make sure initialize value of 3901 * err_data->ue_count and err_data->ce_count 3902 */ 3903 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 3904 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); 3905 } 3906 3907 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3908 void *ras_error_status, int xcc_id) 3909 { 3910 uint32_t i, j, k; 3911 3912 mutex_lock(&adev->grbm_idx_mutex); 3913 3914 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3915 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3916 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3917 /* no need to select if instance number is 1 */ 3918 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3919 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3920 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3921 3922 amdgpu_ras_inst_reset_ras_error_count(adev, 3923 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3924 1, 3925 GET_INST(GC, xcc_id)); 3926 3927 amdgpu_ras_inst_reset_ras_error_count(adev, 3928 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3929 1, 3930 GET_INST(GC, xcc_id)); 3931 } 3932 } 3933 } 3934 3935 /* handle extra register entries of UE */ 3936 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3937 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3938 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3939 /* no need to select if instance number is 1 */ 3940 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3941 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3942 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3943 3944 amdgpu_ras_inst_reset_ras_error_count(adev, 3945 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3946 1, 3947 GET_INST(GC, xcc_id)); 3948 } 3949 } 3950 } 3951 3952 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3953 xcc_id); 3954 mutex_unlock(&adev->grbm_idx_mutex); 3955 } 3956 3957 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3958 void *ras_error_status, int xcc_id) 3959 { 3960 uint32_t i; 3961 uint32_t data; 3962 3963 if (amdgpu_sriov_vf(adev)) 3964 return; 3965 3966 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 3967 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 3968 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 3969 3970 if (amdgpu_watchdog_timer.timeout_fatal_disable && 3971 (amdgpu_watchdog_timer.period < 1 || 3972 amdgpu_watchdog_timer.period > 0x23)) { 3973 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 3974 amdgpu_watchdog_timer.period = 0x23; 3975 } 3976 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 3977 amdgpu_watchdog_timer.period); 3978 3979 mutex_lock(&adev->grbm_idx_mutex); 3980 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3981 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 3982 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 3983 } 3984 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3985 xcc_id); 3986 mutex_unlock(&adev->grbm_idx_mutex); 3987 } 3988 3989 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 3990 void *ras_error_status) 3991 { 3992 amdgpu_gfx_ras_error_func(adev, ras_error_status, 3993 gfx_v9_4_3_inst_query_ras_err_count); 3994 } 3995 3996 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 3997 { 3998 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 3999 } 4000 4001 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4002 { 4003 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4004 } 4005 4006 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4007 .name = "gfx_v9_4_3", 4008 .early_init = gfx_v9_4_3_early_init, 4009 .late_init = gfx_v9_4_3_late_init, 4010 .sw_init = gfx_v9_4_3_sw_init, 4011 .sw_fini = gfx_v9_4_3_sw_fini, 4012 .hw_init = gfx_v9_4_3_hw_init, 4013 .hw_fini = gfx_v9_4_3_hw_fini, 4014 .suspend = gfx_v9_4_3_suspend, 4015 .resume = gfx_v9_4_3_resume, 4016 .is_idle = gfx_v9_4_3_is_idle, 4017 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4018 .soft_reset = gfx_v9_4_3_soft_reset, 4019 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4020 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4021 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4022 .dump_ip_state = NULL, 4023 .print_ip_state = NULL, 4024 }; 4025 4026 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4027 .type = AMDGPU_RING_TYPE_COMPUTE, 4028 .align_mask = 0xff, 4029 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4030 .support_64bit_ptrs = true, 4031 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4032 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4033 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4034 .emit_frame_size = 4035 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4036 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4037 5 + /* hdp invalidate */ 4038 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4039 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4040 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4041 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4042 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4043 7 + /* gfx_v9_4_3_emit_mem_sync */ 4044 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4045 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4046 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4047 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4048 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4049 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4050 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4051 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4052 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4053 .test_ring = gfx_v9_4_3_ring_test_ring, 4054 .test_ib = gfx_v9_4_3_ring_test_ib, 4055 .insert_nop = amdgpu_ring_insert_nop, 4056 .pad_ib = amdgpu_ring_generic_pad_ib, 4057 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4058 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4059 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4060 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4061 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4062 }; 4063 4064 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4065 .type = AMDGPU_RING_TYPE_KIQ, 4066 .align_mask = 0xff, 4067 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4068 .support_64bit_ptrs = true, 4069 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4070 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4071 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4072 .emit_frame_size = 4073 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4074 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4075 5 + /* hdp invalidate */ 4076 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4077 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4078 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4079 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4080 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4081 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4082 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4083 .test_ring = gfx_v9_4_3_ring_test_ring, 4084 .insert_nop = amdgpu_ring_insert_nop, 4085 .pad_ib = amdgpu_ring_generic_pad_ib, 4086 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4087 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4088 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4089 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4090 }; 4091 4092 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4093 { 4094 int i, j, num_xcc; 4095 4096 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4097 for (i = 0; i < num_xcc; i++) { 4098 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4099 4100 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4101 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4102 = &gfx_v9_4_3_ring_funcs_compute; 4103 } 4104 } 4105 4106 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4107 .set = gfx_v9_4_3_set_eop_interrupt_state, 4108 .process = gfx_v9_4_3_eop_irq, 4109 }; 4110 4111 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4112 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4113 .process = gfx_v9_4_3_priv_reg_irq, 4114 }; 4115 4116 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4117 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4118 .process = gfx_v9_4_3_priv_inst_irq, 4119 }; 4120 4121 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4122 { 4123 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4124 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4125 4126 adev->gfx.priv_reg_irq.num_types = 1; 4127 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4128 4129 adev->gfx.priv_inst_irq.num_types = 1; 4130 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4131 } 4132 4133 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4134 { 4135 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4136 } 4137 4138 4139 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4140 { 4141 /* init asci gds info */ 4142 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4143 case IP_VERSION(9, 4, 3): 4144 case IP_VERSION(9, 4, 4): 4145 /* 9.4.3 removed all the GDS internal memory, 4146 * only support GWS opcode in kernel, like barrier 4147 * semaphore.etc */ 4148 adev->gds.gds_size = 0; 4149 break; 4150 default: 4151 adev->gds.gds_size = 0x10000; 4152 break; 4153 } 4154 4155 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4156 case IP_VERSION(9, 4, 3): 4157 case IP_VERSION(9, 4, 4): 4158 /* deprecated for 9.4.3, no usage at all */ 4159 adev->gds.gds_compute_max_wave_id = 0; 4160 break; 4161 default: 4162 /* this really depends on the chip */ 4163 adev->gds.gds_compute_max_wave_id = 0x7ff; 4164 break; 4165 } 4166 4167 adev->gds.gws_size = 64; 4168 adev->gds.oa_size = 16; 4169 } 4170 4171 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4172 u32 bitmap, int xcc_id) 4173 { 4174 u32 data; 4175 4176 if (!bitmap) 4177 return; 4178 4179 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4180 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4181 4182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4183 } 4184 4185 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4186 { 4187 u32 data, mask; 4188 4189 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4190 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4191 4192 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4193 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4194 4195 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4196 4197 return (~data) & mask; 4198 } 4199 4200 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4201 struct amdgpu_cu_info *cu_info) 4202 { 4203 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4204 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4205 unsigned disable_masks[4 * 4]; 4206 bool is_symmetric_cus; 4207 4208 if (!adev || !cu_info) 4209 return -EINVAL; 4210 4211 /* 4212 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4213 */ 4214 if (adev->gfx.config.max_shader_engines * 4215 adev->gfx.config.max_sh_per_se > 16) 4216 return -EINVAL; 4217 4218 amdgpu_gfx_parse_disable_cu(disable_masks, 4219 adev->gfx.config.max_shader_engines, 4220 adev->gfx.config.max_sh_per_se); 4221 4222 mutex_lock(&adev->grbm_idx_mutex); 4223 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4224 is_symmetric_cus = true; 4225 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4226 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4227 mask = 1; 4228 ao_bitmap = 0; 4229 counter = 0; 4230 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4231 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4232 adev, 4233 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4234 xcc_id); 4235 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4236 4237 cu_info->bitmap[xcc_id][i][j] = bitmap; 4238 4239 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4240 if (bitmap & mask) { 4241 if (counter < adev->gfx.config.max_cu_per_sh) 4242 ao_bitmap |= mask; 4243 counter++; 4244 } 4245 mask <<= 1; 4246 } 4247 active_cu_number += counter; 4248 if (i < 2 && j < 2) 4249 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4250 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4251 } 4252 if (i && is_symmetric_cus && prev_counter != counter) 4253 is_symmetric_cus = false; 4254 prev_counter = counter; 4255 } 4256 if (is_symmetric_cus) { 4257 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4258 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4259 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4260 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4261 } 4262 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4263 xcc_id); 4264 } 4265 mutex_unlock(&adev->grbm_idx_mutex); 4266 4267 cu_info->number = active_cu_number; 4268 cu_info->ao_cu_mask = ao_cu_mask; 4269 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4270 4271 return 0; 4272 } 4273 4274 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4275 .type = AMD_IP_BLOCK_TYPE_GFX, 4276 .major = 9, 4277 .minor = 4, 4278 .rev = 3, 4279 .funcs = &gfx_v9_4_3_ip_funcs, 4280 }; 4281 4282 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4283 { 4284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4285 uint32_t tmp_mask; 4286 int i, r; 4287 4288 /* TODO : Initialize golden regs */ 4289 /* gfx_v9_4_3_init_golden_registers(adev); */ 4290 4291 tmp_mask = inst_mask; 4292 for_each_inst(i, tmp_mask) 4293 gfx_v9_4_3_xcc_constants_init(adev, i); 4294 4295 if (!amdgpu_sriov_vf(adev)) { 4296 tmp_mask = inst_mask; 4297 for_each_inst(i, tmp_mask) { 4298 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4299 if (r) 4300 return r; 4301 } 4302 } 4303 4304 tmp_mask = inst_mask; 4305 for_each_inst(i, tmp_mask) { 4306 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4307 if (r) 4308 return r; 4309 } 4310 4311 return 0; 4312 } 4313 4314 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4315 { 4316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4317 int i; 4318 4319 for_each_inst(i, inst_mask) 4320 gfx_v9_4_3_xcc_fini(adev, i); 4321 4322 return 0; 4323 } 4324 4325 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4326 .suspend = &gfx_v9_4_3_xcp_suspend, 4327 .resume = &gfx_v9_4_3_xcp_resume 4328 }; 4329 4330 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4331 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4332 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4333 }; 4334 4335 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4336 { 4337 int r; 4338 4339 r = amdgpu_ras_block_late_init(adev, ras_block); 4340 if (r) 4341 return r; 4342 4343 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4344 &gfx_v9_4_3_aca_info, 4345 NULL); 4346 if (r) 4347 goto late_fini; 4348 4349 return 0; 4350 4351 late_fini: 4352 amdgpu_ras_block_late_fini(adev, ras_block); 4353 4354 return r; 4355 } 4356 4357 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4358 .ras_block = { 4359 .hw_ops = &gfx_v9_4_3_ras_ops, 4360 .ras_late_init = &gfx_v9_4_3_ras_late_init, 4361 }, 4362 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4363 }; 4364