1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 #include "amdgpu_aca.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 47 48 #define GFX9_MEC_HPD_SIZE 4096 49 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 50 51 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 52 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 53 54 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 55 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 56 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 57 58 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 59 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 60 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 61 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 62 63 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 64 (offset & 0xFFFF) 65 66 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 67 68 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 69 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 70 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 71 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 72 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 73 struct amdgpu_cu_info *cu_info); 74 75 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 76 uint64_t queue_mask) 77 { 78 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 79 amdgpu_ring_write(kiq_ring, 80 PACKET3_SET_RESOURCES_VMID_MASK(0) | 81 /* vmid_mask:0* queue_type:0 (KIQ) */ 82 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 83 amdgpu_ring_write(kiq_ring, 84 lower_32_bits(queue_mask)); /* queue mask lo */ 85 amdgpu_ring_write(kiq_ring, 86 upper_32_bits(queue_mask)); /* queue mask hi */ 87 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 88 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 89 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 90 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 91 } 92 93 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 94 struct amdgpu_ring *ring) 95 { 96 struct amdgpu_device *adev = kiq_ring->adev; 97 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 98 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 99 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 100 101 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 102 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 103 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 104 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 105 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 106 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 107 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 108 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 109 /*queue_type: normal compute queue */ 110 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 111 /* alloc format: all_on_one_pipe */ 112 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 113 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 114 /* num_queues: must be 1 */ 115 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 116 amdgpu_ring_write(kiq_ring, 117 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 118 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 119 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 120 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 121 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 122 } 123 124 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 125 struct amdgpu_ring *ring, 126 enum amdgpu_unmap_queues_action action, 127 u64 gpu_addr, u64 seq) 128 { 129 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 130 131 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 132 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 133 PACKET3_UNMAP_QUEUES_ACTION(action) | 134 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 135 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 136 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 137 amdgpu_ring_write(kiq_ring, 138 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 139 140 if (action == PREEMPT_QUEUES_NO_UNMAP) { 141 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 142 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 143 amdgpu_ring_write(kiq_ring, seq); 144 } else { 145 amdgpu_ring_write(kiq_ring, 0); 146 amdgpu_ring_write(kiq_ring, 0); 147 amdgpu_ring_write(kiq_ring, 0); 148 } 149 } 150 151 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 152 struct amdgpu_ring *ring, 153 u64 addr, 154 u64 seq) 155 { 156 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 157 158 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 159 amdgpu_ring_write(kiq_ring, 160 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 161 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 162 PACKET3_QUERY_STATUS_COMMAND(2)); 163 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 164 amdgpu_ring_write(kiq_ring, 165 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 166 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 167 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 168 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 169 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 170 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 171 } 172 173 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 174 uint16_t pasid, uint32_t flush_type, 175 bool all_hub) 176 { 177 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 178 amdgpu_ring_write(kiq_ring, 179 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 180 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 181 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 182 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 183 } 184 185 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 186 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 187 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 188 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 189 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 190 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 191 .set_resources_size = 8, 192 .map_queues_size = 7, 193 .unmap_queues_size = 6, 194 .query_status_size = 7, 195 .invalidate_tlbs_size = 2, 196 }; 197 198 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 199 { 200 int i, num_xcc; 201 202 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 203 for (i = 0; i < num_xcc; i++) 204 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 205 } 206 207 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 208 { 209 int i, num_xcc, dev_inst; 210 211 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 212 for (i = 0; i < num_xcc; i++) { 213 dev_inst = GET_INST(GC, i); 214 215 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 216 GOLDEN_GB_ADDR_CONFIG); 217 /* Golden settings applied by driver for ASIC with rev_id 0 */ 218 if (adev->rev_id == 0) { 219 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 220 REDUCE_FIFO_DEPTH_BY_2, 2); 221 } else { 222 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 223 SPARE, 0x1); 224 } 225 } 226 } 227 228 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 229 { 230 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 231 232 /* If it is an XCC reg, normalize the reg to keep 233 lower 16 bits in local xcc */ 234 235 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 236 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 237 return normalized_reg; 238 else 239 return reg; 240 } 241 242 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 243 bool wc, uint32_t reg, uint32_t val) 244 { 245 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 246 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 247 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 248 WRITE_DATA_DST_SEL(0) | 249 (wc ? WR_CONFIRM : 0)); 250 amdgpu_ring_write(ring, reg); 251 amdgpu_ring_write(ring, 0); 252 amdgpu_ring_write(ring, val); 253 } 254 255 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 256 int mem_space, int opt, uint32_t addr0, 257 uint32_t addr1, uint32_t ref, uint32_t mask, 258 uint32_t inv) 259 { 260 /* Only do the normalization on regspace */ 261 if (mem_space == 0) { 262 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 263 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 264 } 265 266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 267 amdgpu_ring_write(ring, 268 /* memory (1) or register (0) */ 269 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 270 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 271 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 272 WAIT_REG_MEM_ENGINE(eng_sel))); 273 274 if (mem_space) 275 BUG_ON(addr0 & 0x3); /* Dword align */ 276 amdgpu_ring_write(ring, addr0); 277 amdgpu_ring_write(ring, addr1); 278 amdgpu_ring_write(ring, ref); 279 amdgpu_ring_write(ring, mask); 280 amdgpu_ring_write(ring, inv); /* poll interval */ 281 } 282 283 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 284 { 285 uint32_t scratch_reg0_offset, xcc_offset; 286 struct amdgpu_device *adev = ring->adev; 287 uint32_t tmp = 0; 288 unsigned i; 289 int r; 290 291 /* Use register offset which is local to XCC in the packet */ 292 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 293 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 294 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 295 tmp = RREG32(scratch_reg0_offset); 296 297 r = amdgpu_ring_alloc(ring, 3); 298 if (r) 299 return r; 300 301 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 302 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 303 amdgpu_ring_write(ring, 0xDEADBEEF); 304 amdgpu_ring_commit(ring); 305 306 for (i = 0; i < adev->usec_timeout; i++) { 307 tmp = RREG32(scratch_reg0_offset); 308 if (tmp == 0xDEADBEEF) 309 break; 310 udelay(1); 311 } 312 313 if (i >= adev->usec_timeout) 314 r = -ETIMEDOUT; 315 return r; 316 } 317 318 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 319 { 320 struct amdgpu_device *adev = ring->adev; 321 struct amdgpu_ib ib; 322 struct dma_fence *f = NULL; 323 324 unsigned index; 325 uint64_t gpu_addr; 326 uint32_t tmp; 327 long r; 328 329 r = amdgpu_device_wb_get(adev, &index); 330 if (r) 331 return r; 332 333 gpu_addr = adev->wb.gpu_addr + (index * 4); 334 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 335 memset(&ib, 0, sizeof(ib)); 336 337 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 338 if (r) 339 goto err1; 340 341 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 342 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 343 ib.ptr[2] = lower_32_bits(gpu_addr); 344 ib.ptr[3] = upper_32_bits(gpu_addr); 345 ib.ptr[4] = 0xDEADBEEF; 346 ib.length_dw = 5; 347 348 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 349 if (r) 350 goto err2; 351 352 r = dma_fence_wait_timeout(f, false, timeout); 353 if (r == 0) { 354 r = -ETIMEDOUT; 355 goto err2; 356 } else if (r < 0) { 357 goto err2; 358 } 359 360 tmp = adev->wb.wb[index]; 361 if (tmp == 0xDEADBEEF) 362 r = 0; 363 else 364 r = -EINVAL; 365 366 err2: 367 amdgpu_ib_free(adev, &ib, NULL); 368 dma_fence_put(f); 369 err1: 370 amdgpu_device_wb_free(adev, index); 371 return r; 372 } 373 374 375 /* This value might differs per partition */ 376 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 377 { 378 uint64_t clock; 379 380 mutex_lock(&adev->gfx.gpu_clock_mutex); 381 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 382 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 383 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 384 mutex_unlock(&adev->gfx.gpu_clock_mutex); 385 386 return clock; 387 } 388 389 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 390 { 391 amdgpu_ucode_release(&adev->gfx.pfp_fw); 392 amdgpu_ucode_release(&adev->gfx.me_fw); 393 amdgpu_ucode_release(&adev->gfx.ce_fw); 394 amdgpu_ucode_release(&adev->gfx.rlc_fw); 395 amdgpu_ucode_release(&adev->gfx.mec_fw); 396 amdgpu_ucode_release(&adev->gfx.mec2_fw); 397 398 kfree(adev->gfx.rlc.register_list_format); 399 } 400 401 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 402 const char *chip_name) 403 { 404 int err; 405 const struct rlc_firmware_header_v2_0 *rlc_hdr; 406 uint16_t version_major; 407 uint16_t version_minor; 408 409 410 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 411 "amdgpu/%s_rlc.bin", chip_name); 412 if (err) 413 goto out; 414 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 415 416 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 417 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 418 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 419 out: 420 if (err) 421 amdgpu_ucode_release(&adev->gfx.rlc_fw); 422 423 return err; 424 } 425 426 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 427 { 428 return true; 429 } 430 431 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 432 { 433 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 434 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 435 } 436 437 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 438 const char *chip_name) 439 { 440 int err; 441 442 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 443 "amdgpu/%s_mec.bin", chip_name); 444 if (err) 445 goto out; 446 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 447 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 448 449 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 450 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 451 452 gfx_v9_4_3_check_if_need_gfxoff(adev); 453 454 out: 455 if (err) 456 amdgpu_ucode_release(&adev->gfx.mec_fw); 457 return err; 458 } 459 460 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 461 { 462 char ucode_prefix[15]; 463 int r; 464 465 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 466 467 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 468 if (r) 469 return r; 470 471 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 472 if (r) 473 return r; 474 475 return r; 476 } 477 478 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 479 { 480 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 481 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 482 } 483 484 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 485 { 486 int r, i, num_xcc; 487 u32 *hpd; 488 const __le32 *fw_data; 489 unsigned fw_size; 490 u32 *fw; 491 size_t mec_hpd_size; 492 493 const struct gfx_firmware_header_v1_0 *mec_hdr; 494 495 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 496 for (i = 0; i < num_xcc; i++) 497 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 498 AMDGPU_MAX_COMPUTE_QUEUES); 499 500 /* take ownership of the relevant compute queues */ 501 amdgpu_gfx_compute_queue_acquire(adev); 502 mec_hpd_size = 503 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 504 if (mec_hpd_size) { 505 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 506 AMDGPU_GEM_DOMAIN_VRAM | 507 AMDGPU_GEM_DOMAIN_GTT, 508 &adev->gfx.mec.hpd_eop_obj, 509 &adev->gfx.mec.hpd_eop_gpu_addr, 510 (void **)&hpd); 511 if (r) { 512 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 513 gfx_v9_4_3_mec_fini(adev); 514 return r; 515 } 516 517 if (amdgpu_emu_mode == 1) { 518 for (i = 0; i < mec_hpd_size / 4; i++) { 519 memset((void *)(hpd + i), 0, 4); 520 if (i % 50 == 0) 521 msleep(1); 522 } 523 } else { 524 memset(hpd, 0, mec_hpd_size); 525 } 526 527 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 528 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 529 } 530 531 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 532 533 fw_data = (const __le32 *) 534 (adev->gfx.mec_fw->data + 535 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 536 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 537 538 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 540 &adev->gfx.mec.mec_fw_obj, 541 &adev->gfx.mec.mec_fw_gpu_addr, 542 (void **)&fw); 543 if (r) { 544 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 545 gfx_v9_4_3_mec_fini(adev); 546 return r; 547 } 548 549 memcpy(fw, fw_data, fw_size); 550 551 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 552 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 553 554 return 0; 555 } 556 557 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 558 u32 sh_num, u32 instance, int xcc_id) 559 { 560 u32 data; 561 562 if (instance == 0xffffffff) 563 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 564 INSTANCE_BROADCAST_WRITES, 1); 565 else 566 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 567 INSTANCE_INDEX, instance); 568 569 if (se_num == 0xffffffff) 570 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 571 SE_BROADCAST_WRITES, 1); 572 else 573 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 574 575 if (sh_num == 0xffffffff) 576 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 577 SH_BROADCAST_WRITES, 1); 578 else 579 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 580 581 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 582 } 583 584 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 585 { 586 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 587 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 588 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 589 (address << SQ_IND_INDEX__INDEX__SHIFT) | 590 (SQ_IND_INDEX__FORCE_READ_MASK)); 591 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 592 } 593 594 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 595 uint32_t wave, uint32_t thread, 596 uint32_t regno, uint32_t num, uint32_t *out) 597 { 598 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 599 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 600 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 601 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 602 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 603 (SQ_IND_INDEX__FORCE_READ_MASK) | 604 (SQ_IND_INDEX__AUTO_INCR_MASK)); 605 while (num--) 606 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 607 } 608 609 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 610 uint32_t xcc_id, uint32_t simd, uint32_t wave, 611 uint32_t *dst, int *no_fields) 612 { 613 /* type 1 wave data */ 614 dst[(*no_fields)++] = 1; 615 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 616 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 617 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 618 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 619 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 620 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 621 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 622 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 623 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 624 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 625 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 626 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 627 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 628 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 629 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 630 } 631 632 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 633 uint32_t wave, uint32_t start, 634 uint32_t size, uint32_t *dst) 635 { 636 wave_read_regs(adev, xcc_id, simd, wave, 0, 637 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 638 } 639 640 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 641 uint32_t wave, uint32_t thread, 642 uint32_t start, uint32_t size, 643 uint32_t *dst) 644 { 645 wave_read_regs(adev, xcc_id, simd, wave, thread, 646 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 647 } 648 649 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 650 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 651 { 652 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 653 } 654 655 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 656 { 657 u32 xcp_ctl; 658 659 /* Value is expected to be the same on all, fetch from first instance */ 660 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 661 662 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 663 } 664 665 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 666 int num_xccs_per_xcp) 667 { 668 int ret, i, num_xcc; 669 u32 tmp = 0; 670 671 if (adev->psp.funcs) { 672 ret = psp_spatial_partition(&adev->psp, 673 NUM_XCC(adev->gfx.xcc_mask) / 674 num_xccs_per_xcp); 675 if (ret) 676 return ret; 677 } else { 678 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 679 680 for (i = 0; i < num_xcc; i++) { 681 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 682 num_xccs_per_xcp); 683 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 684 i % num_xccs_per_xcp); 685 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 686 tmp); 687 } 688 ret = 0; 689 } 690 691 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 692 693 return ret; 694 } 695 696 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 697 { 698 int xcc; 699 700 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 701 if (!xcc) { 702 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 703 return -EINVAL; 704 } 705 706 return xcc - 1; 707 } 708 709 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 710 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 711 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 712 .read_wave_data = &gfx_v9_4_3_read_wave_data, 713 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 714 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 715 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 716 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 717 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 718 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 719 }; 720 721 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 722 struct aca_bank *bank, enum aca_smu_type type, 723 void *data) 724 { 725 struct aca_bank_info info; 726 u64 misc0; 727 u32 instlo; 728 int ret; 729 730 ret = aca_bank_info_decode(bank, &info); 731 if (ret) 732 return ret; 733 734 /* NOTE: overwrite info.die_id with xcd id for gfx */ 735 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 736 instlo &= GENMASK(31, 1); 737 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 738 739 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 740 741 switch (type) { 742 case ACA_SMU_TYPE_UE: 743 ret = aca_error_cache_log_bank_error(handle, &info, 744 ACA_ERROR_TYPE_UE, 1ULL); 745 break; 746 case ACA_SMU_TYPE_CE: 747 ret = aca_error_cache_log_bank_error(handle, &info, 748 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 return ret; 755 } 756 757 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 758 enum aca_smu_type type, void *data) 759 { 760 u32 instlo; 761 762 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 763 instlo &= GENMASK(31, 1); 764 switch (instlo) { 765 case mmSMNAID_XCD0_MCA_SMU: 766 case mmSMNAID_XCD1_MCA_SMU: 767 case mmSMNXCD_XCD0_MCA_SMU: 768 return true; 769 default: 770 break; 771 } 772 773 return false; 774 } 775 776 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 777 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 778 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 779 }; 780 781 static const struct aca_info gfx_v9_4_3_aca_info = { 782 .hwip = ACA_HWIP_TYPE_SMU, 783 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 784 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 785 }; 786 787 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 788 { 789 u32 gb_addr_config; 790 791 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 792 adev->gfx.ras = &gfx_v9_4_3_ras; 793 794 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 795 case IP_VERSION(9, 4, 3): 796 case IP_VERSION(9, 4, 4): 797 adev->gfx.config.max_hw_contexts = 8; 798 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 799 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 800 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 801 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 802 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 803 break; 804 default: 805 BUG(); 806 break; 807 } 808 809 adev->gfx.config.gb_addr_config = gb_addr_config; 810 811 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 812 REG_GET_FIELD( 813 adev->gfx.config.gb_addr_config, 814 GB_ADDR_CONFIG, 815 NUM_PIPES); 816 817 adev->gfx.config.max_tile_pipes = 818 adev->gfx.config.gb_addr_config_fields.num_pipes; 819 820 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 821 REG_GET_FIELD( 822 adev->gfx.config.gb_addr_config, 823 GB_ADDR_CONFIG, 824 NUM_BANKS); 825 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 826 REG_GET_FIELD( 827 adev->gfx.config.gb_addr_config, 828 GB_ADDR_CONFIG, 829 MAX_COMPRESSED_FRAGS); 830 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 831 REG_GET_FIELD( 832 adev->gfx.config.gb_addr_config, 833 GB_ADDR_CONFIG, 834 NUM_RB_PER_SE); 835 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 836 REG_GET_FIELD( 837 adev->gfx.config.gb_addr_config, 838 GB_ADDR_CONFIG, 839 NUM_SHADER_ENGINES); 840 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 841 REG_GET_FIELD( 842 adev->gfx.config.gb_addr_config, 843 GB_ADDR_CONFIG, 844 PIPE_INTERLEAVE_SIZE)); 845 846 return 0; 847 } 848 849 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 850 int xcc_id, int mec, int pipe, int queue) 851 { 852 unsigned irq_type; 853 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 854 unsigned int hw_prio; 855 uint32_t xcc_doorbell_start; 856 857 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 858 ring_id]; 859 860 /* mec0 is me1 */ 861 ring->xcc_id = xcc_id; 862 ring->me = mec + 1; 863 ring->pipe = pipe; 864 ring->queue = queue; 865 866 ring->ring_obj = NULL; 867 ring->use_doorbell = true; 868 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 869 xcc_id * adev->doorbell_index.xcc_doorbell_range; 870 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 871 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 872 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 873 GFX9_MEC_HPD_SIZE; 874 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 875 sprintf(ring->name, "comp_%d.%d.%d.%d", 876 ring->xcc_id, ring->me, ring->pipe, ring->queue); 877 878 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 879 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 880 + ring->pipe; 881 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 882 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 883 /* type-2 packets are deprecated on MEC, use type-3 instead */ 884 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 885 hw_prio, NULL); 886 } 887 888 static int gfx_v9_4_3_sw_init(void *handle) 889 { 890 int i, j, k, r, ring_id, xcc_id, num_xcc; 891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 892 893 adev->gfx.mec.num_mec = 2; 894 adev->gfx.mec.num_pipe_per_mec = 4; 895 adev->gfx.mec.num_queue_per_pipe = 8; 896 897 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 898 899 /* EOP Event */ 900 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 901 if (r) 902 return r; 903 904 /* Bad opcode Event */ 905 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 906 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 907 &adev->gfx.bad_op_irq); 908 if (r) 909 return r; 910 911 /* Privileged reg */ 912 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 913 &adev->gfx.priv_reg_irq); 914 if (r) 915 return r; 916 917 /* Privileged inst */ 918 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 919 &adev->gfx.priv_inst_irq); 920 if (r) 921 return r; 922 923 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 924 925 r = adev->gfx.rlc.funcs->init(adev); 926 if (r) { 927 DRM_ERROR("Failed to init rlc BOs!\n"); 928 return r; 929 } 930 931 r = gfx_v9_4_3_mec_init(adev); 932 if (r) { 933 DRM_ERROR("Failed to init MEC BOs!\n"); 934 return r; 935 } 936 937 /* set up the compute queues - allocate horizontally across pipes */ 938 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 939 ring_id = 0; 940 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 941 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 942 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 943 k++) { 944 if (!amdgpu_gfx_is_mec_queue_enabled( 945 adev, xcc_id, i, k, j)) 946 continue; 947 948 r = gfx_v9_4_3_compute_ring_init(adev, 949 ring_id, 950 xcc_id, 951 i, k, j); 952 if (r) 953 return r; 954 955 ring_id++; 956 } 957 } 958 } 959 960 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 961 if (r) { 962 DRM_ERROR("Failed to init KIQ BOs!\n"); 963 return r; 964 } 965 966 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 967 if (r) 968 return r; 969 970 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 971 r = amdgpu_gfx_mqd_sw_init(adev, 972 sizeof(struct v9_mqd_allocation), xcc_id); 973 if (r) 974 return r; 975 } 976 977 r = gfx_v9_4_3_gpu_early_init(adev); 978 if (r) 979 return r; 980 981 r = amdgpu_gfx_ras_sw_init(adev); 982 if (r) 983 return r; 984 985 986 if (!amdgpu_sriov_vf(adev)) 987 r = amdgpu_gfx_sysfs_init(adev); 988 989 return r; 990 } 991 992 static int gfx_v9_4_3_sw_fini(void *handle) 993 { 994 int i, num_xcc; 995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 996 997 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 998 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 999 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1000 1001 for (i = 0; i < num_xcc; i++) { 1002 amdgpu_gfx_mqd_sw_fini(adev, i); 1003 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1004 amdgpu_gfx_kiq_fini(adev, i); 1005 } 1006 1007 gfx_v9_4_3_mec_fini(adev); 1008 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1009 gfx_v9_4_3_free_microcode(adev); 1010 if (!amdgpu_sriov_vf(adev)) 1011 amdgpu_gfx_sysfs_fini(adev); 1012 1013 return 0; 1014 } 1015 1016 #define DEFAULT_SH_MEM_BASES (0x6000) 1017 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1018 int xcc_id) 1019 { 1020 int i; 1021 uint32_t sh_mem_config; 1022 uint32_t sh_mem_bases; 1023 uint32_t data; 1024 1025 /* 1026 * Configure apertures: 1027 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1028 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1029 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1030 */ 1031 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1032 1033 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1034 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1035 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1036 1037 mutex_lock(&adev->srbm_mutex); 1038 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1039 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1040 /* CP and shaders */ 1041 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1042 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1043 1044 /* Enable trap for each kfd vmid. */ 1045 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1046 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1047 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1048 } 1049 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1050 mutex_unlock(&adev->srbm_mutex); 1051 1052 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1053 acccess. These should be enabled by FW for target VMIDs. */ 1054 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1055 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1056 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1057 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1058 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1059 } 1060 } 1061 1062 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1063 { 1064 int vmid; 1065 1066 /* 1067 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1068 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1069 * the driver can enable them for graphics. VMID0 should maintain 1070 * access so that HWS firmware can save/restore entries. 1071 */ 1072 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1073 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1074 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1075 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1076 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1077 } 1078 } 1079 1080 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1081 int xcc_id) 1082 { 1083 u32 tmp; 1084 int i; 1085 1086 /* XXX SH_MEM regs */ 1087 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1088 mutex_lock(&adev->srbm_mutex); 1089 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1090 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1091 /* CP and shaders */ 1092 if (i == 0) { 1093 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1094 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1095 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1096 !!adev->gmc.noretry); 1097 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1098 regSH_MEM_CONFIG, tmp); 1099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1100 regSH_MEM_BASES, 0); 1101 } else { 1102 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1103 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1104 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1105 !!adev->gmc.noretry); 1106 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1107 regSH_MEM_CONFIG, tmp); 1108 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1109 (adev->gmc.private_aperture_start >> 1110 48)); 1111 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1112 (adev->gmc.shared_aperture_start >> 1113 48)); 1114 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1115 regSH_MEM_BASES, tmp); 1116 } 1117 } 1118 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1119 1120 mutex_unlock(&adev->srbm_mutex); 1121 1122 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1123 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1124 } 1125 1126 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1127 { 1128 int i, num_xcc; 1129 1130 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1131 1132 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1133 adev->gfx.config.db_debug2 = 1134 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1135 1136 for (i = 0; i < num_xcc; i++) 1137 gfx_v9_4_3_xcc_constants_init(adev, i); 1138 } 1139 1140 static void 1141 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1142 int xcc_id) 1143 { 1144 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1145 } 1146 1147 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1148 { 1149 /* 1150 * Rlc save restore list is workable since v2_1. 1151 * And it's needed by gfxoff feature. 1152 */ 1153 if (adev->gfx.rlc.is_rlc_v2_1) 1154 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1155 } 1156 1157 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1158 { 1159 uint32_t data; 1160 1161 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1162 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1163 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1164 } 1165 1166 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1167 { 1168 uint32_t rlc_setting; 1169 1170 /* if RLC is not enabled, do nothing */ 1171 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1172 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1173 return false; 1174 1175 return true; 1176 } 1177 1178 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1179 { 1180 uint32_t data; 1181 unsigned i; 1182 1183 data = RLC_SAFE_MODE__CMD_MASK; 1184 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1185 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1186 1187 /* wait for RLC_SAFE_MODE */ 1188 for (i = 0; i < adev->usec_timeout; i++) { 1189 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1190 break; 1191 udelay(1); 1192 } 1193 } 1194 1195 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1196 int xcc_id) 1197 { 1198 uint32_t data; 1199 1200 data = RLC_SAFE_MODE__CMD_MASK; 1201 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1202 } 1203 1204 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1205 { 1206 int xcc_id, num_xcc; 1207 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1208 1209 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1210 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1211 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1212 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1213 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1214 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1215 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1216 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1217 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1218 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1219 } 1220 adev->gfx.rlc.rlcg_reg_access_supported = true; 1221 } 1222 1223 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1224 { 1225 /* init spm vmid with 0xf */ 1226 if (adev->gfx.rlc.funcs->update_spm_vmid) 1227 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1228 1229 return 0; 1230 } 1231 1232 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1233 int xcc_id) 1234 { 1235 u32 i, j, k; 1236 u32 mask; 1237 1238 mutex_lock(&adev->grbm_idx_mutex); 1239 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1240 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1241 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1242 xcc_id); 1243 for (k = 0; k < adev->usec_timeout; k++) { 1244 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1245 break; 1246 udelay(1); 1247 } 1248 if (k == adev->usec_timeout) { 1249 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1250 0xffffffff, 1251 0xffffffff, xcc_id); 1252 mutex_unlock(&adev->grbm_idx_mutex); 1253 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1254 i, j); 1255 return; 1256 } 1257 } 1258 } 1259 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1260 xcc_id); 1261 mutex_unlock(&adev->grbm_idx_mutex); 1262 1263 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1264 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1265 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1266 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1267 for (k = 0; k < adev->usec_timeout; k++) { 1268 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1269 break; 1270 udelay(1); 1271 } 1272 } 1273 1274 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1275 bool enable, int xcc_id) 1276 { 1277 u32 tmp; 1278 1279 /* These interrupts should be enabled to drive DS clock */ 1280 1281 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1282 1283 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1284 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1285 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1286 1287 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1288 } 1289 1290 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1291 { 1292 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1293 RLC_ENABLE_F32, 0); 1294 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1295 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1296 } 1297 1298 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1299 { 1300 int i, num_xcc; 1301 1302 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1303 for (i = 0; i < num_xcc; i++) 1304 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1305 } 1306 1307 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1308 { 1309 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1310 SOFT_RESET_RLC, 1); 1311 udelay(50); 1312 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1313 SOFT_RESET_RLC, 0); 1314 udelay(50); 1315 } 1316 1317 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1318 { 1319 int i, num_xcc; 1320 1321 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1322 for (i = 0; i < num_xcc; i++) 1323 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1324 } 1325 1326 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1327 { 1328 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1329 RLC_ENABLE_F32, 1); 1330 udelay(50); 1331 1332 /* carrizo do enable cp interrupt after cp inited */ 1333 if (!(adev->flags & AMD_IS_APU)) { 1334 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1335 udelay(50); 1336 } 1337 } 1338 1339 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1340 { 1341 #ifdef AMDGPU_RLC_DEBUG_RETRY 1342 u32 rlc_ucode_ver; 1343 #endif 1344 int i, num_xcc; 1345 1346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1347 for (i = 0; i < num_xcc; i++) { 1348 gfx_v9_4_3_xcc_rlc_start(adev, i); 1349 #ifdef AMDGPU_RLC_DEBUG_RETRY 1350 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1351 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1352 if (rlc_ucode_ver == 0x108) { 1353 dev_info(adev->dev, 1354 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1355 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1356 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1357 * default is 0x9C4 to create a 100us interval */ 1358 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1359 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1360 * to disable the page fault retry interrupts, default is 1361 * 0x100 (256) */ 1362 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1363 } 1364 #endif 1365 } 1366 } 1367 1368 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1369 int xcc_id) 1370 { 1371 const struct rlc_firmware_header_v2_0 *hdr; 1372 const __le32 *fw_data; 1373 unsigned i, fw_size; 1374 1375 if (!adev->gfx.rlc_fw) 1376 return -EINVAL; 1377 1378 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1379 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1380 1381 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1382 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1383 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1384 1385 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1386 RLCG_UCODE_LOADING_START_ADDRESS); 1387 for (i = 0; i < fw_size; i++) { 1388 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1389 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1390 msleep(1); 1391 } 1392 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1393 } 1394 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1395 1396 return 0; 1397 } 1398 1399 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1400 { 1401 int r; 1402 1403 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1404 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1405 /* legacy rlc firmware loading */ 1406 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1407 if (r) 1408 return r; 1409 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1410 } 1411 1412 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1413 /* disable CG */ 1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1415 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1416 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1417 1418 return 0; 1419 } 1420 1421 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1422 { 1423 int r, i, num_xcc; 1424 1425 if (amdgpu_sriov_vf(adev)) 1426 return 0; 1427 1428 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1429 for (i = 0; i < num_xcc; i++) { 1430 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1431 if (r) 1432 return r; 1433 } 1434 1435 return 0; 1436 } 1437 1438 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1439 unsigned vmid) 1440 { 1441 u32 reg, pre_data, data; 1442 1443 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1444 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1445 pre_data = RREG32_NO_KIQ(reg); 1446 else 1447 pre_data = RREG32(reg); 1448 1449 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1450 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1451 1452 if (pre_data != data) { 1453 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1454 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1455 } else 1456 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1457 } 1458 } 1459 1460 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1461 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1462 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1463 }; 1464 1465 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1466 uint32_t offset, 1467 struct soc15_reg_rlcg *entries, int arr_size) 1468 { 1469 int i, inst; 1470 uint32_t reg; 1471 1472 if (!entries) 1473 return false; 1474 1475 for (i = 0; i < arr_size; i++) { 1476 const struct soc15_reg_rlcg *entry; 1477 1478 entry = &entries[i]; 1479 inst = adev->ip_map.logical_to_dev_inst ? 1480 adev->ip_map.logical_to_dev_inst( 1481 adev, entry->hwip, entry->instance) : 1482 entry->instance; 1483 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1484 entry->reg; 1485 if (offset == reg) 1486 return true; 1487 } 1488 1489 return false; 1490 } 1491 1492 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1493 { 1494 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1495 (void *)rlcg_access_gc_9_4_3, 1496 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1497 } 1498 1499 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1500 bool enable, int xcc_id) 1501 { 1502 if (enable) { 1503 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1504 } else { 1505 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1506 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1507 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1508 } 1509 udelay(50); 1510 } 1511 1512 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1513 int xcc_id) 1514 { 1515 const struct gfx_firmware_header_v1_0 *mec_hdr; 1516 const __le32 *fw_data; 1517 unsigned i; 1518 u32 tmp; 1519 u32 mec_ucode_addr_offset; 1520 u32 mec_ucode_data_offset; 1521 1522 if (!adev->gfx.mec_fw) 1523 return -EINVAL; 1524 1525 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1526 1527 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1528 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1529 1530 fw_data = (const __le32 *) 1531 (adev->gfx.mec_fw->data + 1532 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1533 tmp = 0; 1534 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1535 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1536 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1537 1538 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1539 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1540 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1541 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1542 1543 mec_ucode_addr_offset = 1544 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1545 mec_ucode_data_offset = 1546 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1547 1548 /* MEC1 */ 1549 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1550 for (i = 0; i < mec_hdr->jt_size; i++) 1551 WREG32(mec_ucode_data_offset, 1552 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1553 1554 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1555 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1556 1557 return 0; 1558 } 1559 1560 /* KIQ functions */ 1561 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1562 { 1563 uint32_t tmp; 1564 struct amdgpu_device *adev = ring->adev; 1565 1566 /* tell RLC which is KIQ queue */ 1567 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1568 tmp &= 0xffffff00; 1569 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1570 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1571 tmp |= 0x80; 1572 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1573 } 1574 1575 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1576 { 1577 struct amdgpu_device *adev = ring->adev; 1578 1579 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1580 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1581 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1582 mqd->cp_hqd_queue_priority = 1583 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1584 } 1585 } 1586 } 1587 1588 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1589 { 1590 struct amdgpu_device *adev = ring->adev; 1591 struct v9_mqd *mqd = ring->mqd_ptr; 1592 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1593 uint32_t tmp; 1594 1595 mqd->header = 0xC0310800; 1596 mqd->compute_pipelinestat_enable = 0x00000001; 1597 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1598 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1599 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1600 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1601 mqd->compute_misc_reserved = 0x00000003; 1602 1603 mqd->dynamic_cu_mask_addr_lo = 1604 lower_32_bits(ring->mqd_gpu_addr 1605 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1606 mqd->dynamic_cu_mask_addr_hi = 1607 upper_32_bits(ring->mqd_gpu_addr 1608 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1609 1610 eop_base_addr = ring->eop_gpu_addr >> 8; 1611 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1612 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1613 1614 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1615 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1616 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1617 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1618 1619 mqd->cp_hqd_eop_control = tmp; 1620 1621 /* enable doorbell? */ 1622 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1623 1624 if (ring->use_doorbell) { 1625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1626 DOORBELL_OFFSET, ring->doorbell_index); 1627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1628 DOORBELL_EN, 1); 1629 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1630 DOORBELL_SOURCE, 0); 1631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1632 DOORBELL_HIT, 0); 1633 if (amdgpu_sriov_vf(adev)) 1634 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1635 DOORBELL_MODE, 1); 1636 } else { 1637 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1638 DOORBELL_EN, 0); 1639 } 1640 1641 mqd->cp_hqd_pq_doorbell_control = tmp; 1642 1643 /* disable the queue if it's active */ 1644 ring->wptr = 0; 1645 mqd->cp_hqd_dequeue_request = 0; 1646 mqd->cp_hqd_pq_rptr = 0; 1647 mqd->cp_hqd_pq_wptr_lo = 0; 1648 mqd->cp_hqd_pq_wptr_hi = 0; 1649 1650 /* set the pointer to the MQD */ 1651 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1652 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1653 1654 /* set MQD vmid to 0 */ 1655 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1656 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1657 mqd->cp_mqd_control = tmp; 1658 1659 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1660 hqd_gpu_addr = ring->gpu_addr >> 8; 1661 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1662 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1663 1664 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1665 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1667 (order_base_2(ring->ring_size / 4) - 1)); 1668 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1669 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1670 #ifdef __BIG_ENDIAN 1671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1672 #endif 1673 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1674 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1675 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1676 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1677 mqd->cp_hqd_pq_control = tmp; 1678 1679 /* set the wb address whether it's enabled or not */ 1680 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1681 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1682 mqd->cp_hqd_pq_rptr_report_addr_hi = 1683 upper_32_bits(wb_gpu_addr) & 0xffff; 1684 1685 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1686 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1687 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1688 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1689 1690 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1691 ring->wptr = 0; 1692 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1693 1694 /* set the vmid for the queue */ 1695 mqd->cp_hqd_vmid = 0; 1696 1697 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1698 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1699 mqd->cp_hqd_persistent_state = tmp; 1700 1701 /* set MIN_IB_AVAIL_SIZE */ 1702 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1703 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1704 mqd->cp_hqd_ib_control = tmp; 1705 1706 /* set static priority for a queue/ring */ 1707 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1708 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1709 1710 /* map_queues packet doesn't need activate the queue, 1711 * so only kiq need set this field. 1712 */ 1713 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1714 mqd->cp_hqd_active = 1; 1715 1716 return 0; 1717 } 1718 1719 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1720 int xcc_id) 1721 { 1722 struct amdgpu_device *adev = ring->adev; 1723 struct v9_mqd *mqd = ring->mqd_ptr; 1724 int j; 1725 1726 /* disable wptr polling */ 1727 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1728 1729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1730 mqd->cp_hqd_eop_base_addr_lo); 1731 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1732 mqd->cp_hqd_eop_base_addr_hi); 1733 1734 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1736 mqd->cp_hqd_eop_control); 1737 1738 /* enable doorbell? */ 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1740 mqd->cp_hqd_pq_doorbell_control); 1741 1742 /* disable the queue if it's active */ 1743 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1745 for (j = 0; j < adev->usec_timeout; j++) { 1746 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1747 break; 1748 udelay(1); 1749 } 1750 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1751 mqd->cp_hqd_dequeue_request); 1752 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1753 mqd->cp_hqd_pq_rptr); 1754 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1755 mqd->cp_hqd_pq_wptr_lo); 1756 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1757 mqd->cp_hqd_pq_wptr_hi); 1758 } 1759 1760 /* set the pointer to the MQD */ 1761 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1762 mqd->cp_mqd_base_addr_lo); 1763 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1764 mqd->cp_mqd_base_addr_hi); 1765 1766 /* set MQD vmid to 0 */ 1767 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1768 mqd->cp_mqd_control); 1769 1770 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1771 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1772 mqd->cp_hqd_pq_base_lo); 1773 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1774 mqd->cp_hqd_pq_base_hi); 1775 1776 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1777 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1778 mqd->cp_hqd_pq_control); 1779 1780 /* set the wb address whether it's enabled or not */ 1781 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1782 mqd->cp_hqd_pq_rptr_report_addr_lo); 1783 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1784 mqd->cp_hqd_pq_rptr_report_addr_hi); 1785 1786 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1787 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1788 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1789 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1790 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1791 1792 /* enable the doorbell if requested */ 1793 if (ring->use_doorbell) { 1794 WREG32_SOC15( 1795 GC, GET_INST(GC, xcc_id), 1796 regCP_MEC_DOORBELL_RANGE_LOWER, 1797 ((adev->doorbell_index.kiq + 1798 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1799 2) << 2); 1800 WREG32_SOC15( 1801 GC, GET_INST(GC, xcc_id), 1802 regCP_MEC_DOORBELL_RANGE_UPPER, 1803 ((adev->doorbell_index.userqueue_end + 1804 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1805 2) << 2); 1806 } 1807 1808 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1809 mqd->cp_hqd_pq_doorbell_control); 1810 1811 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1812 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1813 mqd->cp_hqd_pq_wptr_lo); 1814 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1815 mqd->cp_hqd_pq_wptr_hi); 1816 1817 /* set the vmid for the queue */ 1818 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1819 1820 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1821 mqd->cp_hqd_persistent_state); 1822 1823 /* activate the queue */ 1824 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1825 mqd->cp_hqd_active); 1826 1827 if (ring->use_doorbell) 1828 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1829 1830 return 0; 1831 } 1832 1833 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1834 int xcc_id) 1835 { 1836 struct amdgpu_device *adev = ring->adev; 1837 int j; 1838 1839 /* disable the queue if it's active */ 1840 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1841 1842 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1843 1844 for (j = 0; j < adev->usec_timeout; j++) { 1845 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1846 break; 1847 udelay(1); 1848 } 1849 1850 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1851 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1852 1853 /* Manual disable if dequeue request times out */ 1854 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1855 } 1856 1857 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1858 0); 1859 } 1860 1861 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1862 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1863 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1864 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1865 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1866 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1867 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1868 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1869 1870 return 0; 1871 } 1872 1873 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1874 { 1875 struct amdgpu_device *adev = ring->adev; 1876 struct v9_mqd *mqd = ring->mqd_ptr; 1877 struct v9_mqd *tmp_mqd; 1878 1879 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1880 1881 /* GPU could be in bad state during probe, driver trigger the reset 1882 * after load the SMU, in this case , the mqd is not be initialized. 1883 * driver need to re-init the mqd. 1884 * check mqd->cp_hqd_pq_control since this value should not be 0 1885 */ 1886 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1887 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1888 /* for GPU_RESET case , reset MQD to a clean status */ 1889 if (adev->gfx.kiq[xcc_id].mqd_backup) 1890 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1891 1892 /* reset ring buffer */ 1893 ring->wptr = 0; 1894 amdgpu_ring_clear_ring(ring); 1895 mutex_lock(&adev->srbm_mutex); 1896 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1897 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1898 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1899 mutex_unlock(&adev->srbm_mutex); 1900 } else { 1901 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1902 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1903 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1904 mutex_lock(&adev->srbm_mutex); 1905 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1906 amdgpu_ring_clear_ring(ring); 1907 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1908 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1909 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1910 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1911 mutex_unlock(&adev->srbm_mutex); 1912 1913 if (adev->gfx.kiq[xcc_id].mqd_backup) 1914 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1915 } 1916 1917 return 0; 1918 } 1919 1920 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1921 { 1922 struct amdgpu_device *adev = ring->adev; 1923 struct v9_mqd *mqd = ring->mqd_ptr; 1924 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1925 struct v9_mqd *tmp_mqd; 1926 1927 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1928 * is not be initialized before 1929 */ 1930 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1931 1932 if (!tmp_mqd->cp_hqd_pq_control || 1933 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1934 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1935 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1936 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1937 mutex_lock(&adev->srbm_mutex); 1938 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1939 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1940 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1941 mutex_unlock(&adev->srbm_mutex); 1942 1943 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1944 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1945 } else { 1946 /* restore MQD to a clean status */ 1947 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1948 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1949 /* reset ring buffer */ 1950 ring->wptr = 0; 1951 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1952 amdgpu_ring_clear_ring(ring); 1953 } 1954 1955 return 0; 1956 } 1957 1958 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1959 { 1960 struct amdgpu_ring *ring; 1961 int j; 1962 1963 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1964 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1965 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1966 mutex_lock(&adev->srbm_mutex); 1967 soc15_grbm_select(adev, ring->me, 1968 ring->pipe, 1969 ring->queue, 0, GET_INST(GC, xcc_id)); 1970 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1971 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1972 mutex_unlock(&adev->srbm_mutex); 1973 } 1974 } 1975 1976 return 0; 1977 } 1978 1979 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1980 { 1981 struct amdgpu_ring *ring; 1982 int r; 1983 1984 ring = &adev->gfx.kiq[xcc_id].ring; 1985 1986 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1987 if (unlikely(r != 0)) 1988 return r; 1989 1990 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1991 if (unlikely(r != 0)) { 1992 amdgpu_bo_unreserve(ring->mqd_obj); 1993 return r; 1994 } 1995 1996 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1997 amdgpu_bo_kunmap(ring->mqd_obj); 1998 ring->mqd_ptr = NULL; 1999 amdgpu_bo_unreserve(ring->mqd_obj); 2000 return 0; 2001 } 2002 2003 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2004 { 2005 struct amdgpu_ring *ring = NULL; 2006 int r = 0, i; 2007 2008 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2009 2010 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2011 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2012 2013 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2014 if (unlikely(r != 0)) 2015 goto done; 2016 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2017 if (!r) { 2018 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 2019 amdgpu_bo_kunmap(ring->mqd_obj); 2020 ring->mqd_ptr = NULL; 2021 } 2022 amdgpu_bo_unreserve(ring->mqd_obj); 2023 if (r) 2024 goto done; 2025 } 2026 2027 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2028 done: 2029 return r; 2030 } 2031 2032 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2033 { 2034 struct amdgpu_ring *ring; 2035 int r, j; 2036 2037 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2038 2039 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2040 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2041 2042 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2043 if (r) 2044 return r; 2045 } 2046 2047 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2048 if (r) 2049 return r; 2050 2051 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2052 if (r) 2053 return r; 2054 2055 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2056 ring = &adev->gfx.compute_ring 2057 [j + xcc_id * adev->gfx.num_compute_rings]; 2058 r = amdgpu_ring_test_helper(ring); 2059 if (r) 2060 return r; 2061 } 2062 2063 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2064 2065 return 0; 2066 } 2067 2068 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2069 { 2070 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2071 2072 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2073 if (amdgpu_sriov_vf(adev)) { 2074 enum amdgpu_gfx_partition mode; 2075 2076 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2077 AMDGPU_XCP_FL_NONE); 2078 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2079 return -EINVAL; 2080 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2081 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2082 num_xcp = num_xcc / num_xcc_per_xcp; 2083 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2084 2085 } else { 2086 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2087 AMDGPU_XCP_FL_NONE) == 2088 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2089 r = amdgpu_xcp_switch_partition_mode( 2090 adev->xcp_mgr, amdgpu_user_partt_mode); 2091 } 2092 if (r) 2093 return r; 2094 2095 for (i = 0; i < num_xcc; i++) { 2096 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2097 if (r) 2098 return r; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 2105 int xcc_id) 2106 { 2107 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 2108 } 2109 2110 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2111 { 2112 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2113 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2114 2115 if (amdgpu_sriov_vf(adev)) { 2116 /* must disable polling for SRIOV when hw finished, otherwise 2117 * CPC engine may still keep fetching WB address which is already 2118 * invalid after sw finished and trigger DMAR reading error in 2119 * hypervisor side. 2120 */ 2121 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2122 return; 2123 } 2124 2125 /* Use deinitialize sequence from CAIL when unbinding device 2126 * from driver, otherwise KIQ is hanging when binding back 2127 */ 2128 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2129 mutex_lock(&adev->srbm_mutex); 2130 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2131 adev->gfx.kiq[xcc_id].ring.pipe, 2132 adev->gfx.kiq[xcc_id].ring.queue, 0, 2133 GET_INST(GC, xcc_id)); 2134 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2135 xcc_id); 2136 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2137 mutex_unlock(&adev->srbm_mutex); 2138 } 2139 2140 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2141 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2142 } 2143 2144 static int gfx_v9_4_3_hw_init(void *handle) 2145 { 2146 int r; 2147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2148 2149 if (!amdgpu_sriov_vf(adev)) 2150 gfx_v9_4_3_init_golden_registers(adev); 2151 2152 gfx_v9_4_3_constants_init(adev); 2153 2154 r = adev->gfx.rlc.funcs->resume(adev); 2155 if (r) 2156 return r; 2157 2158 r = gfx_v9_4_3_cp_resume(adev); 2159 if (r) 2160 return r; 2161 2162 return r; 2163 } 2164 2165 static int gfx_v9_4_3_hw_fini(void *handle) 2166 { 2167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2168 int i, num_xcc; 2169 2170 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2171 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2172 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2173 2174 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2175 for (i = 0; i < num_xcc; i++) { 2176 gfx_v9_4_3_xcc_fini(adev, i); 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int gfx_v9_4_3_suspend(void *handle) 2183 { 2184 return gfx_v9_4_3_hw_fini(handle); 2185 } 2186 2187 static int gfx_v9_4_3_resume(void *handle) 2188 { 2189 return gfx_v9_4_3_hw_init(handle); 2190 } 2191 2192 static bool gfx_v9_4_3_is_idle(void *handle) 2193 { 2194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2195 int i, num_xcc; 2196 2197 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2198 for (i = 0; i < num_xcc; i++) { 2199 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2200 GRBM_STATUS, GUI_ACTIVE)) 2201 return false; 2202 } 2203 return true; 2204 } 2205 2206 static int gfx_v9_4_3_wait_for_idle(void *handle) 2207 { 2208 unsigned i; 2209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2210 2211 for (i = 0; i < adev->usec_timeout; i++) { 2212 if (gfx_v9_4_3_is_idle(handle)) 2213 return 0; 2214 udelay(1); 2215 } 2216 return -ETIMEDOUT; 2217 } 2218 2219 static int gfx_v9_4_3_soft_reset(void *handle) 2220 { 2221 u32 grbm_soft_reset = 0; 2222 u32 tmp; 2223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2224 2225 /* GRBM_STATUS */ 2226 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2227 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2228 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2229 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2230 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2231 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2232 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2233 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2234 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2235 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2236 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2237 } 2238 2239 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2240 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2241 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2242 } 2243 2244 /* GRBM_STATUS2 */ 2245 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2246 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2247 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2248 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2249 2250 2251 if (grbm_soft_reset) { 2252 /* stop the rlc */ 2253 adev->gfx.rlc.funcs->stop(adev); 2254 2255 /* Disable MEC parsing/prefetching */ 2256 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2257 2258 if (grbm_soft_reset) { 2259 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2260 tmp |= grbm_soft_reset; 2261 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2262 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2263 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2264 2265 udelay(50); 2266 2267 tmp &= ~grbm_soft_reset; 2268 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2269 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2270 } 2271 2272 /* Wait a little for things to settle down */ 2273 udelay(50); 2274 } 2275 return 0; 2276 } 2277 2278 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2279 uint32_t vmid, 2280 uint32_t gds_base, uint32_t gds_size, 2281 uint32_t gws_base, uint32_t gws_size, 2282 uint32_t oa_base, uint32_t oa_size) 2283 { 2284 struct amdgpu_device *adev = ring->adev; 2285 2286 /* GDS Base */ 2287 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2288 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2289 gds_base); 2290 2291 /* GDS Size */ 2292 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2293 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2294 gds_size); 2295 2296 /* GWS */ 2297 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2298 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2299 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2300 2301 /* OA */ 2302 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2303 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2304 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2305 } 2306 2307 static int gfx_v9_4_3_early_init(void *handle) 2308 { 2309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2310 2311 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2312 AMDGPU_MAX_COMPUTE_RINGS); 2313 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2314 gfx_v9_4_3_set_ring_funcs(adev); 2315 gfx_v9_4_3_set_irq_funcs(adev); 2316 gfx_v9_4_3_set_gds_init(adev); 2317 gfx_v9_4_3_set_rlc_funcs(adev); 2318 2319 /* init rlcg reg access ctrl */ 2320 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2321 2322 return gfx_v9_4_3_init_microcode(adev); 2323 } 2324 2325 static int gfx_v9_4_3_late_init(void *handle) 2326 { 2327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2328 int r; 2329 2330 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2331 if (r) 2332 return r; 2333 2334 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2335 if (r) 2336 return r; 2337 2338 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2339 if (r) 2340 return r; 2341 2342 if (adev->gfx.ras && 2343 adev->gfx.ras->enable_watchdog_timer) 2344 adev->gfx.ras->enable_watchdog_timer(adev); 2345 2346 return 0; 2347 } 2348 2349 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2350 bool enable, int xcc_id) 2351 { 2352 uint32_t def, data; 2353 2354 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2355 return; 2356 2357 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2358 regRLC_CGTT_MGCG_OVERRIDE); 2359 2360 if (enable) 2361 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2362 else 2363 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2364 2365 if (def != data) 2366 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2367 regRLC_CGTT_MGCG_OVERRIDE, data); 2368 2369 } 2370 2371 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2372 bool enable, int xcc_id) 2373 { 2374 uint32_t def, data; 2375 2376 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2377 return; 2378 2379 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2380 regRLC_CGTT_MGCG_OVERRIDE); 2381 2382 if (enable) 2383 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2384 else 2385 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2386 2387 if (def != data) 2388 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2389 regRLC_CGTT_MGCG_OVERRIDE, data); 2390 } 2391 2392 static void 2393 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2394 bool enable, int xcc_id) 2395 { 2396 uint32_t data, def; 2397 2398 /* It is disabled by HW by default */ 2399 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2400 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2401 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2402 2403 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2404 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2405 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2406 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2407 2408 if (def != data) 2409 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2410 2411 /* MGLS is a global flag to control all MGLS in GFX */ 2412 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2413 /* 2 - RLC memory Light sleep */ 2414 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2415 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2416 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2417 if (def != data) 2418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2419 } 2420 /* 3 - CP memory Light sleep */ 2421 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2422 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2423 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2424 if (def != data) 2425 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2426 } 2427 } 2428 } else { 2429 /* 1 - MGCG_OVERRIDE */ 2430 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2431 2432 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2433 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2434 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2435 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2436 2437 if (def != data) 2438 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2439 2440 /* 2 - disable MGLS in RLC */ 2441 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2442 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2443 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2444 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2445 } 2446 2447 /* 3 - disable MGLS in CP */ 2448 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2449 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2450 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2451 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2452 } 2453 } 2454 2455 } 2456 2457 static void 2458 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2459 bool enable, int xcc_id) 2460 { 2461 uint32_t def, data; 2462 2463 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2464 2465 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2466 /* unset CGCG override */ 2467 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2468 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2469 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2470 else 2471 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2472 /* update CGCG and CGLS override bits */ 2473 if (def != data) 2474 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2475 2476 /* CGCG Hysteresis: 400us */ 2477 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2478 2479 data = (0x2710 2480 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2481 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2482 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2483 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2484 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2485 if (def != data) 2486 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2487 2488 /* set IDLE_POLL_COUNT(0x33450100)*/ 2489 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2490 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2491 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2492 if (def != data) 2493 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2494 } else { 2495 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2496 /* reset CGCG/CGLS bits */ 2497 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2498 /* disable cgcg and cgls in FSM */ 2499 if (def != data) 2500 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2501 } 2502 2503 } 2504 2505 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2506 bool enable, int xcc_id) 2507 { 2508 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2509 2510 if (enable) { 2511 /* FGCG */ 2512 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2513 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2514 2515 /* CGCG/CGLS should be enabled after MGCG/MGLS 2516 * === MGCG + MGLS === 2517 */ 2518 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2519 xcc_id); 2520 /* === CGCG + CGLS === */ 2521 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2522 xcc_id); 2523 } else { 2524 /* CGCG/CGLS should be disabled before MGCG/MGLS 2525 * === CGCG + CGLS === 2526 */ 2527 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2528 xcc_id); 2529 /* === MGCG + MGLS === */ 2530 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2531 xcc_id); 2532 2533 /* FGCG */ 2534 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2535 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2536 } 2537 2538 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2539 2540 return 0; 2541 } 2542 2543 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2544 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2545 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2546 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2547 .init = gfx_v9_4_3_rlc_init, 2548 .resume = gfx_v9_4_3_rlc_resume, 2549 .stop = gfx_v9_4_3_rlc_stop, 2550 .reset = gfx_v9_4_3_rlc_reset, 2551 .start = gfx_v9_4_3_rlc_start, 2552 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2553 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2554 }; 2555 2556 static int gfx_v9_4_3_set_powergating_state(void *handle, 2557 enum amd_powergating_state state) 2558 { 2559 return 0; 2560 } 2561 2562 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2563 enum amd_clockgating_state state) 2564 { 2565 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2566 int i, num_xcc; 2567 2568 if (amdgpu_sriov_vf(adev)) 2569 return 0; 2570 2571 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2572 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2573 case IP_VERSION(9, 4, 3): 2574 case IP_VERSION(9, 4, 4): 2575 for (i = 0; i < num_xcc; i++) 2576 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2577 adev, state == AMD_CG_STATE_GATE, i); 2578 break; 2579 default: 2580 break; 2581 } 2582 return 0; 2583 } 2584 2585 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2586 { 2587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2588 int data; 2589 2590 if (amdgpu_sriov_vf(adev)) 2591 *flags = 0; 2592 2593 /* AMD_CG_SUPPORT_GFX_MGCG */ 2594 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2595 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2596 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2597 2598 /* AMD_CG_SUPPORT_GFX_CGCG */ 2599 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2600 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2601 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2602 2603 /* AMD_CG_SUPPORT_GFX_CGLS */ 2604 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2605 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2606 2607 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2608 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2609 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2610 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2611 2612 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2613 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2614 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2615 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2616 } 2617 2618 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2619 { 2620 struct amdgpu_device *adev = ring->adev; 2621 u32 ref_and_mask, reg_mem_engine; 2622 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2623 2624 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2625 switch (ring->me) { 2626 case 1: 2627 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2628 break; 2629 case 2: 2630 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2631 break; 2632 default: 2633 return; 2634 } 2635 reg_mem_engine = 0; 2636 } else { 2637 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2638 reg_mem_engine = 1; /* pfp */ 2639 } 2640 2641 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2642 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2643 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2644 ref_and_mask, ref_and_mask, 0x20); 2645 } 2646 2647 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2648 struct amdgpu_job *job, 2649 struct amdgpu_ib *ib, 2650 uint32_t flags) 2651 { 2652 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2653 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2654 2655 /* Currently, there is a high possibility to get wave ID mismatch 2656 * between ME and GDS, leading to a hw deadlock, because ME generates 2657 * different wave IDs than the GDS expects. This situation happens 2658 * randomly when at least 5 compute pipes use GDS ordered append. 2659 * The wave IDs generated by ME are also wrong after suspend/resume. 2660 * Those are probably bugs somewhere else in the kernel driver. 2661 * 2662 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2663 * GDS to 0 for this ring (me/pipe). 2664 */ 2665 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2666 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2667 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2668 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2669 } 2670 2671 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2672 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2673 amdgpu_ring_write(ring, 2674 #ifdef __BIG_ENDIAN 2675 (2 << 0) | 2676 #endif 2677 lower_32_bits(ib->gpu_addr)); 2678 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2679 amdgpu_ring_write(ring, control); 2680 } 2681 2682 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2683 u64 seq, unsigned flags) 2684 { 2685 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2686 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2687 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2688 2689 /* RELEASE_MEM - flush caches, send int */ 2690 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2691 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2692 EOP_TC_NC_ACTION_EN) : 2693 (EOP_TCL1_ACTION_EN | 2694 EOP_TC_ACTION_EN | 2695 EOP_TC_WB_ACTION_EN | 2696 EOP_TC_MD_ACTION_EN)) | 2697 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2698 EVENT_INDEX(5))); 2699 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2700 2701 /* 2702 * the address should be Qword aligned if 64bit write, Dword 2703 * aligned if only send 32bit data low (discard data high) 2704 */ 2705 if (write64bit) 2706 BUG_ON(addr & 0x7); 2707 else 2708 BUG_ON(addr & 0x3); 2709 amdgpu_ring_write(ring, lower_32_bits(addr)); 2710 amdgpu_ring_write(ring, upper_32_bits(addr)); 2711 amdgpu_ring_write(ring, lower_32_bits(seq)); 2712 amdgpu_ring_write(ring, upper_32_bits(seq)); 2713 amdgpu_ring_write(ring, 0); 2714 } 2715 2716 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2717 { 2718 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2719 uint32_t seq = ring->fence_drv.sync_seq; 2720 uint64_t addr = ring->fence_drv.gpu_addr; 2721 2722 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2723 lower_32_bits(addr), upper_32_bits(addr), 2724 seq, 0xffffffff, 4); 2725 } 2726 2727 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2728 unsigned vmid, uint64_t pd_addr) 2729 { 2730 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2731 } 2732 2733 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2734 { 2735 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2736 } 2737 2738 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2739 { 2740 u64 wptr; 2741 2742 /* XXX check if swapping is necessary on BE */ 2743 if (ring->use_doorbell) 2744 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2745 else 2746 BUG(); 2747 return wptr; 2748 } 2749 2750 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2751 { 2752 struct amdgpu_device *adev = ring->adev; 2753 2754 /* XXX check if swapping is necessary on BE */ 2755 if (ring->use_doorbell) { 2756 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2757 WDOORBELL64(ring->doorbell_index, ring->wptr); 2758 } else { 2759 BUG(); /* only DOORBELL method supported on gfx9 now */ 2760 } 2761 } 2762 2763 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2764 u64 seq, unsigned int flags) 2765 { 2766 struct amdgpu_device *adev = ring->adev; 2767 2768 /* we only allocate 32bit for each seq wb address */ 2769 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2770 2771 /* write fence seq to the "addr" */ 2772 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2773 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2774 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2775 amdgpu_ring_write(ring, lower_32_bits(addr)); 2776 amdgpu_ring_write(ring, upper_32_bits(addr)); 2777 amdgpu_ring_write(ring, lower_32_bits(seq)); 2778 2779 if (flags & AMDGPU_FENCE_FLAG_INT) { 2780 /* set register to trigger INT */ 2781 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2782 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2783 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2784 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2785 amdgpu_ring_write(ring, 0); 2786 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2787 } 2788 } 2789 2790 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2791 uint32_t reg_val_offs) 2792 { 2793 struct amdgpu_device *adev = ring->adev; 2794 2795 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2796 2797 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2798 amdgpu_ring_write(ring, 0 | /* src: register*/ 2799 (5 << 8) | /* dst: memory */ 2800 (1 << 20)); /* write confirm */ 2801 amdgpu_ring_write(ring, reg); 2802 amdgpu_ring_write(ring, 0); 2803 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2804 reg_val_offs * 4)); 2805 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2806 reg_val_offs * 4)); 2807 } 2808 2809 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2810 uint32_t val) 2811 { 2812 uint32_t cmd = 0; 2813 2814 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2815 2816 switch (ring->funcs->type) { 2817 case AMDGPU_RING_TYPE_GFX: 2818 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2819 break; 2820 case AMDGPU_RING_TYPE_KIQ: 2821 cmd = (1 << 16); /* no inc addr */ 2822 break; 2823 default: 2824 cmd = WR_CONFIRM; 2825 break; 2826 } 2827 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2828 amdgpu_ring_write(ring, cmd); 2829 amdgpu_ring_write(ring, reg); 2830 amdgpu_ring_write(ring, 0); 2831 amdgpu_ring_write(ring, val); 2832 } 2833 2834 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2835 uint32_t val, uint32_t mask) 2836 { 2837 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2838 } 2839 2840 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2841 uint32_t reg0, uint32_t reg1, 2842 uint32_t ref, uint32_t mask) 2843 { 2844 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2845 ref, mask); 2846 } 2847 2848 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 2849 unsigned vmid) 2850 { 2851 struct amdgpu_device *adev = ring->adev; 2852 uint32_t value = 0; 2853 2854 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 2855 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 2856 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 2857 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 2858 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 2859 } 2860 2861 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2862 struct amdgpu_device *adev, int me, int pipe, 2863 enum amdgpu_interrupt_state state, int xcc_id) 2864 { 2865 u32 mec_int_cntl, mec_int_cntl_reg; 2866 2867 /* 2868 * amdgpu controls only the first MEC. That's why this function only 2869 * handles the setting of interrupts for this specific MEC. All other 2870 * pipes' interrupts are set by amdkfd. 2871 */ 2872 2873 if (me == 1) { 2874 switch (pipe) { 2875 case 0: 2876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2877 break; 2878 case 1: 2879 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2880 break; 2881 case 2: 2882 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2883 break; 2884 case 3: 2885 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2886 break; 2887 default: 2888 DRM_DEBUG("invalid pipe %d\n", pipe); 2889 return; 2890 } 2891 } else { 2892 DRM_DEBUG("invalid me %d\n", me); 2893 return; 2894 } 2895 2896 switch (state) { 2897 case AMDGPU_IRQ_STATE_DISABLE: 2898 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2899 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2900 TIME_STAMP_INT_ENABLE, 0); 2901 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2902 break; 2903 case AMDGPU_IRQ_STATE_ENABLE: 2904 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2905 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2906 TIME_STAMP_INT_ENABLE, 1); 2907 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2908 break; 2909 default: 2910 break; 2911 } 2912 } 2913 2914 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 2915 int xcc_id, int me, int pipe) 2916 { 2917 /* 2918 * amdgpu controls only the first MEC. That's why this function only 2919 * handles the setting of interrupts for this specific MEC. All other 2920 * pipes' interrupts are set by amdkfd. 2921 */ 2922 if (me != 1) 2923 return 0; 2924 2925 switch (pipe) { 2926 case 0: 2927 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2928 case 1: 2929 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2930 case 2: 2931 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2932 case 3: 2933 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2934 default: 2935 return 0; 2936 } 2937 } 2938 2939 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2940 struct amdgpu_irq_src *source, 2941 unsigned type, 2942 enum amdgpu_interrupt_state state) 2943 { 2944 u32 mec_int_cntl_reg, mec_int_cntl; 2945 int i, j, k, num_xcc; 2946 2947 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2948 switch (state) { 2949 case AMDGPU_IRQ_STATE_DISABLE: 2950 case AMDGPU_IRQ_STATE_ENABLE: 2951 for (i = 0; i < num_xcc; i++) { 2952 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2953 PRIV_REG_INT_ENABLE, 2954 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2955 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 2956 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2957 /* MECs start at 1 */ 2958 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 2959 2960 if (mec_int_cntl_reg) { 2961 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 2962 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2963 PRIV_REG_INT_ENABLE, 2964 state == AMDGPU_IRQ_STATE_ENABLE ? 2965 1 : 0); 2966 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 2967 } 2968 } 2969 } 2970 } 2971 break; 2972 default: 2973 break; 2974 } 2975 2976 return 0; 2977 } 2978 2979 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 2980 struct amdgpu_irq_src *source, 2981 unsigned type, 2982 enum amdgpu_interrupt_state state) 2983 { 2984 u32 mec_int_cntl_reg, mec_int_cntl; 2985 int i, j, k, num_xcc; 2986 2987 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2988 switch (state) { 2989 case AMDGPU_IRQ_STATE_DISABLE: 2990 case AMDGPU_IRQ_STATE_ENABLE: 2991 for (i = 0; i < num_xcc; i++) { 2992 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2993 OPCODE_ERROR_INT_ENABLE, 2994 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2995 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 2996 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2997 /* MECs start at 1 */ 2998 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 2999 3000 if (mec_int_cntl_reg) { 3001 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3002 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3003 OPCODE_ERROR_INT_ENABLE, 3004 state == AMDGPU_IRQ_STATE_ENABLE ? 3005 1 : 0); 3006 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3007 } 3008 } 3009 } 3010 } 3011 break; 3012 default: 3013 break; 3014 } 3015 3016 return 0; 3017 } 3018 3019 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3020 struct amdgpu_irq_src *source, 3021 unsigned type, 3022 enum amdgpu_interrupt_state state) 3023 { 3024 int i, num_xcc; 3025 3026 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3027 switch (state) { 3028 case AMDGPU_IRQ_STATE_DISABLE: 3029 case AMDGPU_IRQ_STATE_ENABLE: 3030 for (i = 0; i < num_xcc; i++) 3031 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3032 PRIV_INSTR_INT_ENABLE, 3033 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3034 break; 3035 default: 3036 break; 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3043 struct amdgpu_irq_src *src, 3044 unsigned type, 3045 enum amdgpu_interrupt_state state) 3046 { 3047 int i, num_xcc; 3048 3049 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3050 for (i = 0; i < num_xcc; i++) { 3051 switch (type) { 3052 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3053 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3054 adev, 1, 0, state, i); 3055 break; 3056 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3057 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3058 adev, 1, 1, state, i); 3059 break; 3060 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3061 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3062 adev, 1, 2, state, i); 3063 break; 3064 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3065 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3066 adev, 1, 3, state, i); 3067 break; 3068 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3069 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3070 adev, 2, 0, state, i); 3071 break; 3072 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3073 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3074 adev, 2, 1, state, i); 3075 break; 3076 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3077 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3078 adev, 2, 2, state, i); 3079 break; 3080 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3081 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3082 adev, 2, 3, state, i); 3083 break; 3084 default: 3085 break; 3086 } 3087 } 3088 3089 return 0; 3090 } 3091 3092 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3093 struct amdgpu_irq_src *source, 3094 struct amdgpu_iv_entry *entry) 3095 { 3096 int i, xcc_id; 3097 u8 me_id, pipe_id, queue_id; 3098 struct amdgpu_ring *ring; 3099 3100 DRM_DEBUG("IH: CP EOP\n"); 3101 me_id = (entry->ring_id & 0x0c) >> 2; 3102 pipe_id = (entry->ring_id & 0x03) >> 0; 3103 queue_id = (entry->ring_id & 0x70) >> 4; 3104 3105 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3106 3107 if (xcc_id == -EINVAL) 3108 return -EINVAL; 3109 3110 switch (me_id) { 3111 case 0: 3112 case 1: 3113 case 2: 3114 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3115 ring = &adev->gfx.compute_ring 3116 [i + 3117 xcc_id * adev->gfx.num_compute_rings]; 3118 /* Per-queue interrupt is supported for MEC starting from VI. 3119 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3120 */ 3121 3122 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3123 amdgpu_fence_process(ring); 3124 } 3125 break; 3126 } 3127 return 0; 3128 } 3129 3130 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3131 struct amdgpu_iv_entry *entry) 3132 { 3133 u8 me_id, pipe_id, queue_id; 3134 struct amdgpu_ring *ring; 3135 int i, xcc_id; 3136 3137 me_id = (entry->ring_id & 0x0c) >> 2; 3138 pipe_id = (entry->ring_id & 0x03) >> 0; 3139 queue_id = (entry->ring_id & 0x70) >> 4; 3140 3141 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3142 3143 if (xcc_id == -EINVAL) 3144 return; 3145 3146 switch (me_id) { 3147 case 0: 3148 case 1: 3149 case 2: 3150 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3151 ring = &adev->gfx.compute_ring 3152 [i + 3153 xcc_id * adev->gfx.num_compute_rings]; 3154 if (ring->me == me_id && ring->pipe == pipe_id && 3155 ring->queue == queue_id) 3156 drm_sched_fault(&ring->sched); 3157 } 3158 break; 3159 } 3160 } 3161 3162 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3163 struct amdgpu_irq_src *source, 3164 struct amdgpu_iv_entry *entry) 3165 { 3166 DRM_ERROR("Illegal register access in command stream\n"); 3167 gfx_v9_4_3_fault(adev, entry); 3168 return 0; 3169 } 3170 3171 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3172 struct amdgpu_irq_src *source, 3173 struct amdgpu_iv_entry *entry) 3174 { 3175 DRM_ERROR("Illegal opcode in command stream\n"); 3176 gfx_v9_4_3_fault(adev, entry); 3177 return 0; 3178 } 3179 3180 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3181 struct amdgpu_irq_src *source, 3182 struct amdgpu_iv_entry *entry) 3183 { 3184 DRM_ERROR("Illegal instruction in command stream\n"); 3185 gfx_v9_4_3_fault(adev, entry); 3186 return 0; 3187 } 3188 3189 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3190 { 3191 const unsigned int cp_coher_cntl = 3192 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3193 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3194 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3195 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3196 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3197 3198 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3199 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3200 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3201 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3202 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3203 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3204 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3205 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3206 } 3207 3208 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3209 uint32_t pipe, bool enable) 3210 { 3211 struct amdgpu_device *adev = ring->adev; 3212 uint32_t val; 3213 uint32_t wcl_cs_reg; 3214 3215 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3216 val = enable ? 0x1 : 0x7f; 3217 3218 switch (pipe) { 3219 case 0: 3220 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3221 break; 3222 case 1: 3223 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3224 break; 3225 case 2: 3226 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3227 break; 3228 case 3: 3229 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3230 break; 3231 default: 3232 DRM_DEBUG("invalid pipe %d\n", pipe); 3233 return; 3234 } 3235 3236 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3237 3238 } 3239 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3240 { 3241 struct amdgpu_device *adev = ring->adev; 3242 uint32_t val; 3243 int i; 3244 3245 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3246 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3247 * around 25% of gpu resources. 3248 */ 3249 val = enable ? 0x1f : 0x07ffffff; 3250 amdgpu_ring_emit_wreg(ring, 3251 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3252 val); 3253 3254 /* Restrict waves for normal/low priority compute queues as well 3255 * to get best QoS for high priority compute jobs. 3256 * 3257 * amdgpu controls only 1st ME(0-3 CS pipes). 3258 */ 3259 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3260 if (i != ring->pipe) 3261 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3262 3263 } 3264 } 3265 3266 enum amdgpu_gfx_cp_ras_mem_id { 3267 AMDGPU_GFX_CP_MEM1 = 1, 3268 AMDGPU_GFX_CP_MEM2, 3269 AMDGPU_GFX_CP_MEM3, 3270 AMDGPU_GFX_CP_MEM4, 3271 AMDGPU_GFX_CP_MEM5, 3272 }; 3273 3274 enum amdgpu_gfx_gcea_ras_mem_id { 3275 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3276 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3277 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3278 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3279 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3280 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3281 AMDGPU_GFX_GCEA_MAM_DMEM0, 3282 AMDGPU_GFX_GCEA_MAM_DMEM1, 3283 AMDGPU_GFX_GCEA_MAM_DMEM2, 3284 AMDGPU_GFX_GCEA_MAM_DMEM3, 3285 AMDGPU_GFX_GCEA_MAM_AMEM0, 3286 AMDGPU_GFX_GCEA_MAM_AMEM1, 3287 AMDGPU_GFX_GCEA_MAM_AMEM2, 3288 AMDGPU_GFX_GCEA_MAM_AMEM3, 3289 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3290 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3291 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3292 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3293 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3294 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3295 }; 3296 3297 enum amdgpu_gfx_gc_cane_ras_mem_id { 3298 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3299 }; 3300 3301 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3302 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3303 }; 3304 3305 enum amdgpu_gfx_gds_ras_mem_id { 3306 AMDGPU_GFX_GDS_MEM0 = 0, 3307 }; 3308 3309 enum amdgpu_gfx_lds_ras_mem_id { 3310 AMDGPU_GFX_LDS_BANK0 = 0, 3311 AMDGPU_GFX_LDS_BANK1, 3312 AMDGPU_GFX_LDS_BANK2, 3313 AMDGPU_GFX_LDS_BANK3, 3314 AMDGPU_GFX_LDS_BANK4, 3315 AMDGPU_GFX_LDS_BANK5, 3316 AMDGPU_GFX_LDS_BANK6, 3317 AMDGPU_GFX_LDS_BANK7, 3318 AMDGPU_GFX_LDS_BANK8, 3319 AMDGPU_GFX_LDS_BANK9, 3320 AMDGPU_GFX_LDS_BANK10, 3321 AMDGPU_GFX_LDS_BANK11, 3322 AMDGPU_GFX_LDS_BANK12, 3323 AMDGPU_GFX_LDS_BANK13, 3324 AMDGPU_GFX_LDS_BANK14, 3325 AMDGPU_GFX_LDS_BANK15, 3326 AMDGPU_GFX_LDS_BANK16, 3327 AMDGPU_GFX_LDS_BANK17, 3328 AMDGPU_GFX_LDS_BANK18, 3329 AMDGPU_GFX_LDS_BANK19, 3330 AMDGPU_GFX_LDS_BANK20, 3331 AMDGPU_GFX_LDS_BANK21, 3332 AMDGPU_GFX_LDS_BANK22, 3333 AMDGPU_GFX_LDS_BANK23, 3334 AMDGPU_GFX_LDS_BANK24, 3335 AMDGPU_GFX_LDS_BANK25, 3336 AMDGPU_GFX_LDS_BANK26, 3337 AMDGPU_GFX_LDS_BANK27, 3338 AMDGPU_GFX_LDS_BANK28, 3339 AMDGPU_GFX_LDS_BANK29, 3340 AMDGPU_GFX_LDS_BANK30, 3341 AMDGPU_GFX_LDS_BANK31, 3342 AMDGPU_GFX_LDS_SP_BUFFER_A, 3343 AMDGPU_GFX_LDS_SP_BUFFER_B, 3344 }; 3345 3346 enum amdgpu_gfx_rlc_ras_mem_id { 3347 AMDGPU_GFX_RLC_GPMF32 = 1, 3348 AMDGPU_GFX_RLC_RLCVF32, 3349 AMDGPU_GFX_RLC_SCRATCH, 3350 AMDGPU_GFX_RLC_SRM_ARAM, 3351 AMDGPU_GFX_RLC_SRM_DRAM, 3352 AMDGPU_GFX_RLC_TCTAG, 3353 AMDGPU_GFX_RLC_SPM_SE, 3354 AMDGPU_GFX_RLC_SPM_GRBMT, 3355 }; 3356 3357 enum amdgpu_gfx_sp_ras_mem_id { 3358 AMDGPU_GFX_SP_SIMDID0 = 0, 3359 }; 3360 3361 enum amdgpu_gfx_spi_ras_mem_id { 3362 AMDGPU_GFX_SPI_MEM0 = 0, 3363 AMDGPU_GFX_SPI_MEM1, 3364 AMDGPU_GFX_SPI_MEM2, 3365 AMDGPU_GFX_SPI_MEM3, 3366 }; 3367 3368 enum amdgpu_gfx_sqc_ras_mem_id { 3369 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3370 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3371 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3372 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3373 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3374 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3375 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3376 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3377 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3378 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3379 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3380 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3381 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3382 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3383 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3384 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3385 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3386 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3387 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3388 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3389 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3390 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3391 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3392 }; 3393 3394 enum amdgpu_gfx_sq_ras_mem_id { 3395 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3396 AMDGPU_GFX_SQ_SGPR_MEM1, 3397 AMDGPU_GFX_SQ_SGPR_MEM2, 3398 AMDGPU_GFX_SQ_SGPR_MEM3, 3399 }; 3400 3401 enum amdgpu_gfx_ta_ras_mem_id { 3402 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3403 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3404 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3405 AMDGPU_GFX_TA_FSX_LFIFO, 3406 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3407 }; 3408 3409 enum amdgpu_gfx_tcc_ras_mem_id { 3410 AMDGPU_GFX_TCC_MEM1 = 1, 3411 }; 3412 3413 enum amdgpu_gfx_tca_ras_mem_id { 3414 AMDGPU_GFX_TCA_MEM1 = 1, 3415 }; 3416 3417 enum amdgpu_gfx_tci_ras_mem_id { 3418 AMDGPU_GFX_TCIW_MEM = 1, 3419 }; 3420 3421 enum amdgpu_gfx_tcp_ras_mem_id { 3422 AMDGPU_GFX_TCP_LFIFO0 = 1, 3423 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3424 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3425 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3426 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3427 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3428 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3429 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3430 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3431 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3432 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3433 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3434 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3435 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3436 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3437 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3438 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3439 AMDGPU_GFX_TCP_VM_FIFO, 3440 AMDGPU_GFX_TCP_DB_TAGRAM0, 3441 AMDGPU_GFX_TCP_DB_TAGRAM1, 3442 AMDGPU_GFX_TCP_DB_TAGRAM2, 3443 AMDGPU_GFX_TCP_DB_TAGRAM3, 3444 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3445 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3446 AMDGPU_GFX_TCP_CMD_FIFO, 3447 }; 3448 3449 enum amdgpu_gfx_td_ras_mem_id { 3450 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3451 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3452 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3453 }; 3454 3455 enum amdgpu_gfx_tcx_ras_mem_id { 3456 AMDGPU_GFX_TCX_FIFOD0 = 0, 3457 AMDGPU_GFX_TCX_FIFOD1, 3458 AMDGPU_GFX_TCX_FIFOD2, 3459 AMDGPU_GFX_TCX_FIFOD3, 3460 AMDGPU_GFX_TCX_FIFOD4, 3461 AMDGPU_GFX_TCX_FIFOD5, 3462 AMDGPU_GFX_TCX_FIFOD6, 3463 AMDGPU_GFX_TCX_FIFOD7, 3464 AMDGPU_GFX_TCX_FIFOB0, 3465 AMDGPU_GFX_TCX_FIFOB1, 3466 AMDGPU_GFX_TCX_FIFOB2, 3467 AMDGPU_GFX_TCX_FIFOB3, 3468 AMDGPU_GFX_TCX_FIFOB4, 3469 AMDGPU_GFX_TCX_FIFOB5, 3470 AMDGPU_GFX_TCX_FIFOB6, 3471 AMDGPU_GFX_TCX_FIFOB7, 3472 AMDGPU_GFX_TCX_FIFOA0, 3473 AMDGPU_GFX_TCX_FIFOA1, 3474 AMDGPU_GFX_TCX_FIFOA2, 3475 AMDGPU_GFX_TCX_FIFOA3, 3476 AMDGPU_GFX_TCX_FIFOA4, 3477 AMDGPU_GFX_TCX_FIFOA5, 3478 AMDGPU_GFX_TCX_FIFOA6, 3479 AMDGPU_GFX_TCX_FIFOA7, 3480 AMDGPU_GFX_TCX_CFIFO0, 3481 AMDGPU_GFX_TCX_CFIFO1, 3482 AMDGPU_GFX_TCX_CFIFO2, 3483 AMDGPU_GFX_TCX_CFIFO3, 3484 AMDGPU_GFX_TCX_CFIFO4, 3485 AMDGPU_GFX_TCX_CFIFO5, 3486 AMDGPU_GFX_TCX_CFIFO6, 3487 AMDGPU_GFX_TCX_CFIFO7, 3488 AMDGPU_GFX_TCX_FIFO_ACKB0, 3489 AMDGPU_GFX_TCX_FIFO_ACKB1, 3490 AMDGPU_GFX_TCX_FIFO_ACKB2, 3491 AMDGPU_GFX_TCX_FIFO_ACKB3, 3492 AMDGPU_GFX_TCX_FIFO_ACKB4, 3493 AMDGPU_GFX_TCX_FIFO_ACKB5, 3494 AMDGPU_GFX_TCX_FIFO_ACKB6, 3495 AMDGPU_GFX_TCX_FIFO_ACKB7, 3496 AMDGPU_GFX_TCX_FIFO_ACKD0, 3497 AMDGPU_GFX_TCX_FIFO_ACKD1, 3498 AMDGPU_GFX_TCX_FIFO_ACKD2, 3499 AMDGPU_GFX_TCX_FIFO_ACKD3, 3500 AMDGPU_GFX_TCX_FIFO_ACKD4, 3501 AMDGPU_GFX_TCX_FIFO_ACKD5, 3502 AMDGPU_GFX_TCX_FIFO_ACKD6, 3503 AMDGPU_GFX_TCX_FIFO_ACKD7, 3504 AMDGPU_GFX_TCX_DST_FIFOA0, 3505 AMDGPU_GFX_TCX_DST_FIFOA1, 3506 AMDGPU_GFX_TCX_DST_FIFOA2, 3507 AMDGPU_GFX_TCX_DST_FIFOA3, 3508 AMDGPU_GFX_TCX_DST_FIFOA4, 3509 AMDGPU_GFX_TCX_DST_FIFOA5, 3510 AMDGPU_GFX_TCX_DST_FIFOA6, 3511 AMDGPU_GFX_TCX_DST_FIFOA7, 3512 AMDGPU_GFX_TCX_DST_FIFOB0, 3513 AMDGPU_GFX_TCX_DST_FIFOB1, 3514 AMDGPU_GFX_TCX_DST_FIFOB2, 3515 AMDGPU_GFX_TCX_DST_FIFOB3, 3516 AMDGPU_GFX_TCX_DST_FIFOB4, 3517 AMDGPU_GFX_TCX_DST_FIFOB5, 3518 AMDGPU_GFX_TCX_DST_FIFOB6, 3519 AMDGPU_GFX_TCX_DST_FIFOB7, 3520 AMDGPU_GFX_TCX_DST_FIFOD0, 3521 AMDGPU_GFX_TCX_DST_FIFOD1, 3522 AMDGPU_GFX_TCX_DST_FIFOD2, 3523 AMDGPU_GFX_TCX_DST_FIFOD3, 3524 AMDGPU_GFX_TCX_DST_FIFOD4, 3525 AMDGPU_GFX_TCX_DST_FIFOD5, 3526 AMDGPU_GFX_TCX_DST_FIFOD6, 3527 AMDGPU_GFX_TCX_DST_FIFOD7, 3528 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3529 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3530 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3531 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3532 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3533 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3534 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3535 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3536 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3537 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3538 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3539 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3540 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3541 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3542 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3543 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3544 }; 3545 3546 enum amdgpu_gfx_atc_l2_ras_mem_id { 3547 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3548 }; 3549 3550 enum amdgpu_gfx_utcl2_ras_mem_id { 3551 AMDGPU_GFX_UTCL2_MEM0 = 0, 3552 }; 3553 3554 enum amdgpu_gfx_vml2_ras_mem_id { 3555 AMDGPU_GFX_VML2_MEM0 = 0, 3556 }; 3557 3558 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3559 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3560 }; 3561 3562 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3563 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3564 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3565 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3566 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3567 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3568 }; 3569 3570 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3571 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3572 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3573 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3574 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3575 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3576 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3577 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3578 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3579 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3580 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3581 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3582 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3583 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3584 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3585 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3586 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3587 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3588 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3589 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3590 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3591 }; 3592 3593 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3594 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3595 }; 3596 3597 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3598 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3599 }; 3600 3601 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3602 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3603 }; 3604 3605 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3606 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3607 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3608 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3609 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3610 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3611 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3612 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3613 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3614 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3615 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3616 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3617 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3618 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3619 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3620 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3621 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3622 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3623 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3624 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3625 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3626 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3627 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3628 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3629 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3630 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3631 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3632 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3633 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3634 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3635 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3636 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3637 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3638 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3639 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3640 }; 3641 3642 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3643 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3644 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3645 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3646 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3647 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3648 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3649 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3650 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3651 }; 3652 3653 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3654 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3655 }; 3656 3657 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3658 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3659 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3660 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3661 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3662 }; 3663 3664 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3665 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3666 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3667 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3668 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3669 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3670 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3671 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3672 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3673 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3674 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3675 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3676 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3677 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3678 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3679 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3680 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3681 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3682 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3683 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3684 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3685 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3686 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3687 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3688 }; 3689 3690 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3691 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3692 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3693 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3694 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3695 }; 3696 3697 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3698 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3699 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3700 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3701 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3702 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3703 }; 3704 3705 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3706 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3707 }; 3708 3709 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3710 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3711 }; 3712 3713 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3714 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3715 }; 3716 3717 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3718 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3719 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3720 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3721 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3722 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3723 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3724 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3725 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3726 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3727 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3728 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3729 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3730 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3731 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3732 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3733 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3734 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3735 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3736 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3737 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3738 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3739 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3740 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3741 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3742 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3743 }; 3744 3745 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3746 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3747 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3748 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3749 }; 3750 3751 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3752 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3753 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3754 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3755 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3756 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3757 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3758 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3759 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3760 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3761 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3762 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3763 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3764 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3765 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3766 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3767 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3768 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3769 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3770 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3771 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3772 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3773 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3774 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3775 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3776 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3777 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3778 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3779 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3780 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3781 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3782 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3783 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3784 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3785 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3786 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3787 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3788 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3789 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3790 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3791 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3792 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3793 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3794 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3795 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3796 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3797 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3798 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3799 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3800 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3801 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3802 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3803 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3804 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3805 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3806 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3807 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3808 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3809 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3810 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3811 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3812 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3813 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3814 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3815 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3816 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3817 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3818 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3819 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3820 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3821 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3822 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3823 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3824 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3825 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3826 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3827 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3828 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3829 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3830 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3831 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3832 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3833 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3834 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3835 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3836 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3837 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3838 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3839 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3840 }; 3841 3842 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3843 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3844 }; 3845 3846 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3847 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3848 }; 3849 3850 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3851 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3852 }; 3853 3854 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3855 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3856 }; 3857 3858 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3859 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3860 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3861 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3862 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3863 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3864 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3865 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3866 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3867 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3868 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3869 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3870 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3871 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3872 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3873 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3874 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3875 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3876 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3877 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3878 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3879 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3880 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3881 }; 3882 3883 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3884 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3885 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3886 AMDGPU_GFX_RLC_MEM, 1}, 3887 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3888 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3889 AMDGPU_GFX_CP_MEM, 1}, 3890 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3891 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3892 AMDGPU_GFX_CP_MEM, 1}, 3893 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3894 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3895 AMDGPU_GFX_CP_MEM, 1}, 3896 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3897 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3898 AMDGPU_GFX_GDS_MEM, 1}, 3899 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3900 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3901 AMDGPU_GFX_GC_CANE_MEM, 1}, 3902 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3903 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3904 AMDGPU_GFX_SPI_MEM, 1}, 3905 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3906 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3907 AMDGPU_GFX_SP_MEM, 4}, 3908 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3909 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3910 AMDGPU_GFX_SP_MEM, 4}, 3911 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3912 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3913 AMDGPU_GFX_SQ_MEM, 4}, 3914 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3915 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3916 AMDGPU_GFX_SQC_MEM, 4}, 3917 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3918 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3919 AMDGPU_GFX_TCX_MEM, 1}, 3920 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3921 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3922 AMDGPU_GFX_TCC_MEM, 1}, 3923 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3924 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3925 AMDGPU_GFX_TA_MEM, 4}, 3926 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3927 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3928 AMDGPU_GFX_TCI_MEM, 1}, 3929 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3930 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3931 AMDGPU_GFX_TCP_MEM, 4}, 3932 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3933 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3934 AMDGPU_GFX_TD_MEM, 4}, 3935 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3936 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3937 AMDGPU_GFX_GCEA_MEM, 1}, 3938 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3939 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3940 AMDGPU_GFX_LDS_MEM, 4}, 3941 }; 3942 3943 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3944 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3945 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3946 AMDGPU_GFX_RLC_MEM, 1}, 3947 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3948 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3949 AMDGPU_GFX_CP_MEM, 1}, 3950 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3951 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3952 AMDGPU_GFX_CP_MEM, 1}, 3953 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3954 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3955 AMDGPU_GFX_CP_MEM, 1}, 3956 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3957 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3958 AMDGPU_GFX_GDS_MEM, 1}, 3959 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3960 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3961 AMDGPU_GFX_GC_CANE_MEM, 1}, 3962 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3963 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3964 AMDGPU_GFX_SPI_MEM, 1}, 3965 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3966 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3967 AMDGPU_GFX_SP_MEM, 4}, 3968 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3969 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3970 AMDGPU_GFX_SP_MEM, 4}, 3971 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3972 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3973 AMDGPU_GFX_SQ_MEM, 4}, 3974 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3975 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3976 AMDGPU_GFX_SQC_MEM, 4}, 3977 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3978 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3979 AMDGPU_GFX_TCX_MEM, 1}, 3980 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3981 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3982 AMDGPU_GFX_TCC_MEM, 1}, 3983 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3984 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3985 AMDGPU_GFX_TA_MEM, 4}, 3986 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3987 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3988 AMDGPU_GFX_TCI_MEM, 1}, 3989 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3990 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3991 AMDGPU_GFX_TCP_MEM, 4}, 3992 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3993 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3994 AMDGPU_GFX_TD_MEM, 4}, 3995 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3996 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3997 AMDGPU_GFX_TCA_MEM, 1}, 3998 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3999 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4000 AMDGPU_GFX_GCEA_MEM, 1}, 4001 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4002 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4003 AMDGPU_GFX_LDS_MEM, 4}, 4004 }; 4005 4006 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4007 void *ras_error_status, int xcc_id) 4008 { 4009 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4010 unsigned long ce_count = 0, ue_count = 0; 4011 uint32_t i, j, k; 4012 4013 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4014 struct amdgpu_smuio_mcm_config_info mcm_info = { 4015 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4016 .die_id = xcc_id & 0x01 ? 1 : 0, 4017 }; 4018 4019 mutex_lock(&adev->grbm_idx_mutex); 4020 4021 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4022 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4023 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4024 /* no need to select if instance number is 1 */ 4025 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4026 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4027 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4028 4029 amdgpu_ras_inst_query_ras_error_count(adev, 4030 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4031 1, 4032 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4033 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4034 GET_INST(GC, xcc_id), 4035 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4036 &ce_count); 4037 4038 amdgpu_ras_inst_query_ras_error_count(adev, 4039 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4040 1, 4041 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4042 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4043 GET_INST(GC, xcc_id), 4044 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4045 &ue_count); 4046 } 4047 } 4048 } 4049 4050 /* handle extra register entries of UE */ 4051 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4052 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4053 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4054 /* no need to select if instance number is 1 */ 4055 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4056 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4057 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4058 4059 amdgpu_ras_inst_query_ras_error_count(adev, 4060 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4061 1, 4062 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4063 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4064 GET_INST(GC, xcc_id), 4065 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4066 &ue_count); 4067 } 4068 } 4069 } 4070 4071 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4072 xcc_id); 4073 mutex_unlock(&adev->grbm_idx_mutex); 4074 4075 /* the caller should make sure initialize value of 4076 * err_data->ue_count and err_data->ce_count 4077 */ 4078 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4079 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4080 } 4081 4082 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4083 void *ras_error_status, int xcc_id) 4084 { 4085 uint32_t i, j, k; 4086 4087 mutex_lock(&adev->grbm_idx_mutex); 4088 4089 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4090 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4091 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4092 /* no need to select if instance number is 1 */ 4093 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4094 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4095 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4096 4097 amdgpu_ras_inst_reset_ras_error_count(adev, 4098 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4099 1, 4100 GET_INST(GC, xcc_id)); 4101 4102 amdgpu_ras_inst_reset_ras_error_count(adev, 4103 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4104 1, 4105 GET_INST(GC, xcc_id)); 4106 } 4107 } 4108 } 4109 4110 /* handle extra register entries of UE */ 4111 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4112 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4113 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4114 /* no need to select if instance number is 1 */ 4115 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4116 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4117 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4118 4119 amdgpu_ras_inst_reset_ras_error_count(adev, 4120 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4121 1, 4122 GET_INST(GC, xcc_id)); 4123 } 4124 } 4125 } 4126 4127 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4128 xcc_id); 4129 mutex_unlock(&adev->grbm_idx_mutex); 4130 } 4131 4132 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4133 void *ras_error_status, int xcc_id) 4134 { 4135 uint32_t i; 4136 uint32_t data; 4137 4138 if (amdgpu_sriov_vf(adev)) 4139 return; 4140 4141 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4142 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4143 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4144 4145 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4146 (amdgpu_watchdog_timer.period < 1 || 4147 amdgpu_watchdog_timer.period > 0x23)) { 4148 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4149 amdgpu_watchdog_timer.period = 0x23; 4150 } 4151 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4152 amdgpu_watchdog_timer.period); 4153 4154 mutex_lock(&adev->grbm_idx_mutex); 4155 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4156 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4157 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4158 } 4159 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4160 xcc_id); 4161 mutex_unlock(&adev->grbm_idx_mutex); 4162 } 4163 4164 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4165 void *ras_error_status) 4166 { 4167 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4168 gfx_v9_4_3_inst_query_ras_err_count); 4169 } 4170 4171 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4172 { 4173 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4174 } 4175 4176 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4177 { 4178 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4179 } 4180 4181 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4182 { 4183 int i; 4184 4185 /* Header itself is a NOP packet */ 4186 if (num_nop == 1) { 4187 amdgpu_ring_write(ring, ring->funcs->nop); 4188 return; 4189 } 4190 4191 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4192 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4193 4194 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4195 for (i = 1; i < num_nop; i++) 4196 amdgpu_ring_write(ring, ring->funcs->nop); 4197 } 4198 4199 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4200 .name = "gfx_v9_4_3", 4201 .early_init = gfx_v9_4_3_early_init, 4202 .late_init = gfx_v9_4_3_late_init, 4203 .sw_init = gfx_v9_4_3_sw_init, 4204 .sw_fini = gfx_v9_4_3_sw_fini, 4205 .hw_init = gfx_v9_4_3_hw_init, 4206 .hw_fini = gfx_v9_4_3_hw_fini, 4207 .suspend = gfx_v9_4_3_suspend, 4208 .resume = gfx_v9_4_3_resume, 4209 .is_idle = gfx_v9_4_3_is_idle, 4210 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4211 .soft_reset = gfx_v9_4_3_soft_reset, 4212 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4213 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4214 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4215 .dump_ip_state = NULL, 4216 .print_ip_state = NULL, 4217 }; 4218 4219 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4220 .type = AMDGPU_RING_TYPE_COMPUTE, 4221 .align_mask = 0xff, 4222 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4223 .support_64bit_ptrs = true, 4224 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4225 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4226 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4227 .emit_frame_size = 4228 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4229 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4230 5 + /* hdp invalidate */ 4231 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4232 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4233 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4234 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4235 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4236 7 + /* gfx_v9_4_3_emit_mem_sync */ 4237 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4238 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4239 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4240 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4241 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4242 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4243 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4244 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4245 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4246 .test_ring = gfx_v9_4_3_ring_test_ring, 4247 .test_ib = gfx_v9_4_3_ring_test_ib, 4248 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4249 .pad_ib = amdgpu_ring_generic_pad_ib, 4250 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4251 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4252 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4253 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4254 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4255 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4256 }; 4257 4258 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4259 .type = AMDGPU_RING_TYPE_KIQ, 4260 .align_mask = 0xff, 4261 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4262 .support_64bit_ptrs = true, 4263 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4264 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4265 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4266 .emit_frame_size = 4267 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4268 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4269 5 + /* hdp invalidate */ 4270 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4271 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4272 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4273 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4274 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4275 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4276 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4277 .test_ring = gfx_v9_4_3_ring_test_ring, 4278 .insert_nop = amdgpu_ring_insert_nop, 4279 .pad_ib = amdgpu_ring_generic_pad_ib, 4280 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4281 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4282 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4283 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4284 }; 4285 4286 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4287 { 4288 int i, j, num_xcc; 4289 4290 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4291 for (i = 0; i < num_xcc; i++) { 4292 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4293 4294 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4295 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4296 = &gfx_v9_4_3_ring_funcs_compute; 4297 } 4298 } 4299 4300 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4301 .set = gfx_v9_4_3_set_eop_interrupt_state, 4302 .process = gfx_v9_4_3_eop_irq, 4303 }; 4304 4305 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4306 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4307 .process = gfx_v9_4_3_priv_reg_irq, 4308 }; 4309 4310 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4311 .set = gfx_v9_4_3_set_bad_op_fault_state, 4312 .process = gfx_v9_4_3_bad_op_irq, 4313 }; 4314 4315 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4316 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4317 .process = gfx_v9_4_3_priv_inst_irq, 4318 }; 4319 4320 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4321 { 4322 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4323 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4324 4325 adev->gfx.priv_reg_irq.num_types = 1; 4326 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4327 4328 adev->gfx.bad_op_irq.num_types = 1; 4329 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4330 4331 adev->gfx.priv_inst_irq.num_types = 1; 4332 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4333 } 4334 4335 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4336 { 4337 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4338 } 4339 4340 4341 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4342 { 4343 /* init asci gds info */ 4344 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4345 case IP_VERSION(9, 4, 3): 4346 case IP_VERSION(9, 4, 4): 4347 /* 9.4.3 removed all the GDS internal memory, 4348 * only support GWS opcode in kernel, like barrier 4349 * semaphore.etc */ 4350 adev->gds.gds_size = 0; 4351 break; 4352 default: 4353 adev->gds.gds_size = 0x10000; 4354 break; 4355 } 4356 4357 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4358 case IP_VERSION(9, 4, 3): 4359 case IP_VERSION(9, 4, 4): 4360 /* deprecated for 9.4.3, no usage at all */ 4361 adev->gds.gds_compute_max_wave_id = 0; 4362 break; 4363 default: 4364 /* this really depends on the chip */ 4365 adev->gds.gds_compute_max_wave_id = 0x7ff; 4366 break; 4367 } 4368 4369 adev->gds.gws_size = 64; 4370 adev->gds.oa_size = 16; 4371 } 4372 4373 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4374 u32 bitmap, int xcc_id) 4375 { 4376 u32 data; 4377 4378 if (!bitmap) 4379 return; 4380 4381 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4382 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4383 4384 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4385 } 4386 4387 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4388 { 4389 u32 data, mask; 4390 4391 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4392 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4393 4394 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4395 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4396 4397 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4398 4399 return (~data) & mask; 4400 } 4401 4402 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4403 struct amdgpu_cu_info *cu_info) 4404 { 4405 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4406 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4407 unsigned disable_masks[4 * 4]; 4408 bool is_symmetric_cus; 4409 4410 if (!adev || !cu_info) 4411 return -EINVAL; 4412 4413 /* 4414 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4415 */ 4416 if (adev->gfx.config.max_shader_engines * 4417 adev->gfx.config.max_sh_per_se > 16) 4418 return -EINVAL; 4419 4420 amdgpu_gfx_parse_disable_cu(disable_masks, 4421 adev->gfx.config.max_shader_engines, 4422 adev->gfx.config.max_sh_per_se); 4423 4424 mutex_lock(&adev->grbm_idx_mutex); 4425 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4426 is_symmetric_cus = true; 4427 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4428 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4429 mask = 1; 4430 ao_bitmap = 0; 4431 counter = 0; 4432 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4433 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4434 adev, 4435 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4436 xcc_id); 4437 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4438 4439 cu_info->bitmap[xcc_id][i][j] = bitmap; 4440 4441 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4442 if (bitmap & mask) { 4443 if (counter < adev->gfx.config.max_cu_per_sh) 4444 ao_bitmap |= mask; 4445 counter++; 4446 } 4447 mask <<= 1; 4448 } 4449 active_cu_number += counter; 4450 if (i < 2 && j < 2) 4451 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4452 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4453 } 4454 if (i && is_symmetric_cus && prev_counter != counter) 4455 is_symmetric_cus = false; 4456 prev_counter = counter; 4457 } 4458 if (is_symmetric_cus) { 4459 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4460 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4461 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4462 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4463 } 4464 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4465 xcc_id); 4466 } 4467 mutex_unlock(&adev->grbm_idx_mutex); 4468 4469 cu_info->number = active_cu_number; 4470 cu_info->ao_cu_mask = ao_cu_mask; 4471 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4472 4473 return 0; 4474 } 4475 4476 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4477 .type = AMD_IP_BLOCK_TYPE_GFX, 4478 .major = 9, 4479 .minor = 4, 4480 .rev = 3, 4481 .funcs = &gfx_v9_4_3_ip_funcs, 4482 }; 4483 4484 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4485 { 4486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4487 uint32_t tmp_mask; 4488 int i, r; 4489 4490 /* TODO : Initialize golden regs */ 4491 /* gfx_v9_4_3_init_golden_registers(adev); */ 4492 4493 tmp_mask = inst_mask; 4494 for_each_inst(i, tmp_mask) 4495 gfx_v9_4_3_xcc_constants_init(adev, i); 4496 4497 if (!amdgpu_sriov_vf(adev)) { 4498 tmp_mask = inst_mask; 4499 for_each_inst(i, tmp_mask) { 4500 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4501 if (r) 4502 return r; 4503 } 4504 } 4505 4506 tmp_mask = inst_mask; 4507 for_each_inst(i, tmp_mask) { 4508 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4509 if (r) 4510 return r; 4511 } 4512 4513 return 0; 4514 } 4515 4516 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4517 { 4518 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4519 int i; 4520 4521 for_each_inst(i, inst_mask) 4522 gfx_v9_4_3_xcc_fini(adev, i); 4523 4524 return 0; 4525 } 4526 4527 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4528 .suspend = &gfx_v9_4_3_xcp_suspend, 4529 .resume = &gfx_v9_4_3_xcp_resume 4530 }; 4531 4532 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4533 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4534 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4535 }; 4536 4537 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4538 { 4539 int r; 4540 4541 r = amdgpu_ras_block_late_init(adev, ras_block); 4542 if (r) 4543 return r; 4544 4545 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4546 &gfx_v9_4_3_aca_info, 4547 NULL); 4548 if (r) 4549 goto late_fini; 4550 4551 return 0; 4552 4553 late_fini: 4554 amdgpu_ras_block_late_fini(adev, ras_block); 4555 4556 return r; 4557 } 4558 4559 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4560 .ras_block = { 4561 .hw_ops = &gfx_v9_4_3_ras_ops, 4562 .ras_late_init = &gfx_v9_4_3_ras_late_init, 4563 }, 4564 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4565 }; 4566