1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 BUG_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 }; 852 853 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 854 struct aca_bank *bank, enum aca_smu_type type, 855 void *data) 856 { 857 struct aca_bank_info info; 858 u64 misc0; 859 u32 instlo; 860 int ret; 861 862 ret = aca_bank_info_decode(bank, &info); 863 if (ret) 864 return ret; 865 866 /* NOTE: overwrite info.die_id with xcd id for gfx */ 867 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 868 instlo &= GENMASK(31, 1); 869 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 870 871 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 872 873 switch (type) { 874 case ACA_SMU_TYPE_UE: 875 bank->aca_err_type = ACA_ERROR_TYPE_UE; 876 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 877 break; 878 case ACA_SMU_TYPE_CE: 879 bank->aca_err_type = ACA_ERROR_TYPE_CE; 880 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 881 ACA_REG__MISC0__ERRCNT(misc0)); 882 break; 883 default: 884 return -EINVAL; 885 } 886 887 return ret; 888 } 889 890 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 891 enum aca_smu_type type, void *data) 892 { 893 u32 instlo; 894 895 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 896 instlo &= GENMASK(31, 1); 897 switch (instlo) { 898 case mmSMNAID_XCD0_MCA_SMU: 899 case mmSMNAID_XCD1_MCA_SMU: 900 case mmSMNXCD_XCD0_MCA_SMU: 901 return true; 902 default: 903 break; 904 } 905 906 return false; 907 } 908 909 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 910 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 911 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 912 }; 913 914 static const struct aca_info gfx_v9_4_3_aca_info = { 915 .hwip = ACA_HWIP_TYPE_SMU, 916 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 917 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 918 }; 919 920 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 921 { 922 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 923 adev->gfx.ras = &gfx_v9_4_3_ras; 924 925 adev->gfx.config.max_hw_contexts = 8; 926 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 927 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 928 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 929 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 930 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 931 932 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 933 REG_GET_FIELD( 934 adev->gfx.config.gb_addr_config, 935 GB_ADDR_CONFIG, 936 NUM_PIPES); 937 938 adev->gfx.config.max_tile_pipes = 939 adev->gfx.config.gb_addr_config_fields.num_pipes; 940 941 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 942 REG_GET_FIELD( 943 adev->gfx.config.gb_addr_config, 944 GB_ADDR_CONFIG, 945 NUM_BANKS); 946 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 947 REG_GET_FIELD( 948 adev->gfx.config.gb_addr_config, 949 GB_ADDR_CONFIG, 950 MAX_COMPRESSED_FRAGS); 951 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 952 REG_GET_FIELD( 953 adev->gfx.config.gb_addr_config, 954 GB_ADDR_CONFIG, 955 NUM_RB_PER_SE); 956 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 957 REG_GET_FIELD( 958 adev->gfx.config.gb_addr_config, 959 GB_ADDR_CONFIG, 960 NUM_SHADER_ENGINES); 961 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 962 REG_GET_FIELD( 963 adev->gfx.config.gb_addr_config, 964 GB_ADDR_CONFIG, 965 PIPE_INTERLEAVE_SIZE)); 966 967 return 0; 968 } 969 970 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 971 int xcc_id, int mec, int pipe, int queue) 972 { 973 unsigned irq_type; 974 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 975 unsigned int hw_prio; 976 uint32_t xcc_doorbell_start; 977 978 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 979 ring_id]; 980 981 /* mec0 is me1 */ 982 ring->xcc_id = xcc_id; 983 ring->me = mec + 1; 984 ring->pipe = pipe; 985 ring->queue = queue; 986 987 ring->ring_obj = NULL; 988 ring->use_doorbell = true; 989 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 990 xcc_id * adev->doorbell_index.xcc_doorbell_range; 991 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 992 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 993 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 994 GFX9_MEC_HPD_SIZE; 995 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 996 sprintf(ring->name, "comp_%d.%d.%d.%d", 997 ring->xcc_id, ring->me, ring->pipe, ring->queue); 998 999 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1000 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1001 + ring->pipe; 1002 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1003 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1004 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1005 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1006 hw_prio, NULL); 1007 } 1008 1009 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1010 { 1011 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1012 uint32_t *ptr, num_xcc, inst; 1013 1014 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1015 1016 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1017 if (!ptr) { 1018 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1019 adev->gfx.ip_dump_core = NULL; 1020 } else { 1021 adev->gfx.ip_dump_core = ptr; 1022 } 1023 1024 /* Allocate memory for compute queue registers for all the instances */ 1025 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1026 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1027 adev->gfx.mec.num_queue_per_pipe; 1028 1029 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1030 if (!ptr) { 1031 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1032 adev->gfx.ip_dump_compute_queues = NULL; 1033 } else { 1034 adev->gfx.ip_dump_compute_queues = ptr; 1035 } 1036 } 1037 1038 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1039 { 1040 int i, j, k, r, ring_id, xcc_id, num_xcc; 1041 struct amdgpu_device *adev = ip_block->adev; 1042 1043 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1044 case IP_VERSION(9, 4, 3): 1045 case IP_VERSION(9, 4, 4): 1046 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1047 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1048 if (adev->gfx.mec_fw_version >= 153) { 1049 adev->gfx.enable_cleaner_shader = true; 1050 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1051 if (r) { 1052 adev->gfx.enable_cleaner_shader = false; 1053 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1054 } 1055 } 1056 break; 1057 default: 1058 adev->gfx.enable_cleaner_shader = false; 1059 break; 1060 } 1061 1062 adev->gfx.mec.num_mec = 2; 1063 adev->gfx.mec.num_pipe_per_mec = 4; 1064 adev->gfx.mec.num_queue_per_pipe = 8; 1065 1066 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1067 1068 /* EOP Event */ 1069 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1070 if (r) 1071 return r; 1072 1073 /* Bad opcode Event */ 1074 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1075 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1076 &adev->gfx.bad_op_irq); 1077 if (r) 1078 return r; 1079 1080 /* Privileged reg */ 1081 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1082 &adev->gfx.priv_reg_irq); 1083 if (r) 1084 return r; 1085 1086 /* Privileged inst */ 1087 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1088 &adev->gfx.priv_inst_irq); 1089 if (r) 1090 return r; 1091 1092 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1093 1094 r = adev->gfx.rlc.funcs->init(adev); 1095 if (r) { 1096 DRM_ERROR("Failed to init rlc BOs!\n"); 1097 return r; 1098 } 1099 1100 r = gfx_v9_4_3_mec_init(adev); 1101 if (r) { 1102 DRM_ERROR("Failed to init MEC BOs!\n"); 1103 return r; 1104 } 1105 1106 /* set up the compute queues - allocate horizontally across pipes */ 1107 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1108 ring_id = 0; 1109 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1110 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1111 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1112 k++) { 1113 if (!amdgpu_gfx_is_mec_queue_enabled( 1114 adev, xcc_id, i, k, j)) 1115 continue; 1116 1117 r = gfx_v9_4_3_compute_ring_init(adev, 1118 ring_id, 1119 xcc_id, 1120 i, k, j); 1121 if (r) 1122 return r; 1123 1124 ring_id++; 1125 } 1126 } 1127 } 1128 1129 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1130 if (r) { 1131 DRM_ERROR("Failed to init KIQ BOs!\n"); 1132 return r; 1133 } 1134 1135 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1136 if (r) 1137 return r; 1138 1139 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1140 r = amdgpu_gfx_mqd_sw_init(adev, 1141 sizeof(struct v9_mqd_allocation), xcc_id); 1142 if (r) 1143 return r; 1144 } 1145 1146 adev->gfx.compute_supported_reset = 1147 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1148 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1149 case IP_VERSION(9, 4, 3): 1150 case IP_VERSION(9, 4, 4): 1151 if (adev->gfx.mec_fw_version >= 155) { 1152 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1153 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1154 } 1155 break; 1156 case IP_VERSION(9, 5, 0): 1157 if (adev->gfx.mec_fw_version >= 21) { 1158 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1159 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1160 } 1161 break; 1162 default: 1163 break; 1164 } 1165 r = gfx_v9_4_3_gpu_early_init(adev); 1166 if (r) 1167 return r; 1168 1169 r = amdgpu_gfx_ras_sw_init(adev); 1170 if (r) 1171 return r; 1172 1173 r = amdgpu_gfx_sysfs_init(adev); 1174 if (r) 1175 return r; 1176 1177 gfx_v9_4_3_alloc_ip_dump(adev); 1178 1179 return 0; 1180 } 1181 1182 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1183 { 1184 int i, num_xcc; 1185 struct amdgpu_device *adev = ip_block->adev; 1186 1187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1188 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1189 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1190 1191 for (i = 0; i < num_xcc; i++) { 1192 amdgpu_gfx_mqd_sw_fini(adev, i); 1193 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1194 amdgpu_gfx_kiq_fini(adev, i); 1195 } 1196 1197 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1198 1199 gfx_v9_4_3_mec_fini(adev); 1200 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1201 gfx_v9_4_3_free_microcode(adev); 1202 amdgpu_gfx_sysfs_fini(adev); 1203 1204 kfree(adev->gfx.ip_dump_core); 1205 kfree(adev->gfx.ip_dump_compute_queues); 1206 1207 return 0; 1208 } 1209 1210 #define DEFAULT_SH_MEM_BASES (0x6000) 1211 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1212 int xcc_id) 1213 { 1214 int i; 1215 uint32_t sh_mem_config; 1216 uint32_t sh_mem_bases; 1217 uint32_t data; 1218 1219 /* 1220 * Configure apertures: 1221 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1222 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1223 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1224 */ 1225 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1226 1227 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1228 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1229 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1230 1231 mutex_lock(&adev->srbm_mutex); 1232 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1233 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1234 /* CP and shaders */ 1235 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1236 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1237 1238 /* Enable trap for each kfd vmid. */ 1239 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1240 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1242 } 1243 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1244 mutex_unlock(&adev->srbm_mutex); 1245 1246 /* 1247 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1248 * access. These should be enabled by FW for target VMIDs. 1249 */ 1250 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1251 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1252 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1253 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1254 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1255 } 1256 } 1257 1258 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1259 { 1260 int vmid; 1261 1262 /* 1263 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1264 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1265 * the driver can enable them for graphics. VMID0 should maintain 1266 * access so that HWS firmware can save/restore entries. 1267 */ 1268 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1269 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1270 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1271 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1272 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1273 } 1274 } 1275 1276 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1277 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1278 * bit in SET_RESOURCES 1279 */ 1280 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1281 { 1282 uint32_t data; 1283 1284 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1285 return; 1286 1287 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1288 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1289 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1290 } 1291 1292 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1293 int xcc_id) 1294 { 1295 u32 tmp; 1296 int i; 1297 1298 /* XXX SH_MEM regs */ 1299 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1300 mutex_lock(&adev->srbm_mutex); 1301 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1302 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1303 /* CP and shaders */ 1304 if (i == 0) { 1305 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1306 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1307 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1308 !!adev->gmc.noretry); 1309 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1310 regSH_MEM_CONFIG, tmp); 1311 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1312 regSH_MEM_BASES, 0); 1313 } else { 1314 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1315 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1316 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1317 !!adev->gmc.noretry); 1318 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1319 regSH_MEM_CONFIG, tmp); 1320 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1321 (adev->gmc.private_aperture_start >> 1322 48)); 1323 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1324 (adev->gmc.shared_aperture_start >> 1325 48)); 1326 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1327 regSH_MEM_BASES, tmp); 1328 } 1329 } 1330 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1331 1332 mutex_unlock(&adev->srbm_mutex); 1333 1334 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1335 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1336 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1337 } 1338 1339 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1340 { 1341 int i, num_xcc; 1342 1343 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1344 1345 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1346 adev->gfx.config.db_debug2 = 1347 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1348 1349 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1350 /* ToDo: GC 9.4.4 */ 1351 case IP_VERSION(9, 4, 3): 1352 if (adev->gfx.mec_fw_version >= 184) 1353 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1354 break; 1355 case IP_VERSION(9, 5, 0): 1356 if (adev->gfx.mec_fw_version >= 23) 1357 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1358 break; 1359 default: 1360 break; 1361 } 1362 1363 for (i = 0; i < num_xcc; i++) 1364 gfx_v9_4_3_xcc_constants_init(adev, i); 1365 } 1366 1367 static void 1368 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1369 int xcc_id) 1370 { 1371 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1372 } 1373 1374 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1375 { 1376 /* 1377 * Rlc save restore list is workable since v2_1. 1378 */ 1379 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1380 } 1381 1382 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1383 { 1384 uint32_t data; 1385 1386 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1387 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1388 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1389 } 1390 1391 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1392 { 1393 uint32_t rlc_setting; 1394 1395 /* if RLC is not enabled, do nothing */ 1396 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1397 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1398 return false; 1399 1400 return true; 1401 } 1402 1403 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1404 { 1405 uint32_t data; 1406 unsigned i; 1407 1408 data = RLC_SAFE_MODE__CMD_MASK; 1409 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1410 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1411 1412 /* wait for RLC_SAFE_MODE */ 1413 for (i = 0; i < adev->usec_timeout; i++) { 1414 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1415 break; 1416 udelay(1); 1417 } 1418 } 1419 1420 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1421 int xcc_id) 1422 { 1423 uint32_t data; 1424 1425 data = RLC_SAFE_MODE__CMD_MASK; 1426 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1427 } 1428 1429 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1430 { 1431 int xcc_id, num_xcc; 1432 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1433 1434 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1435 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1436 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1437 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1438 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1439 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1440 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1441 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1442 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1443 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1444 } 1445 adev->gfx.rlc.rlcg_reg_access_supported = true; 1446 } 1447 1448 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1449 { 1450 /* init spm vmid with 0xf */ 1451 if (adev->gfx.rlc.funcs->update_spm_vmid) 1452 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1453 1454 return 0; 1455 } 1456 1457 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1458 int xcc_id) 1459 { 1460 u32 i, j, k; 1461 u32 mask; 1462 1463 mutex_lock(&adev->grbm_idx_mutex); 1464 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1465 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1466 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1467 xcc_id); 1468 for (k = 0; k < adev->usec_timeout; k++) { 1469 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1470 break; 1471 udelay(1); 1472 } 1473 if (k == adev->usec_timeout) { 1474 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1475 0xffffffff, 1476 0xffffffff, xcc_id); 1477 mutex_unlock(&adev->grbm_idx_mutex); 1478 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1479 i, j); 1480 return; 1481 } 1482 } 1483 } 1484 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1485 xcc_id); 1486 mutex_unlock(&adev->grbm_idx_mutex); 1487 1488 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1489 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1490 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1491 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1492 for (k = 0; k < adev->usec_timeout; k++) { 1493 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1494 break; 1495 udelay(1); 1496 } 1497 } 1498 1499 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1500 bool enable, int xcc_id) 1501 { 1502 u32 tmp; 1503 1504 /* These interrupts should be enabled to drive DS clock */ 1505 1506 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1507 1508 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1509 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1510 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1511 1512 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1513 } 1514 1515 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1516 { 1517 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1518 RLC_ENABLE_F32, 0); 1519 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1520 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1521 } 1522 1523 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1524 { 1525 int i, num_xcc; 1526 1527 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1528 for (i = 0; i < num_xcc; i++) 1529 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1530 } 1531 1532 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1533 { 1534 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1535 SOFT_RESET_RLC, 1); 1536 udelay(50); 1537 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1538 SOFT_RESET_RLC, 0); 1539 udelay(50); 1540 } 1541 1542 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1543 { 1544 int i, num_xcc; 1545 1546 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1547 for (i = 0; i < num_xcc; i++) 1548 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1549 } 1550 1551 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1552 { 1553 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1554 RLC_ENABLE_F32, 1); 1555 udelay(50); 1556 1557 /* carrizo do enable cp interrupt after cp inited */ 1558 if (!(adev->flags & AMD_IS_APU)) { 1559 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1560 udelay(50); 1561 } 1562 } 1563 1564 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1565 { 1566 #ifdef AMDGPU_RLC_DEBUG_RETRY 1567 u32 rlc_ucode_ver; 1568 #endif 1569 int i, num_xcc; 1570 1571 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1572 for (i = 0; i < num_xcc; i++) { 1573 gfx_v9_4_3_xcc_rlc_start(adev, i); 1574 #ifdef AMDGPU_RLC_DEBUG_RETRY 1575 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1576 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1577 if (rlc_ucode_ver == 0x108) { 1578 dev_info(adev->dev, 1579 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1580 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1581 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1582 * default is 0x9C4 to create a 100us interval */ 1583 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1584 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1585 * to disable the page fault retry interrupts, default is 1586 * 0x100 (256) */ 1587 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1588 } 1589 #endif 1590 } 1591 } 1592 1593 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1594 int xcc_id) 1595 { 1596 const struct rlc_firmware_header_v2_0 *hdr; 1597 const __le32 *fw_data; 1598 unsigned i, fw_size; 1599 1600 if (!adev->gfx.rlc_fw) 1601 return -EINVAL; 1602 1603 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1604 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1605 1606 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1607 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1608 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1609 1610 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1611 RLCG_UCODE_LOADING_START_ADDRESS); 1612 for (i = 0; i < fw_size; i++) { 1613 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1614 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1615 msleep(1); 1616 } 1617 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1618 } 1619 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1620 1621 return 0; 1622 } 1623 1624 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1625 { 1626 int r; 1627 1628 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1629 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1630 /* legacy rlc firmware loading */ 1631 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1632 if (r) 1633 return r; 1634 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1635 } 1636 1637 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1638 /* disable CG */ 1639 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1640 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1641 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1642 1643 return 0; 1644 } 1645 1646 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1647 { 1648 int r, i, num_xcc; 1649 1650 if (amdgpu_sriov_vf(adev)) 1651 return 0; 1652 1653 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1654 for (i = 0; i < num_xcc; i++) { 1655 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1656 if (r) 1657 return r; 1658 } 1659 1660 return 0; 1661 } 1662 1663 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1664 unsigned vmid) 1665 { 1666 u32 reg, pre_data, data; 1667 1668 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1669 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1670 pre_data = RREG32_NO_KIQ(reg); 1671 else 1672 pre_data = RREG32(reg); 1673 1674 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1675 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1676 1677 if (pre_data != data) { 1678 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1679 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1680 } else 1681 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1682 } 1683 } 1684 1685 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1686 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1687 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1688 }; 1689 1690 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1691 uint32_t offset, 1692 struct soc15_reg_rlcg *entries, int arr_size) 1693 { 1694 int i, inst; 1695 uint32_t reg; 1696 1697 if (!entries) 1698 return false; 1699 1700 for (i = 0; i < arr_size; i++) { 1701 const struct soc15_reg_rlcg *entry; 1702 1703 entry = &entries[i]; 1704 inst = adev->ip_map.logical_to_dev_inst ? 1705 adev->ip_map.logical_to_dev_inst( 1706 adev, entry->hwip, entry->instance) : 1707 entry->instance; 1708 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1709 entry->reg; 1710 if (offset == reg) 1711 return true; 1712 } 1713 1714 return false; 1715 } 1716 1717 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1718 { 1719 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1720 (void *)rlcg_access_gc_9_4_3, 1721 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1722 } 1723 1724 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1725 bool enable, int xcc_id) 1726 { 1727 if (enable) { 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1729 } else { 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1731 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1732 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1733 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1734 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1735 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1736 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1737 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1738 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1739 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1740 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1741 } 1742 udelay(50); 1743 } 1744 1745 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1746 int xcc_id) 1747 { 1748 const struct gfx_firmware_header_v1_0 *mec_hdr; 1749 const __le32 *fw_data; 1750 unsigned i; 1751 u32 tmp; 1752 u32 mec_ucode_addr_offset; 1753 u32 mec_ucode_data_offset; 1754 1755 if (!adev->gfx.mec_fw) 1756 return -EINVAL; 1757 1758 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1759 1760 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1761 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1762 1763 fw_data = (const __le32 *) 1764 (adev->gfx.mec_fw->data + 1765 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1766 tmp = 0; 1767 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1768 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1769 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1770 1771 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1772 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1773 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1774 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1775 1776 mec_ucode_addr_offset = 1777 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1778 mec_ucode_data_offset = 1779 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1780 1781 /* MEC1 */ 1782 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1783 for (i = 0; i < mec_hdr->jt_size; i++) 1784 WREG32(mec_ucode_data_offset, 1785 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1786 1787 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1788 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1789 1790 return 0; 1791 } 1792 1793 /* KIQ functions */ 1794 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1795 { 1796 uint32_t tmp; 1797 struct amdgpu_device *adev = ring->adev; 1798 1799 /* tell RLC which is KIQ queue */ 1800 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1801 tmp &= 0xffffff00; 1802 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1803 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1804 } 1805 1806 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1807 { 1808 struct amdgpu_device *adev = ring->adev; 1809 1810 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1811 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1812 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1813 mqd->cp_hqd_queue_priority = 1814 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1815 } 1816 } 1817 } 1818 1819 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1820 { 1821 struct amdgpu_device *adev = ring->adev; 1822 struct v9_mqd *mqd = ring->mqd_ptr; 1823 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1824 uint32_t tmp; 1825 1826 mqd->header = 0xC0310800; 1827 mqd->compute_pipelinestat_enable = 0x00000001; 1828 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1829 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1830 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1831 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1832 mqd->compute_misc_reserved = 0x00000003; 1833 1834 mqd->dynamic_cu_mask_addr_lo = 1835 lower_32_bits(ring->mqd_gpu_addr 1836 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1837 mqd->dynamic_cu_mask_addr_hi = 1838 upper_32_bits(ring->mqd_gpu_addr 1839 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1840 1841 eop_base_addr = ring->eop_gpu_addr >> 8; 1842 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1843 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1844 1845 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1846 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1847 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1848 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1849 1850 mqd->cp_hqd_eop_control = tmp; 1851 1852 /* enable doorbell? */ 1853 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1854 1855 if (ring->use_doorbell) { 1856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1857 DOORBELL_OFFSET, ring->doorbell_index); 1858 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1859 DOORBELL_EN, 1); 1860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1861 DOORBELL_SOURCE, 0); 1862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1863 DOORBELL_HIT, 0); 1864 if (amdgpu_sriov_multi_vf_mode(adev)) 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1866 DOORBELL_MODE, 1); 1867 } else { 1868 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1869 DOORBELL_EN, 0); 1870 } 1871 1872 mqd->cp_hqd_pq_doorbell_control = tmp; 1873 1874 /* disable the queue if it's active */ 1875 ring->wptr = 0; 1876 mqd->cp_hqd_dequeue_request = 0; 1877 mqd->cp_hqd_pq_rptr = 0; 1878 mqd->cp_hqd_pq_wptr_lo = 0; 1879 mqd->cp_hqd_pq_wptr_hi = 0; 1880 1881 /* set the pointer to the MQD */ 1882 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1883 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1884 1885 /* set MQD vmid to 0 */ 1886 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1887 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1888 mqd->cp_mqd_control = tmp; 1889 1890 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1891 hqd_gpu_addr = ring->gpu_addr >> 8; 1892 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1893 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1894 1895 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1896 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1897 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1898 (order_base_2(ring->ring_size / 4) - 1)); 1899 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1900 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1901 #ifdef __BIG_ENDIAN 1902 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1903 #endif 1904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1905 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1907 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1908 mqd->cp_hqd_pq_control = tmp; 1909 1910 /* set the wb address whether it's enabled or not */ 1911 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1912 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1913 mqd->cp_hqd_pq_rptr_report_addr_hi = 1914 upper_32_bits(wb_gpu_addr) & 0xffff; 1915 1916 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1917 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1918 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1919 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1920 1921 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1922 ring->wptr = 0; 1923 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1924 1925 /* set the vmid for the queue */ 1926 mqd->cp_hqd_vmid = 0; 1927 1928 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1929 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1930 mqd->cp_hqd_persistent_state = tmp; 1931 1932 /* set MIN_IB_AVAIL_SIZE */ 1933 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1934 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1935 mqd->cp_hqd_ib_control = tmp; 1936 1937 /* set static priority for a queue/ring */ 1938 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1939 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1940 1941 /* map_queues packet doesn't need activate the queue, 1942 * so only kiq need set this field. 1943 */ 1944 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1945 mqd->cp_hqd_active = 1; 1946 1947 return 0; 1948 } 1949 1950 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1951 int xcc_id) 1952 { 1953 struct amdgpu_device *adev = ring->adev; 1954 struct v9_mqd *mqd = ring->mqd_ptr; 1955 int j; 1956 1957 /* disable wptr polling */ 1958 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1959 1960 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1961 mqd->cp_hqd_eop_base_addr_lo); 1962 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1963 mqd->cp_hqd_eop_base_addr_hi); 1964 1965 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1966 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1967 mqd->cp_hqd_eop_control); 1968 1969 /* enable doorbell? */ 1970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1971 mqd->cp_hqd_pq_doorbell_control); 1972 1973 /* disable the queue if it's active */ 1974 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1975 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1976 for (j = 0; j < adev->usec_timeout; j++) { 1977 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1978 break; 1979 udelay(1); 1980 } 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1982 mqd->cp_hqd_dequeue_request); 1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1984 mqd->cp_hqd_pq_rptr); 1985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1986 mqd->cp_hqd_pq_wptr_lo); 1987 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1988 mqd->cp_hqd_pq_wptr_hi); 1989 } 1990 1991 /* set the pointer to the MQD */ 1992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1993 mqd->cp_mqd_base_addr_lo); 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1995 mqd->cp_mqd_base_addr_hi); 1996 1997 /* set MQD vmid to 0 */ 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1999 mqd->cp_mqd_control); 2000 2001 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2002 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2003 mqd->cp_hqd_pq_base_lo); 2004 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2005 mqd->cp_hqd_pq_base_hi); 2006 2007 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2008 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2009 mqd->cp_hqd_pq_control); 2010 2011 /* set the wb address whether it's enabled or not */ 2012 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2013 mqd->cp_hqd_pq_rptr_report_addr_lo); 2014 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2015 mqd->cp_hqd_pq_rptr_report_addr_hi); 2016 2017 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2018 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2019 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2020 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2021 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2022 2023 /* enable the doorbell if requested */ 2024 if (ring->use_doorbell) { 2025 WREG32_SOC15( 2026 GC, GET_INST(GC, xcc_id), 2027 regCP_MEC_DOORBELL_RANGE_LOWER, 2028 ((adev->doorbell_index.kiq + 2029 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2030 2) << 2); 2031 WREG32_SOC15( 2032 GC, GET_INST(GC, xcc_id), 2033 regCP_MEC_DOORBELL_RANGE_UPPER, 2034 ((adev->doorbell_index.userqueue_end + 2035 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2036 2) << 2); 2037 } 2038 2039 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2040 mqd->cp_hqd_pq_doorbell_control); 2041 2042 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2043 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2044 mqd->cp_hqd_pq_wptr_lo); 2045 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2046 mqd->cp_hqd_pq_wptr_hi); 2047 2048 /* set the vmid for the queue */ 2049 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2050 2051 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2052 mqd->cp_hqd_persistent_state); 2053 2054 /* activate the queue */ 2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2056 mqd->cp_hqd_active); 2057 2058 if (ring->use_doorbell) 2059 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2060 2061 return 0; 2062 } 2063 2064 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2065 int xcc_id) 2066 { 2067 struct amdgpu_device *adev = ring->adev; 2068 int j; 2069 2070 /* disable the queue if it's active */ 2071 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2072 2073 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2074 2075 for (j = 0; j < adev->usec_timeout; j++) { 2076 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2077 break; 2078 udelay(1); 2079 } 2080 2081 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2082 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2083 2084 /* Manual disable if dequeue request times out */ 2085 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2086 } 2087 2088 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2089 0); 2090 } 2091 2092 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2093 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2094 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2095 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2096 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2097 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2098 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2100 2101 return 0; 2102 } 2103 2104 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2105 { 2106 struct amdgpu_device *adev = ring->adev; 2107 struct v9_mqd *mqd = ring->mqd_ptr; 2108 struct v9_mqd *tmp_mqd; 2109 2110 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2111 2112 /* GPU could be in bad state during probe, driver trigger the reset 2113 * after load the SMU, in this case , the mqd is not be initialized. 2114 * driver need to re-init the mqd. 2115 * check mqd->cp_hqd_pq_control since this value should not be 0 2116 */ 2117 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2118 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2119 /* for GPU_RESET case , reset MQD to a clean status */ 2120 if (adev->gfx.kiq[xcc_id].mqd_backup) 2121 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2122 2123 /* reset ring buffer */ 2124 ring->wptr = 0; 2125 amdgpu_ring_clear_ring(ring); 2126 mutex_lock(&adev->srbm_mutex); 2127 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2128 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2129 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2130 mutex_unlock(&adev->srbm_mutex); 2131 } else { 2132 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2133 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2134 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2135 mutex_lock(&adev->srbm_mutex); 2136 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2137 amdgpu_ring_clear_ring(ring); 2138 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2139 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2140 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2141 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2142 mutex_unlock(&adev->srbm_mutex); 2143 2144 if (adev->gfx.kiq[xcc_id].mqd_backup) 2145 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2146 } 2147 2148 return 0; 2149 } 2150 2151 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2152 { 2153 struct amdgpu_device *adev = ring->adev; 2154 struct v9_mqd *mqd = ring->mqd_ptr; 2155 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2156 struct v9_mqd *tmp_mqd; 2157 2158 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2159 * is not be initialized before 2160 */ 2161 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2162 2163 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2164 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2165 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2166 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2167 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2168 mutex_lock(&adev->srbm_mutex); 2169 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2170 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2171 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2172 mutex_unlock(&adev->srbm_mutex); 2173 2174 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2175 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2176 } else { 2177 /* restore MQD to a clean status */ 2178 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2179 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2180 /* reset ring buffer */ 2181 ring->wptr = 0; 2182 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2183 amdgpu_ring_clear_ring(ring); 2184 } 2185 2186 return 0; 2187 } 2188 2189 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2190 { 2191 struct amdgpu_ring *ring; 2192 int j; 2193 2194 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2195 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2196 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2197 mutex_lock(&adev->srbm_mutex); 2198 soc15_grbm_select(adev, ring->me, 2199 ring->pipe, 2200 ring->queue, 0, GET_INST(GC, xcc_id)); 2201 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2202 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2203 mutex_unlock(&adev->srbm_mutex); 2204 } 2205 } 2206 2207 return 0; 2208 } 2209 2210 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2211 { 2212 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2213 return 0; 2214 } 2215 2216 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2217 { 2218 struct amdgpu_ring *ring; 2219 int i, r; 2220 2221 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2222 2223 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2224 ring = &adev->gfx.compute_ring[i + xcc_id * 2225 adev->gfx.num_compute_rings]; 2226 2227 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2228 if (r) 2229 return r; 2230 } 2231 2232 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2233 } 2234 2235 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2236 { 2237 struct amdgpu_ring *ring; 2238 int r, j; 2239 2240 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2241 2242 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2243 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2244 2245 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2246 if (r) 2247 return r; 2248 } else { 2249 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2250 } 2251 2252 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2253 if (r) 2254 return r; 2255 2256 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2257 if (r) 2258 return r; 2259 2260 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2261 ring = &adev->gfx.compute_ring 2262 [j + xcc_id * adev->gfx.num_compute_rings]; 2263 r = amdgpu_ring_test_helper(ring); 2264 if (r) 2265 return r; 2266 } 2267 2268 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2269 2270 return 0; 2271 } 2272 2273 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2274 { 2275 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2276 2277 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2278 if (amdgpu_sriov_vf(adev)) { 2279 enum amdgpu_gfx_partition mode; 2280 2281 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2282 AMDGPU_XCP_FL_NONE); 2283 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2284 return -EINVAL; 2285 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2286 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2287 num_xcp = num_xcc / num_xcc_per_xcp; 2288 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2289 2290 } else { 2291 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2292 AMDGPU_XCP_FL_NONE) == 2293 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2294 r = amdgpu_xcp_switch_partition_mode( 2295 adev->xcp_mgr, amdgpu_user_partt_mode); 2296 } 2297 if (r) 2298 return r; 2299 2300 for (i = 0; i < num_xcc; i++) { 2301 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2302 if (r) 2303 return r; 2304 } 2305 2306 return 0; 2307 } 2308 2309 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2310 { 2311 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2312 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2313 2314 if (amdgpu_sriov_vf(adev)) { 2315 /* must disable polling for SRIOV when hw finished, otherwise 2316 * CPC engine may still keep fetching WB address which is already 2317 * invalid after sw finished and trigger DMAR reading error in 2318 * hypervisor side. 2319 */ 2320 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2321 return; 2322 } 2323 2324 /* Use deinitialize sequence from CAIL when unbinding device 2325 * from driver, otherwise KIQ is hanging when binding back 2326 */ 2327 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2328 mutex_lock(&adev->srbm_mutex); 2329 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2330 adev->gfx.kiq[xcc_id].ring.pipe, 2331 adev->gfx.kiq[xcc_id].ring.queue, 0, 2332 GET_INST(GC, xcc_id)); 2333 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2334 xcc_id); 2335 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2336 mutex_unlock(&adev->srbm_mutex); 2337 } 2338 2339 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2340 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2341 } 2342 2343 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2344 { 2345 int r; 2346 struct amdgpu_device *adev = ip_block->adev; 2347 2348 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2349 adev->gfx.cleaner_shader_ptr); 2350 2351 if (!amdgpu_sriov_vf(adev)) 2352 gfx_v9_4_3_init_golden_registers(adev); 2353 2354 gfx_v9_4_3_constants_init(adev); 2355 2356 r = adev->gfx.rlc.funcs->resume(adev); 2357 if (r) 2358 return r; 2359 2360 r = gfx_v9_4_3_cp_resume(adev); 2361 if (r) 2362 return r; 2363 2364 return r; 2365 } 2366 2367 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2368 { 2369 struct amdgpu_device *adev = ip_block->adev; 2370 int i, num_xcc; 2371 2372 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2373 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2374 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2375 2376 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2377 for (i = 0; i < num_xcc; i++) { 2378 gfx_v9_4_3_xcc_fini(adev, i); 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2385 { 2386 return gfx_v9_4_3_hw_fini(ip_block); 2387 } 2388 2389 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2390 { 2391 return gfx_v9_4_3_hw_init(ip_block); 2392 } 2393 2394 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2395 { 2396 struct amdgpu_device *adev = ip_block->adev; 2397 int i, num_xcc; 2398 2399 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2400 for (i = 0; i < num_xcc; i++) { 2401 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2402 GRBM_STATUS, GUI_ACTIVE)) 2403 return false; 2404 } 2405 return true; 2406 } 2407 2408 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2409 { 2410 unsigned i; 2411 struct amdgpu_device *adev = ip_block->adev; 2412 2413 for (i = 0; i < adev->usec_timeout; i++) { 2414 if (gfx_v9_4_3_is_idle(ip_block)) 2415 return 0; 2416 udelay(1); 2417 } 2418 return -ETIMEDOUT; 2419 } 2420 2421 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2422 { 2423 u32 grbm_soft_reset = 0; 2424 u32 tmp; 2425 struct amdgpu_device *adev = ip_block->adev; 2426 2427 /* GRBM_STATUS */ 2428 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2429 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2430 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2431 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2432 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2433 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2434 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2435 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2436 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2437 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2438 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2439 } 2440 2441 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2442 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2443 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2444 } 2445 2446 /* GRBM_STATUS2 */ 2447 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2448 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2449 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2450 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2451 2452 2453 if (grbm_soft_reset) { 2454 /* stop the rlc */ 2455 adev->gfx.rlc.funcs->stop(adev); 2456 2457 /* Disable MEC parsing/prefetching */ 2458 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2459 2460 if (grbm_soft_reset) { 2461 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2462 tmp |= grbm_soft_reset; 2463 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2464 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2465 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2466 2467 udelay(50); 2468 2469 tmp &= ~grbm_soft_reset; 2470 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2471 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2472 } 2473 2474 /* Wait a little for things to settle down */ 2475 udelay(50); 2476 } 2477 return 0; 2478 } 2479 2480 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2481 uint32_t vmid, 2482 uint32_t gds_base, uint32_t gds_size, 2483 uint32_t gws_base, uint32_t gws_size, 2484 uint32_t oa_base, uint32_t oa_size) 2485 { 2486 struct amdgpu_device *adev = ring->adev; 2487 2488 /* GDS Base */ 2489 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2490 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2491 gds_base); 2492 2493 /* GDS Size */ 2494 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2495 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2496 gds_size); 2497 2498 /* GWS */ 2499 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2500 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2501 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2502 2503 /* OA */ 2504 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2505 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2506 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2507 } 2508 2509 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2510 { 2511 struct amdgpu_device *adev = ip_block->adev; 2512 2513 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2514 AMDGPU_MAX_COMPUTE_RINGS); 2515 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2516 gfx_v9_4_3_set_ring_funcs(adev); 2517 gfx_v9_4_3_set_irq_funcs(adev); 2518 gfx_v9_4_3_set_gds_init(adev); 2519 gfx_v9_4_3_set_rlc_funcs(adev); 2520 2521 /* init rlcg reg access ctrl */ 2522 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2523 2524 return gfx_v9_4_3_init_microcode(adev); 2525 } 2526 2527 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2528 { 2529 struct amdgpu_device *adev = ip_block->adev; 2530 int r; 2531 2532 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2533 if (r) 2534 return r; 2535 2536 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2537 if (r) 2538 return r; 2539 2540 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2541 if (r) 2542 return r; 2543 2544 if (adev->gfx.ras && 2545 adev->gfx.ras->enable_watchdog_timer) 2546 adev->gfx.ras->enable_watchdog_timer(adev); 2547 2548 return 0; 2549 } 2550 2551 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2552 bool enable, int xcc_id) 2553 { 2554 uint32_t def, data; 2555 2556 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2557 return; 2558 2559 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2560 regRLC_CGTT_MGCG_OVERRIDE); 2561 2562 if (enable) 2563 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2564 else 2565 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2566 2567 if (def != data) 2568 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2569 regRLC_CGTT_MGCG_OVERRIDE, data); 2570 2571 } 2572 2573 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2574 bool enable, int xcc_id) 2575 { 2576 uint32_t def, data; 2577 2578 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2579 return; 2580 2581 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2582 regRLC_CGTT_MGCG_OVERRIDE); 2583 2584 if (enable) 2585 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2586 else 2587 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2588 2589 if (def != data) 2590 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2591 regRLC_CGTT_MGCG_OVERRIDE, data); 2592 } 2593 2594 static void 2595 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2596 bool enable, int xcc_id) 2597 { 2598 uint32_t data, def; 2599 2600 /* It is disabled by HW by default */ 2601 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2602 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2603 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2604 2605 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2606 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2607 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2608 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2609 2610 if (def != data) 2611 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2612 2613 /* MGLS is a global flag to control all MGLS in GFX */ 2614 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2615 /* 2 - RLC memory Light sleep */ 2616 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2617 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2618 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2619 if (def != data) 2620 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2621 } 2622 /* 3 - CP memory Light sleep */ 2623 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2624 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2625 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2626 if (def != data) 2627 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2628 } 2629 } 2630 } else { 2631 /* 1 - MGCG_OVERRIDE */ 2632 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2633 2634 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2635 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2636 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2637 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2638 2639 if (def != data) 2640 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2641 2642 /* 2 - disable MGLS in RLC */ 2643 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2644 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2645 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2647 } 2648 2649 /* 3 - disable MGLS in CP */ 2650 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2651 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2652 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2653 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2654 } 2655 } 2656 2657 } 2658 2659 static void 2660 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2661 bool enable, int xcc_id) 2662 { 2663 uint32_t def, data; 2664 2665 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2666 2667 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2668 /* unset CGCG override */ 2669 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2670 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2672 else 2673 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2674 /* update CGCG and CGLS override bits */ 2675 if (def != data) 2676 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2677 2678 /* CGCG Hysteresis: 400us */ 2679 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2680 2681 data = (0x2710 2682 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2683 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2684 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2685 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2686 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2687 if (def != data) 2688 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2689 2690 /* set IDLE_POLL_COUNT(0x33450100)*/ 2691 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2692 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2693 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2694 if (def != data) 2695 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2696 } else { 2697 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2698 /* reset CGCG/CGLS bits */ 2699 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2700 /* disable cgcg and cgls in FSM */ 2701 if (def != data) 2702 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2703 } 2704 2705 } 2706 2707 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2708 bool enable, int xcc_id) 2709 { 2710 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2711 2712 if (enable) { 2713 /* FGCG */ 2714 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2715 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2716 2717 /* CGCG/CGLS should be enabled after MGCG/MGLS 2718 * === MGCG + MGLS === 2719 */ 2720 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2721 xcc_id); 2722 /* === CGCG + CGLS === */ 2723 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2724 xcc_id); 2725 } else { 2726 /* CGCG/CGLS should be disabled before MGCG/MGLS 2727 * === CGCG + CGLS === 2728 */ 2729 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2730 xcc_id); 2731 /* === MGCG + MGLS === */ 2732 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2733 xcc_id); 2734 2735 /* FGCG */ 2736 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2737 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2738 } 2739 2740 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2741 2742 return 0; 2743 } 2744 2745 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2746 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2747 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2748 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2749 .init = gfx_v9_4_3_rlc_init, 2750 .resume = gfx_v9_4_3_rlc_resume, 2751 .stop = gfx_v9_4_3_rlc_stop, 2752 .reset = gfx_v9_4_3_rlc_reset, 2753 .start = gfx_v9_4_3_rlc_start, 2754 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2755 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2756 }; 2757 2758 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2759 enum amd_powergating_state state) 2760 { 2761 return 0; 2762 } 2763 2764 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2765 enum amd_clockgating_state state) 2766 { 2767 struct amdgpu_device *adev = ip_block->adev; 2768 int i, num_xcc; 2769 2770 if (amdgpu_sriov_vf(adev)) 2771 return 0; 2772 2773 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2774 for (i = 0; i < num_xcc; i++) 2775 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2776 adev, state == AMD_CG_STATE_GATE, i); 2777 2778 return 0; 2779 } 2780 2781 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2782 { 2783 struct amdgpu_device *adev = ip_block->adev; 2784 int data; 2785 2786 if (amdgpu_sriov_vf(adev)) 2787 *flags = 0; 2788 2789 /* AMD_CG_SUPPORT_GFX_MGCG */ 2790 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2791 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2792 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2793 2794 /* AMD_CG_SUPPORT_GFX_CGCG */ 2795 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2796 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2797 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2798 2799 /* AMD_CG_SUPPORT_GFX_CGLS */ 2800 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2801 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2802 2803 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2804 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2805 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2806 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2807 2808 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2809 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2810 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2811 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2812 } 2813 2814 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2815 { 2816 struct amdgpu_device *adev = ring->adev; 2817 u32 ref_and_mask, reg_mem_engine; 2818 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2819 2820 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2821 switch (ring->me) { 2822 case 1: 2823 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2824 break; 2825 case 2: 2826 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2827 break; 2828 default: 2829 return; 2830 } 2831 reg_mem_engine = 0; 2832 } else { 2833 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2834 reg_mem_engine = 1; /* pfp */ 2835 } 2836 2837 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2838 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2839 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2840 ref_and_mask, ref_and_mask, 0x20); 2841 } 2842 2843 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2844 struct amdgpu_job *job, 2845 struct amdgpu_ib *ib, 2846 uint32_t flags) 2847 { 2848 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2849 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2850 2851 /* Currently, there is a high possibility to get wave ID mismatch 2852 * between ME and GDS, leading to a hw deadlock, because ME generates 2853 * different wave IDs than the GDS expects. This situation happens 2854 * randomly when at least 5 compute pipes use GDS ordered append. 2855 * The wave IDs generated by ME are also wrong after suspend/resume. 2856 * Those are probably bugs somewhere else in the kernel driver. 2857 * 2858 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2859 * GDS to 0 for this ring (me/pipe). 2860 */ 2861 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2862 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2863 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2864 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2865 } 2866 2867 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2868 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2869 amdgpu_ring_write(ring, 2870 #ifdef __BIG_ENDIAN 2871 (2 << 0) | 2872 #endif 2873 lower_32_bits(ib->gpu_addr)); 2874 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2875 amdgpu_ring_write(ring, control); 2876 } 2877 2878 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2879 u64 seq, unsigned flags) 2880 { 2881 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2882 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2883 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2884 2885 /* RELEASE_MEM - flush caches, send int */ 2886 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2887 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2888 EOP_TC_NC_ACTION_EN) : 2889 (EOP_TCL1_ACTION_EN | 2890 EOP_TC_ACTION_EN | 2891 EOP_TC_WB_ACTION_EN | 2892 EOP_TC_MD_ACTION_EN)) | 2893 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2894 EVENT_INDEX(5))); 2895 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2896 2897 /* 2898 * the address should be Qword aligned if 64bit write, Dword 2899 * aligned if only send 32bit data low (discard data high) 2900 */ 2901 if (write64bit) 2902 BUG_ON(addr & 0x7); 2903 else 2904 BUG_ON(addr & 0x3); 2905 amdgpu_ring_write(ring, lower_32_bits(addr)); 2906 amdgpu_ring_write(ring, upper_32_bits(addr)); 2907 amdgpu_ring_write(ring, lower_32_bits(seq)); 2908 amdgpu_ring_write(ring, upper_32_bits(seq)); 2909 amdgpu_ring_write(ring, 0); 2910 } 2911 2912 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2913 { 2914 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2915 uint32_t seq = ring->fence_drv.sync_seq; 2916 uint64_t addr = ring->fence_drv.gpu_addr; 2917 2918 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2919 lower_32_bits(addr), upper_32_bits(addr), 2920 seq, 0xffffffff, 4); 2921 } 2922 2923 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2924 unsigned vmid, uint64_t pd_addr) 2925 { 2926 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2927 } 2928 2929 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2930 { 2931 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2932 } 2933 2934 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2935 { 2936 u64 wptr; 2937 2938 /* XXX check if swapping is necessary on BE */ 2939 if (ring->use_doorbell) 2940 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2941 else 2942 BUG(); 2943 return wptr; 2944 } 2945 2946 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2947 { 2948 struct amdgpu_device *adev = ring->adev; 2949 2950 /* XXX check if swapping is necessary on BE */ 2951 if (ring->use_doorbell) { 2952 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2953 WDOORBELL64(ring->doorbell_index, ring->wptr); 2954 } else { 2955 BUG(); /* only DOORBELL method supported on gfx9 now */ 2956 } 2957 } 2958 2959 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2960 u64 seq, unsigned int flags) 2961 { 2962 struct amdgpu_device *adev = ring->adev; 2963 2964 /* we only allocate 32bit for each seq wb address */ 2965 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2966 2967 /* write fence seq to the "addr" */ 2968 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2969 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2970 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2971 amdgpu_ring_write(ring, lower_32_bits(addr)); 2972 amdgpu_ring_write(ring, upper_32_bits(addr)); 2973 amdgpu_ring_write(ring, lower_32_bits(seq)); 2974 2975 if (flags & AMDGPU_FENCE_FLAG_INT) { 2976 /* set register to trigger INT */ 2977 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2978 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2979 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2980 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2981 amdgpu_ring_write(ring, 0); 2982 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2983 } 2984 } 2985 2986 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2987 uint32_t reg_val_offs) 2988 { 2989 struct amdgpu_device *adev = ring->adev; 2990 2991 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2992 2993 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2994 amdgpu_ring_write(ring, 0 | /* src: register*/ 2995 (5 << 8) | /* dst: memory */ 2996 (1 << 20)); /* write confirm */ 2997 amdgpu_ring_write(ring, reg); 2998 amdgpu_ring_write(ring, 0); 2999 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3000 reg_val_offs * 4)); 3001 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3002 reg_val_offs * 4)); 3003 } 3004 3005 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3006 uint32_t val) 3007 { 3008 uint32_t cmd = 0; 3009 3010 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3011 3012 switch (ring->funcs->type) { 3013 case AMDGPU_RING_TYPE_GFX: 3014 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3015 break; 3016 case AMDGPU_RING_TYPE_KIQ: 3017 cmd = (1 << 16); /* no inc addr */ 3018 break; 3019 default: 3020 cmd = WR_CONFIRM; 3021 break; 3022 } 3023 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3024 amdgpu_ring_write(ring, cmd); 3025 amdgpu_ring_write(ring, reg); 3026 amdgpu_ring_write(ring, 0); 3027 amdgpu_ring_write(ring, val); 3028 } 3029 3030 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3031 uint32_t val, uint32_t mask) 3032 { 3033 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3034 } 3035 3036 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3037 uint32_t reg0, uint32_t reg1, 3038 uint32_t ref, uint32_t mask) 3039 { 3040 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3041 ref, mask); 3042 } 3043 3044 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3045 unsigned vmid) 3046 { 3047 struct amdgpu_device *adev = ring->adev; 3048 uint32_t value = 0; 3049 3050 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3051 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3052 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3053 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3054 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3055 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3056 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3057 } 3058 3059 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3060 struct amdgpu_device *adev, int me, int pipe, 3061 enum amdgpu_interrupt_state state, int xcc_id) 3062 { 3063 u32 mec_int_cntl, mec_int_cntl_reg; 3064 3065 /* 3066 * amdgpu controls only the first MEC. That's why this function only 3067 * handles the setting of interrupts for this specific MEC. All other 3068 * pipes' interrupts are set by amdkfd. 3069 */ 3070 3071 if (me == 1) { 3072 switch (pipe) { 3073 case 0: 3074 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3075 break; 3076 case 1: 3077 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3078 break; 3079 case 2: 3080 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3081 break; 3082 case 3: 3083 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3084 break; 3085 default: 3086 DRM_DEBUG("invalid pipe %d\n", pipe); 3087 return; 3088 } 3089 } else { 3090 DRM_DEBUG("invalid me %d\n", me); 3091 return; 3092 } 3093 3094 switch (state) { 3095 case AMDGPU_IRQ_STATE_DISABLE: 3096 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3097 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3098 TIME_STAMP_INT_ENABLE, 0); 3099 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3100 break; 3101 case AMDGPU_IRQ_STATE_ENABLE: 3102 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3103 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3104 TIME_STAMP_INT_ENABLE, 1); 3105 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3106 break; 3107 default: 3108 break; 3109 } 3110 } 3111 3112 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3113 int xcc_id, int me, int pipe) 3114 { 3115 /* 3116 * amdgpu controls only the first MEC. That's why this function only 3117 * handles the setting of interrupts for this specific MEC. All other 3118 * pipes' interrupts are set by amdkfd. 3119 */ 3120 if (me != 1) 3121 return 0; 3122 3123 switch (pipe) { 3124 case 0: 3125 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3126 case 1: 3127 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3128 case 2: 3129 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3130 case 3: 3131 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3132 default: 3133 return 0; 3134 } 3135 } 3136 3137 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3138 struct amdgpu_irq_src *source, 3139 unsigned type, 3140 enum amdgpu_interrupt_state state) 3141 { 3142 u32 mec_int_cntl_reg, mec_int_cntl; 3143 int i, j, k, num_xcc; 3144 3145 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3146 switch (state) { 3147 case AMDGPU_IRQ_STATE_DISABLE: 3148 case AMDGPU_IRQ_STATE_ENABLE: 3149 for (i = 0; i < num_xcc; i++) { 3150 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3151 PRIV_REG_INT_ENABLE, 3152 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3153 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3154 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3155 /* MECs start at 1 */ 3156 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3157 3158 if (mec_int_cntl_reg) { 3159 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3160 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3161 PRIV_REG_INT_ENABLE, 3162 state == AMDGPU_IRQ_STATE_ENABLE ? 3163 1 : 0); 3164 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3165 } 3166 } 3167 } 3168 } 3169 break; 3170 default: 3171 break; 3172 } 3173 3174 return 0; 3175 } 3176 3177 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3178 struct amdgpu_irq_src *source, 3179 unsigned type, 3180 enum amdgpu_interrupt_state state) 3181 { 3182 u32 mec_int_cntl_reg, mec_int_cntl; 3183 int i, j, k, num_xcc; 3184 3185 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3186 switch (state) { 3187 case AMDGPU_IRQ_STATE_DISABLE: 3188 case AMDGPU_IRQ_STATE_ENABLE: 3189 for (i = 0; i < num_xcc; i++) { 3190 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3191 OPCODE_ERROR_INT_ENABLE, 3192 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3193 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3194 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3195 /* MECs start at 1 */ 3196 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3197 3198 if (mec_int_cntl_reg) { 3199 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3200 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3201 OPCODE_ERROR_INT_ENABLE, 3202 state == AMDGPU_IRQ_STATE_ENABLE ? 3203 1 : 0); 3204 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3205 } 3206 } 3207 } 3208 } 3209 break; 3210 default: 3211 break; 3212 } 3213 3214 return 0; 3215 } 3216 3217 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3218 struct amdgpu_irq_src *source, 3219 unsigned type, 3220 enum amdgpu_interrupt_state state) 3221 { 3222 int i, num_xcc; 3223 3224 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3225 switch (state) { 3226 case AMDGPU_IRQ_STATE_DISABLE: 3227 case AMDGPU_IRQ_STATE_ENABLE: 3228 for (i = 0; i < num_xcc; i++) 3229 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3230 PRIV_INSTR_INT_ENABLE, 3231 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3232 break; 3233 default: 3234 break; 3235 } 3236 3237 return 0; 3238 } 3239 3240 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3241 struct amdgpu_irq_src *src, 3242 unsigned type, 3243 enum amdgpu_interrupt_state state) 3244 { 3245 int i, num_xcc; 3246 3247 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3248 for (i = 0; i < num_xcc; i++) { 3249 switch (type) { 3250 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3251 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3252 adev, 1, 0, state, i); 3253 break; 3254 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3255 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3256 adev, 1, 1, state, i); 3257 break; 3258 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3259 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3260 adev, 1, 2, state, i); 3261 break; 3262 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3263 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3264 adev, 1, 3, state, i); 3265 break; 3266 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3267 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3268 adev, 2, 0, state, i); 3269 break; 3270 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3271 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3272 adev, 2, 1, state, i); 3273 break; 3274 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3275 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3276 adev, 2, 2, state, i); 3277 break; 3278 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3279 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3280 adev, 2, 3, state, i); 3281 break; 3282 default: 3283 break; 3284 } 3285 } 3286 3287 return 0; 3288 } 3289 3290 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3291 struct amdgpu_irq_src *source, 3292 struct amdgpu_iv_entry *entry) 3293 { 3294 int i, xcc_id; 3295 u8 me_id, pipe_id, queue_id; 3296 struct amdgpu_ring *ring; 3297 3298 DRM_DEBUG("IH: CP EOP\n"); 3299 me_id = (entry->ring_id & 0x0c) >> 2; 3300 pipe_id = (entry->ring_id & 0x03) >> 0; 3301 queue_id = (entry->ring_id & 0x70) >> 4; 3302 3303 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3304 3305 if (xcc_id == -EINVAL) 3306 return -EINVAL; 3307 3308 switch (me_id) { 3309 case 0: 3310 case 1: 3311 case 2: 3312 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3313 ring = &adev->gfx.compute_ring 3314 [i + 3315 xcc_id * adev->gfx.num_compute_rings]; 3316 /* Per-queue interrupt is supported for MEC starting from VI. 3317 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3318 */ 3319 3320 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3321 amdgpu_fence_process(ring); 3322 } 3323 break; 3324 } 3325 return 0; 3326 } 3327 3328 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3329 struct amdgpu_iv_entry *entry) 3330 { 3331 u8 me_id, pipe_id, queue_id; 3332 struct amdgpu_ring *ring; 3333 int i, xcc_id; 3334 3335 me_id = (entry->ring_id & 0x0c) >> 2; 3336 pipe_id = (entry->ring_id & 0x03) >> 0; 3337 queue_id = (entry->ring_id & 0x70) >> 4; 3338 3339 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3340 3341 if (xcc_id == -EINVAL) 3342 return; 3343 3344 switch (me_id) { 3345 case 0: 3346 case 1: 3347 case 2: 3348 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3349 ring = &adev->gfx.compute_ring 3350 [i + 3351 xcc_id * adev->gfx.num_compute_rings]; 3352 if (ring->me == me_id && ring->pipe == pipe_id && 3353 ring->queue == queue_id) 3354 drm_sched_fault(&ring->sched); 3355 } 3356 break; 3357 } 3358 } 3359 3360 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3361 struct amdgpu_irq_src *source, 3362 struct amdgpu_iv_entry *entry) 3363 { 3364 DRM_ERROR("Illegal register access in command stream\n"); 3365 gfx_v9_4_3_fault(adev, entry); 3366 return 0; 3367 } 3368 3369 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3370 struct amdgpu_irq_src *source, 3371 struct amdgpu_iv_entry *entry) 3372 { 3373 DRM_ERROR("Illegal opcode in command stream\n"); 3374 gfx_v9_4_3_fault(adev, entry); 3375 return 0; 3376 } 3377 3378 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3379 struct amdgpu_irq_src *source, 3380 struct amdgpu_iv_entry *entry) 3381 { 3382 DRM_ERROR("Illegal instruction in command stream\n"); 3383 gfx_v9_4_3_fault(adev, entry); 3384 return 0; 3385 } 3386 3387 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3388 { 3389 const unsigned int cp_coher_cntl = 3390 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3391 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3392 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3393 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3394 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3395 3396 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3397 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3398 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3399 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3400 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3401 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3402 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3403 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3404 } 3405 3406 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3407 uint32_t pipe, bool enable) 3408 { 3409 struct amdgpu_device *adev = ring->adev; 3410 uint32_t val; 3411 uint32_t wcl_cs_reg; 3412 3413 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3414 val = enable ? 0x1 : 0x7f; 3415 3416 switch (pipe) { 3417 case 0: 3418 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3419 break; 3420 case 1: 3421 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3422 break; 3423 case 2: 3424 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3425 break; 3426 case 3: 3427 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3428 break; 3429 default: 3430 DRM_DEBUG("invalid pipe %d\n", pipe); 3431 return; 3432 } 3433 3434 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3435 3436 } 3437 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3438 { 3439 struct amdgpu_device *adev = ring->adev; 3440 uint32_t val; 3441 int i; 3442 3443 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3444 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3445 * around 25% of gpu resources. 3446 */ 3447 val = enable ? 0x1f : 0x07ffffff; 3448 amdgpu_ring_emit_wreg(ring, 3449 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3450 val); 3451 3452 /* Restrict waves for normal/low priority compute queues as well 3453 * to get best QoS for high priority compute jobs. 3454 * 3455 * amdgpu controls only 1st ME(0-3 CS pipes). 3456 */ 3457 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3458 if (i != ring->pipe) 3459 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3460 3461 } 3462 } 3463 3464 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3465 uint32_t pipe, uint32_t queue, 3466 uint32_t xcc_id) 3467 { 3468 int i, r; 3469 /* make sure dequeue is complete*/ 3470 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3471 mutex_lock(&adev->srbm_mutex); 3472 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3473 for (i = 0; i < adev->usec_timeout; i++) { 3474 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3475 break; 3476 udelay(1); 3477 } 3478 if (i >= adev->usec_timeout) 3479 r = -ETIMEDOUT; 3480 else 3481 r = 0; 3482 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3483 mutex_unlock(&adev->srbm_mutex); 3484 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3485 3486 return r; 3487 3488 } 3489 3490 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3491 { 3492 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3493 return true; 3494 else 3495 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3496 3497 return false; 3498 } 3499 3500 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3501 { 3502 struct amdgpu_device *adev = ring->adev; 3503 uint32_t reset_pipe, clean_pipe; 3504 int r; 3505 3506 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3507 return -EINVAL; 3508 3509 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3510 mutex_lock(&adev->srbm_mutex); 3511 3512 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3513 clean_pipe = reset_pipe; 3514 3515 if (ring->me == 1) { 3516 switch (ring->pipe) { 3517 case 0: 3518 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3519 MEC_ME1_PIPE0_RESET, 1); 3520 break; 3521 case 1: 3522 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3523 MEC_ME1_PIPE1_RESET, 1); 3524 break; 3525 case 2: 3526 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3527 MEC_ME1_PIPE2_RESET, 1); 3528 break; 3529 case 3: 3530 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3531 MEC_ME1_PIPE3_RESET, 1); 3532 break; 3533 default: 3534 break; 3535 } 3536 } else { 3537 if (ring->pipe) 3538 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3539 MEC_ME2_PIPE1_RESET, 1); 3540 else 3541 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3542 MEC_ME2_PIPE0_RESET, 1); 3543 } 3544 3545 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3546 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3547 mutex_unlock(&adev->srbm_mutex); 3548 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3549 3550 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3551 return r; 3552 } 3553 3554 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3555 unsigned int vmid) 3556 { 3557 struct amdgpu_device *adev = ring->adev; 3558 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3559 struct amdgpu_ring *kiq_ring = &kiq->ring; 3560 unsigned long flags; 3561 int r; 3562 3563 if (amdgpu_sriov_vf(adev)) 3564 return -EINVAL; 3565 3566 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3567 return -EINVAL; 3568 3569 spin_lock_irqsave(&kiq->ring_lock, flags); 3570 3571 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3572 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3573 return -ENOMEM; 3574 } 3575 3576 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3577 0, 0); 3578 amdgpu_ring_commit(kiq_ring); 3579 3580 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3581 3582 r = amdgpu_ring_test_ring(kiq_ring); 3583 if (r) { 3584 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3585 ring->name); 3586 goto pipe_reset; 3587 } 3588 3589 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3590 if (r) 3591 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3592 3593 pipe_reset: 3594 if(r) { 3595 r = gfx_v9_4_3_reset_hw_pipe(ring); 3596 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3597 r ? "failed" : "successfully"); 3598 if (r) 3599 return r; 3600 } 3601 3602 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3603 if (r) { 3604 dev_err(adev->dev, "fail to init kcq\n"); 3605 return r; 3606 } 3607 spin_lock_irqsave(&kiq->ring_lock, flags); 3608 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3609 if (r) { 3610 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3611 return -ENOMEM; 3612 } 3613 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3614 amdgpu_ring_commit(kiq_ring); 3615 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3616 3617 r = amdgpu_ring_test_ring(kiq_ring); 3618 if (r) { 3619 dev_err(adev->dev, "fail to remap queue\n"); 3620 return r; 3621 } 3622 return amdgpu_ring_test_ring(ring); 3623 } 3624 3625 enum amdgpu_gfx_cp_ras_mem_id { 3626 AMDGPU_GFX_CP_MEM1 = 1, 3627 AMDGPU_GFX_CP_MEM2, 3628 AMDGPU_GFX_CP_MEM3, 3629 AMDGPU_GFX_CP_MEM4, 3630 AMDGPU_GFX_CP_MEM5, 3631 }; 3632 3633 enum amdgpu_gfx_gcea_ras_mem_id { 3634 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3635 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3636 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3637 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3638 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3639 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3640 AMDGPU_GFX_GCEA_MAM_DMEM0, 3641 AMDGPU_GFX_GCEA_MAM_DMEM1, 3642 AMDGPU_GFX_GCEA_MAM_DMEM2, 3643 AMDGPU_GFX_GCEA_MAM_DMEM3, 3644 AMDGPU_GFX_GCEA_MAM_AMEM0, 3645 AMDGPU_GFX_GCEA_MAM_AMEM1, 3646 AMDGPU_GFX_GCEA_MAM_AMEM2, 3647 AMDGPU_GFX_GCEA_MAM_AMEM3, 3648 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3649 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3650 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3651 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3652 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3653 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3654 }; 3655 3656 enum amdgpu_gfx_gc_cane_ras_mem_id { 3657 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3658 }; 3659 3660 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3661 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3662 }; 3663 3664 enum amdgpu_gfx_gds_ras_mem_id { 3665 AMDGPU_GFX_GDS_MEM0 = 0, 3666 }; 3667 3668 enum amdgpu_gfx_lds_ras_mem_id { 3669 AMDGPU_GFX_LDS_BANK0 = 0, 3670 AMDGPU_GFX_LDS_BANK1, 3671 AMDGPU_GFX_LDS_BANK2, 3672 AMDGPU_GFX_LDS_BANK3, 3673 AMDGPU_GFX_LDS_BANK4, 3674 AMDGPU_GFX_LDS_BANK5, 3675 AMDGPU_GFX_LDS_BANK6, 3676 AMDGPU_GFX_LDS_BANK7, 3677 AMDGPU_GFX_LDS_BANK8, 3678 AMDGPU_GFX_LDS_BANK9, 3679 AMDGPU_GFX_LDS_BANK10, 3680 AMDGPU_GFX_LDS_BANK11, 3681 AMDGPU_GFX_LDS_BANK12, 3682 AMDGPU_GFX_LDS_BANK13, 3683 AMDGPU_GFX_LDS_BANK14, 3684 AMDGPU_GFX_LDS_BANK15, 3685 AMDGPU_GFX_LDS_BANK16, 3686 AMDGPU_GFX_LDS_BANK17, 3687 AMDGPU_GFX_LDS_BANK18, 3688 AMDGPU_GFX_LDS_BANK19, 3689 AMDGPU_GFX_LDS_BANK20, 3690 AMDGPU_GFX_LDS_BANK21, 3691 AMDGPU_GFX_LDS_BANK22, 3692 AMDGPU_GFX_LDS_BANK23, 3693 AMDGPU_GFX_LDS_BANK24, 3694 AMDGPU_GFX_LDS_BANK25, 3695 AMDGPU_GFX_LDS_BANK26, 3696 AMDGPU_GFX_LDS_BANK27, 3697 AMDGPU_GFX_LDS_BANK28, 3698 AMDGPU_GFX_LDS_BANK29, 3699 AMDGPU_GFX_LDS_BANK30, 3700 AMDGPU_GFX_LDS_BANK31, 3701 AMDGPU_GFX_LDS_SP_BUFFER_A, 3702 AMDGPU_GFX_LDS_SP_BUFFER_B, 3703 }; 3704 3705 enum amdgpu_gfx_rlc_ras_mem_id { 3706 AMDGPU_GFX_RLC_GPMF32 = 1, 3707 AMDGPU_GFX_RLC_RLCVF32, 3708 AMDGPU_GFX_RLC_SCRATCH, 3709 AMDGPU_GFX_RLC_SRM_ARAM, 3710 AMDGPU_GFX_RLC_SRM_DRAM, 3711 AMDGPU_GFX_RLC_TCTAG, 3712 AMDGPU_GFX_RLC_SPM_SE, 3713 AMDGPU_GFX_RLC_SPM_GRBMT, 3714 }; 3715 3716 enum amdgpu_gfx_sp_ras_mem_id { 3717 AMDGPU_GFX_SP_SIMDID0 = 0, 3718 }; 3719 3720 enum amdgpu_gfx_spi_ras_mem_id { 3721 AMDGPU_GFX_SPI_MEM0 = 0, 3722 AMDGPU_GFX_SPI_MEM1, 3723 AMDGPU_GFX_SPI_MEM2, 3724 AMDGPU_GFX_SPI_MEM3, 3725 }; 3726 3727 enum amdgpu_gfx_sqc_ras_mem_id { 3728 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3729 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3730 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3731 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3732 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3733 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3734 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3735 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3736 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3737 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3738 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3739 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3740 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3741 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3742 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3743 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3744 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3745 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3746 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3747 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3748 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3749 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3750 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3751 }; 3752 3753 enum amdgpu_gfx_sq_ras_mem_id { 3754 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3755 AMDGPU_GFX_SQ_SGPR_MEM1, 3756 AMDGPU_GFX_SQ_SGPR_MEM2, 3757 AMDGPU_GFX_SQ_SGPR_MEM3, 3758 }; 3759 3760 enum amdgpu_gfx_ta_ras_mem_id { 3761 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3762 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3763 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3764 AMDGPU_GFX_TA_FSX_LFIFO, 3765 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3766 }; 3767 3768 enum amdgpu_gfx_tcc_ras_mem_id { 3769 AMDGPU_GFX_TCC_MEM1 = 1, 3770 }; 3771 3772 enum amdgpu_gfx_tca_ras_mem_id { 3773 AMDGPU_GFX_TCA_MEM1 = 1, 3774 }; 3775 3776 enum amdgpu_gfx_tci_ras_mem_id { 3777 AMDGPU_GFX_TCIW_MEM = 1, 3778 }; 3779 3780 enum amdgpu_gfx_tcp_ras_mem_id { 3781 AMDGPU_GFX_TCP_LFIFO0 = 1, 3782 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3783 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3784 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3785 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3786 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3787 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3788 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3789 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3790 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3791 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3792 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3793 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3794 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3795 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3796 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3797 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3798 AMDGPU_GFX_TCP_VM_FIFO, 3799 AMDGPU_GFX_TCP_DB_TAGRAM0, 3800 AMDGPU_GFX_TCP_DB_TAGRAM1, 3801 AMDGPU_GFX_TCP_DB_TAGRAM2, 3802 AMDGPU_GFX_TCP_DB_TAGRAM3, 3803 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3804 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3805 AMDGPU_GFX_TCP_CMD_FIFO, 3806 }; 3807 3808 enum amdgpu_gfx_td_ras_mem_id { 3809 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3810 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3811 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3812 }; 3813 3814 enum amdgpu_gfx_tcx_ras_mem_id { 3815 AMDGPU_GFX_TCX_FIFOD0 = 0, 3816 AMDGPU_GFX_TCX_FIFOD1, 3817 AMDGPU_GFX_TCX_FIFOD2, 3818 AMDGPU_GFX_TCX_FIFOD3, 3819 AMDGPU_GFX_TCX_FIFOD4, 3820 AMDGPU_GFX_TCX_FIFOD5, 3821 AMDGPU_GFX_TCX_FIFOD6, 3822 AMDGPU_GFX_TCX_FIFOD7, 3823 AMDGPU_GFX_TCX_FIFOB0, 3824 AMDGPU_GFX_TCX_FIFOB1, 3825 AMDGPU_GFX_TCX_FIFOB2, 3826 AMDGPU_GFX_TCX_FIFOB3, 3827 AMDGPU_GFX_TCX_FIFOB4, 3828 AMDGPU_GFX_TCX_FIFOB5, 3829 AMDGPU_GFX_TCX_FIFOB6, 3830 AMDGPU_GFX_TCX_FIFOB7, 3831 AMDGPU_GFX_TCX_FIFOA0, 3832 AMDGPU_GFX_TCX_FIFOA1, 3833 AMDGPU_GFX_TCX_FIFOA2, 3834 AMDGPU_GFX_TCX_FIFOA3, 3835 AMDGPU_GFX_TCX_FIFOA4, 3836 AMDGPU_GFX_TCX_FIFOA5, 3837 AMDGPU_GFX_TCX_FIFOA6, 3838 AMDGPU_GFX_TCX_FIFOA7, 3839 AMDGPU_GFX_TCX_CFIFO0, 3840 AMDGPU_GFX_TCX_CFIFO1, 3841 AMDGPU_GFX_TCX_CFIFO2, 3842 AMDGPU_GFX_TCX_CFIFO3, 3843 AMDGPU_GFX_TCX_CFIFO4, 3844 AMDGPU_GFX_TCX_CFIFO5, 3845 AMDGPU_GFX_TCX_CFIFO6, 3846 AMDGPU_GFX_TCX_CFIFO7, 3847 AMDGPU_GFX_TCX_FIFO_ACKB0, 3848 AMDGPU_GFX_TCX_FIFO_ACKB1, 3849 AMDGPU_GFX_TCX_FIFO_ACKB2, 3850 AMDGPU_GFX_TCX_FIFO_ACKB3, 3851 AMDGPU_GFX_TCX_FIFO_ACKB4, 3852 AMDGPU_GFX_TCX_FIFO_ACKB5, 3853 AMDGPU_GFX_TCX_FIFO_ACKB6, 3854 AMDGPU_GFX_TCX_FIFO_ACKB7, 3855 AMDGPU_GFX_TCX_FIFO_ACKD0, 3856 AMDGPU_GFX_TCX_FIFO_ACKD1, 3857 AMDGPU_GFX_TCX_FIFO_ACKD2, 3858 AMDGPU_GFX_TCX_FIFO_ACKD3, 3859 AMDGPU_GFX_TCX_FIFO_ACKD4, 3860 AMDGPU_GFX_TCX_FIFO_ACKD5, 3861 AMDGPU_GFX_TCX_FIFO_ACKD6, 3862 AMDGPU_GFX_TCX_FIFO_ACKD7, 3863 AMDGPU_GFX_TCX_DST_FIFOA0, 3864 AMDGPU_GFX_TCX_DST_FIFOA1, 3865 AMDGPU_GFX_TCX_DST_FIFOA2, 3866 AMDGPU_GFX_TCX_DST_FIFOA3, 3867 AMDGPU_GFX_TCX_DST_FIFOA4, 3868 AMDGPU_GFX_TCX_DST_FIFOA5, 3869 AMDGPU_GFX_TCX_DST_FIFOA6, 3870 AMDGPU_GFX_TCX_DST_FIFOA7, 3871 AMDGPU_GFX_TCX_DST_FIFOB0, 3872 AMDGPU_GFX_TCX_DST_FIFOB1, 3873 AMDGPU_GFX_TCX_DST_FIFOB2, 3874 AMDGPU_GFX_TCX_DST_FIFOB3, 3875 AMDGPU_GFX_TCX_DST_FIFOB4, 3876 AMDGPU_GFX_TCX_DST_FIFOB5, 3877 AMDGPU_GFX_TCX_DST_FIFOB6, 3878 AMDGPU_GFX_TCX_DST_FIFOB7, 3879 AMDGPU_GFX_TCX_DST_FIFOD0, 3880 AMDGPU_GFX_TCX_DST_FIFOD1, 3881 AMDGPU_GFX_TCX_DST_FIFOD2, 3882 AMDGPU_GFX_TCX_DST_FIFOD3, 3883 AMDGPU_GFX_TCX_DST_FIFOD4, 3884 AMDGPU_GFX_TCX_DST_FIFOD5, 3885 AMDGPU_GFX_TCX_DST_FIFOD6, 3886 AMDGPU_GFX_TCX_DST_FIFOD7, 3887 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3888 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3889 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3890 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3891 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3892 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3893 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3894 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3895 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3896 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3897 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3898 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3899 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3900 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3901 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3902 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3903 }; 3904 3905 enum amdgpu_gfx_atc_l2_ras_mem_id { 3906 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3907 }; 3908 3909 enum amdgpu_gfx_utcl2_ras_mem_id { 3910 AMDGPU_GFX_UTCL2_MEM0 = 0, 3911 }; 3912 3913 enum amdgpu_gfx_vml2_ras_mem_id { 3914 AMDGPU_GFX_VML2_MEM0 = 0, 3915 }; 3916 3917 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3918 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3919 }; 3920 3921 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3922 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3923 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3924 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3925 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3926 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3927 }; 3928 3929 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3930 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3931 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3932 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3933 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3934 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3935 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3936 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3937 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3938 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3939 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3940 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3941 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3942 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3943 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3944 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3945 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3946 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3947 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3948 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3949 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3950 }; 3951 3952 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3953 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3954 }; 3955 3956 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3957 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3958 }; 3959 3960 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3961 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3962 }; 3963 3964 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3965 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3966 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3967 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3968 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3969 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3970 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3971 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3972 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3973 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3974 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3975 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3976 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3977 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3978 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3979 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3980 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3981 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3982 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3983 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3984 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3985 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3986 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3987 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3988 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3989 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3990 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3991 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3992 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3993 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3994 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3995 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3996 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3997 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3998 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3999 }; 4000 4001 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4002 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4003 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4004 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4005 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4006 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4007 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4008 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4009 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4010 }; 4011 4012 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4013 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4014 }; 4015 4016 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4017 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4018 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4019 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4020 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4021 }; 4022 4023 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4024 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4025 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4026 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4027 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4028 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4029 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4030 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4031 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4032 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4033 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4034 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4035 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4036 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4037 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4038 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4039 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4040 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4041 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4042 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4043 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4044 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4045 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4046 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4047 }; 4048 4049 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4050 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4051 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4052 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4053 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4054 }; 4055 4056 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4057 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4058 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4059 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4060 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4061 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4062 }; 4063 4064 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4065 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4066 }; 4067 4068 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4069 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4070 }; 4071 4072 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4073 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4074 }; 4075 4076 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4077 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4078 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4079 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4080 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4081 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4082 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4083 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4084 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4085 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4086 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4087 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4088 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4089 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4090 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4091 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4092 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4093 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4094 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4095 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4096 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4097 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4098 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4099 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4100 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4101 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4102 }; 4103 4104 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4105 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4106 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4107 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4108 }; 4109 4110 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4111 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4112 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4113 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4114 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4115 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4116 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4117 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4118 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4119 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4120 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4121 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4122 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4123 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4124 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4125 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4126 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4127 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4128 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4129 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4130 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4131 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4132 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4133 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4134 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4135 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4136 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4137 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4138 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4139 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4140 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4141 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4142 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4143 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4144 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4145 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4146 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4147 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4148 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4149 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4150 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4151 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4152 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4153 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4154 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4155 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4156 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4157 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4158 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4159 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4160 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4161 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4162 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4163 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4164 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4165 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4166 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4167 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4168 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4169 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4170 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4171 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4172 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4173 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4174 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4175 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4176 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4177 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4178 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4183 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4184 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4185 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4186 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4187 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4188 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4189 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4190 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4191 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4192 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4193 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4194 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4195 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4196 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4197 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4198 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4199 }; 4200 4201 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4202 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4203 }; 4204 4205 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4206 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4207 }; 4208 4209 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4210 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4211 }; 4212 4213 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4214 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4215 }; 4216 4217 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4218 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4219 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4220 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4221 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4222 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4223 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4224 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4225 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4226 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4227 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4228 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4229 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4230 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4231 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4232 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4233 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4234 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4235 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4236 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4237 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4240 }; 4241 4242 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4243 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4244 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4245 AMDGPU_GFX_RLC_MEM, 1}, 4246 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4247 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4248 AMDGPU_GFX_CP_MEM, 1}, 4249 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4250 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4251 AMDGPU_GFX_CP_MEM, 1}, 4252 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4253 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4254 AMDGPU_GFX_CP_MEM, 1}, 4255 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4256 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4257 AMDGPU_GFX_GDS_MEM, 1}, 4258 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4259 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4260 AMDGPU_GFX_GC_CANE_MEM, 1}, 4261 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4262 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4263 AMDGPU_GFX_SPI_MEM, 1}, 4264 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4265 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4266 AMDGPU_GFX_SP_MEM, 4}, 4267 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4268 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4269 AMDGPU_GFX_SP_MEM, 4}, 4270 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4271 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4272 AMDGPU_GFX_SQ_MEM, 4}, 4273 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4274 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4275 AMDGPU_GFX_SQC_MEM, 4}, 4276 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4277 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4278 AMDGPU_GFX_TCX_MEM, 1}, 4279 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4280 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4281 AMDGPU_GFX_TCC_MEM, 1}, 4282 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4283 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4284 AMDGPU_GFX_TA_MEM, 4}, 4285 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4286 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4287 AMDGPU_GFX_TCI_MEM, 1}, 4288 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4289 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4290 AMDGPU_GFX_TCP_MEM, 4}, 4291 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4292 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4293 AMDGPU_GFX_TD_MEM, 4}, 4294 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4295 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4296 AMDGPU_GFX_GCEA_MEM, 1}, 4297 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4298 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4299 AMDGPU_GFX_LDS_MEM, 4}, 4300 }; 4301 4302 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4303 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4304 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4305 AMDGPU_GFX_RLC_MEM, 1}, 4306 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4307 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4308 AMDGPU_GFX_CP_MEM, 1}, 4309 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4310 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4311 AMDGPU_GFX_CP_MEM, 1}, 4312 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4313 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4314 AMDGPU_GFX_CP_MEM, 1}, 4315 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4316 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4317 AMDGPU_GFX_GDS_MEM, 1}, 4318 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4319 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4320 AMDGPU_GFX_GC_CANE_MEM, 1}, 4321 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4322 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4323 AMDGPU_GFX_SPI_MEM, 1}, 4324 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4325 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4326 AMDGPU_GFX_SP_MEM, 4}, 4327 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4328 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4329 AMDGPU_GFX_SP_MEM, 4}, 4330 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4331 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4332 AMDGPU_GFX_SQ_MEM, 4}, 4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4334 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4335 AMDGPU_GFX_SQC_MEM, 4}, 4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4337 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4338 AMDGPU_GFX_TCX_MEM, 1}, 4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4340 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4341 AMDGPU_GFX_TCC_MEM, 1}, 4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4343 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4344 AMDGPU_GFX_TA_MEM, 4}, 4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4346 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4347 AMDGPU_GFX_TCI_MEM, 1}, 4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4349 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4350 AMDGPU_GFX_TCP_MEM, 4}, 4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4352 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4353 AMDGPU_GFX_TD_MEM, 4}, 4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4355 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4356 AMDGPU_GFX_TCA_MEM, 1}, 4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4358 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4359 AMDGPU_GFX_GCEA_MEM, 1}, 4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4361 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4362 AMDGPU_GFX_LDS_MEM, 4}, 4363 }; 4364 4365 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4366 void *ras_error_status, int xcc_id) 4367 { 4368 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4369 unsigned long ce_count = 0, ue_count = 0; 4370 uint32_t i, j, k; 4371 4372 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4373 struct amdgpu_smuio_mcm_config_info mcm_info = { 4374 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4375 .die_id = xcc_id & 0x01 ? 1 : 0, 4376 }; 4377 4378 mutex_lock(&adev->grbm_idx_mutex); 4379 4380 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4381 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4382 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4383 /* no need to select if instance number is 1 */ 4384 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4385 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4386 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4387 4388 amdgpu_ras_inst_query_ras_error_count(adev, 4389 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4390 1, 4391 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4392 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4393 GET_INST(GC, xcc_id), 4394 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4395 &ce_count); 4396 4397 amdgpu_ras_inst_query_ras_error_count(adev, 4398 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4399 1, 4400 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4401 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4402 GET_INST(GC, xcc_id), 4403 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4404 &ue_count); 4405 } 4406 } 4407 } 4408 4409 /* handle extra register entries of UE */ 4410 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4411 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4412 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4413 /* no need to select if instance number is 1 */ 4414 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4415 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4416 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4417 4418 amdgpu_ras_inst_query_ras_error_count(adev, 4419 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4420 1, 4421 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4422 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4423 GET_INST(GC, xcc_id), 4424 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4425 &ue_count); 4426 } 4427 } 4428 } 4429 4430 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4431 xcc_id); 4432 mutex_unlock(&adev->grbm_idx_mutex); 4433 4434 /* the caller should make sure initialize value of 4435 * err_data->ue_count and err_data->ce_count 4436 */ 4437 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4438 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4439 } 4440 4441 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4442 void *ras_error_status, int xcc_id) 4443 { 4444 uint32_t i, j, k; 4445 4446 mutex_lock(&adev->grbm_idx_mutex); 4447 4448 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4449 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4450 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4451 /* no need to select if instance number is 1 */ 4452 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4453 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4454 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4455 4456 amdgpu_ras_inst_reset_ras_error_count(adev, 4457 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4458 1, 4459 GET_INST(GC, xcc_id)); 4460 4461 amdgpu_ras_inst_reset_ras_error_count(adev, 4462 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4463 1, 4464 GET_INST(GC, xcc_id)); 4465 } 4466 } 4467 } 4468 4469 /* handle extra register entries of UE */ 4470 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4471 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4472 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4473 /* no need to select if instance number is 1 */ 4474 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4475 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4476 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4477 4478 amdgpu_ras_inst_reset_ras_error_count(adev, 4479 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4480 1, 4481 GET_INST(GC, xcc_id)); 4482 } 4483 } 4484 } 4485 4486 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4487 xcc_id); 4488 mutex_unlock(&adev->grbm_idx_mutex); 4489 } 4490 4491 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4492 void *ras_error_status, int xcc_id) 4493 { 4494 uint32_t i; 4495 uint32_t data; 4496 4497 if (amdgpu_sriov_vf(adev)) 4498 return; 4499 4500 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4501 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4502 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4503 4504 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4505 (amdgpu_watchdog_timer.period < 1 || 4506 amdgpu_watchdog_timer.period > 0x23)) { 4507 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4508 amdgpu_watchdog_timer.period = 0x23; 4509 } 4510 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4511 amdgpu_watchdog_timer.period); 4512 4513 mutex_lock(&adev->grbm_idx_mutex); 4514 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4515 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4516 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4517 } 4518 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4519 xcc_id); 4520 mutex_unlock(&adev->grbm_idx_mutex); 4521 } 4522 4523 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4524 void *ras_error_status) 4525 { 4526 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4527 gfx_v9_4_3_inst_query_ras_err_count); 4528 } 4529 4530 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4531 { 4532 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4533 } 4534 4535 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4536 { 4537 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4538 } 4539 4540 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4541 { 4542 /* Header itself is a NOP packet */ 4543 if (num_nop == 1) { 4544 amdgpu_ring_write(ring, ring->funcs->nop); 4545 return; 4546 } 4547 4548 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4549 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4550 4551 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4552 amdgpu_ring_insert_nop(ring, num_nop - 1); 4553 } 4554 4555 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4556 { 4557 struct amdgpu_device *adev = ip_block->adev; 4558 uint32_t i, j, k; 4559 uint32_t xcc_id, xcc_offset, inst_offset; 4560 uint32_t num_xcc, reg, num_inst; 4561 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4562 4563 if (!adev->gfx.ip_dump_core) 4564 return; 4565 4566 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4567 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4568 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4569 xcc_offset = xcc_id * reg_count; 4570 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4571 for (i = 0; i < reg_count; i++) 4572 drm_printf(p, "%-50s \t 0x%08x\n", 4573 gc_reg_list_9_4_3[i].reg_name, 4574 adev->gfx.ip_dump_core[xcc_offset + i]); 4575 } 4576 4577 /* print compute queue registers for all instances */ 4578 if (!adev->gfx.ip_dump_compute_queues) 4579 return; 4580 4581 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4582 adev->gfx.mec.num_queue_per_pipe; 4583 4584 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4585 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4586 num_xcc, 4587 adev->gfx.mec.num_mec, 4588 adev->gfx.mec.num_pipe_per_mec, 4589 adev->gfx.mec.num_queue_per_pipe); 4590 4591 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4592 xcc_offset = xcc_id * reg_count * num_inst; 4593 inst_offset = 0; 4594 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4595 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4596 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4597 drm_printf(p, 4598 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4599 xcc_id, i, j, k); 4600 for (reg = 0; reg < reg_count; reg++) { 4601 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4602 regCP_MEC_ME1_HEADER_DUMP) 4603 drm_printf(p, 4604 "%-50s \t 0x%08x\n", 4605 "regCP_MEC_ME2_HEADER_DUMP", 4606 adev->gfx.ip_dump_compute_queues 4607 [xcc_offset + inst_offset + 4608 reg]); 4609 else 4610 drm_printf(p, 4611 "%-50s \t 0x%08x\n", 4612 gc_cp_reg_list_9_4_3[reg].reg_name, 4613 adev->gfx.ip_dump_compute_queues 4614 [xcc_offset + inst_offset + 4615 reg]); 4616 } 4617 inst_offset += reg_count; 4618 } 4619 } 4620 } 4621 } 4622 } 4623 4624 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4625 { 4626 struct amdgpu_device *adev = ip_block->adev; 4627 uint32_t i, j, k; 4628 uint32_t num_xcc, reg, num_inst; 4629 uint32_t xcc_id, xcc_offset, inst_offset; 4630 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4631 4632 if (!adev->gfx.ip_dump_core) 4633 return; 4634 4635 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4636 4637 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4638 xcc_offset = xcc_id * reg_count; 4639 for (i = 0; i < reg_count; i++) 4640 adev->gfx.ip_dump_core[xcc_offset + i] = 4641 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4642 GET_INST(GC, xcc_id))); 4643 } 4644 4645 /* dump compute queue registers for all instances */ 4646 if (!adev->gfx.ip_dump_compute_queues) 4647 return; 4648 4649 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4650 adev->gfx.mec.num_queue_per_pipe; 4651 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4652 mutex_lock(&adev->srbm_mutex); 4653 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4654 xcc_offset = xcc_id * reg_count * num_inst; 4655 inst_offset = 0; 4656 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4657 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4658 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4659 /* ME0 is for GFX so start from 1 for CP */ 4660 soc15_grbm_select(adev, 1 + i, j, k, 0, 4661 GET_INST(GC, xcc_id)); 4662 4663 for (reg = 0; reg < reg_count; reg++) { 4664 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4665 regCP_MEC_ME1_HEADER_DUMP) 4666 adev->gfx.ip_dump_compute_queues 4667 [xcc_offset + 4668 inst_offset + reg] = 4669 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4670 regCP_MEC_ME2_HEADER_DUMP)); 4671 else 4672 adev->gfx.ip_dump_compute_queues 4673 [xcc_offset + 4674 inst_offset + reg] = 4675 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4676 gc_cp_reg_list_9_4_3[reg], 4677 GET_INST(GC, xcc_id))); 4678 } 4679 inst_offset += reg_count; 4680 } 4681 } 4682 } 4683 } 4684 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4685 mutex_unlock(&adev->srbm_mutex); 4686 } 4687 4688 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4689 { 4690 /* Emit the cleaner shader */ 4691 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4692 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4693 } 4694 4695 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4696 .name = "gfx_v9_4_3", 4697 .early_init = gfx_v9_4_3_early_init, 4698 .late_init = gfx_v9_4_3_late_init, 4699 .sw_init = gfx_v9_4_3_sw_init, 4700 .sw_fini = gfx_v9_4_3_sw_fini, 4701 .hw_init = gfx_v9_4_3_hw_init, 4702 .hw_fini = gfx_v9_4_3_hw_fini, 4703 .suspend = gfx_v9_4_3_suspend, 4704 .resume = gfx_v9_4_3_resume, 4705 .is_idle = gfx_v9_4_3_is_idle, 4706 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4707 .soft_reset = gfx_v9_4_3_soft_reset, 4708 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4709 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4710 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4711 .dump_ip_state = gfx_v9_4_3_ip_dump, 4712 .print_ip_state = gfx_v9_4_3_ip_print, 4713 }; 4714 4715 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4716 .type = AMDGPU_RING_TYPE_COMPUTE, 4717 .align_mask = 0xff, 4718 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4719 .support_64bit_ptrs = true, 4720 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4721 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4722 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4723 .emit_frame_size = 4724 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4725 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4726 5 + /* hdp invalidate */ 4727 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4728 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4729 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4730 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4731 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4732 7 + /* gfx_v9_4_3_emit_mem_sync */ 4733 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4734 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4735 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4736 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4737 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4738 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4739 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4740 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4741 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4742 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4743 .test_ring = gfx_v9_4_3_ring_test_ring, 4744 .test_ib = gfx_v9_4_3_ring_test_ib, 4745 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4746 .pad_ib = amdgpu_ring_generic_pad_ib, 4747 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4748 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4749 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4750 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4751 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4752 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4753 .reset = gfx_v9_4_3_reset_kcq, 4754 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4755 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4756 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4757 }; 4758 4759 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4760 .type = AMDGPU_RING_TYPE_KIQ, 4761 .align_mask = 0xff, 4762 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4763 .support_64bit_ptrs = true, 4764 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4765 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4766 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4767 .emit_frame_size = 4768 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4769 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4770 5 + /* hdp invalidate */ 4771 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4772 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4773 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4774 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4775 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4776 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4777 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4778 .test_ring = gfx_v9_4_3_ring_test_ring, 4779 .insert_nop = amdgpu_ring_insert_nop, 4780 .pad_ib = amdgpu_ring_generic_pad_ib, 4781 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4782 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4783 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4784 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4785 }; 4786 4787 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4788 { 4789 int i, j, num_xcc; 4790 4791 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4792 for (i = 0; i < num_xcc; i++) { 4793 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4794 4795 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4796 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4797 = &gfx_v9_4_3_ring_funcs_compute; 4798 } 4799 } 4800 4801 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4802 .set = gfx_v9_4_3_set_eop_interrupt_state, 4803 .process = gfx_v9_4_3_eop_irq, 4804 }; 4805 4806 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4807 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4808 .process = gfx_v9_4_3_priv_reg_irq, 4809 }; 4810 4811 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4812 .set = gfx_v9_4_3_set_bad_op_fault_state, 4813 .process = gfx_v9_4_3_bad_op_irq, 4814 }; 4815 4816 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4817 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4818 .process = gfx_v9_4_3_priv_inst_irq, 4819 }; 4820 4821 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4822 { 4823 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4824 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4825 4826 adev->gfx.priv_reg_irq.num_types = 1; 4827 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4828 4829 adev->gfx.bad_op_irq.num_types = 1; 4830 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4831 4832 adev->gfx.priv_inst_irq.num_types = 1; 4833 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4834 } 4835 4836 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4837 { 4838 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4839 } 4840 4841 4842 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4843 { 4844 /* 9.4.3 variants removed all the GDS internal memory, 4845 * only support GWS opcode in kernel, like barrier 4846 * semaphore.etc */ 4847 4848 /* init asic gds info */ 4849 adev->gds.gds_size = 0; 4850 adev->gds.gds_compute_max_wave_id = 0; 4851 adev->gds.gws_size = 64; 4852 adev->gds.oa_size = 16; 4853 } 4854 4855 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4856 u32 bitmap, int xcc_id) 4857 { 4858 u32 data; 4859 4860 if (!bitmap) 4861 return; 4862 4863 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4864 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4865 4866 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4867 } 4868 4869 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4870 { 4871 u32 data, mask; 4872 4873 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4874 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4875 4876 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4877 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4878 4879 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4880 4881 return (~data) & mask; 4882 } 4883 4884 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4885 struct amdgpu_cu_info *cu_info) 4886 { 4887 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4888 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4889 unsigned disable_masks[4 * 4]; 4890 bool is_symmetric_cus; 4891 4892 if (!adev || !cu_info) 4893 return -EINVAL; 4894 4895 /* 4896 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4897 */ 4898 if (adev->gfx.config.max_shader_engines * 4899 adev->gfx.config.max_sh_per_se > 16) 4900 return -EINVAL; 4901 4902 amdgpu_gfx_parse_disable_cu(disable_masks, 4903 adev->gfx.config.max_shader_engines, 4904 adev->gfx.config.max_sh_per_se); 4905 4906 mutex_lock(&adev->grbm_idx_mutex); 4907 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4908 is_symmetric_cus = true; 4909 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4910 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4911 mask = 1; 4912 ao_bitmap = 0; 4913 counter = 0; 4914 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4915 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4916 adev, 4917 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4918 xcc_id); 4919 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4920 4921 cu_info->bitmap[xcc_id][i][j] = bitmap; 4922 4923 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4924 if (bitmap & mask) { 4925 if (counter < adev->gfx.config.max_cu_per_sh) 4926 ao_bitmap |= mask; 4927 counter++; 4928 } 4929 mask <<= 1; 4930 } 4931 active_cu_number += counter; 4932 if (i < 2 && j < 2) 4933 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4934 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4935 } 4936 if (i && is_symmetric_cus && prev_counter != counter) 4937 is_symmetric_cus = false; 4938 prev_counter = counter; 4939 } 4940 if (is_symmetric_cus) { 4941 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4942 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4943 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4944 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4945 } 4946 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4947 xcc_id); 4948 } 4949 mutex_unlock(&adev->grbm_idx_mutex); 4950 4951 cu_info->number = active_cu_number; 4952 cu_info->ao_cu_mask = ao_cu_mask; 4953 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4954 4955 return 0; 4956 } 4957 4958 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4959 .type = AMD_IP_BLOCK_TYPE_GFX, 4960 .major = 9, 4961 .minor = 4, 4962 .rev = 3, 4963 .funcs = &gfx_v9_4_3_ip_funcs, 4964 }; 4965 4966 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4967 { 4968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4969 uint32_t tmp_mask; 4970 int i, r; 4971 4972 /* TODO : Initialize golden regs */ 4973 /* gfx_v9_4_3_init_golden_registers(adev); */ 4974 4975 tmp_mask = inst_mask; 4976 for_each_inst(i, tmp_mask) 4977 gfx_v9_4_3_xcc_constants_init(adev, i); 4978 4979 if (!amdgpu_sriov_vf(adev)) { 4980 tmp_mask = inst_mask; 4981 for_each_inst(i, tmp_mask) { 4982 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4983 if (r) 4984 return r; 4985 } 4986 } 4987 4988 tmp_mask = inst_mask; 4989 for_each_inst(i, tmp_mask) { 4990 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4991 if (r) 4992 return r; 4993 } 4994 4995 return 0; 4996 } 4997 4998 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4999 { 5000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5001 int i; 5002 5003 for_each_inst(i, inst_mask) 5004 gfx_v9_4_3_xcc_fini(adev, i); 5005 5006 return 0; 5007 } 5008 5009 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5010 .suspend = &gfx_v9_4_3_xcp_suspend, 5011 .resume = &gfx_v9_4_3_xcp_resume 5012 }; 5013 5014 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5015 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5016 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5017 }; 5018 5019 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5020 { 5021 int r; 5022 5023 r = amdgpu_ras_block_late_init(adev, ras_block); 5024 if (r) 5025 return r; 5026 5027 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5028 &gfx_v9_4_3_aca_info, 5029 NULL); 5030 if (r) 5031 goto late_fini; 5032 5033 return 0; 5034 5035 late_fini: 5036 amdgpu_ras_block_late_fini(adev, ras_block); 5037 5038 return r; 5039 } 5040 5041 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5042 .ras_block = { 5043 .hw_ops = &gfx_v9_4_3_ras_ops, 5044 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5045 }, 5046 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5047 }; 5048