1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 50 51 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 52 53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 58 struct amdgpu_cu_info *cu_info); 59 60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 61 uint64_t queue_mask) 62 { 63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 64 amdgpu_ring_write(kiq_ring, 65 PACKET3_SET_RESOURCES_VMID_MASK(0) | 66 /* vmid_mask:0* queue_type:0 (KIQ) */ 67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 68 amdgpu_ring_write(kiq_ring, 69 lower_32_bits(queue_mask)); /* queue mask lo */ 70 amdgpu_ring_write(kiq_ring, 71 upper_32_bits(queue_mask)); /* queue mask hi */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 76 } 77 78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 79 struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = kiq_ring->adev; 82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 85 86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 94 /*queue_type: normal compute queue */ 95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 96 /* alloc format: all_on_one_pipe */ 97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 99 /* num_queues: must be 1 */ 100 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 101 amdgpu_ring_write(kiq_ring, 102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 107 } 108 109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 110 struct amdgpu_ring *ring, 111 enum amdgpu_unmap_queues_action action, 112 u64 gpu_addr, u64 seq) 113 { 114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 115 116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 118 PACKET3_UNMAP_QUEUES_ACTION(action) | 119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 122 amdgpu_ring_write(kiq_ring, 123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 124 125 if (action == PREEMPT_QUEUES_NO_UNMAP) { 126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 128 amdgpu_ring_write(kiq_ring, seq); 129 } else { 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 amdgpu_ring_write(kiq_ring, 0); 133 } 134 } 135 136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 137 struct amdgpu_ring *ring, 138 u64 addr, 139 u64 seq) 140 { 141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 142 143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 144 amdgpu_ring_write(kiq_ring, 145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 147 PACKET3_QUERY_STATUS_COMMAND(2)); 148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 149 amdgpu_ring_write(kiq_ring, 150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 156 } 157 158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 159 uint16_t pasid, uint32_t flush_type, 160 bool all_hub) 161 { 162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 163 amdgpu_ring_write(kiq_ring, 164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 166 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 168 } 169 170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 174 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 176 .set_resources_size = 8, 177 .map_queues_size = 7, 178 .unmap_queues_size = 6, 179 .query_status_size = 7, 180 .invalidate_tlbs_size = 2, 181 }; 182 183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 184 { 185 int i, num_xcc; 186 187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 188 for (i = 0; i < num_xcc; i++) 189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 190 } 191 192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 193 { 194 int i, num_xcc, dev_inst; 195 196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 197 for (i = 0; i < num_xcc; i++) { 198 dev_inst = GET_INST(GC, i); 199 200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 201 GOLDEN_GB_ADDR_CONFIG); 202 /* Golden settings applied by driver for ASIC with rev_id 0 */ 203 if (adev->rev_id == 0) { 204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 205 REDUCE_FIFO_DEPTH_BY_2, 2); 206 } 207 } 208 } 209 210 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 211 bool wc, uint32_t reg, uint32_t val) 212 { 213 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 214 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 215 WRITE_DATA_DST_SEL(0) | 216 (wc ? WR_CONFIRM : 0)); 217 amdgpu_ring_write(ring, reg); 218 amdgpu_ring_write(ring, 0); 219 amdgpu_ring_write(ring, val); 220 } 221 222 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 223 int mem_space, int opt, uint32_t addr0, 224 uint32_t addr1, uint32_t ref, uint32_t mask, 225 uint32_t inv) 226 { 227 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 228 amdgpu_ring_write(ring, 229 /* memory (1) or register (0) */ 230 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 231 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 232 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 233 WAIT_REG_MEM_ENGINE(eng_sel))); 234 235 if (mem_space) 236 BUG_ON(addr0 & 0x3); /* Dword align */ 237 amdgpu_ring_write(ring, addr0); 238 amdgpu_ring_write(ring, addr1); 239 amdgpu_ring_write(ring, ref); 240 amdgpu_ring_write(ring, mask); 241 amdgpu_ring_write(ring, inv); /* poll interval */ 242 } 243 244 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 245 { 246 uint32_t scratch_reg0_offset, xcc_offset; 247 struct amdgpu_device *adev = ring->adev; 248 uint32_t tmp = 0; 249 unsigned i; 250 int r; 251 252 /* Use register offset which is local to XCC in the packet */ 253 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 254 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 255 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 256 257 r = amdgpu_ring_alloc(ring, 3); 258 if (r) 259 return r; 260 261 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 262 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 263 amdgpu_ring_write(ring, 0xDEADBEEF); 264 amdgpu_ring_commit(ring); 265 266 for (i = 0; i < adev->usec_timeout; i++) { 267 tmp = RREG32(scratch_reg0_offset); 268 if (tmp == 0xDEADBEEF) 269 break; 270 udelay(1); 271 } 272 273 if (i >= adev->usec_timeout) 274 r = -ETIMEDOUT; 275 return r; 276 } 277 278 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 279 { 280 struct amdgpu_device *adev = ring->adev; 281 struct amdgpu_ib ib; 282 struct dma_fence *f = NULL; 283 284 unsigned index; 285 uint64_t gpu_addr; 286 uint32_t tmp; 287 long r; 288 289 r = amdgpu_device_wb_get(adev, &index); 290 if (r) 291 return r; 292 293 gpu_addr = adev->wb.gpu_addr + (index * 4); 294 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 295 memset(&ib, 0, sizeof(ib)); 296 r = amdgpu_ib_get(adev, NULL, 16, 297 AMDGPU_IB_POOL_DIRECT, &ib); 298 if (r) 299 goto err1; 300 301 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 302 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 303 ib.ptr[2] = lower_32_bits(gpu_addr); 304 ib.ptr[3] = upper_32_bits(gpu_addr); 305 ib.ptr[4] = 0xDEADBEEF; 306 ib.length_dw = 5; 307 308 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 309 if (r) 310 goto err2; 311 312 r = dma_fence_wait_timeout(f, false, timeout); 313 if (r == 0) { 314 r = -ETIMEDOUT; 315 goto err2; 316 } else if (r < 0) { 317 goto err2; 318 } 319 320 tmp = adev->wb.wb[index]; 321 if (tmp == 0xDEADBEEF) 322 r = 0; 323 else 324 r = -EINVAL; 325 326 err2: 327 amdgpu_ib_free(adev, &ib, NULL); 328 dma_fence_put(f); 329 err1: 330 amdgpu_device_wb_free(adev, index); 331 return r; 332 } 333 334 335 /* This value might differs per partition */ 336 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 337 { 338 uint64_t clock; 339 340 mutex_lock(&adev->gfx.gpu_clock_mutex); 341 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 342 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 343 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 344 mutex_unlock(&adev->gfx.gpu_clock_mutex); 345 346 return clock; 347 } 348 349 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 350 { 351 amdgpu_ucode_release(&adev->gfx.pfp_fw); 352 amdgpu_ucode_release(&adev->gfx.me_fw); 353 amdgpu_ucode_release(&adev->gfx.ce_fw); 354 amdgpu_ucode_release(&adev->gfx.rlc_fw); 355 amdgpu_ucode_release(&adev->gfx.mec_fw); 356 amdgpu_ucode_release(&adev->gfx.mec2_fw); 357 358 kfree(adev->gfx.rlc.register_list_format); 359 } 360 361 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 362 const char *chip_name) 363 { 364 char fw_name[30]; 365 int err; 366 const struct rlc_firmware_header_v2_0 *rlc_hdr; 367 uint16_t version_major; 368 uint16_t version_minor; 369 370 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 371 372 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 373 if (err) 374 goto out; 375 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 376 377 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 378 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 379 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 380 out: 381 if (err) 382 amdgpu_ucode_release(&adev->gfx.rlc_fw); 383 384 return err; 385 } 386 387 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 388 { 389 return true; 390 } 391 392 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 393 { 394 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 395 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 396 } 397 398 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 399 const char *chip_name) 400 { 401 char fw_name[30]; 402 int err; 403 404 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 405 406 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 407 if (err) 408 goto out; 409 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 410 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 411 412 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 413 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 414 415 gfx_v9_4_3_check_if_need_gfxoff(adev); 416 417 out: 418 if (err) 419 amdgpu_ucode_release(&adev->gfx.mec_fw); 420 return err; 421 } 422 423 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 424 { 425 const char *chip_name; 426 int r; 427 428 chip_name = "gc_9_4_3"; 429 430 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 431 if (r) 432 return r; 433 434 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 435 if (r) 436 return r; 437 438 return r; 439 } 440 441 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 442 { 443 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 444 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 445 } 446 447 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 448 { 449 int r, i, num_xcc; 450 u32 *hpd; 451 const __le32 *fw_data; 452 unsigned fw_size; 453 u32 *fw; 454 size_t mec_hpd_size; 455 456 const struct gfx_firmware_header_v1_0 *mec_hdr; 457 458 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 459 for (i = 0; i < num_xcc; i++) 460 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 461 AMDGPU_MAX_COMPUTE_QUEUES); 462 463 /* take ownership of the relevant compute queues */ 464 amdgpu_gfx_compute_queue_acquire(adev); 465 mec_hpd_size = 466 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 467 if (mec_hpd_size) { 468 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 469 AMDGPU_GEM_DOMAIN_VRAM | 470 AMDGPU_GEM_DOMAIN_GTT, 471 &adev->gfx.mec.hpd_eop_obj, 472 &adev->gfx.mec.hpd_eop_gpu_addr, 473 (void **)&hpd); 474 if (r) { 475 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 476 gfx_v9_4_3_mec_fini(adev); 477 return r; 478 } 479 480 if (amdgpu_emu_mode == 1) { 481 for (i = 0; i < mec_hpd_size / 4; i++) { 482 memset((void *)(hpd + i), 0, 4); 483 if (i % 50 == 0) 484 msleep(1); 485 } 486 } else { 487 memset(hpd, 0, mec_hpd_size); 488 } 489 490 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 491 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 492 } 493 494 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 495 496 fw_data = (const __le32 *) 497 (adev->gfx.mec_fw->data + 498 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 499 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 500 501 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 503 &adev->gfx.mec.mec_fw_obj, 504 &adev->gfx.mec.mec_fw_gpu_addr, 505 (void **)&fw); 506 if (r) { 507 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 508 gfx_v9_4_3_mec_fini(adev); 509 return r; 510 } 511 512 memcpy(fw, fw_data, fw_size); 513 514 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 515 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 516 517 return 0; 518 } 519 520 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 521 u32 sh_num, u32 instance, int xcc_id) 522 { 523 u32 data; 524 525 if (instance == 0xffffffff) 526 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 527 INSTANCE_BROADCAST_WRITES, 1); 528 else 529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 530 INSTANCE_INDEX, instance); 531 532 if (se_num == 0xffffffff) 533 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 534 SE_BROADCAST_WRITES, 1); 535 else 536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 537 538 if (sh_num == 0xffffffff) 539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 540 SH_BROADCAST_WRITES, 1); 541 else 542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 543 544 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 545 } 546 547 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 548 { 549 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 550 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 551 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 552 (address << SQ_IND_INDEX__INDEX__SHIFT) | 553 (SQ_IND_INDEX__FORCE_READ_MASK)); 554 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 555 } 556 557 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 558 uint32_t wave, uint32_t thread, 559 uint32_t regno, uint32_t num, uint32_t *out) 560 { 561 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 562 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 563 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 564 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 565 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 566 (SQ_IND_INDEX__FORCE_READ_MASK) | 567 (SQ_IND_INDEX__AUTO_INCR_MASK)); 568 while (num--) 569 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 570 } 571 572 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 573 uint32_t xcc_id, uint32_t simd, uint32_t wave, 574 uint32_t *dst, int *no_fields) 575 { 576 /* type 1 wave data */ 577 dst[(*no_fields)++] = 1; 578 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 579 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 593 } 594 595 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 596 uint32_t wave, uint32_t start, 597 uint32_t size, uint32_t *dst) 598 { 599 wave_read_regs(adev, xcc_id, simd, wave, 0, 600 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 601 } 602 603 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 604 uint32_t wave, uint32_t thread, 605 uint32_t start, uint32_t size, 606 uint32_t *dst) 607 { 608 wave_read_regs(adev, xcc_id, simd, wave, thread, 609 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 610 } 611 612 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 613 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 614 { 615 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 616 } 617 618 619 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 620 int num_xccs_per_xcp) 621 { 622 int ret, i, num_xcc; 623 u32 tmp = 0, regval; 624 625 if (adev->psp.funcs) { 626 ret = psp_spatial_partition(&adev->psp, 627 NUM_XCC(adev->gfx.xcc_mask) / 628 num_xccs_per_xcp); 629 if (ret) 630 return ret; 631 } 632 633 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 634 635 for (i = 0; i < num_xcc; i++) { 636 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 637 num_xccs_per_xcp); 638 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 639 i % num_xccs_per_xcp); 640 regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL); 641 if (regval != tmp) 642 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 643 tmp); 644 } 645 646 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 647 648 return 0; 649 } 650 651 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 652 { 653 int xcc; 654 655 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 656 if (!xcc) { 657 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 658 return -EINVAL; 659 } 660 661 return xcc - 1; 662 } 663 664 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 665 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 666 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 667 .read_wave_data = &gfx_v9_4_3_read_wave_data, 668 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 669 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 670 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 671 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 672 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 673 }; 674 675 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 676 { 677 u32 gb_addr_config; 678 679 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 680 adev->gfx.ras = &gfx_v9_4_3_ras; 681 682 switch (adev->ip_versions[GC_HWIP][0]) { 683 case IP_VERSION(9, 4, 3): 684 adev->gfx.config.max_hw_contexts = 8; 685 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 686 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 687 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 688 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 689 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 690 break; 691 default: 692 BUG(); 693 break; 694 } 695 696 adev->gfx.config.gb_addr_config = gb_addr_config; 697 698 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 699 REG_GET_FIELD( 700 adev->gfx.config.gb_addr_config, 701 GB_ADDR_CONFIG, 702 NUM_PIPES); 703 704 adev->gfx.config.max_tile_pipes = 705 adev->gfx.config.gb_addr_config_fields.num_pipes; 706 707 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 708 REG_GET_FIELD( 709 adev->gfx.config.gb_addr_config, 710 GB_ADDR_CONFIG, 711 NUM_BANKS); 712 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 713 REG_GET_FIELD( 714 adev->gfx.config.gb_addr_config, 715 GB_ADDR_CONFIG, 716 MAX_COMPRESSED_FRAGS); 717 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 718 REG_GET_FIELD( 719 adev->gfx.config.gb_addr_config, 720 GB_ADDR_CONFIG, 721 NUM_RB_PER_SE); 722 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 723 REG_GET_FIELD( 724 adev->gfx.config.gb_addr_config, 725 GB_ADDR_CONFIG, 726 NUM_SHADER_ENGINES); 727 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 728 REG_GET_FIELD( 729 adev->gfx.config.gb_addr_config, 730 GB_ADDR_CONFIG, 731 PIPE_INTERLEAVE_SIZE)); 732 733 return 0; 734 } 735 736 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 737 int xcc_id, int mec, int pipe, int queue) 738 { 739 unsigned irq_type; 740 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 741 unsigned int hw_prio; 742 uint32_t xcc_doorbell_start; 743 744 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 745 ring_id]; 746 747 /* mec0 is me1 */ 748 ring->xcc_id = xcc_id; 749 ring->me = mec + 1; 750 ring->pipe = pipe; 751 ring->queue = queue; 752 753 ring->ring_obj = NULL; 754 ring->use_doorbell = true; 755 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 756 xcc_id * adev->doorbell_index.xcc_doorbell_range; 757 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 758 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 759 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 760 GFX9_MEC_HPD_SIZE; 761 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 762 sprintf(ring->name, "comp_%d.%d.%d.%d", 763 ring->xcc_id, ring->me, ring->pipe, ring->queue); 764 765 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 766 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 767 + ring->pipe; 768 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 769 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 770 /* type-2 packets are deprecated on MEC, use type-3 instead */ 771 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 772 hw_prio, NULL); 773 } 774 775 static int gfx_v9_4_3_sw_init(void *handle) 776 { 777 int i, j, k, r, ring_id, xcc_id, num_xcc; 778 struct amdgpu_kiq *kiq; 779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 780 781 adev->gfx.mec.num_mec = 2; 782 adev->gfx.mec.num_pipe_per_mec = 4; 783 adev->gfx.mec.num_queue_per_pipe = 8; 784 785 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 786 787 /* EOP Event */ 788 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 789 if (r) 790 return r; 791 792 /* Privileged reg */ 793 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 794 &adev->gfx.priv_reg_irq); 795 if (r) 796 return r; 797 798 /* Privileged inst */ 799 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 800 &adev->gfx.priv_inst_irq); 801 if (r) 802 return r; 803 804 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 805 806 r = adev->gfx.rlc.funcs->init(adev); 807 if (r) { 808 DRM_ERROR("Failed to init rlc BOs!\n"); 809 return r; 810 } 811 812 r = gfx_v9_4_3_mec_init(adev); 813 if (r) { 814 DRM_ERROR("Failed to init MEC BOs!\n"); 815 return r; 816 } 817 818 /* set up the compute queues - allocate horizontally across pipes */ 819 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 820 ring_id = 0; 821 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 822 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 823 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 824 k++) { 825 if (!amdgpu_gfx_is_mec_queue_enabled( 826 adev, xcc_id, i, k, j)) 827 continue; 828 829 r = gfx_v9_4_3_compute_ring_init(adev, 830 ring_id, 831 xcc_id, 832 i, k, j); 833 if (r) 834 return r; 835 836 ring_id++; 837 } 838 } 839 } 840 841 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 842 if (r) { 843 DRM_ERROR("Failed to init KIQ BOs!\n"); 844 return r; 845 } 846 847 kiq = &adev->gfx.kiq[xcc_id]; 848 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 849 if (r) 850 return r; 851 852 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 853 r = amdgpu_gfx_mqd_sw_init(adev, 854 sizeof(struct v9_mqd_allocation), xcc_id); 855 if (r) 856 return r; 857 } 858 859 r = gfx_v9_4_3_gpu_early_init(adev); 860 if (r) 861 return r; 862 863 r = amdgpu_gfx_sysfs_init(adev); 864 if (r) 865 return r; 866 867 return amdgpu_gfx_ras_sw_init(adev); 868 } 869 870 static int gfx_v9_4_3_sw_fini(void *handle) 871 { 872 int i, num_xcc; 873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 874 875 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 876 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 877 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 878 879 for (i = 0; i < num_xcc; i++) { 880 amdgpu_gfx_mqd_sw_fini(adev, i); 881 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 882 amdgpu_gfx_kiq_fini(adev, i); 883 } 884 885 gfx_v9_4_3_mec_fini(adev); 886 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 887 gfx_v9_4_3_free_microcode(adev); 888 amdgpu_gfx_sysfs_fini(adev); 889 890 return 0; 891 } 892 893 #define DEFAULT_SH_MEM_BASES (0x6000) 894 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 895 int xcc_id) 896 { 897 int i; 898 uint32_t sh_mem_config; 899 uint32_t sh_mem_bases; 900 uint32_t data; 901 902 /* 903 * Configure apertures: 904 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 905 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 906 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 907 */ 908 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 909 910 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 911 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 912 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 913 914 mutex_lock(&adev->srbm_mutex); 915 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 916 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 917 /* CP and shaders */ 918 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 919 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 920 921 /* Enable trap for each kfd vmid. */ 922 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 923 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 924 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 925 } 926 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 927 mutex_unlock(&adev->srbm_mutex); 928 929 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 930 acccess. These should be enabled by FW for target VMIDs. */ 931 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 932 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 933 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 934 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 935 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 936 } 937 } 938 939 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 940 { 941 int vmid; 942 943 /* 944 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 945 * access. Compute VMIDs should be enabled by FW for target VMIDs, 946 * the driver can enable them for graphics. VMID0 should maintain 947 * access so that HWS firmware can save/restore entries. 948 */ 949 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 950 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 951 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 952 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 953 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 954 } 955 } 956 957 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 958 int xcc_id) 959 { 960 u32 tmp; 961 int i; 962 963 /* XXX SH_MEM regs */ 964 /* where to put LDS, scratch, GPUVM in FSA64 space */ 965 mutex_lock(&adev->srbm_mutex); 966 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 967 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 968 /* CP and shaders */ 969 if (i == 0) { 970 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 971 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 972 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 973 !!adev->gmc.noretry); 974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 975 regSH_MEM_CONFIG, tmp); 976 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 977 regSH_MEM_BASES, 0); 978 } else { 979 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 980 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 981 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 982 !!adev->gmc.noretry); 983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 984 regSH_MEM_CONFIG, tmp); 985 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 986 (adev->gmc.private_aperture_start >> 987 48)); 988 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 989 (adev->gmc.shared_aperture_start >> 990 48)); 991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 992 regSH_MEM_BASES, tmp); 993 } 994 } 995 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 996 997 mutex_unlock(&adev->srbm_mutex); 998 999 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1000 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1001 } 1002 1003 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1004 { 1005 int i, num_xcc; 1006 1007 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1008 1009 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1010 adev->gfx.config.db_debug2 = 1011 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1012 1013 for (i = 0; i < num_xcc; i++) 1014 gfx_v9_4_3_xcc_constants_init(adev, i); 1015 } 1016 1017 static void 1018 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1019 int xcc_id) 1020 { 1021 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1022 } 1023 1024 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1025 { 1026 /* 1027 * Rlc save restore list is workable since v2_1. 1028 * And it's needed by gfxoff feature. 1029 */ 1030 if (adev->gfx.rlc.is_rlc_v2_1) 1031 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1032 } 1033 1034 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1035 { 1036 uint32_t data; 1037 1038 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1039 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1040 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1041 } 1042 1043 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1044 { 1045 uint32_t rlc_setting; 1046 1047 /* if RLC is not enabled, do nothing */ 1048 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1049 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1050 return false; 1051 1052 return true; 1053 } 1054 1055 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1056 { 1057 uint32_t data; 1058 unsigned i; 1059 1060 data = RLC_SAFE_MODE__CMD_MASK; 1061 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1062 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1063 1064 /* wait for RLC_SAFE_MODE */ 1065 for (i = 0; i < adev->usec_timeout; i++) { 1066 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1067 break; 1068 udelay(1); 1069 } 1070 } 1071 1072 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1073 int xcc_id) 1074 { 1075 uint32_t data; 1076 1077 data = RLC_SAFE_MODE__CMD_MASK; 1078 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1079 } 1080 1081 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1082 { 1083 int xcc_id, num_xcc; 1084 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1085 1086 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1087 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1088 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1089 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1090 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1091 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1092 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1093 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1094 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1095 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1096 } 1097 } 1098 1099 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1100 { 1101 /* init spm vmid with 0xf */ 1102 if (adev->gfx.rlc.funcs->update_spm_vmid) 1103 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1104 1105 return 0; 1106 } 1107 1108 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1109 int xcc_id) 1110 { 1111 u32 i, j, k; 1112 u32 mask; 1113 1114 mutex_lock(&adev->grbm_idx_mutex); 1115 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1116 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1117 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1118 xcc_id); 1119 for (k = 0; k < adev->usec_timeout; k++) { 1120 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1121 break; 1122 udelay(1); 1123 } 1124 if (k == adev->usec_timeout) { 1125 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1126 0xffffffff, 1127 0xffffffff, xcc_id); 1128 mutex_unlock(&adev->grbm_idx_mutex); 1129 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1130 i, j); 1131 return; 1132 } 1133 } 1134 } 1135 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1136 xcc_id); 1137 mutex_unlock(&adev->grbm_idx_mutex); 1138 1139 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1140 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1141 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1142 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1143 for (k = 0; k < adev->usec_timeout; k++) { 1144 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1145 break; 1146 udelay(1); 1147 } 1148 } 1149 1150 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1151 bool enable, int xcc_id) 1152 { 1153 u32 tmp; 1154 1155 /* These interrupts should be enabled to drive DS clock */ 1156 1157 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1158 1159 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1160 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1161 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1162 1163 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1164 } 1165 1166 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1167 { 1168 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1169 RLC_ENABLE_F32, 0); 1170 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1171 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1172 } 1173 1174 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1175 { 1176 int i, num_xcc; 1177 1178 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1179 for (i = 0; i < num_xcc; i++) 1180 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1181 } 1182 1183 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1184 { 1185 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1186 SOFT_RESET_RLC, 1); 1187 udelay(50); 1188 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1189 SOFT_RESET_RLC, 0); 1190 udelay(50); 1191 } 1192 1193 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1194 { 1195 int i, num_xcc; 1196 1197 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1198 for (i = 0; i < num_xcc; i++) 1199 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1200 } 1201 1202 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1203 { 1204 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1205 RLC_ENABLE_F32, 1); 1206 udelay(50); 1207 1208 /* carrizo do enable cp interrupt after cp inited */ 1209 if (!(adev->flags & AMD_IS_APU)) { 1210 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1211 udelay(50); 1212 } 1213 } 1214 1215 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1216 { 1217 #ifdef AMDGPU_RLC_DEBUG_RETRY 1218 u32 rlc_ucode_ver; 1219 #endif 1220 int i, num_xcc; 1221 1222 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1223 for (i = 0; i < num_xcc; i++) { 1224 gfx_v9_4_3_xcc_rlc_start(adev, i); 1225 #ifdef AMDGPU_RLC_DEBUG_RETRY 1226 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1227 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1228 if (rlc_ucode_ver == 0x108) { 1229 dev_info(adev->dev, 1230 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1231 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1232 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1233 * default is 0x9C4 to create a 100us interval */ 1234 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1235 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1236 * to disable the page fault retry interrupts, default is 1237 * 0x100 (256) */ 1238 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1239 } 1240 #endif 1241 } 1242 } 1243 1244 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1245 int xcc_id) 1246 { 1247 const struct rlc_firmware_header_v2_0 *hdr; 1248 const __le32 *fw_data; 1249 unsigned i, fw_size; 1250 1251 if (!adev->gfx.rlc_fw) 1252 return -EINVAL; 1253 1254 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1255 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1256 1257 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1258 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1259 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1260 1261 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1262 RLCG_UCODE_LOADING_START_ADDRESS); 1263 for (i = 0; i < fw_size; i++) { 1264 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1265 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1266 msleep(1); 1267 } 1268 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1269 } 1270 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1271 1272 return 0; 1273 } 1274 1275 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1276 { 1277 int r; 1278 1279 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1280 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1281 /* legacy rlc firmware loading */ 1282 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1283 if (r) 1284 return r; 1285 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1286 } 1287 1288 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1289 /* disable CG */ 1290 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1291 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1292 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1293 1294 return 0; 1295 } 1296 1297 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1298 { 1299 int r, i, num_xcc; 1300 1301 if (amdgpu_sriov_vf(adev)) 1302 return 0; 1303 1304 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1305 for (i = 0; i < num_xcc; i++) { 1306 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1307 if (r) 1308 return r; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1315 unsigned vmid) 1316 { 1317 u32 reg, data; 1318 1319 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1320 if (amdgpu_sriov_is_pp_one_vf(adev)) 1321 data = RREG32_NO_KIQ(reg); 1322 else 1323 data = RREG32(reg); 1324 1325 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1326 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1327 1328 if (amdgpu_sriov_is_pp_one_vf(adev)) 1329 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1330 else 1331 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1332 } 1333 1334 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1335 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1336 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1337 }; 1338 1339 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1340 uint32_t offset, 1341 struct soc15_reg_rlcg *entries, int arr_size) 1342 { 1343 int i, inst; 1344 uint32_t reg; 1345 1346 if (!entries) 1347 return false; 1348 1349 for (i = 0; i < arr_size; i++) { 1350 const struct soc15_reg_rlcg *entry; 1351 1352 entry = &entries[i]; 1353 inst = adev->ip_map.logical_to_dev_inst ? 1354 adev->ip_map.logical_to_dev_inst( 1355 adev, entry->hwip, entry->instance) : 1356 entry->instance; 1357 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1358 entry->reg; 1359 if (offset == reg) 1360 return true; 1361 } 1362 1363 return false; 1364 } 1365 1366 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1367 { 1368 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1369 (void *)rlcg_access_gc_9_4_3, 1370 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1371 } 1372 1373 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1374 bool enable, int xcc_id) 1375 { 1376 if (enable) { 1377 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1378 } else { 1379 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1380 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1381 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1382 } 1383 udelay(50); 1384 } 1385 1386 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1387 int xcc_id) 1388 { 1389 const struct gfx_firmware_header_v1_0 *mec_hdr; 1390 const __le32 *fw_data; 1391 unsigned i; 1392 u32 tmp; 1393 u32 mec_ucode_addr_offset; 1394 u32 mec_ucode_data_offset; 1395 1396 if (!adev->gfx.mec_fw) 1397 return -EINVAL; 1398 1399 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1400 1401 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1402 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1403 1404 fw_data = (const __le32 *) 1405 (adev->gfx.mec_fw->data + 1406 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1407 tmp = 0; 1408 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1409 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1410 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1411 1412 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1413 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1415 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1416 1417 mec_ucode_addr_offset = 1418 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1419 mec_ucode_data_offset = 1420 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1421 1422 /* MEC1 */ 1423 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1424 for (i = 0; i < mec_hdr->jt_size; i++) 1425 WREG32(mec_ucode_data_offset, 1426 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1427 1428 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1429 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1430 1431 return 0; 1432 } 1433 1434 /* KIQ functions */ 1435 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1436 { 1437 uint32_t tmp; 1438 struct amdgpu_device *adev = ring->adev; 1439 1440 /* tell RLC which is KIQ queue */ 1441 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1442 tmp &= 0xffffff00; 1443 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1444 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1445 tmp |= 0x80; 1446 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1447 } 1448 1449 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1450 { 1451 struct amdgpu_device *adev = ring->adev; 1452 1453 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1454 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1455 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1456 mqd->cp_hqd_queue_priority = 1457 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1458 } 1459 } 1460 } 1461 1462 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1463 { 1464 struct amdgpu_device *adev = ring->adev; 1465 struct v9_mqd *mqd = ring->mqd_ptr; 1466 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1467 uint32_t tmp; 1468 1469 mqd->header = 0xC0310800; 1470 mqd->compute_pipelinestat_enable = 0x00000001; 1471 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1472 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1473 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1474 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1475 mqd->compute_misc_reserved = 0x00000003; 1476 1477 mqd->dynamic_cu_mask_addr_lo = 1478 lower_32_bits(ring->mqd_gpu_addr 1479 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1480 mqd->dynamic_cu_mask_addr_hi = 1481 upper_32_bits(ring->mqd_gpu_addr 1482 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1483 1484 eop_base_addr = ring->eop_gpu_addr >> 8; 1485 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1486 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1487 1488 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1489 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1490 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1491 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1492 1493 mqd->cp_hqd_eop_control = tmp; 1494 1495 /* enable doorbell? */ 1496 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1497 1498 if (ring->use_doorbell) { 1499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1500 DOORBELL_OFFSET, ring->doorbell_index); 1501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1502 DOORBELL_EN, 1); 1503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1504 DOORBELL_SOURCE, 0); 1505 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1506 DOORBELL_HIT, 0); 1507 } else { 1508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1509 DOORBELL_EN, 0); 1510 } 1511 1512 mqd->cp_hqd_pq_doorbell_control = tmp; 1513 1514 /* disable the queue if it's active */ 1515 ring->wptr = 0; 1516 mqd->cp_hqd_dequeue_request = 0; 1517 mqd->cp_hqd_pq_rptr = 0; 1518 mqd->cp_hqd_pq_wptr_lo = 0; 1519 mqd->cp_hqd_pq_wptr_hi = 0; 1520 1521 /* set the pointer to the MQD */ 1522 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1523 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1524 1525 /* set MQD vmid to 0 */ 1526 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1527 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1528 mqd->cp_mqd_control = tmp; 1529 1530 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1531 hqd_gpu_addr = ring->gpu_addr >> 8; 1532 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1533 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1534 1535 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1536 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1538 (order_base_2(ring->ring_size / 4) - 1)); 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1540 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1541 #ifdef __BIG_ENDIAN 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1543 #endif 1544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1548 mqd->cp_hqd_pq_control = tmp; 1549 1550 /* set the wb address whether it's enabled or not */ 1551 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1552 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1553 mqd->cp_hqd_pq_rptr_report_addr_hi = 1554 upper_32_bits(wb_gpu_addr) & 0xffff; 1555 1556 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1557 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1558 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1559 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1560 1561 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1562 ring->wptr = 0; 1563 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1564 1565 /* set the vmid for the queue */ 1566 mqd->cp_hqd_vmid = 0; 1567 1568 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1569 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1570 mqd->cp_hqd_persistent_state = tmp; 1571 1572 /* set MIN_IB_AVAIL_SIZE */ 1573 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1574 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1575 mqd->cp_hqd_ib_control = tmp; 1576 1577 /* set static priority for a queue/ring */ 1578 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1579 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1580 1581 /* map_queues packet doesn't need activate the queue, 1582 * so only kiq need set this field. 1583 */ 1584 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1585 mqd->cp_hqd_active = 1; 1586 1587 return 0; 1588 } 1589 1590 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1591 int xcc_id) 1592 { 1593 struct amdgpu_device *adev = ring->adev; 1594 struct v9_mqd *mqd = ring->mqd_ptr; 1595 int j; 1596 1597 /* disable wptr polling */ 1598 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1599 1600 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1601 mqd->cp_hqd_eop_base_addr_lo); 1602 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1603 mqd->cp_hqd_eop_base_addr_hi); 1604 1605 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1606 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1607 mqd->cp_hqd_eop_control); 1608 1609 /* enable doorbell? */ 1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1611 mqd->cp_hqd_pq_doorbell_control); 1612 1613 /* disable the queue if it's active */ 1614 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1615 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1616 for (j = 0; j < adev->usec_timeout; j++) { 1617 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1618 break; 1619 udelay(1); 1620 } 1621 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1622 mqd->cp_hqd_dequeue_request); 1623 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1624 mqd->cp_hqd_pq_rptr); 1625 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1626 mqd->cp_hqd_pq_wptr_lo); 1627 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1628 mqd->cp_hqd_pq_wptr_hi); 1629 } 1630 1631 /* set the pointer to the MQD */ 1632 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1633 mqd->cp_mqd_base_addr_lo); 1634 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1635 mqd->cp_mqd_base_addr_hi); 1636 1637 /* set MQD vmid to 0 */ 1638 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1639 mqd->cp_mqd_control); 1640 1641 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1642 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1643 mqd->cp_hqd_pq_base_lo); 1644 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1645 mqd->cp_hqd_pq_base_hi); 1646 1647 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1648 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1649 mqd->cp_hqd_pq_control); 1650 1651 /* set the wb address whether it's enabled or not */ 1652 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1653 mqd->cp_hqd_pq_rptr_report_addr_lo); 1654 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1655 mqd->cp_hqd_pq_rptr_report_addr_hi); 1656 1657 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1658 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1659 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1660 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1661 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1662 1663 /* enable the doorbell if requested */ 1664 if (ring->use_doorbell) { 1665 WREG32_SOC15( 1666 GC, GET_INST(GC, xcc_id), 1667 regCP_MEC_DOORBELL_RANGE_LOWER, 1668 ((adev->doorbell_index.kiq + 1669 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1670 2) << 2); 1671 WREG32_SOC15( 1672 GC, GET_INST(GC, xcc_id), 1673 regCP_MEC_DOORBELL_RANGE_UPPER, 1674 ((adev->doorbell_index.userqueue_end + 1675 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1676 2) << 2); 1677 } 1678 1679 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1680 mqd->cp_hqd_pq_doorbell_control); 1681 1682 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1683 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1684 mqd->cp_hqd_pq_wptr_lo); 1685 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1686 mqd->cp_hqd_pq_wptr_hi); 1687 1688 /* set the vmid for the queue */ 1689 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1690 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1692 mqd->cp_hqd_persistent_state); 1693 1694 /* activate the queue */ 1695 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1696 mqd->cp_hqd_active); 1697 1698 if (ring->use_doorbell) 1699 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1700 1701 return 0; 1702 } 1703 1704 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1705 int xcc_id) 1706 { 1707 struct amdgpu_device *adev = ring->adev; 1708 int j; 1709 1710 /* disable the queue if it's active */ 1711 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1712 1713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1714 1715 for (j = 0; j < adev->usec_timeout; j++) { 1716 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1717 break; 1718 udelay(1); 1719 } 1720 1721 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1722 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1723 1724 /* Manual disable if dequeue request times out */ 1725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1726 } 1727 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1729 0); 1730 } 1731 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1738 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1740 1741 return 0; 1742 } 1743 1744 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1745 { 1746 struct amdgpu_device *adev = ring->adev; 1747 struct v9_mqd *mqd = ring->mqd_ptr; 1748 struct v9_mqd *tmp_mqd; 1749 1750 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1751 1752 /* GPU could be in bad state during probe, driver trigger the reset 1753 * after load the SMU, in this case , the mqd is not be initialized. 1754 * driver need to re-init the mqd. 1755 * check mqd->cp_hqd_pq_control since this value should not be 0 1756 */ 1757 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1758 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1759 /* for GPU_RESET case , reset MQD to a clean status */ 1760 if (adev->gfx.kiq[xcc_id].mqd_backup) 1761 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1762 1763 /* reset ring buffer */ 1764 ring->wptr = 0; 1765 amdgpu_ring_clear_ring(ring); 1766 mutex_lock(&adev->srbm_mutex); 1767 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1768 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1769 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1770 mutex_unlock(&adev->srbm_mutex); 1771 } else { 1772 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1773 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1774 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1775 mutex_lock(&adev->srbm_mutex); 1776 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1777 amdgpu_ring_clear_ring(ring); 1778 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1779 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1780 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1781 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1782 mutex_unlock(&adev->srbm_mutex); 1783 1784 if (adev->gfx.kiq[xcc_id].mqd_backup) 1785 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1786 } 1787 1788 return 0; 1789 } 1790 1791 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1792 { 1793 struct amdgpu_device *adev = ring->adev; 1794 struct v9_mqd *mqd = ring->mqd_ptr; 1795 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1796 struct v9_mqd *tmp_mqd; 1797 1798 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1799 * is not be initialized before 1800 */ 1801 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1802 1803 if (!tmp_mqd->cp_hqd_pq_control || 1804 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1805 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1806 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1807 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1808 mutex_lock(&adev->srbm_mutex); 1809 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1810 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1811 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1812 mutex_unlock(&adev->srbm_mutex); 1813 1814 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1815 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1816 } else { 1817 /* restore MQD to a clean status */ 1818 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1819 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1820 /* reset ring buffer */ 1821 ring->wptr = 0; 1822 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1823 amdgpu_ring_clear_ring(ring); 1824 } 1825 1826 return 0; 1827 } 1828 1829 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1830 { 1831 struct amdgpu_ring *ring; 1832 int j; 1833 1834 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1835 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1836 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1837 mutex_lock(&adev->srbm_mutex); 1838 soc15_grbm_select(adev, ring->me, 1839 ring->pipe, 1840 ring->queue, 0, GET_INST(GC, xcc_id)); 1841 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1842 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1843 mutex_unlock(&adev->srbm_mutex); 1844 } 1845 } 1846 1847 return 0; 1848 } 1849 1850 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1851 { 1852 struct amdgpu_ring *ring; 1853 int r; 1854 1855 ring = &adev->gfx.kiq[xcc_id].ring; 1856 1857 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1858 if (unlikely(r != 0)) 1859 return r; 1860 1861 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1862 if (unlikely(r != 0)) { 1863 amdgpu_bo_unreserve(ring->mqd_obj); 1864 return r; 1865 } 1866 1867 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1868 amdgpu_bo_kunmap(ring->mqd_obj); 1869 ring->mqd_ptr = NULL; 1870 amdgpu_bo_unreserve(ring->mqd_obj); 1871 return 0; 1872 } 1873 1874 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1875 { 1876 struct amdgpu_ring *ring = NULL; 1877 int r = 0, i; 1878 1879 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1880 1881 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1882 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1883 1884 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1885 if (unlikely(r != 0)) 1886 goto done; 1887 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1888 if (!r) { 1889 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1890 amdgpu_bo_kunmap(ring->mqd_obj); 1891 ring->mqd_ptr = NULL; 1892 } 1893 amdgpu_bo_unreserve(ring->mqd_obj); 1894 if (r) 1895 goto done; 1896 } 1897 1898 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1899 done: 1900 return r; 1901 } 1902 1903 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1904 { 1905 struct amdgpu_ring *ring; 1906 int r, j; 1907 1908 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1909 1910 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1911 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1912 1913 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1914 if (r) 1915 return r; 1916 } 1917 1918 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1919 if (r) 1920 return r; 1921 1922 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1923 if (r) 1924 return r; 1925 1926 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1927 ring = &adev->gfx.compute_ring 1928 [j + xcc_id * adev->gfx.num_compute_rings]; 1929 r = amdgpu_ring_test_helper(ring); 1930 if (r) 1931 return r; 1932 } 1933 1934 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1935 1936 return 0; 1937 } 1938 1939 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1940 { 1941 int r = 0, i, num_xcc; 1942 1943 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1944 AMDGPU_XCP_FL_NONE) == 1945 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1946 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1947 amdgpu_user_partt_mode); 1948 1949 if (r) 1950 return r; 1951 1952 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1953 for (i = 0; i < num_xcc; i++) { 1954 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1955 if (r) 1956 return r; 1957 } 1958 1959 return 0; 1960 } 1961 1962 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1963 int xcc_id) 1964 { 1965 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1966 } 1967 1968 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1969 { 1970 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1971 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1972 1973 if (amdgpu_sriov_vf(adev)) { 1974 /* must disable polling for SRIOV when hw finished, otherwise 1975 * CPC engine may still keep fetching WB address which is already 1976 * invalid after sw finished and trigger DMAR reading error in 1977 * hypervisor side. 1978 */ 1979 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1980 return; 1981 } 1982 1983 /* Use deinitialize sequence from CAIL when unbinding device 1984 * from driver, otherwise KIQ is hanging when binding back 1985 */ 1986 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1987 mutex_lock(&adev->srbm_mutex); 1988 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1989 adev->gfx.kiq[xcc_id].ring.pipe, 1990 adev->gfx.kiq[xcc_id].ring.queue, 0, 1991 GET_INST(GC, xcc_id)); 1992 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1993 xcc_id); 1994 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1995 mutex_unlock(&adev->srbm_mutex); 1996 } 1997 1998 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 1999 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2000 } 2001 2002 static int gfx_v9_4_3_hw_init(void *handle) 2003 { 2004 int r; 2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2006 2007 if (!amdgpu_sriov_vf(adev)) 2008 gfx_v9_4_3_init_golden_registers(adev); 2009 2010 gfx_v9_4_3_constants_init(adev); 2011 2012 r = adev->gfx.rlc.funcs->resume(adev); 2013 if (r) 2014 return r; 2015 2016 r = gfx_v9_4_3_cp_resume(adev); 2017 if (r) 2018 return r; 2019 2020 return r; 2021 } 2022 2023 static int gfx_v9_4_3_hw_fini(void *handle) 2024 { 2025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2026 int i, num_xcc; 2027 2028 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2029 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2030 2031 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2032 for (i = 0; i < num_xcc; i++) { 2033 gfx_v9_4_3_xcc_fini(adev, i); 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int gfx_v9_4_3_suspend(void *handle) 2040 { 2041 return gfx_v9_4_3_hw_fini(handle); 2042 } 2043 2044 static int gfx_v9_4_3_resume(void *handle) 2045 { 2046 return gfx_v9_4_3_hw_init(handle); 2047 } 2048 2049 static bool gfx_v9_4_3_is_idle(void *handle) 2050 { 2051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2052 int i, num_xcc; 2053 2054 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2055 for (i = 0; i < num_xcc; i++) { 2056 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2057 GRBM_STATUS, GUI_ACTIVE)) 2058 return false; 2059 } 2060 return true; 2061 } 2062 2063 static int gfx_v9_4_3_wait_for_idle(void *handle) 2064 { 2065 unsigned i; 2066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2067 2068 for (i = 0; i < adev->usec_timeout; i++) { 2069 if (gfx_v9_4_3_is_idle(handle)) 2070 return 0; 2071 udelay(1); 2072 } 2073 return -ETIMEDOUT; 2074 } 2075 2076 static int gfx_v9_4_3_soft_reset(void *handle) 2077 { 2078 u32 grbm_soft_reset = 0; 2079 u32 tmp; 2080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2081 2082 /* GRBM_STATUS */ 2083 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2084 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2085 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2086 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2087 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2088 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2089 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2090 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2091 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2093 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2094 } 2095 2096 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2097 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2098 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2099 } 2100 2101 /* GRBM_STATUS2 */ 2102 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2103 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2104 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2105 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2106 2107 2108 if (grbm_soft_reset) { 2109 /* stop the rlc */ 2110 adev->gfx.rlc.funcs->stop(adev); 2111 2112 /* Disable MEC parsing/prefetching */ 2113 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2114 2115 if (grbm_soft_reset) { 2116 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2117 tmp |= grbm_soft_reset; 2118 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2119 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2120 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2121 2122 udelay(50); 2123 2124 tmp &= ~grbm_soft_reset; 2125 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2126 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2127 } 2128 2129 /* Wait a little for things to settle down */ 2130 udelay(50); 2131 } 2132 return 0; 2133 } 2134 2135 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2136 uint32_t vmid, 2137 uint32_t gds_base, uint32_t gds_size, 2138 uint32_t gws_base, uint32_t gws_size, 2139 uint32_t oa_base, uint32_t oa_size) 2140 { 2141 struct amdgpu_device *adev = ring->adev; 2142 2143 /* GDS Base */ 2144 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2145 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2146 gds_base); 2147 2148 /* GDS Size */ 2149 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2150 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2151 gds_size); 2152 2153 /* GWS */ 2154 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2155 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2156 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2157 2158 /* OA */ 2159 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2160 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2161 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2162 } 2163 2164 static int gfx_v9_4_3_early_init(void *handle) 2165 { 2166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2167 2168 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2169 AMDGPU_MAX_COMPUTE_RINGS); 2170 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2171 gfx_v9_4_3_set_ring_funcs(adev); 2172 gfx_v9_4_3_set_irq_funcs(adev); 2173 gfx_v9_4_3_set_gds_init(adev); 2174 gfx_v9_4_3_set_rlc_funcs(adev); 2175 2176 /* init rlcg reg access ctrl */ 2177 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2178 2179 return gfx_v9_4_3_init_microcode(adev); 2180 } 2181 2182 static int gfx_v9_4_3_late_init(void *handle) 2183 { 2184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2185 int r; 2186 2187 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2188 if (r) 2189 return r; 2190 2191 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2192 if (r) 2193 return r; 2194 2195 if (adev->gfx.ras && 2196 adev->gfx.ras->enable_watchdog_timer) 2197 adev->gfx.ras->enable_watchdog_timer(adev); 2198 2199 return 0; 2200 } 2201 2202 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2203 bool enable, int xcc_id) 2204 { 2205 uint32_t def, data; 2206 2207 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2208 return; 2209 2210 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2211 regRLC_CGTT_MGCG_OVERRIDE); 2212 2213 if (enable) 2214 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2215 else 2216 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2217 2218 if (def != data) 2219 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2220 regRLC_CGTT_MGCG_OVERRIDE, data); 2221 2222 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2223 2224 if (enable) 2225 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2226 else 2227 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2228 2229 if (def != data) 2230 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2231 } 2232 2233 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2234 bool enable, int xcc_id) 2235 { 2236 uint32_t def, data; 2237 2238 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2239 return; 2240 2241 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2242 regRLC_CGTT_MGCG_OVERRIDE); 2243 2244 if (enable) 2245 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2246 else 2247 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2248 2249 if (def != data) 2250 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2251 regRLC_CGTT_MGCG_OVERRIDE, data); 2252 } 2253 2254 static void 2255 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2256 bool enable, int xcc_id) 2257 { 2258 uint32_t data, def; 2259 2260 /* It is disabled by HW by default */ 2261 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2262 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2263 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2264 2265 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2267 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2268 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2269 2270 if (def != data) 2271 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2272 2273 /* MGLS is a global flag to control all MGLS in GFX */ 2274 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2275 /* 2 - RLC memory Light sleep */ 2276 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2277 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2278 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2279 if (def != data) 2280 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2281 } 2282 /* 3 - CP memory Light sleep */ 2283 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2284 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2285 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2286 if (def != data) 2287 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2288 } 2289 } 2290 } else { 2291 /* 1 - MGCG_OVERRIDE */ 2292 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2293 2294 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2295 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2296 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2297 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2298 2299 if (def != data) 2300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2301 2302 /* 2 - disable MGLS in RLC */ 2303 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2304 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2305 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2306 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2307 } 2308 2309 /* 3 - disable MGLS in CP */ 2310 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2311 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2312 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2313 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2314 } 2315 } 2316 2317 } 2318 2319 static void 2320 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2321 bool enable, int xcc_id) 2322 { 2323 uint32_t def, data; 2324 2325 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2326 2327 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2328 /* unset CGCG override */ 2329 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2330 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2331 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2332 else 2333 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2334 /* update CGCG and CGLS override bits */ 2335 if (def != data) 2336 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2337 2338 /* enable cgcg FSM(0x0000363F) */ 2339 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2340 2341 data = (0x36 2342 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2343 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2344 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2345 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2346 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2347 if (def != data) 2348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2349 2350 /* set IDLE_POLL_COUNT(0x00900100) */ 2351 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2352 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2353 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2354 if (def != data) 2355 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2356 } else { 2357 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2358 /* reset CGCG/CGLS bits */ 2359 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2360 /* disable cgcg and cgls in FSM */ 2361 if (def != data) 2362 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2363 } 2364 2365 } 2366 2367 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2368 bool enable, int xcc_id) 2369 { 2370 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2371 2372 if (enable) { 2373 /* FGCG */ 2374 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2375 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2376 2377 /* CGCG/CGLS should be enabled after MGCG/MGLS 2378 * === MGCG + MGLS === 2379 */ 2380 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2381 xcc_id); 2382 /* === CGCG + CGLS === */ 2383 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2384 xcc_id); 2385 } else { 2386 /* CGCG/CGLS should be disabled before MGCG/MGLS 2387 * === CGCG + CGLS === 2388 */ 2389 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2390 xcc_id); 2391 /* === MGCG + MGLS === */ 2392 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2393 xcc_id); 2394 2395 /* FGCG */ 2396 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2397 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2398 } 2399 2400 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2401 2402 return 0; 2403 } 2404 2405 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2406 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2407 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2408 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2409 .init = gfx_v9_4_3_rlc_init, 2410 .resume = gfx_v9_4_3_rlc_resume, 2411 .stop = gfx_v9_4_3_rlc_stop, 2412 .reset = gfx_v9_4_3_rlc_reset, 2413 .start = gfx_v9_4_3_rlc_start, 2414 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2415 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2416 }; 2417 2418 static int gfx_v9_4_3_set_powergating_state(void *handle, 2419 enum amd_powergating_state state) 2420 { 2421 return 0; 2422 } 2423 2424 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2425 enum amd_clockgating_state state) 2426 { 2427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2428 int i, num_xcc; 2429 2430 if (amdgpu_sriov_vf(adev)) 2431 return 0; 2432 2433 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2434 switch (adev->ip_versions[GC_HWIP][0]) { 2435 case IP_VERSION(9, 4, 3): 2436 for (i = 0; i < num_xcc; i++) 2437 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2438 adev, state == AMD_CG_STATE_GATE, i); 2439 break; 2440 default: 2441 break; 2442 } 2443 return 0; 2444 } 2445 2446 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2447 { 2448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2449 int data; 2450 2451 if (amdgpu_sriov_vf(adev)) 2452 *flags = 0; 2453 2454 /* AMD_CG_SUPPORT_GFX_MGCG */ 2455 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2456 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2457 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2458 2459 /* AMD_CG_SUPPORT_GFX_CGCG */ 2460 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2461 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2462 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2463 2464 /* AMD_CG_SUPPORT_GFX_CGLS */ 2465 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2466 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2467 2468 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2469 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2470 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2471 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2472 2473 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2474 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2475 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2476 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2477 } 2478 2479 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2480 { 2481 struct amdgpu_device *adev = ring->adev; 2482 u32 ref_and_mask, reg_mem_engine; 2483 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2484 2485 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2486 switch (ring->me) { 2487 case 1: 2488 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2489 break; 2490 case 2: 2491 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2492 break; 2493 default: 2494 return; 2495 } 2496 reg_mem_engine = 0; 2497 } else { 2498 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2499 reg_mem_engine = 1; /* pfp */ 2500 } 2501 2502 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2503 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2504 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2505 ref_and_mask, ref_and_mask, 0x20); 2506 } 2507 2508 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2509 struct amdgpu_job *job, 2510 struct amdgpu_ib *ib, 2511 uint32_t flags) 2512 { 2513 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2514 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2515 2516 /* Currently, there is a high possibility to get wave ID mismatch 2517 * between ME and GDS, leading to a hw deadlock, because ME generates 2518 * different wave IDs than the GDS expects. This situation happens 2519 * randomly when at least 5 compute pipes use GDS ordered append. 2520 * The wave IDs generated by ME are also wrong after suspend/resume. 2521 * Those are probably bugs somewhere else in the kernel driver. 2522 * 2523 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2524 * GDS to 0 for this ring (me/pipe). 2525 */ 2526 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2527 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2528 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2529 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2530 } 2531 2532 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2533 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2534 amdgpu_ring_write(ring, 2535 #ifdef __BIG_ENDIAN 2536 (2 << 0) | 2537 #endif 2538 lower_32_bits(ib->gpu_addr)); 2539 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2540 amdgpu_ring_write(ring, control); 2541 } 2542 2543 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2544 u64 seq, unsigned flags) 2545 { 2546 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2547 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2548 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2549 2550 /* RELEASE_MEM - flush caches, send int */ 2551 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2552 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2553 EOP_TC_NC_ACTION_EN) : 2554 (EOP_TCL1_ACTION_EN | 2555 EOP_TC_ACTION_EN | 2556 EOP_TC_WB_ACTION_EN | 2557 EOP_TC_MD_ACTION_EN)) | 2558 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2559 EVENT_INDEX(5))); 2560 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2561 2562 /* 2563 * the address should be Qword aligned if 64bit write, Dword 2564 * aligned if only send 32bit data low (discard data high) 2565 */ 2566 if (write64bit) 2567 BUG_ON(addr & 0x7); 2568 else 2569 BUG_ON(addr & 0x3); 2570 amdgpu_ring_write(ring, lower_32_bits(addr)); 2571 amdgpu_ring_write(ring, upper_32_bits(addr)); 2572 amdgpu_ring_write(ring, lower_32_bits(seq)); 2573 amdgpu_ring_write(ring, upper_32_bits(seq)); 2574 amdgpu_ring_write(ring, 0); 2575 } 2576 2577 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2578 { 2579 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2580 uint32_t seq = ring->fence_drv.sync_seq; 2581 uint64_t addr = ring->fence_drv.gpu_addr; 2582 2583 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2584 lower_32_bits(addr), upper_32_bits(addr), 2585 seq, 0xffffffff, 4); 2586 } 2587 2588 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2589 unsigned vmid, uint64_t pd_addr) 2590 { 2591 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2592 } 2593 2594 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2595 { 2596 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2597 } 2598 2599 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2600 { 2601 u64 wptr; 2602 2603 /* XXX check if swapping is necessary on BE */ 2604 if (ring->use_doorbell) 2605 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2606 else 2607 BUG(); 2608 return wptr; 2609 } 2610 2611 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2612 { 2613 struct amdgpu_device *adev = ring->adev; 2614 2615 /* XXX check if swapping is necessary on BE */ 2616 if (ring->use_doorbell) { 2617 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2618 WDOORBELL64(ring->doorbell_index, ring->wptr); 2619 } else { 2620 BUG(); /* only DOORBELL method supported on gfx9 now */ 2621 } 2622 } 2623 2624 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2625 u64 seq, unsigned int flags) 2626 { 2627 struct amdgpu_device *adev = ring->adev; 2628 2629 /* we only allocate 32bit for each seq wb address */ 2630 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2631 2632 /* write fence seq to the "addr" */ 2633 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2634 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2635 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2636 amdgpu_ring_write(ring, lower_32_bits(addr)); 2637 amdgpu_ring_write(ring, upper_32_bits(addr)); 2638 amdgpu_ring_write(ring, lower_32_bits(seq)); 2639 2640 if (flags & AMDGPU_FENCE_FLAG_INT) { 2641 /* set register to trigger INT */ 2642 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2643 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2644 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2645 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2646 amdgpu_ring_write(ring, 0); 2647 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2648 } 2649 } 2650 2651 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2652 uint32_t reg_val_offs) 2653 { 2654 struct amdgpu_device *adev = ring->adev; 2655 2656 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2657 amdgpu_ring_write(ring, 0 | /* src: register*/ 2658 (5 << 8) | /* dst: memory */ 2659 (1 << 20)); /* write confirm */ 2660 amdgpu_ring_write(ring, reg); 2661 amdgpu_ring_write(ring, 0); 2662 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2663 reg_val_offs * 4)); 2664 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2665 reg_val_offs * 4)); 2666 } 2667 2668 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2669 uint32_t val) 2670 { 2671 uint32_t cmd = 0; 2672 2673 switch (ring->funcs->type) { 2674 case AMDGPU_RING_TYPE_GFX: 2675 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2676 break; 2677 case AMDGPU_RING_TYPE_KIQ: 2678 cmd = (1 << 16); /* no inc addr */ 2679 break; 2680 default: 2681 cmd = WR_CONFIRM; 2682 break; 2683 } 2684 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2685 amdgpu_ring_write(ring, cmd); 2686 amdgpu_ring_write(ring, reg); 2687 amdgpu_ring_write(ring, 0); 2688 amdgpu_ring_write(ring, val); 2689 } 2690 2691 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2692 uint32_t val, uint32_t mask) 2693 { 2694 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2695 } 2696 2697 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2698 uint32_t reg0, uint32_t reg1, 2699 uint32_t ref, uint32_t mask) 2700 { 2701 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2702 ref, mask); 2703 } 2704 2705 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2706 struct amdgpu_device *adev, int me, int pipe, 2707 enum amdgpu_interrupt_state state, int xcc_id) 2708 { 2709 u32 mec_int_cntl, mec_int_cntl_reg; 2710 2711 /* 2712 * amdgpu controls only the first MEC. That's why this function only 2713 * handles the setting of interrupts for this specific MEC. All other 2714 * pipes' interrupts are set by amdkfd. 2715 */ 2716 2717 if (me == 1) { 2718 switch (pipe) { 2719 case 0: 2720 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2721 break; 2722 case 1: 2723 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2724 break; 2725 case 2: 2726 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2727 break; 2728 case 3: 2729 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2730 break; 2731 default: 2732 DRM_DEBUG("invalid pipe %d\n", pipe); 2733 return; 2734 } 2735 } else { 2736 DRM_DEBUG("invalid me %d\n", me); 2737 return; 2738 } 2739 2740 switch (state) { 2741 case AMDGPU_IRQ_STATE_DISABLE: 2742 mec_int_cntl = RREG32(mec_int_cntl_reg); 2743 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2744 TIME_STAMP_INT_ENABLE, 0); 2745 WREG32(mec_int_cntl_reg, mec_int_cntl); 2746 break; 2747 case AMDGPU_IRQ_STATE_ENABLE: 2748 mec_int_cntl = RREG32(mec_int_cntl_reg); 2749 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2750 TIME_STAMP_INT_ENABLE, 1); 2751 WREG32(mec_int_cntl_reg, mec_int_cntl); 2752 break; 2753 default: 2754 break; 2755 } 2756 } 2757 2758 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2759 struct amdgpu_irq_src *source, 2760 unsigned type, 2761 enum amdgpu_interrupt_state state) 2762 { 2763 int i, num_xcc; 2764 2765 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2766 switch (state) { 2767 case AMDGPU_IRQ_STATE_DISABLE: 2768 case AMDGPU_IRQ_STATE_ENABLE: 2769 for (i = 0; i < num_xcc; i++) 2770 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2771 PRIV_REG_INT_ENABLE, 2772 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2773 break; 2774 default: 2775 break; 2776 } 2777 2778 return 0; 2779 } 2780 2781 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2782 struct amdgpu_irq_src *source, 2783 unsigned type, 2784 enum amdgpu_interrupt_state state) 2785 { 2786 int i, num_xcc; 2787 2788 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2789 switch (state) { 2790 case AMDGPU_IRQ_STATE_DISABLE: 2791 case AMDGPU_IRQ_STATE_ENABLE: 2792 for (i = 0; i < num_xcc; i++) 2793 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2794 PRIV_INSTR_INT_ENABLE, 2795 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2796 break; 2797 default: 2798 break; 2799 } 2800 2801 return 0; 2802 } 2803 2804 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2805 struct amdgpu_irq_src *src, 2806 unsigned type, 2807 enum amdgpu_interrupt_state state) 2808 { 2809 int i, num_xcc; 2810 2811 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2812 for (i = 0; i < num_xcc; i++) { 2813 switch (type) { 2814 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2815 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2816 adev, 1, 0, state, i); 2817 break; 2818 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2819 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2820 adev, 1, 1, state, i); 2821 break; 2822 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2823 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2824 adev, 1, 2, state, i); 2825 break; 2826 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2827 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2828 adev, 1, 3, state, i); 2829 break; 2830 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2831 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2832 adev, 2, 0, state, i); 2833 break; 2834 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2835 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2836 adev, 2, 1, state, i); 2837 break; 2838 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2839 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2840 adev, 2, 2, state, i); 2841 break; 2842 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2843 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2844 adev, 2, 3, state, i); 2845 break; 2846 default: 2847 break; 2848 } 2849 } 2850 2851 return 0; 2852 } 2853 2854 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2855 struct amdgpu_irq_src *source, 2856 struct amdgpu_iv_entry *entry) 2857 { 2858 int i, xcc_id; 2859 u8 me_id, pipe_id, queue_id; 2860 struct amdgpu_ring *ring; 2861 2862 DRM_DEBUG("IH: CP EOP\n"); 2863 me_id = (entry->ring_id & 0x0c) >> 2; 2864 pipe_id = (entry->ring_id & 0x03) >> 0; 2865 queue_id = (entry->ring_id & 0x70) >> 4; 2866 2867 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2868 2869 if (xcc_id == -EINVAL) 2870 return -EINVAL; 2871 2872 switch (me_id) { 2873 case 0: 2874 case 1: 2875 case 2: 2876 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2877 ring = &adev->gfx.compute_ring 2878 [i + 2879 xcc_id * adev->gfx.num_compute_rings]; 2880 /* Per-queue interrupt is supported for MEC starting from VI. 2881 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2882 */ 2883 2884 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2885 amdgpu_fence_process(ring); 2886 } 2887 break; 2888 } 2889 return 0; 2890 } 2891 2892 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2893 struct amdgpu_iv_entry *entry) 2894 { 2895 u8 me_id, pipe_id, queue_id; 2896 struct amdgpu_ring *ring; 2897 int i, xcc_id; 2898 2899 me_id = (entry->ring_id & 0x0c) >> 2; 2900 pipe_id = (entry->ring_id & 0x03) >> 0; 2901 queue_id = (entry->ring_id & 0x70) >> 4; 2902 2903 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2904 2905 if (xcc_id == -EINVAL) 2906 return; 2907 2908 switch (me_id) { 2909 case 0: 2910 case 1: 2911 case 2: 2912 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2913 ring = &adev->gfx.compute_ring 2914 [i + 2915 xcc_id * adev->gfx.num_compute_rings]; 2916 if (ring->me == me_id && ring->pipe == pipe_id && 2917 ring->queue == queue_id) 2918 drm_sched_fault(&ring->sched); 2919 } 2920 break; 2921 } 2922 } 2923 2924 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2925 struct amdgpu_irq_src *source, 2926 struct amdgpu_iv_entry *entry) 2927 { 2928 DRM_ERROR("Illegal register access in command stream\n"); 2929 gfx_v9_4_3_fault(adev, entry); 2930 return 0; 2931 } 2932 2933 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2934 struct amdgpu_irq_src *source, 2935 struct amdgpu_iv_entry *entry) 2936 { 2937 DRM_ERROR("Illegal instruction in command stream\n"); 2938 gfx_v9_4_3_fault(adev, entry); 2939 return 0; 2940 } 2941 2942 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2943 { 2944 const unsigned int cp_coher_cntl = 2945 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2946 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2947 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2948 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2949 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2950 2951 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2952 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2953 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2954 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2955 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2956 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2957 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2958 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2959 } 2960 2961 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2962 uint32_t pipe, bool enable) 2963 { 2964 struct amdgpu_device *adev = ring->adev; 2965 uint32_t val; 2966 uint32_t wcl_cs_reg; 2967 2968 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2969 val = enable ? 0x1 : 0x7f; 2970 2971 switch (pipe) { 2972 case 0: 2973 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2974 break; 2975 case 1: 2976 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2977 break; 2978 case 2: 2979 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2980 break; 2981 case 3: 2982 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2983 break; 2984 default: 2985 DRM_DEBUG("invalid pipe %d\n", pipe); 2986 return; 2987 } 2988 2989 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2990 2991 } 2992 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2993 { 2994 struct amdgpu_device *adev = ring->adev; 2995 uint32_t val; 2996 int i; 2997 2998 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2999 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3000 * around 25% of gpu resources. 3001 */ 3002 val = enable ? 0x1f : 0x07ffffff; 3003 amdgpu_ring_emit_wreg(ring, 3004 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3005 val); 3006 3007 /* Restrict waves for normal/low priority compute queues as well 3008 * to get best QoS for high priority compute jobs. 3009 * 3010 * amdgpu controls only 1st ME(0-3 CS pipes). 3011 */ 3012 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3013 if (i != ring->pipe) 3014 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3015 3016 } 3017 } 3018 3019 enum amdgpu_gfx_cp_ras_mem_id { 3020 AMDGPU_GFX_CP_MEM1 = 1, 3021 AMDGPU_GFX_CP_MEM2, 3022 AMDGPU_GFX_CP_MEM3, 3023 AMDGPU_GFX_CP_MEM4, 3024 AMDGPU_GFX_CP_MEM5, 3025 }; 3026 3027 enum amdgpu_gfx_gcea_ras_mem_id { 3028 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3029 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3030 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3031 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3032 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3033 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3034 AMDGPU_GFX_GCEA_MAM_DMEM0, 3035 AMDGPU_GFX_GCEA_MAM_DMEM1, 3036 AMDGPU_GFX_GCEA_MAM_DMEM2, 3037 AMDGPU_GFX_GCEA_MAM_DMEM3, 3038 AMDGPU_GFX_GCEA_MAM_AMEM0, 3039 AMDGPU_GFX_GCEA_MAM_AMEM1, 3040 AMDGPU_GFX_GCEA_MAM_AMEM2, 3041 AMDGPU_GFX_GCEA_MAM_AMEM3, 3042 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3043 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3044 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3045 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3046 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3047 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3048 }; 3049 3050 enum amdgpu_gfx_gc_cane_ras_mem_id { 3051 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3052 }; 3053 3054 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3055 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3056 }; 3057 3058 enum amdgpu_gfx_gds_ras_mem_id { 3059 AMDGPU_GFX_GDS_MEM0 = 0, 3060 }; 3061 3062 enum amdgpu_gfx_lds_ras_mem_id { 3063 AMDGPU_GFX_LDS_BANK0 = 0, 3064 AMDGPU_GFX_LDS_BANK1, 3065 AMDGPU_GFX_LDS_BANK2, 3066 AMDGPU_GFX_LDS_BANK3, 3067 AMDGPU_GFX_LDS_BANK4, 3068 AMDGPU_GFX_LDS_BANK5, 3069 AMDGPU_GFX_LDS_BANK6, 3070 AMDGPU_GFX_LDS_BANK7, 3071 AMDGPU_GFX_LDS_BANK8, 3072 AMDGPU_GFX_LDS_BANK9, 3073 AMDGPU_GFX_LDS_BANK10, 3074 AMDGPU_GFX_LDS_BANK11, 3075 AMDGPU_GFX_LDS_BANK12, 3076 AMDGPU_GFX_LDS_BANK13, 3077 AMDGPU_GFX_LDS_BANK14, 3078 AMDGPU_GFX_LDS_BANK15, 3079 AMDGPU_GFX_LDS_BANK16, 3080 AMDGPU_GFX_LDS_BANK17, 3081 AMDGPU_GFX_LDS_BANK18, 3082 AMDGPU_GFX_LDS_BANK19, 3083 AMDGPU_GFX_LDS_BANK20, 3084 AMDGPU_GFX_LDS_BANK21, 3085 AMDGPU_GFX_LDS_BANK22, 3086 AMDGPU_GFX_LDS_BANK23, 3087 AMDGPU_GFX_LDS_BANK24, 3088 AMDGPU_GFX_LDS_BANK25, 3089 AMDGPU_GFX_LDS_BANK26, 3090 AMDGPU_GFX_LDS_BANK27, 3091 AMDGPU_GFX_LDS_BANK28, 3092 AMDGPU_GFX_LDS_BANK29, 3093 AMDGPU_GFX_LDS_BANK30, 3094 AMDGPU_GFX_LDS_BANK31, 3095 AMDGPU_GFX_LDS_SP_BUFFER_A, 3096 AMDGPU_GFX_LDS_SP_BUFFER_B, 3097 }; 3098 3099 enum amdgpu_gfx_rlc_ras_mem_id { 3100 AMDGPU_GFX_RLC_GPMF32 = 1, 3101 AMDGPU_GFX_RLC_RLCVF32, 3102 AMDGPU_GFX_RLC_SCRATCH, 3103 AMDGPU_GFX_RLC_SRM_ARAM, 3104 AMDGPU_GFX_RLC_SRM_DRAM, 3105 AMDGPU_GFX_RLC_TCTAG, 3106 AMDGPU_GFX_RLC_SPM_SE, 3107 AMDGPU_GFX_RLC_SPM_GRBMT, 3108 }; 3109 3110 enum amdgpu_gfx_sp_ras_mem_id { 3111 AMDGPU_GFX_SP_SIMDID0 = 0, 3112 }; 3113 3114 enum amdgpu_gfx_spi_ras_mem_id { 3115 AMDGPU_GFX_SPI_MEM0 = 0, 3116 AMDGPU_GFX_SPI_MEM1, 3117 AMDGPU_GFX_SPI_MEM2, 3118 AMDGPU_GFX_SPI_MEM3, 3119 }; 3120 3121 enum amdgpu_gfx_sqc_ras_mem_id { 3122 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3123 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3124 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3125 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3126 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3127 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3128 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3129 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3130 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3131 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3132 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3133 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3134 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3135 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3136 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3137 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3138 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3139 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3140 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3141 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3142 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3143 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3144 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3145 }; 3146 3147 enum amdgpu_gfx_sq_ras_mem_id { 3148 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3149 AMDGPU_GFX_SQ_SGPR_MEM1, 3150 AMDGPU_GFX_SQ_SGPR_MEM2, 3151 AMDGPU_GFX_SQ_SGPR_MEM3, 3152 }; 3153 3154 enum amdgpu_gfx_ta_ras_mem_id { 3155 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3156 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3157 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3158 AMDGPU_GFX_TA_FSX_LFIFO, 3159 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3160 }; 3161 3162 enum amdgpu_gfx_tcc_ras_mem_id { 3163 AMDGPU_GFX_TCC_MEM1 = 1, 3164 }; 3165 3166 enum amdgpu_gfx_tca_ras_mem_id { 3167 AMDGPU_GFX_TCA_MEM1 = 1, 3168 }; 3169 3170 enum amdgpu_gfx_tci_ras_mem_id { 3171 AMDGPU_GFX_TCIW_MEM = 1, 3172 }; 3173 3174 enum amdgpu_gfx_tcp_ras_mem_id { 3175 AMDGPU_GFX_TCP_LFIFO0 = 1, 3176 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3177 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3178 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3179 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3180 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3181 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3182 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3183 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3184 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3185 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3186 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3187 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3188 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3189 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3190 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3191 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3192 AMDGPU_GFX_TCP_VM_FIFO, 3193 AMDGPU_GFX_TCP_DB_TAGRAM0, 3194 AMDGPU_GFX_TCP_DB_TAGRAM1, 3195 AMDGPU_GFX_TCP_DB_TAGRAM2, 3196 AMDGPU_GFX_TCP_DB_TAGRAM3, 3197 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3198 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3199 AMDGPU_GFX_TCP_CMD_FIFO, 3200 }; 3201 3202 enum amdgpu_gfx_td_ras_mem_id { 3203 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3204 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3205 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3206 }; 3207 3208 enum amdgpu_gfx_tcx_ras_mem_id { 3209 AMDGPU_GFX_TCX_FIFOD0 = 0, 3210 AMDGPU_GFX_TCX_FIFOD1, 3211 AMDGPU_GFX_TCX_FIFOD2, 3212 AMDGPU_GFX_TCX_FIFOD3, 3213 AMDGPU_GFX_TCX_FIFOD4, 3214 AMDGPU_GFX_TCX_FIFOD5, 3215 AMDGPU_GFX_TCX_FIFOD6, 3216 AMDGPU_GFX_TCX_FIFOD7, 3217 AMDGPU_GFX_TCX_FIFOB0, 3218 AMDGPU_GFX_TCX_FIFOB1, 3219 AMDGPU_GFX_TCX_FIFOB2, 3220 AMDGPU_GFX_TCX_FIFOB3, 3221 AMDGPU_GFX_TCX_FIFOB4, 3222 AMDGPU_GFX_TCX_FIFOB5, 3223 AMDGPU_GFX_TCX_FIFOB6, 3224 AMDGPU_GFX_TCX_FIFOB7, 3225 AMDGPU_GFX_TCX_FIFOA0, 3226 AMDGPU_GFX_TCX_FIFOA1, 3227 AMDGPU_GFX_TCX_FIFOA2, 3228 AMDGPU_GFX_TCX_FIFOA3, 3229 AMDGPU_GFX_TCX_FIFOA4, 3230 AMDGPU_GFX_TCX_FIFOA5, 3231 AMDGPU_GFX_TCX_FIFOA6, 3232 AMDGPU_GFX_TCX_FIFOA7, 3233 AMDGPU_GFX_TCX_CFIFO0, 3234 AMDGPU_GFX_TCX_CFIFO1, 3235 AMDGPU_GFX_TCX_CFIFO2, 3236 AMDGPU_GFX_TCX_CFIFO3, 3237 AMDGPU_GFX_TCX_CFIFO4, 3238 AMDGPU_GFX_TCX_CFIFO5, 3239 AMDGPU_GFX_TCX_CFIFO6, 3240 AMDGPU_GFX_TCX_CFIFO7, 3241 AMDGPU_GFX_TCX_FIFO_ACKB0, 3242 AMDGPU_GFX_TCX_FIFO_ACKB1, 3243 AMDGPU_GFX_TCX_FIFO_ACKB2, 3244 AMDGPU_GFX_TCX_FIFO_ACKB3, 3245 AMDGPU_GFX_TCX_FIFO_ACKB4, 3246 AMDGPU_GFX_TCX_FIFO_ACKB5, 3247 AMDGPU_GFX_TCX_FIFO_ACKB6, 3248 AMDGPU_GFX_TCX_FIFO_ACKB7, 3249 AMDGPU_GFX_TCX_FIFO_ACKD0, 3250 AMDGPU_GFX_TCX_FIFO_ACKD1, 3251 AMDGPU_GFX_TCX_FIFO_ACKD2, 3252 AMDGPU_GFX_TCX_FIFO_ACKD3, 3253 AMDGPU_GFX_TCX_FIFO_ACKD4, 3254 AMDGPU_GFX_TCX_FIFO_ACKD5, 3255 AMDGPU_GFX_TCX_FIFO_ACKD6, 3256 AMDGPU_GFX_TCX_FIFO_ACKD7, 3257 AMDGPU_GFX_TCX_DST_FIFOA0, 3258 AMDGPU_GFX_TCX_DST_FIFOA1, 3259 AMDGPU_GFX_TCX_DST_FIFOA2, 3260 AMDGPU_GFX_TCX_DST_FIFOA3, 3261 AMDGPU_GFX_TCX_DST_FIFOA4, 3262 AMDGPU_GFX_TCX_DST_FIFOA5, 3263 AMDGPU_GFX_TCX_DST_FIFOA6, 3264 AMDGPU_GFX_TCX_DST_FIFOA7, 3265 AMDGPU_GFX_TCX_DST_FIFOB0, 3266 AMDGPU_GFX_TCX_DST_FIFOB1, 3267 AMDGPU_GFX_TCX_DST_FIFOB2, 3268 AMDGPU_GFX_TCX_DST_FIFOB3, 3269 AMDGPU_GFX_TCX_DST_FIFOB4, 3270 AMDGPU_GFX_TCX_DST_FIFOB5, 3271 AMDGPU_GFX_TCX_DST_FIFOB6, 3272 AMDGPU_GFX_TCX_DST_FIFOB7, 3273 AMDGPU_GFX_TCX_DST_FIFOD0, 3274 AMDGPU_GFX_TCX_DST_FIFOD1, 3275 AMDGPU_GFX_TCX_DST_FIFOD2, 3276 AMDGPU_GFX_TCX_DST_FIFOD3, 3277 AMDGPU_GFX_TCX_DST_FIFOD4, 3278 AMDGPU_GFX_TCX_DST_FIFOD5, 3279 AMDGPU_GFX_TCX_DST_FIFOD6, 3280 AMDGPU_GFX_TCX_DST_FIFOD7, 3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3285 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3286 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3287 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3288 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3293 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3294 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3295 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3296 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3297 }; 3298 3299 enum amdgpu_gfx_atc_l2_ras_mem_id { 3300 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3301 }; 3302 3303 enum amdgpu_gfx_utcl2_ras_mem_id { 3304 AMDGPU_GFX_UTCL2_MEM0 = 0, 3305 }; 3306 3307 enum amdgpu_gfx_vml2_ras_mem_id { 3308 AMDGPU_GFX_VML2_MEM0 = 0, 3309 }; 3310 3311 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3312 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3313 }; 3314 3315 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3316 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3317 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3318 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3319 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3320 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3321 }; 3322 3323 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3324 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3325 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3326 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3327 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3328 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3329 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3330 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3331 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3332 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3333 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3334 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3335 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3336 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3337 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3338 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3339 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3340 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3341 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3342 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3343 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3344 }; 3345 3346 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3347 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3348 }; 3349 3350 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3351 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3352 }; 3353 3354 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3355 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3356 }; 3357 3358 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3359 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3360 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3361 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3362 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3363 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3364 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3365 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3366 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3367 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3368 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3369 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3370 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3371 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3372 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3373 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3374 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3375 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3376 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3377 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3378 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3379 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3380 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3381 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3382 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3383 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3384 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3385 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3386 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3387 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3388 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3389 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3390 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3391 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3392 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3393 }; 3394 3395 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3396 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3397 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3398 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3399 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3400 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3401 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3402 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3403 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3404 }; 3405 3406 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3407 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3408 }; 3409 3410 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3411 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3412 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3413 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3414 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3415 }; 3416 3417 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3418 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3419 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3420 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3421 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3422 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3423 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3424 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3425 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3426 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3427 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3428 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3429 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3430 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3431 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3432 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3433 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3434 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3435 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3436 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3437 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3438 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3439 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3440 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3441 }; 3442 3443 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3444 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3445 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3446 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3447 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3448 }; 3449 3450 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3451 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3452 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3453 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3454 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3455 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3456 }; 3457 3458 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3459 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3460 }; 3461 3462 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3463 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3464 }; 3465 3466 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3467 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3468 }; 3469 3470 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3471 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3472 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3473 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3474 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3475 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3476 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3477 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3478 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3479 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3480 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3481 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3482 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3483 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3484 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3485 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3486 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3487 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3488 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3489 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3490 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3491 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3492 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3493 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3494 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3495 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3496 }; 3497 3498 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3499 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3500 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3501 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3502 }; 3503 3504 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3505 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3506 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3507 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3508 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3509 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3510 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3511 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3512 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3513 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3514 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3515 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3516 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3517 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3518 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3519 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3520 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3521 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3522 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3523 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3524 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3525 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3526 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3527 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3528 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3529 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3530 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3531 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3532 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3533 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3534 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3535 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3536 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3537 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3538 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3539 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3540 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3541 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3542 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3543 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3544 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3545 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3546 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3547 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3548 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3549 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3550 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3551 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3552 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3553 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3554 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3555 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3556 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3557 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3558 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3559 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3560 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3561 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3562 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3563 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3564 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3565 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3566 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3567 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3568 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3569 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3570 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3571 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3572 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3573 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3574 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3575 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3576 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3589 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3590 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3591 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3592 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3593 }; 3594 3595 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3596 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3597 }; 3598 3599 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3600 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3601 }; 3602 3603 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3604 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3605 }; 3606 3607 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3608 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3609 }; 3610 3611 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3630 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3631 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3632 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3633 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3634 }; 3635 3636 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3637 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3638 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3639 AMDGPU_GFX_RLC_MEM, 1}, 3640 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3641 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3642 AMDGPU_GFX_CP_MEM, 1}, 3643 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3644 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3645 AMDGPU_GFX_CP_MEM, 1}, 3646 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3647 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3648 AMDGPU_GFX_CP_MEM, 1}, 3649 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3650 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3651 AMDGPU_GFX_GDS_MEM, 1}, 3652 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3653 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3654 AMDGPU_GFX_GC_CANE_MEM, 1}, 3655 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3656 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3657 AMDGPU_GFX_SPI_MEM, 8}, 3658 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3659 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3660 AMDGPU_GFX_SP_MEM, 1}, 3661 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3662 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3663 AMDGPU_GFX_SP_MEM, 1}, 3664 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3665 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3666 AMDGPU_GFX_SQ_MEM, 8}, 3667 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3668 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3669 AMDGPU_GFX_SQC_MEM, 8}, 3670 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3671 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3672 AMDGPU_GFX_TCX_MEM, 1}, 3673 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3674 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3675 AMDGPU_GFX_TCC_MEM, 1}, 3676 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3677 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3678 AMDGPU_GFX_TA_MEM, 8}, 3679 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3680 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3681 AMDGPU_GFX_TCI_MEM, 1}, 3682 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3683 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3684 AMDGPU_GFX_TCP_MEM, 8}, 3685 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3686 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3687 AMDGPU_GFX_TD_MEM, 8}, 3688 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3689 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3690 AMDGPU_GFX_GCEA_MEM, 1}, 3691 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3692 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3693 AMDGPU_GFX_LDS_MEM, 1}, 3694 }; 3695 3696 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3697 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3698 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3699 AMDGPU_GFX_RLC_MEM, 1}, 3700 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3701 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3702 AMDGPU_GFX_CP_MEM, 1}, 3703 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3704 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3705 AMDGPU_GFX_CP_MEM, 1}, 3706 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3707 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3708 AMDGPU_GFX_CP_MEM, 1}, 3709 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3710 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3711 AMDGPU_GFX_GDS_MEM, 1}, 3712 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3713 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3714 AMDGPU_GFX_GC_CANE_MEM, 1}, 3715 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3716 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3717 AMDGPU_GFX_SPI_MEM, 8}, 3718 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3719 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3720 AMDGPU_GFX_SP_MEM, 1}, 3721 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3722 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3723 AMDGPU_GFX_SP_MEM, 1}, 3724 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3725 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3726 AMDGPU_GFX_SQ_MEM, 8}, 3727 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3728 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3729 AMDGPU_GFX_SQC_MEM, 8}, 3730 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3731 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3732 AMDGPU_GFX_TCX_MEM, 1}, 3733 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3734 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3735 AMDGPU_GFX_TCC_MEM, 1}, 3736 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3737 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3738 AMDGPU_GFX_TA_MEM, 8}, 3739 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3740 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3741 AMDGPU_GFX_TCI_MEM, 1}, 3742 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3743 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3744 AMDGPU_GFX_TCP_MEM, 8}, 3745 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3746 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3747 AMDGPU_GFX_TD_MEM, 8}, 3748 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3749 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3750 AMDGPU_GFX_TCA_MEM, 1}, 3751 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3752 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3753 AMDGPU_GFX_GCEA_MEM, 1}, 3754 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3755 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3756 AMDGPU_GFX_LDS_MEM, 1}, 3757 }; 3758 3759 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3760 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3761 }; 3762 3763 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3764 void *ras_error_status, int xcc_id) 3765 { 3766 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3767 unsigned long ce_count = 0, ue_count = 0; 3768 uint32_t i, j, k; 3769 3770 mutex_lock(&adev->grbm_idx_mutex); 3771 3772 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3773 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3774 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3775 /* no need to select if instance number is 1 */ 3776 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3777 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3778 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3779 3780 amdgpu_ras_inst_query_ras_error_count(adev, 3781 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3782 1, 3783 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3784 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3785 GET_INST(GC, xcc_id), 3786 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3787 &ce_count); 3788 3789 amdgpu_ras_inst_query_ras_error_count(adev, 3790 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3791 1, 3792 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3793 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3794 GET_INST(GC, xcc_id), 3795 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3796 &ue_count); 3797 } 3798 } 3799 } 3800 3801 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3802 xcc_id); 3803 mutex_unlock(&adev->grbm_idx_mutex); 3804 3805 /* the caller should make sure initialize value of 3806 * err_data->ue_count and err_data->ce_count 3807 */ 3808 err_data->ce_count += ce_count; 3809 err_data->ue_count += ue_count; 3810 } 3811 3812 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3813 void *ras_error_status, int xcc_id) 3814 { 3815 uint32_t i, j, k; 3816 3817 mutex_lock(&adev->grbm_idx_mutex); 3818 3819 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3820 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3821 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3822 /* no need to select if instance number is 1 */ 3823 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3824 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3825 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3826 3827 amdgpu_ras_inst_reset_ras_error_count(adev, 3828 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3829 1, 3830 GET_INST(GC, xcc_id)); 3831 3832 amdgpu_ras_inst_reset_ras_error_count(adev, 3833 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3834 1, 3835 GET_INST(GC, xcc_id)); 3836 } 3837 } 3838 } 3839 3840 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3841 xcc_id); 3842 mutex_unlock(&adev->grbm_idx_mutex); 3843 } 3844 3845 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3846 int xcc_id) 3847 { 3848 uint32_t i, j; 3849 uint32_t reg_value; 3850 3851 mutex_lock(&adev->grbm_idx_mutex); 3852 3853 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3854 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3855 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3856 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3857 regGCEA_ERR_STATUS); 3858 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3859 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3860 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3861 dev_warn(adev->dev, 3862 "GCEA err detected at instance: %d, status: 0x%x!\n", 3863 j, reg_value); 3864 } 3865 /* clear after read */ 3866 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3867 CLEAR_ERROR_STATUS, 0x1); 3868 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3869 reg_value); 3870 } 3871 } 3872 3873 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3874 xcc_id); 3875 mutex_unlock(&adev->grbm_idx_mutex); 3876 } 3877 3878 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3879 int xcc_id) 3880 { 3881 uint32_t data; 3882 3883 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3884 if (data) { 3885 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3886 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3887 } 3888 3889 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3890 if (data) { 3891 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3892 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3893 } 3894 3895 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3896 regVML2_WALKER_MEM_ECC_STATUS); 3897 if (data) { 3898 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3899 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3900 0x3); 3901 } 3902 } 3903 3904 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3905 uint32_t status, int xcc_id) 3906 { 3907 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3908 uint32_t i, simd, wave; 3909 uint32_t wave_status; 3910 uint32_t wave_pc_lo, wave_pc_hi; 3911 uint32_t wave_exec_lo, wave_exec_hi; 3912 uint32_t wave_inst_dw0, wave_inst_dw1; 3913 uint32_t wave_ib_sts; 3914 3915 for (i = 0; i < 32; i++) { 3916 if (!((i << 1) & status)) 3917 continue; 3918 3919 simd = i / cu_info->max_waves_per_simd; 3920 wave = i % cu_info->max_waves_per_simd; 3921 3922 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3923 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3924 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3925 wave_exec_lo = 3926 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3927 wave_exec_hi = 3928 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3929 wave_inst_dw0 = 3930 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3931 wave_inst_dw1 = 3932 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3933 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3934 3935 dev_info( 3936 adev->dev, 3937 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3938 simd, wave, wave_status, 3939 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3940 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3941 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3942 wave_ib_sts); 3943 } 3944 } 3945 3946 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3947 int xcc_id) 3948 { 3949 uint32_t se_idx, sh_idx, cu_idx; 3950 uint32_t status; 3951 3952 mutex_lock(&adev->grbm_idx_mutex); 3953 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3954 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3955 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3956 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3957 cu_idx, xcc_id); 3958 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3959 regSQ_TIMEOUT_STATUS); 3960 if (status != 0) { 3961 dev_info( 3962 adev->dev, 3963 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3964 se_idx, sh_idx, cu_idx); 3965 gfx_v9_4_3_log_cu_timeout_status( 3966 adev, status, xcc_id); 3967 } 3968 /* clear old status */ 3969 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3970 regSQ_TIMEOUT_STATUS, 0); 3971 } 3972 } 3973 } 3974 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3975 xcc_id); 3976 mutex_unlock(&adev->grbm_idx_mutex); 3977 } 3978 3979 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3980 void *ras_error_status, int xcc_id) 3981 { 3982 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3983 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3984 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3985 } 3986 3987 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3988 int xcc_id) 3989 { 3990 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3991 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3992 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3993 } 3994 3995 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3996 int xcc_id) 3997 { 3998 uint32_t i, j; 3999 uint32_t value; 4000 4001 mutex_lock(&adev->grbm_idx_mutex); 4002 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 4003 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 4004 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 4005 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 4006 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 4007 CLEAR_ERROR_STATUS, 0x1); 4008 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 4009 } 4010 } 4011 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4012 xcc_id); 4013 mutex_unlock(&adev->grbm_idx_mutex); 4014 } 4015 4016 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 4017 int xcc_id) 4018 { 4019 uint32_t se_idx, sh_idx, cu_idx; 4020 4021 mutex_lock(&adev->grbm_idx_mutex); 4022 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 4023 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 4024 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 4025 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 4026 cu_idx, xcc_id); 4027 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4028 regSQ_TIMEOUT_STATUS, 0); 4029 } 4030 } 4031 } 4032 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4033 xcc_id); 4034 mutex_unlock(&adev->grbm_idx_mutex); 4035 } 4036 4037 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4038 void *ras_error_status, int xcc_id) 4039 { 4040 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4041 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4042 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4043 } 4044 4045 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4046 void *ras_error_status, int xcc_id) 4047 { 4048 uint32_t i; 4049 uint32_t data; 4050 4051 data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4052 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4053 4054 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4055 (amdgpu_watchdog_timer.period < 1 || 4056 amdgpu_watchdog_timer.period > 0x23)) { 4057 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4058 amdgpu_watchdog_timer.period = 0x23; 4059 } 4060 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4061 amdgpu_watchdog_timer.period); 4062 4063 mutex_lock(&adev->grbm_idx_mutex); 4064 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4065 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4066 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4067 } 4068 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4069 xcc_id); 4070 mutex_unlock(&adev->grbm_idx_mutex); 4071 } 4072 4073 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4074 void *ras_error_status) 4075 { 4076 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4077 gfx_v9_4_3_inst_query_ras_err_count); 4078 } 4079 4080 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4081 { 4082 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4083 } 4084 4085 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4086 { 4087 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4088 } 4089 4090 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4091 { 4092 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4093 } 4094 4095 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4096 { 4097 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4098 } 4099 4100 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4101 .name = "gfx_v9_4_3", 4102 .early_init = gfx_v9_4_3_early_init, 4103 .late_init = gfx_v9_4_3_late_init, 4104 .sw_init = gfx_v9_4_3_sw_init, 4105 .sw_fini = gfx_v9_4_3_sw_fini, 4106 .hw_init = gfx_v9_4_3_hw_init, 4107 .hw_fini = gfx_v9_4_3_hw_fini, 4108 .suspend = gfx_v9_4_3_suspend, 4109 .resume = gfx_v9_4_3_resume, 4110 .is_idle = gfx_v9_4_3_is_idle, 4111 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4112 .soft_reset = gfx_v9_4_3_soft_reset, 4113 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4114 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4115 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4116 }; 4117 4118 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4119 .type = AMDGPU_RING_TYPE_COMPUTE, 4120 .align_mask = 0xff, 4121 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4122 .support_64bit_ptrs = true, 4123 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4124 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4125 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4126 .emit_frame_size = 4127 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4128 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4129 5 + /* hdp invalidate */ 4130 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4131 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4132 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4133 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4134 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4135 7 + /* gfx_v9_4_3_emit_mem_sync */ 4136 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4137 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4138 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4139 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4140 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4141 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4142 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4143 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4144 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4145 .test_ring = gfx_v9_4_3_ring_test_ring, 4146 .test_ib = gfx_v9_4_3_ring_test_ib, 4147 .insert_nop = amdgpu_ring_insert_nop, 4148 .pad_ib = amdgpu_ring_generic_pad_ib, 4149 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4150 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4151 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4152 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4153 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4154 }; 4155 4156 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4157 .type = AMDGPU_RING_TYPE_KIQ, 4158 .align_mask = 0xff, 4159 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4160 .support_64bit_ptrs = true, 4161 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4162 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4163 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4164 .emit_frame_size = 4165 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4166 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4167 5 + /* hdp invalidate */ 4168 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4169 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4170 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4171 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4172 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4173 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4174 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4175 .test_ring = gfx_v9_4_3_ring_test_ring, 4176 .insert_nop = amdgpu_ring_insert_nop, 4177 .pad_ib = amdgpu_ring_generic_pad_ib, 4178 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4179 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4180 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4181 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4182 }; 4183 4184 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4185 { 4186 int i, j, num_xcc; 4187 4188 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4189 for (i = 0; i < num_xcc; i++) { 4190 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4191 4192 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4193 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4194 = &gfx_v9_4_3_ring_funcs_compute; 4195 } 4196 } 4197 4198 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4199 .set = gfx_v9_4_3_set_eop_interrupt_state, 4200 .process = gfx_v9_4_3_eop_irq, 4201 }; 4202 4203 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4204 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4205 .process = gfx_v9_4_3_priv_reg_irq, 4206 }; 4207 4208 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4209 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4210 .process = gfx_v9_4_3_priv_inst_irq, 4211 }; 4212 4213 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4214 { 4215 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4216 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4217 4218 adev->gfx.priv_reg_irq.num_types = 1; 4219 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4220 4221 adev->gfx.priv_inst_irq.num_types = 1; 4222 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4223 } 4224 4225 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4226 { 4227 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4228 } 4229 4230 4231 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4232 { 4233 /* init asci gds info */ 4234 switch (adev->ip_versions[GC_HWIP][0]) { 4235 case IP_VERSION(9, 4, 3): 4236 /* 9.4.3 removed all the GDS internal memory, 4237 * only support GWS opcode in kernel, like barrier 4238 * semaphore.etc */ 4239 adev->gds.gds_size = 0; 4240 break; 4241 default: 4242 adev->gds.gds_size = 0x10000; 4243 break; 4244 } 4245 4246 switch (adev->ip_versions[GC_HWIP][0]) { 4247 case IP_VERSION(9, 4, 3): 4248 /* deprecated for 9.4.3, no usage at all */ 4249 adev->gds.gds_compute_max_wave_id = 0; 4250 break; 4251 default: 4252 /* this really depends on the chip */ 4253 adev->gds.gds_compute_max_wave_id = 0x7ff; 4254 break; 4255 } 4256 4257 adev->gds.gws_size = 64; 4258 adev->gds.oa_size = 16; 4259 } 4260 4261 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4262 u32 bitmap) 4263 { 4264 u32 data; 4265 4266 if (!bitmap) 4267 return; 4268 4269 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4270 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4271 4272 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4273 } 4274 4275 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4276 { 4277 u32 data, mask; 4278 4279 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4280 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4281 4282 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4283 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4284 4285 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4286 4287 return (~data) & mask; 4288 } 4289 4290 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4291 struct amdgpu_cu_info *cu_info) 4292 { 4293 int i, j, k, counter, active_cu_number = 0; 4294 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4295 unsigned disable_masks[4 * 4]; 4296 4297 if (!adev || !cu_info) 4298 return -EINVAL; 4299 4300 /* 4301 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4302 */ 4303 if (adev->gfx.config.max_shader_engines * 4304 adev->gfx.config.max_sh_per_se > 16) 4305 return -EINVAL; 4306 4307 amdgpu_gfx_parse_disable_cu(disable_masks, 4308 adev->gfx.config.max_shader_engines, 4309 adev->gfx.config.max_sh_per_se); 4310 4311 mutex_lock(&adev->grbm_idx_mutex); 4312 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4313 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4314 mask = 1; 4315 ao_bitmap = 0; 4316 counter = 0; 4317 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4318 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4319 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4320 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4321 4322 /* 4323 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4324 * 4x4 size array, and it's usually suitable for Vega 4325 * ASICs which has 4*2 SE/SH layout. 4326 * But for Arcturus, SE/SH layout is changed to 8*1. 4327 * To mostly reduce the impact, we make it compatible 4328 * with current bitmap array as below: 4329 * SE4,SH0 --> bitmap[0][1] 4330 * SE5,SH0 --> bitmap[1][1] 4331 * SE6,SH0 --> bitmap[2][1] 4332 * SE7,SH0 --> bitmap[3][1] 4333 */ 4334 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4335 4336 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4337 if (bitmap & mask) { 4338 if (counter < adev->gfx.config.max_cu_per_sh) 4339 ao_bitmap |= mask; 4340 counter++; 4341 } 4342 mask <<= 1; 4343 } 4344 active_cu_number += counter; 4345 if (i < 2 && j < 2) 4346 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4347 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4348 } 4349 } 4350 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4351 0); 4352 mutex_unlock(&adev->grbm_idx_mutex); 4353 4354 cu_info->number = active_cu_number; 4355 cu_info->ao_cu_mask = ao_cu_mask; 4356 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4357 4358 return 0; 4359 } 4360 4361 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4362 .type = AMD_IP_BLOCK_TYPE_GFX, 4363 .major = 9, 4364 .minor = 4, 4365 .rev = 0, 4366 .funcs = &gfx_v9_4_3_ip_funcs, 4367 }; 4368 4369 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4370 { 4371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4372 uint32_t tmp_mask; 4373 int i, r; 4374 4375 /* TODO : Initialize golden regs */ 4376 /* gfx_v9_4_3_init_golden_registers(adev); */ 4377 4378 tmp_mask = inst_mask; 4379 for_each_inst(i, tmp_mask) 4380 gfx_v9_4_3_xcc_constants_init(adev, i); 4381 4382 if (!amdgpu_sriov_vf(adev)) { 4383 tmp_mask = inst_mask; 4384 for_each_inst(i, tmp_mask) { 4385 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4386 if (r) 4387 return r; 4388 } 4389 } 4390 4391 tmp_mask = inst_mask; 4392 for_each_inst(i, tmp_mask) { 4393 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4394 if (r) 4395 return r; 4396 } 4397 4398 return 0; 4399 } 4400 4401 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4402 { 4403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4404 int i; 4405 4406 for_each_inst(i, inst_mask) 4407 gfx_v9_4_3_xcc_fini(adev, i); 4408 4409 return 0; 4410 } 4411 4412 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4413 .suspend = &gfx_v9_4_3_xcp_suspend, 4414 .resume = &gfx_v9_4_3_xcp_resume 4415 }; 4416 4417 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4418 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4419 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4420 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4421 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4422 }; 4423 4424 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4425 .ras_block = { 4426 .hw_ops = &gfx_v9_4_3_ras_ops, 4427 }, 4428 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4429 }; 4430