1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 353 } 354 } 355 356 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 357 { 358 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 359 360 /* If it is an XCC reg, normalize the reg to keep 361 lower 16 bits in local xcc */ 362 363 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 364 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 365 return normalized_reg; 366 else 367 return reg; 368 } 369 370 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 371 bool wc, uint32_t reg, uint32_t val) 372 { 373 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 375 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 376 WRITE_DATA_DST_SEL(0) | 377 (wc ? WR_CONFIRM : 0)); 378 amdgpu_ring_write(ring, reg); 379 amdgpu_ring_write(ring, 0); 380 amdgpu_ring_write(ring, val); 381 } 382 383 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 384 int mem_space, int opt, uint32_t addr0, 385 uint32_t addr1, uint32_t ref, uint32_t mask, 386 uint32_t inv) 387 { 388 /* Only do the normalization on regspace */ 389 if (mem_space == 0) { 390 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 391 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 392 } 393 394 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 395 amdgpu_ring_write(ring, 396 /* memory (1) or register (0) */ 397 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 398 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 399 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 400 WAIT_REG_MEM_ENGINE(eng_sel))); 401 402 if (mem_space) 403 BUG_ON(addr0 & 0x3); /* Dword align */ 404 amdgpu_ring_write(ring, addr0); 405 amdgpu_ring_write(ring, addr1); 406 amdgpu_ring_write(ring, ref); 407 amdgpu_ring_write(ring, mask); 408 amdgpu_ring_write(ring, inv); /* poll interval */ 409 } 410 411 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 412 { 413 uint32_t scratch_reg0_offset, xcc_offset; 414 struct amdgpu_device *adev = ring->adev; 415 uint32_t tmp = 0; 416 unsigned i; 417 int r; 418 419 /* Use register offset which is local to XCC in the packet */ 420 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 421 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 422 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 423 tmp = RREG32(scratch_reg0_offset); 424 425 r = amdgpu_ring_alloc(ring, 3); 426 if (r) 427 return r; 428 429 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 430 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 431 amdgpu_ring_write(ring, 0xDEADBEEF); 432 amdgpu_ring_commit(ring); 433 434 for (i = 0; i < adev->usec_timeout; i++) { 435 tmp = RREG32(scratch_reg0_offset); 436 if (tmp == 0xDEADBEEF) 437 break; 438 udelay(1); 439 } 440 441 if (i >= adev->usec_timeout) 442 r = -ETIMEDOUT; 443 return r; 444 } 445 446 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 447 { 448 struct amdgpu_device *adev = ring->adev; 449 struct amdgpu_ib ib; 450 struct dma_fence *f = NULL; 451 452 unsigned index; 453 uint64_t gpu_addr; 454 uint32_t tmp; 455 long r; 456 457 r = amdgpu_device_wb_get(adev, &index); 458 if (r) 459 return r; 460 461 gpu_addr = adev->wb.gpu_addr + (index * 4); 462 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 463 memset(&ib, 0, sizeof(ib)); 464 465 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 466 if (r) 467 goto err1; 468 469 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 470 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 471 ib.ptr[2] = lower_32_bits(gpu_addr); 472 ib.ptr[3] = upper_32_bits(gpu_addr); 473 ib.ptr[4] = 0xDEADBEEF; 474 ib.length_dw = 5; 475 476 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 477 if (r) 478 goto err2; 479 480 r = dma_fence_wait_timeout(f, false, timeout); 481 if (r == 0) { 482 r = -ETIMEDOUT; 483 goto err2; 484 } else if (r < 0) { 485 goto err2; 486 } 487 488 tmp = adev->wb.wb[index]; 489 if (tmp == 0xDEADBEEF) 490 r = 0; 491 else 492 r = -EINVAL; 493 494 err2: 495 amdgpu_ib_free(&ib, NULL); 496 dma_fence_put(f); 497 err1: 498 amdgpu_device_wb_free(adev, index); 499 return r; 500 } 501 502 503 /* This value might differs per partition */ 504 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 505 { 506 uint64_t clock; 507 508 mutex_lock(&adev->gfx.gpu_clock_mutex); 509 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 510 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 511 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 512 mutex_unlock(&adev->gfx.gpu_clock_mutex); 513 514 return clock; 515 } 516 517 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 518 { 519 amdgpu_ucode_release(&adev->gfx.pfp_fw); 520 amdgpu_ucode_release(&adev->gfx.me_fw); 521 amdgpu_ucode_release(&adev->gfx.ce_fw); 522 amdgpu_ucode_release(&adev->gfx.rlc_fw); 523 amdgpu_ucode_release(&adev->gfx.mec_fw); 524 amdgpu_ucode_release(&adev->gfx.mec2_fw); 525 526 kfree(adev->gfx.rlc.register_list_format); 527 } 528 529 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 530 const char *chip_name) 531 { 532 int err; 533 const struct rlc_firmware_header_v2_0 *rlc_hdr; 534 uint16_t version_major; 535 uint16_t version_minor; 536 537 538 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 539 AMDGPU_UCODE_REQUIRED, 540 "amdgpu/%s_rlc.bin", chip_name); 541 if (err) 542 goto out; 543 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 544 545 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 546 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 547 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 548 out: 549 if (err) 550 amdgpu_ucode_release(&adev->gfx.rlc_fw); 551 552 return err; 553 } 554 555 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 556 const char *chip_name) 557 { 558 int err; 559 560 if (amdgpu_sriov_vf(adev)) { 561 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 562 AMDGPU_UCODE_REQUIRED, 563 "amdgpu/%s_sjt_mec.bin", chip_name); 564 565 if (err) 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_mec.bin", chip_name); 569 } else 570 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_mec.bin", chip_name); 573 if (err) 574 goto out; 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 576 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 577 578 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 579 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 580 581 out: 582 if (err) 583 amdgpu_ucode_release(&adev->gfx.mec_fw); 584 return err; 585 } 586 587 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int r; 591 592 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 593 594 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 595 if (r) 596 return r; 597 598 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 599 if (r) 600 return r; 601 602 return r; 603 } 604 605 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 606 { 607 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 608 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 609 } 610 611 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 612 { 613 int r, i, num_xcc; 614 u32 *hpd; 615 const __le32 *fw_data; 616 unsigned fw_size; 617 u32 *fw; 618 size_t mec_hpd_size; 619 620 const struct gfx_firmware_header_v1_0 *mec_hdr; 621 622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 623 for (i = 0; i < num_xcc; i++) 624 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 625 AMDGPU_MAX_COMPUTE_QUEUES); 626 627 /* take ownership of the relevant compute queues */ 628 amdgpu_gfx_compute_queue_acquire(adev); 629 mec_hpd_size = 630 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 631 if (mec_hpd_size) { 632 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 633 AMDGPU_GEM_DOMAIN_VRAM | 634 AMDGPU_GEM_DOMAIN_GTT, 635 &adev->gfx.mec.hpd_eop_obj, 636 &adev->gfx.mec.hpd_eop_gpu_addr, 637 (void **)&hpd); 638 if (r) { 639 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 640 gfx_v9_4_3_mec_fini(adev); 641 return r; 642 } 643 644 if (amdgpu_emu_mode == 1) { 645 for (i = 0; i < mec_hpd_size / 4; i++) { 646 memset((void *)(hpd + i), 0, 4); 647 if (i % 50 == 0) 648 msleep(1); 649 } 650 } else { 651 memset(hpd, 0, mec_hpd_size); 652 } 653 654 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 655 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 656 } 657 658 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 659 660 fw_data = (const __le32 *) 661 (adev->gfx.mec_fw->data + 662 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 663 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 664 665 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 666 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 667 &adev->gfx.mec.mec_fw_obj, 668 &adev->gfx.mec.mec_fw_gpu_addr, 669 (void **)&fw); 670 if (r) { 671 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 672 gfx_v9_4_3_mec_fini(adev); 673 return r; 674 } 675 676 memcpy(fw, fw_data, fw_size); 677 678 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 679 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 680 681 return 0; 682 } 683 684 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 685 u32 sh_num, u32 instance, int xcc_id) 686 { 687 u32 data; 688 689 if (instance == 0xffffffff) 690 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 691 INSTANCE_BROADCAST_WRITES, 1); 692 else 693 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 694 INSTANCE_INDEX, instance); 695 696 if (se_num == 0xffffffff) 697 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 698 SE_BROADCAST_WRITES, 1); 699 else 700 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 701 702 if (sh_num == 0xffffffff) 703 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 704 SH_BROADCAST_WRITES, 1); 705 else 706 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 707 708 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 709 } 710 711 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 712 { 713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 714 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 715 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 716 (address << SQ_IND_INDEX__INDEX__SHIFT) | 717 (SQ_IND_INDEX__FORCE_READ_MASK)); 718 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 719 } 720 721 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 722 uint32_t wave, uint32_t thread, 723 uint32_t regno, uint32_t num, uint32_t *out) 724 { 725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 726 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 727 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 728 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 729 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 730 (SQ_IND_INDEX__FORCE_READ_MASK) | 731 (SQ_IND_INDEX__AUTO_INCR_MASK)); 732 while (num--) 733 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 734 } 735 736 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 737 uint32_t xcc_id, uint32_t simd, uint32_t wave, 738 uint32_t *dst, int *no_fields) 739 { 740 /* type 1 wave data */ 741 dst[(*no_fields)++] = 1; 742 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 743 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 744 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 745 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 746 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 757 } 758 759 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 760 uint32_t wave, uint32_t start, 761 uint32_t size, uint32_t *dst) 762 { 763 wave_read_regs(adev, xcc_id, simd, wave, 0, 764 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 765 } 766 767 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 768 uint32_t wave, uint32_t thread, 769 uint32_t start, uint32_t size, 770 uint32_t *dst) 771 { 772 wave_read_regs(adev, xcc_id, simd, wave, thread, 773 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 774 } 775 776 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 777 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 778 { 779 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 780 } 781 782 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 783 { 784 u32 xcp_ctl; 785 786 /* Value is expected to be the same on all, fetch from first instance */ 787 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 788 789 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 790 } 791 792 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 793 int num_xccs_per_xcp) 794 { 795 int ret, i, num_xcc; 796 u32 tmp = 0; 797 798 if (adev->psp.funcs) { 799 ret = psp_spatial_partition(&adev->psp, 800 NUM_XCC(adev->gfx.xcc_mask) / 801 num_xccs_per_xcp); 802 if (ret) 803 return ret; 804 } else { 805 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 806 807 for (i = 0; i < num_xcc; i++) { 808 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 809 num_xccs_per_xcp); 810 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 811 i % num_xccs_per_xcp); 812 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 813 tmp); 814 } 815 ret = 0; 816 } 817 818 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 819 820 return ret; 821 } 822 823 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 824 { 825 int xcc; 826 827 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 828 if (!xcc) { 829 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 830 return -EINVAL; 831 } 832 833 return xcc - 1; 834 } 835 836 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 837 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 838 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 839 .read_wave_data = &gfx_v9_4_3_read_wave_data, 840 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 841 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 842 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 843 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 844 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 845 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 846 }; 847 848 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 849 struct aca_bank *bank, enum aca_smu_type type, 850 void *data) 851 { 852 struct aca_bank_info info; 853 u64 misc0; 854 u32 instlo; 855 int ret; 856 857 ret = aca_bank_info_decode(bank, &info); 858 if (ret) 859 return ret; 860 861 /* NOTE: overwrite info.die_id with xcd id for gfx */ 862 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 863 instlo &= GENMASK(31, 1); 864 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 865 866 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 867 868 switch (type) { 869 case ACA_SMU_TYPE_UE: 870 bank->aca_err_type = ACA_ERROR_TYPE_UE; 871 ret = aca_error_cache_log_bank_error(handle, &info, 872 ACA_ERROR_TYPE_UE, 1ULL); 873 break; 874 case ACA_SMU_TYPE_CE: 875 bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); 876 ret = aca_error_cache_log_bank_error(handle, &info, 877 bank->aca_err_type, 878 ACA_REG__MISC0__ERRCNT(misc0)); 879 break; 880 default: 881 return -EINVAL; 882 } 883 884 return ret; 885 } 886 887 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 888 enum aca_smu_type type, void *data) 889 { 890 u32 instlo; 891 892 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 893 instlo &= GENMASK(31, 1); 894 switch (instlo) { 895 case mmSMNAID_XCD0_MCA_SMU: 896 case mmSMNAID_XCD1_MCA_SMU: 897 case mmSMNXCD_XCD0_MCA_SMU: 898 return true; 899 default: 900 break; 901 } 902 903 return false; 904 } 905 906 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 907 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 908 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 909 }; 910 911 static const struct aca_info gfx_v9_4_3_aca_info = { 912 .hwip = ACA_HWIP_TYPE_SMU, 913 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 914 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 915 }; 916 917 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 918 { 919 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 920 adev->gfx.ras = &gfx_v9_4_3_ras; 921 922 adev->gfx.config.max_hw_contexts = 8; 923 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 924 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 925 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 926 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 927 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 928 929 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 930 REG_GET_FIELD( 931 adev->gfx.config.gb_addr_config, 932 GB_ADDR_CONFIG, 933 NUM_PIPES); 934 935 adev->gfx.config.max_tile_pipes = 936 adev->gfx.config.gb_addr_config_fields.num_pipes; 937 938 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 939 REG_GET_FIELD( 940 adev->gfx.config.gb_addr_config, 941 GB_ADDR_CONFIG, 942 NUM_BANKS); 943 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 944 REG_GET_FIELD( 945 adev->gfx.config.gb_addr_config, 946 GB_ADDR_CONFIG, 947 MAX_COMPRESSED_FRAGS); 948 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 949 REG_GET_FIELD( 950 adev->gfx.config.gb_addr_config, 951 GB_ADDR_CONFIG, 952 NUM_RB_PER_SE); 953 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 954 REG_GET_FIELD( 955 adev->gfx.config.gb_addr_config, 956 GB_ADDR_CONFIG, 957 NUM_SHADER_ENGINES); 958 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 959 REG_GET_FIELD( 960 adev->gfx.config.gb_addr_config, 961 GB_ADDR_CONFIG, 962 PIPE_INTERLEAVE_SIZE)); 963 964 return 0; 965 } 966 967 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 968 int xcc_id, int mec, int pipe, int queue) 969 { 970 unsigned irq_type; 971 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 972 unsigned int hw_prio; 973 uint32_t xcc_doorbell_start; 974 975 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 976 ring_id]; 977 978 /* mec0 is me1 */ 979 ring->xcc_id = xcc_id; 980 ring->me = mec + 1; 981 ring->pipe = pipe; 982 ring->queue = queue; 983 984 ring->ring_obj = NULL; 985 ring->use_doorbell = true; 986 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 987 xcc_id * adev->doorbell_index.xcc_doorbell_range; 988 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 989 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 990 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 991 GFX9_MEC_HPD_SIZE; 992 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 993 sprintf(ring->name, "comp_%d.%d.%d.%d", 994 ring->xcc_id, ring->me, ring->pipe, ring->queue); 995 996 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 997 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 998 + ring->pipe; 999 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1000 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1001 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1002 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1003 hw_prio, NULL); 1004 } 1005 1006 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1007 { 1008 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1009 uint32_t *ptr, num_xcc, inst; 1010 1011 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1012 1013 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1014 if (!ptr) { 1015 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1016 adev->gfx.ip_dump_core = NULL; 1017 } else { 1018 adev->gfx.ip_dump_core = ptr; 1019 } 1020 1021 /* Allocate memory for compute queue registers for all the instances */ 1022 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1023 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1024 adev->gfx.mec.num_queue_per_pipe; 1025 1026 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1027 if (!ptr) { 1028 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1029 adev->gfx.ip_dump_compute_queues = NULL; 1030 } else { 1031 adev->gfx.ip_dump_compute_queues = ptr; 1032 } 1033 } 1034 1035 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1036 { 1037 int i, j, k, r, ring_id, xcc_id, num_xcc; 1038 struct amdgpu_device *adev = ip_block->adev; 1039 1040 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1041 case IP_VERSION(9, 4, 3): 1042 case IP_VERSION(9, 4, 4): 1043 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1044 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1045 if (adev->gfx.mec_fw_version >= 153) { 1046 adev->gfx.enable_cleaner_shader = true; 1047 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1048 if (r) { 1049 adev->gfx.enable_cleaner_shader = false; 1050 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1051 } 1052 } 1053 break; 1054 default: 1055 adev->gfx.enable_cleaner_shader = false; 1056 break; 1057 } 1058 1059 adev->gfx.mec.num_mec = 2; 1060 adev->gfx.mec.num_pipe_per_mec = 4; 1061 adev->gfx.mec.num_queue_per_pipe = 8; 1062 1063 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1064 1065 /* EOP Event */ 1066 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1067 if (r) 1068 return r; 1069 1070 /* Bad opcode Event */ 1071 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1072 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1073 &adev->gfx.bad_op_irq); 1074 if (r) 1075 return r; 1076 1077 /* Privileged reg */ 1078 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1079 &adev->gfx.priv_reg_irq); 1080 if (r) 1081 return r; 1082 1083 /* Privileged inst */ 1084 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1085 &adev->gfx.priv_inst_irq); 1086 if (r) 1087 return r; 1088 1089 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1090 1091 r = adev->gfx.rlc.funcs->init(adev); 1092 if (r) { 1093 DRM_ERROR("Failed to init rlc BOs!\n"); 1094 return r; 1095 } 1096 1097 r = gfx_v9_4_3_mec_init(adev); 1098 if (r) { 1099 DRM_ERROR("Failed to init MEC BOs!\n"); 1100 return r; 1101 } 1102 1103 /* set up the compute queues - allocate horizontally across pipes */ 1104 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1105 ring_id = 0; 1106 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1107 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1108 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1109 k++) { 1110 if (!amdgpu_gfx_is_mec_queue_enabled( 1111 adev, xcc_id, i, k, j)) 1112 continue; 1113 1114 r = gfx_v9_4_3_compute_ring_init(adev, 1115 ring_id, 1116 xcc_id, 1117 i, k, j); 1118 if (r) 1119 return r; 1120 1121 ring_id++; 1122 } 1123 } 1124 } 1125 1126 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1127 if (r) { 1128 DRM_ERROR("Failed to init KIQ BOs!\n"); 1129 return r; 1130 } 1131 1132 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1133 if (r) 1134 return r; 1135 1136 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1137 r = amdgpu_gfx_mqd_sw_init(adev, 1138 sizeof(struct v9_mqd_allocation), xcc_id); 1139 if (r) 1140 return r; 1141 } 1142 1143 adev->gfx.compute_supported_reset = 1144 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1145 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1146 case IP_VERSION(9, 4, 3): 1147 case IP_VERSION(9, 4, 4): 1148 if (adev->gfx.mec_fw_version >= 155) { 1149 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1150 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1151 } 1152 break; 1153 default: 1154 break; 1155 } 1156 r = gfx_v9_4_3_gpu_early_init(adev); 1157 if (r) 1158 return r; 1159 1160 r = amdgpu_gfx_ras_sw_init(adev); 1161 if (r) 1162 return r; 1163 1164 r = amdgpu_gfx_sysfs_init(adev); 1165 if (r) 1166 return r; 1167 1168 gfx_v9_4_3_alloc_ip_dump(adev); 1169 1170 return 0; 1171 } 1172 1173 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1174 { 1175 int i, num_xcc; 1176 struct amdgpu_device *adev = ip_block->adev; 1177 1178 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1179 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1180 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1181 1182 for (i = 0; i < num_xcc; i++) { 1183 amdgpu_gfx_mqd_sw_fini(adev, i); 1184 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1185 amdgpu_gfx_kiq_fini(adev, i); 1186 } 1187 1188 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1189 1190 gfx_v9_4_3_mec_fini(adev); 1191 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1192 gfx_v9_4_3_free_microcode(adev); 1193 amdgpu_gfx_sysfs_fini(adev); 1194 1195 kfree(adev->gfx.ip_dump_core); 1196 kfree(adev->gfx.ip_dump_compute_queues); 1197 1198 return 0; 1199 } 1200 1201 #define DEFAULT_SH_MEM_BASES (0x6000) 1202 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1203 int xcc_id) 1204 { 1205 int i; 1206 uint32_t sh_mem_config; 1207 uint32_t sh_mem_bases; 1208 uint32_t data; 1209 1210 /* 1211 * Configure apertures: 1212 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1213 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1214 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1215 */ 1216 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1217 1218 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1219 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1220 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1221 1222 mutex_lock(&adev->srbm_mutex); 1223 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1224 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1225 /* CP and shaders */ 1226 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1227 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1228 1229 /* Enable trap for each kfd vmid. */ 1230 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1231 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1232 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1233 } 1234 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1235 mutex_unlock(&adev->srbm_mutex); 1236 1237 /* 1238 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1239 * access. These should be enabled by FW for target VMIDs. 1240 */ 1241 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1242 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1243 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1244 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1245 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1246 } 1247 } 1248 1249 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1250 { 1251 int vmid; 1252 1253 /* 1254 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1255 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1256 * the driver can enable them for graphics. VMID0 should maintain 1257 * access so that HWS firmware can save/restore entries. 1258 */ 1259 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1260 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1261 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1262 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1263 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1264 } 1265 } 1266 1267 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1268 int xcc_id) 1269 { 1270 u32 tmp; 1271 int i; 1272 1273 /* XXX SH_MEM regs */ 1274 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1275 mutex_lock(&adev->srbm_mutex); 1276 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1277 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1278 /* CP and shaders */ 1279 if (i == 0) { 1280 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1281 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1282 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1283 !!adev->gmc.noretry); 1284 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1285 regSH_MEM_CONFIG, tmp); 1286 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1287 regSH_MEM_BASES, 0); 1288 } else { 1289 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1290 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1291 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1292 !!adev->gmc.noretry); 1293 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1294 regSH_MEM_CONFIG, tmp); 1295 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1296 (adev->gmc.private_aperture_start >> 1297 48)); 1298 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1299 (adev->gmc.shared_aperture_start >> 1300 48)); 1301 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1302 regSH_MEM_BASES, tmp); 1303 } 1304 } 1305 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1306 1307 mutex_unlock(&adev->srbm_mutex); 1308 1309 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1310 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1311 } 1312 1313 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1314 { 1315 int i, num_xcc; 1316 1317 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1318 1319 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1320 adev->gfx.config.db_debug2 = 1321 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1322 1323 for (i = 0; i < num_xcc; i++) 1324 gfx_v9_4_3_xcc_constants_init(adev, i); 1325 } 1326 1327 static void 1328 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1329 int xcc_id) 1330 { 1331 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1332 } 1333 1334 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1335 { 1336 /* 1337 * Rlc save restore list is workable since v2_1. 1338 */ 1339 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1340 } 1341 1342 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1343 { 1344 uint32_t data; 1345 1346 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1347 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1349 } 1350 1351 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1352 { 1353 uint32_t rlc_setting; 1354 1355 /* if RLC is not enabled, do nothing */ 1356 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1357 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1358 return false; 1359 1360 return true; 1361 } 1362 1363 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1364 { 1365 uint32_t data; 1366 unsigned i; 1367 1368 data = RLC_SAFE_MODE__CMD_MASK; 1369 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1370 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1371 1372 /* wait for RLC_SAFE_MODE */ 1373 for (i = 0; i < adev->usec_timeout; i++) { 1374 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1375 break; 1376 udelay(1); 1377 } 1378 } 1379 1380 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1381 int xcc_id) 1382 { 1383 uint32_t data; 1384 1385 data = RLC_SAFE_MODE__CMD_MASK; 1386 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1387 } 1388 1389 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1390 { 1391 int xcc_id, num_xcc; 1392 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1393 1394 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1395 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1396 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1397 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1398 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1399 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1400 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1401 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1402 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1403 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1404 } 1405 adev->gfx.rlc.rlcg_reg_access_supported = true; 1406 } 1407 1408 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1409 { 1410 /* init spm vmid with 0xf */ 1411 if (adev->gfx.rlc.funcs->update_spm_vmid) 1412 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1413 1414 return 0; 1415 } 1416 1417 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1418 int xcc_id) 1419 { 1420 u32 i, j, k; 1421 u32 mask; 1422 1423 mutex_lock(&adev->grbm_idx_mutex); 1424 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1425 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1426 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1427 xcc_id); 1428 for (k = 0; k < adev->usec_timeout; k++) { 1429 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1430 break; 1431 udelay(1); 1432 } 1433 if (k == adev->usec_timeout) { 1434 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1435 0xffffffff, 1436 0xffffffff, xcc_id); 1437 mutex_unlock(&adev->grbm_idx_mutex); 1438 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1439 i, j); 1440 return; 1441 } 1442 } 1443 } 1444 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1445 xcc_id); 1446 mutex_unlock(&adev->grbm_idx_mutex); 1447 1448 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1449 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1450 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1451 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1452 for (k = 0; k < adev->usec_timeout; k++) { 1453 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1454 break; 1455 udelay(1); 1456 } 1457 } 1458 1459 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1460 bool enable, int xcc_id) 1461 { 1462 u32 tmp; 1463 1464 /* These interrupts should be enabled to drive DS clock */ 1465 1466 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1467 1468 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1469 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1470 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1471 1472 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1473 } 1474 1475 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1476 { 1477 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1478 RLC_ENABLE_F32, 0); 1479 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1480 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1481 } 1482 1483 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1484 { 1485 int i, num_xcc; 1486 1487 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1488 for (i = 0; i < num_xcc; i++) 1489 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1490 } 1491 1492 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1493 { 1494 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1495 SOFT_RESET_RLC, 1); 1496 udelay(50); 1497 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1498 SOFT_RESET_RLC, 0); 1499 udelay(50); 1500 } 1501 1502 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1503 { 1504 int i, num_xcc; 1505 1506 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1507 for (i = 0; i < num_xcc; i++) 1508 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1509 } 1510 1511 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1512 { 1513 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1514 RLC_ENABLE_F32, 1); 1515 udelay(50); 1516 1517 /* carrizo do enable cp interrupt after cp inited */ 1518 if (!(adev->flags & AMD_IS_APU)) { 1519 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1520 udelay(50); 1521 } 1522 } 1523 1524 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1525 { 1526 #ifdef AMDGPU_RLC_DEBUG_RETRY 1527 u32 rlc_ucode_ver; 1528 #endif 1529 int i, num_xcc; 1530 1531 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1532 for (i = 0; i < num_xcc; i++) { 1533 gfx_v9_4_3_xcc_rlc_start(adev, i); 1534 #ifdef AMDGPU_RLC_DEBUG_RETRY 1535 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1536 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1537 if (rlc_ucode_ver == 0x108) { 1538 dev_info(adev->dev, 1539 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1540 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1541 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1542 * default is 0x9C4 to create a 100us interval */ 1543 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1544 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1545 * to disable the page fault retry interrupts, default is 1546 * 0x100 (256) */ 1547 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1548 } 1549 #endif 1550 } 1551 } 1552 1553 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1554 int xcc_id) 1555 { 1556 const struct rlc_firmware_header_v2_0 *hdr; 1557 const __le32 *fw_data; 1558 unsigned i, fw_size; 1559 1560 if (!adev->gfx.rlc_fw) 1561 return -EINVAL; 1562 1563 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1564 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1565 1566 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1567 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1568 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1569 1570 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1571 RLCG_UCODE_LOADING_START_ADDRESS); 1572 for (i = 0; i < fw_size; i++) { 1573 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1574 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1575 msleep(1); 1576 } 1577 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1578 } 1579 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1580 1581 return 0; 1582 } 1583 1584 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1585 { 1586 int r; 1587 1588 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1589 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1590 /* legacy rlc firmware loading */ 1591 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1592 if (r) 1593 return r; 1594 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1595 } 1596 1597 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1598 /* disable CG */ 1599 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1600 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1601 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1602 1603 return 0; 1604 } 1605 1606 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1607 { 1608 int r, i, num_xcc; 1609 1610 if (amdgpu_sriov_vf(adev)) 1611 return 0; 1612 1613 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1614 for (i = 0; i < num_xcc; i++) { 1615 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1616 if (r) 1617 return r; 1618 } 1619 1620 return 0; 1621 } 1622 1623 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1624 unsigned vmid) 1625 { 1626 u32 reg, pre_data, data; 1627 1628 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1629 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1630 pre_data = RREG32_NO_KIQ(reg); 1631 else 1632 pre_data = RREG32(reg); 1633 1634 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1635 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1636 1637 if (pre_data != data) { 1638 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1639 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1640 } else 1641 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1642 } 1643 } 1644 1645 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1646 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1647 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1648 }; 1649 1650 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1651 uint32_t offset, 1652 struct soc15_reg_rlcg *entries, int arr_size) 1653 { 1654 int i, inst; 1655 uint32_t reg; 1656 1657 if (!entries) 1658 return false; 1659 1660 for (i = 0; i < arr_size; i++) { 1661 const struct soc15_reg_rlcg *entry; 1662 1663 entry = &entries[i]; 1664 inst = adev->ip_map.logical_to_dev_inst ? 1665 adev->ip_map.logical_to_dev_inst( 1666 adev, entry->hwip, entry->instance) : 1667 entry->instance; 1668 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1669 entry->reg; 1670 if (offset == reg) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1678 { 1679 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1680 (void *)rlcg_access_gc_9_4_3, 1681 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1682 } 1683 1684 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1685 bool enable, int xcc_id) 1686 { 1687 if (enable) { 1688 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1689 } else { 1690 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1691 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1692 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1693 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1694 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1695 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1696 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1697 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1698 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1699 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1700 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1701 } 1702 udelay(50); 1703 } 1704 1705 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1706 int xcc_id) 1707 { 1708 const struct gfx_firmware_header_v1_0 *mec_hdr; 1709 const __le32 *fw_data; 1710 unsigned i; 1711 u32 tmp; 1712 u32 mec_ucode_addr_offset; 1713 u32 mec_ucode_data_offset; 1714 1715 if (!adev->gfx.mec_fw) 1716 return -EINVAL; 1717 1718 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1719 1720 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1721 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1722 1723 fw_data = (const __le32 *) 1724 (adev->gfx.mec_fw->data + 1725 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1726 tmp = 0; 1727 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1728 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1729 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1730 1731 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1732 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1733 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1734 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1735 1736 mec_ucode_addr_offset = 1737 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1738 mec_ucode_data_offset = 1739 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1740 1741 /* MEC1 */ 1742 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1743 for (i = 0; i < mec_hdr->jt_size; i++) 1744 WREG32(mec_ucode_data_offset, 1745 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1746 1747 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1748 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1749 1750 return 0; 1751 } 1752 1753 /* KIQ functions */ 1754 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1755 { 1756 uint32_t tmp; 1757 struct amdgpu_device *adev = ring->adev; 1758 1759 /* tell RLC which is KIQ queue */ 1760 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1761 tmp &= 0xffffff00; 1762 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1763 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1764 } 1765 1766 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1767 { 1768 struct amdgpu_device *adev = ring->adev; 1769 1770 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1771 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1772 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1773 mqd->cp_hqd_queue_priority = 1774 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1775 } 1776 } 1777 } 1778 1779 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1780 { 1781 struct amdgpu_device *adev = ring->adev; 1782 struct v9_mqd *mqd = ring->mqd_ptr; 1783 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1784 uint32_t tmp; 1785 1786 mqd->header = 0xC0310800; 1787 mqd->compute_pipelinestat_enable = 0x00000001; 1788 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1789 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1790 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1791 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1792 mqd->compute_misc_reserved = 0x00000003; 1793 1794 mqd->dynamic_cu_mask_addr_lo = 1795 lower_32_bits(ring->mqd_gpu_addr 1796 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1797 mqd->dynamic_cu_mask_addr_hi = 1798 upper_32_bits(ring->mqd_gpu_addr 1799 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1800 1801 eop_base_addr = ring->eop_gpu_addr >> 8; 1802 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1803 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1804 1805 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1806 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1807 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1808 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1809 1810 mqd->cp_hqd_eop_control = tmp; 1811 1812 /* enable doorbell? */ 1813 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1814 1815 if (ring->use_doorbell) { 1816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1817 DOORBELL_OFFSET, ring->doorbell_index); 1818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1819 DOORBELL_EN, 1); 1820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1821 DOORBELL_SOURCE, 0); 1822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1823 DOORBELL_HIT, 0); 1824 if (amdgpu_sriov_vf(adev)) 1825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1826 DOORBELL_MODE, 1); 1827 } else { 1828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1829 DOORBELL_EN, 0); 1830 } 1831 1832 mqd->cp_hqd_pq_doorbell_control = tmp; 1833 1834 /* disable the queue if it's active */ 1835 ring->wptr = 0; 1836 mqd->cp_hqd_dequeue_request = 0; 1837 mqd->cp_hqd_pq_rptr = 0; 1838 mqd->cp_hqd_pq_wptr_lo = 0; 1839 mqd->cp_hqd_pq_wptr_hi = 0; 1840 1841 /* set the pointer to the MQD */ 1842 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1843 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1844 1845 /* set MQD vmid to 0 */ 1846 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1847 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1848 mqd->cp_mqd_control = tmp; 1849 1850 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1851 hqd_gpu_addr = ring->gpu_addr >> 8; 1852 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1853 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1854 1855 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1856 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1857 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1858 (order_base_2(ring->ring_size / 4) - 1)); 1859 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1860 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1861 #ifdef __BIG_ENDIAN 1862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1863 #endif 1864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1866 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1868 mqd->cp_hqd_pq_control = tmp; 1869 1870 /* set the wb address whether it's enabled or not */ 1871 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1872 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1873 mqd->cp_hqd_pq_rptr_report_addr_hi = 1874 upper_32_bits(wb_gpu_addr) & 0xffff; 1875 1876 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1877 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1878 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1879 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1880 1881 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1882 ring->wptr = 0; 1883 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1884 1885 /* set the vmid for the queue */ 1886 mqd->cp_hqd_vmid = 0; 1887 1888 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1889 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1890 mqd->cp_hqd_persistent_state = tmp; 1891 1892 /* set MIN_IB_AVAIL_SIZE */ 1893 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1894 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1895 mqd->cp_hqd_ib_control = tmp; 1896 1897 /* set static priority for a queue/ring */ 1898 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1899 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1900 1901 /* map_queues packet doesn't need activate the queue, 1902 * so only kiq need set this field. 1903 */ 1904 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1905 mqd->cp_hqd_active = 1; 1906 1907 return 0; 1908 } 1909 1910 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1911 int xcc_id) 1912 { 1913 struct amdgpu_device *adev = ring->adev; 1914 struct v9_mqd *mqd = ring->mqd_ptr; 1915 int j; 1916 1917 /* disable wptr polling */ 1918 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1919 1920 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1921 mqd->cp_hqd_eop_base_addr_lo); 1922 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1923 mqd->cp_hqd_eop_base_addr_hi); 1924 1925 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1927 mqd->cp_hqd_eop_control); 1928 1929 /* enable doorbell? */ 1930 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1931 mqd->cp_hqd_pq_doorbell_control); 1932 1933 /* disable the queue if it's active */ 1934 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1935 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1936 for (j = 0; j < adev->usec_timeout; j++) { 1937 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1938 break; 1939 udelay(1); 1940 } 1941 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1942 mqd->cp_hqd_dequeue_request); 1943 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1944 mqd->cp_hqd_pq_rptr); 1945 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1946 mqd->cp_hqd_pq_wptr_lo); 1947 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1948 mqd->cp_hqd_pq_wptr_hi); 1949 } 1950 1951 /* set the pointer to the MQD */ 1952 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1953 mqd->cp_mqd_base_addr_lo); 1954 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1955 mqd->cp_mqd_base_addr_hi); 1956 1957 /* set MQD vmid to 0 */ 1958 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1959 mqd->cp_mqd_control); 1960 1961 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1962 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1963 mqd->cp_hqd_pq_base_lo); 1964 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1965 mqd->cp_hqd_pq_base_hi); 1966 1967 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1968 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1969 mqd->cp_hqd_pq_control); 1970 1971 /* set the wb address whether it's enabled or not */ 1972 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1973 mqd->cp_hqd_pq_rptr_report_addr_lo); 1974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1975 mqd->cp_hqd_pq_rptr_report_addr_hi); 1976 1977 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1979 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1980 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1981 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1982 1983 /* enable the doorbell if requested */ 1984 if (ring->use_doorbell) { 1985 WREG32_SOC15( 1986 GC, GET_INST(GC, xcc_id), 1987 regCP_MEC_DOORBELL_RANGE_LOWER, 1988 ((adev->doorbell_index.kiq + 1989 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1990 2) << 2); 1991 WREG32_SOC15( 1992 GC, GET_INST(GC, xcc_id), 1993 regCP_MEC_DOORBELL_RANGE_UPPER, 1994 ((adev->doorbell_index.userqueue_end + 1995 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1996 2) << 2); 1997 } 1998 1999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2000 mqd->cp_hqd_pq_doorbell_control); 2001 2002 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2004 mqd->cp_hqd_pq_wptr_lo); 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2006 mqd->cp_hqd_pq_wptr_hi); 2007 2008 /* set the vmid for the queue */ 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2010 2011 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2012 mqd->cp_hqd_persistent_state); 2013 2014 /* activate the queue */ 2015 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2016 mqd->cp_hqd_active); 2017 2018 if (ring->use_doorbell) 2019 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2020 2021 return 0; 2022 } 2023 2024 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2025 int xcc_id) 2026 { 2027 struct amdgpu_device *adev = ring->adev; 2028 int j; 2029 2030 /* disable the queue if it's active */ 2031 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2032 2033 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2034 2035 for (j = 0; j < adev->usec_timeout; j++) { 2036 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2037 break; 2038 udelay(1); 2039 } 2040 2041 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2042 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2043 2044 /* Manual disable if dequeue request times out */ 2045 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2046 } 2047 2048 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2049 0); 2050 } 2051 2052 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2053 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2057 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2058 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2059 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2060 2061 return 0; 2062 } 2063 2064 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2065 { 2066 struct amdgpu_device *adev = ring->adev; 2067 struct v9_mqd *mqd = ring->mqd_ptr; 2068 struct v9_mqd *tmp_mqd; 2069 2070 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2071 2072 /* GPU could be in bad state during probe, driver trigger the reset 2073 * after load the SMU, in this case , the mqd is not be initialized. 2074 * driver need to re-init the mqd. 2075 * check mqd->cp_hqd_pq_control since this value should not be 0 2076 */ 2077 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2078 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2079 /* for GPU_RESET case , reset MQD to a clean status */ 2080 if (adev->gfx.kiq[xcc_id].mqd_backup) 2081 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2082 2083 /* reset ring buffer */ 2084 ring->wptr = 0; 2085 amdgpu_ring_clear_ring(ring); 2086 mutex_lock(&adev->srbm_mutex); 2087 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2088 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2089 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2090 mutex_unlock(&adev->srbm_mutex); 2091 } else { 2092 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2093 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2094 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2095 mutex_lock(&adev->srbm_mutex); 2096 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2097 amdgpu_ring_clear_ring(ring); 2098 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2099 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2100 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2101 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2102 mutex_unlock(&adev->srbm_mutex); 2103 2104 if (adev->gfx.kiq[xcc_id].mqd_backup) 2105 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2112 { 2113 struct amdgpu_device *adev = ring->adev; 2114 struct v9_mqd *mqd = ring->mqd_ptr; 2115 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2116 struct v9_mqd *tmp_mqd; 2117 2118 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2119 * is not be initialized before 2120 */ 2121 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2122 2123 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2124 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2125 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2126 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2127 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2128 mutex_lock(&adev->srbm_mutex); 2129 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2130 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2131 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2132 mutex_unlock(&adev->srbm_mutex); 2133 2134 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2135 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2136 } else { 2137 /* restore MQD to a clean status */ 2138 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2139 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2140 /* reset ring buffer */ 2141 ring->wptr = 0; 2142 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2143 amdgpu_ring_clear_ring(ring); 2144 } 2145 2146 return 0; 2147 } 2148 2149 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2150 { 2151 struct amdgpu_ring *ring; 2152 int j; 2153 2154 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2155 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2156 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2157 mutex_lock(&adev->srbm_mutex); 2158 soc15_grbm_select(adev, ring->me, 2159 ring->pipe, 2160 ring->queue, 0, GET_INST(GC, xcc_id)); 2161 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2162 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2163 mutex_unlock(&adev->srbm_mutex); 2164 } 2165 } 2166 2167 return 0; 2168 } 2169 2170 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2171 { 2172 struct amdgpu_ring *ring; 2173 int r; 2174 2175 ring = &adev->gfx.kiq[xcc_id].ring; 2176 2177 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2178 if (unlikely(r != 0)) 2179 return r; 2180 2181 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2182 if (unlikely(r != 0)) { 2183 amdgpu_bo_unreserve(ring->mqd_obj); 2184 return r; 2185 } 2186 2187 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2188 amdgpu_bo_kunmap(ring->mqd_obj); 2189 ring->mqd_ptr = NULL; 2190 amdgpu_bo_unreserve(ring->mqd_obj); 2191 return 0; 2192 } 2193 2194 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2195 { 2196 struct amdgpu_ring *ring = NULL; 2197 int r = 0, i; 2198 2199 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2200 2201 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2202 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2203 2204 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2205 if (unlikely(r != 0)) 2206 goto done; 2207 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2208 if (!r) { 2209 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2210 amdgpu_bo_kunmap(ring->mqd_obj); 2211 ring->mqd_ptr = NULL; 2212 } 2213 amdgpu_bo_unreserve(ring->mqd_obj); 2214 if (r) 2215 goto done; 2216 } 2217 2218 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2219 done: 2220 return r; 2221 } 2222 2223 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2224 { 2225 struct amdgpu_ring *ring; 2226 int r, j; 2227 2228 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2229 2230 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2231 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2232 2233 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2234 if (r) 2235 return r; 2236 } else { 2237 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2238 } 2239 2240 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2241 if (r) 2242 return r; 2243 2244 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2245 if (r) 2246 return r; 2247 2248 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2249 ring = &adev->gfx.compute_ring 2250 [j + xcc_id * adev->gfx.num_compute_rings]; 2251 r = amdgpu_ring_test_helper(ring); 2252 if (r) 2253 return r; 2254 } 2255 2256 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2257 2258 return 0; 2259 } 2260 2261 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2262 { 2263 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2264 2265 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2266 if (amdgpu_sriov_vf(adev)) { 2267 enum amdgpu_gfx_partition mode; 2268 2269 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2270 AMDGPU_XCP_FL_NONE); 2271 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2272 return -EINVAL; 2273 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2274 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2275 num_xcp = num_xcc / num_xcc_per_xcp; 2276 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2277 2278 } else { 2279 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2280 AMDGPU_XCP_FL_NONE) == 2281 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2282 r = amdgpu_xcp_switch_partition_mode( 2283 adev->xcp_mgr, amdgpu_user_partt_mode); 2284 } 2285 if (r) 2286 return r; 2287 2288 for (i = 0; i < num_xcc; i++) { 2289 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2290 if (r) 2291 return r; 2292 } 2293 2294 return 0; 2295 } 2296 2297 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2298 { 2299 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2300 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2301 2302 if (amdgpu_sriov_vf(adev)) { 2303 /* must disable polling for SRIOV when hw finished, otherwise 2304 * CPC engine may still keep fetching WB address which is already 2305 * invalid after sw finished and trigger DMAR reading error in 2306 * hypervisor side. 2307 */ 2308 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2309 return; 2310 } 2311 2312 /* Use deinitialize sequence from CAIL when unbinding device 2313 * from driver, otherwise KIQ is hanging when binding back 2314 */ 2315 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2316 mutex_lock(&adev->srbm_mutex); 2317 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2318 adev->gfx.kiq[xcc_id].ring.pipe, 2319 adev->gfx.kiq[xcc_id].ring.queue, 0, 2320 GET_INST(GC, xcc_id)); 2321 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2322 xcc_id); 2323 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2324 mutex_unlock(&adev->srbm_mutex); 2325 } 2326 2327 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2328 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2329 } 2330 2331 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2332 { 2333 int r; 2334 struct amdgpu_device *adev = ip_block->adev; 2335 2336 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2337 adev->gfx.cleaner_shader_ptr); 2338 2339 if (!amdgpu_sriov_vf(adev)) 2340 gfx_v9_4_3_init_golden_registers(adev); 2341 2342 gfx_v9_4_3_constants_init(adev); 2343 2344 r = adev->gfx.rlc.funcs->resume(adev); 2345 if (r) 2346 return r; 2347 2348 r = gfx_v9_4_3_cp_resume(adev); 2349 if (r) 2350 return r; 2351 2352 return r; 2353 } 2354 2355 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2356 { 2357 struct amdgpu_device *adev = ip_block->adev; 2358 int i, num_xcc; 2359 2360 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2361 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2362 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2363 2364 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2365 for (i = 0; i < num_xcc; i++) { 2366 gfx_v9_4_3_xcc_fini(adev, i); 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2373 { 2374 return gfx_v9_4_3_hw_fini(ip_block); 2375 } 2376 2377 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2378 { 2379 return gfx_v9_4_3_hw_init(ip_block); 2380 } 2381 2382 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2383 { 2384 struct amdgpu_device *adev = ip_block->adev; 2385 int i, num_xcc; 2386 2387 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2388 for (i = 0; i < num_xcc; i++) { 2389 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2390 GRBM_STATUS, GUI_ACTIVE)) 2391 return false; 2392 } 2393 return true; 2394 } 2395 2396 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2397 { 2398 unsigned i; 2399 struct amdgpu_device *adev = ip_block->adev; 2400 2401 for (i = 0; i < adev->usec_timeout; i++) { 2402 if (gfx_v9_4_3_is_idle(ip_block)) 2403 return 0; 2404 udelay(1); 2405 } 2406 return -ETIMEDOUT; 2407 } 2408 2409 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2410 { 2411 u32 grbm_soft_reset = 0; 2412 u32 tmp; 2413 struct amdgpu_device *adev = ip_block->adev; 2414 2415 /* GRBM_STATUS */ 2416 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2417 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2418 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2419 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2420 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2421 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2422 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2423 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2424 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2425 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2426 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2427 } 2428 2429 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2430 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2431 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2432 } 2433 2434 /* GRBM_STATUS2 */ 2435 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2436 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2437 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2438 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2439 2440 2441 if (grbm_soft_reset) { 2442 /* stop the rlc */ 2443 adev->gfx.rlc.funcs->stop(adev); 2444 2445 /* Disable MEC parsing/prefetching */ 2446 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2447 2448 if (grbm_soft_reset) { 2449 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2450 tmp |= grbm_soft_reset; 2451 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2452 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2453 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2454 2455 udelay(50); 2456 2457 tmp &= ~grbm_soft_reset; 2458 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2459 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2460 } 2461 2462 /* Wait a little for things to settle down */ 2463 udelay(50); 2464 } 2465 return 0; 2466 } 2467 2468 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2469 uint32_t vmid, 2470 uint32_t gds_base, uint32_t gds_size, 2471 uint32_t gws_base, uint32_t gws_size, 2472 uint32_t oa_base, uint32_t oa_size) 2473 { 2474 struct amdgpu_device *adev = ring->adev; 2475 2476 /* GDS Base */ 2477 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2478 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2479 gds_base); 2480 2481 /* GDS Size */ 2482 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2483 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2484 gds_size); 2485 2486 /* GWS */ 2487 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2488 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2489 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2490 2491 /* OA */ 2492 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2493 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2494 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2495 } 2496 2497 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2498 { 2499 struct amdgpu_device *adev = ip_block->adev; 2500 2501 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2502 AMDGPU_MAX_COMPUTE_RINGS); 2503 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2504 gfx_v9_4_3_set_ring_funcs(adev); 2505 gfx_v9_4_3_set_irq_funcs(adev); 2506 gfx_v9_4_3_set_gds_init(adev); 2507 gfx_v9_4_3_set_rlc_funcs(adev); 2508 2509 /* init rlcg reg access ctrl */ 2510 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2511 2512 return gfx_v9_4_3_init_microcode(adev); 2513 } 2514 2515 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2516 { 2517 struct amdgpu_device *adev = ip_block->adev; 2518 int r; 2519 2520 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2521 if (r) 2522 return r; 2523 2524 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2525 if (r) 2526 return r; 2527 2528 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2529 if (r) 2530 return r; 2531 2532 if (adev->gfx.ras && 2533 adev->gfx.ras->enable_watchdog_timer) 2534 adev->gfx.ras->enable_watchdog_timer(adev); 2535 2536 return 0; 2537 } 2538 2539 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2540 bool enable, int xcc_id) 2541 { 2542 uint32_t def, data; 2543 2544 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2545 return; 2546 2547 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2548 regRLC_CGTT_MGCG_OVERRIDE); 2549 2550 if (enable) 2551 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2552 else 2553 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2554 2555 if (def != data) 2556 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2557 regRLC_CGTT_MGCG_OVERRIDE, data); 2558 2559 } 2560 2561 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2562 bool enable, int xcc_id) 2563 { 2564 uint32_t def, data; 2565 2566 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2567 return; 2568 2569 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2570 regRLC_CGTT_MGCG_OVERRIDE); 2571 2572 if (enable) 2573 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2574 else 2575 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2576 2577 if (def != data) 2578 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2579 regRLC_CGTT_MGCG_OVERRIDE, data); 2580 } 2581 2582 static void 2583 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2584 bool enable, int xcc_id) 2585 { 2586 uint32_t data, def; 2587 2588 /* It is disabled by HW by default */ 2589 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2590 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2591 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2592 2593 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2594 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2595 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2596 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2597 2598 if (def != data) 2599 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2600 2601 /* MGLS is a global flag to control all MGLS in GFX */ 2602 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2603 /* 2 - RLC memory Light sleep */ 2604 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2605 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2606 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2607 if (def != data) 2608 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2609 } 2610 /* 3 - CP memory Light sleep */ 2611 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2612 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2613 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2614 if (def != data) 2615 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2616 } 2617 } 2618 } else { 2619 /* 1 - MGCG_OVERRIDE */ 2620 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2621 2622 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2623 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2624 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2625 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2626 2627 if (def != data) 2628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2629 2630 /* 2 - disable MGLS in RLC */ 2631 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2632 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2633 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2634 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2635 } 2636 2637 /* 3 - disable MGLS in CP */ 2638 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2639 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2640 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2641 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2642 } 2643 } 2644 2645 } 2646 2647 static void 2648 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2649 bool enable, int xcc_id) 2650 { 2651 uint32_t def, data; 2652 2653 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2654 2655 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2656 /* unset CGCG override */ 2657 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2658 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2659 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2660 else 2661 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2662 /* update CGCG and CGLS override bits */ 2663 if (def != data) 2664 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2665 2666 /* CGCG Hysteresis: 400us */ 2667 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2668 2669 data = (0x2710 2670 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2671 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2672 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2673 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2674 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2675 if (def != data) 2676 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2677 2678 /* set IDLE_POLL_COUNT(0x33450100)*/ 2679 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2680 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2681 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2682 if (def != data) 2683 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2684 } else { 2685 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2686 /* reset CGCG/CGLS bits */ 2687 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2688 /* disable cgcg and cgls in FSM */ 2689 if (def != data) 2690 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2691 } 2692 2693 } 2694 2695 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2696 bool enable, int xcc_id) 2697 { 2698 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2699 2700 if (enable) { 2701 /* FGCG */ 2702 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2703 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2704 2705 /* CGCG/CGLS should be enabled after MGCG/MGLS 2706 * === MGCG + MGLS === 2707 */ 2708 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2709 xcc_id); 2710 /* === CGCG + CGLS === */ 2711 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2712 xcc_id); 2713 } else { 2714 /* CGCG/CGLS should be disabled before MGCG/MGLS 2715 * === CGCG + CGLS === 2716 */ 2717 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2718 xcc_id); 2719 /* === MGCG + MGLS === */ 2720 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2721 xcc_id); 2722 2723 /* FGCG */ 2724 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2725 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2726 } 2727 2728 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2729 2730 return 0; 2731 } 2732 2733 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2734 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2735 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2736 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2737 .init = gfx_v9_4_3_rlc_init, 2738 .resume = gfx_v9_4_3_rlc_resume, 2739 .stop = gfx_v9_4_3_rlc_stop, 2740 .reset = gfx_v9_4_3_rlc_reset, 2741 .start = gfx_v9_4_3_rlc_start, 2742 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2743 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2744 }; 2745 2746 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2747 enum amd_powergating_state state) 2748 { 2749 return 0; 2750 } 2751 2752 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2753 enum amd_clockgating_state state) 2754 { 2755 struct amdgpu_device *adev = ip_block->adev; 2756 int i, num_xcc; 2757 2758 if (amdgpu_sriov_vf(adev)) 2759 return 0; 2760 2761 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2762 for (i = 0; i < num_xcc; i++) 2763 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2764 adev, state == AMD_CG_STATE_GATE, i); 2765 2766 return 0; 2767 } 2768 2769 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2770 { 2771 struct amdgpu_device *adev = ip_block->adev; 2772 int data; 2773 2774 if (amdgpu_sriov_vf(adev)) 2775 *flags = 0; 2776 2777 /* AMD_CG_SUPPORT_GFX_MGCG */ 2778 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2779 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2780 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2781 2782 /* AMD_CG_SUPPORT_GFX_CGCG */ 2783 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2784 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2785 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2786 2787 /* AMD_CG_SUPPORT_GFX_CGLS */ 2788 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2789 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2790 2791 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2792 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2793 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2794 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2795 2796 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2797 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2798 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2799 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2800 } 2801 2802 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2803 { 2804 struct amdgpu_device *adev = ring->adev; 2805 u32 ref_and_mask, reg_mem_engine; 2806 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2807 2808 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2809 switch (ring->me) { 2810 case 1: 2811 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2812 break; 2813 case 2: 2814 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2815 break; 2816 default: 2817 return; 2818 } 2819 reg_mem_engine = 0; 2820 } else { 2821 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2822 reg_mem_engine = 1; /* pfp */ 2823 } 2824 2825 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2826 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2827 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2828 ref_and_mask, ref_and_mask, 0x20); 2829 } 2830 2831 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2832 struct amdgpu_job *job, 2833 struct amdgpu_ib *ib, 2834 uint32_t flags) 2835 { 2836 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2837 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2838 2839 /* Currently, there is a high possibility to get wave ID mismatch 2840 * between ME and GDS, leading to a hw deadlock, because ME generates 2841 * different wave IDs than the GDS expects. This situation happens 2842 * randomly when at least 5 compute pipes use GDS ordered append. 2843 * The wave IDs generated by ME are also wrong after suspend/resume. 2844 * Those are probably bugs somewhere else in the kernel driver. 2845 * 2846 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2847 * GDS to 0 for this ring (me/pipe). 2848 */ 2849 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2851 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2852 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2853 } 2854 2855 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2856 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2857 amdgpu_ring_write(ring, 2858 #ifdef __BIG_ENDIAN 2859 (2 << 0) | 2860 #endif 2861 lower_32_bits(ib->gpu_addr)); 2862 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2863 amdgpu_ring_write(ring, control); 2864 } 2865 2866 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2867 u64 seq, unsigned flags) 2868 { 2869 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2870 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2871 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2872 2873 /* RELEASE_MEM - flush caches, send int */ 2874 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2875 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2876 EOP_TC_NC_ACTION_EN) : 2877 (EOP_TCL1_ACTION_EN | 2878 EOP_TC_ACTION_EN | 2879 EOP_TC_WB_ACTION_EN | 2880 EOP_TC_MD_ACTION_EN)) | 2881 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2882 EVENT_INDEX(5))); 2883 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2884 2885 /* 2886 * the address should be Qword aligned if 64bit write, Dword 2887 * aligned if only send 32bit data low (discard data high) 2888 */ 2889 if (write64bit) 2890 BUG_ON(addr & 0x7); 2891 else 2892 BUG_ON(addr & 0x3); 2893 amdgpu_ring_write(ring, lower_32_bits(addr)); 2894 amdgpu_ring_write(ring, upper_32_bits(addr)); 2895 amdgpu_ring_write(ring, lower_32_bits(seq)); 2896 amdgpu_ring_write(ring, upper_32_bits(seq)); 2897 amdgpu_ring_write(ring, 0); 2898 } 2899 2900 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2901 { 2902 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2903 uint32_t seq = ring->fence_drv.sync_seq; 2904 uint64_t addr = ring->fence_drv.gpu_addr; 2905 2906 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2907 lower_32_bits(addr), upper_32_bits(addr), 2908 seq, 0xffffffff, 4); 2909 } 2910 2911 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2912 unsigned vmid, uint64_t pd_addr) 2913 { 2914 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2915 } 2916 2917 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2918 { 2919 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2920 } 2921 2922 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2923 { 2924 u64 wptr; 2925 2926 /* XXX check if swapping is necessary on BE */ 2927 if (ring->use_doorbell) 2928 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2929 else 2930 BUG(); 2931 return wptr; 2932 } 2933 2934 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2935 { 2936 struct amdgpu_device *adev = ring->adev; 2937 2938 /* XXX check if swapping is necessary on BE */ 2939 if (ring->use_doorbell) { 2940 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2941 WDOORBELL64(ring->doorbell_index, ring->wptr); 2942 } else { 2943 BUG(); /* only DOORBELL method supported on gfx9 now */ 2944 } 2945 } 2946 2947 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2948 u64 seq, unsigned int flags) 2949 { 2950 struct amdgpu_device *adev = ring->adev; 2951 2952 /* we only allocate 32bit for each seq wb address */ 2953 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2954 2955 /* write fence seq to the "addr" */ 2956 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2957 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2958 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2959 amdgpu_ring_write(ring, lower_32_bits(addr)); 2960 amdgpu_ring_write(ring, upper_32_bits(addr)); 2961 amdgpu_ring_write(ring, lower_32_bits(seq)); 2962 2963 if (flags & AMDGPU_FENCE_FLAG_INT) { 2964 /* set register to trigger INT */ 2965 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2966 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2967 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2968 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2969 amdgpu_ring_write(ring, 0); 2970 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2971 } 2972 } 2973 2974 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2975 uint32_t reg_val_offs) 2976 { 2977 struct amdgpu_device *adev = ring->adev; 2978 2979 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2980 2981 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2982 amdgpu_ring_write(ring, 0 | /* src: register*/ 2983 (5 << 8) | /* dst: memory */ 2984 (1 << 20)); /* write confirm */ 2985 amdgpu_ring_write(ring, reg); 2986 amdgpu_ring_write(ring, 0); 2987 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2988 reg_val_offs * 4)); 2989 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2990 reg_val_offs * 4)); 2991 } 2992 2993 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2994 uint32_t val) 2995 { 2996 uint32_t cmd = 0; 2997 2998 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2999 3000 switch (ring->funcs->type) { 3001 case AMDGPU_RING_TYPE_GFX: 3002 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3003 break; 3004 case AMDGPU_RING_TYPE_KIQ: 3005 cmd = (1 << 16); /* no inc addr */ 3006 break; 3007 default: 3008 cmd = WR_CONFIRM; 3009 break; 3010 } 3011 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3012 amdgpu_ring_write(ring, cmd); 3013 amdgpu_ring_write(ring, reg); 3014 amdgpu_ring_write(ring, 0); 3015 amdgpu_ring_write(ring, val); 3016 } 3017 3018 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3019 uint32_t val, uint32_t mask) 3020 { 3021 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3022 } 3023 3024 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3025 uint32_t reg0, uint32_t reg1, 3026 uint32_t ref, uint32_t mask) 3027 { 3028 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3029 ref, mask); 3030 } 3031 3032 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3033 unsigned vmid) 3034 { 3035 struct amdgpu_device *adev = ring->adev; 3036 uint32_t value = 0; 3037 3038 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3039 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3040 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3041 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3042 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3043 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3044 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3045 } 3046 3047 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3048 struct amdgpu_device *adev, int me, int pipe, 3049 enum amdgpu_interrupt_state state, int xcc_id) 3050 { 3051 u32 mec_int_cntl, mec_int_cntl_reg; 3052 3053 /* 3054 * amdgpu controls only the first MEC. That's why this function only 3055 * handles the setting of interrupts for this specific MEC. All other 3056 * pipes' interrupts are set by amdkfd. 3057 */ 3058 3059 if (me == 1) { 3060 switch (pipe) { 3061 case 0: 3062 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3063 break; 3064 case 1: 3065 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3066 break; 3067 case 2: 3068 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3069 break; 3070 case 3: 3071 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3072 break; 3073 default: 3074 DRM_DEBUG("invalid pipe %d\n", pipe); 3075 return; 3076 } 3077 } else { 3078 DRM_DEBUG("invalid me %d\n", me); 3079 return; 3080 } 3081 3082 switch (state) { 3083 case AMDGPU_IRQ_STATE_DISABLE: 3084 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3085 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3086 TIME_STAMP_INT_ENABLE, 0); 3087 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3088 break; 3089 case AMDGPU_IRQ_STATE_ENABLE: 3090 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3091 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3092 TIME_STAMP_INT_ENABLE, 1); 3093 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3094 break; 3095 default: 3096 break; 3097 } 3098 } 3099 3100 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3101 int xcc_id, int me, int pipe) 3102 { 3103 /* 3104 * amdgpu controls only the first MEC. That's why this function only 3105 * handles the setting of interrupts for this specific MEC. All other 3106 * pipes' interrupts are set by amdkfd. 3107 */ 3108 if (me != 1) 3109 return 0; 3110 3111 switch (pipe) { 3112 case 0: 3113 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3114 case 1: 3115 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3116 case 2: 3117 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3118 case 3: 3119 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3120 default: 3121 return 0; 3122 } 3123 } 3124 3125 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3126 struct amdgpu_irq_src *source, 3127 unsigned type, 3128 enum amdgpu_interrupt_state state) 3129 { 3130 u32 mec_int_cntl_reg, mec_int_cntl; 3131 int i, j, k, num_xcc; 3132 3133 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3134 switch (state) { 3135 case AMDGPU_IRQ_STATE_DISABLE: 3136 case AMDGPU_IRQ_STATE_ENABLE: 3137 for (i = 0; i < num_xcc; i++) { 3138 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3139 PRIV_REG_INT_ENABLE, 3140 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3141 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3142 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3143 /* MECs start at 1 */ 3144 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3145 3146 if (mec_int_cntl_reg) { 3147 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3148 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3149 PRIV_REG_INT_ENABLE, 3150 state == AMDGPU_IRQ_STATE_ENABLE ? 3151 1 : 0); 3152 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3153 } 3154 } 3155 } 3156 } 3157 break; 3158 default: 3159 break; 3160 } 3161 3162 return 0; 3163 } 3164 3165 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3166 struct amdgpu_irq_src *source, 3167 unsigned type, 3168 enum amdgpu_interrupt_state state) 3169 { 3170 u32 mec_int_cntl_reg, mec_int_cntl; 3171 int i, j, k, num_xcc; 3172 3173 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3174 switch (state) { 3175 case AMDGPU_IRQ_STATE_DISABLE: 3176 case AMDGPU_IRQ_STATE_ENABLE: 3177 for (i = 0; i < num_xcc; i++) { 3178 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3179 OPCODE_ERROR_INT_ENABLE, 3180 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3181 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3182 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3183 /* MECs start at 1 */ 3184 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3185 3186 if (mec_int_cntl_reg) { 3187 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3188 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3189 OPCODE_ERROR_INT_ENABLE, 3190 state == AMDGPU_IRQ_STATE_ENABLE ? 3191 1 : 0); 3192 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3193 } 3194 } 3195 } 3196 } 3197 break; 3198 default: 3199 break; 3200 } 3201 3202 return 0; 3203 } 3204 3205 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3206 struct amdgpu_irq_src *source, 3207 unsigned type, 3208 enum amdgpu_interrupt_state state) 3209 { 3210 int i, num_xcc; 3211 3212 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3213 switch (state) { 3214 case AMDGPU_IRQ_STATE_DISABLE: 3215 case AMDGPU_IRQ_STATE_ENABLE: 3216 for (i = 0; i < num_xcc; i++) 3217 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3218 PRIV_INSTR_INT_ENABLE, 3219 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3220 break; 3221 default: 3222 break; 3223 } 3224 3225 return 0; 3226 } 3227 3228 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3229 struct amdgpu_irq_src *src, 3230 unsigned type, 3231 enum amdgpu_interrupt_state state) 3232 { 3233 int i, num_xcc; 3234 3235 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3236 for (i = 0; i < num_xcc; i++) { 3237 switch (type) { 3238 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3239 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3240 adev, 1, 0, state, i); 3241 break; 3242 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3243 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3244 adev, 1, 1, state, i); 3245 break; 3246 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3247 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3248 adev, 1, 2, state, i); 3249 break; 3250 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3251 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3252 adev, 1, 3, state, i); 3253 break; 3254 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3255 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3256 adev, 2, 0, state, i); 3257 break; 3258 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3259 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3260 adev, 2, 1, state, i); 3261 break; 3262 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3263 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3264 adev, 2, 2, state, i); 3265 break; 3266 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3267 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3268 adev, 2, 3, state, i); 3269 break; 3270 default: 3271 break; 3272 } 3273 } 3274 3275 return 0; 3276 } 3277 3278 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3279 struct amdgpu_irq_src *source, 3280 struct amdgpu_iv_entry *entry) 3281 { 3282 int i, xcc_id; 3283 u8 me_id, pipe_id, queue_id; 3284 struct amdgpu_ring *ring; 3285 3286 DRM_DEBUG("IH: CP EOP\n"); 3287 me_id = (entry->ring_id & 0x0c) >> 2; 3288 pipe_id = (entry->ring_id & 0x03) >> 0; 3289 queue_id = (entry->ring_id & 0x70) >> 4; 3290 3291 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3292 3293 if (xcc_id == -EINVAL) 3294 return -EINVAL; 3295 3296 switch (me_id) { 3297 case 0: 3298 case 1: 3299 case 2: 3300 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3301 ring = &adev->gfx.compute_ring 3302 [i + 3303 xcc_id * adev->gfx.num_compute_rings]; 3304 /* Per-queue interrupt is supported for MEC starting from VI. 3305 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3306 */ 3307 3308 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3309 amdgpu_fence_process(ring); 3310 } 3311 break; 3312 } 3313 return 0; 3314 } 3315 3316 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3317 struct amdgpu_iv_entry *entry) 3318 { 3319 u8 me_id, pipe_id, queue_id; 3320 struct amdgpu_ring *ring; 3321 int i, xcc_id; 3322 3323 me_id = (entry->ring_id & 0x0c) >> 2; 3324 pipe_id = (entry->ring_id & 0x03) >> 0; 3325 queue_id = (entry->ring_id & 0x70) >> 4; 3326 3327 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3328 3329 if (xcc_id == -EINVAL) 3330 return; 3331 3332 switch (me_id) { 3333 case 0: 3334 case 1: 3335 case 2: 3336 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3337 ring = &adev->gfx.compute_ring 3338 [i + 3339 xcc_id * adev->gfx.num_compute_rings]; 3340 if (ring->me == me_id && ring->pipe == pipe_id && 3341 ring->queue == queue_id) 3342 drm_sched_fault(&ring->sched); 3343 } 3344 break; 3345 } 3346 } 3347 3348 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3349 struct amdgpu_irq_src *source, 3350 struct amdgpu_iv_entry *entry) 3351 { 3352 DRM_ERROR("Illegal register access in command stream\n"); 3353 gfx_v9_4_3_fault(adev, entry); 3354 return 0; 3355 } 3356 3357 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3358 struct amdgpu_irq_src *source, 3359 struct amdgpu_iv_entry *entry) 3360 { 3361 DRM_ERROR("Illegal opcode in command stream\n"); 3362 gfx_v9_4_3_fault(adev, entry); 3363 return 0; 3364 } 3365 3366 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3367 struct amdgpu_irq_src *source, 3368 struct amdgpu_iv_entry *entry) 3369 { 3370 DRM_ERROR("Illegal instruction in command stream\n"); 3371 gfx_v9_4_3_fault(adev, entry); 3372 return 0; 3373 } 3374 3375 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3376 { 3377 const unsigned int cp_coher_cntl = 3378 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3379 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3380 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3381 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3382 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3383 3384 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3385 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3386 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3387 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3388 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3389 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3390 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3391 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3392 } 3393 3394 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3395 uint32_t pipe, bool enable) 3396 { 3397 struct amdgpu_device *adev = ring->adev; 3398 uint32_t val; 3399 uint32_t wcl_cs_reg; 3400 3401 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3402 val = enable ? 0x1 : 0x7f; 3403 3404 switch (pipe) { 3405 case 0: 3406 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3407 break; 3408 case 1: 3409 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3410 break; 3411 case 2: 3412 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3413 break; 3414 case 3: 3415 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3416 break; 3417 default: 3418 DRM_DEBUG("invalid pipe %d\n", pipe); 3419 return; 3420 } 3421 3422 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3423 3424 } 3425 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3426 { 3427 struct amdgpu_device *adev = ring->adev; 3428 uint32_t val; 3429 int i; 3430 3431 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3432 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3433 * around 25% of gpu resources. 3434 */ 3435 val = enable ? 0x1f : 0x07ffffff; 3436 amdgpu_ring_emit_wreg(ring, 3437 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3438 val); 3439 3440 /* Restrict waves for normal/low priority compute queues as well 3441 * to get best QoS for high priority compute jobs. 3442 * 3443 * amdgpu controls only 1st ME(0-3 CS pipes). 3444 */ 3445 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3446 if (i != ring->pipe) 3447 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3448 3449 } 3450 } 3451 3452 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3453 uint32_t pipe, uint32_t queue, 3454 uint32_t xcc_id) 3455 { 3456 int i, r; 3457 /* make sure dequeue is complete*/ 3458 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3459 mutex_lock(&adev->srbm_mutex); 3460 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3461 for (i = 0; i < adev->usec_timeout; i++) { 3462 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3463 break; 3464 udelay(1); 3465 } 3466 if (i >= adev->usec_timeout) 3467 r = -ETIMEDOUT; 3468 else 3469 r = 0; 3470 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3471 mutex_unlock(&adev->srbm_mutex); 3472 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3473 3474 return r; 3475 3476 } 3477 3478 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3479 { 3480 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3481 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3482 adev->gfx.mec_fw_version >= 0x0000009b) 3483 return true; 3484 else 3485 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3486 3487 return false; 3488 } 3489 3490 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3491 { 3492 struct amdgpu_device *adev = ring->adev; 3493 uint32_t reset_pipe, clean_pipe; 3494 int r; 3495 3496 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3497 return -EINVAL; 3498 3499 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3500 mutex_lock(&adev->srbm_mutex); 3501 3502 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3503 clean_pipe = reset_pipe; 3504 3505 if (ring->me == 1) { 3506 switch (ring->pipe) { 3507 case 0: 3508 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3509 MEC_ME1_PIPE0_RESET, 1); 3510 break; 3511 case 1: 3512 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3513 MEC_ME1_PIPE1_RESET, 1); 3514 break; 3515 case 2: 3516 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3517 MEC_ME1_PIPE2_RESET, 1); 3518 break; 3519 case 3: 3520 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3521 MEC_ME1_PIPE3_RESET, 1); 3522 break; 3523 default: 3524 break; 3525 } 3526 } else { 3527 if (ring->pipe) 3528 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3529 MEC_ME2_PIPE1_RESET, 1); 3530 else 3531 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3532 MEC_ME2_PIPE0_RESET, 1); 3533 } 3534 3535 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3536 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3537 mutex_unlock(&adev->srbm_mutex); 3538 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3539 3540 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3541 return r; 3542 } 3543 3544 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3545 unsigned int vmid) 3546 { 3547 struct amdgpu_device *adev = ring->adev; 3548 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3549 struct amdgpu_ring *kiq_ring = &kiq->ring; 3550 unsigned long flags; 3551 int r; 3552 3553 if (amdgpu_sriov_vf(adev)) 3554 return -EINVAL; 3555 3556 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3557 return -EINVAL; 3558 3559 spin_lock_irqsave(&kiq->ring_lock, flags); 3560 3561 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3562 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3563 return -ENOMEM; 3564 } 3565 3566 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3567 0, 0); 3568 amdgpu_ring_commit(kiq_ring); 3569 3570 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3571 3572 r = amdgpu_ring_test_ring(kiq_ring); 3573 if (r) { 3574 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3575 ring->name); 3576 goto pipe_reset; 3577 } 3578 3579 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3580 if (r) 3581 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3582 3583 pipe_reset: 3584 if(r) { 3585 r = gfx_v9_4_3_reset_hw_pipe(ring); 3586 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3587 r ? "failed" : "successfully"); 3588 if (r) 3589 return r; 3590 } 3591 3592 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3593 if (unlikely(r != 0)){ 3594 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3595 return r; 3596 } 3597 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3598 if (!r) { 3599 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3600 amdgpu_bo_kunmap(ring->mqd_obj); 3601 ring->mqd_ptr = NULL; 3602 } 3603 amdgpu_bo_unreserve(ring->mqd_obj); 3604 if (r) { 3605 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3606 return r; 3607 } 3608 spin_lock_irqsave(&kiq->ring_lock, flags); 3609 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3610 if (r) { 3611 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3612 return -ENOMEM; 3613 } 3614 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3615 amdgpu_ring_commit(kiq_ring); 3616 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3617 3618 r = amdgpu_ring_test_ring(kiq_ring); 3619 if (r) { 3620 dev_err(adev->dev, "fail to remap queue\n"); 3621 return r; 3622 } 3623 return amdgpu_ring_test_ring(ring); 3624 } 3625 3626 enum amdgpu_gfx_cp_ras_mem_id { 3627 AMDGPU_GFX_CP_MEM1 = 1, 3628 AMDGPU_GFX_CP_MEM2, 3629 AMDGPU_GFX_CP_MEM3, 3630 AMDGPU_GFX_CP_MEM4, 3631 AMDGPU_GFX_CP_MEM5, 3632 }; 3633 3634 enum amdgpu_gfx_gcea_ras_mem_id { 3635 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3636 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3637 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3638 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3639 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3640 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3641 AMDGPU_GFX_GCEA_MAM_DMEM0, 3642 AMDGPU_GFX_GCEA_MAM_DMEM1, 3643 AMDGPU_GFX_GCEA_MAM_DMEM2, 3644 AMDGPU_GFX_GCEA_MAM_DMEM3, 3645 AMDGPU_GFX_GCEA_MAM_AMEM0, 3646 AMDGPU_GFX_GCEA_MAM_AMEM1, 3647 AMDGPU_GFX_GCEA_MAM_AMEM2, 3648 AMDGPU_GFX_GCEA_MAM_AMEM3, 3649 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3650 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3651 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3652 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3653 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3654 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3655 }; 3656 3657 enum amdgpu_gfx_gc_cane_ras_mem_id { 3658 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3659 }; 3660 3661 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3662 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3663 }; 3664 3665 enum amdgpu_gfx_gds_ras_mem_id { 3666 AMDGPU_GFX_GDS_MEM0 = 0, 3667 }; 3668 3669 enum amdgpu_gfx_lds_ras_mem_id { 3670 AMDGPU_GFX_LDS_BANK0 = 0, 3671 AMDGPU_GFX_LDS_BANK1, 3672 AMDGPU_GFX_LDS_BANK2, 3673 AMDGPU_GFX_LDS_BANK3, 3674 AMDGPU_GFX_LDS_BANK4, 3675 AMDGPU_GFX_LDS_BANK5, 3676 AMDGPU_GFX_LDS_BANK6, 3677 AMDGPU_GFX_LDS_BANK7, 3678 AMDGPU_GFX_LDS_BANK8, 3679 AMDGPU_GFX_LDS_BANK9, 3680 AMDGPU_GFX_LDS_BANK10, 3681 AMDGPU_GFX_LDS_BANK11, 3682 AMDGPU_GFX_LDS_BANK12, 3683 AMDGPU_GFX_LDS_BANK13, 3684 AMDGPU_GFX_LDS_BANK14, 3685 AMDGPU_GFX_LDS_BANK15, 3686 AMDGPU_GFX_LDS_BANK16, 3687 AMDGPU_GFX_LDS_BANK17, 3688 AMDGPU_GFX_LDS_BANK18, 3689 AMDGPU_GFX_LDS_BANK19, 3690 AMDGPU_GFX_LDS_BANK20, 3691 AMDGPU_GFX_LDS_BANK21, 3692 AMDGPU_GFX_LDS_BANK22, 3693 AMDGPU_GFX_LDS_BANK23, 3694 AMDGPU_GFX_LDS_BANK24, 3695 AMDGPU_GFX_LDS_BANK25, 3696 AMDGPU_GFX_LDS_BANK26, 3697 AMDGPU_GFX_LDS_BANK27, 3698 AMDGPU_GFX_LDS_BANK28, 3699 AMDGPU_GFX_LDS_BANK29, 3700 AMDGPU_GFX_LDS_BANK30, 3701 AMDGPU_GFX_LDS_BANK31, 3702 AMDGPU_GFX_LDS_SP_BUFFER_A, 3703 AMDGPU_GFX_LDS_SP_BUFFER_B, 3704 }; 3705 3706 enum amdgpu_gfx_rlc_ras_mem_id { 3707 AMDGPU_GFX_RLC_GPMF32 = 1, 3708 AMDGPU_GFX_RLC_RLCVF32, 3709 AMDGPU_GFX_RLC_SCRATCH, 3710 AMDGPU_GFX_RLC_SRM_ARAM, 3711 AMDGPU_GFX_RLC_SRM_DRAM, 3712 AMDGPU_GFX_RLC_TCTAG, 3713 AMDGPU_GFX_RLC_SPM_SE, 3714 AMDGPU_GFX_RLC_SPM_GRBMT, 3715 }; 3716 3717 enum amdgpu_gfx_sp_ras_mem_id { 3718 AMDGPU_GFX_SP_SIMDID0 = 0, 3719 }; 3720 3721 enum amdgpu_gfx_spi_ras_mem_id { 3722 AMDGPU_GFX_SPI_MEM0 = 0, 3723 AMDGPU_GFX_SPI_MEM1, 3724 AMDGPU_GFX_SPI_MEM2, 3725 AMDGPU_GFX_SPI_MEM3, 3726 }; 3727 3728 enum amdgpu_gfx_sqc_ras_mem_id { 3729 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3730 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3731 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3732 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3733 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3734 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3735 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3736 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3737 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3738 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3739 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3740 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3741 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3742 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3743 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3744 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3745 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3746 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3747 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3748 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3749 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3750 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3751 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3752 }; 3753 3754 enum amdgpu_gfx_sq_ras_mem_id { 3755 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3756 AMDGPU_GFX_SQ_SGPR_MEM1, 3757 AMDGPU_GFX_SQ_SGPR_MEM2, 3758 AMDGPU_GFX_SQ_SGPR_MEM3, 3759 }; 3760 3761 enum amdgpu_gfx_ta_ras_mem_id { 3762 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3763 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3764 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3765 AMDGPU_GFX_TA_FSX_LFIFO, 3766 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3767 }; 3768 3769 enum amdgpu_gfx_tcc_ras_mem_id { 3770 AMDGPU_GFX_TCC_MEM1 = 1, 3771 }; 3772 3773 enum amdgpu_gfx_tca_ras_mem_id { 3774 AMDGPU_GFX_TCA_MEM1 = 1, 3775 }; 3776 3777 enum amdgpu_gfx_tci_ras_mem_id { 3778 AMDGPU_GFX_TCIW_MEM = 1, 3779 }; 3780 3781 enum amdgpu_gfx_tcp_ras_mem_id { 3782 AMDGPU_GFX_TCP_LFIFO0 = 1, 3783 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3784 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3785 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3786 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3787 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3788 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3789 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3790 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3791 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3792 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3793 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3794 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3795 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3796 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3797 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3798 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3799 AMDGPU_GFX_TCP_VM_FIFO, 3800 AMDGPU_GFX_TCP_DB_TAGRAM0, 3801 AMDGPU_GFX_TCP_DB_TAGRAM1, 3802 AMDGPU_GFX_TCP_DB_TAGRAM2, 3803 AMDGPU_GFX_TCP_DB_TAGRAM3, 3804 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3805 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3806 AMDGPU_GFX_TCP_CMD_FIFO, 3807 }; 3808 3809 enum amdgpu_gfx_td_ras_mem_id { 3810 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3811 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3812 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3813 }; 3814 3815 enum amdgpu_gfx_tcx_ras_mem_id { 3816 AMDGPU_GFX_TCX_FIFOD0 = 0, 3817 AMDGPU_GFX_TCX_FIFOD1, 3818 AMDGPU_GFX_TCX_FIFOD2, 3819 AMDGPU_GFX_TCX_FIFOD3, 3820 AMDGPU_GFX_TCX_FIFOD4, 3821 AMDGPU_GFX_TCX_FIFOD5, 3822 AMDGPU_GFX_TCX_FIFOD6, 3823 AMDGPU_GFX_TCX_FIFOD7, 3824 AMDGPU_GFX_TCX_FIFOB0, 3825 AMDGPU_GFX_TCX_FIFOB1, 3826 AMDGPU_GFX_TCX_FIFOB2, 3827 AMDGPU_GFX_TCX_FIFOB3, 3828 AMDGPU_GFX_TCX_FIFOB4, 3829 AMDGPU_GFX_TCX_FIFOB5, 3830 AMDGPU_GFX_TCX_FIFOB6, 3831 AMDGPU_GFX_TCX_FIFOB7, 3832 AMDGPU_GFX_TCX_FIFOA0, 3833 AMDGPU_GFX_TCX_FIFOA1, 3834 AMDGPU_GFX_TCX_FIFOA2, 3835 AMDGPU_GFX_TCX_FIFOA3, 3836 AMDGPU_GFX_TCX_FIFOA4, 3837 AMDGPU_GFX_TCX_FIFOA5, 3838 AMDGPU_GFX_TCX_FIFOA6, 3839 AMDGPU_GFX_TCX_FIFOA7, 3840 AMDGPU_GFX_TCX_CFIFO0, 3841 AMDGPU_GFX_TCX_CFIFO1, 3842 AMDGPU_GFX_TCX_CFIFO2, 3843 AMDGPU_GFX_TCX_CFIFO3, 3844 AMDGPU_GFX_TCX_CFIFO4, 3845 AMDGPU_GFX_TCX_CFIFO5, 3846 AMDGPU_GFX_TCX_CFIFO6, 3847 AMDGPU_GFX_TCX_CFIFO7, 3848 AMDGPU_GFX_TCX_FIFO_ACKB0, 3849 AMDGPU_GFX_TCX_FIFO_ACKB1, 3850 AMDGPU_GFX_TCX_FIFO_ACKB2, 3851 AMDGPU_GFX_TCX_FIFO_ACKB3, 3852 AMDGPU_GFX_TCX_FIFO_ACKB4, 3853 AMDGPU_GFX_TCX_FIFO_ACKB5, 3854 AMDGPU_GFX_TCX_FIFO_ACKB6, 3855 AMDGPU_GFX_TCX_FIFO_ACKB7, 3856 AMDGPU_GFX_TCX_FIFO_ACKD0, 3857 AMDGPU_GFX_TCX_FIFO_ACKD1, 3858 AMDGPU_GFX_TCX_FIFO_ACKD2, 3859 AMDGPU_GFX_TCX_FIFO_ACKD3, 3860 AMDGPU_GFX_TCX_FIFO_ACKD4, 3861 AMDGPU_GFX_TCX_FIFO_ACKD5, 3862 AMDGPU_GFX_TCX_FIFO_ACKD6, 3863 AMDGPU_GFX_TCX_FIFO_ACKD7, 3864 AMDGPU_GFX_TCX_DST_FIFOA0, 3865 AMDGPU_GFX_TCX_DST_FIFOA1, 3866 AMDGPU_GFX_TCX_DST_FIFOA2, 3867 AMDGPU_GFX_TCX_DST_FIFOA3, 3868 AMDGPU_GFX_TCX_DST_FIFOA4, 3869 AMDGPU_GFX_TCX_DST_FIFOA5, 3870 AMDGPU_GFX_TCX_DST_FIFOA6, 3871 AMDGPU_GFX_TCX_DST_FIFOA7, 3872 AMDGPU_GFX_TCX_DST_FIFOB0, 3873 AMDGPU_GFX_TCX_DST_FIFOB1, 3874 AMDGPU_GFX_TCX_DST_FIFOB2, 3875 AMDGPU_GFX_TCX_DST_FIFOB3, 3876 AMDGPU_GFX_TCX_DST_FIFOB4, 3877 AMDGPU_GFX_TCX_DST_FIFOB5, 3878 AMDGPU_GFX_TCX_DST_FIFOB6, 3879 AMDGPU_GFX_TCX_DST_FIFOB7, 3880 AMDGPU_GFX_TCX_DST_FIFOD0, 3881 AMDGPU_GFX_TCX_DST_FIFOD1, 3882 AMDGPU_GFX_TCX_DST_FIFOD2, 3883 AMDGPU_GFX_TCX_DST_FIFOD3, 3884 AMDGPU_GFX_TCX_DST_FIFOD4, 3885 AMDGPU_GFX_TCX_DST_FIFOD5, 3886 AMDGPU_GFX_TCX_DST_FIFOD6, 3887 AMDGPU_GFX_TCX_DST_FIFOD7, 3888 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3889 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3890 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3891 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3892 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3893 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3894 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3895 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3896 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3897 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3898 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3899 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3900 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3901 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3902 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3903 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3904 }; 3905 3906 enum amdgpu_gfx_atc_l2_ras_mem_id { 3907 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3908 }; 3909 3910 enum amdgpu_gfx_utcl2_ras_mem_id { 3911 AMDGPU_GFX_UTCL2_MEM0 = 0, 3912 }; 3913 3914 enum amdgpu_gfx_vml2_ras_mem_id { 3915 AMDGPU_GFX_VML2_MEM0 = 0, 3916 }; 3917 3918 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3919 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3920 }; 3921 3922 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3923 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3924 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3925 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3926 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3927 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3928 }; 3929 3930 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3931 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3932 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3933 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3934 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3935 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3936 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3937 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3938 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3939 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3940 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3941 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3942 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3943 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3944 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3945 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3946 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3947 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3948 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3949 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3950 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3951 }; 3952 3953 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3954 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3955 }; 3956 3957 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3958 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3959 }; 3960 3961 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3962 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3963 }; 3964 3965 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3966 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3967 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3968 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3969 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3970 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3971 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3972 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3973 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3974 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3975 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3976 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3977 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3978 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3979 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3980 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3981 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3982 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3983 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3984 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3985 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3986 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3987 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3988 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3989 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3990 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3991 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3992 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3993 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3994 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3995 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3996 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3997 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3998 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3999 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4000 }; 4001 4002 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4003 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4004 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4005 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4006 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4007 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4008 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4009 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4010 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4011 }; 4012 4013 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4014 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4015 }; 4016 4017 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4018 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4019 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4020 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4021 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4022 }; 4023 4024 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4025 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4026 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4027 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4028 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4029 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4030 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4031 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4032 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4033 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4034 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4035 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4036 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4037 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4038 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4039 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4040 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4041 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4042 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4043 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4044 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4045 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4046 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4047 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4048 }; 4049 4050 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4051 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4052 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4053 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4054 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4055 }; 4056 4057 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4058 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4059 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4060 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4061 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4062 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4063 }; 4064 4065 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4066 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4067 }; 4068 4069 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4070 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4071 }; 4072 4073 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4074 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4075 }; 4076 4077 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4078 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4079 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4080 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4081 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4082 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4083 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4084 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4085 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4086 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4087 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4088 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4089 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4090 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4091 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4092 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4093 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4094 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4095 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4096 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4097 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4098 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4099 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4100 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4101 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4102 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4103 }; 4104 4105 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4106 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4107 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4108 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4109 }; 4110 4111 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4112 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4113 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4114 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4115 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4116 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4117 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4118 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4119 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4120 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4121 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4122 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4123 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4124 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4125 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4126 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4127 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4128 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4129 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4130 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4131 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4132 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4133 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4134 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4135 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4136 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4137 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4138 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4139 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4140 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4141 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4142 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4143 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4144 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4145 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4146 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4147 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4148 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4149 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4150 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4151 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4152 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4153 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4154 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4155 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4156 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4157 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4158 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4159 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4160 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4161 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4162 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4163 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4164 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4165 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4166 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4167 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4168 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4169 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4170 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4171 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4172 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4173 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4174 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4175 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4176 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4177 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4178 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4183 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4184 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4185 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4186 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4187 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4188 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4189 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4190 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4191 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4192 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4193 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4194 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4195 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4196 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4197 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4198 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4199 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4200 }; 4201 4202 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4203 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4204 }; 4205 4206 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4207 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4208 }; 4209 4210 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4211 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4212 }; 4213 4214 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4215 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4216 }; 4217 4218 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4219 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4220 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4221 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4222 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4223 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4224 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4225 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4226 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4227 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4228 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4229 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4230 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4231 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4232 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4233 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4234 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4235 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4236 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4237 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4240 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4241 }; 4242 4243 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4244 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4245 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4246 AMDGPU_GFX_RLC_MEM, 1}, 4247 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4248 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4249 AMDGPU_GFX_CP_MEM, 1}, 4250 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4251 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4252 AMDGPU_GFX_CP_MEM, 1}, 4253 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4254 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4255 AMDGPU_GFX_CP_MEM, 1}, 4256 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4257 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4258 AMDGPU_GFX_GDS_MEM, 1}, 4259 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4260 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4261 AMDGPU_GFX_GC_CANE_MEM, 1}, 4262 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4263 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4264 AMDGPU_GFX_SPI_MEM, 1}, 4265 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4266 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4267 AMDGPU_GFX_SP_MEM, 4}, 4268 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4269 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4270 AMDGPU_GFX_SP_MEM, 4}, 4271 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4272 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4273 AMDGPU_GFX_SQ_MEM, 4}, 4274 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4275 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4276 AMDGPU_GFX_SQC_MEM, 4}, 4277 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4278 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4279 AMDGPU_GFX_TCX_MEM, 1}, 4280 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4281 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4282 AMDGPU_GFX_TCC_MEM, 1}, 4283 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4284 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4285 AMDGPU_GFX_TA_MEM, 4}, 4286 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4287 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4288 AMDGPU_GFX_TCI_MEM, 1}, 4289 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4290 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4291 AMDGPU_GFX_TCP_MEM, 4}, 4292 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4293 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4294 AMDGPU_GFX_TD_MEM, 4}, 4295 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4296 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4297 AMDGPU_GFX_GCEA_MEM, 1}, 4298 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4299 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4300 AMDGPU_GFX_LDS_MEM, 4}, 4301 }; 4302 4303 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4304 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4305 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4306 AMDGPU_GFX_RLC_MEM, 1}, 4307 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4308 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4309 AMDGPU_GFX_CP_MEM, 1}, 4310 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4311 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4312 AMDGPU_GFX_CP_MEM, 1}, 4313 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4314 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4315 AMDGPU_GFX_CP_MEM, 1}, 4316 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4317 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4318 AMDGPU_GFX_GDS_MEM, 1}, 4319 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4320 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4321 AMDGPU_GFX_GC_CANE_MEM, 1}, 4322 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4323 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4324 AMDGPU_GFX_SPI_MEM, 1}, 4325 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4326 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4327 AMDGPU_GFX_SP_MEM, 4}, 4328 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4329 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4330 AMDGPU_GFX_SP_MEM, 4}, 4331 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4332 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4333 AMDGPU_GFX_SQ_MEM, 4}, 4334 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4335 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4336 AMDGPU_GFX_SQC_MEM, 4}, 4337 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4338 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4339 AMDGPU_GFX_TCX_MEM, 1}, 4340 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4341 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4342 AMDGPU_GFX_TCC_MEM, 1}, 4343 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4344 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4345 AMDGPU_GFX_TA_MEM, 4}, 4346 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4347 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4348 AMDGPU_GFX_TCI_MEM, 1}, 4349 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4350 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4351 AMDGPU_GFX_TCP_MEM, 4}, 4352 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4353 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4354 AMDGPU_GFX_TD_MEM, 4}, 4355 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4356 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4357 AMDGPU_GFX_TCA_MEM, 1}, 4358 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4359 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4360 AMDGPU_GFX_GCEA_MEM, 1}, 4361 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4362 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4363 AMDGPU_GFX_LDS_MEM, 4}, 4364 }; 4365 4366 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4367 void *ras_error_status, int xcc_id) 4368 { 4369 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4370 unsigned long ce_count = 0, ue_count = 0; 4371 uint32_t i, j, k; 4372 4373 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4374 struct amdgpu_smuio_mcm_config_info mcm_info = { 4375 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4376 .die_id = xcc_id & 0x01 ? 1 : 0, 4377 }; 4378 4379 mutex_lock(&adev->grbm_idx_mutex); 4380 4381 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4382 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4383 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4384 /* no need to select if instance number is 1 */ 4385 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4386 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4387 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4388 4389 amdgpu_ras_inst_query_ras_error_count(adev, 4390 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4391 1, 4392 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4393 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4394 GET_INST(GC, xcc_id), 4395 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4396 &ce_count); 4397 4398 amdgpu_ras_inst_query_ras_error_count(adev, 4399 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4400 1, 4401 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4402 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4403 GET_INST(GC, xcc_id), 4404 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4405 &ue_count); 4406 } 4407 } 4408 } 4409 4410 /* handle extra register entries of UE */ 4411 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4412 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4413 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4414 /* no need to select if instance number is 1 */ 4415 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4416 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4417 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4418 4419 amdgpu_ras_inst_query_ras_error_count(adev, 4420 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4421 1, 4422 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4423 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4424 GET_INST(GC, xcc_id), 4425 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4426 &ue_count); 4427 } 4428 } 4429 } 4430 4431 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4432 xcc_id); 4433 mutex_unlock(&adev->grbm_idx_mutex); 4434 4435 /* the caller should make sure initialize value of 4436 * err_data->ue_count and err_data->ce_count 4437 */ 4438 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4439 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4440 } 4441 4442 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4443 void *ras_error_status, int xcc_id) 4444 { 4445 uint32_t i, j, k; 4446 4447 mutex_lock(&adev->grbm_idx_mutex); 4448 4449 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4450 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4451 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4452 /* no need to select if instance number is 1 */ 4453 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4454 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4455 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4456 4457 amdgpu_ras_inst_reset_ras_error_count(adev, 4458 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4459 1, 4460 GET_INST(GC, xcc_id)); 4461 4462 amdgpu_ras_inst_reset_ras_error_count(adev, 4463 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4464 1, 4465 GET_INST(GC, xcc_id)); 4466 } 4467 } 4468 } 4469 4470 /* handle extra register entries of UE */ 4471 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4472 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4473 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4474 /* no need to select if instance number is 1 */ 4475 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4476 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4477 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4478 4479 amdgpu_ras_inst_reset_ras_error_count(adev, 4480 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4481 1, 4482 GET_INST(GC, xcc_id)); 4483 } 4484 } 4485 } 4486 4487 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4488 xcc_id); 4489 mutex_unlock(&adev->grbm_idx_mutex); 4490 } 4491 4492 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4493 void *ras_error_status, int xcc_id) 4494 { 4495 uint32_t i; 4496 uint32_t data; 4497 4498 if (amdgpu_sriov_vf(adev)) 4499 return; 4500 4501 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4502 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4503 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4504 4505 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4506 (amdgpu_watchdog_timer.period < 1 || 4507 amdgpu_watchdog_timer.period > 0x23)) { 4508 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4509 amdgpu_watchdog_timer.period = 0x23; 4510 } 4511 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4512 amdgpu_watchdog_timer.period); 4513 4514 mutex_lock(&adev->grbm_idx_mutex); 4515 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4516 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4517 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4518 } 4519 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4520 xcc_id); 4521 mutex_unlock(&adev->grbm_idx_mutex); 4522 } 4523 4524 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4525 void *ras_error_status) 4526 { 4527 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4528 gfx_v9_4_3_inst_query_ras_err_count); 4529 } 4530 4531 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4532 { 4533 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4534 } 4535 4536 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4537 { 4538 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4539 } 4540 4541 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4542 { 4543 /* Header itself is a NOP packet */ 4544 if (num_nop == 1) { 4545 amdgpu_ring_write(ring, ring->funcs->nop); 4546 return; 4547 } 4548 4549 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4550 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4551 4552 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4553 amdgpu_ring_insert_nop(ring, num_nop - 1); 4554 } 4555 4556 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4557 { 4558 struct amdgpu_device *adev = ip_block->adev; 4559 uint32_t i, j, k; 4560 uint32_t xcc_id, xcc_offset, inst_offset; 4561 uint32_t num_xcc, reg, num_inst; 4562 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4563 4564 if (!adev->gfx.ip_dump_core) 4565 return; 4566 4567 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4568 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4569 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4570 xcc_offset = xcc_id * reg_count; 4571 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4572 for (i = 0; i < reg_count; i++) 4573 drm_printf(p, "%-50s \t 0x%08x\n", 4574 gc_reg_list_9_4_3[i].reg_name, 4575 adev->gfx.ip_dump_core[xcc_offset + i]); 4576 } 4577 4578 /* print compute queue registers for all instances */ 4579 if (!adev->gfx.ip_dump_compute_queues) 4580 return; 4581 4582 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4583 adev->gfx.mec.num_queue_per_pipe; 4584 4585 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4586 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4587 num_xcc, 4588 adev->gfx.mec.num_mec, 4589 adev->gfx.mec.num_pipe_per_mec, 4590 adev->gfx.mec.num_queue_per_pipe); 4591 4592 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4593 xcc_offset = xcc_id * reg_count * num_inst; 4594 inst_offset = 0; 4595 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4596 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4597 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4598 drm_printf(p, 4599 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4600 xcc_id, i, j, k); 4601 for (reg = 0; reg < reg_count; reg++) { 4602 drm_printf(p, 4603 "%-50s \t 0x%08x\n", 4604 gc_cp_reg_list_9_4_3[reg].reg_name, 4605 adev->gfx.ip_dump_compute_queues 4606 [xcc_offset + inst_offset + 4607 reg]); 4608 } 4609 inst_offset += reg_count; 4610 } 4611 } 4612 } 4613 } 4614 } 4615 4616 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4617 { 4618 struct amdgpu_device *adev = ip_block->adev; 4619 uint32_t i, j, k; 4620 uint32_t num_xcc, reg, num_inst; 4621 uint32_t xcc_id, xcc_offset, inst_offset; 4622 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4623 4624 if (!adev->gfx.ip_dump_core) 4625 return; 4626 4627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4628 4629 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4630 xcc_offset = xcc_id * reg_count; 4631 for (i = 0; i < reg_count; i++) 4632 adev->gfx.ip_dump_core[xcc_offset + i] = 4633 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4634 GET_INST(GC, xcc_id))); 4635 } 4636 4637 /* dump compute queue registers for all instances */ 4638 if (!adev->gfx.ip_dump_compute_queues) 4639 return; 4640 4641 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4642 adev->gfx.mec.num_queue_per_pipe; 4643 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4644 mutex_lock(&adev->srbm_mutex); 4645 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4646 xcc_offset = xcc_id * reg_count * num_inst; 4647 inst_offset = 0; 4648 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4649 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4650 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4651 /* ME0 is for GFX so start from 1 for CP */ 4652 soc15_grbm_select(adev, 1 + i, j, k, 0, 4653 GET_INST(GC, xcc_id)); 4654 4655 for (reg = 0; reg < reg_count; reg++) { 4656 adev->gfx.ip_dump_compute_queues 4657 [xcc_offset + 4658 inst_offset + reg] = 4659 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4660 gc_cp_reg_list_9_4_3[reg], 4661 GET_INST(GC, xcc_id))); 4662 } 4663 inst_offset += reg_count; 4664 } 4665 } 4666 } 4667 } 4668 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4669 mutex_unlock(&adev->srbm_mutex); 4670 } 4671 4672 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4673 { 4674 /* Emit the cleaner shader */ 4675 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4676 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4677 } 4678 4679 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4680 .name = "gfx_v9_4_3", 4681 .early_init = gfx_v9_4_3_early_init, 4682 .late_init = gfx_v9_4_3_late_init, 4683 .sw_init = gfx_v9_4_3_sw_init, 4684 .sw_fini = gfx_v9_4_3_sw_fini, 4685 .hw_init = gfx_v9_4_3_hw_init, 4686 .hw_fini = gfx_v9_4_3_hw_fini, 4687 .suspend = gfx_v9_4_3_suspend, 4688 .resume = gfx_v9_4_3_resume, 4689 .is_idle = gfx_v9_4_3_is_idle, 4690 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4691 .soft_reset = gfx_v9_4_3_soft_reset, 4692 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4693 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4694 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4695 .dump_ip_state = gfx_v9_4_3_ip_dump, 4696 .print_ip_state = gfx_v9_4_3_ip_print, 4697 }; 4698 4699 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4700 .type = AMDGPU_RING_TYPE_COMPUTE, 4701 .align_mask = 0xff, 4702 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4703 .support_64bit_ptrs = true, 4704 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4705 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4706 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4707 .emit_frame_size = 4708 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4709 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4710 5 + /* hdp invalidate */ 4711 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4712 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4713 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4714 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4715 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4716 7 + /* gfx_v9_4_3_emit_mem_sync */ 4717 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4718 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4719 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4720 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4721 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4722 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4723 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4724 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4725 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4726 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4727 .test_ring = gfx_v9_4_3_ring_test_ring, 4728 .test_ib = gfx_v9_4_3_ring_test_ib, 4729 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4730 .pad_ib = amdgpu_ring_generic_pad_ib, 4731 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4732 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4733 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4734 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4735 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4736 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4737 .reset = gfx_v9_4_3_reset_kcq, 4738 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4739 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4740 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4741 }; 4742 4743 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4744 .type = AMDGPU_RING_TYPE_KIQ, 4745 .align_mask = 0xff, 4746 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4747 .support_64bit_ptrs = true, 4748 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4749 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4750 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4751 .emit_frame_size = 4752 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4753 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4754 5 + /* hdp invalidate */ 4755 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4756 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4757 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4758 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4759 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4760 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4761 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4762 .test_ring = gfx_v9_4_3_ring_test_ring, 4763 .insert_nop = amdgpu_ring_insert_nop, 4764 .pad_ib = amdgpu_ring_generic_pad_ib, 4765 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4766 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4767 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4768 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4769 }; 4770 4771 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4772 { 4773 int i, j, num_xcc; 4774 4775 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4776 for (i = 0; i < num_xcc; i++) { 4777 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4778 4779 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4780 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4781 = &gfx_v9_4_3_ring_funcs_compute; 4782 } 4783 } 4784 4785 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4786 .set = gfx_v9_4_3_set_eop_interrupt_state, 4787 .process = gfx_v9_4_3_eop_irq, 4788 }; 4789 4790 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4791 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4792 .process = gfx_v9_4_3_priv_reg_irq, 4793 }; 4794 4795 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4796 .set = gfx_v9_4_3_set_bad_op_fault_state, 4797 .process = gfx_v9_4_3_bad_op_irq, 4798 }; 4799 4800 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4801 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4802 .process = gfx_v9_4_3_priv_inst_irq, 4803 }; 4804 4805 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4806 { 4807 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4808 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4809 4810 adev->gfx.priv_reg_irq.num_types = 1; 4811 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4812 4813 adev->gfx.bad_op_irq.num_types = 1; 4814 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4815 4816 adev->gfx.priv_inst_irq.num_types = 1; 4817 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4818 } 4819 4820 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4821 { 4822 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4823 } 4824 4825 4826 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4827 { 4828 /* 9.4.3 variants removed all the GDS internal memory, 4829 * only support GWS opcode in kernel, like barrier 4830 * semaphore.etc */ 4831 4832 /* init asic gds info */ 4833 adev->gds.gds_size = 0; 4834 adev->gds.gds_compute_max_wave_id = 0; 4835 adev->gds.gws_size = 64; 4836 adev->gds.oa_size = 16; 4837 } 4838 4839 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4840 u32 bitmap, int xcc_id) 4841 { 4842 u32 data; 4843 4844 if (!bitmap) 4845 return; 4846 4847 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4848 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4849 4850 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4851 } 4852 4853 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4854 { 4855 u32 data, mask; 4856 4857 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4858 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4859 4860 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4861 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4862 4863 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4864 4865 return (~data) & mask; 4866 } 4867 4868 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4869 struct amdgpu_cu_info *cu_info) 4870 { 4871 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4872 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4873 unsigned disable_masks[4 * 4]; 4874 bool is_symmetric_cus; 4875 4876 if (!adev || !cu_info) 4877 return -EINVAL; 4878 4879 /* 4880 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4881 */ 4882 if (adev->gfx.config.max_shader_engines * 4883 adev->gfx.config.max_sh_per_se > 16) 4884 return -EINVAL; 4885 4886 amdgpu_gfx_parse_disable_cu(disable_masks, 4887 adev->gfx.config.max_shader_engines, 4888 adev->gfx.config.max_sh_per_se); 4889 4890 mutex_lock(&adev->grbm_idx_mutex); 4891 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4892 is_symmetric_cus = true; 4893 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4894 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4895 mask = 1; 4896 ao_bitmap = 0; 4897 counter = 0; 4898 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4899 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4900 adev, 4901 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4902 xcc_id); 4903 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4904 4905 cu_info->bitmap[xcc_id][i][j] = bitmap; 4906 4907 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4908 if (bitmap & mask) { 4909 if (counter < adev->gfx.config.max_cu_per_sh) 4910 ao_bitmap |= mask; 4911 counter++; 4912 } 4913 mask <<= 1; 4914 } 4915 active_cu_number += counter; 4916 if (i < 2 && j < 2) 4917 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4918 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4919 } 4920 if (i && is_symmetric_cus && prev_counter != counter) 4921 is_symmetric_cus = false; 4922 prev_counter = counter; 4923 } 4924 if (is_symmetric_cus) { 4925 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4926 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4927 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4928 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4929 } 4930 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4931 xcc_id); 4932 } 4933 mutex_unlock(&adev->grbm_idx_mutex); 4934 4935 cu_info->number = active_cu_number; 4936 cu_info->ao_cu_mask = ao_cu_mask; 4937 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4938 4939 return 0; 4940 } 4941 4942 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4943 .type = AMD_IP_BLOCK_TYPE_GFX, 4944 .major = 9, 4945 .minor = 4, 4946 .rev = 3, 4947 .funcs = &gfx_v9_4_3_ip_funcs, 4948 }; 4949 4950 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4951 { 4952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4953 uint32_t tmp_mask; 4954 int i, r; 4955 4956 /* TODO : Initialize golden regs */ 4957 /* gfx_v9_4_3_init_golden_registers(adev); */ 4958 4959 tmp_mask = inst_mask; 4960 for_each_inst(i, tmp_mask) 4961 gfx_v9_4_3_xcc_constants_init(adev, i); 4962 4963 if (!amdgpu_sriov_vf(adev)) { 4964 tmp_mask = inst_mask; 4965 for_each_inst(i, tmp_mask) { 4966 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4967 if (r) 4968 return r; 4969 } 4970 } 4971 4972 tmp_mask = inst_mask; 4973 for_each_inst(i, tmp_mask) { 4974 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4975 if (r) 4976 return r; 4977 } 4978 4979 return 0; 4980 } 4981 4982 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4983 { 4984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4985 int i; 4986 4987 for_each_inst(i, inst_mask) 4988 gfx_v9_4_3_xcc_fini(adev, i); 4989 4990 return 0; 4991 } 4992 4993 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4994 .suspend = &gfx_v9_4_3_xcp_suspend, 4995 .resume = &gfx_v9_4_3_xcp_resume 4996 }; 4997 4998 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4999 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5000 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5001 }; 5002 5003 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5004 { 5005 int r; 5006 5007 r = amdgpu_ras_block_late_init(adev, ras_block); 5008 if (r) 5009 return r; 5010 5011 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5012 &gfx_v9_4_3_aca_info, 5013 NULL); 5014 if (r) 5015 goto late_fini; 5016 5017 return 0; 5018 5019 late_fini: 5020 amdgpu_ras_block_late_fini(adev, ras_block); 5021 5022 return r; 5023 } 5024 5025 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5026 .ras_block = { 5027 .hw_ops = &gfx_v9_4_3_ras_ops, 5028 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5029 }, 5030 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5031 }; 5032