1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 31 #include "vega10/soc15ip.h" 32 #include "vega10/GC/gc_9_0_offset.h" 33 #include "vega10/GC/gc_9_0_sh_mask.h" 34 #include "vega10/vega10_enum.h" 35 #include "vega10/HDP/hdp_4_0_offset.h" 36 37 #include "soc15_common.h" 38 #include "clearstate_gfx9.h" 39 #include "v9_structs.h" 40 41 #define GFX9_NUM_GFX_RINGS 1 42 #define GFX9_MEC_HPD_SIZE 2048 43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 45 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34 46 47 #define mmPWR_MISC_CNTL_STATUS 0x0183 48 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 49 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 50 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 51 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 52 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 53 54 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 55 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 57 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 59 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 60 61 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 64 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 65 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 66 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 67 68 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 69 { 70 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), 71 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), 73 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) }, 74 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), 75 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), 76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), 77 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) }, 78 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), 79 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), 80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), 81 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) }, 82 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), 83 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), 84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), 85 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) }, 86 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), 87 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), 88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), 89 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) }, 90 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), 91 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), 92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), 93 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) }, 94 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), 95 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), 96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), 97 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) }, 98 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), 99 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), 100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), 101 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) }, 102 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), 103 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), 104 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), 105 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) }, 106 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), 107 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), 108 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), 109 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) }, 110 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), 111 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), 112 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), 113 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) }, 114 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), 115 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), 116 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), 117 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) }, 118 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), 119 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), 120 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), 121 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, 122 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), 123 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), 124 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), 125 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) }, 126 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), 127 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), 128 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), 129 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) }, 130 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), 131 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), 132 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), 133 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) } 134 }; 135 136 static const u32 golden_settings_gc_9_0[] = 137 { 138 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, 139 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, 140 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, 141 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, 142 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 143 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, 144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 146 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, 148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, 149 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, 150 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, 151 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, 152 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000, 153 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107, 154 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000, 155 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, 157 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, 158 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, 159 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff, 160 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 161 }; 162 163 static const u32 golden_settings_gc_9_0_vg10[] = 164 { 165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, 166 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, 168 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, 169 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, 170 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 171 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800 172 }; 173 174 static const u32 golden_settings_gc_9_1[] = 175 { 176 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104, 177 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, 178 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, 179 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, 180 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, 181 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 182 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, 183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 185 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, 187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, 188 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, 189 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, 190 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, 191 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000, 193 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120, 194 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, 195 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff, 196 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 197 }; 198 199 static const u32 golden_settings_gc_9_1_rv1[] = 200 { 201 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042, 203 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042, 204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000, 205 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000, 206 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 208 }; 209 210 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 211 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 212 213 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 214 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 215 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 216 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 217 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 218 struct amdgpu_cu_info *cu_info); 219 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 220 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 221 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 222 223 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 224 { 225 switch (adev->asic_type) { 226 case CHIP_VEGA10: 227 amdgpu_program_register_sequence(adev, 228 golden_settings_gc_9_0, 229 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 230 amdgpu_program_register_sequence(adev, 231 golden_settings_gc_9_0_vg10, 232 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 233 break; 234 case CHIP_RAVEN: 235 amdgpu_program_register_sequence(adev, 236 golden_settings_gc_9_1, 237 (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); 238 amdgpu_program_register_sequence(adev, 239 golden_settings_gc_9_1_rv1, 240 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 241 break; 242 default: 243 break; 244 } 245 } 246 247 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 248 { 249 adev->gfx.scratch.num_reg = 8; 250 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 251 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 252 } 253 254 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 255 bool wc, uint32_t reg, uint32_t val) 256 { 257 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 258 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 259 WRITE_DATA_DST_SEL(0) | 260 (wc ? WR_CONFIRM : 0)); 261 amdgpu_ring_write(ring, reg); 262 amdgpu_ring_write(ring, 0); 263 amdgpu_ring_write(ring, val); 264 } 265 266 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 267 int mem_space, int opt, uint32_t addr0, 268 uint32_t addr1, uint32_t ref, uint32_t mask, 269 uint32_t inv) 270 { 271 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 272 amdgpu_ring_write(ring, 273 /* memory (1) or register (0) */ 274 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 275 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 276 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 277 WAIT_REG_MEM_ENGINE(eng_sel))); 278 279 if (mem_space) 280 BUG_ON(addr0 & 0x3); /* Dword align */ 281 amdgpu_ring_write(ring, addr0); 282 amdgpu_ring_write(ring, addr1); 283 amdgpu_ring_write(ring, ref); 284 amdgpu_ring_write(ring, mask); 285 amdgpu_ring_write(ring, inv); /* poll interval */ 286 } 287 288 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 289 { 290 struct amdgpu_device *adev = ring->adev; 291 uint32_t scratch; 292 uint32_t tmp = 0; 293 unsigned i; 294 int r; 295 296 r = amdgpu_gfx_scratch_get(adev, &scratch); 297 if (r) { 298 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 299 return r; 300 } 301 WREG32(scratch, 0xCAFEDEAD); 302 r = amdgpu_ring_alloc(ring, 3); 303 if (r) { 304 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 305 ring->idx, r); 306 amdgpu_gfx_scratch_free(adev, scratch); 307 return r; 308 } 309 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 310 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 311 amdgpu_ring_write(ring, 0xDEADBEEF); 312 amdgpu_ring_commit(ring); 313 314 for (i = 0; i < adev->usec_timeout; i++) { 315 tmp = RREG32(scratch); 316 if (tmp == 0xDEADBEEF) 317 break; 318 DRM_UDELAY(1); 319 } 320 if (i < adev->usec_timeout) { 321 DRM_INFO("ring test on %d succeeded in %d usecs\n", 322 ring->idx, i); 323 } else { 324 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 325 ring->idx, scratch, tmp); 326 r = -EINVAL; 327 } 328 amdgpu_gfx_scratch_free(adev, scratch); 329 return r; 330 } 331 332 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 333 { 334 struct amdgpu_device *adev = ring->adev; 335 struct amdgpu_ib ib; 336 struct dma_fence *f = NULL; 337 uint32_t scratch; 338 uint32_t tmp = 0; 339 long r; 340 341 r = amdgpu_gfx_scratch_get(adev, &scratch); 342 if (r) { 343 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 344 return r; 345 } 346 WREG32(scratch, 0xCAFEDEAD); 347 memset(&ib, 0, sizeof(ib)); 348 r = amdgpu_ib_get(adev, NULL, 256, &ib); 349 if (r) { 350 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 351 goto err1; 352 } 353 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 354 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 355 ib.ptr[2] = 0xDEADBEEF; 356 ib.length_dw = 3; 357 358 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 359 if (r) 360 goto err2; 361 362 r = dma_fence_wait_timeout(f, false, timeout); 363 if (r == 0) { 364 DRM_ERROR("amdgpu: IB test timed out.\n"); 365 r = -ETIMEDOUT; 366 goto err2; 367 } else if (r < 0) { 368 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 369 goto err2; 370 } 371 tmp = RREG32(scratch); 372 if (tmp == 0xDEADBEEF) { 373 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 374 r = 0; 375 } else { 376 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 377 scratch, tmp); 378 r = -EINVAL; 379 } 380 err2: 381 amdgpu_ib_free(adev, &ib, NULL); 382 dma_fence_put(f); 383 err1: 384 amdgpu_gfx_scratch_free(adev, scratch); 385 return r; 386 } 387 388 389 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 390 { 391 release_firmware(adev->gfx.pfp_fw); 392 adev->gfx.pfp_fw = NULL; 393 release_firmware(adev->gfx.me_fw); 394 adev->gfx.me_fw = NULL; 395 release_firmware(adev->gfx.ce_fw); 396 adev->gfx.ce_fw = NULL; 397 release_firmware(adev->gfx.rlc_fw); 398 adev->gfx.rlc_fw = NULL; 399 release_firmware(adev->gfx.mec_fw); 400 adev->gfx.mec_fw = NULL; 401 release_firmware(adev->gfx.mec2_fw); 402 adev->gfx.mec2_fw = NULL; 403 404 kfree(adev->gfx.rlc.register_list_format); 405 } 406 407 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 408 { 409 const char *chip_name; 410 char fw_name[30]; 411 int err; 412 struct amdgpu_firmware_info *info = NULL; 413 const struct common_firmware_header *header = NULL; 414 const struct gfx_firmware_header_v1_0 *cp_hdr; 415 const struct rlc_firmware_header_v2_0 *rlc_hdr; 416 unsigned int *tmp = NULL; 417 unsigned int i = 0; 418 419 DRM_DEBUG("\n"); 420 421 switch (adev->asic_type) { 422 case CHIP_VEGA10: 423 chip_name = "vega10"; 424 break; 425 case CHIP_RAVEN: 426 chip_name = "raven"; 427 break; 428 default: 429 BUG(); 430 } 431 432 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 433 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 434 if (err) 435 goto out; 436 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 437 if (err) 438 goto out; 439 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 440 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 441 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 442 443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 444 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 445 if (err) 446 goto out; 447 err = amdgpu_ucode_validate(adev->gfx.me_fw); 448 if (err) 449 goto out; 450 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 451 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 452 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 453 454 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 455 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 456 if (err) 457 goto out; 458 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 459 if (err) 460 goto out; 461 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 462 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 463 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 464 465 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 466 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 467 if (err) 468 goto out; 469 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 470 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 471 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 472 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 473 adev->gfx.rlc.save_and_restore_offset = 474 le32_to_cpu(rlc_hdr->save_and_restore_offset); 475 adev->gfx.rlc.clear_state_descriptor_offset = 476 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 477 adev->gfx.rlc.avail_scratch_ram_locations = 478 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 479 adev->gfx.rlc.reg_restore_list_size = 480 le32_to_cpu(rlc_hdr->reg_restore_list_size); 481 adev->gfx.rlc.reg_list_format_start = 482 le32_to_cpu(rlc_hdr->reg_list_format_start); 483 adev->gfx.rlc.reg_list_format_separate_start = 484 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 485 adev->gfx.rlc.starting_offsets_start = 486 le32_to_cpu(rlc_hdr->starting_offsets_start); 487 adev->gfx.rlc.reg_list_format_size_bytes = 488 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 489 adev->gfx.rlc.reg_list_size_bytes = 490 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 491 adev->gfx.rlc.register_list_format = 492 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 493 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 494 if (!adev->gfx.rlc.register_list_format) { 495 err = -ENOMEM; 496 goto out; 497 } 498 499 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 500 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 501 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 502 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 503 504 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 505 506 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 507 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 508 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 509 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 510 511 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 512 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 513 if (err) 514 goto out; 515 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 516 if (err) 517 goto out; 518 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 519 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 520 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 521 522 523 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 524 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 525 if (!err) { 526 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 527 if (err) 528 goto out; 529 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 530 adev->gfx.mec2_fw->data; 531 adev->gfx.mec2_fw_version = 532 le32_to_cpu(cp_hdr->header.ucode_version); 533 adev->gfx.mec2_feature_version = 534 le32_to_cpu(cp_hdr->ucode_feature_version); 535 } else { 536 err = 0; 537 adev->gfx.mec2_fw = NULL; 538 } 539 540 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 541 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 542 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 543 info->fw = adev->gfx.pfp_fw; 544 header = (const struct common_firmware_header *)info->fw->data; 545 adev->firmware.fw_size += 546 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 547 548 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 549 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 550 info->fw = adev->gfx.me_fw; 551 header = (const struct common_firmware_header *)info->fw->data; 552 adev->firmware.fw_size += 553 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 554 555 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 556 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 557 info->fw = adev->gfx.ce_fw; 558 header = (const struct common_firmware_header *)info->fw->data; 559 adev->firmware.fw_size += 560 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 561 562 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 563 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 564 info->fw = adev->gfx.rlc_fw; 565 header = (const struct common_firmware_header *)info->fw->data; 566 adev->firmware.fw_size += 567 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 568 569 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 570 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 571 info->fw = adev->gfx.mec_fw; 572 header = (const struct common_firmware_header *)info->fw->data; 573 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 574 adev->firmware.fw_size += 575 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 576 577 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 578 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 579 info->fw = adev->gfx.mec_fw; 580 adev->firmware.fw_size += 581 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 582 583 if (adev->gfx.mec2_fw) { 584 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 585 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 586 info->fw = adev->gfx.mec2_fw; 587 header = (const struct common_firmware_header *)info->fw->data; 588 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 589 adev->firmware.fw_size += 590 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 591 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 592 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 593 info->fw = adev->gfx.mec2_fw; 594 adev->firmware.fw_size += 595 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 596 } 597 598 } 599 600 out: 601 if (err) { 602 dev_err(adev->dev, 603 "gfx9: Failed to load firmware \"%s\"\n", 604 fw_name); 605 release_firmware(adev->gfx.pfp_fw); 606 adev->gfx.pfp_fw = NULL; 607 release_firmware(adev->gfx.me_fw); 608 adev->gfx.me_fw = NULL; 609 release_firmware(adev->gfx.ce_fw); 610 adev->gfx.ce_fw = NULL; 611 release_firmware(adev->gfx.rlc_fw); 612 adev->gfx.rlc_fw = NULL; 613 release_firmware(adev->gfx.mec_fw); 614 adev->gfx.mec_fw = NULL; 615 release_firmware(adev->gfx.mec2_fw); 616 adev->gfx.mec2_fw = NULL; 617 } 618 return err; 619 } 620 621 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 622 { 623 u32 count = 0; 624 const struct cs_section_def *sect = NULL; 625 const struct cs_extent_def *ext = NULL; 626 627 /* begin clear state */ 628 count += 2; 629 /* context control state */ 630 count += 3; 631 632 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 633 for (ext = sect->section; ext->extent != NULL; ++ext) { 634 if (sect->id == SECT_CONTEXT) 635 count += 2 + ext->reg_count; 636 else 637 return 0; 638 } 639 } 640 641 /* end clear state */ 642 count += 2; 643 /* clear state */ 644 count += 2; 645 646 return count; 647 } 648 649 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 650 volatile u32 *buffer) 651 { 652 u32 count = 0, i; 653 const struct cs_section_def *sect = NULL; 654 const struct cs_extent_def *ext = NULL; 655 656 if (adev->gfx.rlc.cs_data == NULL) 657 return; 658 if (buffer == NULL) 659 return; 660 661 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 662 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 663 664 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 665 buffer[count++] = cpu_to_le32(0x80000000); 666 buffer[count++] = cpu_to_le32(0x80000000); 667 668 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 669 for (ext = sect->section; ext->extent != NULL; ++ext) { 670 if (sect->id == SECT_CONTEXT) { 671 buffer[count++] = 672 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 673 buffer[count++] = cpu_to_le32(ext->reg_index - 674 PACKET3_SET_CONTEXT_REG_START); 675 for (i = 0; i < ext->reg_count; i++) 676 buffer[count++] = cpu_to_le32(ext->extent[i]); 677 } else { 678 return; 679 } 680 } 681 } 682 683 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 684 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 685 686 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 687 buffer[count++] = cpu_to_le32(0); 688 } 689 690 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 691 { 692 uint32_t data; 693 694 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 695 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 696 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 697 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 698 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 699 700 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 701 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 702 703 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 704 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 705 706 mutex_lock(&adev->grbm_idx_mutex); 707 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 708 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 709 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 710 711 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 712 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 713 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 714 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 715 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 716 717 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 718 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 719 data &= 0x0000FFFF; 720 data |= 0x00C00000; 721 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 722 723 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */ 724 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF); 725 726 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 727 * but used for RLC_LB_CNTL configuration */ 728 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 729 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 730 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 731 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 732 mutex_unlock(&adev->grbm_idx_mutex); 733 } 734 735 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 736 { 737 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 738 } 739 740 static void rv_init_cp_jump_table(struct amdgpu_device *adev) 741 { 742 const __le32 *fw_data; 743 volatile u32 *dst_ptr; 744 int me, i, max_me = 5; 745 u32 bo_offset = 0; 746 u32 table_offset, table_size; 747 748 /* write the cp table buffer */ 749 dst_ptr = adev->gfx.rlc.cp_table_ptr; 750 for (me = 0; me < max_me; me++) { 751 if (me == 0) { 752 const struct gfx_firmware_header_v1_0 *hdr = 753 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 754 fw_data = (const __le32 *) 755 (adev->gfx.ce_fw->data + 756 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 757 table_offset = le32_to_cpu(hdr->jt_offset); 758 table_size = le32_to_cpu(hdr->jt_size); 759 } else if (me == 1) { 760 const struct gfx_firmware_header_v1_0 *hdr = 761 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 762 fw_data = (const __le32 *) 763 (adev->gfx.pfp_fw->data + 764 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 765 table_offset = le32_to_cpu(hdr->jt_offset); 766 table_size = le32_to_cpu(hdr->jt_size); 767 } else if (me == 2) { 768 const struct gfx_firmware_header_v1_0 *hdr = 769 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 770 fw_data = (const __le32 *) 771 (adev->gfx.me_fw->data + 772 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 773 table_offset = le32_to_cpu(hdr->jt_offset); 774 table_size = le32_to_cpu(hdr->jt_size); 775 } else if (me == 3) { 776 const struct gfx_firmware_header_v1_0 *hdr = 777 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 778 fw_data = (const __le32 *) 779 (adev->gfx.mec_fw->data + 780 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 781 table_offset = le32_to_cpu(hdr->jt_offset); 782 table_size = le32_to_cpu(hdr->jt_size); 783 } else if (me == 4) { 784 const struct gfx_firmware_header_v1_0 *hdr = 785 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 786 fw_data = (const __le32 *) 787 (adev->gfx.mec2_fw->data + 788 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 789 table_offset = le32_to_cpu(hdr->jt_offset); 790 table_size = le32_to_cpu(hdr->jt_size); 791 } 792 793 for (i = 0; i < table_size; i ++) { 794 dst_ptr[bo_offset + i] = 795 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 796 } 797 798 bo_offset += table_size; 799 } 800 } 801 802 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) 803 { 804 /* clear state block */ 805 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 806 &adev->gfx.rlc.clear_state_gpu_addr, 807 (void **)&adev->gfx.rlc.cs_ptr); 808 809 /* jump table block */ 810 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 811 &adev->gfx.rlc.cp_table_gpu_addr, 812 (void **)&adev->gfx.rlc.cp_table_ptr); 813 } 814 815 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 816 { 817 volatile u32 *dst_ptr; 818 u32 dws; 819 const struct cs_section_def *cs_data; 820 int r; 821 822 adev->gfx.rlc.cs_data = gfx9_cs_data; 823 824 cs_data = adev->gfx.rlc.cs_data; 825 826 if (cs_data) { 827 /* clear state block */ 828 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); 829 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 830 AMDGPU_GEM_DOMAIN_VRAM, 831 &adev->gfx.rlc.clear_state_obj, 832 &adev->gfx.rlc.clear_state_gpu_addr, 833 (void **)&adev->gfx.rlc.cs_ptr); 834 if (r) { 835 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", 836 r); 837 gfx_v9_0_rlc_fini(adev); 838 return r; 839 } 840 /* set up the cs buffer */ 841 dst_ptr = adev->gfx.rlc.cs_ptr; 842 gfx_v9_0_get_csb_buffer(adev, dst_ptr); 843 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 844 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 845 } 846 847 if (adev->asic_type == CHIP_RAVEN) { 848 /* TODO: double check the cp_table_size for RV */ 849 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 850 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, 851 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 852 &adev->gfx.rlc.cp_table_obj, 853 &adev->gfx.rlc.cp_table_gpu_addr, 854 (void **)&adev->gfx.rlc.cp_table_ptr); 855 if (r) { 856 dev_err(adev->dev, 857 "(%d) failed to create cp table bo\n", r); 858 gfx_v9_0_rlc_fini(adev); 859 return r; 860 } 861 862 rv_init_cp_jump_table(adev); 863 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 864 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 865 866 gfx_v9_0_init_lbpw(adev); 867 } 868 869 return 0; 870 } 871 872 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 873 { 874 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 875 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 876 } 877 878 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 879 { 880 int r; 881 u32 *hpd; 882 const __le32 *fw_data; 883 unsigned fw_size; 884 u32 *fw; 885 size_t mec_hpd_size; 886 887 const struct gfx_firmware_header_v1_0 *mec_hdr; 888 889 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 890 891 /* take ownership of the relevant compute queues */ 892 amdgpu_gfx_compute_queue_acquire(adev); 893 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 894 895 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 896 AMDGPU_GEM_DOMAIN_GTT, 897 &adev->gfx.mec.hpd_eop_obj, 898 &adev->gfx.mec.hpd_eop_gpu_addr, 899 (void **)&hpd); 900 if (r) { 901 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 902 gfx_v9_0_mec_fini(adev); 903 return r; 904 } 905 906 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 907 908 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 909 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 910 911 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 912 913 fw_data = (const __le32 *) 914 (adev->gfx.mec_fw->data + 915 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 916 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 917 918 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 919 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 920 &adev->gfx.mec.mec_fw_obj, 921 &adev->gfx.mec.mec_fw_gpu_addr, 922 (void **)&fw); 923 if (r) { 924 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 925 gfx_v9_0_mec_fini(adev); 926 return r; 927 } 928 929 memcpy(fw, fw_data, fw_size); 930 931 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 932 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 933 934 return 0; 935 } 936 937 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 938 { 939 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 940 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 941 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 942 (address << SQ_IND_INDEX__INDEX__SHIFT) | 943 (SQ_IND_INDEX__FORCE_READ_MASK)); 944 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 945 } 946 947 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 948 uint32_t wave, uint32_t thread, 949 uint32_t regno, uint32_t num, uint32_t *out) 950 { 951 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 952 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 953 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 954 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 955 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 956 (SQ_IND_INDEX__FORCE_READ_MASK) | 957 (SQ_IND_INDEX__AUTO_INCR_MASK)); 958 while (num--) 959 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 960 } 961 962 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 963 { 964 /* type 1 wave data */ 965 dst[(*no_fields)++] = 1; 966 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 967 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 968 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 969 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 970 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 971 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 972 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 973 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 980 } 981 982 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 983 uint32_t wave, uint32_t start, 984 uint32_t size, uint32_t *dst) 985 { 986 wave_read_regs( 987 adev, simd, wave, 0, 988 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 989 } 990 991 992 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 993 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 994 .select_se_sh = &gfx_v9_0_select_se_sh, 995 .read_wave_data = &gfx_v9_0_read_wave_data, 996 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 997 }; 998 999 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1000 { 1001 u32 gb_addr_config; 1002 1003 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1004 1005 switch (adev->asic_type) { 1006 case CHIP_VEGA10: 1007 adev->gfx.config.max_hw_contexts = 8; 1008 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1009 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1010 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1011 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1012 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1013 break; 1014 case CHIP_RAVEN: 1015 adev->gfx.config.max_hw_contexts = 8; 1016 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1017 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1018 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1019 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1020 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1021 break; 1022 default: 1023 BUG(); 1024 break; 1025 } 1026 1027 adev->gfx.config.gb_addr_config = gb_addr_config; 1028 1029 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1030 REG_GET_FIELD( 1031 adev->gfx.config.gb_addr_config, 1032 GB_ADDR_CONFIG, 1033 NUM_PIPES); 1034 1035 adev->gfx.config.max_tile_pipes = 1036 adev->gfx.config.gb_addr_config_fields.num_pipes; 1037 1038 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1039 REG_GET_FIELD( 1040 adev->gfx.config.gb_addr_config, 1041 GB_ADDR_CONFIG, 1042 NUM_BANKS); 1043 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1044 REG_GET_FIELD( 1045 adev->gfx.config.gb_addr_config, 1046 GB_ADDR_CONFIG, 1047 MAX_COMPRESSED_FRAGS); 1048 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1049 REG_GET_FIELD( 1050 adev->gfx.config.gb_addr_config, 1051 GB_ADDR_CONFIG, 1052 NUM_RB_PER_SE); 1053 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1054 REG_GET_FIELD( 1055 adev->gfx.config.gb_addr_config, 1056 GB_ADDR_CONFIG, 1057 NUM_SHADER_ENGINES); 1058 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1059 REG_GET_FIELD( 1060 adev->gfx.config.gb_addr_config, 1061 GB_ADDR_CONFIG, 1062 PIPE_INTERLEAVE_SIZE)); 1063 } 1064 1065 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1066 struct amdgpu_ngg_buf *ngg_buf, 1067 int size_se, 1068 int default_size_se) 1069 { 1070 int r; 1071 1072 if (size_se < 0) { 1073 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1074 return -EINVAL; 1075 } 1076 size_se = size_se ? size_se : default_size_se; 1077 1078 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1079 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1080 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1081 &ngg_buf->bo, 1082 &ngg_buf->gpu_addr, 1083 NULL); 1084 if (r) { 1085 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1086 return r; 1087 } 1088 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1089 1090 return r; 1091 } 1092 1093 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1094 { 1095 int i; 1096 1097 for (i = 0; i < NGG_BUF_MAX; i++) 1098 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1099 &adev->gfx.ngg.buf[i].gpu_addr, 1100 NULL); 1101 1102 memset(&adev->gfx.ngg.buf[0], 0, 1103 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1104 1105 adev->gfx.ngg.init = false; 1106 1107 return 0; 1108 } 1109 1110 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1111 { 1112 int r; 1113 1114 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1115 return 0; 1116 1117 /* GDS reserve memory: 64 bytes alignment */ 1118 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1119 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1120 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1121 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; 1122 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; 1123 1124 /* Primitive Buffer */ 1125 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1126 amdgpu_prim_buf_per_se, 1127 64 * 1024); 1128 if (r) { 1129 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1130 goto err; 1131 } 1132 1133 /* Position Buffer */ 1134 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1135 amdgpu_pos_buf_per_se, 1136 256 * 1024); 1137 if (r) { 1138 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1139 goto err; 1140 } 1141 1142 /* Control Sideband */ 1143 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1144 amdgpu_cntl_sb_buf_per_se, 1145 256); 1146 if (r) { 1147 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1148 goto err; 1149 } 1150 1151 /* Parameter Cache, not created by default */ 1152 if (amdgpu_param_buf_per_se <= 0) 1153 goto out; 1154 1155 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1156 amdgpu_param_buf_per_se, 1157 512 * 1024); 1158 if (r) { 1159 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1160 goto err; 1161 } 1162 1163 out: 1164 adev->gfx.ngg.init = true; 1165 return 0; 1166 err: 1167 gfx_v9_0_ngg_fini(adev); 1168 return r; 1169 } 1170 1171 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1172 { 1173 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1174 int r; 1175 u32 data, base; 1176 1177 if (!amdgpu_ngg) 1178 return 0; 1179 1180 /* Program buffer size */ 1181 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, 1182 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); 1183 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, 1184 adev->gfx.ngg.buf[NGG_POS].size >> 8); 1185 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1186 1187 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, 1188 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); 1189 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, 1190 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); 1191 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1192 1193 /* Program buffer base address */ 1194 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1195 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1196 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1197 1198 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1199 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1200 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1201 1202 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1203 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1204 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1205 1206 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1207 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1208 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1209 1210 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1211 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1212 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1213 1214 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1215 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1216 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1217 1218 /* Clear GDS reserved memory */ 1219 r = amdgpu_ring_alloc(ring, 17); 1220 if (r) { 1221 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", 1222 ring->idx, r); 1223 return r; 1224 } 1225 1226 gfx_v9_0_write_data_to_reg(ring, 0, false, 1227 amdgpu_gds_reg_offset[0].mem_size, 1228 (adev->gds.mem.total_size + 1229 adev->gfx.ngg.gds_reserve_size) >> 1230 AMDGPU_GDS_SHIFT); 1231 1232 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1233 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1234 PACKET3_DMA_DATA_SRC_SEL(2))); 1235 amdgpu_ring_write(ring, 0); 1236 amdgpu_ring_write(ring, 0); 1237 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1238 amdgpu_ring_write(ring, 0); 1239 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); 1240 1241 1242 gfx_v9_0_write_data_to_reg(ring, 0, false, 1243 amdgpu_gds_reg_offset[0].mem_size, 0); 1244 1245 amdgpu_ring_commit(ring); 1246 1247 return 0; 1248 } 1249 1250 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1251 int mec, int pipe, int queue) 1252 { 1253 int r; 1254 unsigned irq_type; 1255 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1256 1257 ring = &adev->gfx.compute_ring[ring_id]; 1258 1259 /* mec0 is me1 */ 1260 ring->me = mec + 1; 1261 ring->pipe = pipe; 1262 ring->queue = queue; 1263 1264 ring->ring_obj = NULL; 1265 ring->use_doorbell = true; 1266 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; 1267 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1268 + (ring_id * GFX9_MEC_HPD_SIZE); 1269 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1270 1271 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1272 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1273 + ring->pipe; 1274 1275 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1276 r = amdgpu_ring_init(adev, ring, 1024, 1277 &adev->gfx.eop_irq, irq_type); 1278 if (r) 1279 return r; 1280 1281 1282 return 0; 1283 } 1284 1285 static int gfx_v9_0_sw_init(void *handle) 1286 { 1287 int i, j, k, r, ring_id; 1288 struct amdgpu_ring *ring; 1289 struct amdgpu_kiq *kiq; 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 switch (adev->asic_type) { 1293 case CHIP_VEGA10: 1294 case CHIP_RAVEN: 1295 adev->gfx.mec.num_mec = 2; 1296 break; 1297 default: 1298 adev->gfx.mec.num_mec = 1; 1299 break; 1300 } 1301 1302 adev->gfx.mec.num_pipe_per_mec = 4; 1303 adev->gfx.mec.num_queue_per_pipe = 8; 1304 1305 /* KIQ event */ 1306 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); 1307 if (r) 1308 return r; 1309 1310 /* EOP Event */ 1311 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); 1312 if (r) 1313 return r; 1314 1315 /* Privileged reg */ 1316 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, 1317 &adev->gfx.priv_reg_irq); 1318 if (r) 1319 return r; 1320 1321 /* Privileged inst */ 1322 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, 1323 &adev->gfx.priv_inst_irq); 1324 if (r) 1325 return r; 1326 1327 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1328 1329 gfx_v9_0_scratch_init(adev); 1330 1331 r = gfx_v9_0_init_microcode(adev); 1332 if (r) { 1333 DRM_ERROR("Failed to load gfx firmware!\n"); 1334 return r; 1335 } 1336 1337 r = gfx_v9_0_rlc_init(adev); 1338 if (r) { 1339 DRM_ERROR("Failed to init rlc BOs!\n"); 1340 return r; 1341 } 1342 1343 r = gfx_v9_0_mec_init(adev); 1344 if (r) { 1345 DRM_ERROR("Failed to init MEC BOs!\n"); 1346 return r; 1347 } 1348 1349 /* set up the gfx ring */ 1350 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1351 ring = &adev->gfx.gfx_ring[i]; 1352 ring->ring_obj = NULL; 1353 if (!i) 1354 sprintf(ring->name, "gfx"); 1355 else 1356 sprintf(ring->name, "gfx_%d", i); 1357 ring->use_doorbell = true; 1358 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; 1359 r = amdgpu_ring_init(adev, ring, 1024, 1360 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1361 if (r) 1362 return r; 1363 } 1364 1365 /* set up the compute queues - allocate horizontally across pipes */ 1366 ring_id = 0; 1367 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1368 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1369 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1370 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 1371 continue; 1372 1373 r = gfx_v9_0_compute_ring_init(adev, 1374 ring_id, 1375 i, k, j); 1376 if (r) 1377 return r; 1378 1379 ring_id++; 1380 } 1381 } 1382 } 1383 1384 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 1385 if (r) { 1386 DRM_ERROR("Failed to init KIQ BOs!\n"); 1387 return r; 1388 } 1389 1390 kiq = &adev->gfx.kiq; 1391 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1392 if (r) 1393 return r; 1394 1395 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1396 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 1397 if (r) 1398 return r; 1399 1400 /* reserve GDS, GWS and OA resource for gfx */ 1401 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 1402 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 1403 &adev->gds.gds_gfx_bo, NULL, NULL); 1404 if (r) 1405 return r; 1406 1407 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 1408 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 1409 &adev->gds.gws_gfx_bo, NULL, NULL); 1410 if (r) 1411 return r; 1412 1413 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 1414 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 1415 &adev->gds.oa_gfx_bo, NULL, NULL); 1416 if (r) 1417 return r; 1418 1419 adev->gfx.ce_ram_size = 0x8000; 1420 1421 gfx_v9_0_gpu_early_init(adev); 1422 1423 r = gfx_v9_0_ngg_init(adev); 1424 if (r) 1425 return r; 1426 1427 return 0; 1428 } 1429 1430 1431 static int gfx_v9_0_sw_fini(void *handle) 1432 { 1433 int i; 1434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1435 1436 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1437 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1438 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1439 1440 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1441 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1442 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1443 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1444 1445 amdgpu_gfx_compute_mqd_sw_fini(adev); 1446 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1447 amdgpu_gfx_kiq_fini(adev); 1448 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); 1449 1450 gfx_v9_0_mec_fini(adev); 1451 gfx_v9_0_ngg_fini(adev); 1452 gfx_v9_0_free_microcode(adev); 1453 1454 return 0; 1455 } 1456 1457 1458 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1459 { 1460 /* TODO */ 1461 } 1462 1463 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1464 { 1465 u32 data; 1466 1467 if (instance == 0xffffffff) 1468 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1469 else 1470 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1471 1472 if (se_num == 0xffffffff) 1473 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1474 else 1475 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1476 1477 if (sh_num == 0xffffffff) 1478 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1479 else 1480 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1481 1482 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1483 } 1484 1485 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1486 { 1487 u32 data, mask; 1488 1489 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1490 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1491 1492 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1493 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1494 1495 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1496 adev->gfx.config.max_sh_per_se); 1497 1498 return (~data) & mask; 1499 } 1500 1501 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1502 { 1503 int i, j; 1504 u32 data; 1505 u32 active_rbs = 0; 1506 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1507 adev->gfx.config.max_sh_per_se; 1508 1509 mutex_lock(&adev->grbm_idx_mutex); 1510 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1511 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1512 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1513 data = gfx_v9_0_get_rb_active_bitmap(adev); 1514 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1515 rb_bitmap_width_per_sh); 1516 } 1517 } 1518 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1519 mutex_unlock(&adev->grbm_idx_mutex); 1520 1521 adev->gfx.config.backend_enable_mask = active_rbs; 1522 adev->gfx.config.num_rbs = hweight32(active_rbs); 1523 } 1524 1525 #define DEFAULT_SH_MEM_BASES (0x6000) 1526 #define FIRST_COMPUTE_VMID (8) 1527 #define LAST_COMPUTE_VMID (16) 1528 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1529 { 1530 int i; 1531 uint32_t sh_mem_config; 1532 uint32_t sh_mem_bases; 1533 1534 /* 1535 * Configure apertures: 1536 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1537 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1538 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1539 */ 1540 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1541 1542 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1543 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1544 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1545 1546 mutex_lock(&adev->srbm_mutex); 1547 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1548 soc15_grbm_select(adev, 0, 0, 0, i); 1549 /* CP and shaders */ 1550 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1551 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1552 } 1553 soc15_grbm_select(adev, 0, 0, 0, 0); 1554 mutex_unlock(&adev->srbm_mutex); 1555 } 1556 1557 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 1558 { 1559 u32 tmp; 1560 int i; 1561 1562 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1563 1564 gfx_v9_0_tiling_mode_table_init(adev); 1565 1566 gfx_v9_0_setup_rb(adev); 1567 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1568 1569 /* XXX SH_MEM regs */ 1570 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1571 mutex_lock(&adev->srbm_mutex); 1572 for (i = 0; i < 16; i++) { 1573 soc15_grbm_select(adev, 0, 0, 0, i); 1574 /* CP and shaders */ 1575 tmp = 0; 1576 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 1577 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1578 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1579 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1580 } 1581 soc15_grbm_select(adev, 0, 0, 0, 0); 1582 1583 mutex_unlock(&adev->srbm_mutex); 1584 1585 gfx_v9_0_init_compute_vmid(adev); 1586 1587 mutex_lock(&adev->grbm_idx_mutex); 1588 /* 1589 * making sure that the following register writes will be broadcasted 1590 * to all the shaders 1591 */ 1592 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1593 1594 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1595 (adev->gfx.config.sc_prim_fifo_size_frontend << 1596 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1597 (adev->gfx.config.sc_prim_fifo_size_backend << 1598 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1599 (adev->gfx.config.sc_hiz_tile_fifo_size << 1600 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1601 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1602 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1603 mutex_unlock(&adev->grbm_idx_mutex); 1604 1605 } 1606 1607 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1608 { 1609 u32 i, j, k; 1610 u32 mask; 1611 1612 mutex_lock(&adev->grbm_idx_mutex); 1613 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1614 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1615 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1616 for (k = 0; k < adev->usec_timeout; k++) { 1617 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1618 break; 1619 udelay(1); 1620 } 1621 } 1622 } 1623 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1624 mutex_unlock(&adev->grbm_idx_mutex); 1625 1626 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1627 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1628 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1629 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1630 for (k = 0; k < adev->usec_timeout; k++) { 1631 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1632 break; 1633 udelay(1); 1634 } 1635 } 1636 1637 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1638 bool enable) 1639 { 1640 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1641 1642 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1643 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1644 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1645 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1646 1647 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1648 } 1649 1650 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 1651 { 1652 /* csib */ 1653 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 1654 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1655 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 1656 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1657 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 1658 adev->gfx.rlc.clear_state_size); 1659 } 1660 1661 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format, 1662 int indirect_offset, 1663 int list_size, 1664 int *unique_indirect_regs, 1665 int *unique_indirect_reg_count, 1666 int max_indirect_reg_count, 1667 int *indirect_start_offsets, 1668 int *indirect_start_offsets_count, 1669 int max_indirect_start_offsets_count) 1670 { 1671 int idx; 1672 bool new_entry = true; 1673 1674 for (; indirect_offset < list_size; indirect_offset++) { 1675 1676 if (new_entry) { 1677 new_entry = false; 1678 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 1679 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 1680 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count); 1681 } 1682 1683 if (register_list_format[indirect_offset] == 0xFFFFFFFF) { 1684 new_entry = true; 1685 continue; 1686 } 1687 1688 indirect_offset += 2; 1689 1690 /* look for the matching indice */ 1691 for (idx = 0; idx < *unique_indirect_reg_count; idx++) { 1692 if (unique_indirect_regs[idx] == 1693 register_list_format[indirect_offset]) 1694 break; 1695 } 1696 1697 if (idx >= *unique_indirect_reg_count) { 1698 unique_indirect_regs[*unique_indirect_reg_count] = 1699 register_list_format[indirect_offset]; 1700 idx = *unique_indirect_reg_count; 1701 *unique_indirect_reg_count = *unique_indirect_reg_count + 1; 1702 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count); 1703 } 1704 1705 register_list_format[indirect_offset] = idx; 1706 } 1707 } 1708 1709 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) 1710 { 1711 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1712 int unique_indirect_reg_count = 0; 1713 1714 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1715 int indirect_start_offsets_count = 0; 1716 1717 int list_size = 0; 1718 int i = 0; 1719 u32 tmp = 0; 1720 1721 u32 *register_list_format = 1722 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 1723 if (!register_list_format) 1724 return -ENOMEM; 1725 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 1726 adev->gfx.rlc.reg_list_format_size_bytes); 1727 1728 /* setup unique_indirect_regs array and indirect_start_offsets array */ 1729 gfx_v9_0_parse_ind_reg_list(register_list_format, 1730 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, 1731 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 1732 unique_indirect_regs, 1733 &unique_indirect_reg_count, 1734 ARRAY_SIZE(unique_indirect_regs), 1735 indirect_start_offsets, 1736 &indirect_start_offsets_count, 1737 ARRAY_SIZE(indirect_start_offsets)); 1738 1739 /* enable auto inc in case it is disabled */ 1740 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1741 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1742 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1743 1744 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 1745 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 1746 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 1747 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1748 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1749 adev->gfx.rlc.register_restore[i]); 1750 1751 /* load direct register */ 1752 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0); 1753 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1754 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1755 adev->gfx.rlc.register_restore[i]); 1756 1757 /* load indirect register */ 1758 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1759 adev->gfx.rlc.reg_list_format_start); 1760 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) 1761 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1762 register_list_format[i]); 1763 1764 /* set save/restore list size */ 1765 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 1766 list_size = list_size >> 1; 1767 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1768 adev->gfx.rlc.reg_restore_list_size); 1769 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 1770 1771 /* write the starting offsets to RLC scratch ram */ 1772 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1773 adev->gfx.rlc.starting_offsets_start); 1774 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 1775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1776 indirect_start_offsets[i]); 1777 1778 /* load unique indirect regs*/ 1779 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 1780 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i, 1781 unique_indirect_regs[i] & 0x3FFFF); 1782 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i, 1783 unique_indirect_regs[i] >> 20); 1784 } 1785 1786 kfree(register_list_format); 1787 return 0; 1788 } 1789 1790 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 1791 { 1792 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 1793 } 1794 1795 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 1796 bool enable) 1797 { 1798 uint32_t data = 0; 1799 uint32_t default_data = 0; 1800 1801 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 1802 if (enable == true) { 1803 /* enable GFXIP control over CGPG */ 1804 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1805 if(default_data != data) 1806 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1807 1808 /* update status */ 1809 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 1810 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 1811 if(default_data != data) 1812 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1813 } else { 1814 /* restore GFXIP control over GCPG */ 1815 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1816 if(default_data != data) 1817 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1818 } 1819 } 1820 1821 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 1822 { 1823 uint32_t data = 0; 1824 1825 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1826 AMD_PG_SUPPORT_GFX_SMG | 1827 AMD_PG_SUPPORT_GFX_DMG)) { 1828 /* init IDLE_POLL_COUNT = 60 */ 1829 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 1830 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 1831 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 1832 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 1833 1834 /* init RLC PG Delay */ 1835 data = 0; 1836 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 1837 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 1838 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 1839 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 1840 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 1841 1842 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 1843 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 1844 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 1845 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 1846 1847 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 1848 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 1849 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 1850 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 1851 1852 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 1853 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 1854 1855 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 1856 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 1857 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 1858 1859 pwr_10_0_gfxip_control_over_cgpg(adev, true); 1860 } 1861 } 1862 1863 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 1864 bool enable) 1865 { 1866 uint32_t data = 0; 1867 uint32_t default_data = 0; 1868 1869 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1870 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1871 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 1872 enable ? 1 : 0); 1873 if (default_data != data) 1874 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1875 } 1876 1877 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 1878 bool enable) 1879 { 1880 uint32_t data = 0; 1881 uint32_t default_data = 0; 1882 1883 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1884 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1885 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 1886 enable ? 1 : 0); 1887 if(default_data != data) 1888 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1889 } 1890 1891 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 1892 bool enable) 1893 { 1894 uint32_t data = 0; 1895 uint32_t default_data = 0; 1896 1897 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1898 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1899 CP_PG_DISABLE, 1900 enable ? 0 : 1); 1901 if(default_data != data) 1902 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1903 } 1904 1905 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 1906 bool enable) 1907 { 1908 uint32_t data, default_data; 1909 1910 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1911 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1912 GFX_POWER_GATING_ENABLE, 1913 enable ? 1 : 0); 1914 if(default_data != data) 1915 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1916 } 1917 1918 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 1919 bool enable) 1920 { 1921 uint32_t data, default_data; 1922 1923 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1924 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1925 GFX_PIPELINE_PG_ENABLE, 1926 enable ? 1 : 0); 1927 if(default_data != data) 1928 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1929 1930 if (!enable) 1931 /* read any GFX register to wake up GFX */ 1932 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 1933 } 1934 1935 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 1936 bool enable) 1937 { 1938 uint32_t data, default_data; 1939 1940 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1941 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1942 STATIC_PER_CU_PG_ENABLE, 1943 enable ? 1 : 0); 1944 if(default_data != data) 1945 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1946 } 1947 1948 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 1949 bool enable) 1950 { 1951 uint32_t data, default_data; 1952 1953 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1954 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1955 DYN_PER_CU_PG_ENABLE, 1956 enable ? 1 : 0); 1957 if(default_data != data) 1958 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1959 } 1960 1961 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 1962 { 1963 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1964 AMD_PG_SUPPORT_GFX_SMG | 1965 AMD_PG_SUPPORT_GFX_DMG | 1966 AMD_PG_SUPPORT_CP | 1967 AMD_PG_SUPPORT_GDS | 1968 AMD_PG_SUPPORT_RLC_SMU_HS)) { 1969 gfx_v9_0_init_csb(adev); 1970 gfx_v9_0_init_rlc_save_restore_list(adev); 1971 gfx_v9_0_enable_save_restore_machine(adev); 1972 1973 if (adev->asic_type == CHIP_RAVEN) { 1974 WREG32(mmRLC_JUMP_TABLE_RESTORE, 1975 adev->gfx.rlc.cp_table_gpu_addr >> 8); 1976 gfx_v9_0_init_gfx_power_gating(adev); 1977 1978 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 1979 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 1980 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 1981 } else { 1982 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 1983 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 1984 } 1985 1986 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 1987 gfx_v9_0_enable_cp_power_gating(adev, true); 1988 else 1989 gfx_v9_0_enable_cp_power_gating(adev, false); 1990 } 1991 } 1992 } 1993 1994 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 1995 { 1996 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 1997 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 1998 gfx_v9_0_wait_for_rlc_serdes(adev); 1999 } 2000 2001 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2002 { 2003 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2004 udelay(50); 2005 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2006 udelay(50); 2007 } 2008 2009 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2010 { 2011 #ifdef AMDGPU_RLC_DEBUG_RETRY 2012 u32 rlc_ucode_ver; 2013 #endif 2014 2015 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2016 2017 /* carrizo do enable cp interrupt after cp inited */ 2018 if (!(adev->flags & AMD_IS_APU)) 2019 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2020 2021 udelay(50); 2022 2023 #ifdef AMDGPU_RLC_DEBUG_RETRY 2024 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2025 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2026 if(rlc_ucode_ver == 0x108) { 2027 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2028 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2029 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2030 * default is 0x9C4 to create a 100us interval */ 2031 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2032 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2033 * to disable the page fault retry interrupts, default is 2034 * 0x100 (256) */ 2035 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2036 } 2037 #endif 2038 } 2039 2040 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2041 { 2042 const struct rlc_firmware_header_v2_0 *hdr; 2043 const __le32 *fw_data; 2044 unsigned i, fw_size; 2045 2046 if (!adev->gfx.rlc_fw) 2047 return -EINVAL; 2048 2049 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2050 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2051 2052 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2053 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2054 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2055 2056 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2057 RLCG_UCODE_LOADING_START_ADDRESS); 2058 for (i = 0; i < fw_size; i++) 2059 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2060 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2061 2062 return 0; 2063 } 2064 2065 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2066 { 2067 int r; 2068 2069 if (amdgpu_sriov_vf(adev)) { 2070 gfx_v9_0_init_csb(adev); 2071 return 0; 2072 } 2073 2074 gfx_v9_0_rlc_stop(adev); 2075 2076 /* disable CG */ 2077 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2078 2079 /* disable PG */ 2080 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 2081 2082 gfx_v9_0_rlc_reset(adev); 2083 2084 gfx_v9_0_init_pg(adev); 2085 2086 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2087 /* legacy rlc firmware loading */ 2088 r = gfx_v9_0_rlc_load_microcode(adev); 2089 if (r) 2090 return r; 2091 } 2092 2093 if (adev->asic_type == CHIP_RAVEN) { 2094 if (amdgpu_lbpw != 0) 2095 gfx_v9_0_enable_lbpw(adev, true); 2096 else 2097 gfx_v9_0_enable_lbpw(adev, false); 2098 } 2099 2100 gfx_v9_0_rlc_start(adev); 2101 2102 return 0; 2103 } 2104 2105 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2106 { 2107 int i; 2108 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2109 2110 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2111 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2112 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2113 if (!enable) { 2114 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2115 adev->gfx.gfx_ring[i].ready = false; 2116 } 2117 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2118 udelay(50); 2119 } 2120 2121 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2122 { 2123 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2124 const struct gfx_firmware_header_v1_0 *ce_hdr; 2125 const struct gfx_firmware_header_v1_0 *me_hdr; 2126 const __le32 *fw_data; 2127 unsigned i, fw_size; 2128 2129 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2130 return -EINVAL; 2131 2132 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2133 adev->gfx.pfp_fw->data; 2134 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2135 adev->gfx.ce_fw->data; 2136 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2137 adev->gfx.me_fw->data; 2138 2139 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2140 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2141 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2142 2143 gfx_v9_0_cp_gfx_enable(adev, false); 2144 2145 /* PFP */ 2146 fw_data = (const __le32 *) 2147 (adev->gfx.pfp_fw->data + 2148 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2149 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2150 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2151 for (i = 0; i < fw_size; i++) 2152 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2153 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2154 2155 /* CE */ 2156 fw_data = (const __le32 *) 2157 (adev->gfx.ce_fw->data + 2158 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2159 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2160 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2161 for (i = 0; i < fw_size; i++) 2162 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2163 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2164 2165 /* ME */ 2166 fw_data = (const __le32 *) 2167 (adev->gfx.me_fw->data + 2168 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2169 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2170 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2171 for (i = 0; i < fw_size; i++) 2172 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2173 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2174 2175 return 0; 2176 } 2177 2178 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2179 { 2180 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2181 const struct cs_section_def *sect = NULL; 2182 const struct cs_extent_def *ext = NULL; 2183 int r, i, tmp; 2184 2185 /* init the CP */ 2186 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2187 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2188 2189 gfx_v9_0_cp_gfx_enable(adev, true); 2190 2191 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 2192 if (r) { 2193 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2194 return r; 2195 } 2196 2197 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2198 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2199 2200 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2201 amdgpu_ring_write(ring, 0x80000000); 2202 amdgpu_ring_write(ring, 0x80000000); 2203 2204 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2205 for (ext = sect->section; ext->extent != NULL; ++ext) { 2206 if (sect->id == SECT_CONTEXT) { 2207 amdgpu_ring_write(ring, 2208 PACKET3(PACKET3_SET_CONTEXT_REG, 2209 ext->reg_count)); 2210 amdgpu_ring_write(ring, 2211 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2212 for (i = 0; i < ext->reg_count; i++) 2213 amdgpu_ring_write(ring, ext->extent[i]); 2214 } 2215 } 2216 } 2217 2218 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2219 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2220 2221 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2222 amdgpu_ring_write(ring, 0); 2223 2224 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2225 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2226 amdgpu_ring_write(ring, 0x8000); 2227 amdgpu_ring_write(ring, 0x8000); 2228 2229 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 2230 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 2231 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 2232 amdgpu_ring_write(ring, tmp); 2233 amdgpu_ring_write(ring, 0); 2234 2235 amdgpu_ring_commit(ring); 2236 2237 return 0; 2238 } 2239 2240 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2241 { 2242 struct amdgpu_ring *ring; 2243 u32 tmp; 2244 u32 rb_bufsz; 2245 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2246 2247 /* Set the write pointer delay */ 2248 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2249 2250 /* set the RB to use vmid 0 */ 2251 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2252 2253 /* Set ring buffer size */ 2254 ring = &adev->gfx.gfx_ring[0]; 2255 rb_bufsz = order_base_2(ring->ring_size / 8); 2256 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2257 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2258 #ifdef __BIG_ENDIAN 2259 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2260 #endif 2261 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2262 2263 /* Initialize the ring buffer's write pointers */ 2264 ring->wptr = 0; 2265 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2266 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2267 2268 /* set the wb address wether it's enabled or not */ 2269 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2270 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2271 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2272 2273 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2274 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2275 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2276 2277 mdelay(1); 2278 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2279 2280 rb_addr = ring->gpu_addr >> 8; 2281 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2282 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2283 2284 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2285 if (ring->use_doorbell) { 2286 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2287 DOORBELL_OFFSET, ring->doorbell_index); 2288 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2289 DOORBELL_EN, 1); 2290 } else { 2291 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2292 } 2293 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2294 2295 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2296 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2297 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2298 2299 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2300 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2301 2302 2303 /* start the ring */ 2304 gfx_v9_0_cp_gfx_start(adev); 2305 ring->ready = true; 2306 2307 return 0; 2308 } 2309 2310 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2311 { 2312 int i; 2313 2314 if (enable) { 2315 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2316 } else { 2317 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2318 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2319 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2320 adev->gfx.compute_ring[i].ready = false; 2321 adev->gfx.kiq.ring.ready = false; 2322 } 2323 udelay(50); 2324 } 2325 2326 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2327 { 2328 const struct gfx_firmware_header_v1_0 *mec_hdr; 2329 const __le32 *fw_data; 2330 unsigned i; 2331 u32 tmp; 2332 2333 if (!adev->gfx.mec_fw) 2334 return -EINVAL; 2335 2336 gfx_v9_0_cp_compute_enable(adev, false); 2337 2338 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2339 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2340 2341 fw_data = (const __le32 *) 2342 (adev->gfx.mec_fw->data + 2343 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2344 tmp = 0; 2345 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2346 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2348 2349 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2350 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2351 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2352 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2353 2354 /* MEC1 */ 2355 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2356 mec_hdr->jt_offset); 2357 for (i = 0; i < mec_hdr->jt_size; i++) 2358 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2359 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2360 2361 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2362 adev->gfx.mec_fw_version); 2363 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2364 2365 return 0; 2366 } 2367 2368 /* KIQ functions */ 2369 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2370 { 2371 uint32_t tmp; 2372 struct amdgpu_device *adev = ring->adev; 2373 2374 /* tell RLC which is KIQ queue */ 2375 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2376 tmp &= 0xffffff00; 2377 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2378 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2379 tmp |= 0x80; 2380 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2381 } 2382 2383 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) 2384 { 2385 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 2386 uint32_t scratch, tmp = 0; 2387 uint64_t queue_mask = 0; 2388 int r, i; 2389 2390 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 2391 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 2392 continue; 2393 2394 /* This situation may be hit in the future if a new HW 2395 * generation exposes more than 64 queues. If so, the 2396 * definition of queue_mask needs updating */ 2397 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 2398 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 2399 break; 2400 } 2401 2402 queue_mask |= (1ull << i); 2403 } 2404 2405 r = amdgpu_gfx_scratch_get(adev, &scratch); 2406 if (r) { 2407 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2408 return r; 2409 } 2410 WREG32(scratch, 0xCAFEDEAD); 2411 2412 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); 2413 if (r) { 2414 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2415 amdgpu_gfx_scratch_free(adev, scratch); 2416 return r; 2417 } 2418 2419 /* set resources */ 2420 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2421 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2422 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2423 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 2424 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 2425 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 2426 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 2427 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 2428 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 2429 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2430 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2431 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2432 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2433 2434 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2435 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2436 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2437 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2438 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2439 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2440 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2441 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2442 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2443 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */ 2444 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2445 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2446 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2447 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2448 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2449 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2450 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2451 } 2452 /* write to scratch for completion */ 2453 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2454 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2455 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2456 amdgpu_ring_commit(kiq_ring); 2457 2458 for (i = 0; i < adev->usec_timeout; i++) { 2459 tmp = RREG32(scratch); 2460 if (tmp == 0xDEADBEEF) 2461 break; 2462 DRM_UDELAY(1); 2463 } 2464 if (i >= adev->usec_timeout) { 2465 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", 2466 scratch, tmp); 2467 r = -EINVAL; 2468 } 2469 amdgpu_gfx_scratch_free(adev, scratch); 2470 2471 return r; 2472 } 2473 2474 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2475 { 2476 struct amdgpu_device *adev = ring->adev; 2477 struct v9_mqd *mqd = ring->mqd_ptr; 2478 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2479 uint32_t tmp; 2480 2481 mqd->header = 0xC0310800; 2482 mqd->compute_pipelinestat_enable = 0x00000001; 2483 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2484 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2485 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2486 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2487 mqd->compute_misc_reserved = 0x00000003; 2488 2489 mqd->dynamic_cu_mask_addr_lo = 2490 lower_32_bits(ring->mqd_gpu_addr 2491 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2492 mqd->dynamic_cu_mask_addr_hi = 2493 upper_32_bits(ring->mqd_gpu_addr 2494 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2495 2496 eop_base_addr = ring->eop_gpu_addr >> 8; 2497 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2498 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2499 2500 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2501 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2502 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2503 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2504 2505 mqd->cp_hqd_eop_control = tmp; 2506 2507 /* enable doorbell? */ 2508 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2509 2510 if (ring->use_doorbell) { 2511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2512 DOORBELL_OFFSET, ring->doorbell_index); 2513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2514 DOORBELL_EN, 1); 2515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2516 DOORBELL_SOURCE, 0); 2517 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2518 DOORBELL_HIT, 0); 2519 } else { 2520 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2521 DOORBELL_EN, 0); 2522 } 2523 2524 mqd->cp_hqd_pq_doorbell_control = tmp; 2525 2526 /* disable the queue if it's active */ 2527 ring->wptr = 0; 2528 mqd->cp_hqd_dequeue_request = 0; 2529 mqd->cp_hqd_pq_rptr = 0; 2530 mqd->cp_hqd_pq_wptr_lo = 0; 2531 mqd->cp_hqd_pq_wptr_hi = 0; 2532 2533 /* set the pointer to the MQD */ 2534 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2535 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2536 2537 /* set MQD vmid to 0 */ 2538 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2539 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2540 mqd->cp_mqd_control = tmp; 2541 2542 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2543 hqd_gpu_addr = ring->gpu_addr >> 8; 2544 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2545 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2546 2547 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2548 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2550 (order_base_2(ring->ring_size / 4) - 1)); 2551 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2552 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2553 #ifdef __BIG_ENDIAN 2554 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2555 #endif 2556 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2557 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2559 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2560 mqd->cp_hqd_pq_control = tmp; 2561 2562 /* set the wb address whether it's enabled or not */ 2563 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2564 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2565 mqd->cp_hqd_pq_rptr_report_addr_hi = 2566 upper_32_bits(wb_gpu_addr) & 0xffff; 2567 2568 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2569 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2570 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2571 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2572 2573 tmp = 0; 2574 /* enable the doorbell if requested */ 2575 if (ring->use_doorbell) { 2576 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2577 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2578 DOORBELL_OFFSET, ring->doorbell_index); 2579 2580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2581 DOORBELL_EN, 1); 2582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2583 DOORBELL_SOURCE, 0); 2584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2585 DOORBELL_HIT, 0); 2586 } 2587 2588 mqd->cp_hqd_pq_doorbell_control = tmp; 2589 2590 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2591 ring->wptr = 0; 2592 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2593 2594 /* set the vmid for the queue */ 2595 mqd->cp_hqd_vmid = 0; 2596 2597 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2598 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2599 mqd->cp_hqd_persistent_state = tmp; 2600 2601 /* set MIN_IB_AVAIL_SIZE */ 2602 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2603 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2604 mqd->cp_hqd_ib_control = tmp; 2605 2606 /* activate the queue */ 2607 mqd->cp_hqd_active = 1; 2608 2609 return 0; 2610 } 2611 2612 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2613 { 2614 struct amdgpu_device *adev = ring->adev; 2615 struct v9_mqd *mqd = ring->mqd_ptr; 2616 int j; 2617 2618 /* disable wptr polling */ 2619 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2620 2621 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2622 mqd->cp_hqd_eop_base_addr_lo); 2623 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2624 mqd->cp_hqd_eop_base_addr_hi); 2625 2626 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2627 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2628 mqd->cp_hqd_eop_control); 2629 2630 /* enable doorbell? */ 2631 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2632 mqd->cp_hqd_pq_doorbell_control); 2633 2634 /* disable the queue if it's active */ 2635 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2636 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2637 for (j = 0; j < adev->usec_timeout; j++) { 2638 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2639 break; 2640 udelay(1); 2641 } 2642 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2643 mqd->cp_hqd_dequeue_request); 2644 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 2645 mqd->cp_hqd_pq_rptr); 2646 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2647 mqd->cp_hqd_pq_wptr_lo); 2648 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2649 mqd->cp_hqd_pq_wptr_hi); 2650 } 2651 2652 /* set the pointer to the MQD */ 2653 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 2654 mqd->cp_mqd_base_addr_lo); 2655 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 2656 mqd->cp_mqd_base_addr_hi); 2657 2658 /* set MQD vmid to 0 */ 2659 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 2660 mqd->cp_mqd_control); 2661 2662 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2663 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 2664 mqd->cp_hqd_pq_base_lo); 2665 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 2666 mqd->cp_hqd_pq_base_hi); 2667 2668 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2669 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 2670 mqd->cp_hqd_pq_control); 2671 2672 /* set the wb address whether it's enabled or not */ 2673 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2674 mqd->cp_hqd_pq_rptr_report_addr_lo); 2675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2676 mqd->cp_hqd_pq_rptr_report_addr_hi); 2677 2678 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2679 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 2680 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2681 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2682 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2683 2684 /* enable the doorbell if requested */ 2685 if (ring->use_doorbell) { 2686 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 2687 (AMDGPU_DOORBELL64_KIQ *2) << 2); 2688 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 2689 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); 2690 } 2691 2692 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2693 mqd->cp_hqd_pq_doorbell_control); 2694 2695 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2696 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2697 mqd->cp_hqd_pq_wptr_lo); 2698 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2699 mqd->cp_hqd_pq_wptr_hi); 2700 2701 /* set the vmid for the queue */ 2702 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 2703 2704 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 2705 mqd->cp_hqd_persistent_state); 2706 2707 /* activate the queue */ 2708 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 2709 mqd->cp_hqd_active); 2710 2711 if (ring->use_doorbell) 2712 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2713 2714 return 0; 2715 } 2716 2717 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 2718 { 2719 struct amdgpu_device *adev = ring->adev; 2720 struct v9_mqd *mqd = ring->mqd_ptr; 2721 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2722 2723 gfx_v9_0_kiq_setting(ring); 2724 2725 if (adev->in_sriov_reset) { /* for GPU_RESET case */ 2726 /* reset MQD to a clean status */ 2727 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2728 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2729 2730 /* reset ring buffer */ 2731 ring->wptr = 0; 2732 amdgpu_ring_clear_ring(ring); 2733 2734 mutex_lock(&adev->srbm_mutex); 2735 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2736 gfx_v9_0_kiq_init_register(ring); 2737 soc15_grbm_select(adev, 0, 0, 0, 0); 2738 mutex_unlock(&adev->srbm_mutex); 2739 } else { 2740 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2741 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2742 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2743 mutex_lock(&adev->srbm_mutex); 2744 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2745 gfx_v9_0_mqd_init(ring); 2746 gfx_v9_0_kiq_init_register(ring); 2747 soc15_grbm_select(adev, 0, 0, 0, 0); 2748 mutex_unlock(&adev->srbm_mutex); 2749 2750 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2751 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2752 } 2753 2754 return 0; 2755 } 2756 2757 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 2758 { 2759 struct amdgpu_device *adev = ring->adev; 2760 struct v9_mqd *mqd = ring->mqd_ptr; 2761 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2762 2763 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { 2764 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2765 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2766 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2767 mutex_lock(&adev->srbm_mutex); 2768 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2769 gfx_v9_0_mqd_init(ring); 2770 soc15_grbm_select(adev, 0, 0, 0, 0); 2771 mutex_unlock(&adev->srbm_mutex); 2772 2773 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2774 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2775 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ 2776 /* reset MQD to a clean status */ 2777 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2778 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2779 2780 /* reset ring buffer */ 2781 ring->wptr = 0; 2782 amdgpu_ring_clear_ring(ring); 2783 } else { 2784 amdgpu_ring_clear_ring(ring); 2785 } 2786 2787 return 0; 2788 } 2789 2790 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 2791 { 2792 struct amdgpu_ring *ring = NULL; 2793 int r = 0, i; 2794 2795 gfx_v9_0_cp_compute_enable(adev, true); 2796 2797 ring = &adev->gfx.kiq.ring; 2798 2799 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2800 if (unlikely(r != 0)) 2801 goto done; 2802 2803 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2804 if (!r) { 2805 r = gfx_v9_0_kiq_init_queue(ring); 2806 amdgpu_bo_kunmap(ring->mqd_obj); 2807 ring->mqd_ptr = NULL; 2808 } 2809 amdgpu_bo_unreserve(ring->mqd_obj); 2810 if (r) 2811 goto done; 2812 2813 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2814 ring = &adev->gfx.compute_ring[i]; 2815 2816 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2817 if (unlikely(r != 0)) 2818 goto done; 2819 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2820 if (!r) { 2821 r = gfx_v9_0_kcq_init_queue(ring); 2822 amdgpu_bo_kunmap(ring->mqd_obj); 2823 ring->mqd_ptr = NULL; 2824 } 2825 amdgpu_bo_unreserve(ring->mqd_obj); 2826 if (r) 2827 goto done; 2828 } 2829 2830 r = gfx_v9_0_kiq_kcq_enable(adev); 2831 done: 2832 return r; 2833 } 2834 2835 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 2836 { 2837 int r, i; 2838 struct amdgpu_ring *ring; 2839 2840 if (!(adev->flags & AMD_IS_APU)) 2841 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2842 2843 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2844 /* legacy firmware loading */ 2845 r = gfx_v9_0_cp_gfx_load_microcode(adev); 2846 if (r) 2847 return r; 2848 2849 r = gfx_v9_0_cp_compute_load_microcode(adev); 2850 if (r) 2851 return r; 2852 } 2853 2854 r = gfx_v9_0_cp_gfx_resume(adev); 2855 if (r) 2856 return r; 2857 2858 r = gfx_v9_0_kiq_resume(adev); 2859 if (r) 2860 return r; 2861 2862 ring = &adev->gfx.gfx_ring[0]; 2863 r = amdgpu_ring_test_ring(ring); 2864 if (r) { 2865 ring->ready = false; 2866 return r; 2867 } 2868 2869 ring = &adev->gfx.kiq.ring; 2870 ring->ready = true; 2871 r = amdgpu_ring_test_ring(ring); 2872 if (r) 2873 ring->ready = false; 2874 2875 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2876 ring = &adev->gfx.compute_ring[i]; 2877 2878 ring->ready = true; 2879 r = amdgpu_ring_test_ring(ring); 2880 if (r) 2881 ring->ready = false; 2882 } 2883 2884 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2885 2886 return 0; 2887 } 2888 2889 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 2890 { 2891 gfx_v9_0_cp_gfx_enable(adev, enable); 2892 gfx_v9_0_cp_compute_enable(adev, enable); 2893 } 2894 2895 static int gfx_v9_0_hw_init(void *handle) 2896 { 2897 int r; 2898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2899 2900 gfx_v9_0_init_golden_registers(adev); 2901 2902 gfx_v9_0_gpu_init(adev); 2903 2904 r = gfx_v9_0_rlc_resume(adev); 2905 if (r) 2906 return r; 2907 2908 r = gfx_v9_0_cp_resume(adev); 2909 if (r) 2910 return r; 2911 2912 r = gfx_v9_0_ngg_en(adev); 2913 if (r) 2914 return r; 2915 2916 return r; 2917 } 2918 2919 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) 2920 { 2921 struct amdgpu_device *adev = kiq_ring->adev; 2922 uint32_t scratch, tmp = 0; 2923 int r, i; 2924 2925 r = amdgpu_gfx_scratch_get(adev, &scratch); 2926 if (r) { 2927 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2928 return r; 2929 } 2930 WREG32(scratch, 0xCAFEDEAD); 2931 2932 r = amdgpu_ring_alloc(kiq_ring, 10); 2933 if (r) { 2934 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2935 amdgpu_gfx_scratch_free(adev, scratch); 2936 return r; 2937 } 2938 2939 /* unmap queues */ 2940 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 2941 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2942 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 2943 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 2944 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 2945 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 2946 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 2947 amdgpu_ring_write(kiq_ring, 0); 2948 amdgpu_ring_write(kiq_ring, 0); 2949 amdgpu_ring_write(kiq_ring, 0); 2950 /* write to scratch for completion */ 2951 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2952 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2953 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2954 amdgpu_ring_commit(kiq_ring); 2955 2956 for (i = 0; i < adev->usec_timeout; i++) { 2957 tmp = RREG32(scratch); 2958 if (tmp == 0xDEADBEEF) 2959 break; 2960 DRM_UDELAY(1); 2961 } 2962 if (i >= adev->usec_timeout) { 2963 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); 2964 r = -EINVAL; 2965 } 2966 amdgpu_gfx_scratch_free(adev, scratch); 2967 return r; 2968 } 2969 2970 2971 static int gfx_v9_0_hw_fini(void *handle) 2972 { 2973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2974 int i; 2975 2976 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2977 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2978 2979 /* disable KCQ to avoid CPC touch memory not valid anymore */ 2980 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2981 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); 2982 2983 if (amdgpu_sriov_vf(adev)) { 2984 pr_debug("For SRIOV client, shouldn't do anything.\n"); 2985 return 0; 2986 } 2987 gfx_v9_0_cp_enable(adev, false); 2988 gfx_v9_0_rlc_stop(adev); 2989 2990 return 0; 2991 } 2992 2993 static int gfx_v9_0_suspend(void *handle) 2994 { 2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2996 2997 adev->gfx.in_suspend = true; 2998 return gfx_v9_0_hw_fini(adev); 2999 } 3000 3001 static int gfx_v9_0_resume(void *handle) 3002 { 3003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3004 int r; 3005 3006 r = gfx_v9_0_hw_init(adev); 3007 adev->gfx.in_suspend = false; 3008 return r; 3009 } 3010 3011 static bool gfx_v9_0_is_idle(void *handle) 3012 { 3013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3014 3015 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3016 GRBM_STATUS, GUI_ACTIVE)) 3017 return false; 3018 else 3019 return true; 3020 } 3021 3022 static int gfx_v9_0_wait_for_idle(void *handle) 3023 { 3024 unsigned i; 3025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3026 3027 for (i = 0; i < adev->usec_timeout; i++) { 3028 if (gfx_v9_0_is_idle(handle)) 3029 return 0; 3030 udelay(1); 3031 } 3032 return -ETIMEDOUT; 3033 } 3034 3035 static int gfx_v9_0_soft_reset(void *handle) 3036 { 3037 u32 grbm_soft_reset = 0; 3038 u32 tmp; 3039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3040 3041 /* GRBM_STATUS */ 3042 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3043 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3044 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3045 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3046 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3047 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3048 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3049 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3050 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3051 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3052 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3053 } 3054 3055 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3056 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3057 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3058 } 3059 3060 /* GRBM_STATUS2 */ 3061 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3062 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3063 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3064 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3065 3066 3067 if (grbm_soft_reset) { 3068 /* stop the rlc */ 3069 gfx_v9_0_rlc_stop(adev); 3070 3071 /* Disable GFX parsing/prefetching */ 3072 gfx_v9_0_cp_gfx_enable(adev, false); 3073 3074 /* Disable MEC parsing/prefetching */ 3075 gfx_v9_0_cp_compute_enable(adev, false); 3076 3077 if (grbm_soft_reset) { 3078 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3079 tmp |= grbm_soft_reset; 3080 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3081 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3082 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3083 3084 udelay(50); 3085 3086 tmp &= ~grbm_soft_reset; 3087 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3088 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3089 } 3090 3091 /* Wait a little for things to settle down */ 3092 udelay(50); 3093 } 3094 return 0; 3095 } 3096 3097 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3098 { 3099 uint64_t clock; 3100 3101 mutex_lock(&adev->gfx.gpu_clock_mutex); 3102 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3103 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3104 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3105 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3106 return clock; 3107 } 3108 3109 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3110 uint32_t vmid, 3111 uint32_t gds_base, uint32_t gds_size, 3112 uint32_t gws_base, uint32_t gws_size, 3113 uint32_t oa_base, uint32_t oa_size) 3114 { 3115 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 3116 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 3117 3118 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 3119 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 3120 3121 oa_base = oa_base >> AMDGPU_OA_SHIFT; 3122 oa_size = oa_size >> AMDGPU_OA_SHIFT; 3123 3124 /* GDS Base */ 3125 gfx_v9_0_write_data_to_reg(ring, 0, false, 3126 amdgpu_gds_reg_offset[vmid].mem_base, 3127 gds_base); 3128 3129 /* GDS Size */ 3130 gfx_v9_0_write_data_to_reg(ring, 0, false, 3131 amdgpu_gds_reg_offset[vmid].mem_size, 3132 gds_size); 3133 3134 /* GWS */ 3135 gfx_v9_0_write_data_to_reg(ring, 0, false, 3136 amdgpu_gds_reg_offset[vmid].gws, 3137 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3138 3139 /* OA */ 3140 gfx_v9_0_write_data_to_reg(ring, 0, false, 3141 amdgpu_gds_reg_offset[vmid].oa, 3142 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3143 } 3144 3145 static int gfx_v9_0_early_init(void *handle) 3146 { 3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3148 3149 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3150 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3151 gfx_v9_0_set_ring_funcs(adev); 3152 gfx_v9_0_set_irq_funcs(adev); 3153 gfx_v9_0_set_gds_init(adev); 3154 gfx_v9_0_set_rlc_funcs(adev); 3155 3156 return 0; 3157 } 3158 3159 static int gfx_v9_0_late_init(void *handle) 3160 { 3161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3162 int r; 3163 3164 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3165 if (r) 3166 return r; 3167 3168 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3169 if (r) 3170 return r; 3171 3172 return 0; 3173 } 3174 3175 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3176 { 3177 uint32_t rlc_setting, data; 3178 unsigned i; 3179 3180 if (adev->gfx.rlc.in_safe_mode) 3181 return; 3182 3183 /* if RLC is not enabled, do nothing */ 3184 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3185 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3186 return; 3187 3188 if (adev->cg_flags & 3189 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | 3190 AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3191 data = RLC_SAFE_MODE__CMD_MASK; 3192 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3193 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3194 3195 /* wait for RLC_SAFE_MODE */ 3196 for (i = 0; i < adev->usec_timeout; i++) { 3197 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3198 break; 3199 udelay(1); 3200 } 3201 adev->gfx.rlc.in_safe_mode = true; 3202 } 3203 } 3204 3205 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3206 { 3207 uint32_t rlc_setting, data; 3208 3209 if (!adev->gfx.rlc.in_safe_mode) 3210 return; 3211 3212 /* if RLC is not enabled, do nothing */ 3213 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3214 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3215 return; 3216 3217 if (adev->cg_flags & 3218 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 3219 /* 3220 * Try to exit safe mode only if it is already in safe 3221 * mode. 3222 */ 3223 data = RLC_SAFE_MODE__CMD_MASK; 3224 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3225 adev->gfx.rlc.in_safe_mode = false; 3226 } 3227 } 3228 3229 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3230 bool enable) 3231 { 3232 /* TODO: double check if we need to perform under safe mdoe */ 3233 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3234 3235 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3236 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3237 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3238 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3239 } else { 3240 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3241 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3242 } 3243 3244 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3245 } 3246 3247 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3248 bool enable) 3249 { 3250 /* TODO: double check if we need to perform under safe mode */ 3251 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3252 3253 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3254 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3255 else 3256 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3257 3258 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3259 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3260 else 3261 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3262 3263 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3264 } 3265 3266 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3267 bool enable) 3268 { 3269 uint32_t data, def; 3270 3271 /* It is disabled by HW by default */ 3272 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3273 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3274 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3275 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3276 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3277 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3278 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3279 3280 /* only for Vega10 & Raven1 */ 3281 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3282 3283 if (def != data) 3284 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3285 3286 /* MGLS is a global flag to control all MGLS in GFX */ 3287 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3288 /* 2 - RLC memory Light sleep */ 3289 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3290 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3291 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3292 if (def != data) 3293 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3294 } 3295 /* 3 - CP memory Light sleep */ 3296 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3297 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3298 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3299 if (def != data) 3300 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3301 } 3302 } 3303 } else { 3304 /* 1 - MGCG_OVERRIDE */ 3305 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3306 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3307 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3308 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3309 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3310 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3311 if (def != data) 3312 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3313 3314 /* 2 - disable MGLS in RLC */ 3315 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3316 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3317 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3318 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3319 } 3320 3321 /* 3 - disable MGLS in CP */ 3322 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3323 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3324 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3325 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3326 } 3327 } 3328 } 3329 3330 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3331 bool enable) 3332 { 3333 uint32_t data, def; 3334 3335 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3336 3337 /* Enable 3D CGCG/CGLS */ 3338 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3339 /* write cmd to clear cgcg/cgls ov */ 3340 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3341 /* unset CGCG override */ 3342 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3343 /* update CGCG and CGLS override bits */ 3344 if (def != data) 3345 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3346 /* enable 3Dcgcg FSM(0x0020003f) */ 3347 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3348 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3349 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3350 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3351 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3352 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3353 if (def != data) 3354 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3355 3356 /* set IDLE_POLL_COUNT(0x00900100) */ 3357 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3358 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3359 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3360 if (def != data) 3361 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3362 } else { 3363 /* Disable CGCG/CGLS */ 3364 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3365 /* disable cgcg, cgls should be disabled */ 3366 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3367 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3368 /* disable cgcg and cgls in FSM */ 3369 if (def != data) 3370 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3371 } 3372 3373 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3374 } 3375 3376 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3377 bool enable) 3378 { 3379 uint32_t def, data; 3380 3381 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3382 3383 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3384 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3385 /* unset CGCG override */ 3386 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3388 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3389 else 3390 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3391 /* update CGCG and CGLS override bits */ 3392 if (def != data) 3393 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3394 3395 /* enable cgcg FSM(0x0020003F) */ 3396 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3397 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3398 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3399 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3400 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3401 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3402 if (def != data) 3403 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3404 3405 /* set IDLE_POLL_COUNT(0x00900100) */ 3406 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3407 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3408 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3409 if (def != data) 3410 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3411 } else { 3412 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3413 /* reset CGCG/CGLS bits */ 3414 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3415 /* disable cgcg and cgls in FSM */ 3416 if (def != data) 3417 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3418 } 3419 3420 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3421 } 3422 3423 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3424 bool enable) 3425 { 3426 if (enable) { 3427 /* CGCG/CGLS should be enabled after MGCG/MGLS 3428 * === MGCG + MGLS === 3429 */ 3430 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3431 /* === CGCG /CGLS for GFX 3D Only === */ 3432 gfx_v9_0_update_3d_clock_gating(adev, enable); 3433 /* === CGCG + CGLS === */ 3434 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3435 } else { 3436 /* CGCG/CGLS should be disabled before MGCG/MGLS 3437 * === CGCG + CGLS === 3438 */ 3439 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3440 /* === CGCG /CGLS for GFX 3D Only === */ 3441 gfx_v9_0_update_3d_clock_gating(adev, enable); 3442 /* === MGCG + MGLS === */ 3443 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3444 } 3445 return 0; 3446 } 3447 3448 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3449 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3450 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 3451 }; 3452 3453 static int gfx_v9_0_set_powergating_state(void *handle, 3454 enum amd_powergating_state state) 3455 { 3456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3457 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3458 3459 switch (adev->asic_type) { 3460 case CHIP_RAVEN: 3461 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3462 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3463 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3464 } else { 3465 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3466 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3467 } 3468 3469 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3470 gfx_v9_0_enable_cp_power_gating(adev, true); 3471 else 3472 gfx_v9_0_enable_cp_power_gating(adev, false); 3473 3474 /* update gfx cgpg state */ 3475 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3476 3477 /* update mgcg state */ 3478 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3479 break; 3480 default: 3481 break; 3482 } 3483 3484 return 0; 3485 } 3486 3487 static int gfx_v9_0_set_clockgating_state(void *handle, 3488 enum amd_clockgating_state state) 3489 { 3490 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3491 3492 if (amdgpu_sriov_vf(adev)) 3493 return 0; 3494 3495 switch (adev->asic_type) { 3496 case CHIP_VEGA10: 3497 case CHIP_RAVEN: 3498 gfx_v9_0_update_gfx_clock_gating(adev, 3499 state == AMD_CG_STATE_GATE ? true : false); 3500 break; 3501 default: 3502 break; 3503 } 3504 return 0; 3505 } 3506 3507 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3508 { 3509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3510 int data; 3511 3512 if (amdgpu_sriov_vf(adev)) 3513 *flags = 0; 3514 3515 /* AMD_CG_SUPPORT_GFX_MGCG */ 3516 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3517 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3518 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3519 3520 /* AMD_CG_SUPPORT_GFX_CGCG */ 3521 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3522 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3523 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3524 3525 /* AMD_CG_SUPPORT_GFX_CGLS */ 3526 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3527 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3528 3529 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 3530 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3531 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 3532 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 3533 3534 /* AMD_CG_SUPPORT_GFX_CP_LS */ 3535 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3536 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 3537 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 3538 3539 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3540 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3541 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3542 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3543 3544 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3545 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3546 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3547 } 3548 3549 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3550 { 3551 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 3552 } 3553 3554 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3555 { 3556 struct amdgpu_device *adev = ring->adev; 3557 u64 wptr; 3558 3559 /* XXX check if swapping is necessary on BE */ 3560 if (ring->use_doorbell) { 3561 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3562 } else { 3563 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 3564 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 3565 } 3566 3567 return wptr; 3568 } 3569 3570 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3571 { 3572 struct amdgpu_device *adev = ring->adev; 3573 3574 if (ring->use_doorbell) { 3575 /* XXX check if swapping is necessary on BE */ 3576 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3577 WDOORBELL64(ring->doorbell_index, ring->wptr); 3578 } else { 3579 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3580 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3581 } 3582 } 3583 3584 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3585 { 3586 u32 ref_and_mask, reg_mem_engine; 3587 const struct nbio_hdp_flush_reg *nbio_hf_reg; 3588 3589 if (ring->adev->flags & AMD_IS_APU) 3590 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; 3591 else 3592 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 3593 3594 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3595 switch (ring->me) { 3596 case 1: 3597 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3598 break; 3599 case 2: 3600 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3601 break; 3602 default: 3603 return; 3604 } 3605 reg_mem_engine = 0; 3606 } else { 3607 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3608 reg_mem_engine = 1; /* pfp */ 3609 } 3610 3611 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3612 nbio_hf_reg->hdp_flush_req_offset, 3613 nbio_hf_reg->hdp_flush_done_offset, 3614 ref_and_mask, ref_and_mask, 0x20); 3615 } 3616 3617 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 3618 { 3619 gfx_v9_0_write_data_to_reg(ring, 0, true, 3620 SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 3621 } 3622 3623 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3624 struct amdgpu_ib *ib, 3625 unsigned vm_id, bool ctx_switch) 3626 { 3627 u32 header, control = 0; 3628 3629 if (ib->flags & AMDGPU_IB_FLAG_CE) 3630 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3631 else 3632 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3633 3634 control |= ib->length_dw | (vm_id << 24); 3635 3636 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3637 control |= INDIRECT_BUFFER_PRE_ENB(1); 3638 3639 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 3640 gfx_v9_0_ring_emit_de_meta(ring); 3641 } 3642 3643 amdgpu_ring_write(ring, header); 3644 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3645 amdgpu_ring_write(ring, 3646 #ifdef __BIG_ENDIAN 3647 (2 << 0) | 3648 #endif 3649 lower_32_bits(ib->gpu_addr)); 3650 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3651 amdgpu_ring_write(ring, control); 3652 } 3653 3654 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3655 struct amdgpu_ib *ib, 3656 unsigned vm_id, bool ctx_switch) 3657 { 3658 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 3659 3660 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3661 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3662 amdgpu_ring_write(ring, 3663 #ifdef __BIG_ENDIAN 3664 (2 << 0) | 3665 #endif 3666 lower_32_bits(ib->gpu_addr)); 3667 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3668 amdgpu_ring_write(ring, control); 3669 } 3670 3671 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3672 u64 seq, unsigned flags) 3673 { 3674 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3675 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3676 3677 /* RELEASE_MEM - flush caches, send int */ 3678 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3679 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3680 EOP_TC_ACTION_EN | 3681 EOP_TC_WB_ACTION_EN | 3682 EOP_TC_MD_ACTION_EN | 3683 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3684 EVENT_INDEX(5))); 3685 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3686 3687 /* 3688 * the address should be Qword aligned if 64bit write, Dword 3689 * aligned if only send 32bit data low (discard data high) 3690 */ 3691 if (write64bit) 3692 BUG_ON(addr & 0x7); 3693 else 3694 BUG_ON(addr & 0x3); 3695 amdgpu_ring_write(ring, lower_32_bits(addr)); 3696 amdgpu_ring_write(ring, upper_32_bits(addr)); 3697 amdgpu_ring_write(ring, lower_32_bits(seq)); 3698 amdgpu_ring_write(ring, upper_32_bits(seq)); 3699 amdgpu_ring_write(ring, 0); 3700 } 3701 3702 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3703 { 3704 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3705 uint32_t seq = ring->fence_drv.sync_seq; 3706 uint64_t addr = ring->fence_drv.gpu_addr; 3707 3708 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 3709 lower_32_bits(addr), upper_32_bits(addr), 3710 seq, 0xffffffff, 4); 3711 } 3712 3713 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3714 unsigned vm_id, uint64_t pd_addr) 3715 { 3716 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 3717 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3718 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 3719 unsigned eng = ring->vm_inv_eng; 3720 3721 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); 3722 pd_addr |= AMDGPU_PTE_VALID; 3723 3724 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3725 hub->ctx0_ptb_addr_lo32 + (2 * vm_id), 3726 lower_32_bits(pd_addr)); 3727 3728 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3729 hub->ctx0_ptb_addr_hi32 + (2 * vm_id), 3730 upper_32_bits(pd_addr)); 3731 3732 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3733 hub->vm_inv_eng0_req + eng, req); 3734 3735 /* wait for the invalidate to complete */ 3736 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + 3737 eng, 0, 1 << vm_id, 1 << vm_id, 0x20); 3738 3739 /* compute doesn't have PFP */ 3740 if (usepfp) { 3741 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3742 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3743 amdgpu_ring_write(ring, 0x0); 3744 } 3745 } 3746 3747 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3748 { 3749 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3750 } 3751 3752 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3753 { 3754 u64 wptr; 3755 3756 /* XXX check if swapping is necessary on BE */ 3757 if (ring->use_doorbell) 3758 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3759 else 3760 BUG(); 3761 return wptr; 3762 } 3763 3764 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 3765 { 3766 struct amdgpu_device *adev = ring->adev; 3767 3768 /* XXX check if swapping is necessary on BE */ 3769 if (ring->use_doorbell) { 3770 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3771 WDOORBELL64(ring->doorbell_index, ring->wptr); 3772 } else{ 3773 BUG(); /* only DOORBELL method supported on gfx9 now */ 3774 } 3775 } 3776 3777 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3778 u64 seq, unsigned int flags) 3779 { 3780 /* we only allocate 32bit for each seq wb address */ 3781 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 3782 3783 /* write fence seq to the "addr" */ 3784 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3785 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3786 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3787 amdgpu_ring_write(ring, lower_32_bits(addr)); 3788 amdgpu_ring_write(ring, upper_32_bits(addr)); 3789 amdgpu_ring_write(ring, lower_32_bits(seq)); 3790 3791 if (flags & AMDGPU_FENCE_FLAG_INT) { 3792 /* set register to trigger INT */ 3793 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3794 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3795 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3796 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 3797 amdgpu_ring_write(ring, 0); 3798 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3799 } 3800 } 3801 3802 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 3803 { 3804 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3805 amdgpu_ring_write(ring, 0); 3806 } 3807 3808 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 3809 { 3810 struct v9_ce_ib_state ce_payload = {0}; 3811 uint64_t csa_addr; 3812 int cnt; 3813 3814 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 3815 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3816 3817 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3818 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 3819 WRITE_DATA_DST_SEL(8) | 3820 WR_CONFIRM) | 3821 WRITE_DATA_CACHE_POLICY(0)); 3822 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3823 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3824 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 3825 } 3826 3827 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 3828 { 3829 struct v9_de_ib_state de_payload = {0}; 3830 uint64_t csa_addr, gds_addr; 3831 int cnt; 3832 3833 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3834 gds_addr = csa_addr + 4096; 3835 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 3836 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 3837 3838 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 3839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3840 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 3841 WRITE_DATA_DST_SEL(8) | 3842 WR_CONFIRM) | 3843 WRITE_DATA_CACHE_POLICY(0)); 3844 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3845 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3846 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 3847 } 3848 3849 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 3850 { 3851 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 3852 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 3853 } 3854 3855 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3856 { 3857 uint32_t dw2 = 0; 3858 3859 if (amdgpu_sriov_vf(ring->adev)) 3860 gfx_v9_0_ring_emit_ce_meta(ring); 3861 3862 gfx_v9_0_ring_emit_tmz(ring, true); 3863 3864 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3865 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3866 /* set load_global_config & load_global_uconfig */ 3867 dw2 |= 0x8001; 3868 /* set load_cs_sh_regs */ 3869 dw2 |= 0x01000000; 3870 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 3871 dw2 |= 0x10002; 3872 3873 /* set load_ce_ram if preamble presented */ 3874 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 3875 dw2 |= 0x10000000; 3876 } else { 3877 /* still load_ce_ram if this is the first time preamble presented 3878 * although there is no context switch happens. 3879 */ 3880 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 3881 dw2 |= 0x10000000; 3882 } 3883 3884 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3885 amdgpu_ring_write(ring, dw2); 3886 amdgpu_ring_write(ring, 0); 3887 } 3888 3889 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 3890 { 3891 unsigned ret; 3892 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 3893 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 3894 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 3895 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 3896 ret = ring->wptr & ring->buf_mask; 3897 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 3898 return ret; 3899 } 3900 3901 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 3902 { 3903 unsigned cur; 3904 BUG_ON(offset > ring->buf_mask); 3905 BUG_ON(ring->ring[offset] != 0x55aa55aa); 3906 3907 cur = (ring->wptr & ring->buf_mask) - 1; 3908 if (likely(cur > offset)) 3909 ring->ring[offset] = cur - offset; 3910 else 3911 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 3912 } 3913 3914 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 3915 { 3916 struct amdgpu_device *adev = ring->adev; 3917 3918 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3919 amdgpu_ring_write(ring, 0 | /* src: register*/ 3920 (5 << 8) | /* dst: memory */ 3921 (1 << 20)); /* write confirm */ 3922 amdgpu_ring_write(ring, reg); 3923 amdgpu_ring_write(ring, 0); 3924 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3925 adev->virt.reg_val_offs * 4)); 3926 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3927 adev->virt.reg_val_offs * 4)); 3928 } 3929 3930 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3931 uint32_t val) 3932 { 3933 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3934 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ 3935 amdgpu_ring_write(ring, reg); 3936 amdgpu_ring_write(ring, 0); 3937 amdgpu_ring_write(ring, val); 3938 } 3939 3940 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3941 enum amdgpu_interrupt_state state) 3942 { 3943 switch (state) { 3944 case AMDGPU_IRQ_STATE_DISABLE: 3945 case AMDGPU_IRQ_STATE_ENABLE: 3946 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 3947 TIME_STAMP_INT_ENABLE, 3948 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3949 break; 3950 default: 3951 break; 3952 } 3953 } 3954 3955 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3956 int me, int pipe, 3957 enum amdgpu_interrupt_state state) 3958 { 3959 u32 mec_int_cntl, mec_int_cntl_reg; 3960 3961 /* 3962 * amdgpu controls only the first MEC. That's why this function only 3963 * handles the setting of interrupts for this specific MEC. All other 3964 * pipes' interrupts are set by amdkfd. 3965 */ 3966 3967 if (me == 1) { 3968 switch (pipe) { 3969 case 0: 3970 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 3971 break; 3972 case 1: 3973 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 3974 break; 3975 case 2: 3976 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 3977 break; 3978 case 3: 3979 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 3980 break; 3981 default: 3982 DRM_DEBUG("invalid pipe %d\n", pipe); 3983 return; 3984 } 3985 } else { 3986 DRM_DEBUG("invalid me %d\n", me); 3987 return; 3988 } 3989 3990 switch (state) { 3991 case AMDGPU_IRQ_STATE_DISABLE: 3992 mec_int_cntl = RREG32(mec_int_cntl_reg); 3993 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3994 TIME_STAMP_INT_ENABLE, 0); 3995 WREG32(mec_int_cntl_reg, mec_int_cntl); 3996 break; 3997 case AMDGPU_IRQ_STATE_ENABLE: 3998 mec_int_cntl = RREG32(mec_int_cntl_reg); 3999 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4000 TIME_STAMP_INT_ENABLE, 1); 4001 WREG32(mec_int_cntl_reg, mec_int_cntl); 4002 break; 4003 default: 4004 break; 4005 } 4006 } 4007 4008 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4009 struct amdgpu_irq_src *source, 4010 unsigned type, 4011 enum amdgpu_interrupt_state state) 4012 { 4013 switch (state) { 4014 case AMDGPU_IRQ_STATE_DISABLE: 4015 case AMDGPU_IRQ_STATE_ENABLE: 4016 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4017 PRIV_REG_INT_ENABLE, 4018 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4019 break; 4020 default: 4021 break; 4022 } 4023 4024 return 0; 4025 } 4026 4027 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4028 struct amdgpu_irq_src *source, 4029 unsigned type, 4030 enum amdgpu_interrupt_state state) 4031 { 4032 switch (state) { 4033 case AMDGPU_IRQ_STATE_DISABLE: 4034 case AMDGPU_IRQ_STATE_ENABLE: 4035 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4036 PRIV_INSTR_INT_ENABLE, 4037 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4038 default: 4039 break; 4040 } 4041 4042 return 0; 4043 } 4044 4045 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4046 struct amdgpu_irq_src *src, 4047 unsigned type, 4048 enum amdgpu_interrupt_state state) 4049 { 4050 switch (type) { 4051 case AMDGPU_CP_IRQ_GFX_EOP: 4052 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4053 break; 4054 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4055 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4056 break; 4057 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4058 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4059 break; 4060 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4061 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4062 break; 4063 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4064 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4065 break; 4066 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4067 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4068 break; 4069 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4070 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4071 break; 4072 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4073 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4074 break; 4075 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4076 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4077 break; 4078 default: 4079 break; 4080 } 4081 return 0; 4082 } 4083 4084 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4085 struct amdgpu_irq_src *source, 4086 struct amdgpu_iv_entry *entry) 4087 { 4088 int i; 4089 u8 me_id, pipe_id, queue_id; 4090 struct amdgpu_ring *ring; 4091 4092 DRM_DEBUG("IH: CP EOP\n"); 4093 me_id = (entry->ring_id & 0x0c) >> 2; 4094 pipe_id = (entry->ring_id & 0x03) >> 0; 4095 queue_id = (entry->ring_id & 0x70) >> 4; 4096 4097 switch (me_id) { 4098 case 0: 4099 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4100 break; 4101 case 1: 4102 case 2: 4103 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4104 ring = &adev->gfx.compute_ring[i]; 4105 /* Per-queue interrupt is supported for MEC starting from VI. 4106 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4107 */ 4108 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4109 amdgpu_fence_process(ring); 4110 } 4111 break; 4112 } 4113 return 0; 4114 } 4115 4116 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4117 struct amdgpu_irq_src *source, 4118 struct amdgpu_iv_entry *entry) 4119 { 4120 DRM_ERROR("Illegal register access in command stream\n"); 4121 schedule_work(&adev->reset_work); 4122 return 0; 4123 } 4124 4125 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4126 struct amdgpu_irq_src *source, 4127 struct amdgpu_iv_entry *entry) 4128 { 4129 DRM_ERROR("Illegal instruction in command stream\n"); 4130 schedule_work(&adev->reset_work); 4131 return 0; 4132 } 4133 4134 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4135 struct amdgpu_irq_src *src, 4136 unsigned int type, 4137 enum amdgpu_interrupt_state state) 4138 { 4139 uint32_t tmp, target; 4140 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4141 4142 if (ring->me == 1) 4143 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4144 else 4145 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4146 target += ring->pipe; 4147 4148 switch (type) { 4149 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4150 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4151 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4152 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4153 GENERIC2_INT_ENABLE, 0); 4154 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4155 4156 tmp = RREG32(target); 4157 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4158 GENERIC2_INT_ENABLE, 0); 4159 WREG32(target, tmp); 4160 } else { 4161 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4162 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4163 GENERIC2_INT_ENABLE, 1); 4164 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4165 4166 tmp = RREG32(target); 4167 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4168 GENERIC2_INT_ENABLE, 1); 4169 WREG32(target, tmp); 4170 } 4171 break; 4172 default: 4173 BUG(); /* kiq only support GENERIC2_INT now */ 4174 break; 4175 } 4176 return 0; 4177 } 4178 4179 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, 4180 struct amdgpu_irq_src *source, 4181 struct amdgpu_iv_entry *entry) 4182 { 4183 u8 me_id, pipe_id, queue_id; 4184 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4185 4186 me_id = (entry->ring_id & 0x0c) >> 2; 4187 pipe_id = (entry->ring_id & 0x03) >> 0; 4188 queue_id = (entry->ring_id & 0x70) >> 4; 4189 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 4190 me_id, pipe_id, queue_id); 4191 4192 amdgpu_fence_process(ring); 4193 return 0; 4194 } 4195 4196 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4197 .name = "gfx_v9_0", 4198 .early_init = gfx_v9_0_early_init, 4199 .late_init = gfx_v9_0_late_init, 4200 .sw_init = gfx_v9_0_sw_init, 4201 .sw_fini = gfx_v9_0_sw_fini, 4202 .hw_init = gfx_v9_0_hw_init, 4203 .hw_fini = gfx_v9_0_hw_fini, 4204 .suspend = gfx_v9_0_suspend, 4205 .resume = gfx_v9_0_resume, 4206 .is_idle = gfx_v9_0_is_idle, 4207 .wait_for_idle = gfx_v9_0_wait_for_idle, 4208 .soft_reset = gfx_v9_0_soft_reset, 4209 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4210 .set_powergating_state = gfx_v9_0_set_powergating_state, 4211 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4212 }; 4213 4214 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4215 .type = AMDGPU_RING_TYPE_GFX, 4216 .align_mask = 0xff, 4217 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4218 .support_64bit_ptrs = true, 4219 .vmhub = AMDGPU_GFXHUB, 4220 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4221 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4222 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4223 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4224 5 + /* COND_EXEC */ 4225 7 + /* PIPELINE_SYNC */ 4226 24 + /* VM_FLUSH */ 4227 8 + /* FENCE for VM_FLUSH */ 4228 20 + /* GDS switch */ 4229 4 + /* double SWITCH_BUFFER, 4230 the first COND_EXEC jump to the place just 4231 prior to this double SWITCH_BUFFER */ 4232 5 + /* COND_EXEC */ 4233 7 + /* HDP_flush */ 4234 4 + /* VGT_flush */ 4235 14 + /* CE_META */ 4236 31 + /* DE_META */ 4237 3 + /* CNTX_CTRL */ 4238 5 + /* HDP_INVL */ 4239 8 + 8 + /* FENCE x2 */ 4240 2, /* SWITCH_BUFFER */ 4241 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4242 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4243 .emit_fence = gfx_v9_0_ring_emit_fence, 4244 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4245 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4246 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4247 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4248 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4249 .test_ring = gfx_v9_0_ring_test_ring, 4250 .test_ib = gfx_v9_0_ring_test_ib, 4251 .insert_nop = amdgpu_ring_insert_nop, 4252 .pad_ib = amdgpu_ring_generic_pad_ib, 4253 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4254 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4255 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4256 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4257 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4258 }; 4259 4260 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4261 .type = AMDGPU_RING_TYPE_COMPUTE, 4262 .align_mask = 0xff, 4263 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4264 .support_64bit_ptrs = true, 4265 .vmhub = AMDGPU_GFXHUB, 4266 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4267 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4268 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4269 .emit_frame_size = 4270 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4271 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4272 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4273 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4274 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4275 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4276 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4277 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4278 .emit_fence = gfx_v9_0_ring_emit_fence, 4279 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4280 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4281 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4282 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4283 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4284 .test_ring = gfx_v9_0_ring_test_ring, 4285 .test_ib = gfx_v9_0_ring_test_ib, 4286 .insert_nop = amdgpu_ring_insert_nop, 4287 .pad_ib = amdgpu_ring_generic_pad_ib, 4288 }; 4289 4290 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4291 .type = AMDGPU_RING_TYPE_KIQ, 4292 .align_mask = 0xff, 4293 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4294 .support_64bit_ptrs = true, 4295 .vmhub = AMDGPU_GFXHUB, 4296 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4297 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4298 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4299 .emit_frame_size = 4300 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4301 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4302 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4303 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4304 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4305 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4306 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4307 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4308 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4309 .test_ring = gfx_v9_0_ring_test_ring, 4310 .test_ib = gfx_v9_0_ring_test_ib, 4311 .insert_nop = amdgpu_ring_insert_nop, 4312 .pad_ib = amdgpu_ring_generic_pad_ib, 4313 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4314 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4315 }; 4316 4317 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4318 { 4319 int i; 4320 4321 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4322 4323 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4324 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4325 4326 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4327 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 4328 } 4329 4330 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { 4331 .set = gfx_v9_0_kiq_set_interrupt_state, 4332 .process = gfx_v9_0_kiq_irq, 4333 }; 4334 4335 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 4336 .set = gfx_v9_0_set_eop_interrupt_state, 4337 .process = gfx_v9_0_eop_irq, 4338 }; 4339 4340 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 4341 .set = gfx_v9_0_set_priv_reg_fault_state, 4342 .process = gfx_v9_0_priv_reg_irq, 4343 }; 4344 4345 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 4346 .set = gfx_v9_0_set_priv_inst_fault_state, 4347 .process = gfx_v9_0_priv_inst_irq, 4348 }; 4349 4350 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 4351 { 4352 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4353 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 4354 4355 adev->gfx.priv_reg_irq.num_types = 1; 4356 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 4357 4358 adev->gfx.priv_inst_irq.num_types = 1; 4359 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 4360 4361 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 4362 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; 4363 } 4364 4365 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 4366 { 4367 switch (adev->asic_type) { 4368 case CHIP_VEGA10: 4369 case CHIP_RAVEN: 4370 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4371 break; 4372 default: 4373 break; 4374 } 4375 } 4376 4377 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4378 { 4379 /* init asci gds info */ 4380 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4381 adev->gds.gws.total_size = 64; 4382 adev->gds.oa.total_size = 16; 4383 4384 if (adev->gds.mem.total_size == 64 * 1024) { 4385 adev->gds.mem.gfx_partition_size = 4096; 4386 adev->gds.mem.cs_partition_size = 4096; 4387 4388 adev->gds.gws.gfx_partition_size = 4; 4389 adev->gds.gws.cs_partition_size = 4; 4390 4391 adev->gds.oa.gfx_partition_size = 4; 4392 adev->gds.oa.cs_partition_size = 1; 4393 } else { 4394 adev->gds.mem.gfx_partition_size = 1024; 4395 adev->gds.mem.cs_partition_size = 1024; 4396 4397 adev->gds.gws.gfx_partition_size = 16; 4398 adev->gds.gws.cs_partition_size = 16; 4399 4400 adev->gds.oa.gfx_partition_size = 4; 4401 adev->gds.oa.cs_partition_size = 4; 4402 } 4403 } 4404 4405 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4406 u32 bitmap) 4407 { 4408 u32 data; 4409 4410 if (!bitmap) 4411 return; 4412 4413 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4414 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4415 4416 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 4417 } 4418 4419 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4420 { 4421 u32 data, mask; 4422 4423 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 4424 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 4425 4426 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4427 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4428 4429 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4430 4431 return (~data) & mask; 4432 } 4433 4434 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 4435 struct amdgpu_cu_info *cu_info) 4436 { 4437 int i, j, k, counter, active_cu_number = 0; 4438 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4439 unsigned disable_masks[4 * 2]; 4440 4441 if (!adev || !cu_info) 4442 return -EINVAL; 4443 4444 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 4445 4446 mutex_lock(&adev->grbm_idx_mutex); 4447 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4448 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4449 mask = 1; 4450 ao_bitmap = 0; 4451 counter = 0; 4452 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4453 if (i < 4 && j < 2) 4454 gfx_v9_0_set_user_cu_inactive_bitmap( 4455 adev, disable_masks[i * 2 + j]); 4456 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4457 cu_info->bitmap[i][j] = bitmap; 4458 4459 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4460 if (bitmap & mask) { 4461 if (counter < adev->gfx.config.max_cu_per_sh) 4462 ao_bitmap |= mask; 4463 counter ++; 4464 } 4465 mask <<= 1; 4466 } 4467 active_cu_number += counter; 4468 if (i < 2 && j < 2) 4469 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4470 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4471 } 4472 } 4473 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4474 mutex_unlock(&adev->grbm_idx_mutex); 4475 4476 cu_info->number = active_cu_number; 4477 cu_info->ao_cu_mask = ao_cu_mask; 4478 4479 return 0; 4480 } 4481 4482 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4483 { 4484 .type = AMD_IP_BLOCK_TYPE_GFX, 4485 .major = 9, 4486 .minor = 0, 4487 .rev = 0, 4488 .funcs = &gfx_v9_0_ip_funcs, 4489 }; 4490