1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "amdgpu_ring_mux.h" 51 #include "gfx_v9_4.h" 52 #include "gfx_v9_0.h" 53 #include "gfx_v9_4_2.h" 54 55 #include "asic_reg/pwr/pwr_10_0_offset.h" 56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 57 #include "asic_reg/gc/gc_9_0_default.h" 58 59 #define GFX9_NUM_GFX_RINGS 1 60 #define GFX9_NUM_SW_GFX_RINGS 2 61 #define GFX9_MEC_HPD_SIZE 4096 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 114 115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 127 128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 133 134 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 144 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 146 147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 151 152 static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = { 153 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 155 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 156 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 157 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 158 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 159 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 160 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 161 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 162 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 163 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 164 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 165 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 166 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 167 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 168 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 169 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 170 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 171 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 173 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 174 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 175 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 176 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 177 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 178 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 179 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 180 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 183 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 184 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 185 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 186 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 187 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 188 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 189 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 190 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 191 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 192 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 193 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 194 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 195 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 196 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 197 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 198 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_CNTL), 199 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 200 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 201 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 202 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL1_STATUS), 203 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS), 204 SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS), 205 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL1_STATUS), 206 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 207 SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), 208 SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS), 209 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 210 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 211 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 212 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 213 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 214 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 215 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 216 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 217 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 218 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 219 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 220 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 221 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 222 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 223 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 224 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 225 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 226 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 227 /* cp header registers */ 228 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 229 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 230 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 231 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 232 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 233 /* SE status registers */ 234 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 235 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 236 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 237 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 238 }; 239 240 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = { 241 /* compute queue registers */ 242 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 243 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE), 244 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 245 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 246 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 247 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 248 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 249 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 250 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 251 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 252 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 253 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 254 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 255 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 256 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 257 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 258 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 259 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 260 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 261 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 262 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 263 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 264 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 265 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 266 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 267 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 268 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 269 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 270 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 271 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 272 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 273 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 274 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 275 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 276 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 277 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 278 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS), 279 }; 280 281 enum ta_ras_gfx_subblock { 282 /*CPC*/ 283 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 284 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 285 TA_RAS_BLOCK__GFX_CPC_UCODE, 286 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 287 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 288 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 289 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 290 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 291 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 292 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 293 /* CPF*/ 294 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 295 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 296 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 297 TA_RAS_BLOCK__GFX_CPF_TAG, 298 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 299 /* CPG*/ 300 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 301 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 302 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 303 TA_RAS_BLOCK__GFX_CPG_TAG, 304 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 305 /* GDS*/ 306 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 307 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 308 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 309 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 310 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 311 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 312 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 313 /* SPI*/ 314 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 315 /* SQ*/ 316 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 317 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 318 TA_RAS_BLOCK__GFX_SQ_LDS_D, 319 TA_RAS_BLOCK__GFX_SQ_LDS_I, 320 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 321 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 322 /* SQC (3 ranges)*/ 323 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 324 /* SQC range 0*/ 325 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 326 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 327 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 328 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 329 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 330 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 331 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 332 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 333 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 334 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 335 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 336 /* SQC range 1*/ 337 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 338 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 339 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 340 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 341 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 342 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 343 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 344 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 345 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 346 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 347 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 348 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 349 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 350 /* SQC range 2*/ 351 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 352 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 353 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 354 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 355 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 356 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 357 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 358 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 359 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 360 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 361 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 362 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 363 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 364 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 365 /* TA*/ 366 TA_RAS_BLOCK__GFX_TA_INDEX_START, 367 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 368 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 369 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 370 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 371 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 372 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 373 /* TCA*/ 374 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 375 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 376 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 377 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 378 /* TCC (5 sub-ranges)*/ 379 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 380 /* TCC range 0*/ 381 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 382 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 383 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 384 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 385 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 386 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 387 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 388 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 389 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 390 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 391 /* TCC range 1*/ 392 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 393 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 394 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 395 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 396 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 397 /* TCC range 2*/ 398 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 399 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 400 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 401 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 402 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 403 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 404 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 405 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 406 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 407 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 408 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 409 /* TCC range 3*/ 410 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 411 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 412 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 413 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 414 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 415 /* TCC range 4*/ 416 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 417 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 418 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 419 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 420 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 421 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 422 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 423 /* TCI*/ 424 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 425 /* TCP*/ 426 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 427 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 428 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 429 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 430 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 431 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 432 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 433 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 434 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 435 /* TD*/ 436 TA_RAS_BLOCK__GFX_TD_INDEX_START, 437 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 438 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 439 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 440 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 441 /* EA (3 sub-ranges)*/ 442 TA_RAS_BLOCK__GFX_EA_INDEX_START, 443 /* EA range 0*/ 444 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 445 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 446 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 447 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 448 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 449 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 450 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 451 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 452 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 453 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 454 /* EA range 1*/ 455 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 456 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 457 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 458 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 459 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 460 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 461 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 462 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 463 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 464 /* EA range 2*/ 465 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 466 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 467 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 468 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 469 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 470 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 471 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 472 /* UTC VM L2 bank*/ 473 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 474 /* UTC VM walker*/ 475 TA_RAS_BLOCK__UTC_VML2_WALKER, 476 /* UTC ATC L2 2MB cache*/ 477 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 478 /* UTC ATC L2 4KB cache*/ 479 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 480 TA_RAS_BLOCK__GFX_MAX 481 }; 482 483 struct ras_gfx_subblock { 484 unsigned char *name; 485 int ta_subblock; 486 int hw_supported_error_type; 487 int sw_supported_error_type; 488 }; 489 490 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 491 [AMDGPU_RAS_BLOCK__##subblock] = { \ 492 #subblock, \ 493 TA_RAS_BLOCK__##subblock, \ 494 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 495 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 496 } 497 498 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 499 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 500 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 501 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 502 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 505 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 510 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 511 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 512 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 513 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 515 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 516 0), 517 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 518 0), 519 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 520 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 521 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 522 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 523 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 524 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 525 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 526 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 527 0, 0), 528 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 529 0), 530 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 531 0, 0), 532 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 533 0), 534 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 535 0, 0), 536 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 537 0), 538 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 539 1), 540 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 541 0, 0, 0), 542 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 543 0), 544 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 545 0), 546 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 547 0), 548 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 549 0), 550 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 551 0), 552 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 553 0, 0), 554 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 555 0), 556 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 557 0), 558 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 559 0, 0, 0), 560 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 561 0), 562 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 563 0), 564 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 565 0), 566 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 567 0), 568 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 569 0), 570 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 571 0, 0), 572 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 573 0), 574 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 575 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 576 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 577 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 578 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 579 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 580 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 581 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 582 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 583 1), 584 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 585 1), 586 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 587 1), 588 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 589 0), 590 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 591 0), 592 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 593 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 594 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 595 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 596 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 597 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 598 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 599 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 600 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 601 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 602 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 603 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 604 0), 605 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 606 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 607 0), 608 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 609 0, 0), 610 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 611 0), 612 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 613 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 614 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 615 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 616 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 617 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 618 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 619 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 620 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 621 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 622 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 623 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 624 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 625 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 626 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 627 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 628 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 629 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 630 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 631 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 632 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 633 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 634 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 635 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 636 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 637 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 638 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 639 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 640 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 641 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 642 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 643 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 644 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 645 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 646 }; 647 648 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 649 { 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 670 }; 671 672 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 673 { 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 692 }; 693 694 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 695 { 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 707 }; 708 709 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 710 { 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 735 }; 736 737 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 738 { 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 746 }; 747 748 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 749 { 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 769 }; 770 771 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 772 { 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 785 }; 786 787 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 788 { 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 792 }; 793 794 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 795 { 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 812 }; 813 814 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 815 { 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 829 }; 830 831 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 832 { 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 844 }; 845 846 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 847 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 848 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 849 }; 850 851 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 852 { 853 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 854 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 855 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 856 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 857 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 858 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 859 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 860 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 861 }; 862 863 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 864 { 865 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 866 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 867 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 868 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 869 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 870 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 871 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 872 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 873 }; 874 875 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 876 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 877 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 878 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 879 880 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 881 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 882 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 883 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 884 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 885 struct amdgpu_cu_info *cu_info); 886 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 887 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds); 888 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 889 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 890 void *ras_error_status); 891 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 892 void *inject_if, uint32_t instance_mask); 893 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 894 static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, 895 unsigned int vmid); 896 897 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 898 uint64_t queue_mask) 899 { 900 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 901 amdgpu_ring_write(kiq_ring, 902 PACKET3_SET_RESOURCES_VMID_MASK(0) | 903 /* vmid_mask:0* queue_type:0 (KIQ) */ 904 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 905 amdgpu_ring_write(kiq_ring, 906 lower_32_bits(queue_mask)); /* queue mask lo */ 907 amdgpu_ring_write(kiq_ring, 908 upper_32_bits(queue_mask)); /* queue mask hi */ 909 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 910 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 911 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 912 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 913 } 914 915 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 916 struct amdgpu_ring *ring) 917 { 918 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 919 uint64_t wptr_addr = ring->wptr_gpu_addr; 920 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 921 922 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 923 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 924 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 925 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 926 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 927 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 928 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 929 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 930 /*queue_type: normal compute queue */ 931 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 932 /* alloc format: all_on_one_pipe */ 933 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 934 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 935 /* num_queues: must be 1 */ 936 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 937 amdgpu_ring_write(kiq_ring, 938 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 939 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 940 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 941 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 942 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 943 } 944 945 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 946 struct amdgpu_ring *ring, 947 enum amdgpu_unmap_queues_action action, 948 u64 gpu_addr, u64 seq) 949 { 950 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 951 952 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 953 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 954 PACKET3_UNMAP_QUEUES_ACTION(action) | 955 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 956 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 957 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 958 amdgpu_ring_write(kiq_ring, 959 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 960 961 if (action == PREEMPT_QUEUES_NO_UNMAP) { 962 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 963 amdgpu_ring_write(kiq_ring, 0); 964 amdgpu_ring_write(kiq_ring, 0); 965 966 } else { 967 amdgpu_ring_write(kiq_ring, 0); 968 amdgpu_ring_write(kiq_ring, 0); 969 amdgpu_ring_write(kiq_ring, 0); 970 } 971 } 972 973 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 974 struct amdgpu_ring *ring, 975 u64 addr, 976 u64 seq) 977 { 978 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 979 980 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 981 amdgpu_ring_write(kiq_ring, 982 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 983 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 984 PACKET3_QUERY_STATUS_COMMAND(2)); 985 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 986 amdgpu_ring_write(kiq_ring, 987 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 988 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 989 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 990 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 991 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 992 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 993 } 994 995 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 996 uint16_t pasid, uint32_t flush_type, 997 bool all_hub) 998 { 999 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 1000 amdgpu_ring_write(kiq_ring, 1001 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 1002 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 1003 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 1004 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 1005 } 1006 1007 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 1008 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 1009 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 1010 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 1011 .kiq_query_status = gfx_v9_0_kiq_query_status, 1012 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 1013 .set_resources_size = 8, 1014 .map_queues_size = 7, 1015 .unmap_queues_size = 6, 1016 .query_status_size = 7, 1017 .invalidate_tlbs_size = 2, 1018 }; 1019 1020 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 1021 { 1022 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; 1023 } 1024 1025 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 1026 { 1027 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1028 case IP_VERSION(9, 0, 1): 1029 soc15_program_register_sequence(adev, 1030 golden_settings_gc_9_0, 1031 ARRAY_SIZE(golden_settings_gc_9_0)); 1032 soc15_program_register_sequence(adev, 1033 golden_settings_gc_9_0_vg10, 1034 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 1035 break; 1036 case IP_VERSION(9, 2, 1): 1037 soc15_program_register_sequence(adev, 1038 golden_settings_gc_9_2_1, 1039 ARRAY_SIZE(golden_settings_gc_9_2_1)); 1040 soc15_program_register_sequence(adev, 1041 golden_settings_gc_9_2_1_vg12, 1042 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 1043 break; 1044 case IP_VERSION(9, 4, 0): 1045 soc15_program_register_sequence(adev, 1046 golden_settings_gc_9_0, 1047 ARRAY_SIZE(golden_settings_gc_9_0)); 1048 soc15_program_register_sequence(adev, 1049 golden_settings_gc_9_0_vg20, 1050 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 1051 break; 1052 case IP_VERSION(9, 4, 1): 1053 soc15_program_register_sequence(adev, 1054 golden_settings_gc_9_4_1_arct, 1055 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 1056 break; 1057 case IP_VERSION(9, 2, 2): 1058 case IP_VERSION(9, 1, 0): 1059 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 1060 ARRAY_SIZE(golden_settings_gc_9_1)); 1061 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1062 soc15_program_register_sequence(adev, 1063 golden_settings_gc_9_1_rv2, 1064 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 1065 else 1066 soc15_program_register_sequence(adev, 1067 golden_settings_gc_9_1_rv1, 1068 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 1069 break; 1070 case IP_VERSION(9, 3, 0): 1071 soc15_program_register_sequence(adev, 1072 golden_settings_gc_9_1_rn, 1073 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 1074 return; /* for renoir, don't need common goldensetting */ 1075 case IP_VERSION(9, 4, 2): 1076 gfx_v9_4_2_init_golden_registers(adev, 1077 adev->smuio.funcs->get_die_id(adev)); 1078 break; 1079 default: 1080 break; 1081 } 1082 1083 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && 1084 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2))) 1085 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 1086 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 1087 } 1088 1089 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 1090 bool wc, uint32_t reg, uint32_t val) 1091 { 1092 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1093 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 1094 WRITE_DATA_DST_SEL(0) | 1095 (wc ? WR_CONFIRM : 0)); 1096 amdgpu_ring_write(ring, reg); 1097 amdgpu_ring_write(ring, 0); 1098 amdgpu_ring_write(ring, val); 1099 } 1100 1101 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 1102 int mem_space, int opt, uint32_t addr0, 1103 uint32_t addr1, uint32_t ref, uint32_t mask, 1104 uint32_t inv) 1105 { 1106 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1107 amdgpu_ring_write(ring, 1108 /* memory (1) or register (0) */ 1109 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 1110 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 1111 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 1112 WAIT_REG_MEM_ENGINE(eng_sel))); 1113 1114 if (mem_space) 1115 BUG_ON(addr0 & 0x3); /* Dword align */ 1116 amdgpu_ring_write(ring, addr0); 1117 amdgpu_ring_write(ring, addr1); 1118 amdgpu_ring_write(ring, ref); 1119 amdgpu_ring_write(ring, mask); 1120 amdgpu_ring_write(ring, inv); /* poll interval */ 1121 } 1122 1123 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1124 { 1125 struct amdgpu_device *adev = ring->adev; 1126 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1127 uint32_t tmp = 0; 1128 unsigned i; 1129 int r; 1130 1131 WREG32(scratch, 0xCAFEDEAD); 1132 r = amdgpu_ring_alloc(ring, 3); 1133 if (r) 1134 return r; 1135 1136 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1137 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1138 amdgpu_ring_write(ring, 0xDEADBEEF); 1139 amdgpu_ring_commit(ring); 1140 1141 for (i = 0; i < adev->usec_timeout; i++) { 1142 tmp = RREG32(scratch); 1143 if (tmp == 0xDEADBEEF) 1144 break; 1145 udelay(1); 1146 } 1147 1148 if (i >= adev->usec_timeout) 1149 r = -ETIMEDOUT; 1150 return r; 1151 } 1152 1153 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1154 { 1155 struct amdgpu_device *adev = ring->adev; 1156 struct amdgpu_ib ib; 1157 struct dma_fence *f = NULL; 1158 1159 unsigned index; 1160 uint64_t gpu_addr; 1161 uint32_t tmp; 1162 long r; 1163 1164 r = amdgpu_device_wb_get(adev, &index); 1165 if (r) 1166 return r; 1167 1168 gpu_addr = adev->wb.gpu_addr + (index * 4); 1169 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1170 memset(&ib, 0, sizeof(ib)); 1171 1172 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 1173 if (r) 1174 goto err1; 1175 1176 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1177 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1178 ib.ptr[2] = lower_32_bits(gpu_addr); 1179 ib.ptr[3] = upper_32_bits(gpu_addr); 1180 ib.ptr[4] = 0xDEADBEEF; 1181 ib.length_dw = 5; 1182 1183 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1184 if (r) 1185 goto err2; 1186 1187 r = dma_fence_wait_timeout(f, false, timeout); 1188 if (r == 0) { 1189 r = -ETIMEDOUT; 1190 goto err2; 1191 } else if (r < 0) { 1192 goto err2; 1193 } 1194 1195 tmp = adev->wb.wb[index]; 1196 if (tmp == 0xDEADBEEF) 1197 r = 0; 1198 else 1199 r = -EINVAL; 1200 1201 err2: 1202 amdgpu_ib_free(adev, &ib, NULL); 1203 dma_fence_put(f); 1204 err1: 1205 amdgpu_device_wb_free(adev, index); 1206 return r; 1207 } 1208 1209 1210 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1211 { 1212 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1213 amdgpu_ucode_release(&adev->gfx.me_fw); 1214 amdgpu_ucode_release(&adev->gfx.ce_fw); 1215 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1216 amdgpu_ucode_release(&adev->gfx.mec_fw); 1217 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1218 1219 kfree(adev->gfx.rlc.register_list_format); 1220 } 1221 1222 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1223 { 1224 adev->gfx.me_fw_write_wait = false; 1225 adev->gfx.mec_fw_write_wait = false; 1226 1227 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && 1228 ((adev->gfx.mec_fw_version < 0x000001a5) || 1229 (adev->gfx.mec_feature_version < 46) || 1230 (adev->gfx.pfp_fw_version < 0x000000b7) || 1231 (adev->gfx.pfp_feature_version < 46))) 1232 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1233 1234 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1235 case IP_VERSION(9, 0, 1): 1236 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1237 (adev->gfx.me_feature_version >= 42) && 1238 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1239 (adev->gfx.pfp_feature_version >= 42)) 1240 adev->gfx.me_fw_write_wait = true; 1241 1242 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1243 (adev->gfx.mec_feature_version >= 42)) 1244 adev->gfx.mec_fw_write_wait = true; 1245 break; 1246 case IP_VERSION(9, 2, 1): 1247 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1248 (adev->gfx.me_feature_version >= 44) && 1249 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1250 (adev->gfx.pfp_feature_version >= 44)) 1251 adev->gfx.me_fw_write_wait = true; 1252 1253 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1254 (adev->gfx.mec_feature_version >= 44)) 1255 adev->gfx.mec_fw_write_wait = true; 1256 break; 1257 case IP_VERSION(9, 4, 0): 1258 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1259 (adev->gfx.me_feature_version >= 44) && 1260 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1261 (adev->gfx.pfp_feature_version >= 44)) 1262 adev->gfx.me_fw_write_wait = true; 1263 1264 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1265 (adev->gfx.mec_feature_version >= 44)) 1266 adev->gfx.mec_fw_write_wait = true; 1267 break; 1268 case IP_VERSION(9, 1, 0): 1269 case IP_VERSION(9, 2, 2): 1270 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1271 (adev->gfx.me_feature_version >= 42) && 1272 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1273 (adev->gfx.pfp_feature_version >= 42)) 1274 adev->gfx.me_fw_write_wait = true; 1275 1276 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1277 (adev->gfx.mec_feature_version >= 42)) 1278 adev->gfx.mec_fw_write_wait = true; 1279 break; 1280 default: 1281 adev->gfx.me_fw_write_wait = true; 1282 adev->gfx.mec_fw_write_wait = true; 1283 break; 1284 } 1285 } 1286 1287 struct amdgpu_gfxoff_quirk { 1288 u16 chip_vendor; 1289 u16 chip_device; 1290 u16 subsys_vendor; 1291 u16 subsys_device; 1292 u8 revision; 1293 }; 1294 1295 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1296 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1297 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1298 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1299 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1300 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1301 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1302 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1303 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1304 { 0, 0, 0, 0, 0 }, 1305 }; 1306 1307 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1308 { 1309 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1310 1311 while (p && p->chip_device != 0) { 1312 if (pdev->vendor == p->chip_vendor && 1313 pdev->device == p->chip_device && 1314 pdev->subsystem_vendor == p->subsys_vendor && 1315 pdev->subsystem_device == p->subsys_device && 1316 pdev->revision == p->revision) { 1317 return true; 1318 } 1319 ++p; 1320 } 1321 return false; 1322 } 1323 1324 static bool is_raven_kicker(struct amdgpu_device *adev) 1325 { 1326 if (adev->pm.fw_version >= 0x41e2b) 1327 return true; 1328 else 1329 return false; 1330 } 1331 1332 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1333 { 1334 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 3, 0)) && 1335 (adev->gfx.me_fw_version >= 0x000000a5) && 1336 (adev->gfx.me_feature_version >= 52)) 1337 return true; 1338 else 1339 return false; 1340 } 1341 1342 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1343 { 1344 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1345 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1346 1347 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1348 case IP_VERSION(9, 0, 1): 1349 case IP_VERSION(9, 2, 1): 1350 case IP_VERSION(9, 4, 0): 1351 break; 1352 case IP_VERSION(9, 2, 2): 1353 case IP_VERSION(9, 1, 0): 1354 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1355 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1356 ((!is_raven_kicker(adev) && 1357 adev->gfx.rlc_fw_version < 531) || 1358 (adev->gfx.rlc_feature_version < 1) || 1359 !adev->gfx.rlc.is_rlc_v2_1)) 1360 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1361 1362 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1363 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1364 AMD_PG_SUPPORT_CP | 1365 AMD_PG_SUPPORT_RLC_SMU_HS; 1366 break; 1367 case IP_VERSION(9, 3, 0): 1368 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1369 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1370 AMD_PG_SUPPORT_CP | 1371 AMD_PG_SUPPORT_RLC_SMU_HS; 1372 break; 1373 default: 1374 break; 1375 } 1376 } 1377 1378 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1379 char *chip_name) 1380 { 1381 int err; 1382 1383 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 1384 "amdgpu/%s_pfp.bin", chip_name); 1385 if (err) 1386 goto out; 1387 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1388 1389 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 1390 "amdgpu/%s_me.bin", chip_name); 1391 if (err) 1392 goto out; 1393 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1394 1395 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 1396 "amdgpu/%s_ce.bin", chip_name); 1397 if (err) 1398 goto out; 1399 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1400 1401 out: 1402 if (err) { 1403 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1404 amdgpu_ucode_release(&adev->gfx.me_fw); 1405 amdgpu_ucode_release(&adev->gfx.ce_fw); 1406 } 1407 return err; 1408 } 1409 1410 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1411 char *chip_name) 1412 { 1413 int err; 1414 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1415 uint16_t version_major; 1416 uint16_t version_minor; 1417 uint32_t smu_version; 1418 1419 /* 1420 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1421 * instead of picasso_rlc.bin. 1422 * Judgment method: 1423 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1424 * or revision >= 0xD8 && revision <= 0xDF 1425 * otherwise is PCO FP5 1426 */ 1427 if (!strcmp(chip_name, "picasso") && 1428 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1429 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1430 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 1431 "amdgpu/%s_rlc_am4.bin", chip_name); 1432 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1433 (smu_version >= 0x41e2b)) 1434 /** 1435 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1436 */ 1437 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 1438 "amdgpu/%s_kicker_rlc.bin", chip_name); 1439 else 1440 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 1441 "amdgpu/%s_rlc.bin", chip_name); 1442 if (err) 1443 goto out; 1444 1445 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1446 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1447 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1448 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1449 out: 1450 if (err) 1451 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1452 1453 return err; 1454 } 1455 1456 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1457 { 1458 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 1459 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1460 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 3, 0)) 1461 return false; 1462 1463 return true; 1464 } 1465 1466 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1467 char *chip_name) 1468 { 1469 int err; 1470 1471 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1472 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 1473 "amdgpu/%s_sjt_mec.bin", chip_name); 1474 else 1475 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 1476 "amdgpu/%s_mec.bin", chip_name); 1477 if (err) 1478 goto out; 1479 1480 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1481 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1482 1483 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1484 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1485 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 1486 "amdgpu/%s_sjt_mec2.bin", chip_name); 1487 else 1488 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 1489 "amdgpu/%s_mec2.bin", chip_name); 1490 if (!err) { 1491 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1492 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1493 } else { 1494 err = 0; 1495 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1496 } 1497 } else { 1498 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1499 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1500 } 1501 1502 gfx_v9_0_check_if_need_gfxoff(adev); 1503 gfx_v9_0_check_fw_write_wait(adev); 1504 1505 out: 1506 if (err) 1507 amdgpu_ucode_release(&adev->gfx.mec_fw); 1508 return err; 1509 } 1510 1511 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1512 { 1513 char ucode_prefix[30]; 1514 int r; 1515 1516 DRM_DEBUG("\n"); 1517 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 1518 1519 /* No CPG in Arcturus */ 1520 if (adev->gfx.num_gfx_rings) { 1521 r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); 1522 if (r) 1523 return r; 1524 } 1525 1526 r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); 1527 if (r) 1528 return r; 1529 1530 r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); 1531 if (r) 1532 return r; 1533 1534 return r; 1535 } 1536 1537 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1538 { 1539 u32 count = 0; 1540 const struct cs_section_def *sect = NULL; 1541 const struct cs_extent_def *ext = NULL; 1542 1543 /* begin clear state */ 1544 count += 2; 1545 /* context control state */ 1546 count += 3; 1547 1548 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1549 for (ext = sect->section; ext->extent != NULL; ++ext) { 1550 if (sect->id == SECT_CONTEXT) 1551 count += 2 + ext->reg_count; 1552 else 1553 return 0; 1554 } 1555 } 1556 1557 /* end clear state */ 1558 count += 2; 1559 /* clear state */ 1560 count += 2; 1561 1562 return count; 1563 } 1564 1565 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1566 volatile u32 *buffer) 1567 { 1568 u32 count = 0, i; 1569 const struct cs_section_def *sect = NULL; 1570 const struct cs_extent_def *ext = NULL; 1571 1572 if (adev->gfx.rlc.cs_data == NULL) 1573 return; 1574 if (buffer == NULL) 1575 return; 1576 1577 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1578 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1579 1580 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1581 buffer[count++] = cpu_to_le32(0x80000000); 1582 buffer[count++] = cpu_to_le32(0x80000000); 1583 1584 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1585 for (ext = sect->section; ext->extent != NULL; ++ext) { 1586 if (sect->id == SECT_CONTEXT) { 1587 buffer[count++] = 1588 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1589 buffer[count++] = cpu_to_le32(ext->reg_index - 1590 PACKET3_SET_CONTEXT_REG_START); 1591 for (i = 0; i < ext->reg_count; i++) 1592 buffer[count++] = cpu_to_le32(ext->extent[i]); 1593 } else { 1594 return; 1595 } 1596 } 1597 } 1598 1599 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1600 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1601 1602 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1603 buffer[count++] = cpu_to_le32(0); 1604 } 1605 1606 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1607 { 1608 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1609 uint32_t pg_always_on_cu_num = 2; 1610 uint32_t always_on_cu_num; 1611 uint32_t i, j, k; 1612 uint32_t mask, cu_bitmap, counter; 1613 1614 if (adev->flags & AMD_IS_APU) 1615 always_on_cu_num = 4; 1616 else if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 2, 1)) 1617 always_on_cu_num = 8; 1618 else 1619 always_on_cu_num = 12; 1620 1621 mutex_lock(&adev->grbm_idx_mutex); 1622 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1623 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1624 mask = 1; 1625 cu_bitmap = 0; 1626 counter = 0; 1627 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 1628 1629 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1630 if (cu_info->bitmap[0][i][j] & mask) { 1631 if (counter == pg_always_on_cu_num) 1632 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1633 if (counter < always_on_cu_num) 1634 cu_bitmap |= mask; 1635 else 1636 break; 1637 counter++; 1638 } 1639 mask <<= 1; 1640 } 1641 1642 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1643 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1644 } 1645 } 1646 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1647 mutex_unlock(&adev->grbm_idx_mutex); 1648 } 1649 1650 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1651 { 1652 uint32_t data; 1653 1654 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1655 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1656 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1657 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1658 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1659 1660 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1661 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1662 1663 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1664 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1665 1666 mutex_lock(&adev->grbm_idx_mutex); 1667 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1668 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1669 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1670 1671 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1672 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1673 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1674 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1675 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1676 1677 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1678 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1679 data &= 0x0000FFFF; 1680 data |= 0x00C00000; 1681 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1682 1683 /* 1684 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1685 * programmed in gfx_v9_0_init_always_on_cu_mask() 1686 */ 1687 1688 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1689 * but used for RLC_LB_CNTL configuration */ 1690 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1691 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1692 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1693 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1694 mutex_unlock(&adev->grbm_idx_mutex); 1695 1696 gfx_v9_0_init_always_on_cu_mask(adev); 1697 } 1698 1699 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1700 { 1701 uint32_t data; 1702 1703 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1704 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1705 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1706 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1707 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1708 1709 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1710 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1711 1712 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1713 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1714 1715 mutex_lock(&adev->grbm_idx_mutex); 1716 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1717 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1718 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1719 1720 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1721 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1722 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1723 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1724 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1725 1726 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1727 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1728 data &= 0x0000FFFF; 1729 data |= 0x00C00000; 1730 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1731 1732 /* 1733 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1734 * programmed in gfx_v9_0_init_always_on_cu_mask() 1735 */ 1736 1737 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1738 * but used for RLC_LB_CNTL configuration */ 1739 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1740 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1741 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1742 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1743 mutex_unlock(&adev->grbm_idx_mutex); 1744 1745 gfx_v9_0_init_always_on_cu_mask(adev); 1746 } 1747 1748 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1749 { 1750 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1751 } 1752 1753 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1754 { 1755 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1756 return 5; 1757 else 1758 return 4; 1759 } 1760 1761 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1762 { 1763 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1764 1765 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 1766 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1767 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1768 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1769 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1770 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1771 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1772 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1773 adev->gfx.rlc.rlcg_reg_access_supported = true; 1774 } 1775 1776 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1777 { 1778 const struct cs_section_def *cs_data; 1779 int r; 1780 1781 adev->gfx.rlc.cs_data = gfx9_cs_data; 1782 1783 cs_data = adev->gfx.rlc.cs_data; 1784 1785 if (cs_data) { 1786 /* init clear state block */ 1787 r = amdgpu_gfx_rlc_init_csb(adev); 1788 if (r) 1789 return r; 1790 } 1791 1792 if (adev->flags & AMD_IS_APU) { 1793 /* TODO: double check the cp_table_size for RV */ 1794 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1795 r = amdgpu_gfx_rlc_init_cpt(adev); 1796 if (r) 1797 return r; 1798 } 1799 1800 return 0; 1801 } 1802 1803 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1804 { 1805 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1806 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1807 } 1808 1809 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1810 { 1811 int r; 1812 u32 *hpd; 1813 const __le32 *fw_data; 1814 unsigned fw_size; 1815 u32 *fw; 1816 size_t mec_hpd_size; 1817 1818 const struct gfx_firmware_header_v1_0 *mec_hdr; 1819 1820 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1821 1822 /* take ownership of the relevant compute queues */ 1823 amdgpu_gfx_compute_queue_acquire(adev); 1824 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1825 if (mec_hpd_size) { 1826 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1827 AMDGPU_GEM_DOMAIN_VRAM | 1828 AMDGPU_GEM_DOMAIN_GTT, 1829 &adev->gfx.mec.hpd_eop_obj, 1830 &adev->gfx.mec.hpd_eop_gpu_addr, 1831 (void **)&hpd); 1832 if (r) { 1833 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1834 gfx_v9_0_mec_fini(adev); 1835 return r; 1836 } 1837 1838 memset(hpd, 0, mec_hpd_size); 1839 1840 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1841 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1842 } 1843 1844 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1845 1846 fw_data = (const __le32 *) 1847 (adev->gfx.mec_fw->data + 1848 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1849 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1850 1851 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1852 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1853 &adev->gfx.mec.mec_fw_obj, 1854 &adev->gfx.mec.mec_fw_gpu_addr, 1855 (void **)&fw); 1856 if (r) { 1857 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1858 gfx_v9_0_mec_fini(adev); 1859 return r; 1860 } 1861 1862 memcpy(fw, fw_data, fw_size); 1863 1864 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1865 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1866 1867 return 0; 1868 } 1869 1870 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1871 { 1872 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1873 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1874 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1875 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1876 (SQ_IND_INDEX__FORCE_READ_MASK)); 1877 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1878 } 1879 1880 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1881 uint32_t wave, uint32_t thread, 1882 uint32_t regno, uint32_t num, uint32_t *out) 1883 { 1884 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1885 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1886 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1887 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1888 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1889 (SQ_IND_INDEX__FORCE_READ_MASK) | 1890 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1891 while (num--) 1892 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1893 } 1894 1895 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1896 { 1897 /* type 1 wave data */ 1898 dst[(*no_fields)++] = 1; 1899 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1900 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1901 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1902 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1903 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1904 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1905 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1906 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1907 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1908 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1909 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1910 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1911 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1912 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1913 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1914 } 1915 1916 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1917 uint32_t wave, uint32_t start, 1918 uint32_t size, uint32_t *dst) 1919 { 1920 wave_read_regs( 1921 adev, simd, wave, 0, 1922 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1923 } 1924 1925 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1926 uint32_t wave, uint32_t thread, 1927 uint32_t start, uint32_t size, 1928 uint32_t *dst) 1929 { 1930 wave_read_regs( 1931 adev, simd, wave, thread, 1932 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1933 } 1934 1935 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1936 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1937 { 1938 soc15_grbm_select(adev, me, pipe, q, vm, 0); 1939 } 1940 1941 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1942 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1943 .select_se_sh = &gfx_v9_0_select_se_sh, 1944 .read_wave_data = &gfx_v9_0_read_wave_data, 1945 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1946 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1947 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1948 }; 1949 1950 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1951 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1952 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1953 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1954 }; 1955 1956 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1957 .ras_block = { 1958 .hw_ops = &gfx_v9_0_ras_ops, 1959 }, 1960 }; 1961 1962 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1963 { 1964 u32 gb_addr_config; 1965 int err; 1966 1967 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1968 case IP_VERSION(9, 0, 1): 1969 adev->gfx.config.max_hw_contexts = 8; 1970 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1971 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1972 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1973 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1974 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1975 break; 1976 case IP_VERSION(9, 2, 1): 1977 adev->gfx.config.max_hw_contexts = 8; 1978 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1979 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1980 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1981 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1982 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1983 DRM_INFO("fix gfx.config for vega12\n"); 1984 break; 1985 case IP_VERSION(9, 4, 0): 1986 adev->gfx.ras = &gfx_v9_0_ras; 1987 adev->gfx.config.max_hw_contexts = 8; 1988 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1989 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1990 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1991 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1992 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1993 gb_addr_config &= ~0xf3e777ff; 1994 gb_addr_config |= 0x22014042; 1995 /* check vbios table if gpu info is not available */ 1996 err = amdgpu_atomfirmware_get_gfx_info(adev); 1997 if (err) 1998 return err; 1999 break; 2000 case IP_VERSION(9, 2, 2): 2001 case IP_VERSION(9, 1, 0): 2002 adev->gfx.config.max_hw_contexts = 8; 2003 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2004 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2005 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2006 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2007 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 2008 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 2009 else 2010 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 2011 break; 2012 case IP_VERSION(9, 4, 1): 2013 adev->gfx.ras = &gfx_v9_4_ras; 2014 adev->gfx.config.max_hw_contexts = 8; 2015 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2016 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2017 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2018 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2019 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2020 gb_addr_config &= ~0xf3e777ff; 2021 gb_addr_config |= 0x22014042; 2022 break; 2023 case IP_VERSION(9, 3, 0): 2024 adev->gfx.config.max_hw_contexts = 8; 2025 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2026 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2027 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 2028 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2029 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2030 gb_addr_config &= ~0xf3e777ff; 2031 gb_addr_config |= 0x22010042; 2032 break; 2033 case IP_VERSION(9, 4, 2): 2034 adev->gfx.ras = &gfx_v9_4_2_ras; 2035 adev->gfx.config.max_hw_contexts = 8; 2036 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2037 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2038 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2039 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2040 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2041 gb_addr_config &= ~0xf3e777ff; 2042 gb_addr_config |= 0x22014042; 2043 /* check vbios table if gpu info is not available */ 2044 err = amdgpu_atomfirmware_get_gfx_info(adev); 2045 if (err) 2046 return err; 2047 break; 2048 default: 2049 BUG(); 2050 break; 2051 } 2052 2053 adev->gfx.config.gb_addr_config = gb_addr_config; 2054 2055 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2056 REG_GET_FIELD( 2057 adev->gfx.config.gb_addr_config, 2058 GB_ADDR_CONFIG, 2059 NUM_PIPES); 2060 2061 adev->gfx.config.max_tile_pipes = 2062 adev->gfx.config.gb_addr_config_fields.num_pipes; 2063 2064 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2065 REG_GET_FIELD( 2066 adev->gfx.config.gb_addr_config, 2067 GB_ADDR_CONFIG, 2068 NUM_BANKS); 2069 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2070 REG_GET_FIELD( 2071 adev->gfx.config.gb_addr_config, 2072 GB_ADDR_CONFIG, 2073 MAX_COMPRESSED_FRAGS); 2074 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2075 REG_GET_FIELD( 2076 adev->gfx.config.gb_addr_config, 2077 GB_ADDR_CONFIG, 2078 NUM_RB_PER_SE); 2079 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2080 REG_GET_FIELD( 2081 adev->gfx.config.gb_addr_config, 2082 GB_ADDR_CONFIG, 2083 NUM_SHADER_ENGINES); 2084 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2085 REG_GET_FIELD( 2086 adev->gfx.config.gb_addr_config, 2087 GB_ADDR_CONFIG, 2088 PIPE_INTERLEAVE_SIZE)); 2089 2090 return 0; 2091 } 2092 2093 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2094 int mec, int pipe, int queue) 2095 { 2096 unsigned irq_type; 2097 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2098 unsigned int hw_prio; 2099 2100 ring = &adev->gfx.compute_ring[ring_id]; 2101 2102 /* mec0 is me1 */ 2103 ring->me = mec + 1; 2104 ring->pipe = pipe; 2105 ring->queue = queue; 2106 2107 ring->ring_obj = NULL; 2108 ring->use_doorbell = true; 2109 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2110 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2111 + (ring_id * GFX9_MEC_HPD_SIZE); 2112 ring->vm_hub = AMDGPU_GFXHUB(0); 2113 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2114 2115 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2116 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2117 + ring->pipe; 2118 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2119 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2120 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2121 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2122 hw_prio, NULL); 2123 } 2124 2125 static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device *adev) 2126 { 2127 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9); 2128 uint32_t *ptr; 2129 uint32_t inst; 2130 2131 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 2132 if (ptr == NULL) { 2133 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 2134 adev->gfx.ip_dump_core = NULL; 2135 } else { 2136 adev->gfx.ip_dump_core = ptr; 2137 } 2138 2139 /* Allocate memory for compute queue registers for all the instances */ 2140 reg_count = ARRAY_SIZE(gc_cp_reg_list_9); 2141 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 2142 adev->gfx.mec.num_queue_per_pipe; 2143 2144 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 2145 if (ptr == NULL) { 2146 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 2147 adev->gfx.ip_dump_compute_queues = NULL; 2148 } else { 2149 adev->gfx.ip_dump_compute_queues = ptr; 2150 } 2151 } 2152 2153 static int gfx_v9_0_sw_init(void *handle) 2154 { 2155 int i, j, k, r, ring_id; 2156 int xcc_id = 0; 2157 struct amdgpu_ring *ring; 2158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2159 unsigned int hw_prio; 2160 2161 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2162 case IP_VERSION(9, 0, 1): 2163 case IP_VERSION(9, 2, 1): 2164 case IP_VERSION(9, 4, 0): 2165 case IP_VERSION(9, 2, 2): 2166 case IP_VERSION(9, 1, 0): 2167 case IP_VERSION(9, 4, 1): 2168 case IP_VERSION(9, 3, 0): 2169 case IP_VERSION(9, 4, 2): 2170 adev->gfx.mec.num_mec = 2; 2171 break; 2172 default: 2173 adev->gfx.mec.num_mec = 1; 2174 break; 2175 } 2176 2177 adev->gfx.mec.num_pipe_per_mec = 4; 2178 adev->gfx.mec.num_queue_per_pipe = 8; 2179 2180 /* EOP Event */ 2181 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2182 if (r) 2183 return r; 2184 2185 /* Bad opcode Event */ 2186 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 2187 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 2188 &adev->gfx.bad_op_irq); 2189 if (r) 2190 return r; 2191 2192 /* Privileged reg */ 2193 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2194 &adev->gfx.priv_reg_irq); 2195 if (r) 2196 return r; 2197 2198 /* Privileged inst */ 2199 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2200 &adev->gfx.priv_inst_irq); 2201 if (r) 2202 return r; 2203 2204 /* ECC error */ 2205 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2206 &adev->gfx.cp_ecc_error_irq); 2207 if (r) 2208 return r; 2209 2210 /* FUE error */ 2211 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2212 &adev->gfx.cp_ecc_error_irq); 2213 if (r) 2214 return r; 2215 2216 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2217 2218 if (adev->gfx.rlc.funcs) { 2219 if (adev->gfx.rlc.funcs->init) { 2220 r = adev->gfx.rlc.funcs->init(adev); 2221 if (r) { 2222 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2223 return r; 2224 } 2225 } 2226 } 2227 2228 r = gfx_v9_0_mec_init(adev); 2229 if (r) { 2230 DRM_ERROR("Failed to init MEC BOs!\n"); 2231 return r; 2232 } 2233 2234 /* set up the gfx ring */ 2235 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2236 ring = &adev->gfx.gfx_ring[i]; 2237 ring->ring_obj = NULL; 2238 if (!i) 2239 sprintf(ring->name, "gfx"); 2240 else 2241 sprintf(ring->name, "gfx_%d", i); 2242 ring->use_doorbell = true; 2243 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2244 2245 /* disable scheduler on the real ring */ 2246 ring->no_scheduler = adev->gfx.mcbp; 2247 ring->vm_hub = AMDGPU_GFXHUB(0); 2248 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2249 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2250 AMDGPU_RING_PRIO_DEFAULT, NULL); 2251 if (r) 2252 return r; 2253 } 2254 2255 /* set up the software rings */ 2256 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { 2257 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2258 ring = &adev->gfx.sw_gfx_ring[i]; 2259 ring->ring_obj = NULL; 2260 sprintf(ring->name, amdgpu_sw_ring_name(i)); 2261 ring->use_doorbell = true; 2262 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2263 ring->is_sw_ring = true; 2264 hw_prio = amdgpu_sw_ring_priority(i); 2265 ring->vm_hub = AMDGPU_GFXHUB(0); 2266 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2267 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, 2268 NULL); 2269 if (r) 2270 return r; 2271 ring->wptr = 0; 2272 } 2273 2274 /* init the muxer and add software rings */ 2275 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], 2276 GFX9_NUM_SW_GFX_RINGS); 2277 if (r) { 2278 DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); 2279 return r; 2280 } 2281 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2282 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, 2283 &adev->gfx.sw_gfx_ring[i]); 2284 if (r) { 2285 DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); 2286 return r; 2287 } 2288 } 2289 } 2290 2291 /* set up the compute queues - allocate horizontally across pipes */ 2292 ring_id = 0; 2293 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2294 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2295 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2296 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 2297 k, j)) 2298 continue; 2299 2300 r = gfx_v9_0_compute_ring_init(adev, 2301 ring_id, 2302 i, k, j); 2303 if (r) 2304 return r; 2305 2306 ring_id++; 2307 } 2308 } 2309 } 2310 2311 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); 2312 if (r) { 2313 DRM_ERROR("Failed to init KIQ BOs!\n"); 2314 return r; 2315 } 2316 2317 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 2318 if (r) 2319 return r; 2320 2321 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2322 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0); 2323 if (r) 2324 return r; 2325 2326 adev->gfx.ce_ram_size = 0x8000; 2327 2328 r = gfx_v9_0_gpu_early_init(adev); 2329 if (r) 2330 return r; 2331 2332 if (amdgpu_gfx_ras_sw_init(adev)) { 2333 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 2334 return -EINVAL; 2335 } 2336 2337 gfx_v9_0_alloc_ip_dump(adev); 2338 2339 return 0; 2340 } 2341 2342 2343 static int gfx_v9_0_sw_fini(void *handle) 2344 { 2345 int i; 2346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2347 2348 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { 2349 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 2350 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); 2351 amdgpu_ring_mux_fini(&adev->gfx.muxer); 2352 } 2353 2354 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2355 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2356 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2357 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2358 2359 amdgpu_gfx_mqd_sw_fini(adev, 0); 2360 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2361 amdgpu_gfx_kiq_fini(adev, 0); 2362 2363 gfx_v9_0_mec_fini(adev); 2364 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2365 &adev->gfx.rlc.clear_state_gpu_addr, 2366 (void **)&adev->gfx.rlc.cs_ptr); 2367 if (adev->flags & AMD_IS_APU) { 2368 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2369 &adev->gfx.rlc.cp_table_gpu_addr, 2370 (void **)&adev->gfx.rlc.cp_table_ptr); 2371 } 2372 gfx_v9_0_free_microcode(adev); 2373 2374 kfree(adev->gfx.ip_dump_core); 2375 kfree(adev->gfx.ip_dump_compute_queues); 2376 2377 return 0; 2378 } 2379 2380 2381 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2382 { 2383 /* TODO */ 2384 } 2385 2386 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2387 u32 instance, int xcc_id) 2388 { 2389 u32 data; 2390 2391 if (instance == 0xffffffff) 2392 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2393 else 2394 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2395 2396 if (se_num == 0xffffffff) 2397 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2398 else 2399 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2400 2401 if (sh_num == 0xffffffff) 2402 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2403 else 2404 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2405 2406 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2407 } 2408 2409 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2410 { 2411 u32 data, mask; 2412 2413 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2414 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2415 2416 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2417 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2418 2419 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2420 adev->gfx.config.max_sh_per_se); 2421 2422 return (~data) & mask; 2423 } 2424 2425 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2426 { 2427 int i, j; 2428 u32 data; 2429 u32 active_rbs = 0; 2430 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2431 adev->gfx.config.max_sh_per_se; 2432 2433 mutex_lock(&adev->grbm_idx_mutex); 2434 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2435 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2436 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2437 data = gfx_v9_0_get_rb_active_bitmap(adev); 2438 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2439 rb_bitmap_width_per_sh); 2440 } 2441 } 2442 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2443 mutex_unlock(&adev->grbm_idx_mutex); 2444 2445 adev->gfx.config.backend_enable_mask = active_rbs; 2446 adev->gfx.config.num_rbs = hweight32(active_rbs); 2447 } 2448 2449 static void gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev, 2450 uint32_t first_vmid, 2451 uint32_t last_vmid) 2452 { 2453 uint32_t data; 2454 uint32_t trap_config_vmid_mask = 0; 2455 int i; 2456 2457 /* Calculate trap config vmid mask */ 2458 for (i = first_vmid; i < last_vmid; i++) 2459 trap_config_vmid_mask |= (1 << i); 2460 2461 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 2462 VMID_SEL, trap_config_vmid_mask); 2463 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 2464 TRAP_EN, 1); 2465 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 2466 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 2467 2468 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 2469 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 2470 } 2471 2472 #define DEFAULT_SH_MEM_BASES (0x6000) 2473 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2474 { 2475 int i; 2476 uint32_t sh_mem_config; 2477 uint32_t sh_mem_bases; 2478 2479 /* 2480 * Configure apertures: 2481 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2482 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2483 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2484 */ 2485 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2486 2487 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2488 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2489 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2490 2491 mutex_lock(&adev->srbm_mutex); 2492 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2493 soc15_grbm_select(adev, 0, 0, 0, i, 0); 2494 /* CP and shaders */ 2495 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2496 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2497 } 2498 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2499 mutex_unlock(&adev->srbm_mutex); 2500 2501 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2502 access. These should be enabled by FW for target VMIDs. */ 2503 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2504 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2505 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2506 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2507 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2508 } 2509 } 2510 2511 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2512 { 2513 int vmid; 2514 2515 /* 2516 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2517 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2518 * the driver can enable them for graphics. VMID0 should maintain 2519 * access so that HWS firmware can save/restore entries. 2520 */ 2521 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2522 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2523 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2524 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2525 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2526 } 2527 } 2528 2529 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2530 { 2531 uint32_t tmp; 2532 2533 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2534 case IP_VERSION(9, 4, 1): 2535 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2536 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT, 2537 !READ_ONCE(adev->barrier_has_auto_waitcnt)); 2538 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2539 break; 2540 default: 2541 break; 2542 } 2543 } 2544 2545 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2546 { 2547 u32 tmp; 2548 int i; 2549 2550 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2551 2552 gfx_v9_0_tiling_mode_table_init(adev); 2553 2554 if (adev->gfx.num_gfx_rings) 2555 gfx_v9_0_setup_rb(adev); 2556 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2557 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2558 2559 /* XXX SH_MEM regs */ 2560 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2561 mutex_lock(&adev->srbm_mutex); 2562 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2563 soc15_grbm_select(adev, 0, 0, 0, i, 0); 2564 /* CP and shaders */ 2565 if (i == 0) { 2566 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2567 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2568 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2569 !!adev->gmc.noretry); 2570 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2571 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2572 } else { 2573 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2574 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2575 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2576 !!adev->gmc.noretry); 2577 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2578 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2579 (adev->gmc.private_aperture_start >> 48)); 2580 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2581 (adev->gmc.shared_aperture_start >> 48)); 2582 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2583 } 2584 } 2585 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2586 2587 mutex_unlock(&adev->srbm_mutex); 2588 2589 gfx_v9_0_init_compute_vmid(adev); 2590 gfx_v9_0_init_gds_vmid(adev); 2591 gfx_v9_0_init_sq_config(adev); 2592 } 2593 2594 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2595 { 2596 u32 i, j, k; 2597 u32 mask; 2598 2599 mutex_lock(&adev->grbm_idx_mutex); 2600 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2601 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2602 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2603 for (k = 0; k < adev->usec_timeout; k++) { 2604 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2605 break; 2606 udelay(1); 2607 } 2608 if (k == adev->usec_timeout) { 2609 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2610 0xffffffff, 0xffffffff, 0); 2611 mutex_unlock(&adev->grbm_idx_mutex); 2612 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2613 i, j); 2614 return; 2615 } 2616 } 2617 } 2618 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2619 mutex_unlock(&adev->grbm_idx_mutex); 2620 2621 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2622 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2623 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2624 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2625 for (k = 0; k < adev->usec_timeout; k++) { 2626 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2627 break; 2628 udelay(1); 2629 } 2630 } 2631 2632 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2633 bool enable) 2634 { 2635 u32 tmp; 2636 2637 /* These interrupts should be enabled to drive DS clock */ 2638 2639 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2640 2641 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2642 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2643 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2644 if (adev->gfx.num_gfx_rings) 2645 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2646 2647 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2648 } 2649 2650 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2651 { 2652 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2653 /* csib */ 2654 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2655 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2656 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2657 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2658 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2659 adev->gfx.rlc.clear_state_size); 2660 } 2661 2662 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2663 int indirect_offset, 2664 int list_size, 2665 int *unique_indirect_regs, 2666 int unique_indirect_reg_count, 2667 int *indirect_start_offsets, 2668 int *indirect_start_offsets_count, 2669 int max_start_offsets_count) 2670 { 2671 int idx; 2672 2673 for (; indirect_offset < list_size; indirect_offset++) { 2674 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2675 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2676 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2677 2678 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2679 indirect_offset += 2; 2680 2681 /* look for the matching indice */ 2682 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2683 if (unique_indirect_regs[idx] == 2684 register_list_format[indirect_offset] || 2685 !unique_indirect_regs[idx]) 2686 break; 2687 } 2688 2689 BUG_ON(idx >= unique_indirect_reg_count); 2690 2691 if (!unique_indirect_regs[idx]) 2692 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2693 2694 indirect_offset++; 2695 } 2696 } 2697 } 2698 2699 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2700 { 2701 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2702 int unique_indirect_reg_count = 0; 2703 2704 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2705 int indirect_start_offsets_count = 0; 2706 2707 int list_size = 0; 2708 int i = 0, j = 0; 2709 u32 tmp = 0; 2710 2711 u32 *register_list_format = 2712 kmemdup(adev->gfx.rlc.register_list_format, 2713 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2714 if (!register_list_format) 2715 return -ENOMEM; 2716 2717 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2718 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2719 gfx_v9_1_parse_ind_reg_list(register_list_format, 2720 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2721 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2722 unique_indirect_regs, 2723 unique_indirect_reg_count, 2724 indirect_start_offsets, 2725 &indirect_start_offsets_count, 2726 ARRAY_SIZE(indirect_start_offsets)); 2727 2728 /* enable auto inc in case it is disabled */ 2729 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2730 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2731 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2732 2733 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2734 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2735 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2736 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2737 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2738 adev->gfx.rlc.register_restore[i]); 2739 2740 /* load indirect register */ 2741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2742 adev->gfx.rlc.reg_list_format_start); 2743 2744 /* direct register portion */ 2745 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2746 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2747 register_list_format[i]); 2748 2749 /* indirect register portion */ 2750 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2751 if (register_list_format[i] == 0xFFFFFFFF) { 2752 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2753 continue; 2754 } 2755 2756 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2757 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2758 2759 for (j = 0; j < unique_indirect_reg_count; j++) { 2760 if (register_list_format[i] == unique_indirect_regs[j]) { 2761 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2762 break; 2763 } 2764 } 2765 2766 BUG_ON(j >= unique_indirect_reg_count); 2767 2768 i++; 2769 } 2770 2771 /* set save/restore list size */ 2772 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2773 list_size = list_size >> 1; 2774 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2775 adev->gfx.rlc.reg_restore_list_size); 2776 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2777 2778 /* write the starting offsets to RLC scratch ram */ 2779 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2780 adev->gfx.rlc.starting_offsets_start); 2781 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2782 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2783 indirect_start_offsets[i]); 2784 2785 /* load unique indirect regs*/ 2786 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2787 if (unique_indirect_regs[i] != 0) { 2788 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2789 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2790 unique_indirect_regs[i] & 0x3FFFF); 2791 2792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2793 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2794 unique_indirect_regs[i] >> 20); 2795 } 2796 } 2797 2798 kfree(register_list_format); 2799 return 0; 2800 } 2801 2802 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2803 { 2804 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2805 } 2806 2807 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2808 bool enable) 2809 { 2810 uint32_t data = 0; 2811 uint32_t default_data = 0; 2812 2813 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2814 if (enable) { 2815 /* enable GFXIP control over CGPG */ 2816 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2817 if(default_data != data) 2818 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2819 2820 /* update status */ 2821 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2822 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2823 if(default_data != data) 2824 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2825 } else { 2826 /* restore GFXIP control over GCPG */ 2827 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2828 if(default_data != data) 2829 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2830 } 2831 } 2832 2833 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2834 { 2835 uint32_t data = 0; 2836 2837 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2838 AMD_PG_SUPPORT_GFX_SMG | 2839 AMD_PG_SUPPORT_GFX_DMG)) { 2840 /* init IDLE_POLL_COUNT = 60 */ 2841 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2842 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2843 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2844 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2845 2846 /* init RLC PG Delay */ 2847 data = 0; 2848 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2849 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2850 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2851 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2853 2854 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2855 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2856 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2857 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2858 2859 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2860 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2861 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2862 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2863 2864 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2865 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2866 2867 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2868 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2869 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2870 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 3, 0)) 2871 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2872 } 2873 } 2874 2875 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2876 bool enable) 2877 { 2878 uint32_t data = 0; 2879 uint32_t default_data = 0; 2880 2881 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2882 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2883 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2884 enable ? 1 : 0); 2885 if (default_data != data) 2886 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2887 } 2888 2889 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2890 bool enable) 2891 { 2892 uint32_t data = 0; 2893 uint32_t default_data = 0; 2894 2895 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2896 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2897 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2898 enable ? 1 : 0); 2899 if(default_data != data) 2900 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2901 } 2902 2903 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2904 bool enable) 2905 { 2906 uint32_t data = 0; 2907 uint32_t default_data = 0; 2908 2909 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2910 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2911 CP_PG_DISABLE, 2912 enable ? 0 : 1); 2913 if(default_data != data) 2914 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2915 } 2916 2917 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2918 bool enable) 2919 { 2920 uint32_t data, default_data; 2921 2922 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2923 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2924 GFX_POWER_GATING_ENABLE, 2925 enable ? 1 : 0); 2926 if(default_data != data) 2927 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2928 } 2929 2930 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2931 bool enable) 2932 { 2933 uint32_t data, default_data; 2934 2935 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2936 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2937 GFX_PIPELINE_PG_ENABLE, 2938 enable ? 1 : 0); 2939 if(default_data != data) 2940 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2941 2942 if (!enable) 2943 /* read any GFX register to wake up GFX */ 2944 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2945 } 2946 2947 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2948 bool enable) 2949 { 2950 uint32_t data, default_data; 2951 2952 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2953 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2954 STATIC_PER_CU_PG_ENABLE, 2955 enable ? 1 : 0); 2956 if(default_data != data) 2957 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2958 } 2959 2960 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2961 bool enable) 2962 { 2963 uint32_t data, default_data; 2964 2965 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2966 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2967 DYN_PER_CU_PG_ENABLE, 2968 enable ? 1 : 0); 2969 if(default_data != data) 2970 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2971 } 2972 2973 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2974 { 2975 gfx_v9_0_init_csb(adev); 2976 2977 /* 2978 * Rlc save restore list is workable since v2_1. 2979 * And it's needed by gfxoff feature. 2980 */ 2981 if (adev->gfx.rlc.is_rlc_v2_1) { 2982 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2983 IP_VERSION(9, 2, 1) || 2984 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2985 gfx_v9_1_init_rlc_save_restore_list(adev); 2986 gfx_v9_0_enable_save_restore_machine(adev); 2987 } 2988 2989 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2990 AMD_PG_SUPPORT_GFX_SMG | 2991 AMD_PG_SUPPORT_GFX_DMG | 2992 AMD_PG_SUPPORT_CP | 2993 AMD_PG_SUPPORT_GDS | 2994 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2995 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2996 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2997 gfx_v9_0_init_gfx_power_gating(adev); 2998 } 2999 } 3000 3001 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 3002 { 3003 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 3004 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3005 gfx_v9_0_wait_for_rlc_serdes(adev); 3006 } 3007 3008 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 3009 { 3010 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3011 udelay(50); 3012 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 3013 udelay(50); 3014 } 3015 3016 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 3017 { 3018 #ifdef AMDGPU_RLC_DEBUG_RETRY 3019 u32 rlc_ucode_ver; 3020 #endif 3021 3022 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 3023 udelay(50); 3024 3025 /* carrizo do enable cp interrupt after cp inited */ 3026 if (!(adev->flags & AMD_IS_APU)) { 3027 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3028 udelay(50); 3029 } 3030 3031 #ifdef AMDGPU_RLC_DEBUG_RETRY 3032 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 3033 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 3034 if(rlc_ucode_ver == 0x108) { 3035 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 3036 rlc_ucode_ver, adev->gfx.rlc_fw_version); 3037 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 3038 * default is 0x9C4 to create a 100us interval */ 3039 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 3040 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 3041 * to disable the page fault retry interrupts, default is 3042 * 0x100 (256) */ 3043 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 3044 } 3045 #endif 3046 } 3047 3048 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 3049 { 3050 const struct rlc_firmware_header_v2_0 *hdr; 3051 const __le32 *fw_data; 3052 unsigned i, fw_size; 3053 3054 if (!adev->gfx.rlc_fw) 3055 return -EINVAL; 3056 3057 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3058 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3059 3060 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 3061 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3062 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3063 3064 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 3065 RLCG_UCODE_LOADING_START_ADDRESS); 3066 for (i = 0; i < fw_size; i++) 3067 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3068 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3069 3070 return 0; 3071 } 3072 3073 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 3074 { 3075 int r; 3076 3077 if (amdgpu_sriov_vf(adev)) { 3078 gfx_v9_0_init_csb(adev); 3079 return 0; 3080 } 3081 3082 adev->gfx.rlc.funcs->stop(adev); 3083 3084 /* disable CG */ 3085 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 3086 3087 gfx_v9_0_init_pg(adev); 3088 3089 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3090 /* legacy rlc firmware loading */ 3091 r = gfx_v9_0_rlc_load_microcode(adev); 3092 if (r) 3093 return r; 3094 } 3095 3096 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3097 case IP_VERSION(9, 2, 2): 3098 case IP_VERSION(9, 1, 0): 3099 gfx_v9_0_init_lbpw(adev); 3100 if (amdgpu_lbpw == 0) 3101 gfx_v9_0_enable_lbpw(adev, false); 3102 else 3103 gfx_v9_0_enable_lbpw(adev, true); 3104 break; 3105 case IP_VERSION(9, 4, 0): 3106 gfx_v9_4_init_lbpw(adev); 3107 if (amdgpu_lbpw > 0) 3108 gfx_v9_0_enable_lbpw(adev, true); 3109 else 3110 gfx_v9_0_enable_lbpw(adev, false); 3111 break; 3112 default: 3113 break; 3114 } 3115 3116 gfx_v9_0_update_spm_vmid_internal(adev, 0xf); 3117 3118 adev->gfx.rlc.funcs->start(adev); 3119 3120 return 0; 3121 } 3122 3123 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3124 { 3125 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 3126 3127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3128 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3129 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 3130 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 3131 udelay(50); 3132 } 3133 3134 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3135 { 3136 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3137 const struct gfx_firmware_header_v1_0 *ce_hdr; 3138 const struct gfx_firmware_header_v1_0 *me_hdr; 3139 const __le32 *fw_data; 3140 unsigned i, fw_size; 3141 3142 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3143 return -EINVAL; 3144 3145 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3146 adev->gfx.pfp_fw->data; 3147 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3148 adev->gfx.ce_fw->data; 3149 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3150 adev->gfx.me_fw->data; 3151 3152 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3153 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3154 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3155 3156 gfx_v9_0_cp_gfx_enable(adev, false); 3157 3158 /* PFP */ 3159 fw_data = (const __le32 *) 3160 (adev->gfx.pfp_fw->data + 3161 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3162 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3163 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3164 for (i = 0; i < fw_size; i++) 3165 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3166 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3167 3168 /* CE */ 3169 fw_data = (const __le32 *) 3170 (adev->gfx.ce_fw->data + 3171 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3172 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3173 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3174 for (i = 0; i < fw_size; i++) 3175 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3176 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3177 3178 /* ME */ 3179 fw_data = (const __le32 *) 3180 (adev->gfx.me_fw->data + 3181 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3182 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3183 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3184 for (i = 0; i < fw_size; i++) 3185 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3186 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3187 3188 return 0; 3189 } 3190 3191 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3192 { 3193 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3194 const struct cs_section_def *sect = NULL; 3195 const struct cs_extent_def *ext = NULL; 3196 int r, i, tmp; 3197 3198 /* init the CP */ 3199 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3200 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3201 3202 gfx_v9_0_cp_gfx_enable(adev, true); 3203 3204 /* Now only limit the quirk on the APU gfx9 series and already 3205 * confirmed that the APU gfx10/gfx11 needn't such update. 3206 */ 3207 if (adev->flags & AMD_IS_APU && 3208 adev->in_s3 && !adev->suspend_complete) { 3209 DRM_INFO(" Will skip the CSB packet resubmit\n"); 3210 return 0; 3211 } 3212 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3213 if (r) { 3214 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3215 return r; 3216 } 3217 3218 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3219 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3220 3221 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3222 amdgpu_ring_write(ring, 0x80000000); 3223 amdgpu_ring_write(ring, 0x80000000); 3224 3225 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3226 for (ext = sect->section; ext->extent != NULL; ++ext) { 3227 if (sect->id == SECT_CONTEXT) { 3228 amdgpu_ring_write(ring, 3229 PACKET3(PACKET3_SET_CONTEXT_REG, 3230 ext->reg_count)); 3231 amdgpu_ring_write(ring, 3232 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3233 for (i = 0; i < ext->reg_count; i++) 3234 amdgpu_ring_write(ring, ext->extent[i]); 3235 } 3236 } 3237 } 3238 3239 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3240 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3241 3242 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3243 amdgpu_ring_write(ring, 0); 3244 3245 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3246 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3247 amdgpu_ring_write(ring, 0x8000); 3248 amdgpu_ring_write(ring, 0x8000); 3249 3250 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3251 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3252 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3253 amdgpu_ring_write(ring, tmp); 3254 amdgpu_ring_write(ring, 0); 3255 3256 amdgpu_ring_commit(ring); 3257 3258 return 0; 3259 } 3260 3261 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3262 { 3263 struct amdgpu_ring *ring; 3264 u32 tmp; 3265 u32 rb_bufsz; 3266 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3267 3268 /* Set the write pointer delay */ 3269 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3270 3271 /* set the RB to use vmid 0 */ 3272 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3273 3274 /* Set ring buffer size */ 3275 ring = &adev->gfx.gfx_ring[0]; 3276 rb_bufsz = order_base_2(ring->ring_size / 8); 3277 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3278 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3279 #ifdef __BIG_ENDIAN 3280 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3281 #endif 3282 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3283 3284 /* Initialize the ring buffer's write pointers */ 3285 ring->wptr = 0; 3286 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3287 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3288 3289 /* set the wb address wether it's enabled or not */ 3290 rptr_addr = ring->rptr_gpu_addr; 3291 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3292 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3293 3294 wptr_gpu_addr = ring->wptr_gpu_addr; 3295 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3296 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3297 3298 mdelay(1); 3299 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3300 3301 rb_addr = ring->gpu_addr >> 8; 3302 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3303 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3304 3305 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3306 if (ring->use_doorbell) { 3307 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3308 DOORBELL_OFFSET, ring->doorbell_index); 3309 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3310 DOORBELL_EN, 1); 3311 } else { 3312 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3313 } 3314 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3315 3316 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3317 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3318 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3319 3320 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3321 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3322 3323 3324 /* start the ring */ 3325 gfx_v9_0_cp_gfx_start(adev); 3326 3327 return 0; 3328 } 3329 3330 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3331 { 3332 if (enable) { 3333 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3334 } else { 3335 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3336 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3337 adev->gfx.kiq[0].ring.sched.ready = false; 3338 } 3339 udelay(50); 3340 } 3341 3342 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3343 { 3344 const struct gfx_firmware_header_v1_0 *mec_hdr; 3345 const __le32 *fw_data; 3346 unsigned i; 3347 u32 tmp; 3348 3349 if (!adev->gfx.mec_fw) 3350 return -EINVAL; 3351 3352 gfx_v9_0_cp_compute_enable(adev, false); 3353 3354 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3355 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3356 3357 fw_data = (const __le32 *) 3358 (adev->gfx.mec_fw->data + 3359 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3360 tmp = 0; 3361 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3362 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3363 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3364 3365 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3366 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3367 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3368 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3369 3370 /* MEC1 */ 3371 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3372 mec_hdr->jt_offset); 3373 for (i = 0; i < mec_hdr->jt_size; i++) 3374 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3375 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3376 3377 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3378 adev->gfx.mec_fw_version); 3379 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3380 3381 return 0; 3382 } 3383 3384 /* KIQ functions */ 3385 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3386 { 3387 uint32_t tmp; 3388 struct amdgpu_device *adev = ring->adev; 3389 3390 /* tell RLC which is KIQ queue */ 3391 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3392 tmp &= 0xffffff00; 3393 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3394 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3395 tmp |= 0x80; 3396 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3397 } 3398 3399 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3400 { 3401 struct amdgpu_device *adev = ring->adev; 3402 3403 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3404 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3405 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3406 mqd->cp_hqd_queue_priority = 3407 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3408 } 3409 } 3410 } 3411 3412 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3413 { 3414 struct amdgpu_device *adev = ring->adev; 3415 struct v9_mqd *mqd = ring->mqd_ptr; 3416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3417 uint32_t tmp; 3418 3419 mqd->header = 0xC0310800; 3420 mqd->compute_pipelinestat_enable = 0x00000001; 3421 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3422 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3423 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3424 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3425 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3426 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3427 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3428 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3429 mqd->compute_misc_reserved = 0x00000003; 3430 3431 mqd->dynamic_cu_mask_addr_lo = 3432 lower_32_bits(ring->mqd_gpu_addr 3433 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3434 mqd->dynamic_cu_mask_addr_hi = 3435 upper_32_bits(ring->mqd_gpu_addr 3436 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3437 3438 eop_base_addr = ring->eop_gpu_addr >> 8; 3439 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3440 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3441 3442 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3443 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3444 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3445 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3446 3447 mqd->cp_hqd_eop_control = tmp; 3448 3449 /* enable doorbell? */ 3450 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3451 3452 if (ring->use_doorbell) { 3453 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3454 DOORBELL_OFFSET, ring->doorbell_index); 3455 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3456 DOORBELL_EN, 1); 3457 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3458 DOORBELL_SOURCE, 0); 3459 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3460 DOORBELL_HIT, 0); 3461 } else { 3462 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3463 DOORBELL_EN, 0); 3464 } 3465 3466 mqd->cp_hqd_pq_doorbell_control = tmp; 3467 3468 /* disable the queue if it's active */ 3469 ring->wptr = 0; 3470 mqd->cp_hqd_dequeue_request = 0; 3471 mqd->cp_hqd_pq_rptr = 0; 3472 mqd->cp_hqd_pq_wptr_lo = 0; 3473 mqd->cp_hqd_pq_wptr_hi = 0; 3474 3475 /* set the pointer to the MQD */ 3476 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3477 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3478 3479 /* set MQD vmid to 0 */ 3480 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3481 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3482 mqd->cp_mqd_control = tmp; 3483 3484 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3485 hqd_gpu_addr = ring->gpu_addr >> 8; 3486 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3487 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3488 3489 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3490 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3492 (order_base_2(ring->ring_size / 4) - 1)); 3493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3494 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3495 #ifdef __BIG_ENDIAN 3496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3497 #endif 3498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3502 mqd->cp_hqd_pq_control = tmp; 3503 3504 /* set the wb address whether it's enabled or not */ 3505 wb_gpu_addr = ring->rptr_gpu_addr; 3506 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3507 mqd->cp_hqd_pq_rptr_report_addr_hi = 3508 upper_32_bits(wb_gpu_addr) & 0xffff; 3509 3510 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3511 wb_gpu_addr = ring->wptr_gpu_addr; 3512 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3513 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3514 3515 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3516 ring->wptr = 0; 3517 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3518 3519 /* set the vmid for the queue */ 3520 mqd->cp_hqd_vmid = 0; 3521 3522 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3523 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3524 mqd->cp_hqd_persistent_state = tmp; 3525 3526 /* set MIN_IB_AVAIL_SIZE */ 3527 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3528 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3529 mqd->cp_hqd_ib_control = tmp; 3530 3531 /* set static priority for a queue/ring */ 3532 gfx_v9_0_mqd_set_priority(ring, mqd); 3533 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3534 3535 /* map_queues packet doesn't need activate the queue, 3536 * so only kiq need set this field. 3537 */ 3538 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3539 mqd->cp_hqd_active = 1; 3540 3541 return 0; 3542 } 3543 3544 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3545 { 3546 struct amdgpu_device *adev = ring->adev; 3547 struct v9_mqd *mqd = ring->mqd_ptr; 3548 int j; 3549 3550 /* disable wptr polling */ 3551 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3552 3553 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3554 mqd->cp_hqd_eop_base_addr_lo); 3555 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3556 mqd->cp_hqd_eop_base_addr_hi); 3557 3558 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3559 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3560 mqd->cp_hqd_eop_control); 3561 3562 /* enable doorbell? */ 3563 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3564 mqd->cp_hqd_pq_doorbell_control); 3565 3566 /* disable the queue if it's active */ 3567 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3568 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3569 for (j = 0; j < adev->usec_timeout; j++) { 3570 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3571 break; 3572 udelay(1); 3573 } 3574 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3575 mqd->cp_hqd_dequeue_request); 3576 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3577 mqd->cp_hqd_pq_rptr); 3578 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3579 mqd->cp_hqd_pq_wptr_lo); 3580 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3581 mqd->cp_hqd_pq_wptr_hi); 3582 } 3583 3584 /* set the pointer to the MQD */ 3585 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3586 mqd->cp_mqd_base_addr_lo); 3587 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3588 mqd->cp_mqd_base_addr_hi); 3589 3590 /* set MQD vmid to 0 */ 3591 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3592 mqd->cp_mqd_control); 3593 3594 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3595 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3596 mqd->cp_hqd_pq_base_lo); 3597 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3598 mqd->cp_hqd_pq_base_hi); 3599 3600 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3601 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3602 mqd->cp_hqd_pq_control); 3603 3604 /* set the wb address whether it's enabled or not */ 3605 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3606 mqd->cp_hqd_pq_rptr_report_addr_lo); 3607 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3608 mqd->cp_hqd_pq_rptr_report_addr_hi); 3609 3610 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3611 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3612 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3613 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3614 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3615 3616 /* enable the doorbell if requested */ 3617 if (ring->use_doorbell) { 3618 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3619 (adev->doorbell_index.kiq * 2) << 2); 3620 /* If GC has entered CGPG, ringing doorbell > first page 3621 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3622 * workaround this issue. And this change has to align with firmware 3623 * update. 3624 */ 3625 if (check_if_enlarge_doorbell_range(adev)) 3626 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3627 (adev->doorbell.size - 4)); 3628 else 3629 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3630 (adev->doorbell_index.userqueue_end * 2) << 2); 3631 } 3632 3633 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3634 mqd->cp_hqd_pq_doorbell_control); 3635 3636 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3637 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3638 mqd->cp_hqd_pq_wptr_lo); 3639 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3640 mqd->cp_hqd_pq_wptr_hi); 3641 3642 /* set the vmid for the queue */ 3643 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3644 3645 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3646 mqd->cp_hqd_persistent_state); 3647 3648 /* activate the queue */ 3649 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3650 mqd->cp_hqd_active); 3651 3652 if (ring->use_doorbell) 3653 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3654 3655 return 0; 3656 } 3657 3658 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3659 { 3660 struct amdgpu_device *adev = ring->adev; 3661 int j; 3662 3663 /* disable the queue if it's active */ 3664 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3665 3666 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3667 3668 for (j = 0; j < adev->usec_timeout; j++) { 3669 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3670 break; 3671 udelay(1); 3672 } 3673 3674 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3675 DRM_DEBUG("KIQ dequeue request failed.\n"); 3676 3677 /* Manual disable if dequeue request times out */ 3678 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3679 } 3680 3681 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3682 0); 3683 } 3684 3685 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3686 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3687 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3688 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3689 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3690 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3691 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3692 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3693 3694 return 0; 3695 } 3696 3697 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3698 { 3699 struct amdgpu_device *adev = ring->adev; 3700 struct v9_mqd *mqd = ring->mqd_ptr; 3701 struct v9_mqd *tmp_mqd; 3702 3703 gfx_v9_0_kiq_setting(ring); 3704 3705 /* GPU could be in bad state during probe, driver trigger the reset 3706 * after load the SMU, in this case , the mqd is not be initialized. 3707 * driver need to re-init the mqd. 3708 * check mqd->cp_hqd_pq_control since this value should not be 0 3709 */ 3710 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; 3711 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3712 /* for GPU_RESET case , reset MQD to a clean status */ 3713 if (adev->gfx.kiq[0].mqd_backup) 3714 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); 3715 3716 /* reset ring buffer */ 3717 ring->wptr = 0; 3718 amdgpu_ring_clear_ring(ring); 3719 3720 mutex_lock(&adev->srbm_mutex); 3721 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3722 gfx_v9_0_kiq_init_register(ring); 3723 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3724 mutex_unlock(&adev->srbm_mutex); 3725 } else { 3726 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3727 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3728 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3729 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3730 amdgpu_ring_clear_ring(ring); 3731 mutex_lock(&adev->srbm_mutex); 3732 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3733 gfx_v9_0_mqd_init(ring); 3734 gfx_v9_0_kiq_init_register(ring); 3735 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3736 mutex_unlock(&adev->srbm_mutex); 3737 3738 if (adev->gfx.kiq[0].mqd_backup) 3739 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 3740 } 3741 3742 return 0; 3743 } 3744 3745 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3746 { 3747 struct amdgpu_device *adev = ring->adev; 3748 struct v9_mqd *mqd = ring->mqd_ptr; 3749 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3750 struct v9_mqd *tmp_mqd; 3751 3752 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3753 * is not be initialized before 3754 */ 3755 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3756 3757 if (!tmp_mqd->cp_hqd_pq_control || 3758 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3759 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3760 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3761 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3762 mutex_lock(&adev->srbm_mutex); 3763 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3764 gfx_v9_0_mqd_init(ring); 3765 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3766 mutex_unlock(&adev->srbm_mutex); 3767 3768 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3769 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3770 } else { 3771 /* restore MQD to a clean status */ 3772 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3773 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3774 /* reset ring buffer */ 3775 ring->wptr = 0; 3776 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3777 amdgpu_ring_clear_ring(ring); 3778 } 3779 3780 return 0; 3781 } 3782 3783 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3784 { 3785 struct amdgpu_ring *ring; 3786 int r; 3787 3788 ring = &adev->gfx.kiq[0].ring; 3789 3790 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3791 if (unlikely(r != 0)) 3792 return r; 3793 3794 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3795 if (unlikely(r != 0)) { 3796 amdgpu_bo_unreserve(ring->mqd_obj); 3797 return r; 3798 } 3799 3800 gfx_v9_0_kiq_init_queue(ring); 3801 amdgpu_bo_kunmap(ring->mqd_obj); 3802 ring->mqd_ptr = NULL; 3803 amdgpu_bo_unreserve(ring->mqd_obj); 3804 return 0; 3805 } 3806 3807 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3808 { 3809 struct amdgpu_ring *ring = NULL; 3810 int r = 0, i; 3811 3812 gfx_v9_0_cp_compute_enable(adev, true); 3813 3814 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3815 ring = &adev->gfx.compute_ring[i]; 3816 3817 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3818 if (unlikely(r != 0)) 3819 goto done; 3820 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3821 if (!r) { 3822 r = gfx_v9_0_kcq_init_queue(ring); 3823 amdgpu_bo_kunmap(ring->mqd_obj); 3824 ring->mqd_ptr = NULL; 3825 } 3826 amdgpu_bo_unreserve(ring->mqd_obj); 3827 if (r) 3828 goto done; 3829 } 3830 3831 r = amdgpu_gfx_enable_kcq(adev, 0); 3832 done: 3833 return r; 3834 } 3835 3836 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3837 { 3838 int r, i; 3839 struct amdgpu_ring *ring; 3840 3841 if (!(adev->flags & AMD_IS_APU)) 3842 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3843 3844 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3845 if (adev->gfx.num_gfx_rings) { 3846 /* legacy firmware loading */ 3847 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3848 if (r) 3849 return r; 3850 } 3851 3852 r = gfx_v9_0_cp_compute_load_microcode(adev); 3853 if (r) 3854 return r; 3855 } 3856 3857 r = gfx_v9_0_kiq_resume(adev); 3858 if (r) 3859 return r; 3860 3861 if (adev->gfx.num_gfx_rings) { 3862 r = gfx_v9_0_cp_gfx_resume(adev); 3863 if (r) 3864 return r; 3865 } 3866 3867 r = gfx_v9_0_kcq_resume(adev); 3868 if (r) 3869 return r; 3870 3871 if (adev->gfx.num_gfx_rings) { 3872 ring = &adev->gfx.gfx_ring[0]; 3873 r = amdgpu_ring_test_helper(ring); 3874 if (r) 3875 return r; 3876 } 3877 3878 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3879 ring = &adev->gfx.compute_ring[i]; 3880 amdgpu_ring_test_helper(ring); 3881 } 3882 3883 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3884 3885 return 0; 3886 } 3887 3888 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3889 { 3890 u32 tmp; 3891 3892 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1) && 3893 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) 3894 return; 3895 3896 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3897 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3898 adev->df.hash_status.hash_64k); 3899 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3900 adev->df.hash_status.hash_2m); 3901 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3902 adev->df.hash_status.hash_1g); 3903 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3904 } 3905 3906 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3907 { 3908 if (adev->gfx.num_gfx_rings) 3909 gfx_v9_0_cp_gfx_enable(adev, enable); 3910 gfx_v9_0_cp_compute_enable(adev, enable); 3911 } 3912 3913 static int gfx_v9_0_hw_init(void *handle) 3914 { 3915 int r; 3916 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3917 3918 if (!amdgpu_sriov_vf(adev)) 3919 gfx_v9_0_init_golden_registers(adev); 3920 3921 gfx_v9_0_constants_init(adev); 3922 3923 gfx_v9_0_init_tcp_config(adev); 3924 3925 r = adev->gfx.rlc.funcs->resume(adev); 3926 if (r) 3927 return r; 3928 3929 r = gfx_v9_0_cp_resume(adev); 3930 if (r) 3931 return r; 3932 3933 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 3934 gfx_v9_4_2_set_power_brake_sequence(adev); 3935 3936 return r; 3937 } 3938 3939 static int gfx_v9_0_hw_fini(void *handle) 3940 { 3941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3942 3943 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 3944 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3945 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3946 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3947 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3948 3949 /* DF freeze and kcq disable will fail */ 3950 if (!amdgpu_ras_intr_triggered()) 3951 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3952 amdgpu_gfx_disable_kcq(adev, 0); 3953 3954 if (amdgpu_sriov_vf(adev)) { 3955 gfx_v9_0_cp_gfx_enable(adev, false); 3956 /* must disable polling for SRIOV when hw finished, otherwise 3957 * CPC engine may still keep fetching WB address which is already 3958 * invalid after sw finished and trigger DMAR reading error in 3959 * hypervisor side. 3960 */ 3961 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3962 return 0; 3963 } 3964 3965 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3966 * otherwise KIQ is hanging when binding back 3967 */ 3968 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3969 mutex_lock(&adev->srbm_mutex); 3970 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, 3971 adev->gfx.kiq[0].ring.pipe, 3972 adev->gfx.kiq[0].ring.queue, 0, 0); 3973 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); 3974 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3975 mutex_unlock(&adev->srbm_mutex); 3976 } 3977 3978 gfx_v9_0_cp_enable(adev, false); 3979 3980 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3981 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3982 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) { 3983 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3984 return 0; 3985 } 3986 3987 adev->gfx.rlc.funcs->stop(adev); 3988 return 0; 3989 } 3990 3991 static int gfx_v9_0_suspend(void *handle) 3992 { 3993 return gfx_v9_0_hw_fini(handle); 3994 } 3995 3996 static int gfx_v9_0_resume(void *handle) 3997 { 3998 return gfx_v9_0_hw_init(handle); 3999 } 4000 4001 static bool gfx_v9_0_is_idle(void *handle) 4002 { 4003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4004 4005 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 4006 GRBM_STATUS, GUI_ACTIVE)) 4007 return false; 4008 else 4009 return true; 4010 } 4011 4012 static int gfx_v9_0_wait_for_idle(void *handle) 4013 { 4014 unsigned i; 4015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4016 4017 for (i = 0; i < adev->usec_timeout; i++) { 4018 if (gfx_v9_0_is_idle(handle)) 4019 return 0; 4020 udelay(1); 4021 } 4022 return -ETIMEDOUT; 4023 } 4024 4025 static int gfx_v9_0_soft_reset(void *handle) 4026 { 4027 u32 grbm_soft_reset = 0; 4028 u32 tmp; 4029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4030 4031 /* GRBM_STATUS */ 4032 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 4033 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4034 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4035 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4036 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4037 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4038 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 4039 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4040 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4041 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4042 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4043 } 4044 4045 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4046 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4047 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4048 } 4049 4050 /* GRBM_STATUS2 */ 4051 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 4052 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4053 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4054 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4055 4056 4057 if (grbm_soft_reset) { 4058 /* stop the rlc */ 4059 adev->gfx.rlc.funcs->stop(adev); 4060 4061 if (adev->gfx.num_gfx_rings) 4062 /* Disable GFX parsing/prefetching */ 4063 gfx_v9_0_cp_gfx_enable(adev, false); 4064 4065 /* Disable MEC parsing/prefetching */ 4066 gfx_v9_0_cp_compute_enable(adev, false); 4067 4068 if (grbm_soft_reset) { 4069 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4070 tmp |= grbm_soft_reset; 4071 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4072 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4073 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4074 4075 udelay(50); 4076 4077 tmp &= ~grbm_soft_reset; 4078 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4079 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4080 } 4081 4082 /* Wait a little for things to settle down */ 4083 udelay(50); 4084 } 4085 return 0; 4086 } 4087 4088 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 4089 { 4090 signed long r, cnt = 0; 4091 unsigned long flags; 4092 uint32_t seq, reg_val_offs = 0; 4093 uint64_t value = 0; 4094 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4095 struct amdgpu_ring *ring = &kiq->ring; 4096 4097 BUG_ON(!ring->funcs->emit_rreg); 4098 4099 spin_lock_irqsave(&kiq->ring_lock, flags); 4100 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 4101 pr_err("critical bug! too many kiq readers\n"); 4102 goto failed_unlock; 4103 } 4104 amdgpu_ring_alloc(ring, 32); 4105 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4106 amdgpu_ring_write(ring, 9 | /* src: register*/ 4107 (5 << 8) | /* dst: memory */ 4108 (1 << 16) | /* count sel */ 4109 (1 << 20)); /* write confirm */ 4110 amdgpu_ring_write(ring, 0); 4111 amdgpu_ring_write(ring, 0); 4112 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4113 reg_val_offs * 4)); 4114 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4115 reg_val_offs * 4)); 4116 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 4117 if (r) 4118 goto failed_undo; 4119 4120 amdgpu_ring_commit(ring); 4121 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4122 4123 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4124 4125 /* don't wait anymore for gpu reset case because this way may 4126 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 4127 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 4128 * never return if we keep waiting in virt_kiq_rreg, which cause 4129 * gpu_recover() hang there. 4130 * 4131 * also don't wait anymore for IRQ context 4132 * */ 4133 if (r < 1 && (amdgpu_in_reset(adev))) 4134 goto failed_kiq_read; 4135 4136 might_sleep(); 4137 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 4138 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 4139 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4140 } 4141 4142 if (cnt > MAX_KIQ_REG_TRY) 4143 goto failed_kiq_read; 4144 4145 mb(); 4146 value = (uint64_t)adev->wb.wb[reg_val_offs] | 4147 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 4148 amdgpu_device_wb_free(adev, reg_val_offs); 4149 return value; 4150 4151 failed_undo: 4152 amdgpu_ring_undo(ring); 4153 failed_unlock: 4154 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4155 failed_kiq_read: 4156 if (reg_val_offs) 4157 amdgpu_device_wb_free(adev, reg_val_offs); 4158 pr_err("failed to read gpu clock\n"); 4159 return ~0; 4160 } 4161 4162 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4163 { 4164 uint64_t clock, clock_lo, clock_hi, hi_check; 4165 4166 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4167 case IP_VERSION(9, 3, 0): 4168 preempt_disable(); 4169 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4170 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4171 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4172 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 4173 * roughly every 42 seconds. 4174 */ 4175 if (hi_check != clock_hi) { 4176 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4177 clock_hi = hi_check; 4178 } 4179 preempt_enable(); 4180 clock = clock_lo | (clock_hi << 32ULL); 4181 break; 4182 default: 4183 amdgpu_gfx_off_ctrl(adev, false); 4184 mutex_lock(&adev->gfx.gpu_clock_mutex); 4185 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 4186 IP_VERSION(9, 0, 1) && 4187 amdgpu_sriov_runtime(adev)) { 4188 clock = gfx_v9_0_kiq_read_clock(adev); 4189 } else { 4190 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4191 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4192 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4193 } 4194 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4195 amdgpu_gfx_off_ctrl(adev, true); 4196 break; 4197 } 4198 return clock; 4199 } 4200 4201 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4202 uint32_t vmid, 4203 uint32_t gds_base, uint32_t gds_size, 4204 uint32_t gws_base, uint32_t gws_size, 4205 uint32_t oa_base, uint32_t oa_size) 4206 { 4207 struct amdgpu_device *adev = ring->adev; 4208 4209 /* GDS Base */ 4210 gfx_v9_0_write_data_to_reg(ring, 0, false, 4211 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4212 gds_base); 4213 4214 /* GDS Size */ 4215 gfx_v9_0_write_data_to_reg(ring, 0, false, 4216 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4217 gds_size); 4218 4219 /* GWS */ 4220 gfx_v9_0_write_data_to_reg(ring, 0, false, 4221 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4222 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4223 4224 /* OA */ 4225 gfx_v9_0_write_data_to_reg(ring, 0, false, 4226 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4227 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4228 } 4229 4230 static const u32 vgpr_init_compute_shader[] = 4231 { 4232 0xb07c0000, 0xbe8000ff, 4233 0x000000f8, 0xbf110800, 4234 0x7e000280, 0x7e020280, 4235 0x7e040280, 0x7e060280, 4236 0x7e080280, 0x7e0a0280, 4237 0x7e0c0280, 0x7e0e0280, 4238 0x80808800, 0xbe803200, 4239 0xbf84fff5, 0xbf9c0000, 4240 0xd28c0001, 0x0001007f, 4241 0xd28d0001, 0x0002027e, 4242 0x10020288, 0xb8810904, 4243 0xb7814000, 0xd1196a01, 4244 0x00000301, 0xbe800087, 4245 0xbefc00c1, 0xd89c4000, 4246 0x00020201, 0xd89cc080, 4247 0x00040401, 0x320202ff, 4248 0x00000800, 0x80808100, 4249 0xbf84fff8, 0x7e020280, 4250 0xbf810000, 0x00000000, 4251 }; 4252 4253 static const u32 sgpr_init_compute_shader[] = 4254 { 4255 0xb07c0000, 0xbe8000ff, 4256 0x0000005f, 0xbee50080, 4257 0xbe812c65, 0xbe822c65, 4258 0xbe832c65, 0xbe842c65, 4259 0xbe852c65, 0xb77c0005, 4260 0x80808500, 0xbf84fff8, 4261 0xbe800080, 0xbf810000, 4262 }; 4263 4264 static const u32 vgpr_init_compute_shader_arcturus[] = { 4265 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4266 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4267 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4268 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4269 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4270 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4271 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4272 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4273 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4274 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4275 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4276 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4277 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4278 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4279 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4280 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4281 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4282 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4283 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4284 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4285 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4286 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4287 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4288 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4289 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4290 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4291 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4292 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4293 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4294 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4295 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4296 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4297 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4298 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4299 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4300 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4301 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4302 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4303 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4304 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4305 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4306 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4307 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4308 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4309 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4310 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4311 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4312 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4313 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4314 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4315 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4316 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4317 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4318 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4319 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4320 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4321 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4322 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4323 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4324 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4325 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4326 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4327 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4328 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4329 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4330 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4331 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4332 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4333 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4334 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4335 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4336 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4337 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4338 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4339 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4340 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4341 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4342 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4343 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4344 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4345 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4346 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4347 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4348 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4349 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4350 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4351 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4352 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4353 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4354 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4355 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4356 0xbf84fff8, 0xbf810000, 4357 }; 4358 4359 /* When below register arrays changed, please update gpr_reg_size, 4360 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4361 to cover all gfx9 ASICs */ 4362 static const struct soc15_reg_entry vgpr_init_regs[] = { 4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4366 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4367 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4368 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4369 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4370 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4371 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4372 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4373 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4374 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4375 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4376 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4377 }; 4378 4379 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4380 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4381 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4382 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4383 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4384 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4385 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4386 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4387 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4388 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4389 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4390 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4391 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4392 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4393 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4394 }; 4395 4396 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4397 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4398 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4399 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4400 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4401 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4402 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4403 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4404 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4405 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4406 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4407 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4408 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4409 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4410 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4411 }; 4412 4413 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4414 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4415 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4416 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4417 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4418 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4419 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4420 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4421 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4422 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4423 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4424 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4425 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4426 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4427 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4428 }; 4429 4430 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4431 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4432 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4433 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4434 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4435 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4436 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4437 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4438 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4439 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4440 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4441 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4442 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4443 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4444 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4445 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4446 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4447 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4448 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4449 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4450 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4451 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4452 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4453 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4454 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4455 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4456 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4457 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4458 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4459 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4460 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4461 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4462 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4463 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4464 }; 4465 4466 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4467 { 4468 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4469 int i, r; 4470 4471 /* only support when RAS is enabled */ 4472 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4473 return 0; 4474 4475 r = amdgpu_ring_alloc(ring, 7); 4476 if (r) { 4477 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4478 ring->name, r); 4479 return r; 4480 } 4481 4482 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4483 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4484 4485 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4486 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4487 PACKET3_DMA_DATA_DST_SEL(1) | 4488 PACKET3_DMA_DATA_SRC_SEL(2) | 4489 PACKET3_DMA_DATA_ENGINE(0))); 4490 amdgpu_ring_write(ring, 0); 4491 amdgpu_ring_write(ring, 0); 4492 amdgpu_ring_write(ring, 0); 4493 amdgpu_ring_write(ring, 0); 4494 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4495 adev->gds.gds_size); 4496 4497 amdgpu_ring_commit(ring); 4498 4499 for (i = 0; i < adev->usec_timeout; i++) { 4500 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4501 break; 4502 udelay(1); 4503 } 4504 4505 if (i >= adev->usec_timeout) 4506 r = -ETIMEDOUT; 4507 4508 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4509 4510 return r; 4511 } 4512 4513 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4514 { 4515 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4516 struct amdgpu_ib ib; 4517 struct dma_fence *f = NULL; 4518 int r, i; 4519 unsigned total_size, vgpr_offset, sgpr_offset; 4520 u64 gpu_addr; 4521 4522 int compute_dim_x = adev->gfx.config.max_shader_engines * 4523 adev->gfx.config.max_cu_per_sh * 4524 adev->gfx.config.max_sh_per_se; 4525 int sgpr_work_group_size = 5; 4526 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4527 int vgpr_init_shader_size; 4528 const u32 *vgpr_init_shader_ptr; 4529 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4530 4531 /* only support when RAS is enabled */ 4532 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4533 return 0; 4534 4535 /* bail if the compute ring is not ready */ 4536 if (!ring->sched.ready) 4537 return 0; 4538 4539 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 4540 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4541 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4542 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4543 } else { 4544 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4545 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4546 vgpr_init_regs_ptr = vgpr_init_regs; 4547 } 4548 4549 total_size = 4550 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4551 total_size += 4552 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4553 total_size += 4554 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4555 total_size = ALIGN(total_size, 256); 4556 vgpr_offset = total_size; 4557 total_size += ALIGN(vgpr_init_shader_size, 256); 4558 sgpr_offset = total_size; 4559 total_size += sizeof(sgpr_init_compute_shader); 4560 4561 /* allocate an indirect buffer to put the commands in */ 4562 memset(&ib, 0, sizeof(ib)); 4563 r = amdgpu_ib_get(adev, NULL, total_size, 4564 AMDGPU_IB_POOL_DIRECT, &ib); 4565 if (r) { 4566 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4567 return r; 4568 } 4569 4570 /* load the compute shaders */ 4571 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4572 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4573 4574 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4575 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4576 4577 /* init the ib length to 0 */ 4578 ib.length_dw = 0; 4579 4580 /* VGPR */ 4581 /* write the register state for the compute dispatch */ 4582 for (i = 0; i < gpr_reg_size; i++) { 4583 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4584 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4585 - PACKET3_SET_SH_REG_START; 4586 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4587 } 4588 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4589 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4591 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4592 - PACKET3_SET_SH_REG_START; 4593 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4594 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4595 4596 /* write dispatch packet */ 4597 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4598 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4599 ib.ptr[ib.length_dw++] = 1; /* y */ 4600 ib.ptr[ib.length_dw++] = 1; /* z */ 4601 ib.ptr[ib.length_dw++] = 4602 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4603 4604 /* write CS partial flush packet */ 4605 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4606 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4607 4608 /* SGPR1 */ 4609 /* write the register state for the compute dispatch */ 4610 for (i = 0; i < gpr_reg_size; i++) { 4611 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4612 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4613 - PACKET3_SET_SH_REG_START; 4614 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4615 } 4616 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4617 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4618 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4619 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4620 - PACKET3_SET_SH_REG_START; 4621 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4622 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4623 4624 /* write dispatch packet */ 4625 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4626 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4627 ib.ptr[ib.length_dw++] = 1; /* y */ 4628 ib.ptr[ib.length_dw++] = 1; /* z */ 4629 ib.ptr[ib.length_dw++] = 4630 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4631 4632 /* write CS partial flush packet */ 4633 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4634 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4635 4636 /* SGPR2 */ 4637 /* write the register state for the compute dispatch */ 4638 for (i = 0; i < gpr_reg_size; i++) { 4639 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4640 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4641 - PACKET3_SET_SH_REG_START; 4642 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4643 } 4644 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4645 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4646 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4647 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4648 - PACKET3_SET_SH_REG_START; 4649 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4650 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4651 4652 /* write dispatch packet */ 4653 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4654 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4655 ib.ptr[ib.length_dw++] = 1; /* y */ 4656 ib.ptr[ib.length_dw++] = 1; /* z */ 4657 ib.ptr[ib.length_dw++] = 4658 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4659 4660 /* write CS partial flush packet */ 4661 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4662 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4663 4664 /* shedule the ib on the ring */ 4665 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4666 if (r) { 4667 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4668 goto fail; 4669 } 4670 4671 /* wait for the GPU to finish processing the IB */ 4672 r = dma_fence_wait(f, false); 4673 if (r) { 4674 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4675 goto fail; 4676 } 4677 4678 fail: 4679 amdgpu_ib_free(adev, &ib, NULL); 4680 dma_fence_put(f); 4681 4682 return r; 4683 } 4684 4685 static int gfx_v9_0_early_init(void *handle) 4686 { 4687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4688 4689 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 4690 4691 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 4692 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 4693 adev->gfx.num_gfx_rings = 0; 4694 else 4695 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4696 adev->gfx.xcc_mask = 1; 4697 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4698 AMDGPU_MAX_COMPUTE_RINGS); 4699 gfx_v9_0_set_kiq_pm4_funcs(adev); 4700 gfx_v9_0_set_ring_funcs(adev); 4701 gfx_v9_0_set_irq_funcs(adev); 4702 gfx_v9_0_set_gds_init(adev); 4703 gfx_v9_0_set_rlc_funcs(adev); 4704 4705 /* init rlcg reg access ctrl */ 4706 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4707 4708 return gfx_v9_0_init_microcode(adev); 4709 } 4710 4711 static int gfx_v9_0_ecc_late_init(void *handle) 4712 { 4713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4714 int r; 4715 4716 /* 4717 * Temp workaround to fix the issue that CP firmware fails to 4718 * update read pointer when CPDMA is writing clearing operation 4719 * to GDS in suspend/resume sequence on several cards. So just 4720 * limit this operation in cold boot sequence. 4721 */ 4722 if ((!adev->in_suspend) && 4723 (adev->gds.gds_size)) { 4724 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4725 if (r) 4726 return r; 4727 } 4728 4729 /* requires IBs so do in late init after IB pool is initialized */ 4730 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 4731 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4732 else 4733 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4734 4735 if (r) 4736 return r; 4737 4738 if (adev->gfx.ras && 4739 adev->gfx.ras->enable_watchdog_timer) 4740 adev->gfx.ras->enable_watchdog_timer(adev); 4741 4742 return 0; 4743 } 4744 4745 static int gfx_v9_0_late_init(void *handle) 4746 { 4747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4748 int r; 4749 4750 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4751 if (r) 4752 return r; 4753 4754 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4755 if (r) 4756 return r; 4757 4758 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 4759 if (r) 4760 return r; 4761 4762 r = gfx_v9_0_ecc_late_init(handle); 4763 if (r) 4764 return r; 4765 4766 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 4767 gfx_v9_4_2_debug_trap_config_init(adev, 4768 adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); 4769 else 4770 gfx_v9_0_debug_trap_config_init(adev, 4771 adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); 4772 4773 return 0; 4774 } 4775 4776 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4777 { 4778 uint32_t rlc_setting; 4779 4780 /* if RLC is not enabled, do nothing */ 4781 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4782 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4783 return false; 4784 4785 return true; 4786 } 4787 4788 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4789 { 4790 uint32_t data; 4791 unsigned i; 4792 4793 data = RLC_SAFE_MODE__CMD_MASK; 4794 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4795 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4796 4797 /* wait for RLC_SAFE_MODE */ 4798 for (i = 0; i < adev->usec_timeout; i++) { 4799 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4800 break; 4801 udelay(1); 4802 } 4803 } 4804 4805 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4806 { 4807 uint32_t data; 4808 4809 data = RLC_SAFE_MODE__CMD_MASK; 4810 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4811 } 4812 4813 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4814 bool enable) 4815 { 4816 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4817 4818 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4819 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4820 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4821 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4822 } else { 4823 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4824 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4825 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4826 } 4827 4828 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4829 } 4830 4831 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4832 bool enable) 4833 { 4834 /* TODO: double check if we need to perform under safe mode */ 4835 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4836 4837 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4838 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4839 else 4840 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4841 4842 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4843 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4844 else 4845 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4846 4847 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4848 } 4849 4850 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4851 bool enable) 4852 { 4853 uint32_t data, def; 4854 4855 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4856 4857 /* It is disabled by HW by default */ 4858 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4859 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4860 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4861 4862 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 2, 1)) 4863 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4864 4865 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4866 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4867 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4868 4869 /* only for Vega10 & Raven1 */ 4870 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4871 4872 if (def != data) 4873 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4874 4875 /* MGLS is a global flag to control all MGLS in GFX */ 4876 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4877 /* 2 - RLC memory Light sleep */ 4878 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4879 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4880 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4881 if (def != data) 4882 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4883 } 4884 /* 3 - CP memory Light sleep */ 4885 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4886 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4887 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4888 if (def != data) 4889 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4890 } 4891 } 4892 } else { 4893 /* 1 - MGCG_OVERRIDE */ 4894 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4895 4896 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 2, 1)) 4897 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4898 4899 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4900 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4901 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4902 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4903 4904 if (def != data) 4905 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4906 4907 /* 2 - disable MGLS in RLC */ 4908 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4909 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4910 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4911 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4912 } 4913 4914 /* 3 - disable MGLS in CP */ 4915 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4916 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4917 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4918 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4919 } 4920 } 4921 4922 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4923 } 4924 4925 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4926 bool enable) 4927 { 4928 uint32_t data, def; 4929 4930 if (!adev->gfx.num_gfx_rings) 4931 return; 4932 4933 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4934 4935 /* Enable 3D CGCG/CGLS */ 4936 if (enable) { 4937 /* write cmd to clear cgcg/cgls ov */ 4938 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4939 /* unset CGCG override */ 4940 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4941 /* update CGCG and CGLS override bits */ 4942 if (def != data) 4943 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4944 4945 /* enable 3Dcgcg FSM(0x0000363f) */ 4946 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4947 4948 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4949 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4950 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4951 else 4952 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4953 4954 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4955 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4956 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4957 if (def != data) 4958 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4959 4960 /* set IDLE_POLL_COUNT(0x00900100) */ 4961 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4962 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4963 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4964 if (def != data) 4965 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4966 } else { 4967 /* Disable CGCG/CGLS */ 4968 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4969 /* disable cgcg, cgls should be disabled */ 4970 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4971 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4972 /* disable cgcg and cgls in FSM */ 4973 if (def != data) 4974 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4975 } 4976 4977 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4978 } 4979 4980 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4981 bool enable) 4982 { 4983 uint32_t def, data; 4984 4985 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4986 4987 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4988 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4989 /* unset CGCG override */ 4990 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4991 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4992 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4993 else 4994 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4995 /* update CGCG and CGLS override bits */ 4996 if (def != data) 4997 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4998 4999 /* enable cgcg FSM(0x0000363F) */ 5000 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 5001 5002 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) 5003 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5004 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5005 else 5006 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5007 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5008 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5009 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5010 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5011 if (def != data) 5012 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 5013 5014 /* set IDLE_POLL_COUNT(0x00900100) */ 5015 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 5016 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5017 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5018 if (def != data) 5019 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 5020 } else { 5021 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 5022 /* reset CGCG/CGLS bits */ 5023 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 5024 /* disable cgcg and cgls in FSM */ 5025 if (def != data) 5026 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 5027 } 5028 5029 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5030 } 5031 5032 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5033 bool enable) 5034 { 5035 if (enable) { 5036 /* CGCG/CGLS should be enabled after MGCG/MGLS 5037 * === MGCG + MGLS === 5038 */ 5039 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 5040 /* === CGCG /CGLS for GFX 3D Only === */ 5041 gfx_v9_0_update_3d_clock_gating(adev, enable); 5042 /* === CGCG + CGLS === */ 5043 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 5044 } else { 5045 /* CGCG/CGLS should be disabled before MGCG/MGLS 5046 * === CGCG + CGLS === 5047 */ 5048 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 5049 /* === CGCG /CGLS for GFX 3D Only === */ 5050 gfx_v9_0_update_3d_clock_gating(adev, enable); 5051 /* === MGCG + MGLS === */ 5052 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 5053 } 5054 return 0; 5055 } 5056 5057 static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, 5058 unsigned int vmid) 5059 { 5060 u32 reg, data; 5061 5062 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 5063 if (amdgpu_sriov_is_pp_one_vf(adev)) 5064 data = RREG32_NO_KIQ(reg); 5065 else 5066 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 5067 5068 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5069 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5070 5071 if (amdgpu_sriov_is_pp_one_vf(adev)) 5072 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 5073 else 5074 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 5075 } 5076 5077 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 5078 { 5079 amdgpu_gfx_off_ctrl(adev, false); 5080 5081 gfx_v9_0_update_spm_vmid_internal(adev, vmid); 5082 5083 amdgpu_gfx_off_ctrl(adev, true); 5084 } 5085 5086 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 5087 uint32_t offset, 5088 struct soc15_reg_rlcg *entries, int arr_size) 5089 { 5090 int i; 5091 uint32_t reg; 5092 5093 if (!entries) 5094 return false; 5095 5096 for (i = 0; i < arr_size; i++) { 5097 const struct soc15_reg_rlcg *entry; 5098 5099 entry = &entries[i]; 5100 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 5101 if (offset == reg) 5102 return true; 5103 } 5104 5105 return false; 5106 } 5107 5108 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 5109 { 5110 return gfx_v9_0_check_rlcg_range(adev, offset, 5111 (void *)rlcg_access_gc_9_0, 5112 ARRAY_SIZE(rlcg_access_gc_9_0)); 5113 } 5114 5115 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 5116 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 5117 .set_safe_mode = gfx_v9_0_set_safe_mode, 5118 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 5119 .init = gfx_v9_0_rlc_init, 5120 .get_csb_size = gfx_v9_0_get_csb_size, 5121 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 5122 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 5123 .resume = gfx_v9_0_rlc_resume, 5124 .stop = gfx_v9_0_rlc_stop, 5125 .reset = gfx_v9_0_rlc_reset, 5126 .start = gfx_v9_0_rlc_start, 5127 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 5128 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 5129 }; 5130 5131 static int gfx_v9_0_set_powergating_state(void *handle, 5132 enum amd_powergating_state state) 5133 { 5134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5135 bool enable = (state == AMD_PG_STATE_GATE); 5136 5137 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5138 case IP_VERSION(9, 2, 2): 5139 case IP_VERSION(9, 1, 0): 5140 case IP_VERSION(9, 3, 0): 5141 if (!enable) 5142 amdgpu_gfx_off_ctrl(adev, false); 5143 5144 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5145 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 5146 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 5147 } else { 5148 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 5149 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 5150 } 5151 5152 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5153 gfx_v9_0_enable_cp_power_gating(adev, true); 5154 else 5155 gfx_v9_0_enable_cp_power_gating(adev, false); 5156 5157 /* update gfx cgpg state */ 5158 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 5159 5160 /* update mgcg state */ 5161 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 5162 5163 if (enable) 5164 amdgpu_gfx_off_ctrl(adev, true); 5165 break; 5166 case IP_VERSION(9, 2, 1): 5167 amdgpu_gfx_off_ctrl(adev, enable); 5168 break; 5169 default: 5170 break; 5171 } 5172 5173 return 0; 5174 } 5175 5176 static int gfx_v9_0_set_clockgating_state(void *handle, 5177 enum amd_clockgating_state state) 5178 { 5179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5180 5181 if (amdgpu_sriov_vf(adev)) 5182 return 0; 5183 5184 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5185 case IP_VERSION(9, 0, 1): 5186 case IP_VERSION(9, 2, 1): 5187 case IP_VERSION(9, 4, 0): 5188 case IP_VERSION(9, 2, 2): 5189 case IP_VERSION(9, 1, 0): 5190 case IP_VERSION(9, 4, 1): 5191 case IP_VERSION(9, 3, 0): 5192 case IP_VERSION(9, 4, 2): 5193 gfx_v9_0_update_gfx_clock_gating(adev, 5194 state == AMD_CG_STATE_GATE); 5195 break; 5196 default: 5197 break; 5198 } 5199 return 0; 5200 } 5201 5202 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5203 { 5204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5205 int data; 5206 5207 if (amdgpu_sriov_vf(adev)) 5208 *flags = 0; 5209 5210 /* AMD_CG_SUPPORT_GFX_MGCG */ 5211 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5212 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5213 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5214 5215 /* AMD_CG_SUPPORT_GFX_CGCG */ 5216 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5217 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5218 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5219 5220 /* AMD_CG_SUPPORT_GFX_CGLS */ 5221 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5222 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5223 5224 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5225 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5226 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5227 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5228 5229 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5230 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5231 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5232 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5233 5234 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) { 5235 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5236 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5237 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5238 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5239 5240 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5241 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5242 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5243 } 5244 } 5245 5246 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5247 { 5248 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5249 } 5250 5251 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5252 { 5253 struct amdgpu_device *adev = ring->adev; 5254 u64 wptr; 5255 5256 /* XXX check if swapping is necessary on BE */ 5257 if (ring->use_doorbell) { 5258 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5259 } else { 5260 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5261 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5262 } 5263 5264 return wptr; 5265 } 5266 5267 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5268 { 5269 struct amdgpu_device *adev = ring->adev; 5270 5271 if (ring->use_doorbell) { 5272 /* XXX check if swapping is necessary on BE */ 5273 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5274 WDOORBELL64(ring->doorbell_index, ring->wptr); 5275 } else { 5276 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5277 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5278 } 5279 } 5280 5281 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5282 { 5283 struct amdgpu_device *adev = ring->adev; 5284 u32 ref_and_mask, reg_mem_engine; 5285 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5286 5287 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5288 switch (ring->me) { 5289 case 1: 5290 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5291 break; 5292 case 2: 5293 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5294 break; 5295 default: 5296 return; 5297 } 5298 reg_mem_engine = 0; 5299 } else { 5300 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5301 reg_mem_engine = 1; /* pfp */ 5302 } 5303 5304 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5305 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5306 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5307 ref_and_mask, ref_and_mask, 0x20); 5308 } 5309 5310 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5311 struct amdgpu_job *job, 5312 struct amdgpu_ib *ib, 5313 uint32_t flags) 5314 { 5315 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5316 u32 header, control = 0; 5317 5318 if (ib->flags & AMDGPU_IB_FLAG_CE) 5319 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5320 else 5321 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5322 5323 control |= ib->length_dw | (vmid << 24); 5324 5325 if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 5326 control |= INDIRECT_BUFFER_PRE_ENB(1); 5327 5328 if (flags & AMDGPU_IB_PREEMPTED) 5329 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5330 5331 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5332 gfx_v9_0_ring_emit_de_meta(ring, 5333 (!amdgpu_sriov_vf(ring->adev) && 5334 flags & AMDGPU_IB_PREEMPTED) ? 5335 true : false, 5336 job->gds_size > 0 && job->gds_base != 0); 5337 } 5338 5339 amdgpu_ring_write(ring, header); 5340 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5341 amdgpu_ring_write(ring, 5342 #ifdef __BIG_ENDIAN 5343 (2 << 0) | 5344 #endif 5345 lower_32_bits(ib->gpu_addr)); 5346 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5347 amdgpu_ring_ib_on_emit_cntl(ring); 5348 amdgpu_ring_write(ring, control); 5349 } 5350 5351 static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring, 5352 unsigned offset) 5353 { 5354 u32 control = ring->ring[offset]; 5355 5356 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5357 ring->ring[offset] = control; 5358 } 5359 5360 static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring, 5361 unsigned offset) 5362 { 5363 struct amdgpu_device *adev = ring->adev; 5364 void *ce_payload_cpu_addr; 5365 uint64_t payload_offset, payload_size; 5366 5367 payload_size = sizeof(struct v9_ce_ib_state); 5368 5369 if (ring->is_mes_queue) { 5370 payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5371 gfx[0].gfx_meta_data) + 5372 offsetof(struct v9_gfx_meta_data, ce_payload); 5373 ce_payload_cpu_addr = 5374 amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); 5375 } else { 5376 payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5377 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; 5378 } 5379 5380 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { 5381 memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size); 5382 } else { 5383 memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, 5384 (ring->buf_mask + 1 - offset) << 2); 5385 payload_size -= (ring->buf_mask + 1 - offset) << 2; 5386 memcpy((void *)&ring->ring[0], 5387 ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), 5388 payload_size); 5389 } 5390 } 5391 5392 static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring, 5393 unsigned offset) 5394 { 5395 struct amdgpu_device *adev = ring->adev; 5396 void *de_payload_cpu_addr; 5397 uint64_t payload_offset, payload_size; 5398 5399 payload_size = sizeof(struct v9_de_ib_state); 5400 5401 if (ring->is_mes_queue) { 5402 payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5403 gfx[0].gfx_meta_data) + 5404 offsetof(struct v9_gfx_meta_data, de_payload); 5405 de_payload_cpu_addr = 5406 amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); 5407 } else { 5408 payload_offset = offsetof(struct v9_gfx_meta_data, de_payload); 5409 de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; 5410 } 5411 5412 ((struct v9_de_ib_state *)de_payload_cpu_addr)->ib_completion_status = 5413 IB_COMPLETION_STATUS_PREEMPTED; 5414 5415 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { 5416 memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size); 5417 } else { 5418 memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, 5419 (ring->buf_mask + 1 - offset) << 2); 5420 payload_size -= (ring->buf_mask + 1 - offset) << 2; 5421 memcpy((void *)&ring->ring[0], 5422 de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), 5423 payload_size); 5424 } 5425 } 5426 5427 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5428 struct amdgpu_job *job, 5429 struct amdgpu_ib *ib, 5430 uint32_t flags) 5431 { 5432 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5433 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5434 5435 /* Currently, there is a high possibility to get wave ID mismatch 5436 * between ME and GDS, leading to a hw deadlock, because ME generates 5437 * different wave IDs than the GDS expects. This situation happens 5438 * randomly when at least 5 compute pipes use GDS ordered append. 5439 * The wave IDs generated by ME are also wrong after suspend/resume. 5440 * Those are probably bugs somewhere else in the kernel driver. 5441 * 5442 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5443 * GDS to 0 for this ring (me/pipe). 5444 */ 5445 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5446 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5447 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5448 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5449 } 5450 5451 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5452 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5453 amdgpu_ring_write(ring, 5454 #ifdef __BIG_ENDIAN 5455 (2 << 0) | 5456 #endif 5457 lower_32_bits(ib->gpu_addr)); 5458 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5459 amdgpu_ring_write(ring, control); 5460 } 5461 5462 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5463 u64 seq, unsigned flags) 5464 { 5465 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5466 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5467 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5468 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 5469 uint32_t dw2 = 0; 5470 5471 /* RELEASE_MEM - flush caches, send int */ 5472 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5473 5474 if (writeback) { 5475 dw2 = EOP_TC_NC_ACTION_EN; 5476 } else { 5477 dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | 5478 EOP_TC_MD_ACTION_EN; 5479 } 5480 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5481 EVENT_INDEX(5); 5482 if (exec) 5483 dw2 |= EOP_EXEC; 5484 5485 amdgpu_ring_write(ring, dw2); 5486 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5487 5488 /* 5489 * the address should be Qword aligned if 64bit write, Dword 5490 * aligned if only send 32bit data low (discard data high) 5491 */ 5492 if (write64bit) 5493 BUG_ON(addr & 0x7); 5494 else 5495 BUG_ON(addr & 0x3); 5496 amdgpu_ring_write(ring, lower_32_bits(addr)); 5497 amdgpu_ring_write(ring, upper_32_bits(addr)); 5498 amdgpu_ring_write(ring, lower_32_bits(seq)); 5499 amdgpu_ring_write(ring, upper_32_bits(seq)); 5500 amdgpu_ring_write(ring, 0); 5501 } 5502 5503 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5504 { 5505 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5506 uint32_t seq = ring->fence_drv.sync_seq; 5507 uint64_t addr = ring->fence_drv.gpu_addr; 5508 5509 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5510 lower_32_bits(addr), upper_32_bits(addr), 5511 seq, 0xffffffff, 4); 5512 } 5513 5514 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5515 unsigned vmid, uint64_t pd_addr) 5516 { 5517 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5518 5519 /* compute doesn't have PFP */ 5520 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5521 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5522 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5523 amdgpu_ring_write(ring, 0x0); 5524 } 5525 } 5526 5527 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5528 { 5529 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5530 } 5531 5532 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5533 { 5534 u64 wptr; 5535 5536 /* XXX check if swapping is necessary on BE */ 5537 if (ring->use_doorbell) 5538 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5539 else 5540 BUG(); 5541 return wptr; 5542 } 5543 5544 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5545 { 5546 struct amdgpu_device *adev = ring->adev; 5547 5548 /* XXX check if swapping is necessary on BE */ 5549 if (ring->use_doorbell) { 5550 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5551 WDOORBELL64(ring->doorbell_index, ring->wptr); 5552 } else{ 5553 BUG(); /* only DOORBELL method supported on gfx9 now */ 5554 } 5555 } 5556 5557 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5558 u64 seq, unsigned int flags) 5559 { 5560 struct amdgpu_device *adev = ring->adev; 5561 5562 /* we only allocate 32bit for each seq wb address */ 5563 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5564 5565 /* write fence seq to the "addr" */ 5566 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5567 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5568 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5569 amdgpu_ring_write(ring, lower_32_bits(addr)); 5570 amdgpu_ring_write(ring, upper_32_bits(addr)); 5571 amdgpu_ring_write(ring, lower_32_bits(seq)); 5572 5573 if (flags & AMDGPU_FENCE_FLAG_INT) { 5574 /* set register to trigger INT */ 5575 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5576 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5577 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5578 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5579 amdgpu_ring_write(ring, 0); 5580 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5581 } 5582 } 5583 5584 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5585 { 5586 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5587 amdgpu_ring_write(ring, 0); 5588 } 5589 5590 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 5591 { 5592 struct amdgpu_device *adev = ring->adev; 5593 struct v9_ce_ib_state ce_payload = {0}; 5594 uint64_t offset, ce_payload_gpu_addr; 5595 void *ce_payload_cpu_addr; 5596 int cnt; 5597 5598 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5599 5600 if (ring->is_mes_queue) { 5601 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5602 gfx[0].gfx_meta_data) + 5603 offsetof(struct v9_gfx_meta_data, ce_payload); 5604 ce_payload_gpu_addr = 5605 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5606 ce_payload_cpu_addr = 5607 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5608 } else { 5609 offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5610 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5611 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5612 } 5613 5614 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5615 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5616 WRITE_DATA_DST_SEL(8) | 5617 WR_CONFIRM) | 5618 WRITE_DATA_CACHE_POLICY(0)); 5619 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5620 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5621 5622 amdgpu_ring_ib_on_emit_ce(ring); 5623 5624 if (resume) 5625 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5626 sizeof(ce_payload) >> 2); 5627 else 5628 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 5629 sizeof(ce_payload) >> 2); 5630 } 5631 5632 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 5633 { 5634 int i, r = 0; 5635 struct amdgpu_device *adev = ring->adev; 5636 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5637 struct amdgpu_ring *kiq_ring = &kiq->ring; 5638 unsigned long flags; 5639 5640 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5641 return -EINVAL; 5642 5643 spin_lock_irqsave(&kiq->ring_lock, flags); 5644 5645 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5646 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5647 return -ENOMEM; 5648 } 5649 5650 /* assert preemption condition */ 5651 amdgpu_ring_set_preempt_cond_exec(ring, false); 5652 5653 ring->trail_seq += 1; 5654 amdgpu_ring_alloc(ring, 13); 5655 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5656 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5657 5658 /* assert IB preemption, emit the trailing fence */ 5659 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5660 ring->trail_fence_gpu_addr, 5661 ring->trail_seq); 5662 5663 amdgpu_ring_commit(kiq_ring); 5664 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5665 5666 /* poll the trailing fence */ 5667 for (i = 0; i < adev->usec_timeout; i++) { 5668 if (ring->trail_seq == 5669 le32_to_cpu(*ring->trail_fence_cpu_addr)) 5670 break; 5671 udelay(1); 5672 } 5673 5674 if (i >= adev->usec_timeout) { 5675 r = -EINVAL; 5676 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5677 } 5678 5679 /*reset the CP_VMID_PREEMPT after trailing fence*/ 5680 amdgpu_ring_emit_wreg(ring, 5681 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5682 0x0); 5683 amdgpu_ring_commit(ring); 5684 5685 /* deassert preemption condition */ 5686 amdgpu_ring_set_preempt_cond_exec(ring, true); 5687 return r; 5688 } 5689 5690 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds) 5691 { 5692 struct amdgpu_device *adev = ring->adev; 5693 struct v9_de_ib_state de_payload = {0}; 5694 uint64_t offset, gds_addr, de_payload_gpu_addr; 5695 void *de_payload_cpu_addr; 5696 int cnt; 5697 5698 if (ring->is_mes_queue) { 5699 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5700 gfx[0].gfx_meta_data) + 5701 offsetof(struct v9_gfx_meta_data, de_payload); 5702 de_payload_gpu_addr = 5703 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5704 de_payload_cpu_addr = 5705 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5706 5707 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5708 gfx[0].gds_backup) + 5709 offsetof(struct v9_gfx_meta_data, de_payload); 5710 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5711 } else { 5712 offset = offsetof(struct v9_gfx_meta_data, de_payload); 5713 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5714 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5715 5716 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5717 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5718 PAGE_SIZE); 5719 } 5720 5721 if (usegds) { 5722 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5723 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5724 } 5725 5726 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5727 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5728 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5729 WRITE_DATA_DST_SEL(8) | 5730 WR_CONFIRM) | 5731 WRITE_DATA_CACHE_POLICY(0)); 5732 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5733 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5734 5735 amdgpu_ring_ib_on_emit_de(ring); 5736 if (resume) 5737 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5738 sizeof(de_payload) >> 2); 5739 else 5740 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5741 sizeof(de_payload) >> 2); 5742 } 5743 5744 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5745 bool secure) 5746 { 5747 uint32_t v = secure ? FRAME_TMZ : 0; 5748 5749 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5750 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5751 } 5752 5753 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5754 { 5755 uint32_t dw2 = 0; 5756 5757 gfx_v9_0_ring_emit_ce_meta(ring, 5758 (!amdgpu_sriov_vf(ring->adev) && 5759 flags & AMDGPU_IB_PREEMPTED) ? true : false); 5760 5761 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5762 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5763 /* set load_global_config & load_global_uconfig */ 5764 dw2 |= 0x8001; 5765 /* set load_cs_sh_regs */ 5766 dw2 |= 0x01000000; 5767 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5768 dw2 |= 0x10002; 5769 5770 /* set load_ce_ram if preamble presented */ 5771 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5772 dw2 |= 0x10000000; 5773 } else { 5774 /* still load_ce_ram if this is the first time preamble presented 5775 * although there is no context switch happens. 5776 */ 5777 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5778 dw2 |= 0x10000000; 5779 } 5780 5781 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5782 amdgpu_ring_write(ring, dw2); 5783 amdgpu_ring_write(ring, 0); 5784 } 5785 5786 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5787 uint64_t addr) 5788 { 5789 unsigned ret; 5790 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5791 amdgpu_ring_write(ring, lower_32_bits(addr)); 5792 amdgpu_ring_write(ring, upper_32_bits(addr)); 5793 /* discard following DWs if *cond_exec_gpu_addr==0 */ 5794 amdgpu_ring_write(ring, 0); 5795 ret = ring->wptr & ring->buf_mask; 5796 /* patch dummy value later */ 5797 amdgpu_ring_write(ring, 0); 5798 return ret; 5799 } 5800 5801 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5802 uint32_t reg_val_offs) 5803 { 5804 struct amdgpu_device *adev = ring->adev; 5805 5806 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5807 amdgpu_ring_write(ring, 0 | /* src: register*/ 5808 (5 << 8) | /* dst: memory */ 5809 (1 << 20)); /* write confirm */ 5810 amdgpu_ring_write(ring, reg); 5811 amdgpu_ring_write(ring, 0); 5812 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5813 reg_val_offs * 4)); 5814 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5815 reg_val_offs * 4)); 5816 } 5817 5818 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5819 uint32_t val) 5820 { 5821 uint32_t cmd = 0; 5822 5823 switch (ring->funcs->type) { 5824 case AMDGPU_RING_TYPE_GFX: 5825 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5826 break; 5827 case AMDGPU_RING_TYPE_KIQ: 5828 cmd = (1 << 16); /* no inc addr */ 5829 break; 5830 default: 5831 cmd = WR_CONFIRM; 5832 break; 5833 } 5834 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5835 amdgpu_ring_write(ring, cmd); 5836 amdgpu_ring_write(ring, reg); 5837 amdgpu_ring_write(ring, 0); 5838 amdgpu_ring_write(ring, val); 5839 } 5840 5841 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5842 uint32_t val, uint32_t mask) 5843 { 5844 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5845 } 5846 5847 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5848 uint32_t reg0, uint32_t reg1, 5849 uint32_t ref, uint32_t mask) 5850 { 5851 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5852 struct amdgpu_device *adev = ring->adev; 5853 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5854 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5855 5856 if (fw_version_ok) 5857 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5858 ref, mask, 0x20); 5859 else 5860 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5861 ref, mask); 5862 } 5863 5864 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5865 { 5866 struct amdgpu_device *adev = ring->adev; 5867 uint32_t value = 0; 5868 5869 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5870 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5871 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5872 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5873 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5874 } 5875 5876 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5877 enum amdgpu_interrupt_state state) 5878 { 5879 switch (state) { 5880 case AMDGPU_IRQ_STATE_DISABLE: 5881 case AMDGPU_IRQ_STATE_ENABLE: 5882 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5883 TIME_STAMP_INT_ENABLE, 5884 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5885 break; 5886 default: 5887 break; 5888 } 5889 } 5890 5891 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5892 int me, int pipe, 5893 enum amdgpu_interrupt_state state) 5894 { 5895 u32 mec_int_cntl, mec_int_cntl_reg; 5896 5897 /* 5898 * amdgpu controls only the first MEC. That's why this function only 5899 * handles the setting of interrupts for this specific MEC. All other 5900 * pipes' interrupts are set by amdkfd. 5901 */ 5902 5903 if (me == 1) { 5904 switch (pipe) { 5905 case 0: 5906 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5907 break; 5908 case 1: 5909 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5910 break; 5911 case 2: 5912 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5913 break; 5914 case 3: 5915 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5916 break; 5917 default: 5918 DRM_DEBUG("invalid pipe %d\n", pipe); 5919 return; 5920 } 5921 } else { 5922 DRM_DEBUG("invalid me %d\n", me); 5923 return; 5924 } 5925 5926 switch (state) { 5927 case AMDGPU_IRQ_STATE_DISABLE: 5928 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5929 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5930 TIME_STAMP_INT_ENABLE, 0); 5931 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5932 break; 5933 case AMDGPU_IRQ_STATE_ENABLE: 5934 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5935 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5936 TIME_STAMP_INT_ENABLE, 1); 5937 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5938 break; 5939 default: 5940 break; 5941 } 5942 } 5943 5944 static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5945 int me, int pipe) 5946 { 5947 /* 5948 * amdgpu controls only the first MEC. That's why this function only 5949 * handles the setting of interrupts for this specific MEC. All other 5950 * pipes' interrupts are set by amdkfd. 5951 */ 5952 if (me != 1) 5953 return 0; 5954 5955 switch (pipe) { 5956 case 0: 5957 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5958 case 1: 5959 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5960 case 2: 5961 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5962 case 3: 5963 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5964 default: 5965 return 0; 5966 } 5967 } 5968 5969 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5970 struct amdgpu_irq_src *source, 5971 unsigned type, 5972 enum amdgpu_interrupt_state state) 5973 { 5974 u32 cp_int_cntl_reg, cp_int_cntl; 5975 int i, j; 5976 5977 switch (state) { 5978 case AMDGPU_IRQ_STATE_DISABLE: 5979 case AMDGPU_IRQ_STATE_ENABLE: 5980 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5981 PRIV_REG_INT_ENABLE, 5982 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5983 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5984 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5985 /* MECs start at 1 */ 5986 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); 5987 5988 if (cp_int_cntl_reg) { 5989 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5990 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5991 PRIV_REG_INT_ENABLE, 5992 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5993 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5994 } 5995 } 5996 } 5997 break; 5998 default: 5999 break; 6000 } 6001 6002 return 0; 6003 } 6004 6005 static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6006 struct amdgpu_irq_src *source, 6007 unsigned type, 6008 enum amdgpu_interrupt_state state) 6009 { 6010 u32 cp_int_cntl_reg, cp_int_cntl; 6011 int i, j; 6012 6013 switch (state) { 6014 case AMDGPU_IRQ_STATE_DISABLE: 6015 case AMDGPU_IRQ_STATE_ENABLE: 6016 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 6017 OPCODE_ERROR_INT_ENABLE, 6018 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6019 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6020 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6021 /* MECs start at 1 */ 6022 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); 6023 6024 if (cp_int_cntl_reg) { 6025 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6026 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6027 OPCODE_ERROR_INT_ENABLE, 6028 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6029 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6030 } 6031 } 6032 } 6033 break; 6034 default: 6035 break; 6036 } 6037 6038 return 0; 6039 } 6040 6041 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6042 struct amdgpu_irq_src *source, 6043 unsigned type, 6044 enum amdgpu_interrupt_state state) 6045 { 6046 switch (state) { 6047 case AMDGPU_IRQ_STATE_DISABLE: 6048 case AMDGPU_IRQ_STATE_ENABLE: 6049 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 6050 PRIV_INSTR_INT_ENABLE, 6051 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6052 break; 6053 default: 6054 break; 6055 } 6056 6057 return 0; 6058 } 6059 6060 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 6061 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 6062 CP_ECC_ERROR_INT_ENABLE, 1) 6063 6064 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 6065 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 6066 CP_ECC_ERROR_INT_ENABLE, 0) 6067 6068 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 6069 struct amdgpu_irq_src *source, 6070 unsigned type, 6071 enum amdgpu_interrupt_state state) 6072 { 6073 switch (state) { 6074 case AMDGPU_IRQ_STATE_DISABLE: 6075 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 6076 CP_ECC_ERROR_INT_ENABLE, 0); 6077 DISABLE_ECC_ON_ME_PIPE(1, 0); 6078 DISABLE_ECC_ON_ME_PIPE(1, 1); 6079 DISABLE_ECC_ON_ME_PIPE(1, 2); 6080 DISABLE_ECC_ON_ME_PIPE(1, 3); 6081 break; 6082 6083 case AMDGPU_IRQ_STATE_ENABLE: 6084 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 6085 CP_ECC_ERROR_INT_ENABLE, 1); 6086 ENABLE_ECC_ON_ME_PIPE(1, 0); 6087 ENABLE_ECC_ON_ME_PIPE(1, 1); 6088 ENABLE_ECC_ON_ME_PIPE(1, 2); 6089 ENABLE_ECC_ON_ME_PIPE(1, 3); 6090 break; 6091 default: 6092 break; 6093 } 6094 6095 return 0; 6096 } 6097 6098 6099 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6100 struct amdgpu_irq_src *src, 6101 unsigned type, 6102 enum amdgpu_interrupt_state state) 6103 { 6104 switch (type) { 6105 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6106 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 6107 break; 6108 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6109 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6110 break; 6111 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6112 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6113 break; 6114 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6115 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6116 break; 6117 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6118 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6119 break; 6120 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 6121 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 6122 break; 6123 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 6124 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 6125 break; 6126 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 6127 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 6128 break; 6129 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 6130 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 6131 break; 6132 default: 6133 break; 6134 } 6135 return 0; 6136 } 6137 6138 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 6139 struct amdgpu_irq_src *source, 6140 struct amdgpu_iv_entry *entry) 6141 { 6142 int i; 6143 u8 me_id, pipe_id, queue_id; 6144 struct amdgpu_ring *ring; 6145 6146 DRM_DEBUG("IH: CP EOP\n"); 6147 me_id = (entry->ring_id & 0x0c) >> 2; 6148 pipe_id = (entry->ring_id & 0x03) >> 0; 6149 queue_id = (entry->ring_id & 0x70) >> 4; 6150 6151 switch (me_id) { 6152 case 0: 6153 if (adev->gfx.num_gfx_rings) { 6154 if (!adev->gfx.mcbp) { 6155 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6156 } else if (!amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { 6157 /* Fence signals are handled on the software rings*/ 6158 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 6159 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); 6160 } 6161 } 6162 break; 6163 case 1: 6164 case 2: 6165 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6166 ring = &adev->gfx.compute_ring[i]; 6167 /* Per-queue interrupt is supported for MEC starting from VI. 6168 * The interrupt can only be enabled/disabled per pipe instead of per queue. 6169 */ 6170 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 6171 amdgpu_fence_process(ring); 6172 } 6173 break; 6174 } 6175 return 0; 6176 } 6177 6178 static void gfx_v9_0_fault(struct amdgpu_device *adev, 6179 struct amdgpu_iv_entry *entry) 6180 { 6181 u8 me_id, pipe_id, queue_id; 6182 struct amdgpu_ring *ring; 6183 int i; 6184 6185 me_id = (entry->ring_id & 0x0c) >> 2; 6186 pipe_id = (entry->ring_id & 0x03) >> 0; 6187 queue_id = (entry->ring_id & 0x70) >> 4; 6188 6189 switch (me_id) { 6190 case 0: 6191 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 6192 break; 6193 case 1: 6194 case 2: 6195 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6196 ring = &adev->gfx.compute_ring[i]; 6197 if (ring->me == me_id && ring->pipe == pipe_id && 6198 ring->queue == queue_id) 6199 drm_sched_fault(&ring->sched); 6200 } 6201 break; 6202 } 6203 } 6204 6205 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 6206 struct amdgpu_irq_src *source, 6207 struct amdgpu_iv_entry *entry) 6208 { 6209 DRM_ERROR("Illegal register access in command stream\n"); 6210 gfx_v9_0_fault(adev, entry); 6211 return 0; 6212 } 6213 6214 static int gfx_v9_0_bad_op_irq(struct amdgpu_device *adev, 6215 struct amdgpu_irq_src *source, 6216 struct amdgpu_iv_entry *entry) 6217 { 6218 DRM_ERROR("Illegal opcode in command stream\n"); 6219 gfx_v9_0_fault(adev, entry); 6220 return 0; 6221 } 6222 6223 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 6224 struct amdgpu_irq_src *source, 6225 struct amdgpu_iv_entry *entry) 6226 { 6227 DRM_ERROR("Illegal instruction in command stream\n"); 6228 gfx_v9_0_fault(adev, entry); 6229 return 0; 6230 } 6231 6232 6233 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 6234 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 6235 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 6236 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 6237 }, 6238 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 6239 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 6240 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 6241 }, 6242 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 6243 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 6244 0, 0 6245 }, 6246 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 6247 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 6248 0, 0 6249 }, 6250 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 6251 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 6252 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 6253 }, 6254 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 6255 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 6256 0, 0 6257 }, 6258 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 6259 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 6260 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 6261 }, 6262 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 6263 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 6264 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 6265 }, 6266 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 6267 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 6268 0, 0 6269 }, 6270 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 6271 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 6272 0, 0 6273 }, 6274 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 6275 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 6276 0, 0 6277 }, 6278 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 6279 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 6280 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 6281 }, 6282 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 6283 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 6284 0, 0 6285 }, 6286 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6287 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 6288 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 6289 }, 6290 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 6291 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6292 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 6293 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 6294 }, 6295 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 6296 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6297 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 6298 0, 0 6299 }, 6300 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 6301 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6302 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 6303 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 6304 }, 6305 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 6306 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6307 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 6308 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 6309 }, 6310 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 6311 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6312 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 6313 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 6314 }, 6315 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 6316 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6317 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 6318 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 6319 }, 6320 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 6321 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 6322 0, 0 6323 }, 6324 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6325 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 6326 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 6327 }, 6328 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6329 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 6330 0, 0 6331 }, 6332 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6333 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 6334 0, 0 6335 }, 6336 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6337 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 6338 0, 0 6339 }, 6340 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6341 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 6342 0, 0 6343 }, 6344 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6345 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 6346 0, 0 6347 }, 6348 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6349 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 6350 0, 0 6351 }, 6352 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6353 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 6354 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 6355 }, 6356 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6357 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 6358 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 6359 }, 6360 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6361 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 6362 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 6363 }, 6364 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6365 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6366 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6367 }, 6368 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6369 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6370 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6371 }, 6372 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6373 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6374 0, 0 6375 }, 6376 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6377 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6378 0, 0 6379 }, 6380 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6381 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6382 0, 0 6383 }, 6384 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6385 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6386 0, 0 6387 }, 6388 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6389 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6390 0, 0 6391 }, 6392 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6393 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6394 0, 0 6395 }, 6396 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6397 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6398 0, 0 6399 }, 6400 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6401 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6402 0, 0 6403 }, 6404 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6405 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6406 0, 0 6407 }, 6408 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6409 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6410 0, 0 6411 }, 6412 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6413 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6414 0, 0 6415 }, 6416 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6417 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6418 0, 0 6419 }, 6420 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6421 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6422 0, 0 6423 }, 6424 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6425 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6426 0, 0 6427 }, 6428 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6429 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6430 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6431 }, 6432 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6433 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6434 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6435 }, 6436 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6437 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6438 0, 0 6439 }, 6440 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6441 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6442 0, 0 6443 }, 6444 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6445 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6446 0, 0 6447 }, 6448 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6449 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6450 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6451 }, 6452 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6453 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6454 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6455 }, 6456 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6457 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6458 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6459 }, 6460 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6461 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6462 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6463 }, 6464 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6465 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6466 0, 0 6467 }, 6468 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6469 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6470 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6471 }, 6472 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6473 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6474 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6475 }, 6476 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6477 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6478 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6479 }, 6480 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6481 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6482 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6483 }, 6484 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6485 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6486 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6487 }, 6488 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6489 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6490 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6491 }, 6492 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6493 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6494 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6495 }, 6496 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6497 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6498 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6499 }, 6500 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6501 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6502 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6503 }, 6504 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6505 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6506 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6507 }, 6508 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6509 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6510 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6511 }, 6512 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6513 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6514 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6515 }, 6516 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6517 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6518 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6519 }, 6520 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6521 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6522 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6523 }, 6524 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6525 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6526 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6527 }, 6528 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6529 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6530 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6531 }, 6532 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6533 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6534 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6535 }, 6536 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6537 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6538 0, 0 6539 }, 6540 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6541 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6542 0, 0 6543 }, 6544 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6545 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6546 0, 0 6547 }, 6548 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6549 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6550 0, 0 6551 }, 6552 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6553 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6554 0, 0 6555 }, 6556 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6557 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6558 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6559 }, 6560 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6561 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6562 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6563 }, 6564 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6565 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6566 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6567 }, 6568 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6569 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6570 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6571 }, 6572 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6573 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6574 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6575 }, 6576 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6577 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6578 0, 0 6579 }, 6580 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6581 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6582 0, 0 6583 }, 6584 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6585 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6586 0, 0 6587 }, 6588 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6589 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6590 0, 0 6591 }, 6592 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6593 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6594 0, 0 6595 }, 6596 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6597 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6598 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6599 }, 6600 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6601 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6602 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6603 }, 6604 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6605 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6606 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6607 }, 6608 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6609 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6610 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6611 }, 6612 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6613 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6614 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6615 }, 6616 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6617 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6618 0, 0 6619 }, 6620 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6621 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6622 0, 0 6623 }, 6624 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6625 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6626 0, 0 6627 }, 6628 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6629 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6630 0, 0 6631 }, 6632 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6633 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6634 0, 0 6635 }, 6636 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6637 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6638 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6639 }, 6640 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6641 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6642 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6643 }, 6644 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6645 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6646 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6647 }, 6648 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6649 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6650 0, 0 6651 }, 6652 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6653 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6654 0, 0 6655 }, 6656 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6657 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6658 0, 0 6659 }, 6660 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6661 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6662 0, 0 6663 }, 6664 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6665 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6666 0, 0 6667 }, 6668 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6669 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6670 0, 0 6671 } 6672 }; 6673 6674 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6675 void *inject_if, uint32_t instance_mask) 6676 { 6677 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6678 int ret; 6679 struct ta_ras_trigger_error_input block_info = { 0 }; 6680 6681 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6682 return -EINVAL; 6683 6684 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6685 return -EINVAL; 6686 6687 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6688 return -EPERM; 6689 6690 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6691 info->head.type)) { 6692 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6693 ras_gfx_subblocks[info->head.sub_block_index].name, 6694 info->head.type); 6695 return -EPERM; 6696 } 6697 6698 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6699 info->head.type)) { 6700 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6701 ras_gfx_subblocks[info->head.sub_block_index].name, 6702 info->head.type); 6703 return -EPERM; 6704 } 6705 6706 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6707 block_info.sub_block_index = 6708 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6709 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6710 block_info.address = info->address; 6711 block_info.value = info->value; 6712 6713 mutex_lock(&adev->grbm_idx_mutex); 6714 ret = psp_ras_trigger_error(&adev->psp, &block_info, instance_mask); 6715 mutex_unlock(&adev->grbm_idx_mutex); 6716 6717 return ret; 6718 } 6719 6720 static const char * const vml2_mems[] = { 6721 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6722 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6723 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6724 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6725 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6726 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6727 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6728 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6729 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6730 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6731 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6732 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6733 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6734 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6735 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6736 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6737 }; 6738 6739 static const char * const vml2_walker_mems[] = { 6740 "UTC_VML2_CACHE_PDE0_MEM0", 6741 "UTC_VML2_CACHE_PDE0_MEM1", 6742 "UTC_VML2_CACHE_PDE1_MEM0", 6743 "UTC_VML2_CACHE_PDE1_MEM1", 6744 "UTC_VML2_CACHE_PDE2_MEM0", 6745 "UTC_VML2_CACHE_PDE2_MEM1", 6746 "UTC_VML2_RDIF_LOG_FIFO", 6747 }; 6748 6749 static const char * const atc_l2_cache_2m_mems[] = { 6750 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6751 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6752 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6753 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6754 }; 6755 6756 static const char *atc_l2_cache_4k_mems[] = { 6757 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6758 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6759 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6760 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6761 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6762 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6763 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6764 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6765 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6766 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6767 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6768 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6769 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6770 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6771 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6772 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6773 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6774 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6775 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6776 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6777 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6778 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6779 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6780 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6781 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6782 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6783 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6784 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6785 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6786 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6787 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6788 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6789 }; 6790 6791 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6792 struct ras_err_data *err_data) 6793 { 6794 uint32_t i, data; 6795 uint32_t sec_count, ded_count; 6796 6797 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6798 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6799 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6800 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6801 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6802 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6803 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6804 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6805 6806 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6807 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6808 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6809 6810 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6811 if (sec_count) { 6812 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6813 "SEC %d\n", i, vml2_mems[i], sec_count); 6814 err_data->ce_count += sec_count; 6815 } 6816 6817 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6818 if (ded_count) { 6819 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6820 "DED %d\n", i, vml2_mems[i], ded_count); 6821 err_data->ue_count += ded_count; 6822 } 6823 } 6824 6825 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6826 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6827 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6828 6829 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6830 SEC_COUNT); 6831 if (sec_count) { 6832 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6833 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6834 err_data->ce_count += sec_count; 6835 } 6836 6837 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6838 DED_COUNT); 6839 if (ded_count) { 6840 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6841 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6842 err_data->ue_count += ded_count; 6843 } 6844 } 6845 6846 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6847 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6848 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6849 6850 sec_count = (data & 0x00006000L) >> 0xd; 6851 if (sec_count) { 6852 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6853 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6854 sec_count); 6855 err_data->ce_count += sec_count; 6856 } 6857 } 6858 6859 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6860 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6861 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6862 6863 sec_count = (data & 0x00006000L) >> 0xd; 6864 if (sec_count) { 6865 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6866 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6867 sec_count); 6868 err_data->ce_count += sec_count; 6869 } 6870 6871 ded_count = (data & 0x00018000L) >> 0xf; 6872 if (ded_count) { 6873 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6874 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6875 ded_count); 6876 err_data->ue_count += ded_count; 6877 } 6878 } 6879 6880 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6881 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6882 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6883 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6884 6885 return 0; 6886 } 6887 6888 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6889 const struct soc15_reg_entry *reg, 6890 uint32_t se_id, uint32_t inst_id, uint32_t value, 6891 uint32_t *sec_count, uint32_t *ded_count) 6892 { 6893 uint32_t i; 6894 uint32_t sec_cnt, ded_cnt; 6895 6896 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6897 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6898 gfx_v9_0_ras_fields[i].seg != reg->seg || 6899 gfx_v9_0_ras_fields[i].inst != reg->inst) 6900 continue; 6901 6902 sec_cnt = (value & 6903 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6904 gfx_v9_0_ras_fields[i].sec_count_shift; 6905 if (sec_cnt) { 6906 dev_info(adev->dev, "GFX SubBlock %s, " 6907 "Instance[%d][%d], SEC %d\n", 6908 gfx_v9_0_ras_fields[i].name, 6909 se_id, inst_id, 6910 sec_cnt); 6911 *sec_count += sec_cnt; 6912 } 6913 6914 ded_cnt = (value & 6915 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6916 gfx_v9_0_ras_fields[i].ded_count_shift; 6917 if (ded_cnt) { 6918 dev_info(adev->dev, "GFX SubBlock %s, " 6919 "Instance[%d][%d], DED %d\n", 6920 gfx_v9_0_ras_fields[i].name, 6921 se_id, inst_id, 6922 ded_cnt); 6923 *ded_count += ded_cnt; 6924 } 6925 } 6926 6927 return 0; 6928 } 6929 6930 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6931 { 6932 int i, j, k; 6933 6934 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6935 return; 6936 6937 /* read back registers to clear the counters */ 6938 mutex_lock(&adev->grbm_idx_mutex); 6939 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6940 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6941 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6942 amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0); 6943 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6944 } 6945 } 6946 } 6947 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6948 mutex_unlock(&adev->grbm_idx_mutex); 6949 6950 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6951 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6952 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6953 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6954 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6955 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6956 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6957 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6958 6959 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6960 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6961 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6962 } 6963 6964 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6965 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6966 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6967 } 6968 6969 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6970 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6971 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6972 } 6973 6974 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6975 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6976 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6977 } 6978 6979 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6980 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6981 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6982 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6983 } 6984 6985 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6986 void *ras_error_status) 6987 { 6988 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6989 uint32_t sec_count = 0, ded_count = 0; 6990 uint32_t i, j, k; 6991 uint32_t reg_value; 6992 6993 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6994 return; 6995 6996 err_data->ue_count = 0; 6997 err_data->ce_count = 0; 6998 6999 mutex_lock(&adev->grbm_idx_mutex); 7000 7001 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 7002 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 7003 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 7004 amdgpu_gfx_select_se_sh(adev, j, 0, k, 0); 7005 reg_value = 7006 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 7007 if (reg_value) 7008 gfx_v9_0_ras_error_count(adev, 7009 &gfx_v9_0_edc_counter_regs[i], 7010 j, k, reg_value, 7011 &sec_count, &ded_count); 7012 } 7013 } 7014 } 7015 7016 err_data->ce_count += sec_count; 7017 err_data->ue_count += ded_count; 7018 7019 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7020 mutex_unlock(&adev->grbm_idx_mutex); 7021 7022 gfx_v9_0_query_utc_edc_status(adev, err_data); 7023 } 7024 7025 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 7026 { 7027 const unsigned int cp_coher_cntl = 7028 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 7029 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 7030 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 7031 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 7032 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 7033 7034 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 7035 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 7036 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 7037 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 7038 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 7039 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 7040 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 7041 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 7042 } 7043 7044 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 7045 uint32_t pipe, bool enable) 7046 { 7047 struct amdgpu_device *adev = ring->adev; 7048 uint32_t val; 7049 uint32_t wcl_cs_reg; 7050 7051 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 7052 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 7053 7054 switch (pipe) { 7055 case 0: 7056 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 7057 break; 7058 case 1: 7059 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 7060 break; 7061 case 2: 7062 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 7063 break; 7064 case 3: 7065 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 7066 break; 7067 default: 7068 DRM_DEBUG("invalid pipe %d\n", pipe); 7069 return; 7070 } 7071 7072 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 7073 7074 } 7075 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 7076 { 7077 struct amdgpu_device *adev = ring->adev; 7078 uint32_t val; 7079 int i; 7080 7081 7082 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 7083 * number of gfx waves. Setting 5 bit will make sure gfx only gets 7084 * around 25% of gpu resources. 7085 */ 7086 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 7087 amdgpu_ring_emit_wreg(ring, 7088 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 7089 val); 7090 7091 /* Restrict waves for normal/low priority compute queues as well 7092 * to get best QoS for high priority compute jobs. 7093 * 7094 * amdgpu controls only 1st ME(0-3 CS pipes). 7095 */ 7096 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 7097 if (i != ring->pipe) 7098 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 7099 7100 } 7101 } 7102 7103 static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 7104 { 7105 int i; 7106 7107 /* Header itself is a NOP packet */ 7108 if (num_nop == 1) { 7109 amdgpu_ring_write(ring, ring->funcs->nop); 7110 return; 7111 } 7112 7113 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 7114 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 7115 7116 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 7117 for (i = 1; i < num_nop; i++) 7118 amdgpu_ring_write(ring, ring->funcs->nop); 7119 } 7120 7121 static void gfx_v9_ip_print(void *handle, struct drm_printer *p) 7122 { 7123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7124 uint32_t i, j, k, reg, index = 0; 7125 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9); 7126 7127 if (!adev->gfx.ip_dump_core) 7128 return; 7129 7130 for (i = 0; i < reg_count; i++) 7131 drm_printf(p, "%-50s \t 0x%08x\n", 7132 gc_reg_list_9[i].reg_name, 7133 adev->gfx.ip_dump_core[i]); 7134 7135 /* print compute queue registers for all instances */ 7136 if (!adev->gfx.ip_dump_compute_queues) 7137 return; 7138 7139 reg_count = ARRAY_SIZE(gc_cp_reg_list_9); 7140 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 7141 adev->gfx.mec.num_mec, 7142 adev->gfx.mec.num_pipe_per_mec, 7143 adev->gfx.mec.num_queue_per_pipe); 7144 7145 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7146 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7147 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7148 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 7149 for (reg = 0; reg < reg_count; reg++) { 7150 drm_printf(p, "%-50s \t 0x%08x\n", 7151 gc_cp_reg_list_9[reg].reg_name, 7152 adev->gfx.ip_dump_compute_queues[index + reg]); 7153 } 7154 index += reg_count; 7155 } 7156 } 7157 } 7158 7159 } 7160 7161 static void gfx_v9_ip_dump(void *handle) 7162 { 7163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7164 uint32_t i, j, k, reg, index = 0; 7165 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9); 7166 7167 if (!adev->gfx.ip_dump_core || !adev->gfx.num_gfx_rings) 7168 return; 7169 7170 amdgpu_gfx_off_ctrl(adev, false); 7171 for (i = 0; i < reg_count; i++) 7172 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); 7173 amdgpu_gfx_off_ctrl(adev, true); 7174 7175 /* dump compute queue registers for all instances */ 7176 if (!adev->gfx.ip_dump_compute_queues) 7177 return; 7178 7179 reg_count = ARRAY_SIZE(gc_cp_reg_list_9); 7180 amdgpu_gfx_off_ctrl(adev, false); 7181 mutex_lock(&adev->srbm_mutex); 7182 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7183 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7184 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7185 /* ME0 is for GFX so start from 1 for CP */ 7186 soc15_grbm_select(adev, 1 + i, j, k, 0, 0); 7187 7188 for (reg = 0; reg < reg_count; reg++) { 7189 adev->gfx.ip_dump_compute_queues[index + reg] = 7190 RREG32(SOC15_REG_ENTRY_OFFSET( 7191 gc_cp_reg_list_9[reg])); 7192 } 7193 index += reg_count; 7194 } 7195 } 7196 } 7197 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 7198 mutex_unlock(&adev->srbm_mutex); 7199 amdgpu_gfx_off_ctrl(adev, true); 7200 7201 } 7202 7203 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 7204 .name = "gfx_v9_0", 7205 .early_init = gfx_v9_0_early_init, 7206 .late_init = gfx_v9_0_late_init, 7207 .sw_init = gfx_v9_0_sw_init, 7208 .sw_fini = gfx_v9_0_sw_fini, 7209 .hw_init = gfx_v9_0_hw_init, 7210 .hw_fini = gfx_v9_0_hw_fini, 7211 .suspend = gfx_v9_0_suspend, 7212 .resume = gfx_v9_0_resume, 7213 .is_idle = gfx_v9_0_is_idle, 7214 .wait_for_idle = gfx_v9_0_wait_for_idle, 7215 .soft_reset = gfx_v9_0_soft_reset, 7216 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 7217 .set_powergating_state = gfx_v9_0_set_powergating_state, 7218 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 7219 .dump_ip_state = gfx_v9_ip_dump, 7220 .print_ip_state = gfx_v9_ip_print, 7221 }; 7222 7223 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 7224 .type = AMDGPU_RING_TYPE_GFX, 7225 .align_mask = 0xff, 7226 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7227 .support_64bit_ptrs = true, 7228 .secure_submission_supported = true, 7229 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 7230 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 7231 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 7232 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 7233 5 + /* COND_EXEC */ 7234 7 + /* PIPELINE_SYNC */ 7235 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7236 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7237 2 + /* VM_FLUSH */ 7238 8 + /* FENCE for VM_FLUSH */ 7239 20 + /* GDS switch */ 7240 4 + /* double SWITCH_BUFFER, 7241 the first COND_EXEC jump to the place just 7242 prior to this double SWITCH_BUFFER */ 7243 5 + /* COND_EXEC */ 7244 7 + /* HDP_flush */ 7245 4 + /* VGT_flush */ 7246 14 + /* CE_META */ 7247 31 + /* DE_META */ 7248 3 + /* CNTX_CTRL */ 7249 5 + /* HDP_INVL */ 7250 8 + 8 + /* FENCE x2 */ 7251 2 + /* SWITCH_BUFFER */ 7252 7, /* gfx_v9_0_emit_mem_sync */ 7253 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 7254 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 7255 .emit_fence = gfx_v9_0_ring_emit_fence, 7256 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 7257 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 7258 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 7259 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 7260 .test_ring = gfx_v9_0_ring_test_ring, 7261 .insert_nop = gfx_v9_ring_insert_nop, 7262 .pad_ib = amdgpu_ring_generic_pad_ib, 7263 .emit_switch_buffer = gfx_v9_ring_emit_sb, 7264 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 7265 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 7266 .preempt_ib = gfx_v9_0_ring_preempt_ib, 7267 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 7268 .emit_wreg = gfx_v9_0_ring_emit_wreg, 7269 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 7270 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 7271 .soft_recovery = gfx_v9_0_ring_soft_recovery, 7272 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 7273 }; 7274 7275 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 7276 .type = AMDGPU_RING_TYPE_GFX, 7277 .align_mask = 0xff, 7278 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7279 .support_64bit_ptrs = true, 7280 .secure_submission_supported = true, 7281 .get_rptr = amdgpu_sw_ring_get_rptr_gfx, 7282 .get_wptr = amdgpu_sw_ring_get_wptr_gfx, 7283 .set_wptr = amdgpu_sw_ring_set_wptr_gfx, 7284 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 7285 5 + /* COND_EXEC */ 7286 7 + /* PIPELINE_SYNC */ 7287 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7288 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7289 2 + /* VM_FLUSH */ 7290 8 + /* FENCE for VM_FLUSH */ 7291 20 + /* GDS switch */ 7292 4 + /* double SWITCH_BUFFER, 7293 * the first COND_EXEC jump to the place just 7294 * prior to this double SWITCH_BUFFER 7295 */ 7296 5 + /* COND_EXEC */ 7297 7 + /* HDP_flush */ 7298 4 + /* VGT_flush */ 7299 14 + /* CE_META */ 7300 31 + /* DE_META */ 7301 3 + /* CNTX_CTRL */ 7302 5 + /* HDP_INVL */ 7303 8 + 8 + /* FENCE x2 */ 7304 2 + /* SWITCH_BUFFER */ 7305 7, /* gfx_v9_0_emit_mem_sync */ 7306 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 7307 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 7308 .emit_fence = gfx_v9_0_ring_emit_fence, 7309 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 7310 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 7311 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 7312 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 7313 .test_ring = gfx_v9_0_ring_test_ring, 7314 .test_ib = gfx_v9_0_ring_test_ib, 7315 .insert_nop = gfx_v9_ring_insert_nop, 7316 .pad_ib = amdgpu_ring_generic_pad_ib, 7317 .emit_switch_buffer = gfx_v9_ring_emit_sb, 7318 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 7319 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 7320 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 7321 .emit_wreg = gfx_v9_0_ring_emit_wreg, 7322 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 7323 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 7324 .soft_recovery = gfx_v9_0_ring_soft_recovery, 7325 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 7326 .patch_cntl = gfx_v9_0_ring_patch_cntl, 7327 .patch_de = gfx_v9_0_ring_patch_de_meta, 7328 .patch_ce = gfx_v9_0_ring_patch_ce_meta, 7329 }; 7330 7331 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 7332 .type = AMDGPU_RING_TYPE_COMPUTE, 7333 .align_mask = 0xff, 7334 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7335 .support_64bit_ptrs = true, 7336 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 7337 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 7338 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 7339 .emit_frame_size = 7340 20 + /* gfx_v9_0_ring_emit_gds_switch */ 7341 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 7342 5 + /* hdp invalidate */ 7343 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 7344 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7345 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7346 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 7347 7 + /* gfx_v9_0_emit_mem_sync */ 7348 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 7349 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 7350 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 7351 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 7352 .emit_fence = gfx_v9_0_ring_emit_fence, 7353 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 7354 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 7355 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 7356 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 7357 .test_ring = gfx_v9_0_ring_test_ring, 7358 .test_ib = gfx_v9_0_ring_test_ib, 7359 .insert_nop = gfx_v9_ring_insert_nop, 7360 .pad_ib = amdgpu_ring_generic_pad_ib, 7361 .emit_wreg = gfx_v9_0_ring_emit_wreg, 7362 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 7363 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 7364 .soft_recovery = gfx_v9_0_ring_soft_recovery, 7365 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 7366 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 7367 }; 7368 7369 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 7370 .type = AMDGPU_RING_TYPE_KIQ, 7371 .align_mask = 0xff, 7372 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7373 .support_64bit_ptrs = true, 7374 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 7375 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 7376 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 7377 .emit_frame_size = 7378 20 + /* gfx_v9_0_ring_emit_gds_switch */ 7379 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 7380 5 + /* hdp invalidate */ 7381 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 7382 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7383 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7384 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7385 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 7386 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 7387 .test_ring = gfx_v9_0_ring_test_ring, 7388 .insert_nop = amdgpu_ring_insert_nop, 7389 .pad_ib = amdgpu_ring_generic_pad_ib, 7390 .emit_rreg = gfx_v9_0_ring_emit_rreg, 7391 .emit_wreg = gfx_v9_0_ring_emit_wreg, 7392 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 7393 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 7394 }; 7395 7396 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 7397 { 7398 int i; 7399 7400 adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; 7401 7402 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7403 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 7404 7405 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { 7406 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 7407 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; 7408 } 7409 7410 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7411 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 7412 } 7413 7414 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 7415 .set = gfx_v9_0_set_eop_interrupt_state, 7416 .process = gfx_v9_0_eop_irq, 7417 }; 7418 7419 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 7420 .set = gfx_v9_0_set_priv_reg_fault_state, 7421 .process = gfx_v9_0_priv_reg_irq, 7422 }; 7423 7424 static const struct amdgpu_irq_src_funcs gfx_v9_0_bad_op_irq_funcs = { 7425 .set = gfx_v9_0_set_bad_op_fault_state, 7426 .process = gfx_v9_0_bad_op_irq, 7427 }; 7428 7429 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 7430 .set = gfx_v9_0_set_priv_inst_fault_state, 7431 .process = gfx_v9_0_priv_inst_irq, 7432 }; 7433 7434 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 7435 .set = gfx_v9_0_set_cp_ecc_error_state, 7436 .process = amdgpu_gfx_cp_ecc_error_irq, 7437 }; 7438 7439 7440 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 7441 { 7442 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7443 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 7444 7445 adev->gfx.priv_reg_irq.num_types = 1; 7446 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 7447 7448 adev->gfx.bad_op_irq.num_types = 1; 7449 adev->gfx.bad_op_irq.funcs = &gfx_v9_0_bad_op_irq_funcs; 7450 7451 adev->gfx.priv_inst_irq.num_types = 1; 7452 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 7453 7454 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 7455 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 7456 } 7457 7458 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 7459 { 7460 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7461 case IP_VERSION(9, 0, 1): 7462 case IP_VERSION(9, 2, 1): 7463 case IP_VERSION(9, 4, 0): 7464 case IP_VERSION(9, 2, 2): 7465 case IP_VERSION(9, 1, 0): 7466 case IP_VERSION(9, 4, 1): 7467 case IP_VERSION(9, 3, 0): 7468 case IP_VERSION(9, 4, 2): 7469 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 7470 break; 7471 default: 7472 break; 7473 } 7474 } 7475 7476 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 7477 { 7478 /* init asci gds info */ 7479 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7480 case IP_VERSION(9, 0, 1): 7481 case IP_VERSION(9, 2, 1): 7482 case IP_VERSION(9, 4, 0): 7483 adev->gds.gds_size = 0x10000; 7484 break; 7485 case IP_VERSION(9, 2, 2): 7486 case IP_VERSION(9, 1, 0): 7487 case IP_VERSION(9, 4, 1): 7488 adev->gds.gds_size = 0x1000; 7489 break; 7490 case IP_VERSION(9, 4, 2): 7491 /* aldebaran removed all the GDS internal memory, 7492 * only support GWS opcode in kernel, like barrier 7493 * semaphore.etc */ 7494 adev->gds.gds_size = 0; 7495 break; 7496 default: 7497 adev->gds.gds_size = 0x10000; 7498 break; 7499 } 7500 7501 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7502 case IP_VERSION(9, 0, 1): 7503 case IP_VERSION(9, 4, 0): 7504 adev->gds.gds_compute_max_wave_id = 0x7ff; 7505 break; 7506 case IP_VERSION(9, 2, 1): 7507 adev->gds.gds_compute_max_wave_id = 0x27f; 7508 break; 7509 case IP_VERSION(9, 2, 2): 7510 case IP_VERSION(9, 1, 0): 7511 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 7512 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 7513 else 7514 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 7515 break; 7516 case IP_VERSION(9, 4, 1): 7517 adev->gds.gds_compute_max_wave_id = 0xfff; 7518 break; 7519 case IP_VERSION(9, 4, 2): 7520 /* deprecated for Aldebaran, no usage at all */ 7521 adev->gds.gds_compute_max_wave_id = 0; 7522 break; 7523 default: 7524 /* this really depends on the chip */ 7525 adev->gds.gds_compute_max_wave_id = 0x7ff; 7526 break; 7527 } 7528 7529 adev->gds.gws_size = 64; 7530 adev->gds.oa_size = 16; 7531 } 7532 7533 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7534 u32 bitmap) 7535 { 7536 u32 data; 7537 7538 if (!bitmap) 7539 return; 7540 7541 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7542 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7543 7544 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7545 } 7546 7547 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7548 { 7549 u32 data, mask; 7550 7551 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7552 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7553 7554 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7555 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7556 7557 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7558 7559 return (~data) & mask; 7560 } 7561 7562 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7563 struct amdgpu_cu_info *cu_info) 7564 { 7565 int i, j, k, counter, active_cu_number = 0; 7566 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7567 unsigned disable_masks[4 * 4]; 7568 7569 if (!adev || !cu_info) 7570 return -EINVAL; 7571 7572 /* 7573 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7574 */ 7575 if (adev->gfx.config.max_shader_engines * 7576 adev->gfx.config.max_sh_per_se > 16) 7577 return -EINVAL; 7578 7579 amdgpu_gfx_parse_disable_cu(disable_masks, 7580 adev->gfx.config.max_shader_engines, 7581 adev->gfx.config.max_sh_per_se); 7582 7583 mutex_lock(&adev->grbm_idx_mutex); 7584 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7585 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7586 mask = 1; 7587 ao_bitmap = 0; 7588 counter = 0; 7589 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 7590 gfx_v9_0_set_user_cu_inactive_bitmap( 7591 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7592 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7593 7594 /* 7595 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7596 * 4x4 size array, and it's usually suitable for Vega 7597 * ASICs which has 4*2 SE/SH layout. 7598 * But for Arcturus, SE/SH layout is changed to 8*1. 7599 * To mostly reduce the impact, we make it compatible 7600 * with current bitmap array as below: 7601 * SE4,SH0 --> bitmap[0][1] 7602 * SE5,SH0 --> bitmap[1][1] 7603 * SE6,SH0 --> bitmap[2][1] 7604 * SE7,SH0 --> bitmap[3][1] 7605 */ 7606 cu_info->bitmap[0][i % 4][j + i / 4] = bitmap; 7607 7608 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7609 if (bitmap & mask) { 7610 if (counter < adev->gfx.config.max_cu_per_sh) 7611 ao_bitmap |= mask; 7612 counter ++; 7613 } 7614 mask <<= 1; 7615 } 7616 active_cu_number += counter; 7617 if (i < 2 && j < 2) 7618 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7619 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7620 } 7621 } 7622 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7623 mutex_unlock(&adev->grbm_idx_mutex); 7624 7625 cu_info->number = active_cu_number; 7626 cu_info->ao_cu_mask = ao_cu_mask; 7627 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7628 7629 return 0; 7630 } 7631 7632 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7633 { 7634 .type = AMD_IP_BLOCK_TYPE_GFX, 7635 .major = 9, 7636 .minor = 0, 7637 .rev = 0, 7638 .funcs = &gfx_v9_0_ip_funcs, 7639 }; 7640