1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "amdgpu_ring_mux.h" 51 #include "gfx_v9_4.h" 52 #include "gfx_v9_0.h" 53 #include "gfx_v9_4_2.h" 54 55 #include "asic_reg/pwr/pwr_10_0_offset.h" 56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 57 #include "asic_reg/gc/gc_9_0_default.h" 58 59 #define GFX9_NUM_GFX_RINGS 1 60 #define GFX9_NUM_SW_GFX_RINGS 2 61 #define GFX9_MEC_HPD_SIZE 4096 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 114 115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 127 128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 133 134 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 144 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 146 147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 151 152 enum ta_ras_gfx_subblock { 153 /*CPC*/ 154 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 155 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 156 TA_RAS_BLOCK__GFX_CPC_UCODE, 157 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 158 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 159 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 160 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 161 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 162 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 163 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 164 /* CPF*/ 165 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 166 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 167 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 168 TA_RAS_BLOCK__GFX_CPF_TAG, 169 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 170 /* CPG*/ 171 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 172 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 173 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 174 TA_RAS_BLOCK__GFX_CPG_TAG, 175 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 176 /* GDS*/ 177 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 178 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 179 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 180 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 181 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 182 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 183 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 184 /* SPI*/ 185 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 186 /* SQ*/ 187 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 188 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 189 TA_RAS_BLOCK__GFX_SQ_LDS_D, 190 TA_RAS_BLOCK__GFX_SQ_LDS_I, 191 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 192 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 193 /* SQC (3 ranges)*/ 194 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 195 /* SQC range 0*/ 196 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 197 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 198 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 199 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 200 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 201 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 202 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 203 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 204 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 205 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 206 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 207 /* SQC range 1*/ 208 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 210 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 212 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 213 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 217 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 219 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 220 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 221 /* SQC range 2*/ 222 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 223 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 224 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 225 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 226 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 227 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 228 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 229 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 230 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 231 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 232 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 233 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 234 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 235 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 236 /* TA*/ 237 TA_RAS_BLOCK__GFX_TA_INDEX_START, 238 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 239 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 240 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 241 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 242 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 243 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 244 /* TCA*/ 245 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 246 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 247 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 248 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 249 /* TCC (5 sub-ranges)*/ 250 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 251 /* TCC range 0*/ 252 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 253 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 254 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 255 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 256 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 257 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 258 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 259 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 260 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 261 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 262 /* TCC range 1*/ 263 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 264 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 265 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 266 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 267 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 268 /* TCC range 2*/ 269 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 270 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 271 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 272 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 273 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 274 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 275 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 276 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 277 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 278 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 279 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 280 /* TCC range 3*/ 281 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 282 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 283 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 284 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 285 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 286 /* TCC range 4*/ 287 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 288 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 289 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 290 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 291 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 292 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 293 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 294 /* TCI*/ 295 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 296 /* TCP*/ 297 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 298 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 299 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 300 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 301 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 302 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 303 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 304 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 305 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 306 /* TD*/ 307 TA_RAS_BLOCK__GFX_TD_INDEX_START, 308 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 309 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 310 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 311 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 312 /* EA (3 sub-ranges)*/ 313 TA_RAS_BLOCK__GFX_EA_INDEX_START, 314 /* EA range 0*/ 315 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 316 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 317 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 318 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 319 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 320 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 321 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 322 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 323 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 324 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 325 /* EA range 1*/ 326 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 327 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 328 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 329 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 330 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 331 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 332 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 333 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 334 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 335 /* EA range 2*/ 336 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 337 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 338 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 339 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 340 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 341 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 342 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 343 /* UTC VM L2 bank*/ 344 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 345 /* UTC VM walker*/ 346 TA_RAS_BLOCK__UTC_VML2_WALKER, 347 /* UTC ATC L2 2MB cache*/ 348 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 349 /* UTC ATC L2 4KB cache*/ 350 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 351 TA_RAS_BLOCK__GFX_MAX 352 }; 353 354 struct ras_gfx_subblock { 355 unsigned char *name; 356 int ta_subblock; 357 int hw_supported_error_type; 358 int sw_supported_error_type; 359 }; 360 361 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 362 [AMDGPU_RAS_BLOCK__##subblock] = { \ 363 #subblock, \ 364 TA_RAS_BLOCK__##subblock, \ 365 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 366 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 367 } 368 369 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 370 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 371 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 372 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 373 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 375 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 378 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 379 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 380 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 382 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 383 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 384 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 386 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 387 0), 388 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 389 0), 390 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 392 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 394 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 396 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 398 0, 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 400 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 402 0, 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 404 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 406 0, 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 408 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 410 1), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 412 0, 0, 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 416 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 422 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 424 0, 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 430 0, 0, 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 432 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 434 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 436 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 438 0), 439 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 440 0), 441 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 442 0, 0), 443 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 446 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 448 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 454 1), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 456 1), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 458 1), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 460 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 462 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 464 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 466 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 468 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 475 0), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 478 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 480 0, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 482 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 485 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 490 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 492 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 502 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 510 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 511 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 512 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 513 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 515 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 516 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 517 }; 518 519 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 520 { 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 541 }; 542 543 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 544 { 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 563 }; 564 565 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 566 { 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 578 }; 579 580 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 581 { 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 606 }; 607 608 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 609 { 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 617 }; 618 619 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 620 { 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 640 }; 641 642 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 643 { 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 656 }; 657 658 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 659 { 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 663 }; 664 665 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 666 { 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 683 }; 684 685 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 686 { 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 700 }; 701 702 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 703 { 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 715 }; 716 717 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 718 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 719 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 720 }; 721 722 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 723 { 724 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 725 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 726 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 727 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 728 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 729 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 730 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 731 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 732 }; 733 734 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 735 { 736 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 737 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 738 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 739 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 740 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 741 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 742 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 743 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 744 }; 745 746 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 747 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 748 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 749 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 750 751 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 752 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 753 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 754 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 755 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 756 struct amdgpu_cu_info *cu_info); 757 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 758 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 759 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 760 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 761 void *ras_error_status); 762 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 763 void *inject_if); 764 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 765 766 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 767 uint64_t queue_mask) 768 { 769 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 770 amdgpu_ring_write(kiq_ring, 771 PACKET3_SET_RESOURCES_VMID_MASK(0) | 772 /* vmid_mask:0* queue_type:0 (KIQ) */ 773 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 774 amdgpu_ring_write(kiq_ring, 775 lower_32_bits(queue_mask)); /* queue mask lo */ 776 amdgpu_ring_write(kiq_ring, 777 upper_32_bits(queue_mask)); /* queue mask hi */ 778 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 779 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 780 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 781 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 782 } 783 784 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 785 struct amdgpu_ring *ring) 786 { 787 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 788 uint64_t wptr_addr = ring->wptr_gpu_addr; 789 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 790 791 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 792 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 793 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 794 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 795 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 796 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 797 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 798 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 799 /*queue_type: normal compute queue */ 800 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 801 /* alloc format: all_on_one_pipe */ 802 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 803 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 804 /* num_queues: must be 1 */ 805 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 806 amdgpu_ring_write(kiq_ring, 807 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 808 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 809 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 810 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 811 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 812 } 813 814 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 815 struct amdgpu_ring *ring, 816 enum amdgpu_unmap_queues_action action, 817 u64 gpu_addr, u64 seq) 818 { 819 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 820 821 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 822 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 823 PACKET3_UNMAP_QUEUES_ACTION(action) | 824 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 825 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 826 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 827 amdgpu_ring_write(kiq_ring, 828 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 829 830 if (action == PREEMPT_QUEUES_NO_UNMAP) { 831 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 832 amdgpu_ring_write(kiq_ring, 0); 833 amdgpu_ring_write(kiq_ring, 0); 834 835 } else { 836 amdgpu_ring_write(kiq_ring, 0); 837 amdgpu_ring_write(kiq_ring, 0); 838 amdgpu_ring_write(kiq_ring, 0); 839 } 840 } 841 842 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 843 struct amdgpu_ring *ring, 844 u64 addr, 845 u64 seq) 846 { 847 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 848 849 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 850 amdgpu_ring_write(kiq_ring, 851 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 852 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 853 PACKET3_QUERY_STATUS_COMMAND(2)); 854 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 855 amdgpu_ring_write(kiq_ring, 856 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 857 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 858 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 859 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 860 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 861 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 862 } 863 864 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 865 uint16_t pasid, uint32_t flush_type, 866 bool all_hub) 867 { 868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 869 amdgpu_ring_write(kiq_ring, 870 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 871 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 872 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 873 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 874 } 875 876 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 877 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 878 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 879 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 880 .kiq_query_status = gfx_v9_0_kiq_query_status, 881 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 882 .set_resources_size = 8, 883 .map_queues_size = 7, 884 .unmap_queues_size = 6, 885 .query_status_size = 7, 886 .invalidate_tlbs_size = 2, 887 }; 888 889 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 890 { 891 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 892 } 893 894 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 895 { 896 switch (adev->ip_versions[GC_HWIP][0]) { 897 case IP_VERSION(9, 0, 1): 898 soc15_program_register_sequence(adev, 899 golden_settings_gc_9_0, 900 ARRAY_SIZE(golden_settings_gc_9_0)); 901 soc15_program_register_sequence(adev, 902 golden_settings_gc_9_0_vg10, 903 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 904 break; 905 case IP_VERSION(9, 2, 1): 906 soc15_program_register_sequence(adev, 907 golden_settings_gc_9_2_1, 908 ARRAY_SIZE(golden_settings_gc_9_2_1)); 909 soc15_program_register_sequence(adev, 910 golden_settings_gc_9_2_1_vg12, 911 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 912 break; 913 case IP_VERSION(9, 4, 0): 914 soc15_program_register_sequence(adev, 915 golden_settings_gc_9_0, 916 ARRAY_SIZE(golden_settings_gc_9_0)); 917 soc15_program_register_sequence(adev, 918 golden_settings_gc_9_0_vg20, 919 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 920 break; 921 case IP_VERSION(9, 4, 1): 922 soc15_program_register_sequence(adev, 923 golden_settings_gc_9_4_1_arct, 924 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 925 break; 926 case IP_VERSION(9, 2, 2): 927 case IP_VERSION(9, 1, 0): 928 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 929 ARRAY_SIZE(golden_settings_gc_9_1)); 930 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 931 soc15_program_register_sequence(adev, 932 golden_settings_gc_9_1_rv2, 933 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 934 else 935 soc15_program_register_sequence(adev, 936 golden_settings_gc_9_1_rv1, 937 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 938 break; 939 case IP_VERSION(9, 3, 0): 940 soc15_program_register_sequence(adev, 941 golden_settings_gc_9_1_rn, 942 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 943 return; /* for renoir, don't need common goldensetting */ 944 case IP_VERSION(9, 4, 2): 945 gfx_v9_4_2_init_golden_registers(adev, 946 adev->smuio.funcs->get_die_id(adev)); 947 break; 948 default: 949 break; 950 } 951 952 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 953 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) 954 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 955 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 956 } 957 958 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 959 bool wc, uint32_t reg, uint32_t val) 960 { 961 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 962 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 963 WRITE_DATA_DST_SEL(0) | 964 (wc ? WR_CONFIRM : 0)); 965 amdgpu_ring_write(ring, reg); 966 amdgpu_ring_write(ring, 0); 967 amdgpu_ring_write(ring, val); 968 } 969 970 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 971 int mem_space, int opt, uint32_t addr0, 972 uint32_t addr1, uint32_t ref, uint32_t mask, 973 uint32_t inv) 974 { 975 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 976 amdgpu_ring_write(ring, 977 /* memory (1) or register (0) */ 978 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 979 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 980 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 981 WAIT_REG_MEM_ENGINE(eng_sel))); 982 983 if (mem_space) 984 BUG_ON(addr0 & 0x3); /* Dword align */ 985 amdgpu_ring_write(ring, addr0); 986 amdgpu_ring_write(ring, addr1); 987 amdgpu_ring_write(ring, ref); 988 amdgpu_ring_write(ring, mask); 989 amdgpu_ring_write(ring, inv); /* poll interval */ 990 } 991 992 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 993 { 994 struct amdgpu_device *adev = ring->adev; 995 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 996 uint32_t tmp = 0; 997 unsigned i; 998 int r; 999 1000 WREG32(scratch, 0xCAFEDEAD); 1001 r = amdgpu_ring_alloc(ring, 3); 1002 if (r) 1003 return r; 1004 1005 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1006 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1007 amdgpu_ring_write(ring, 0xDEADBEEF); 1008 amdgpu_ring_commit(ring); 1009 1010 for (i = 0; i < adev->usec_timeout; i++) { 1011 tmp = RREG32(scratch); 1012 if (tmp == 0xDEADBEEF) 1013 break; 1014 udelay(1); 1015 } 1016 1017 if (i >= adev->usec_timeout) 1018 r = -ETIMEDOUT; 1019 return r; 1020 } 1021 1022 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1023 { 1024 struct amdgpu_device *adev = ring->adev; 1025 struct amdgpu_ib ib; 1026 struct dma_fence *f = NULL; 1027 1028 unsigned index; 1029 uint64_t gpu_addr; 1030 uint32_t tmp; 1031 long r; 1032 1033 r = amdgpu_device_wb_get(adev, &index); 1034 if (r) 1035 return r; 1036 1037 gpu_addr = adev->wb.gpu_addr + (index * 4); 1038 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1039 memset(&ib, 0, sizeof(ib)); 1040 r = amdgpu_ib_get(adev, NULL, 16, 1041 AMDGPU_IB_POOL_DIRECT, &ib); 1042 if (r) 1043 goto err1; 1044 1045 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1046 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1047 ib.ptr[2] = lower_32_bits(gpu_addr); 1048 ib.ptr[3] = upper_32_bits(gpu_addr); 1049 ib.ptr[4] = 0xDEADBEEF; 1050 ib.length_dw = 5; 1051 1052 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1053 if (r) 1054 goto err2; 1055 1056 r = dma_fence_wait_timeout(f, false, timeout); 1057 if (r == 0) { 1058 r = -ETIMEDOUT; 1059 goto err2; 1060 } else if (r < 0) { 1061 goto err2; 1062 } 1063 1064 tmp = adev->wb.wb[index]; 1065 if (tmp == 0xDEADBEEF) 1066 r = 0; 1067 else 1068 r = -EINVAL; 1069 1070 err2: 1071 amdgpu_ib_free(adev, &ib, NULL); 1072 dma_fence_put(f); 1073 err1: 1074 amdgpu_device_wb_free(adev, index); 1075 return r; 1076 } 1077 1078 1079 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1080 { 1081 release_firmware(adev->gfx.pfp_fw); 1082 adev->gfx.pfp_fw = NULL; 1083 release_firmware(adev->gfx.me_fw); 1084 adev->gfx.me_fw = NULL; 1085 release_firmware(adev->gfx.ce_fw); 1086 adev->gfx.ce_fw = NULL; 1087 release_firmware(adev->gfx.rlc_fw); 1088 adev->gfx.rlc_fw = NULL; 1089 release_firmware(adev->gfx.mec_fw); 1090 adev->gfx.mec_fw = NULL; 1091 release_firmware(adev->gfx.mec2_fw); 1092 adev->gfx.mec2_fw = NULL; 1093 1094 kfree(adev->gfx.rlc.register_list_format); 1095 } 1096 1097 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1098 { 1099 adev->gfx.me_fw_write_wait = false; 1100 adev->gfx.mec_fw_write_wait = false; 1101 1102 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 1103 ((adev->gfx.mec_fw_version < 0x000001a5) || 1104 (adev->gfx.mec_feature_version < 46) || 1105 (adev->gfx.pfp_fw_version < 0x000000b7) || 1106 (adev->gfx.pfp_feature_version < 46))) 1107 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1108 1109 switch (adev->ip_versions[GC_HWIP][0]) { 1110 case IP_VERSION(9, 0, 1): 1111 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1112 (adev->gfx.me_feature_version >= 42) && 1113 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1114 (adev->gfx.pfp_feature_version >= 42)) 1115 adev->gfx.me_fw_write_wait = true; 1116 1117 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1118 (adev->gfx.mec_feature_version >= 42)) 1119 adev->gfx.mec_fw_write_wait = true; 1120 break; 1121 case IP_VERSION(9, 2, 1): 1122 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1123 (adev->gfx.me_feature_version >= 44) && 1124 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1125 (adev->gfx.pfp_feature_version >= 44)) 1126 adev->gfx.me_fw_write_wait = true; 1127 1128 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1129 (adev->gfx.mec_feature_version >= 44)) 1130 adev->gfx.mec_fw_write_wait = true; 1131 break; 1132 case IP_VERSION(9, 4, 0): 1133 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1134 (adev->gfx.me_feature_version >= 44) && 1135 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1136 (adev->gfx.pfp_feature_version >= 44)) 1137 adev->gfx.me_fw_write_wait = true; 1138 1139 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1140 (adev->gfx.mec_feature_version >= 44)) 1141 adev->gfx.mec_fw_write_wait = true; 1142 break; 1143 case IP_VERSION(9, 1, 0): 1144 case IP_VERSION(9, 2, 2): 1145 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1146 (adev->gfx.me_feature_version >= 42) && 1147 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1148 (adev->gfx.pfp_feature_version >= 42)) 1149 adev->gfx.me_fw_write_wait = true; 1150 1151 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1152 (adev->gfx.mec_feature_version >= 42)) 1153 adev->gfx.mec_fw_write_wait = true; 1154 break; 1155 default: 1156 adev->gfx.me_fw_write_wait = true; 1157 adev->gfx.mec_fw_write_wait = true; 1158 break; 1159 } 1160 } 1161 1162 struct amdgpu_gfxoff_quirk { 1163 u16 chip_vendor; 1164 u16 chip_device; 1165 u16 subsys_vendor; 1166 u16 subsys_device; 1167 u8 revision; 1168 }; 1169 1170 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1171 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1172 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1173 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1174 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1175 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1176 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1177 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1178 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1179 { 0, 0, 0, 0, 0 }, 1180 }; 1181 1182 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1183 { 1184 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1185 1186 while (p && p->chip_device != 0) { 1187 if (pdev->vendor == p->chip_vendor && 1188 pdev->device == p->chip_device && 1189 pdev->subsystem_vendor == p->subsys_vendor && 1190 pdev->subsystem_device == p->subsys_device && 1191 pdev->revision == p->revision) { 1192 return true; 1193 } 1194 ++p; 1195 } 1196 return false; 1197 } 1198 1199 static bool is_raven_kicker(struct amdgpu_device *adev) 1200 { 1201 if (adev->pm.fw_version >= 0x41e2b) 1202 return true; 1203 else 1204 return false; 1205 } 1206 1207 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1208 { 1209 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && 1210 (adev->gfx.me_fw_version >= 0x000000a5) && 1211 (adev->gfx.me_feature_version >= 52)) 1212 return true; 1213 else 1214 return false; 1215 } 1216 1217 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1218 { 1219 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1220 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1221 1222 switch (adev->ip_versions[GC_HWIP][0]) { 1223 case IP_VERSION(9, 0, 1): 1224 case IP_VERSION(9, 2, 1): 1225 case IP_VERSION(9, 4, 0): 1226 break; 1227 case IP_VERSION(9, 2, 2): 1228 case IP_VERSION(9, 1, 0): 1229 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1230 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1231 ((!is_raven_kicker(adev) && 1232 adev->gfx.rlc_fw_version < 531) || 1233 (adev->gfx.rlc_feature_version < 1) || 1234 !adev->gfx.rlc.is_rlc_v2_1)) 1235 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1236 1237 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1238 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1239 AMD_PG_SUPPORT_CP | 1240 AMD_PG_SUPPORT_RLC_SMU_HS; 1241 break; 1242 case IP_VERSION(9, 3, 0): 1243 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1244 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1245 AMD_PG_SUPPORT_CP | 1246 AMD_PG_SUPPORT_RLC_SMU_HS; 1247 break; 1248 default: 1249 break; 1250 } 1251 } 1252 1253 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1254 const char *chip_name) 1255 { 1256 char fw_name[30]; 1257 int err; 1258 1259 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1260 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 1261 if (err) 1262 goto out; 1263 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 1264 if (err) 1265 goto out; 1266 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1267 1268 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1269 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 1270 if (err) 1271 goto out; 1272 err = amdgpu_ucode_validate(adev->gfx.me_fw); 1273 if (err) 1274 goto out; 1275 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1276 1277 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1278 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 1279 if (err) 1280 goto out; 1281 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 1282 if (err) 1283 goto out; 1284 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1285 1286 out: 1287 if (err) { 1288 dev_err(adev->dev, 1289 "gfx9: Failed to init firmware \"%s\"\n", 1290 fw_name); 1291 release_firmware(adev->gfx.pfp_fw); 1292 adev->gfx.pfp_fw = NULL; 1293 release_firmware(adev->gfx.me_fw); 1294 adev->gfx.me_fw = NULL; 1295 release_firmware(adev->gfx.ce_fw); 1296 adev->gfx.ce_fw = NULL; 1297 } 1298 return err; 1299 } 1300 1301 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1302 const char *chip_name) 1303 { 1304 char fw_name[30]; 1305 int err; 1306 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1307 uint16_t version_major; 1308 uint16_t version_minor; 1309 uint32_t smu_version; 1310 1311 /* 1312 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1313 * instead of picasso_rlc.bin. 1314 * Judgment method: 1315 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1316 * or revision >= 0xD8 && revision <= 0xDF 1317 * otherwise is PCO FP5 1318 */ 1319 if (!strcmp(chip_name, "picasso") && 1320 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1321 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1323 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1324 (smu_version >= 0x41e2b)) 1325 /** 1326 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1327 */ 1328 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1329 else 1330 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1331 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1332 if (err) 1333 goto out; 1334 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1335 if (err) 1336 goto out; 1337 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1338 1339 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1340 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1341 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1342 out: 1343 if (err) { 1344 dev_err(adev->dev, 1345 "gfx9: Failed to init firmware \"%s\"\n", 1346 fw_name); 1347 release_firmware(adev->gfx.rlc_fw); 1348 adev->gfx.rlc_fw = NULL; 1349 } 1350 return err; 1351 } 1352 1353 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1354 { 1355 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1356 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1357 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) 1358 return false; 1359 1360 return true; 1361 } 1362 1363 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1364 const char *chip_name) 1365 { 1366 char fw_name[30]; 1367 int err; 1368 1369 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1370 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); 1371 else 1372 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1373 1374 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1375 if (err) 1376 goto out; 1377 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1378 if (err) 1379 goto out; 1380 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1381 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1382 1383 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1384 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1385 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); 1386 else 1387 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1388 1389 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1390 if (!err) { 1391 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1392 if (err) 1393 goto out; 1394 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1395 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1396 } else { 1397 err = 0; 1398 adev->gfx.mec2_fw = NULL; 1399 } 1400 } else { 1401 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1402 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1403 } 1404 1405 out: 1406 gfx_v9_0_check_if_need_gfxoff(adev); 1407 gfx_v9_0_check_fw_write_wait(adev); 1408 if (err) { 1409 dev_err(adev->dev, 1410 "gfx9: Failed to init firmware \"%s\"\n", 1411 fw_name); 1412 release_firmware(adev->gfx.mec_fw); 1413 adev->gfx.mec_fw = NULL; 1414 release_firmware(adev->gfx.mec2_fw); 1415 adev->gfx.mec2_fw = NULL; 1416 } 1417 return err; 1418 } 1419 1420 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1421 { 1422 const char *chip_name; 1423 int r; 1424 1425 DRM_DEBUG("\n"); 1426 1427 switch (adev->ip_versions[GC_HWIP][0]) { 1428 case IP_VERSION(9, 0, 1): 1429 chip_name = "vega10"; 1430 break; 1431 case IP_VERSION(9, 2, 1): 1432 chip_name = "vega12"; 1433 break; 1434 case IP_VERSION(9, 4, 0): 1435 chip_name = "vega20"; 1436 break; 1437 case IP_VERSION(9, 2, 2): 1438 case IP_VERSION(9, 1, 0): 1439 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1440 chip_name = "raven2"; 1441 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1442 chip_name = "picasso"; 1443 else 1444 chip_name = "raven"; 1445 break; 1446 case IP_VERSION(9, 4, 1): 1447 chip_name = "arcturus"; 1448 break; 1449 case IP_VERSION(9, 3, 0): 1450 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1451 chip_name = "renoir"; 1452 else 1453 chip_name = "green_sardine"; 1454 break; 1455 case IP_VERSION(9, 4, 2): 1456 chip_name = "aldebaran"; 1457 break; 1458 default: 1459 BUG(); 1460 } 1461 1462 /* No CPG in Arcturus */ 1463 if (adev->gfx.num_gfx_rings) { 1464 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); 1465 if (r) 1466 return r; 1467 } 1468 1469 r = gfx_v9_0_init_rlc_microcode(adev, chip_name); 1470 if (r) 1471 return r; 1472 1473 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); 1474 if (r) 1475 return r; 1476 1477 return r; 1478 } 1479 1480 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1481 { 1482 u32 count = 0; 1483 const struct cs_section_def *sect = NULL; 1484 const struct cs_extent_def *ext = NULL; 1485 1486 /* begin clear state */ 1487 count += 2; 1488 /* context control state */ 1489 count += 3; 1490 1491 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1492 for (ext = sect->section; ext->extent != NULL; ++ext) { 1493 if (sect->id == SECT_CONTEXT) 1494 count += 2 + ext->reg_count; 1495 else 1496 return 0; 1497 } 1498 } 1499 1500 /* end clear state */ 1501 count += 2; 1502 /* clear state */ 1503 count += 2; 1504 1505 return count; 1506 } 1507 1508 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1509 volatile u32 *buffer) 1510 { 1511 u32 count = 0, i; 1512 const struct cs_section_def *sect = NULL; 1513 const struct cs_extent_def *ext = NULL; 1514 1515 if (adev->gfx.rlc.cs_data == NULL) 1516 return; 1517 if (buffer == NULL) 1518 return; 1519 1520 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1521 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1522 1523 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1524 buffer[count++] = cpu_to_le32(0x80000000); 1525 buffer[count++] = cpu_to_le32(0x80000000); 1526 1527 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1528 for (ext = sect->section; ext->extent != NULL; ++ext) { 1529 if (sect->id == SECT_CONTEXT) { 1530 buffer[count++] = 1531 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1532 buffer[count++] = cpu_to_le32(ext->reg_index - 1533 PACKET3_SET_CONTEXT_REG_START); 1534 for (i = 0; i < ext->reg_count; i++) 1535 buffer[count++] = cpu_to_le32(ext->extent[i]); 1536 } else { 1537 return; 1538 } 1539 } 1540 } 1541 1542 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1543 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1544 1545 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1546 buffer[count++] = cpu_to_le32(0); 1547 } 1548 1549 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1550 { 1551 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1552 uint32_t pg_always_on_cu_num = 2; 1553 uint32_t always_on_cu_num; 1554 uint32_t i, j, k; 1555 uint32_t mask, cu_bitmap, counter; 1556 1557 if (adev->flags & AMD_IS_APU) 1558 always_on_cu_num = 4; 1559 else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) 1560 always_on_cu_num = 8; 1561 else 1562 always_on_cu_num = 12; 1563 1564 mutex_lock(&adev->grbm_idx_mutex); 1565 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1566 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1567 mask = 1; 1568 cu_bitmap = 0; 1569 counter = 0; 1570 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 1571 1572 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1573 if (cu_info->bitmap[i][j] & mask) { 1574 if (counter == pg_always_on_cu_num) 1575 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1576 if (counter < always_on_cu_num) 1577 cu_bitmap |= mask; 1578 else 1579 break; 1580 counter++; 1581 } 1582 mask <<= 1; 1583 } 1584 1585 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1586 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1587 } 1588 } 1589 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1590 mutex_unlock(&adev->grbm_idx_mutex); 1591 } 1592 1593 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1594 { 1595 uint32_t data; 1596 1597 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1598 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1599 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1600 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1601 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1602 1603 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1604 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1605 1606 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1607 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1608 1609 mutex_lock(&adev->grbm_idx_mutex); 1610 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1611 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1612 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1613 1614 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1615 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1616 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1617 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1618 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1619 1620 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1621 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1622 data &= 0x0000FFFF; 1623 data |= 0x00C00000; 1624 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1625 1626 /* 1627 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1628 * programmed in gfx_v9_0_init_always_on_cu_mask() 1629 */ 1630 1631 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1632 * but used for RLC_LB_CNTL configuration */ 1633 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1634 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1635 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1636 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1637 mutex_unlock(&adev->grbm_idx_mutex); 1638 1639 gfx_v9_0_init_always_on_cu_mask(adev); 1640 } 1641 1642 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1643 { 1644 uint32_t data; 1645 1646 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1647 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1648 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1649 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1650 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1651 1652 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1653 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1654 1655 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1656 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1657 1658 mutex_lock(&adev->grbm_idx_mutex); 1659 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1660 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1661 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1662 1663 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1664 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1665 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1666 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1667 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1668 1669 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1670 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1671 data &= 0x0000FFFF; 1672 data |= 0x00C00000; 1673 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1674 1675 /* 1676 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1677 * programmed in gfx_v9_0_init_always_on_cu_mask() 1678 */ 1679 1680 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1681 * but used for RLC_LB_CNTL configuration */ 1682 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1683 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1684 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1685 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1686 mutex_unlock(&adev->grbm_idx_mutex); 1687 1688 gfx_v9_0_init_always_on_cu_mask(adev); 1689 } 1690 1691 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1692 { 1693 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1694 } 1695 1696 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1697 { 1698 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1699 return 5; 1700 else 1701 return 4; 1702 } 1703 1704 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1705 { 1706 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1707 1708 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 1709 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1710 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1711 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1712 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1713 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1714 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1715 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1716 adev->gfx.rlc.rlcg_reg_access_supported = true; 1717 } 1718 1719 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1720 { 1721 const struct cs_section_def *cs_data; 1722 int r; 1723 1724 adev->gfx.rlc.cs_data = gfx9_cs_data; 1725 1726 cs_data = adev->gfx.rlc.cs_data; 1727 1728 if (cs_data) { 1729 /* init clear state block */ 1730 r = amdgpu_gfx_rlc_init_csb(adev); 1731 if (r) 1732 return r; 1733 } 1734 1735 if (adev->flags & AMD_IS_APU) { 1736 /* TODO: double check the cp_table_size for RV */ 1737 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1738 r = amdgpu_gfx_rlc_init_cpt(adev); 1739 if (r) 1740 return r; 1741 } 1742 1743 switch (adev->ip_versions[GC_HWIP][0]) { 1744 case IP_VERSION(9, 2, 2): 1745 case IP_VERSION(9, 1, 0): 1746 gfx_v9_0_init_lbpw(adev); 1747 break; 1748 case IP_VERSION(9, 4, 0): 1749 gfx_v9_4_init_lbpw(adev); 1750 break; 1751 default: 1752 break; 1753 } 1754 1755 /* init spm vmid with 0xf */ 1756 if (adev->gfx.rlc.funcs->update_spm_vmid) 1757 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1758 1759 return 0; 1760 } 1761 1762 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1763 { 1764 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1765 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1766 } 1767 1768 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1769 { 1770 int r; 1771 u32 *hpd; 1772 const __le32 *fw_data; 1773 unsigned fw_size; 1774 u32 *fw; 1775 size_t mec_hpd_size; 1776 1777 const struct gfx_firmware_header_v1_0 *mec_hdr; 1778 1779 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1780 1781 /* take ownership of the relevant compute queues */ 1782 amdgpu_gfx_compute_queue_acquire(adev); 1783 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1784 if (mec_hpd_size) { 1785 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1786 AMDGPU_GEM_DOMAIN_VRAM | 1787 AMDGPU_GEM_DOMAIN_GTT, 1788 &adev->gfx.mec.hpd_eop_obj, 1789 &adev->gfx.mec.hpd_eop_gpu_addr, 1790 (void **)&hpd); 1791 if (r) { 1792 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1793 gfx_v9_0_mec_fini(adev); 1794 return r; 1795 } 1796 1797 memset(hpd, 0, mec_hpd_size); 1798 1799 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1800 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1801 } 1802 1803 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1804 1805 fw_data = (const __le32 *) 1806 (adev->gfx.mec_fw->data + 1807 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1808 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1809 1810 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1811 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1812 &adev->gfx.mec.mec_fw_obj, 1813 &adev->gfx.mec.mec_fw_gpu_addr, 1814 (void **)&fw); 1815 if (r) { 1816 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1817 gfx_v9_0_mec_fini(adev); 1818 return r; 1819 } 1820 1821 memcpy(fw, fw_data, fw_size); 1822 1823 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1824 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1825 1826 return 0; 1827 } 1828 1829 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1830 { 1831 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1832 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1833 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1834 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1835 (SQ_IND_INDEX__FORCE_READ_MASK)); 1836 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1837 } 1838 1839 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1840 uint32_t wave, uint32_t thread, 1841 uint32_t regno, uint32_t num, uint32_t *out) 1842 { 1843 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1844 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1845 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1846 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1847 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1848 (SQ_IND_INDEX__FORCE_READ_MASK) | 1849 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1850 while (num--) 1851 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1852 } 1853 1854 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1855 { 1856 /* type 1 wave data */ 1857 dst[(*no_fields)++] = 1; 1858 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1859 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1860 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1861 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1862 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1863 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1864 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1865 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1866 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1867 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1868 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1869 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1870 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1871 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1872 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1873 } 1874 1875 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1876 uint32_t wave, uint32_t start, 1877 uint32_t size, uint32_t *dst) 1878 { 1879 wave_read_regs( 1880 adev, simd, wave, 0, 1881 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1882 } 1883 1884 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1885 uint32_t wave, uint32_t thread, 1886 uint32_t start, uint32_t size, 1887 uint32_t *dst) 1888 { 1889 wave_read_regs( 1890 adev, simd, wave, thread, 1891 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1892 } 1893 1894 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1895 u32 me, u32 pipe, u32 q, u32 vm) 1896 { 1897 soc15_grbm_select(adev, me, pipe, q, vm); 1898 } 1899 1900 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1901 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1902 .select_se_sh = &gfx_v9_0_select_se_sh, 1903 .read_wave_data = &gfx_v9_0_read_wave_data, 1904 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1905 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1906 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1907 }; 1908 1909 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1910 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1911 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1912 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1913 }; 1914 1915 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1916 .ras_block = { 1917 .hw_ops = &gfx_v9_0_ras_ops, 1918 }, 1919 }; 1920 1921 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1922 { 1923 u32 gb_addr_config; 1924 int err; 1925 1926 switch (adev->ip_versions[GC_HWIP][0]) { 1927 case IP_VERSION(9, 0, 1): 1928 adev->gfx.config.max_hw_contexts = 8; 1929 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1930 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1931 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1932 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1933 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1934 break; 1935 case IP_VERSION(9, 2, 1): 1936 adev->gfx.config.max_hw_contexts = 8; 1937 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1938 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1939 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1940 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1941 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1942 DRM_INFO("fix gfx.config for vega12\n"); 1943 break; 1944 case IP_VERSION(9, 4, 0): 1945 adev->gfx.ras = &gfx_v9_0_ras; 1946 adev->gfx.config.max_hw_contexts = 8; 1947 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1948 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1949 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1950 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1951 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1952 gb_addr_config &= ~0xf3e777ff; 1953 gb_addr_config |= 0x22014042; 1954 /* check vbios table if gpu info is not available */ 1955 err = amdgpu_atomfirmware_get_gfx_info(adev); 1956 if (err) 1957 return err; 1958 break; 1959 case IP_VERSION(9, 2, 2): 1960 case IP_VERSION(9, 1, 0): 1961 adev->gfx.config.max_hw_contexts = 8; 1962 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1963 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1964 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1965 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1966 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1967 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1968 else 1969 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1970 break; 1971 case IP_VERSION(9, 4, 1): 1972 adev->gfx.ras = &gfx_v9_4_ras; 1973 adev->gfx.config.max_hw_contexts = 8; 1974 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1975 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1976 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1977 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1978 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1979 gb_addr_config &= ~0xf3e777ff; 1980 gb_addr_config |= 0x22014042; 1981 break; 1982 case IP_VERSION(9, 3, 0): 1983 adev->gfx.config.max_hw_contexts = 8; 1984 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1985 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1986 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1987 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1988 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1989 gb_addr_config &= ~0xf3e777ff; 1990 gb_addr_config |= 0x22010042; 1991 break; 1992 case IP_VERSION(9, 4, 2): 1993 adev->gfx.ras = &gfx_v9_4_2_ras; 1994 adev->gfx.config.max_hw_contexts = 8; 1995 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1996 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1997 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1998 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1999 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2000 gb_addr_config &= ~0xf3e777ff; 2001 gb_addr_config |= 0x22014042; 2002 /* check vbios table if gpu info is not available */ 2003 err = amdgpu_atomfirmware_get_gfx_info(adev); 2004 if (err) 2005 return err; 2006 break; 2007 default: 2008 BUG(); 2009 break; 2010 } 2011 2012 if (adev->gfx.ras) { 2013 err = amdgpu_ras_register_ras_block(adev, &adev->gfx.ras->ras_block); 2014 if (err) { 2015 DRM_ERROR("Failed to register gfx ras block!\n"); 2016 return err; 2017 } 2018 2019 strcpy(adev->gfx.ras->ras_block.ras_comm.name, "gfx"); 2020 adev->gfx.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; 2021 adev->gfx.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 2022 adev->gfx.ras_if = &adev->gfx.ras->ras_block.ras_comm; 2023 2024 /* If not define special ras_late_init function, use gfx default ras_late_init */ 2025 if (!adev->gfx.ras->ras_block.ras_late_init) 2026 adev->gfx.ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; 2027 2028 /* If not defined special ras_cb function, use default ras_cb */ 2029 if (!adev->gfx.ras->ras_block.ras_cb) 2030 adev->gfx.ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; 2031 } 2032 2033 adev->gfx.config.gb_addr_config = gb_addr_config; 2034 2035 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2036 REG_GET_FIELD( 2037 adev->gfx.config.gb_addr_config, 2038 GB_ADDR_CONFIG, 2039 NUM_PIPES); 2040 2041 adev->gfx.config.max_tile_pipes = 2042 adev->gfx.config.gb_addr_config_fields.num_pipes; 2043 2044 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2045 REG_GET_FIELD( 2046 adev->gfx.config.gb_addr_config, 2047 GB_ADDR_CONFIG, 2048 NUM_BANKS); 2049 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2050 REG_GET_FIELD( 2051 adev->gfx.config.gb_addr_config, 2052 GB_ADDR_CONFIG, 2053 MAX_COMPRESSED_FRAGS); 2054 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2055 REG_GET_FIELD( 2056 adev->gfx.config.gb_addr_config, 2057 GB_ADDR_CONFIG, 2058 NUM_RB_PER_SE); 2059 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2060 REG_GET_FIELD( 2061 adev->gfx.config.gb_addr_config, 2062 GB_ADDR_CONFIG, 2063 NUM_SHADER_ENGINES); 2064 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2065 REG_GET_FIELD( 2066 adev->gfx.config.gb_addr_config, 2067 GB_ADDR_CONFIG, 2068 PIPE_INTERLEAVE_SIZE)); 2069 2070 return 0; 2071 } 2072 2073 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2074 int mec, int pipe, int queue) 2075 { 2076 unsigned irq_type; 2077 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2078 unsigned int hw_prio; 2079 2080 ring = &adev->gfx.compute_ring[ring_id]; 2081 2082 /* mec0 is me1 */ 2083 ring->me = mec + 1; 2084 ring->pipe = pipe; 2085 ring->queue = queue; 2086 2087 ring->ring_obj = NULL; 2088 ring->use_doorbell = true; 2089 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2090 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2091 + (ring_id * GFX9_MEC_HPD_SIZE); 2092 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2093 2094 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2095 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2096 + ring->pipe; 2097 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2098 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2099 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2100 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2101 hw_prio, NULL); 2102 } 2103 2104 static int gfx_v9_0_sw_init(void *handle) 2105 { 2106 int i, j, k, r, ring_id; 2107 struct amdgpu_ring *ring; 2108 struct amdgpu_kiq *kiq; 2109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2110 unsigned int hw_prio; 2111 2112 switch (adev->ip_versions[GC_HWIP][0]) { 2113 case IP_VERSION(9, 0, 1): 2114 case IP_VERSION(9, 2, 1): 2115 case IP_VERSION(9, 4, 0): 2116 case IP_VERSION(9, 2, 2): 2117 case IP_VERSION(9, 1, 0): 2118 case IP_VERSION(9, 4, 1): 2119 case IP_VERSION(9, 3, 0): 2120 case IP_VERSION(9, 4, 2): 2121 adev->gfx.mec.num_mec = 2; 2122 break; 2123 default: 2124 adev->gfx.mec.num_mec = 1; 2125 break; 2126 } 2127 2128 adev->gfx.mec.num_pipe_per_mec = 4; 2129 adev->gfx.mec.num_queue_per_pipe = 8; 2130 2131 /* EOP Event */ 2132 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2133 if (r) 2134 return r; 2135 2136 /* Privileged reg */ 2137 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2138 &adev->gfx.priv_reg_irq); 2139 if (r) 2140 return r; 2141 2142 /* Privileged inst */ 2143 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2144 &adev->gfx.priv_inst_irq); 2145 if (r) 2146 return r; 2147 2148 /* ECC error */ 2149 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2150 &adev->gfx.cp_ecc_error_irq); 2151 if (r) 2152 return r; 2153 2154 /* FUE error */ 2155 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2156 &adev->gfx.cp_ecc_error_irq); 2157 if (r) 2158 return r; 2159 2160 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2161 2162 r = gfx_v9_0_init_microcode(adev); 2163 if (r) { 2164 DRM_ERROR("Failed to load gfx firmware!\n"); 2165 return r; 2166 } 2167 2168 if (adev->gfx.rlc.funcs) { 2169 if (adev->gfx.rlc.funcs->init) { 2170 r = adev->gfx.rlc.funcs->init(adev); 2171 if (r) { 2172 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2173 return r; 2174 } 2175 } 2176 } 2177 2178 r = gfx_v9_0_mec_init(adev); 2179 if (r) { 2180 DRM_ERROR("Failed to init MEC BOs!\n"); 2181 return r; 2182 } 2183 2184 /* set up the gfx ring */ 2185 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2186 ring = &adev->gfx.gfx_ring[i]; 2187 ring->ring_obj = NULL; 2188 if (!i) 2189 sprintf(ring->name, "gfx"); 2190 else 2191 sprintf(ring->name, "gfx_%d", i); 2192 ring->use_doorbell = true; 2193 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2194 2195 /* disable scheduler on the real ring */ 2196 ring->no_scheduler = true; 2197 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2198 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2199 AMDGPU_RING_PRIO_DEFAULT, NULL); 2200 if (r) 2201 return r; 2202 } 2203 2204 /* set up the software rings */ 2205 if (adev->gfx.num_gfx_rings) { 2206 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2207 ring = &adev->gfx.sw_gfx_ring[i]; 2208 ring->ring_obj = NULL; 2209 sprintf(ring->name, amdgpu_sw_ring_name(i)); 2210 ring->use_doorbell = true; 2211 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2212 ring->is_sw_ring = true; 2213 hw_prio = amdgpu_sw_ring_priority(i); 2214 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2215 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, 2216 NULL); 2217 if (r) 2218 return r; 2219 ring->wptr = 0; 2220 } 2221 2222 /* init the muxer and add software rings */ 2223 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], 2224 GFX9_NUM_SW_GFX_RINGS); 2225 if (r) { 2226 DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); 2227 return r; 2228 } 2229 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2230 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, 2231 &adev->gfx.sw_gfx_ring[i]); 2232 if (r) { 2233 DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); 2234 return r; 2235 } 2236 } 2237 } 2238 2239 /* set up the compute queues - allocate horizontally across pipes */ 2240 ring_id = 0; 2241 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2242 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2243 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2244 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2245 continue; 2246 2247 r = gfx_v9_0_compute_ring_init(adev, 2248 ring_id, 2249 i, k, j); 2250 if (r) 2251 return r; 2252 2253 ring_id++; 2254 } 2255 } 2256 } 2257 2258 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2259 if (r) { 2260 DRM_ERROR("Failed to init KIQ BOs!\n"); 2261 return r; 2262 } 2263 2264 kiq = &adev->gfx.kiq; 2265 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2266 if (r) 2267 return r; 2268 2269 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2270 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2271 if (r) 2272 return r; 2273 2274 adev->gfx.ce_ram_size = 0x8000; 2275 2276 r = gfx_v9_0_gpu_early_init(adev); 2277 if (r) 2278 return r; 2279 2280 return 0; 2281 } 2282 2283 2284 static int gfx_v9_0_sw_fini(void *handle) 2285 { 2286 int i; 2287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2288 2289 if (adev->gfx.num_gfx_rings) { 2290 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 2291 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); 2292 amdgpu_ring_mux_fini(&adev->gfx.muxer); 2293 } 2294 2295 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2296 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2297 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2298 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2299 2300 amdgpu_gfx_mqd_sw_fini(adev); 2301 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2302 amdgpu_gfx_kiq_fini(adev); 2303 2304 gfx_v9_0_mec_fini(adev); 2305 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2306 &adev->gfx.rlc.clear_state_gpu_addr, 2307 (void **)&adev->gfx.rlc.cs_ptr); 2308 if (adev->flags & AMD_IS_APU) { 2309 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2310 &adev->gfx.rlc.cp_table_gpu_addr, 2311 (void **)&adev->gfx.rlc.cp_table_ptr); 2312 } 2313 gfx_v9_0_free_microcode(adev); 2314 2315 return 0; 2316 } 2317 2318 2319 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2320 { 2321 /* TODO */ 2322 } 2323 2324 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2325 u32 instance) 2326 { 2327 u32 data; 2328 2329 if (instance == 0xffffffff) 2330 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2331 else 2332 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2333 2334 if (se_num == 0xffffffff) 2335 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2336 else 2337 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2338 2339 if (sh_num == 0xffffffff) 2340 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2341 else 2342 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2343 2344 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2345 } 2346 2347 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2348 { 2349 u32 data, mask; 2350 2351 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2352 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2353 2354 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2355 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2356 2357 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2358 adev->gfx.config.max_sh_per_se); 2359 2360 return (~data) & mask; 2361 } 2362 2363 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2364 { 2365 int i, j; 2366 u32 data; 2367 u32 active_rbs = 0; 2368 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2369 adev->gfx.config.max_sh_per_se; 2370 2371 mutex_lock(&adev->grbm_idx_mutex); 2372 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2373 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2374 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2375 data = gfx_v9_0_get_rb_active_bitmap(adev); 2376 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2377 rb_bitmap_width_per_sh); 2378 } 2379 } 2380 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2381 mutex_unlock(&adev->grbm_idx_mutex); 2382 2383 adev->gfx.config.backend_enable_mask = active_rbs; 2384 adev->gfx.config.num_rbs = hweight32(active_rbs); 2385 } 2386 2387 #define DEFAULT_SH_MEM_BASES (0x6000) 2388 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2389 { 2390 int i; 2391 uint32_t sh_mem_config; 2392 uint32_t sh_mem_bases; 2393 2394 /* 2395 * Configure apertures: 2396 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2397 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2398 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2399 */ 2400 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2401 2402 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2403 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2404 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2405 2406 mutex_lock(&adev->srbm_mutex); 2407 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2408 soc15_grbm_select(adev, 0, 0, 0, i); 2409 /* CP and shaders */ 2410 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2411 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2412 } 2413 soc15_grbm_select(adev, 0, 0, 0, 0); 2414 mutex_unlock(&adev->srbm_mutex); 2415 2416 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2417 access. These should be enabled by FW for target VMIDs. */ 2418 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2419 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2420 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2421 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2422 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2423 } 2424 } 2425 2426 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2427 { 2428 int vmid; 2429 2430 /* 2431 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2432 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2433 * the driver can enable them for graphics. VMID0 should maintain 2434 * access so that HWS firmware can save/restore entries. 2435 */ 2436 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2437 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2438 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2439 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2440 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2441 } 2442 } 2443 2444 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2445 { 2446 uint32_t tmp; 2447 2448 switch (adev->ip_versions[GC_HWIP][0]) { 2449 case IP_VERSION(9, 4, 1): 2450 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2451 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2452 DISABLE_BARRIER_WAITCNT, 1); 2453 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2454 break; 2455 default: 2456 break; 2457 } 2458 } 2459 2460 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2461 { 2462 u32 tmp; 2463 int i; 2464 2465 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2466 2467 gfx_v9_0_tiling_mode_table_init(adev); 2468 2469 if (adev->gfx.num_gfx_rings) 2470 gfx_v9_0_setup_rb(adev); 2471 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2472 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2473 2474 /* XXX SH_MEM regs */ 2475 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2476 mutex_lock(&adev->srbm_mutex); 2477 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2478 soc15_grbm_select(adev, 0, 0, 0, i); 2479 /* CP and shaders */ 2480 if (i == 0) { 2481 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2482 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2483 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2484 !!adev->gmc.noretry); 2485 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2486 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2487 } else { 2488 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2489 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2490 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2491 !!adev->gmc.noretry); 2492 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2493 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2494 (adev->gmc.private_aperture_start >> 48)); 2495 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2496 (adev->gmc.shared_aperture_start >> 48)); 2497 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2498 } 2499 } 2500 soc15_grbm_select(adev, 0, 0, 0, 0); 2501 2502 mutex_unlock(&adev->srbm_mutex); 2503 2504 gfx_v9_0_init_compute_vmid(adev); 2505 gfx_v9_0_init_gds_vmid(adev); 2506 gfx_v9_0_init_sq_config(adev); 2507 } 2508 2509 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2510 { 2511 u32 i, j, k; 2512 u32 mask; 2513 2514 mutex_lock(&adev->grbm_idx_mutex); 2515 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2516 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2517 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2518 for (k = 0; k < adev->usec_timeout; k++) { 2519 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2520 break; 2521 udelay(1); 2522 } 2523 if (k == adev->usec_timeout) { 2524 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2525 0xffffffff, 0xffffffff); 2526 mutex_unlock(&adev->grbm_idx_mutex); 2527 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2528 i, j); 2529 return; 2530 } 2531 } 2532 } 2533 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2534 mutex_unlock(&adev->grbm_idx_mutex); 2535 2536 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2537 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2538 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2539 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2540 for (k = 0; k < adev->usec_timeout; k++) { 2541 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2542 break; 2543 udelay(1); 2544 } 2545 } 2546 2547 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2548 bool enable) 2549 { 2550 u32 tmp; 2551 2552 /* These interrupts should be enabled to drive DS clock */ 2553 2554 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2555 2556 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2557 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2558 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2559 if(adev->gfx.num_gfx_rings) 2560 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2561 2562 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2563 } 2564 2565 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2566 { 2567 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2568 /* csib */ 2569 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2570 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2571 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2572 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2573 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2574 adev->gfx.rlc.clear_state_size); 2575 } 2576 2577 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2578 int indirect_offset, 2579 int list_size, 2580 int *unique_indirect_regs, 2581 int unique_indirect_reg_count, 2582 int *indirect_start_offsets, 2583 int *indirect_start_offsets_count, 2584 int max_start_offsets_count) 2585 { 2586 int idx; 2587 2588 for (; indirect_offset < list_size; indirect_offset++) { 2589 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2590 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2591 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2592 2593 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2594 indirect_offset += 2; 2595 2596 /* look for the matching indice */ 2597 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2598 if (unique_indirect_regs[idx] == 2599 register_list_format[indirect_offset] || 2600 !unique_indirect_regs[idx]) 2601 break; 2602 } 2603 2604 BUG_ON(idx >= unique_indirect_reg_count); 2605 2606 if (!unique_indirect_regs[idx]) 2607 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2608 2609 indirect_offset++; 2610 } 2611 } 2612 } 2613 2614 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2615 { 2616 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2617 int unique_indirect_reg_count = 0; 2618 2619 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2620 int indirect_start_offsets_count = 0; 2621 2622 int list_size = 0; 2623 int i = 0, j = 0; 2624 u32 tmp = 0; 2625 2626 u32 *register_list_format = 2627 kmemdup(adev->gfx.rlc.register_list_format, 2628 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2629 if (!register_list_format) 2630 return -ENOMEM; 2631 2632 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2633 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2634 gfx_v9_1_parse_ind_reg_list(register_list_format, 2635 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2636 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2637 unique_indirect_regs, 2638 unique_indirect_reg_count, 2639 indirect_start_offsets, 2640 &indirect_start_offsets_count, 2641 ARRAY_SIZE(indirect_start_offsets)); 2642 2643 /* enable auto inc in case it is disabled */ 2644 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2645 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2646 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2647 2648 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2649 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2650 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2651 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2652 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2653 adev->gfx.rlc.register_restore[i]); 2654 2655 /* load indirect register */ 2656 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2657 adev->gfx.rlc.reg_list_format_start); 2658 2659 /* direct register portion */ 2660 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2661 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2662 register_list_format[i]); 2663 2664 /* indirect register portion */ 2665 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2666 if (register_list_format[i] == 0xFFFFFFFF) { 2667 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2668 continue; 2669 } 2670 2671 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2672 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2673 2674 for (j = 0; j < unique_indirect_reg_count; j++) { 2675 if (register_list_format[i] == unique_indirect_regs[j]) { 2676 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2677 break; 2678 } 2679 } 2680 2681 BUG_ON(j >= unique_indirect_reg_count); 2682 2683 i++; 2684 } 2685 2686 /* set save/restore list size */ 2687 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2688 list_size = list_size >> 1; 2689 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2690 adev->gfx.rlc.reg_restore_list_size); 2691 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2692 2693 /* write the starting offsets to RLC scratch ram */ 2694 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2695 adev->gfx.rlc.starting_offsets_start); 2696 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2697 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2698 indirect_start_offsets[i]); 2699 2700 /* load unique indirect regs*/ 2701 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2702 if (unique_indirect_regs[i] != 0) { 2703 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2704 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2705 unique_indirect_regs[i] & 0x3FFFF); 2706 2707 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2708 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2709 unique_indirect_regs[i] >> 20); 2710 } 2711 } 2712 2713 kfree(register_list_format); 2714 return 0; 2715 } 2716 2717 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2718 { 2719 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2720 } 2721 2722 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2723 bool enable) 2724 { 2725 uint32_t data = 0; 2726 uint32_t default_data = 0; 2727 2728 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2729 if (enable) { 2730 /* enable GFXIP control over CGPG */ 2731 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2732 if(default_data != data) 2733 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2734 2735 /* update status */ 2736 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2737 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2738 if(default_data != data) 2739 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2740 } else { 2741 /* restore GFXIP control over GCPG */ 2742 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2743 if(default_data != data) 2744 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2745 } 2746 } 2747 2748 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2749 { 2750 uint32_t data = 0; 2751 2752 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2753 AMD_PG_SUPPORT_GFX_SMG | 2754 AMD_PG_SUPPORT_GFX_DMG)) { 2755 /* init IDLE_POLL_COUNT = 60 */ 2756 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2757 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2758 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2759 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2760 2761 /* init RLC PG Delay */ 2762 data = 0; 2763 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2764 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2765 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2766 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2767 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2768 2769 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2770 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2771 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2772 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2773 2774 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2775 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2776 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2777 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2778 2779 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2780 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2781 2782 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2783 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2784 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2785 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) 2786 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2787 } 2788 } 2789 2790 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2791 bool enable) 2792 { 2793 uint32_t data = 0; 2794 uint32_t default_data = 0; 2795 2796 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2797 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2798 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2799 enable ? 1 : 0); 2800 if (default_data != data) 2801 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2802 } 2803 2804 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2805 bool enable) 2806 { 2807 uint32_t data = 0; 2808 uint32_t default_data = 0; 2809 2810 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2811 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2812 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2813 enable ? 1 : 0); 2814 if(default_data != data) 2815 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2816 } 2817 2818 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2819 bool enable) 2820 { 2821 uint32_t data = 0; 2822 uint32_t default_data = 0; 2823 2824 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2825 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2826 CP_PG_DISABLE, 2827 enable ? 0 : 1); 2828 if(default_data != data) 2829 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2830 } 2831 2832 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2833 bool enable) 2834 { 2835 uint32_t data, default_data; 2836 2837 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2838 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2839 GFX_POWER_GATING_ENABLE, 2840 enable ? 1 : 0); 2841 if(default_data != data) 2842 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2843 } 2844 2845 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2846 bool enable) 2847 { 2848 uint32_t data, default_data; 2849 2850 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2851 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2852 GFX_PIPELINE_PG_ENABLE, 2853 enable ? 1 : 0); 2854 if(default_data != data) 2855 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2856 2857 if (!enable) 2858 /* read any GFX register to wake up GFX */ 2859 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2860 } 2861 2862 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2863 bool enable) 2864 { 2865 uint32_t data, default_data; 2866 2867 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2868 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2869 STATIC_PER_CU_PG_ENABLE, 2870 enable ? 1 : 0); 2871 if(default_data != data) 2872 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2873 } 2874 2875 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2876 bool enable) 2877 { 2878 uint32_t data, default_data; 2879 2880 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2881 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2882 DYN_PER_CU_PG_ENABLE, 2883 enable ? 1 : 0); 2884 if(default_data != data) 2885 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2886 } 2887 2888 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2889 { 2890 gfx_v9_0_init_csb(adev); 2891 2892 /* 2893 * Rlc save restore list is workable since v2_1. 2894 * And it's needed by gfxoff feature. 2895 */ 2896 if (adev->gfx.rlc.is_rlc_v2_1) { 2897 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || 2898 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2899 gfx_v9_1_init_rlc_save_restore_list(adev); 2900 gfx_v9_0_enable_save_restore_machine(adev); 2901 } 2902 2903 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2904 AMD_PG_SUPPORT_GFX_SMG | 2905 AMD_PG_SUPPORT_GFX_DMG | 2906 AMD_PG_SUPPORT_CP | 2907 AMD_PG_SUPPORT_GDS | 2908 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2909 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2910 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2911 gfx_v9_0_init_gfx_power_gating(adev); 2912 } 2913 } 2914 2915 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2916 { 2917 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2918 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2919 gfx_v9_0_wait_for_rlc_serdes(adev); 2920 } 2921 2922 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2923 { 2924 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2925 udelay(50); 2926 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2927 udelay(50); 2928 } 2929 2930 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2931 { 2932 #ifdef AMDGPU_RLC_DEBUG_RETRY 2933 u32 rlc_ucode_ver; 2934 #endif 2935 2936 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2937 udelay(50); 2938 2939 /* carrizo do enable cp interrupt after cp inited */ 2940 if (!(adev->flags & AMD_IS_APU)) { 2941 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2942 udelay(50); 2943 } 2944 2945 #ifdef AMDGPU_RLC_DEBUG_RETRY 2946 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2947 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2948 if(rlc_ucode_ver == 0x108) { 2949 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2950 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2951 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2952 * default is 0x9C4 to create a 100us interval */ 2953 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2954 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2955 * to disable the page fault retry interrupts, default is 2956 * 0x100 (256) */ 2957 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2958 } 2959 #endif 2960 } 2961 2962 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2963 { 2964 const struct rlc_firmware_header_v2_0 *hdr; 2965 const __le32 *fw_data; 2966 unsigned i, fw_size; 2967 2968 if (!adev->gfx.rlc_fw) 2969 return -EINVAL; 2970 2971 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2972 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2973 2974 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2975 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2976 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2977 2978 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2979 RLCG_UCODE_LOADING_START_ADDRESS); 2980 for (i = 0; i < fw_size; i++) 2981 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2982 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2983 2984 return 0; 2985 } 2986 2987 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2988 { 2989 int r; 2990 2991 if (amdgpu_sriov_vf(adev)) { 2992 gfx_v9_0_init_csb(adev); 2993 return 0; 2994 } 2995 2996 adev->gfx.rlc.funcs->stop(adev); 2997 2998 /* disable CG */ 2999 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 3000 3001 gfx_v9_0_init_pg(adev); 3002 3003 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3004 /* legacy rlc firmware loading */ 3005 r = gfx_v9_0_rlc_load_microcode(adev); 3006 if (r) 3007 return r; 3008 } 3009 3010 switch (adev->ip_versions[GC_HWIP][0]) { 3011 case IP_VERSION(9, 2, 2): 3012 case IP_VERSION(9, 1, 0): 3013 if (amdgpu_lbpw == 0) 3014 gfx_v9_0_enable_lbpw(adev, false); 3015 else 3016 gfx_v9_0_enable_lbpw(adev, true); 3017 break; 3018 case IP_VERSION(9, 4, 0): 3019 if (amdgpu_lbpw > 0) 3020 gfx_v9_0_enable_lbpw(adev, true); 3021 else 3022 gfx_v9_0_enable_lbpw(adev, false); 3023 break; 3024 default: 3025 break; 3026 } 3027 3028 adev->gfx.rlc.funcs->start(adev); 3029 3030 return 0; 3031 } 3032 3033 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3034 { 3035 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 3036 3037 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3038 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3039 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 3040 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 3041 udelay(50); 3042 } 3043 3044 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3045 { 3046 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3047 const struct gfx_firmware_header_v1_0 *ce_hdr; 3048 const struct gfx_firmware_header_v1_0 *me_hdr; 3049 const __le32 *fw_data; 3050 unsigned i, fw_size; 3051 3052 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3053 return -EINVAL; 3054 3055 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3056 adev->gfx.pfp_fw->data; 3057 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3058 adev->gfx.ce_fw->data; 3059 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3060 adev->gfx.me_fw->data; 3061 3062 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3063 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3064 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3065 3066 gfx_v9_0_cp_gfx_enable(adev, false); 3067 3068 /* PFP */ 3069 fw_data = (const __le32 *) 3070 (adev->gfx.pfp_fw->data + 3071 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3072 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3073 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3074 for (i = 0; i < fw_size; i++) 3075 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3076 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3077 3078 /* CE */ 3079 fw_data = (const __le32 *) 3080 (adev->gfx.ce_fw->data + 3081 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3082 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3083 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3084 for (i = 0; i < fw_size; i++) 3085 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3086 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3087 3088 /* ME */ 3089 fw_data = (const __le32 *) 3090 (adev->gfx.me_fw->data + 3091 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3092 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3093 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3094 for (i = 0; i < fw_size; i++) 3095 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3096 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3097 3098 return 0; 3099 } 3100 3101 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3102 { 3103 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3104 const struct cs_section_def *sect = NULL; 3105 const struct cs_extent_def *ext = NULL; 3106 int r, i, tmp; 3107 3108 /* init the CP */ 3109 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3110 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3111 3112 gfx_v9_0_cp_gfx_enable(adev, true); 3113 3114 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3115 if (r) { 3116 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3117 return r; 3118 } 3119 3120 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3121 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3122 3123 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3124 amdgpu_ring_write(ring, 0x80000000); 3125 amdgpu_ring_write(ring, 0x80000000); 3126 3127 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3128 for (ext = sect->section; ext->extent != NULL; ++ext) { 3129 if (sect->id == SECT_CONTEXT) { 3130 amdgpu_ring_write(ring, 3131 PACKET3(PACKET3_SET_CONTEXT_REG, 3132 ext->reg_count)); 3133 amdgpu_ring_write(ring, 3134 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3135 for (i = 0; i < ext->reg_count; i++) 3136 amdgpu_ring_write(ring, ext->extent[i]); 3137 } 3138 } 3139 } 3140 3141 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3142 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3143 3144 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3145 amdgpu_ring_write(ring, 0); 3146 3147 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3148 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3149 amdgpu_ring_write(ring, 0x8000); 3150 amdgpu_ring_write(ring, 0x8000); 3151 3152 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3153 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3154 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3155 amdgpu_ring_write(ring, tmp); 3156 amdgpu_ring_write(ring, 0); 3157 3158 amdgpu_ring_commit(ring); 3159 3160 return 0; 3161 } 3162 3163 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3164 { 3165 struct amdgpu_ring *ring; 3166 u32 tmp; 3167 u32 rb_bufsz; 3168 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3169 3170 /* Set the write pointer delay */ 3171 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3172 3173 /* set the RB to use vmid 0 */ 3174 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3175 3176 /* Set ring buffer size */ 3177 ring = &adev->gfx.gfx_ring[0]; 3178 rb_bufsz = order_base_2(ring->ring_size / 8); 3179 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3180 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3181 #ifdef __BIG_ENDIAN 3182 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3183 #endif 3184 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3185 3186 /* Initialize the ring buffer's write pointers */ 3187 ring->wptr = 0; 3188 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3189 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3190 3191 /* set the wb address wether it's enabled or not */ 3192 rptr_addr = ring->rptr_gpu_addr; 3193 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3194 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3195 3196 wptr_gpu_addr = ring->wptr_gpu_addr; 3197 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3198 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3199 3200 mdelay(1); 3201 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3202 3203 rb_addr = ring->gpu_addr >> 8; 3204 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3205 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3206 3207 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3208 if (ring->use_doorbell) { 3209 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3210 DOORBELL_OFFSET, ring->doorbell_index); 3211 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3212 DOORBELL_EN, 1); 3213 } else { 3214 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3215 } 3216 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3217 3218 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3219 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3220 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3221 3222 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3223 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3224 3225 3226 /* start the ring */ 3227 gfx_v9_0_cp_gfx_start(adev); 3228 ring->sched.ready = true; 3229 3230 return 0; 3231 } 3232 3233 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3234 { 3235 if (enable) { 3236 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3237 } else { 3238 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3239 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3240 adev->gfx.kiq.ring.sched.ready = false; 3241 } 3242 udelay(50); 3243 } 3244 3245 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3246 { 3247 const struct gfx_firmware_header_v1_0 *mec_hdr; 3248 const __le32 *fw_data; 3249 unsigned i; 3250 u32 tmp; 3251 3252 if (!adev->gfx.mec_fw) 3253 return -EINVAL; 3254 3255 gfx_v9_0_cp_compute_enable(adev, false); 3256 3257 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3258 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3259 3260 fw_data = (const __le32 *) 3261 (adev->gfx.mec_fw->data + 3262 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3263 tmp = 0; 3264 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3265 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3266 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3267 3268 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3269 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3270 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3271 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3272 3273 /* MEC1 */ 3274 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3275 mec_hdr->jt_offset); 3276 for (i = 0; i < mec_hdr->jt_size; i++) 3277 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3278 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3279 3280 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3281 adev->gfx.mec_fw_version); 3282 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3283 3284 return 0; 3285 } 3286 3287 /* KIQ functions */ 3288 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3289 { 3290 uint32_t tmp; 3291 struct amdgpu_device *adev = ring->adev; 3292 3293 /* tell RLC which is KIQ queue */ 3294 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3295 tmp &= 0xffffff00; 3296 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3297 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3298 tmp |= 0x80; 3299 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3300 } 3301 3302 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3303 { 3304 struct amdgpu_device *adev = ring->adev; 3305 3306 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3307 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3308 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3309 mqd->cp_hqd_queue_priority = 3310 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3311 } 3312 } 3313 } 3314 3315 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3316 { 3317 struct amdgpu_device *adev = ring->adev; 3318 struct v9_mqd *mqd = ring->mqd_ptr; 3319 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3320 uint32_t tmp; 3321 3322 mqd->header = 0xC0310800; 3323 mqd->compute_pipelinestat_enable = 0x00000001; 3324 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3325 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3326 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3327 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3328 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3329 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3330 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3331 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3332 mqd->compute_misc_reserved = 0x00000003; 3333 3334 mqd->dynamic_cu_mask_addr_lo = 3335 lower_32_bits(ring->mqd_gpu_addr 3336 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3337 mqd->dynamic_cu_mask_addr_hi = 3338 upper_32_bits(ring->mqd_gpu_addr 3339 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3340 3341 eop_base_addr = ring->eop_gpu_addr >> 8; 3342 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3343 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3344 3345 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3346 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3347 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3348 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3349 3350 mqd->cp_hqd_eop_control = tmp; 3351 3352 /* enable doorbell? */ 3353 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3354 3355 if (ring->use_doorbell) { 3356 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3357 DOORBELL_OFFSET, ring->doorbell_index); 3358 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3359 DOORBELL_EN, 1); 3360 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3361 DOORBELL_SOURCE, 0); 3362 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3363 DOORBELL_HIT, 0); 3364 } else { 3365 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3366 DOORBELL_EN, 0); 3367 } 3368 3369 mqd->cp_hqd_pq_doorbell_control = tmp; 3370 3371 /* disable the queue if it's active */ 3372 ring->wptr = 0; 3373 mqd->cp_hqd_dequeue_request = 0; 3374 mqd->cp_hqd_pq_rptr = 0; 3375 mqd->cp_hqd_pq_wptr_lo = 0; 3376 mqd->cp_hqd_pq_wptr_hi = 0; 3377 3378 /* set the pointer to the MQD */ 3379 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3380 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3381 3382 /* set MQD vmid to 0 */ 3383 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3384 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3385 mqd->cp_mqd_control = tmp; 3386 3387 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3388 hqd_gpu_addr = ring->gpu_addr >> 8; 3389 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3390 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3391 3392 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3393 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3394 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3395 (order_base_2(ring->ring_size / 4) - 1)); 3396 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3397 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3398 #ifdef __BIG_ENDIAN 3399 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3400 #endif 3401 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3402 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3403 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3404 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3405 mqd->cp_hqd_pq_control = tmp; 3406 3407 /* set the wb address whether it's enabled or not */ 3408 wb_gpu_addr = ring->rptr_gpu_addr; 3409 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3410 mqd->cp_hqd_pq_rptr_report_addr_hi = 3411 upper_32_bits(wb_gpu_addr) & 0xffff; 3412 3413 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3414 wb_gpu_addr = ring->wptr_gpu_addr; 3415 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3416 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3417 3418 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3419 ring->wptr = 0; 3420 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3421 3422 /* set the vmid for the queue */ 3423 mqd->cp_hqd_vmid = 0; 3424 3425 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3426 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3427 mqd->cp_hqd_persistent_state = tmp; 3428 3429 /* set MIN_IB_AVAIL_SIZE */ 3430 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3431 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3432 mqd->cp_hqd_ib_control = tmp; 3433 3434 /* set static priority for a queue/ring */ 3435 gfx_v9_0_mqd_set_priority(ring, mqd); 3436 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3437 3438 /* map_queues packet doesn't need activate the queue, 3439 * so only kiq need set this field. 3440 */ 3441 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3442 mqd->cp_hqd_active = 1; 3443 3444 return 0; 3445 } 3446 3447 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3448 { 3449 struct amdgpu_device *adev = ring->adev; 3450 struct v9_mqd *mqd = ring->mqd_ptr; 3451 int j; 3452 3453 /* disable wptr polling */ 3454 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3455 3456 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3457 mqd->cp_hqd_eop_base_addr_lo); 3458 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3459 mqd->cp_hqd_eop_base_addr_hi); 3460 3461 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3462 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3463 mqd->cp_hqd_eop_control); 3464 3465 /* enable doorbell? */ 3466 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3467 mqd->cp_hqd_pq_doorbell_control); 3468 3469 /* disable the queue if it's active */ 3470 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3471 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3472 for (j = 0; j < adev->usec_timeout; j++) { 3473 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3474 break; 3475 udelay(1); 3476 } 3477 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3478 mqd->cp_hqd_dequeue_request); 3479 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3480 mqd->cp_hqd_pq_rptr); 3481 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3482 mqd->cp_hqd_pq_wptr_lo); 3483 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3484 mqd->cp_hqd_pq_wptr_hi); 3485 } 3486 3487 /* set the pointer to the MQD */ 3488 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3489 mqd->cp_mqd_base_addr_lo); 3490 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3491 mqd->cp_mqd_base_addr_hi); 3492 3493 /* set MQD vmid to 0 */ 3494 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3495 mqd->cp_mqd_control); 3496 3497 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3498 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3499 mqd->cp_hqd_pq_base_lo); 3500 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3501 mqd->cp_hqd_pq_base_hi); 3502 3503 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3504 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3505 mqd->cp_hqd_pq_control); 3506 3507 /* set the wb address whether it's enabled or not */ 3508 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3509 mqd->cp_hqd_pq_rptr_report_addr_lo); 3510 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3511 mqd->cp_hqd_pq_rptr_report_addr_hi); 3512 3513 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3514 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3515 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3516 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3517 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3518 3519 /* enable the doorbell if requested */ 3520 if (ring->use_doorbell) { 3521 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3522 (adev->doorbell_index.kiq * 2) << 2); 3523 /* If GC has entered CGPG, ringing doorbell > first page 3524 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3525 * workaround this issue. And this change has to align with firmware 3526 * update. 3527 */ 3528 if (check_if_enlarge_doorbell_range(adev)) 3529 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3530 (adev->doorbell.size - 4)); 3531 else 3532 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3533 (adev->doorbell_index.userqueue_end * 2) << 2); 3534 } 3535 3536 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3537 mqd->cp_hqd_pq_doorbell_control); 3538 3539 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3540 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3541 mqd->cp_hqd_pq_wptr_lo); 3542 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3543 mqd->cp_hqd_pq_wptr_hi); 3544 3545 /* set the vmid for the queue */ 3546 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3547 3548 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3549 mqd->cp_hqd_persistent_state); 3550 3551 /* activate the queue */ 3552 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3553 mqd->cp_hqd_active); 3554 3555 if (ring->use_doorbell) 3556 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3557 3558 return 0; 3559 } 3560 3561 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3562 { 3563 struct amdgpu_device *adev = ring->adev; 3564 int j; 3565 3566 /* disable the queue if it's active */ 3567 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3568 3569 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3570 3571 for (j = 0; j < adev->usec_timeout; j++) { 3572 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3573 break; 3574 udelay(1); 3575 } 3576 3577 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3578 DRM_DEBUG("KIQ dequeue request failed.\n"); 3579 3580 /* Manual disable if dequeue request times out */ 3581 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3582 } 3583 3584 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3585 0); 3586 } 3587 3588 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3589 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3590 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3591 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3592 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3593 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3594 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3595 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3596 3597 return 0; 3598 } 3599 3600 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3601 { 3602 struct amdgpu_device *adev = ring->adev; 3603 struct v9_mqd *mqd = ring->mqd_ptr; 3604 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3605 struct v9_mqd *tmp_mqd; 3606 3607 gfx_v9_0_kiq_setting(ring); 3608 3609 /* GPU could be in bad state during probe, driver trigger the reset 3610 * after load the SMU, in this case , the mqd is not be initialized. 3611 * driver need to re-init the mqd. 3612 * check mqd->cp_hqd_pq_control since this value should not be 0 3613 */ 3614 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3615 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3616 /* for GPU_RESET case , reset MQD to a clean status */ 3617 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3618 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3619 3620 /* reset ring buffer */ 3621 ring->wptr = 0; 3622 amdgpu_ring_clear_ring(ring); 3623 3624 mutex_lock(&adev->srbm_mutex); 3625 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3626 gfx_v9_0_kiq_init_register(ring); 3627 soc15_grbm_select(adev, 0, 0, 0, 0); 3628 mutex_unlock(&adev->srbm_mutex); 3629 } else { 3630 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3631 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3632 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3633 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3634 amdgpu_ring_clear_ring(ring); 3635 mutex_lock(&adev->srbm_mutex); 3636 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3637 gfx_v9_0_mqd_init(ring); 3638 gfx_v9_0_kiq_init_register(ring); 3639 soc15_grbm_select(adev, 0, 0, 0, 0); 3640 mutex_unlock(&adev->srbm_mutex); 3641 3642 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3643 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3644 } 3645 3646 return 0; 3647 } 3648 3649 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3650 { 3651 struct amdgpu_device *adev = ring->adev; 3652 struct v9_mqd *mqd = ring->mqd_ptr; 3653 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3654 struct v9_mqd *tmp_mqd; 3655 3656 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3657 * is not be initialized before 3658 */ 3659 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3660 3661 if (!tmp_mqd->cp_hqd_pq_control || 3662 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3663 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3664 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3665 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3666 mutex_lock(&adev->srbm_mutex); 3667 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3668 gfx_v9_0_mqd_init(ring); 3669 soc15_grbm_select(adev, 0, 0, 0, 0); 3670 mutex_unlock(&adev->srbm_mutex); 3671 3672 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3673 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3674 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3675 /* reset MQD to a clean status */ 3676 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3677 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3678 3679 /* reset ring buffer */ 3680 ring->wptr = 0; 3681 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3682 amdgpu_ring_clear_ring(ring); 3683 } else { 3684 amdgpu_ring_clear_ring(ring); 3685 } 3686 3687 return 0; 3688 } 3689 3690 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3691 { 3692 struct amdgpu_ring *ring; 3693 int r; 3694 3695 ring = &adev->gfx.kiq.ring; 3696 3697 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3698 if (unlikely(r != 0)) 3699 return r; 3700 3701 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3702 if (unlikely(r != 0)) 3703 return r; 3704 3705 gfx_v9_0_kiq_init_queue(ring); 3706 amdgpu_bo_kunmap(ring->mqd_obj); 3707 ring->mqd_ptr = NULL; 3708 amdgpu_bo_unreserve(ring->mqd_obj); 3709 ring->sched.ready = true; 3710 return 0; 3711 } 3712 3713 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3714 { 3715 struct amdgpu_ring *ring = NULL; 3716 int r = 0, i; 3717 3718 gfx_v9_0_cp_compute_enable(adev, true); 3719 3720 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3721 ring = &adev->gfx.compute_ring[i]; 3722 3723 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3724 if (unlikely(r != 0)) 3725 goto done; 3726 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3727 if (!r) { 3728 r = gfx_v9_0_kcq_init_queue(ring); 3729 amdgpu_bo_kunmap(ring->mqd_obj); 3730 ring->mqd_ptr = NULL; 3731 } 3732 amdgpu_bo_unreserve(ring->mqd_obj); 3733 if (r) 3734 goto done; 3735 } 3736 3737 r = amdgpu_gfx_enable_kcq(adev); 3738 done: 3739 return r; 3740 } 3741 3742 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3743 { 3744 int r, i; 3745 struct amdgpu_ring *ring; 3746 3747 if (!(adev->flags & AMD_IS_APU)) 3748 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3749 3750 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3751 if (adev->gfx.num_gfx_rings) { 3752 /* legacy firmware loading */ 3753 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3754 if (r) 3755 return r; 3756 } 3757 3758 r = gfx_v9_0_cp_compute_load_microcode(adev); 3759 if (r) 3760 return r; 3761 } 3762 3763 r = gfx_v9_0_kiq_resume(adev); 3764 if (r) 3765 return r; 3766 3767 if (adev->gfx.num_gfx_rings) { 3768 r = gfx_v9_0_cp_gfx_resume(adev); 3769 if (r) 3770 return r; 3771 } 3772 3773 r = gfx_v9_0_kcq_resume(adev); 3774 if (r) 3775 return r; 3776 3777 if (adev->gfx.num_gfx_rings) { 3778 ring = &adev->gfx.gfx_ring[0]; 3779 r = amdgpu_ring_test_helper(ring); 3780 if (r) 3781 return r; 3782 } 3783 3784 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3785 ring = &adev->gfx.compute_ring[i]; 3786 amdgpu_ring_test_helper(ring); 3787 } 3788 3789 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3790 3791 return 0; 3792 } 3793 3794 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3795 { 3796 u32 tmp; 3797 3798 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && 3799 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) 3800 return; 3801 3802 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3803 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3804 adev->df.hash_status.hash_64k); 3805 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3806 adev->df.hash_status.hash_2m); 3807 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3808 adev->df.hash_status.hash_1g); 3809 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3810 } 3811 3812 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3813 { 3814 if (adev->gfx.num_gfx_rings) 3815 gfx_v9_0_cp_gfx_enable(adev, enable); 3816 gfx_v9_0_cp_compute_enable(adev, enable); 3817 } 3818 3819 static int gfx_v9_0_hw_init(void *handle) 3820 { 3821 int r; 3822 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3823 3824 if (!amdgpu_sriov_vf(adev)) 3825 gfx_v9_0_init_golden_registers(adev); 3826 3827 gfx_v9_0_constants_init(adev); 3828 3829 gfx_v9_0_init_tcp_config(adev); 3830 3831 r = adev->gfx.rlc.funcs->resume(adev); 3832 if (r) 3833 return r; 3834 3835 r = gfx_v9_0_cp_resume(adev); 3836 if (r) 3837 return r; 3838 3839 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 3840 gfx_v9_4_2_set_power_brake_sequence(adev); 3841 3842 return r; 3843 } 3844 3845 static int gfx_v9_0_hw_fini(void *handle) 3846 { 3847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3848 3849 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3850 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3851 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3852 3853 /* DF freeze and kcq disable will fail */ 3854 if (!amdgpu_ras_intr_triggered()) 3855 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3856 amdgpu_gfx_disable_kcq(adev); 3857 3858 if (amdgpu_sriov_vf(adev)) { 3859 gfx_v9_0_cp_gfx_enable(adev, false); 3860 /* must disable polling for SRIOV when hw finished, otherwise 3861 * CPC engine may still keep fetching WB address which is already 3862 * invalid after sw finished and trigger DMAR reading error in 3863 * hypervisor side. 3864 */ 3865 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3866 return 0; 3867 } 3868 3869 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3870 * otherwise KIQ is hanging when binding back 3871 */ 3872 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3873 mutex_lock(&adev->srbm_mutex); 3874 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3875 adev->gfx.kiq.ring.pipe, 3876 adev->gfx.kiq.ring.queue, 0); 3877 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3878 soc15_grbm_select(adev, 0, 0, 0, 0); 3879 mutex_unlock(&adev->srbm_mutex); 3880 } 3881 3882 gfx_v9_0_cp_enable(adev, false); 3883 3884 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3885 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3886 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { 3887 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3888 return 0; 3889 } 3890 3891 adev->gfx.rlc.funcs->stop(adev); 3892 return 0; 3893 } 3894 3895 static int gfx_v9_0_suspend(void *handle) 3896 { 3897 return gfx_v9_0_hw_fini(handle); 3898 } 3899 3900 static int gfx_v9_0_resume(void *handle) 3901 { 3902 return gfx_v9_0_hw_init(handle); 3903 } 3904 3905 static bool gfx_v9_0_is_idle(void *handle) 3906 { 3907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3908 3909 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3910 GRBM_STATUS, GUI_ACTIVE)) 3911 return false; 3912 else 3913 return true; 3914 } 3915 3916 static int gfx_v9_0_wait_for_idle(void *handle) 3917 { 3918 unsigned i; 3919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3920 3921 for (i = 0; i < adev->usec_timeout; i++) { 3922 if (gfx_v9_0_is_idle(handle)) 3923 return 0; 3924 udelay(1); 3925 } 3926 return -ETIMEDOUT; 3927 } 3928 3929 static int gfx_v9_0_soft_reset(void *handle) 3930 { 3931 u32 grbm_soft_reset = 0; 3932 u32 tmp; 3933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3934 3935 /* GRBM_STATUS */ 3936 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3937 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3938 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3939 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3940 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3941 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3942 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3943 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3944 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3945 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3946 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3947 } 3948 3949 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3950 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3951 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3952 } 3953 3954 /* GRBM_STATUS2 */ 3955 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3956 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3957 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3958 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3959 3960 3961 if (grbm_soft_reset) { 3962 /* stop the rlc */ 3963 adev->gfx.rlc.funcs->stop(adev); 3964 3965 if (adev->gfx.num_gfx_rings) 3966 /* Disable GFX parsing/prefetching */ 3967 gfx_v9_0_cp_gfx_enable(adev, false); 3968 3969 /* Disable MEC parsing/prefetching */ 3970 gfx_v9_0_cp_compute_enable(adev, false); 3971 3972 if (grbm_soft_reset) { 3973 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3974 tmp |= grbm_soft_reset; 3975 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3976 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3977 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3978 3979 udelay(50); 3980 3981 tmp &= ~grbm_soft_reset; 3982 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3983 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3984 } 3985 3986 /* Wait a little for things to settle down */ 3987 udelay(50); 3988 } 3989 return 0; 3990 } 3991 3992 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 3993 { 3994 signed long r, cnt = 0; 3995 unsigned long flags; 3996 uint32_t seq, reg_val_offs = 0; 3997 uint64_t value = 0; 3998 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3999 struct amdgpu_ring *ring = &kiq->ring; 4000 4001 BUG_ON(!ring->funcs->emit_rreg); 4002 4003 spin_lock_irqsave(&kiq->ring_lock, flags); 4004 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 4005 pr_err("critical bug! too many kiq readers\n"); 4006 goto failed_unlock; 4007 } 4008 amdgpu_ring_alloc(ring, 32); 4009 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4010 amdgpu_ring_write(ring, 9 | /* src: register*/ 4011 (5 << 8) | /* dst: memory */ 4012 (1 << 16) | /* count sel */ 4013 (1 << 20)); /* write confirm */ 4014 amdgpu_ring_write(ring, 0); 4015 amdgpu_ring_write(ring, 0); 4016 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4017 reg_val_offs * 4)); 4018 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4019 reg_val_offs * 4)); 4020 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 4021 if (r) 4022 goto failed_undo; 4023 4024 amdgpu_ring_commit(ring); 4025 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4026 4027 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4028 4029 /* don't wait anymore for gpu reset case because this way may 4030 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 4031 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 4032 * never return if we keep waiting in virt_kiq_rreg, which cause 4033 * gpu_recover() hang there. 4034 * 4035 * also don't wait anymore for IRQ context 4036 * */ 4037 if (r < 1 && (amdgpu_in_reset(adev))) 4038 goto failed_kiq_read; 4039 4040 might_sleep(); 4041 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 4042 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 4043 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4044 } 4045 4046 if (cnt > MAX_KIQ_REG_TRY) 4047 goto failed_kiq_read; 4048 4049 mb(); 4050 value = (uint64_t)adev->wb.wb[reg_val_offs] | 4051 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 4052 amdgpu_device_wb_free(adev, reg_val_offs); 4053 return value; 4054 4055 failed_undo: 4056 amdgpu_ring_undo(ring); 4057 failed_unlock: 4058 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4059 failed_kiq_read: 4060 if (reg_val_offs) 4061 amdgpu_device_wb_free(adev, reg_val_offs); 4062 pr_err("failed to read gpu clock\n"); 4063 return ~0; 4064 } 4065 4066 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4067 { 4068 uint64_t clock, clock_lo, clock_hi, hi_check; 4069 4070 switch (adev->ip_versions[GC_HWIP][0]) { 4071 case IP_VERSION(9, 3, 0): 4072 preempt_disable(); 4073 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4074 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4075 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 4076 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 4077 * roughly every 42 seconds. 4078 */ 4079 if (hi_check != clock_hi) { 4080 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4081 clock_hi = hi_check; 4082 } 4083 preempt_enable(); 4084 clock = clock_lo | (clock_hi << 32ULL); 4085 break; 4086 default: 4087 amdgpu_gfx_off_ctrl(adev, false); 4088 mutex_lock(&adev->gfx.gpu_clock_mutex); 4089 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { 4090 clock = gfx_v9_0_kiq_read_clock(adev); 4091 } else { 4092 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4093 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4094 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4095 } 4096 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4097 amdgpu_gfx_off_ctrl(adev, true); 4098 break; 4099 } 4100 return clock; 4101 } 4102 4103 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4104 uint32_t vmid, 4105 uint32_t gds_base, uint32_t gds_size, 4106 uint32_t gws_base, uint32_t gws_size, 4107 uint32_t oa_base, uint32_t oa_size) 4108 { 4109 struct amdgpu_device *adev = ring->adev; 4110 4111 /* GDS Base */ 4112 gfx_v9_0_write_data_to_reg(ring, 0, false, 4113 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4114 gds_base); 4115 4116 /* GDS Size */ 4117 gfx_v9_0_write_data_to_reg(ring, 0, false, 4118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4119 gds_size); 4120 4121 /* GWS */ 4122 gfx_v9_0_write_data_to_reg(ring, 0, false, 4123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4124 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4125 4126 /* OA */ 4127 gfx_v9_0_write_data_to_reg(ring, 0, false, 4128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4129 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4130 } 4131 4132 static const u32 vgpr_init_compute_shader[] = 4133 { 4134 0xb07c0000, 0xbe8000ff, 4135 0x000000f8, 0xbf110800, 4136 0x7e000280, 0x7e020280, 4137 0x7e040280, 0x7e060280, 4138 0x7e080280, 0x7e0a0280, 4139 0x7e0c0280, 0x7e0e0280, 4140 0x80808800, 0xbe803200, 4141 0xbf84fff5, 0xbf9c0000, 4142 0xd28c0001, 0x0001007f, 4143 0xd28d0001, 0x0002027e, 4144 0x10020288, 0xb8810904, 4145 0xb7814000, 0xd1196a01, 4146 0x00000301, 0xbe800087, 4147 0xbefc00c1, 0xd89c4000, 4148 0x00020201, 0xd89cc080, 4149 0x00040401, 0x320202ff, 4150 0x00000800, 0x80808100, 4151 0xbf84fff8, 0x7e020280, 4152 0xbf810000, 0x00000000, 4153 }; 4154 4155 static const u32 sgpr_init_compute_shader[] = 4156 { 4157 0xb07c0000, 0xbe8000ff, 4158 0x0000005f, 0xbee50080, 4159 0xbe812c65, 0xbe822c65, 4160 0xbe832c65, 0xbe842c65, 4161 0xbe852c65, 0xb77c0005, 4162 0x80808500, 0xbf84fff8, 4163 0xbe800080, 0xbf810000, 4164 }; 4165 4166 static const u32 vgpr_init_compute_shader_arcturus[] = { 4167 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4168 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4169 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4170 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4171 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4172 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4173 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4174 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4175 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4176 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4177 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4178 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4179 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4180 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4181 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4182 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4183 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4184 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4185 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4186 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4187 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4188 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4189 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4190 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4191 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4192 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4193 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4194 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4195 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4196 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4197 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4198 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4199 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4200 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4201 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4202 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4203 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4204 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4205 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4206 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4207 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4208 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4209 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4210 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4211 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4212 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4213 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4214 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4215 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4216 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4217 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4218 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4219 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4220 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4221 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4222 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4223 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4224 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4225 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4226 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4227 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4228 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4229 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4230 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4231 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4232 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4233 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4234 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4235 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4236 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4237 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4238 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4239 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4240 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4241 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4242 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4243 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4244 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4245 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4246 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4247 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4248 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4249 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4250 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4251 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4252 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4253 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4254 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4255 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4256 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4257 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4258 0xbf84fff8, 0xbf810000, 4259 }; 4260 4261 /* When below register arrays changed, please update gpr_reg_size, 4262 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4263 to cover all gfx9 ASICs */ 4264 static const struct soc15_reg_entry vgpr_init_regs[] = { 4265 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4266 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4267 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4268 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4269 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4270 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4271 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4272 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4273 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4274 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4275 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4276 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4277 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4278 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4279 }; 4280 4281 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4282 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4283 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4284 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4285 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4286 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4287 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4288 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4289 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4290 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4291 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4292 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4293 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4294 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4295 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4296 }; 4297 4298 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4299 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4300 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4301 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4302 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4303 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4304 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4305 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4306 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4307 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4308 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4309 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4310 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4311 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4312 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4313 }; 4314 4315 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4316 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4317 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4318 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4319 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4320 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4321 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4322 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4323 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4324 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4325 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4326 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4327 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4328 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4329 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4330 }; 4331 4332 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4333 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4334 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4335 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4336 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4337 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4338 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4339 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4340 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4341 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4342 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4343 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4344 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4345 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4346 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4347 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4348 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4349 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4350 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4351 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4352 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4353 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4354 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4355 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4356 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4357 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4358 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4359 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4360 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4361 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4362 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4363 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4364 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4365 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4366 }; 4367 4368 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4369 { 4370 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4371 int i, r; 4372 4373 /* only support when RAS is enabled */ 4374 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4375 return 0; 4376 4377 r = amdgpu_ring_alloc(ring, 7); 4378 if (r) { 4379 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4380 ring->name, r); 4381 return r; 4382 } 4383 4384 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4385 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4386 4387 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4388 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4389 PACKET3_DMA_DATA_DST_SEL(1) | 4390 PACKET3_DMA_DATA_SRC_SEL(2) | 4391 PACKET3_DMA_DATA_ENGINE(0))); 4392 amdgpu_ring_write(ring, 0); 4393 amdgpu_ring_write(ring, 0); 4394 amdgpu_ring_write(ring, 0); 4395 amdgpu_ring_write(ring, 0); 4396 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4397 adev->gds.gds_size); 4398 4399 amdgpu_ring_commit(ring); 4400 4401 for (i = 0; i < adev->usec_timeout; i++) { 4402 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4403 break; 4404 udelay(1); 4405 } 4406 4407 if (i >= adev->usec_timeout) 4408 r = -ETIMEDOUT; 4409 4410 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4411 4412 return r; 4413 } 4414 4415 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4416 { 4417 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4418 struct amdgpu_ib ib; 4419 struct dma_fence *f = NULL; 4420 int r, i; 4421 unsigned total_size, vgpr_offset, sgpr_offset; 4422 u64 gpu_addr; 4423 4424 int compute_dim_x = adev->gfx.config.max_shader_engines * 4425 adev->gfx.config.max_cu_per_sh * 4426 adev->gfx.config.max_sh_per_se; 4427 int sgpr_work_group_size = 5; 4428 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4429 int vgpr_init_shader_size; 4430 const u32 *vgpr_init_shader_ptr; 4431 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4432 4433 /* only support when RAS is enabled */ 4434 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4435 return 0; 4436 4437 /* bail if the compute ring is not ready */ 4438 if (!ring->sched.ready) 4439 return 0; 4440 4441 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 4442 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4443 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4444 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4445 } else { 4446 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4447 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4448 vgpr_init_regs_ptr = vgpr_init_regs; 4449 } 4450 4451 total_size = 4452 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4453 total_size += 4454 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4455 total_size += 4456 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4457 total_size = ALIGN(total_size, 256); 4458 vgpr_offset = total_size; 4459 total_size += ALIGN(vgpr_init_shader_size, 256); 4460 sgpr_offset = total_size; 4461 total_size += sizeof(sgpr_init_compute_shader); 4462 4463 /* allocate an indirect buffer to put the commands in */ 4464 memset(&ib, 0, sizeof(ib)); 4465 r = amdgpu_ib_get(adev, NULL, total_size, 4466 AMDGPU_IB_POOL_DIRECT, &ib); 4467 if (r) { 4468 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4469 return r; 4470 } 4471 4472 /* load the compute shaders */ 4473 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4474 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4475 4476 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4477 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4478 4479 /* init the ib length to 0 */ 4480 ib.length_dw = 0; 4481 4482 /* VGPR */ 4483 /* write the register state for the compute dispatch */ 4484 for (i = 0; i < gpr_reg_size; i++) { 4485 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4486 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4487 - PACKET3_SET_SH_REG_START; 4488 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4489 } 4490 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4491 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4492 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4493 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4494 - PACKET3_SET_SH_REG_START; 4495 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4496 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4497 4498 /* write dispatch packet */ 4499 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4500 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4501 ib.ptr[ib.length_dw++] = 1; /* y */ 4502 ib.ptr[ib.length_dw++] = 1; /* z */ 4503 ib.ptr[ib.length_dw++] = 4504 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4505 4506 /* write CS partial flush packet */ 4507 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4508 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4509 4510 /* SGPR1 */ 4511 /* write the register state for the compute dispatch */ 4512 for (i = 0; i < gpr_reg_size; i++) { 4513 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4514 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4515 - PACKET3_SET_SH_REG_START; 4516 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4517 } 4518 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4519 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4520 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4521 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4522 - PACKET3_SET_SH_REG_START; 4523 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4524 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4525 4526 /* write dispatch packet */ 4527 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4528 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4529 ib.ptr[ib.length_dw++] = 1; /* y */ 4530 ib.ptr[ib.length_dw++] = 1; /* z */ 4531 ib.ptr[ib.length_dw++] = 4532 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4533 4534 /* write CS partial flush packet */ 4535 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4536 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4537 4538 /* SGPR2 */ 4539 /* write the register state for the compute dispatch */ 4540 for (i = 0; i < gpr_reg_size; i++) { 4541 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4542 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4543 - PACKET3_SET_SH_REG_START; 4544 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4545 } 4546 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4547 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4548 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4549 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4550 - PACKET3_SET_SH_REG_START; 4551 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4552 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4553 4554 /* write dispatch packet */ 4555 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4556 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4557 ib.ptr[ib.length_dw++] = 1; /* y */ 4558 ib.ptr[ib.length_dw++] = 1; /* z */ 4559 ib.ptr[ib.length_dw++] = 4560 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4561 4562 /* write CS partial flush packet */ 4563 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4564 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4565 4566 /* shedule the ib on the ring */ 4567 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4568 if (r) { 4569 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4570 goto fail; 4571 } 4572 4573 /* wait for the GPU to finish processing the IB */ 4574 r = dma_fence_wait(f, false); 4575 if (r) { 4576 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4577 goto fail; 4578 } 4579 4580 fail: 4581 amdgpu_ib_free(adev, &ib, NULL); 4582 dma_fence_put(f); 4583 4584 return r; 4585 } 4586 4587 static int gfx_v9_0_early_init(void *handle) 4588 { 4589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4590 4591 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 4592 4593 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 4594 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4595 adev->gfx.num_gfx_rings = 0; 4596 else 4597 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4598 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4599 AMDGPU_MAX_COMPUTE_RINGS); 4600 gfx_v9_0_set_kiq_pm4_funcs(adev); 4601 gfx_v9_0_set_ring_funcs(adev); 4602 gfx_v9_0_set_irq_funcs(adev); 4603 gfx_v9_0_set_gds_init(adev); 4604 gfx_v9_0_set_rlc_funcs(adev); 4605 4606 /* init rlcg reg access ctrl */ 4607 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4608 4609 return 0; 4610 } 4611 4612 static int gfx_v9_0_ecc_late_init(void *handle) 4613 { 4614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4615 int r; 4616 4617 /* 4618 * Temp workaround to fix the issue that CP firmware fails to 4619 * update read pointer when CPDMA is writing clearing operation 4620 * to GDS in suspend/resume sequence on several cards. So just 4621 * limit this operation in cold boot sequence. 4622 */ 4623 if ((!adev->in_suspend) && 4624 (adev->gds.gds_size)) { 4625 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4626 if (r) 4627 return r; 4628 } 4629 4630 /* requires IBs so do in late init after IB pool is initialized */ 4631 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4632 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4633 else 4634 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4635 4636 if (r) 4637 return r; 4638 4639 if (adev->gfx.ras && 4640 adev->gfx.ras->enable_watchdog_timer) 4641 adev->gfx.ras->enable_watchdog_timer(adev); 4642 4643 return 0; 4644 } 4645 4646 static int gfx_v9_0_late_init(void *handle) 4647 { 4648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4649 int r; 4650 4651 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4652 if (r) 4653 return r; 4654 4655 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4656 if (r) 4657 return r; 4658 4659 r = gfx_v9_0_ecc_late_init(handle); 4660 if (r) 4661 return r; 4662 4663 return 0; 4664 } 4665 4666 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4667 { 4668 uint32_t rlc_setting; 4669 4670 /* if RLC is not enabled, do nothing */ 4671 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4672 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4673 return false; 4674 4675 return true; 4676 } 4677 4678 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4679 { 4680 uint32_t data; 4681 unsigned i; 4682 4683 data = RLC_SAFE_MODE__CMD_MASK; 4684 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4685 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4686 4687 /* wait for RLC_SAFE_MODE */ 4688 for (i = 0; i < adev->usec_timeout; i++) { 4689 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4690 break; 4691 udelay(1); 4692 } 4693 } 4694 4695 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4696 { 4697 uint32_t data; 4698 4699 data = RLC_SAFE_MODE__CMD_MASK; 4700 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4701 } 4702 4703 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4704 bool enable) 4705 { 4706 amdgpu_gfx_rlc_enter_safe_mode(adev); 4707 4708 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4709 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4710 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4711 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4712 } else { 4713 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4714 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4715 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4716 } 4717 4718 amdgpu_gfx_rlc_exit_safe_mode(adev); 4719 } 4720 4721 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4722 bool enable) 4723 { 4724 /* TODO: double check if we need to perform under safe mode */ 4725 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4726 4727 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4728 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4729 else 4730 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4731 4732 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4733 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4734 else 4735 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4736 4737 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4738 } 4739 4740 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4741 bool enable) 4742 { 4743 uint32_t data, def; 4744 4745 amdgpu_gfx_rlc_enter_safe_mode(adev); 4746 4747 /* It is disabled by HW by default */ 4748 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4749 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4750 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4751 4752 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4753 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4754 4755 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4756 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4757 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4758 4759 /* only for Vega10 & Raven1 */ 4760 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4761 4762 if (def != data) 4763 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4764 4765 /* MGLS is a global flag to control all MGLS in GFX */ 4766 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4767 /* 2 - RLC memory Light sleep */ 4768 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4769 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4770 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4771 if (def != data) 4772 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4773 } 4774 /* 3 - CP memory Light sleep */ 4775 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4776 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4777 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4778 if (def != data) 4779 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4780 } 4781 } 4782 } else { 4783 /* 1 - MGCG_OVERRIDE */ 4784 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4785 4786 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4787 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4788 4789 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4790 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4791 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4792 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4793 4794 if (def != data) 4795 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4796 4797 /* 2 - disable MGLS in RLC */ 4798 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4799 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4800 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4801 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4802 } 4803 4804 /* 3 - disable MGLS in CP */ 4805 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4806 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4807 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4808 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4809 } 4810 } 4811 4812 amdgpu_gfx_rlc_exit_safe_mode(adev); 4813 } 4814 4815 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4816 bool enable) 4817 { 4818 uint32_t data, def; 4819 4820 if (!adev->gfx.num_gfx_rings) 4821 return; 4822 4823 amdgpu_gfx_rlc_enter_safe_mode(adev); 4824 4825 /* Enable 3D CGCG/CGLS */ 4826 if (enable) { 4827 /* write cmd to clear cgcg/cgls ov */ 4828 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4829 /* unset CGCG override */ 4830 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4831 /* update CGCG and CGLS override bits */ 4832 if (def != data) 4833 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4834 4835 /* enable 3Dcgcg FSM(0x0000363f) */ 4836 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4837 4838 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4839 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4840 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4841 else 4842 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4843 4844 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4845 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4846 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4847 if (def != data) 4848 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4849 4850 /* set IDLE_POLL_COUNT(0x00900100) */ 4851 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4852 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4853 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4854 if (def != data) 4855 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4856 } else { 4857 /* Disable CGCG/CGLS */ 4858 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4859 /* disable cgcg, cgls should be disabled */ 4860 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4861 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4862 /* disable cgcg and cgls in FSM */ 4863 if (def != data) 4864 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4865 } 4866 4867 amdgpu_gfx_rlc_exit_safe_mode(adev); 4868 } 4869 4870 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4871 bool enable) 4872 { 4873 uint32_t def, data; 4874 4875 amdgpu_gfx_rlc_enter_safe_mode(adev); 4876 4877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4878 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4879 /* unset CGCG override */ 4880 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4882 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4883 else 4884 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4885 /* update CGCG and CGLS override bits */ 4886 if (def != data) 4887 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4888 4889 /* enable cgcg FSM(0x0000363F) */ 4890 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4891 4892 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) 4893 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4894 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4895 else 4896 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4897 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4898 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4899 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4900 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4901 if (def != data) 4902 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4903 4904 /* set IDLE_POLL_COUNT(0x00900100) */ 4905 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4906 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4907 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4908 if (def != data) 4909 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4910 } else { 4911 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4912 /* reset CGCG/CGLS bits */ 4913 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4914 /* disable cgcg and cgls in FSM */ 4915 if (def != data) 4916 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4917 } 4918 4919 amdgpu_gfx_rlc_exit_safe_mode(adev); 4920 } 4921 4922 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4923 bool enable) 4924 { 4925 if (enable) { 4926 /* CGCG/CGLS should be enabled after MGCG/MGLS 4927 * === MGCG + MGLS === 4928 */ 4929 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4930 /* === CGCG /CGLS for GFX 3D Only === */ 4931 gfx_v9_0_update_3d_clock_gating(adev, enable); 4932 /* === CGCG + CGLS === */ 4933 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4934 } else { 4935 /* CGCG/CGLS should be disabled before MGCG/MGLS 4936 * === CGCG + CGLS === 4937 */ 4938 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4939 /* === CGCG /CGLS for GFX 3D Only === */ 4940 gfx_v9_0_update_3d_clock_gating(adev, enable); 4941 /* === MGCG + MGLS === */ 4942 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4943 } 4944 return 0; 4945 } 4946 4947 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4948 { 4949 u32 reg, data; 4950 4951 amdgpu_gfx_off_ctrl(adev, false); 4952 4953 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 4954 if (amdgpu_sriov_is_pp_one_vf(adev)) 4955 data = RREG32_NO_KIQ(reg); 4956 else 4957 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4958 4959 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4960 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4961 4962 if (amdgpu_sriov_is_pp_one_vf(adev)) 4963 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 4964 else 4965 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4966 4967 amdgpu_gfx_off_ctrl(adev, true); 4968 } 4969 4970 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4971 uint32_t offset, 4972 struct soc15_reg_rlcg *entries, int arr_size) 4973 { 4974 int i; 4975 uint32_t reg; 4976 4977 if (!entries) 4978 return false; 4979 4980 for (i = 0; i < arr_size; i++) { 4981 const struct soc15_reg_rlcg *entry; 4982 4983 entry = &entries[i]; 4984 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4985 if (offset == reg) 4986 return true; 4987 } 4988 4989 return false; 4990 } 4991 4992 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4993 { 4994 return gfx_v9_0_check_rlcg_range(adev, offset, 4995 (void *)rlcg_access_gc_9_0, 4996 ARRAY_SIZE(rlcg_access_gc_9_0)); 4997 } 4998 4999 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 5000 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 5001 .set_safe_mode = gfx_v9_0_set_safe_mode, 5002 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 5003 .init = gfx_v9_0_rlc_init, 5004 .get_csb_size = gfx_v9_0_get_csb_size, 5005 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 5006 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 5007 .resume = gfx_v9_0_rlc_resume, 5008 .stop = gfx_v9_0_rlc_stop, 5009 .reset = gfx_v9_0_rlc_reset, 5010 .start = gfx_v9_0_rlc_start, 5011 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 5012 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 5013 }; 5014 5015 static int gfx_v9_0_set_powergating_state(void *handle, 5016 enum amd_powergating_state state) 5017 { 5018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5019 bool enable = (state == AMD_PG_STATE_GATE); 5020 5021 switch (adev->ip_versions[GC_HWIP][0]) { 5022 case IP_VERSION(9, 2, 2): 5023 case IP_VERSION(9, 1, 0): 5024 case IP_VERSION(9, 3, 0): 5025 if (!enable) 5026 amdgpu_gfx_off_ctrl(adev, false); 5027 5028 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5029 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 5030 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 5031 } else { 5032 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 5033 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 5034 } 5035 5036 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5037 gfx_v9_0_enable_cp_power_gating(adev, true); 5038 else 5039 gfx_v9_0_enable_cp_power_gating(adev, false); 5040 5041 /* update gfx cgpg state */ 5042 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 5043 5044 /* update mgcg state */ 5045 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 5046 5047 if (enable) 5048 amdgpu_gfx_off_ctrl(adev, true); 5049 break; 5050 case IP_VERSION(9, 2, 1): 5051 amdgpu_gfx_off_ctrl(adev, enable); 5052 break; 5053 default: 5054 break; 5055 } 5056 5057 return 0; 5058 } 5059 5060 static int gfx_v9_0_set_clockgating_state(void *handle, 5061 enum amd_clockgating_state state) 5062 { 5063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5064 5065 if (amdgpu_sriov_vf(adev)) 5066 return 0; 5067 5068 switch (adev->ip_versions[GC_HWIP][0]) { 5069 case IP_VERSION(9, 0, 1): 5070 case IP_VERSION(9, 2, 1): 5071 case IP_VERSION(9, 4, 0): 5072 case IP_VERSION(9, 2, 2): 5073 case IP_VERSION(9, 1, 0): 5074 case IP_VERSION(9, 4, 1): 5075 case IP_VERSION(9, 3, 0): 5076 case IP_VERSION(9, 4, 2): 5077 gfx_v9_0_update_gfx_clock_gating(adev, 5078 state == AMD_CG_STATE_GATE); 5079 break; 5080 default: 5081 break; 5082 } 5083 return 0; 5084 } 5085 5086 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5087 { 5088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5089 int data; 5090 5091 if (amdgpu_sriov_vf(adev)) 5092 *flags = 0; 5093 5094 /* AMD_CG_SUPPORT_GFX_MGCG */ 5095 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5096 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5097 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5098 5099 /* AMD_CG_SUPPORT_GFX_CGCG */ 5100 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5101 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5102 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5103 5104 /* AMD_CG_SUPPORT_GFX_CGLS */ 5105 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5106 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5107 5108 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5109 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5110 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5111 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5112 5113 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5114 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5115 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5116 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5117 5118 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { 5119 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5120 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5121 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5122 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5123 5124 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5125 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5126 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5127 } 5128 } 5129 5130 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5131 { 5132 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5133 } 5134 5135 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5136 { 5137 struct amdgpu_device *adev = ring->adev; 5138 u64 wptr; 5139 5140 /* XXX check if swapping is necessary on BE */ 5141 if (ring->use_doorbell) { 5142 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5143 } else { 5144 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5145 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5146 } 5147 5148 return wptr; 5149 } 5150 5151 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5152 { 5153 struct amdgpu_device *adev = ring->adev; 5154 5155 if (ring->use_doorbell) { 5156 /* XXX check if swapping is necessary on BE */ 5157 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5158 WDOORBELL64(ring->doorbell_index, ring->wptr); 5159 } else { 5160 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5161 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5162 } 5163 } 5164 5165 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5166 { 5167 struct amdgpu_device *adev = ring->adev; 5168 u32 ref_and_mask, reg_mem_engine; 5169 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5170 5171 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5172 switch (ring->me) { 5173 case 1: 5174 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5175 break; 5176 case 2: 5177 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5178 break; 5179 default: 5180 return; 5181 } 5182 reg_mem_engine = 0; 5183 } else { 5184 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5185 reg_mem_engine = 1; /* pfp */ 5186 } 5187 5188 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5189 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5190 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5191 ref_and_mask, ref_and_mask, 0x20); 5192 } 5193 5194 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5195 struct amdgpu_job *job, 5196 struct amdgpu_ib *ib, 5197 uint32_t flags) 5198 { 5199 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5200 u32 header, control = 0; 5201 5202 if (ib->flags & AMDGPU_IB_FLAG_CE) 5203 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5204 else 5205 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5206 5207 control |= ib->length_dw | (vmid << 24); 5208 5209 if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 5210 control |= INDIRECT_BUFFER_PRE_ENB(1); 5211 5212 if (flags & AMDGPU_IB_PREEMPTED) 5213 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5214 5215 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5216 gfx_v9_0_ring_emit_de_meta(ring, 5217 (!amdgpu_sriov_vf(ring->adev) && 5218 flags & AMDGPU_IB_PREEMPTED) ? 5219 true : false); 5220 } 5221 5222 amdgpu_ring_write(ring, header); 5223 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5224 amdgpu_ring_write(ring, 5225 #ifdef __BIG_ENDIAN 5226 (2 << 0) | 5227 #endif 5228 lower_32_bits(ib->gpu_addr)); 5229 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5230 amdgpu_ring_write(ring, control); 5231 } 5232 5233 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5234 struct amdgpu_job *job, 5235 struct amdgpu_ib *ib, 5236 uint32_t flags) 5237 { 5238 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5239 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5240 5241 /* Currently, there is a high possibility to get wave ID mismatch 5242 * between ME and GDS, leading to a hw deadlock, because ME generates 5243 * different wave IDs than the GDS expects. This situation happens 5244 * randomly when at least 5 compute pipes use GDS ordered append. 5245 * The wave IDs generated by ME are also wrong after suspend/resume. 5246 * Those are probably bugs somewhere else in the kernel driver. 5247 * 5248 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5249 * GDS to 0 for this ring (me/pipe). 5250 */ 5251 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5252 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5253 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5254 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5255 } 5256 5257 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5258 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5259 amdgpu_ring_write(ring, 5260 #ifdef __BIG_ENDIAN 5261 (2 << 0) | 5262 #endif 5263 lower_32_bits(ib->gpu_addr)); 5264 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5265 amdgpu_ring_write(ring, control); 5266 } 5267 5268 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5269 u64 seq, unsigned flags) 5270 { 5271 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5272 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5273 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5274 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 5275 uint32_t dw2 = 0; 5276 5277 /* RELEASE_MEM - flush caches, send int */ 5278 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5279 5280 if (writeback) { 5281 dw2 = EOP_TC_NC_ACTION_EN; 5282 } else { 5283 dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | 5284 EOP_TC_MD_ACTION_EN; 5285 } 5286 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5287 EVENT_INDEX(5); 5288 if (exec) 5289 dw2 |= EOP_EXEC; 5290 5291 amdgpu_ring_write(ring, dw2); 5292 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5293 5294 /* 5295 * the address should be Qword aligned if 64bit write, Dword 5296 * aligned if only send 32bit data low (discard data high) 5297 */ 5298 if (write64bit) 5299 BUG_ON(addr & 0x7); 5300 else 5301 BUG_ON(addr & 0x3); 5302 amdgpu_ring_write(ring, lower_32_bits(addr)); 5303 amdgpu_ring_write(ring, upper_32_bits(addr)); 5304 amdgpu_ring_write(ring, lower_32_bits(seq)); 5305 amdgpu_ring_write(ring, upper_32_bits(seq)); 5306 amdgpu_ring_write(ring, 0); 5307 } 5308 5309 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5310 { 5311 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5312 uint32_t seq = ring->fence_drv.sync_seq; 5313 uint64_t addr = ring->fence_drv.gpu_addr; 5314 5315 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5316 lower_32_bits(addr), upper_32_bits(addr), 5317 seq, 0xffffffff, 4); 5318 } 5319 5320 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5321 unsigned vmid, uint64_t pd_addr) 5322 { 5323 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5324 5325 /* compute doesn't have PFP */ 5326 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5327 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5328 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5329 amdgpu_ring_write(ring, 0x0); 5330 } 5331 } 5332 5333 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5334 { 5335 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5336 } 5337 5338 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5339 { 5340 u64 wptr; 5341 5342 /* XXX check if swapping is necessary on BE */ 5343 if (ring->use_doorbell) 5344 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5345 else 5346 BUG(); 5347 return wptr; 5348 } 5349 5350 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5351 { 5352 struct amdgpu_device *adev = ring->adev; 5353 5354 /* XXX check if swapping is necessary on BE */ 5355 if (ring->use_doorbell) { 5356 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5357 WDOORBELL64(ring->doorbell_index, ring->wptr); 5358 } else{ 5359 BUG(); /* only DOORBELL method supported on gfx9 now */ 5360 } 5361 } 5362 5363 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5364 u64 seq, unsigned int flags) 5365 { 5366 struct amdgpu_device *adev = ring->adev; 5367 5368 /* we only allocate 32bit for each seq wb address */ 5369 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5370 5371 /* write fence seq to the "addr" */ 5372 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5373 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5374 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5375 amdgpu_ring_write(ring, lower_32_bits(addr)); 5376 amdgpu_ring_write(ring, upper_32_bits(addr)); 5377 amdgpu_ring_write(ring, lower_32_bits(seq)); 5378 5379 if (flags & AMDGPU_FENCE_FLAG_INT) { 5380 /* set register to trigger INT */ 5381 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5382 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5383 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5384 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5385 amdgpu_ring_write(ring, 0); 5386 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5387 } 5388 } 5389 5390 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5391 { 5392 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5393 amdgpu_ring_write(ring, 0); 5394 } 5395 5396 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 5397 { 5398 struct amdgpu_device *adev = ring->adev; 5399 struct v9_ce_ib_state ce_payload = {0}; 5400 uint64_t offset, ce_payload_gpu_addr; 5401 void *ce_payload_cpu_addr; 5402 int cnt; 5403 5404 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5405 5406 if (ring->is_mes_queue) { 5407 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5408 gfx[0].gfx_meta_data) + 5409 offsetof(struct v9_gfx_meta_data, ce_payload); 5410 ce_payload_gpu_addr = 5411 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5412 ce_payload_cpu_addr = 5413 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5414 } else { 5415 offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5416 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5417 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5418 } 5419 5420 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5421 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5422 WRITE_DATA_DST_SEL(8) | 5423 WR_CONFIRM) | 5424 WRITE_DATA_CACHE_POLICY(0)); 5425 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5426 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5427 5428 if (resume) 5429 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5430 sizeof(ce_payload) >> 2); 5431 else 5432 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 5433 sizeof(ce_payload) >> 2); 5434 } 5435 5436 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 5437 { 5438 int i, r = 0; 5439 struct amdgpu_device *adev = ring->adev; 5440 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5441 struct amdgpu_ring *kiq_ring = &kiq->ring; 5442 unsigned long flags; 5443 5444 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5445 return -EINVAL; 5446 5447 spin_lock_irqsave(&kiq->ring_lock, flags); 5448 5449 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5450 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5451 return -ENOMEM; 5452 } 5453 5454 /* assert preemption condition */ 5455 amdgpu_ring_set_preempt_cond_exec(ring, false); 5456 5457 ring->trail_seq += 1; 5458 amdgpu_ring_alloc(ring, 13); 5459 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5460 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5461 /*reset the CP_VMID_PREEMPT after trailing fence*/ 5462 amdgpu_ring_emit_wreg(ring, 5463 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5464 0x0); 5465 5466 /* assert IB preemption, emit the trailing fence */ 5467 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5468 ring->trail_fence_gpu_addr, 5469 ring->trail_seq); 5470 5471 amdgpu_ring_commit(kiq_ring); 5472 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5473 5474 /* poll the trailing fence */ 5475 for (i = 0; i < adev->usec_timeout; i++) { 5476 if (ring->trail_seq == 5477 le32_to_cpu(*ring->trail_fence_cpu_addr)) 5478 break; 5479 udelay(1); 5480 } 5481 5482 if (i >= adev->usec_timeout) { 5483 r = -EINVAL; 5484 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5485 } 5486 5487 amdgpu_ring_commit(ring); 5488 5489 /* deassert preemption condition */ 5490 amdgpu_ring_set_preempt_cond_exec(ring, true); 5491 return r; 5492 } 5493 5494 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5495 { 5496 struct amdgpu_device *adev = ring->adev; 5497 struct v9_de_ib_state de_payload = {0}; 5498 uint64_t offset, gds_addr, de_payload_gpu_addr; 5499 void *de_payload_cpu_addr; 5500 int cnt; 5501 5502 if (ring->is_mes_queue) { 5503 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5504 gfx[0].gfx_meta_data) + 5505 offsetof(struct v9_gfx_meta_data, de_payload); 5506 de_payload_gpu_addr = 5507 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5508 de_payload_cpu_addr = 5509 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5510 5511 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5512 gfx[0].gds_backup) + 5513 offsetof(struct v9_gfx_meta_data, de_payload); 5514 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5515 } else { 5516 offset = offsetof(struct v9_gfx_meta_data, de_payload); 5517 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5518 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5519 5520 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5521 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5522 PAGE_SIZE); 5523 } 5524 5525 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5526 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5527 5528 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5529 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5530 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5531 WRITE_DATA_DST_SEL(8) | 5532 WR_CONFIRM) | 5533 WRITE_DATA_CACHE_POLICY(0)); 5534 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5535 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5536 5537 if (resume) 5538 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5539 sizeof(de_payload) >> 2); 5540 else 5541 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5542 sizeof(de_payload) >> 2); 5543 } 5544 5545 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5546 bool secure) 5547 { 5548 uint32_t v = secure ? FRAME_TMZ : 0; 5549 5550 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5551 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5552 } 5553 5554 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5555 { 5556 uint32_t dw2 = 0; 5557 5558 gfx_v9_0_ring_emit_ce_meta(ring, 5559 (!amdgpu_sriov_vf(ring->adev) && 5560 flags & AMDGPU_IB_PREEMPTED) ? true : false); 5561 5562 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5563 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5564 /* set load_global_config & load_global_uconfig */ 5565 dw2 |= 0x8001; 5566 /* set load_cs_sh_regs */ 5567 dw2 |= 0x01000000; 5568 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5569 dw2 |= 0x10002; 5570 5571 /* set load_ce_ram if preamble presented */ 5572 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5573 dw2 |= 0x10000000; 5574 } else { 5575 /* still load_ce_ram if this is the first time preamble presented 5576 * although there is no context switch happens. 5577 */ 5578 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5579 dw2 |= 0x10000000; 5580 } 5581 5582 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5583 amdgpu_ring_write(ring, dw2); 5584 amdgpu_ring_write(ring, 0); 5585 } 5586 5587 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5588 { 5589 unsigned ret; 5590 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5591 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5592 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5593 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5594 ret = ring->wptr & ring->buf_mask; 5595 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5596 return ret; 5597 } 5598 5599 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5600 { 5601 unsigned cur; 5602 BUG_ON(offset > ring->buf_mask); 5603 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5604 5605 cur = (ring->wptr - 1) & ring->buf_mask; 5606 if (likely(cur > offset)) 5607 ring->ring[offset] = cur - offset; 5608 else 5609 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5610 } 5611 5612 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5613 uint32_t reg_val_offs) 5614 { 5615 struct amdgpu_device *adev = ring->adev; 5616 5617 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5618 amdgpu_ring_write(ring, 0 | /* src: register*/ 5619 (5 << 8) | /* dst: memory */ 5620 (1 << 20)); /* write confirm */ 5621 amdgpu_ring_write(ring, reg); 5622 amdgpu_ring_write(ring, 0); 5623 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5624 reg_val_offs * 4)); 5625 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5626 reg_val_offs * 4)); 5627 } 5628 5629 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5630 uint32_t val) 5631 { 5632 uint32_t cmd = 0; 5633 5634 switch (ring->funcs->type) { 5635 case AMDGPU_RING_TYPE_GFX: 5636 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5637 break; 5638 case AMDGPU_RING_TYPE_KIQ: 5639 cmd = (1 << 16); /* no inc addr */ 5640 break; 5641 default: 5642 cmd = WR_CONFIRM; 5643 break; 5644 } 5645 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5646 amdgpu_ring_write(ring, cmd); 5647 amdgpu_ring_write(ring, reg); 5648 amdgpu_ring_write(ring, 0); 5649 amdgpu_ring_write(ring, val); 5650 } 5651 5652 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5653 uint32_t val, uint32_t mask) 5654 { 5655 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5656 } 5657 5658 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5659 uint32_t reg0, uint32_t reg1, 5660 uint32_t ref, uint32_t mask) 5661 { 5662 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5663 struct amdgpu_device *adev = ring->adev; 5664 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5665 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5666 5667 if (fw_version_ok) 5668 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5669 ref, mask, 0x20); 5670 else 5671 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5672 ref, mask); 5673 } 5674 5675 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5676 { 5677 struct amdgpu_device *adev = ring->adev; 5678 uint32_t value = 0; 5679 5680 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5681 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5682 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5683 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5684 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5685 } 5686 5687 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5688 enum amdgpu_interrupt_state state) 5689 { 5690 switch (state) { 5691 case AMDGPU_IRQ_STATE_DISABLE: 5692 case AMDGPU_IRQ_STATE_ENABLE: 5693 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5694 TIME_STAMP_INT_ENABLE, 5695 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5696 break; 5697 default: 5698 break; 5699 } 5700 } 5701 5702 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5703 int me, int pipe, 5704 enum amdgpu_interrupt_state state) 5705 { 5706 u32 mec_int_cntl, mec_int_cntl_reg; 5707 5708 /* 5709 * amdgpu controls only the first MEC. That's why this function only 5710 * handles the setting of interrupts for this specific MEC. All other 5711 * pipes' interrupts are set by amdkfd. 5712 */ 5713 5714 if (me == 1) { 5715 switch (pipe) { 5716 case 0: 5717 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5718 break; 5719 case 1: 5720 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5721 break; 5722 case 2: 5723 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5724 break; 5725 case 3: 5726 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5727 break; 5728 default: 5729 DRM_DEBUG("invalid pipe %d\n", pipe); 5730 return; 5731 } 5732 } else { 5733 DRM_DEBUG("invalid me %d\n", me); 5734 return; 5735 } 5736 5737 switch (state) { 5738 case AMDGPU_IRQ_STATE_DISABLE: 5739 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5740 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5741 TIME_STAMP_INT_ENABLE, 0); 5742 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5743 break; 5744 case AMDGPU_IRQ_STATE_ENABLE: 5745 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5746 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5747 TIME_STAMP_INT_ENABLE, 1); 5748 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5749 break; 5750 default: 5751 break; 5752 } 5753 } 5754 5755 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5756 struct amdgpu_irq_src *source, 5757 unsigned type, 5758 enum amdgpu_interrupt_state state) 5759 { 5760 switch (state) { 5761 case AMDGPU_IRQ_STATE_DISABLE: 5762 case AMDGPU_IRQ_STATE_ENABLE: 5763 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5764 PRIV_REG_INT_ENABLE, 5765 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5766 break; 5767 default: 5768 break; 5769 } 5770 5771 return 0; 5772 } 5773 5774 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5775 struct amdgpu_irq_src *source, 5776 unsigned type, 5777 enum amdgpu_interrupt_state state) 5778 { 5779 switch (state) { 5780 case AMDGPU_IRQ_STATE_DISABLE: 5781 case AMDGPU_IRQ_STATE_ENABLE: 5782 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5783 PRIV_INSTR_INT_ENABLE, 5784 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5785 break; 5786 default: 5787 break; 5788 } 5789 5790 return 0; 5791 } 5792 5793 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5794 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5795 CP_ECC_ERROR_INT_ENABLE, 1) 5796 5797 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5798 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5799 CP_ECC_ERROR_INT_ENABLE, 0) 5800 5801 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5802 struct amdgpu_irq_src *source, 5803 unsigned type, 5804 enum amdgpu_interrupt_state state) 5805 { 5806 switch (state) { 5807 case AMDGPU_IRQ_STATE_DISABLE: 5808 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5809 CP_ECC_ERROR_INT_ENABLE, 0); 5810 DISABLE_ECC_ON_ME_PIPE(1, 0); 5811 DISABLE_ECC_ON_ME_PIPE(1, 1); 5812 DISABLE_ECC_ON_ME_PIPE(1, 2); 5813 DISABLE_ECC_ON_ME_PIPE(1, 3); 5814 break; 5815 5816 case AMDGPU_IRQ_STATE_ENABLE: 5817 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5818 CP_ECC_ERROR_INT_ENABLE, 1); 5819 ENABLE_ECC_ON_ME_PIPE(1, 0); 5820 ENABLE_ECC_ON_ME_PIPE(1, 1); 5821 ENABLE_ECC_ON_ME_PIPE(1, 2); 5822 ENABLE_ECC_ON_ME_PIPE(1, 3); 5823 break; 5824 default: 5825 break; 5826 } 5827 5828 return 0; 5829 } 5830 5831 5832 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5833 struct amdgpu_irq_src *src, 5834 unsigned type, 5835 enum amdgpu_interrupt_state state) 5836 { 5837 switch (type) { 5838 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5839 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5840 break; 5841 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5842 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5843 break; 5844 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5845 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5846 break; 5847 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5848 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5849 break; 5850 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5851 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5852 break; 5853 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5854 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5855 break; 5856 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5857 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5858 break; 5859 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5860 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5861 break; 5862 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5863 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5864 break; 5865 default: 5866 break; 5867 } 5868 return 0; 5869 } 5870 5871 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5872 struct amdgpu_irq_src *source, 5873 struct amdgpu_iv_entry *entry) 5874 { 5875 int i; 5876 u8 me_id, pipe_id, queue_id; 5877 struct amdgpu_ring *ring; 5878 5879 DRM_DEBUG("IH: CP EOP\n"); 5880 me_id = (entry->ring_id & 0x0c) >> 2; 5881 pipe_id = (entry->ring_id & 0x03) >> 0; 5882 queue_id = (entry->ring_id & 0x70) >> 4; 5883 5884 switch (me_id) { 5885 case 0: 5886 if (adev->gfx.num_gfx_rings && 5887 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { 5888 /* Fence signals are handled on the software rings*/ 5889 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 5890 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); 5891 } 5892 break; 5893 case 1: 5894 case 2: 5895 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5896 ring = &adev->gfx.compute_ring[i]; 5897 /* Per-queue interrupt is supported for MEC starting from VI. 5898 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5899 */ 5900 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5901 amdgpu_fence_process(ring); 5902 } 5903 break; 5904 } 5905 return 0; 5906 } 5907 5908 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5909 struct amdgpu_iv_entry *entry) 5910 { 5911 u8 me_id, pipe_id, queue_id; 5912 struct amdgpu_ring *ring; 5913 int i; 5914 5915 me_id = (entry->ring_id & 0x0c) >> 2; 5916 pipe_id = (entry->ring_id & 0x03) >> 0; 5917 queue_id = (entry->ring_id & 0x70) >> 4; 5918 5919 switch (me_id) { 5920 case 0: 5921 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5922 break; 5923 case 1: 5924 case 2: 5925 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5926 ring = &adev->gfx.compute_ring[i]; 5927 if (ring->me == me_id && ring->pipe == pipe_id && 5928 ring->queue == queue_id) 5929 drm_sched_fault(&ring->sched); 5930 } 5931 break; 5932 } 5933 } 5934 5935 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5936 struct amdgpu_irq_src *source, 5937 struct amdgpu_iv_entry *entry) 5938 { 5939 DRM_ERROR("Illegal register access in command stream\n"); 5940 gfx_v9_0_fault(adev, entry); 5941 return 0; 5942 } 5943 5944 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5945 struct amdgpu_irq_src *source, 5946 struct amdgpu_iv_entry *entry) 5947 { 5948 DRM_ERROR("Illegal instruction in command stream\n"); 5949 gfx_v9_0_fault(adev, entry); 5950 return 0; 5951 } 5952 5953 5954 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5955 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5956 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5957 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5958 }, 5959 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5960 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5961 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5962 }, 5963 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5964 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5965 0, 0 5966 }, 5967 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5968 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5969 0, 0 5970 }, 5971 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5972 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5973 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5974 }, 5975 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5976 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5977 0, 0 5978 }, 5979 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5980 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5981 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5982 }, 5983 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5984 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5985 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5986 }, 5987 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5988 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5989 0, 0 5990 }, 5991 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5992 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5993 0, 0 5994 }, 5995 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5996 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5997 0, 0 5998 }, 5999 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 6000 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 6001 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 6002 }, 6003 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 6004 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 6005 0, 0 6006 }, 6007 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6008 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 6009 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 6010 }, 6011 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 6012 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6013 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 6014 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 6015 }, 6016 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 6017 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 6018 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 6019 0, 0 6020 }, 6021 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 6022 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6023 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 6024 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 6025 }, 6026 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 6027 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6028 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 6029 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 6030 }, 6031 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 6032 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6033 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 6034 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 6035 }, 6036 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 6037 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 6038 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 6039 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 6040 }, 6041 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 6042 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 6043 0, 0 6044 }, 6045 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6046 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 6047 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 6048 }, 6049 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6050 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 6051 0, 0 6052 }, 6053 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6054 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 6055 0, 0 6056 }, 6057 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6058 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 6059 0, 0 6060 }, 6061 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6062 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 6063 0, 0 6064 }, 6065 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6066 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 6067 0, 0 6068 }, 6069 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6070 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 6071 0, 0 6072 }, 6073 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6074 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 6075 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 6076 }, 6077 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6078 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 6079 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 6080 }, 6081 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6082 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 6083 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 6084 }, 6085 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6086 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6087 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6088 }, 6089 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6090 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6091 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6092 }, 6093 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6094 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6095 0, 0 6096 }, 6097 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6098 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6099 0, 0 6100 }, 6101 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6102 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6103 0, 0 6104 }, 6105 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6106 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6107 0, 0 6108 }, 6109 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6110 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6111 0, 0 6112 }, 6113 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6114 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6115 0, 0 6116 }, 6117 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6118 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6119 0, 0 6120 }, 6121 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6122 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6123 0, 0 6124 }, 6125 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6126 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6127 0, 0 6128 }, 6129 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6130 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6131 0, 0 6132 }, 6133 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6134 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6135 0, 0 6136 }, 6137 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6138 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6139 0, 0 6140 }, 6141 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6142 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6143 0, 0 6144 }, 6145 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6146 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6147 0, 0 6148 }, 6149 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6150 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6151 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6152 }, 6153 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6154 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6155 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6156 }, 6157 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6158 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6159 0, 0 6160 }, 6161 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6162 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6163 0, 0 6164 }, 6165 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6166 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6167 0, 0 6168 }, 6169 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6170 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6171 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6172 }, 6173 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6174 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6175 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6176 }, 6177 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6178 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6179 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6180 }, 6181 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6182 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6183 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6184 }, 6185 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6186 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6187 0, 0 6188 }, 6189 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6190 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6191 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6192 }, 6193 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6194 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6195 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6196 }, 6197 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6198 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6199 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6200 }, 6201 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6202 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6203 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6204 }, 6205 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6206 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6207 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6208 }, 6209 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6210 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6211 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6212 }, 6213 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6214 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6215 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6216 }, 6217 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6218 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6219 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6220 }, 6221 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6222 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6223 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6224 }, 6225 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6226 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6227 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6228 }, 6229 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6230 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6231 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6232 }, 6233 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6234 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6235 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6236 }, 6237 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6238 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6239 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6240 }, 6241 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6242 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6243 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6244 }, 6245 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6246 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6247 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6248 }, 6249 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6250 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6251 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6252 }, 6253 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6254 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6255 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6256 }, 6257 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6258 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6259 0, 0 6260 }, 6261 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6262 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6263 0, 0 6264 }, 6265 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6266 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6267 0, 0 6268 }, 6269 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6270 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6271 0, 0 6272 }, 6273 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6274 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6275 0, 0 6276 }, 6277 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6278 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6279 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6280 }, 6281 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6282 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6283 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6284 }, 6285 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6286 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6287 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6288 }, 6289 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6290 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6291 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6292 }, 6293 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6294 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6295 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6296 }, 6297 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6298 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6299 0, 0 6300 }, 6301 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6302 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6303 0, 0 6304 }, 6305 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6306 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6307 0, 0 6308 }, 6309 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6310 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6311 0, 0 6312 }, 6313 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6314 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6315 0, 0 6316 }, 6317 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6318 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6319 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6320 }, 6321 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6322 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6323 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6324 }, 6325 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6326 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6327 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6328 }, 6329 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6330 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6331 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6332 }, 6333 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6334 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6335 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6336 }, 6337 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6338 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6339 0, 0 6340 }, 6341 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6342 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6343 0, 0 6344 }, 6345 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6346 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6347 0, 0 6348 }, 6349 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6350 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6351 0, 0 6352 }, 6353 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6354 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6355 0, 0 6356 }, 6357 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6358 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6359 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6360 }, 6361 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6362 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6363 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6364 }, 6365 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6366 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6367 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6368 }, 6369 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6370 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6371 0, 0 6372 }, 6373 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6374 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6375 0, 0 6376 }, 6377 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6378 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6379 0, 0 6380 }, 6381 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6382 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6383 0, 0 6384 }, 6385 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6386 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6387 0, 0 6388 }, 6389 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6390 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6391 0, 0 6392 } 6393 }; 6394 6395 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6396 void *inject_if) 6397 { 6398 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6399 int ret; 6400 struct ta_ras_trigger_error_input block_info = { 0 }; 6401 6402 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6403 return -EINVAL; 6404 6405 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6406 return -EINVAL; 6407 6408 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6409 return -EPERM; 6410 6411 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6412 info->head.type)) { 6413 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6414 ras_gfx_subblocks[info->head.sub_block_index].name, 6415 info->head.type); 6416 return -EPERM; 6417 } 6418 6419 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6420 info->head.type)) { 6421 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6422 ras_gfx_subblocks[info->head.sub_block_index].name, 6423 info->head.type); 6424 return -EPERM; 6425 } 6426 6427 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6428 block_info.sub_block_index = 6429 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6430 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6431 block_info.address = info->address; 6432 block_info.value = info->value; 6433 6434 mutex_lock(&adev->grbm_idx_mutex); 6435 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6436 mutex_unlock(&adev->grbm_idx_mutex); 6437 6438 return ret; 6439 } 6440 6441 static const char *vml2_mems[] = { 6442 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6443 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6444 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6445 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6446 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6447 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6448 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6449 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6450 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6451 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6452 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6453 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6454 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6455 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6456 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6457 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6458 }; 6459 6460 static const char *vml2_walker_mems[] = { 6461 "UTC_VML2_CACHE_PDE0_MEM0", 6462 "UTC_VML2_CACHE_PDE0_MEM1", 6463 "UTC_VML2_CACHE_PDE1_MEM0", 6464 "UTC_VML2_CACHE_PDE1_MEM1", 6465 "UTC_VML2_CACHE_PDE2_MEM0", 6466 "UTC_VML2_CACHE_PDE2_MEM1", 6467 "UTC_VML2_RDIF_LOG_FIFO", 6468 }; 6469 6470 static const char *atc_l2_cache_2m_mems[] = { 6471 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6472 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6473 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6474 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6475 }; 6476 6477 static const char *atc_l2_cache_4k_mems[] = { 6478 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6479 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6480 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6481 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6482 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6483 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6484 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6485 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6486 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6487 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6488 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6489 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6490 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6491 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6492 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6493 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6494 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6495 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6496 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6497 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6498 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6499 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6500 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6501 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6502 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6503 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6504 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6505 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6506 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6507 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6508 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6509 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6510 }; 6511 6512 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6513 struct ras_err_data *err_data) 6514 { 6515 uint32_t i, data; 6516 uint32_t sec_count, ded_count; 6517 6518 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6519 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6520 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6521 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6522 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6523 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6524 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6525 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6526 6527 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6528 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6529 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6530 6531 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6532 if (sec_count) { 6533 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6534 "SEC %d\n", i, vml2_mems[i], sec_count); 6535 err_data->ce_count += sec_count; 6536 } 6537 6538 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6539 if (ded_count) { 6540 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6541 "DED %d\n", i, vml2_mems[i], ded_count); 6542 err_data->ue_count += ded_count; 6543 } 6544 } 6545 6546 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6547 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6548 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6549 6550 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6551 SEC_COUNT); 6552 if (sec_count) { 6553 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6554 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6555 err_data->ce_count += sec_count; 6556 } 6557 6558 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6559 DED_COUNT); 6560 if (ded_count) { 6561 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6562 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6563 err_data->ue_count += ded_count; 6564 } 6565 } 6566 6567 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6568 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6569 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6570 6571 sec_count = (data & 0x00006000L) >> 0xd; 6572 if (sec_count) { 6573 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6574 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6575 sec_count); 6576 err_data->ce_count += sec_count; 6577 } 6578 } 6579 6580 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6581 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6582 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6583 6584 sec_count = (data & 0x00006000L) >> 0xd; 6585 if (sec_count) { 6586 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6587 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6588 sec_count); 6589 err_data->ce_count += sec_count; 6590 } 6591 6592 ded_count = (data & 0x00018000L) >> 0xf; 6593 if (ded_count) { 6594 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6595 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6596 ded_count); 6597 err_data->ue_count += ded_count; 6598 } 6599 } 6600 6601 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6602 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6603 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6604 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6605 6606 return 0; 6607 } 6608 6609 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6610 const struct soc15_reg_entry *reg, 6611 uint32_t se_id, uint32_t inst_id, uint32_t value, 6612 uint32_t *sec_count, uint32_t *ded_count) 6613 { 6614 uint32_t i; 6615 uint32_t sec_cnt, ded_cnt; 6616 6617 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6618 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6619 gfx_v9_0_ras_fields[i].seg != reg->seg || 6620 gfx_v9_0_ras_fields[i].inst != reg->inst) 6621 continue; 6622 6623 sec_cnt = (value & 6624 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6625 gfx_v9_0_ras_fields[i].sec_count_shift; 6626 if (sec_cnt) { 6627 dev_info(adev->dev, "GFX SubBlock %s, " 6628 "Instance[%d][%d], SEC %d\n", 6629 gfx_v9_0_ras_fields[i].name, 6630 se_id, inst_id, 6631 sec_cnt); 6632 *sec_count += sec_cnt; 6633 } 6634 6635 ded_cnt = (value & 6636 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6637 gfx_v9_0_ras_fields[i].ded_count_shift; 6638 if (ded_cnt) { 6639 dev_info(adev->dev, "GFX SubBlock %s, " 6640 "Instance[%d][%d], DED %d\n", 6641 gfx_v9_0_ras_fields[i].name, 6642 se_id, inst_id, 6643 ded_cnt); 6644 *ded_count += ded_cnt; 6645 } 6646 } 6647 6648 return 0; 6649 } 6650 6651 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6652 { 6653 int i, j, k; 6654 6655 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6656 return; 6657 6658 /* read back registers to clear the counters */ 6659 mutex_lock(&adev->grbm_idx_mutex); 6660 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6661 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6662 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6663 amdgpu_gfx_select_se_sh(adev, j, 0x0, k); 6664 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6665 } 6666 } 6667 } 6668 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6669 mutex_unlock(&adev->grbm_idx_mutex); 6670 6671 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6672 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6673 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6674 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6675 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6676 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6677 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6678 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6679 6680 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6681 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6682 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6683 } 6684 6685 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6686 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6687 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6688 } 6689 6690 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6691 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6692 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6693 } 6694 6695 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6696 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6697 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6698 } 6699 6700 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6701 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6702 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6704 } 6705 6706 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6707 void *ras_error_status) 6708 { 6709 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6710 uint32_t sec_count = 0, ded_count = 0; 6711 uint32_t i, j, k; 6712 uint32_t reg_value; 6713 6714 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6715 return; 6716 6717 err_data->ue_count = 0; 6718 err_data->ce_count = 0; 6719 6720 mutex_lock(&adev->grbm_idx_mutex); 6721 6722 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6723 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6724 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6725 amdgpu_gfx_select_se_sh(adev, j, 0, k); 6726 reg_value = 6727 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6728 if (reg_value) 6729 gfx_v9_0_ras_error_count(adev, 6730 &gfx_v9_0_edc_counter_regs[i], 6731 j, k, reg_value, 6732 &sec_count, &ded_count); 6733 } 6734 } 6735 } 6736 6737 err_data->ce_count += sec_count; 6738 err_data->ue_count += ded_count; 6739 6740 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6741 mutex_unlock(&adev->grbm_idx_mutex); 6742 6743 gfx_v9_0_query_utc_edc_status(adev, err_data); 6744 } 6745 6746 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6747 { 6748 const unsigned int cp_coher_cntl = 6749 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6750 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6751 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6752 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6753 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6754 6755 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6756 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6757 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6758 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6759 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6760 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6761 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6762 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6763 } 6764 6765 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6766 uint32_t pipe, bool enable) 6767 { 6768 struct amdgpu_device *adev = ring->adev; 6769 uint32_t val; 6770 uint32_t wcl_cs_reg; 6771 6772 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6773 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6774 6775 switch (pipe) { 6776 case 0: 6777 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6778 break; 6779 case 1: 6780 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6781 break; 6782 case 2: 6783 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6784 break; 6785 case 3: 6786 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6787 break; 6788 default: 6789 DRM_DEBUG("invalid pipe %d\n", pipe); 6790 return; 6791 } 6792 6793 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6794 6795 } 6796 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6797 { 6798 struct amdgpu_device *adev = ring->adev; 6799 uint32_t val; 6800 int i; 6801 6802 6803 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6804 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6805 * around 25% of gpu resources. 6806 */ 6807 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6808 amdgpu_ring_emit_wreg(ring, 6809 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6810 val); 6811 6812 /* Restrict waves for normal/low priority compute queues as well 6813 * to get best QoS for high priority compute jobs. 6814 * 6815 * amdgpu controls only 1st ME(0-3 CS pipes). 6816 */ 6817 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6818 if (i != ring->pipe) 6819 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6820 6821 } 6822 } 6823 6824 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6825 .name = "gfx_v9_0", 6826 .early_init = gfx_v9_0_early_init, 6827 .late_init = gfx_v9_0_late_init, 6828 .sw_init = gfx_v9_0_sw_init, 6829 .sw_fini = gfx_v9_0_sw_fini, 6830 .hw_init = gfx_v9_0_hw_init, 6831 .hw_fini = gfx_v9_0_hw_fini, 6832 .suspend = gfx_v9_0_suspend, 6833 .resume = gfx_v9_0_resume, 6834 .is_idle = gfx_v9_0_is_idle, 6835 .wait_for_idle = gfx_v9_0_wait_for_idle, 6836 .soft_reset = gfx_v9_0_soft_reset, 6837 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6838 .set_powergating_state = gfx_v9_0_set_powergating_state, 6839 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6840 }; 6841 6842 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6843 .type = AMDGPU_RING_TYPE_GFX, 6844 .align_mask = 0xff, 6845 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6846 .support_64bit_ptrs = true, 6847 .secure_submission_supported = true, 6848 .vmhub = AMDGPU_GFXHUB_0, 6849 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6850 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6851 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6852 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6853 5 + /* COND_EXEC */ 6854 7 + /* PIPELINE_SYNC */ 6855 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6856 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6857 2 + /* VM_FLUSH */ 6858 8 + /* FENCE for VM_FLUSH */ 6859 20 + /* GDS switch */ 6860 4 + /* double SWITCH_BUFFER, 6861 the first COND_EXEC jump to the place just 6862 prior to this double SWITCH_BUFFER */ 6863 5 + /* COND_EXEC */ 6864 7 + /* HDP_flush */ 6865 4 + /* VGT_flush */ 6866 14 + /* CE_META */ 6867 31 + /* DE_META */ 6868 3 + /* CNTX_CTRL */ 6869 5 + /* HDP_INVL */ 6870 8 + 8 + /* FENCE x2 */ 6871 2 + /* SWITCH_BUFFER */ 6872 7, /* gfx_v9_0_emit_mem_sync */ 6873 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6874 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6875 .emit_fence = gfx_v9_0_ring_emit_fence, 6876 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6877 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6878 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6879 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6880 .test_ring = gfx_v9_0_ring_test_ring, 6881 .test_ib = gfx_v9_0_ring_test_ib, 6882 .insert_nop = amdgpu_ring_insert_nop, 6883 .pad_ib = amdgpu_ring_generic_pad_ib, 6884 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6885 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6886 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6887 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6888 .preempt_ib = gfx_v9_0_ring_preempt_ib, 6889 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6890 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6891 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6892 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6893 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6894 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6895 }; 6896 6897 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 6898 .type = AMDGPU_RING_TYPE_GFX, 6899 .align_mask = 0xff, 6900 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6901 .support_64bit_ptrs = true, 6902 .secure_submission_supported = true, 6903 .vmhub = AMDGPU_GFXHUB_0, 6904 .get_rptr = amdgpu_sw_ring_get_rptr_gfx, 6905 .get_wptr = amdgpu_sw_ring_get_wptr_gfx, 6906 .set_wptr = amdgpu_sw_ring_set_wptr_gfx, 6907 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6908 5 + /* COND_EXEC */ 6909 7 + /* PIPELINE_SYNC */ 6910 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6911 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6912 2 + /* VM_FLUSH */ 6913 8 + /* FENCE for VM_FLUSH */ 6914 20 + /* GDS switch */ 6915 4 + /* double SWITCH_BUFFER, 6916 * the first COND_EXEC jump to the place just 6917 * prior to this double SWITCH_BUFFER 6918 */ 6919 5 + /* COND_EXEC */ 6920 7 + /* HDP_flush */ 6921 4 + /* VGT_flush */ 6922 14 + /* CE_META */ 6923 31 + /* DE_META */ 6924 3 + /* CNTX_CTRL */ 6925 5 + /* HDP_INVL */ 6926 8 + 8 + /* FENCE x2 */ 6927 2 + /* SWITCH_BUFFER */ 6928 7, /* gfx_v9_0_emit_mem_sync */ 6929 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6930 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6931 .emit_fence = gfx_v9_0_ring_emit_fence, 6932 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6933 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6934 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6935 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6936 .test_ring = gfx_v9_0_ring_test_ring, 6937 .test_ib = gfx_v9_0_ring_test_ib, 6938 .insert_nop = amdgpu_sw_ring_insert_nop, 6939 .pad_ib = amdgpu_ring_generic_pad_ib, 6940 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6941 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6942 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6943 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6944 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6945 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6946 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6947 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6948 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6949 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6950 }; 6951 6952 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6953 .type = AMDGPU_RING_TYPE_COMPUTE, 6954 .align_mask = 0xff, 6955 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6956 .support_64bit_ptrs = true, 6957 .vmhub = AMDGPU_GFXHUB_0, 6958 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6959 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6960 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6961 .emit_frame_size = 6962 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6963 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6964 5 + /* hdp invalidate */ 6965 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6966 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6967 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6968 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6969 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6970 7 + /* gfx_v9_0_emit_mem_sync */ 6971 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6972 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6973 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6974 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6975 .emit_fence = gfx_v9_0_ring_emit_fence, 6976 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6977 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6978 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6979 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6980 .test_ring = gfx_v9_0_ring_test_ring, 6981 .test_ib = gfx_v9_0_ring_test_ib, 6982 .insert_nop = amdgpu_ring_insert_nop, 6983 .pad_ib = amdgpu_ring_generic_pad_ib, 6984 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6985 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6986 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6987 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6988 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6989 }; 6990 6991 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6992 .type = AMDGPU_RING_TYPE_KIQ, 6993 .align_mask = 0xff, 6994 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6995 .support_64bit_ptrs = true, 6996 .vmhub = AMDGPU_GFXHUB_0, 6997 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6998 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6999 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 7000 .emit_frame_size = 7001 20 + /* gfx_v9_0_ring_emit_gds_switch */ 7002 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 7003 5 + /* hdp invalidate */ 7004 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 7005 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7006 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7007 2 + /* gfx_v9_0_ring_emit_vm_flush */ 7008 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7009 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 7010 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 7011 .test_ring = gfx_v9_0_ring_test_ring, 7012 .insert_nop = amdgpu_ring_insert_nop, 7013 .pad_ib = amdgpu_ring_generic_pad_ib, 7014 .emit_rreg = gfx_v9_0_ring_emit_rreg, 7015 .emit_wreg = gfx_v9_0_ring_emit_wreg, 7016 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 7017 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 7018 }; 7019 7020 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 7021 { 7022 int i; 7023 7024 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 7025 7026 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7027 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 7028 7029 if (adev->gfx.num_gfx_rings) { 7030 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 7031 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; 7032 } 7033 7034 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7035 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 7036 } 7037 7038 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 7039 .set = gfx_v9_0_set_eop_interrupt_state, 7040 .process = gfx_v9_0_eop_irq, 7041 }; 7042 7043 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 7044 .set = gfx_v9_0_set_priv_reg_fault_state, 7045 .process = gfx_v9_0_priv_reg_irq, 7046 }; 7047 7048 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 7049 .set = gfx_v9_0_set_priv_inst_fault_state, 7050 .process = gfx_v9_0_priv_inst_irq, 7051 }; 7052 7053 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 7054 .set = gfx_v9_0_set_cp_ecc_error_state, 7055 .process = amdgpu_gfx_cp_ecc_error_irq, 7056 }; 7057 7058 7059 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 7060 { 7061 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7062 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 7063 7064 adev->gfx.priv_reg_irq.num_types = 1; 7065 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 7066 7067 adev->gfx.priv_inst_irq.num_types = 1; 7068 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 7069 7070 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 7071 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 7072 } 7073 7074 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 7075 { 7076 switch (adev->ip_versions[GC_HWIP][0]) { 7077 case IP_VERSION(9, 0, 1): 7078 case IP_VERSION(9, 2, 1): 7079 case IP_VERSION(9, 4, 0): 7080 case IP_VERSION(9, 2, 2): 7081 case IP_VERSION(9, 1, 0): 7082 case IP_VERSION(9, 4, 1): 7083 case IP_VERSION(9, 3, 0): 7084 case IP_VERSION(9, 4, 2): 7085 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 7086 break; 7087 default: 7088 break; 7089 } 7090 } 7091 7092 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 7093 { 7094 /* init asci gds info */ 7095 switch (adev->ip_versions[GC_HWIP][0]) { 7096 case IP_VERSION(9, 0, 1): 7097 case IP_VERSION(9, 2, 1): 7098 case IP_VERSION(9, 4, 0): 7099 adev->gds.gds_size = 0x10000; 7100 break; 7101 case IP_VERSION(9, 2, 2): 7102 case IP_VERSION(9, 1, 0): 7103 case IP_VERSION(9, 4, 1): 7104 adev->gds.gds_size = 0x1000; 7105 break; 7106 case IP_VERSION(9, 4, 2): 7107 /* aldebaran removed all the GDS internal memory, 7108 * only support GWS opcode in kernel, like barrier 7109 * semaphore.etc */ 7110 adev->gds.gds_size = 0; 7111 break; 7112 default: 7113 adev->gds.gds_size = 0x10000; 7114 break; 7115 } 7116 7117 switch (adev->ip_versions[GC_HWIP][0]) { 7118 case IP_VERSION(9, 0, 1): 7119 case IP_VERSION(9, 4, 0): 7120 adev->gds.gds_compute_max_wave_id = 0x7ff; 7121 break; 7122 case IP_VERSION(9, 2, 1): 7123 adev->gds.gds_compute_max_wave_id = 0x27f; 7124 break; 7125 case IP_VERSION(9, 2, 2): 7126 case IP_VERSION(9, 1, 0): 7127 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 7128 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 7129 else 7130 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 7131 break; 7132 case IP_VERSION(9, 4, 1): 7133 adev->gds.gds_compute_max_wave_id = 0xfff; 7134 break; 7135 case IP_VERSION(9, 4, 2): 7136 /* deprecated for Aldebaran, no usage at all */ 7137 adev->gds.gds_compute_max_wave_id = 0; 7138 break; 7139 default: 7140 /* this really depends on the chip */ 7141 adev->gds.gds_compute_max_wave_id = 0x7ff; 7142 break; 7143 } 7144 7145 adev->gds.gws_size = 64; 7146 adev->gds.oa_size = 16; 7147 } 7148 7149 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7150 u32 bitmap) 7151 { 7152 u32 data; 7153 7154 if (!bitmap) 7155 return; 7156 7157 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7158 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7159 7160 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7161 } 7162 7163 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7164 { 7165 u32 data, mask; 7166 7167 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7168 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7169 7170 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7171 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7172 7173 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7174 7175 return (~data) & mask; 7176 } 7177 7178 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7179 struct amdgpu_cu_info *cu_info) 7180 { 7181 int i, j, k, counter, active_cu_number = 0; 7182 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7183 unsigned disable_masks[4 * 4]; 7184 7185 if (!adev || !cu_info) 7186 return -EINVAL; 7187 7188 /* 7189 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7190 */ 7191 if (adev->gfx.config.max_shader_engines * 7192 adev->gfx.config.max_sh_per_se > 16) 7193 return -EINVAL; 7194 7195 amdgpu_gfx_parse_disable_cu(disable_masks, 7196 adev->gfx.config.max_shader_engines, 7197 adev->gfx.config.max_sh_per_se); 7198 7199 mutex_lock(&adev->grbm_idx_mutex); 7200 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7201 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7202 mask = 1; 7203 ao_bitmap = 0; 7204 counter = 0; 7205 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 7206 gfx_v9_0_set_user_cu_inactive_bitmap( 7207 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7208 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7209 7210 /* 7211 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7212 * 4x4 size array, and it's usually suitable for Vega 7213 * ASICs which has 4*2 SE/SH layout. 7214 * But for Arcturus, SE/SH layout is changed to 8*1. 7215 * To mostly reduce the impact, we make it compatible 7216 * with current bitmap array as below: 7217 * SE4,SH0 --> bitmap[0][1] 7218 * SE5,SH0 --> bitmap[1][1] 7219 * SE6,SH0 --> bitmap[2][1] 7220 * SE7,SH0 --> bitmap[3][1] 7221 */ 7222 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 7223 7224 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7225 if (bitmap & mask) { 7226 if (counter < adev->gfx.config.max_cu_per_sh) 7227 ao_bitmap |= mask; 7228 counter ++; 7229 } 7230 mask <<= 1; 7231 } 7232 active_cu_number += counter; 7233 if (i < 2 && j < 2) 7234 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7235 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7236 } 7237 } 7238 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7239 mutex_unlock(&adev->grbm_idx_mutex); 7240 7241 cu_info->number = active_cu_number; 7242 cu_info->ao_cu_mask = ao_cu_mask; 7243 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7244 7245 return 0; 7246 } 7247 7248 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7249 { 7250 .type = AMD_IP_BLOCK_TYPE_GFX, 7251 .major = 9, 7252 .minor = 0, 7253 .rev = 0, 7254 .funcs = &gfx_v9_0_ip_funcs, 7255 }; 7256