1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "vi.h" 28 #include "vid.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_vi.h" 31 32 #include "gmc/gmc_8_2_d.h" 33 #include "gmc/gmc_8_2_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 #include "gca/gfx_8_0_enum.h" 45 46 #include "uvd/uvd_5_0_d.h" 47 #include "uvd/uvd_5_0_sh_mask.h" 48 49 #include "dce/dce_10_0_d.h" 50 #include "dce/dce_10_0_sh_mask.h" 51 52 #define GFX8_NUM_GFX_RINGS 1 53 #define GFX8_NUM_COMPUTE_RINGS 8 54 55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 58 59 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 60 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 62 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) 63 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 64 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) 65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) 66 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) 67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) 68 69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); 72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); 73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); 74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); 75 76 MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/stoney_me.bin"); 79 MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/tonga_me.bin"); 85 MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/topaz_me.bin"); 92 MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/fiji_me.bin"); 99 MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); 102 103 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 104 { 105 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 106 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 107 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 108 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 109 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 110 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 111 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 112 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 113 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 114 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 115 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 116 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 117 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 118 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 119 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 120 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 121 }; 122 123 static const u32 golden_settings_tonga_a11[] = 124 { 125 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, 126 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 127 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 128 mmGB_GPU_ID, 0x0000000f, 0x00000000, 129 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 130 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 131 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 132 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 133 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 134 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 135 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 136 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, 137 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 138 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 139 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 140 }; 141 142 static const u32 tonga_golden_common_all[] = 143 { 144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 145 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 146 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 147 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 148 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 149 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 150 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 151 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 152 }; 153 154 static const u32 tonga_mgcg_cgcg_init[] = 155 { 156 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 157 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 158 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 159 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 160 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 161 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 162 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 163 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 164 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 165 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 166 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 167 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 168 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 169 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 170 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 171 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 172 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 173 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 174 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 175 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 176 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 177 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 178 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 179 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 180 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 181 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 182 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 183 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 184 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 185 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 186 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 187 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 188 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 189 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 190 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 191 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 192 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 193 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 194 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 195 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 196 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 197 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 198 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 199 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 200 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 201 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 202 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 203 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 204 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 205 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 206 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 207 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 208 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 209 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 210 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 211 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 212 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 213 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 214 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 215 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 216 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 217 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 218 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 219 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 220 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 221 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 222 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 223 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 224 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 225 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 226 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 227 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 228 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 229 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 230 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 231 }; 232 233 static const u32 fiji_golden_common_all[] = 234 { 235 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 236 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, 237 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, 238 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 239 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 240 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 241 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 242 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, 243 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 244 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, 245 }; 246 247 static const u32 golden_settings_fiji_a10[] = 248 { 249 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 250 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 251 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 252 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 253 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 254 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 255 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 256 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 257 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 258 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, 259 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 260 }; 261 262 static const u32 fiji_mgcg_cgcg_init[] = 263 { 264 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 265 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 266 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 267 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 268 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 269 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 270 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 271 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 272 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 273 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 274 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 275 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 276 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 277 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 278 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 279 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 280 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 281 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 282 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 283 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 284 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 285 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 286 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 287 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 288 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 289 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 290 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 291 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 292 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 293 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 294 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 295 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 296 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 297 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 298 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 299 }; 300 301 static const u32 golden_settings_iceland_a11[] = 302 { 303 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 304 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 305 mmDB_DEBUG3, 0xc0000000, 0xc0000000, 306 mmGB_GPU_ID, 0x0000000f, 0x00000000, 307 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 308 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 309 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, 310 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 311 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 312 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 313 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 314 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 315 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 316 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 317 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, 318 }; 319 320 static const u32 iceland_golden_common_all[] = 321 { 322 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 323 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 324 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 325 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 326 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 327 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 328 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 329 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 330 }; 331 332 static const u32 iceland_mgcg_cgcg_init[] = 333 { 334 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 336 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 337 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 338 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, 339 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, 340 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, 341 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 342 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 343 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 344 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 345 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 346 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 347 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 348 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 349 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 350 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 351 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 352 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 353 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 354 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 355 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 356 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, 357 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 358 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 359 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 360 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 361 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 362 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 363 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 364 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 365 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 366 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 367 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 368 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 369 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 370 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 371 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 372 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 373 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 374 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 375 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 376 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 377 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 378 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 379 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 380 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 381 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 382 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 383 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 384 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 385 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 386 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 387 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 388 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 389 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 390 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 391 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 392 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 393 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 394 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 395 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 396 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 397 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 398 }; 399 400 static const u32 cz_golden_settings_a11[] = 401 { 402 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 403 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 404 mmGB_GPU_ID, 0x0000000f, 0x00000000, 405 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, 406 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 407 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 408 mmTA_CNTL_AUX, 0x000f000f, 0x00010000, 409 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 410 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, 411 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 412 }; 413 414 static const u32 cz_golden_common_all[] = 415 { 416 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 417 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 418 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 419 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 420 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 421 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 422 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 423 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 424 }; 425 426 static const u32 cz_mgcg_cgcg_init[] = 427 { 428 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 429 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 430 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 431 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 432 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 433 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 434 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, 435 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 436 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 437 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 438 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 439 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 440 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 441 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 442 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 443 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 444 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 445 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 446 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 447 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 448 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 449 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 450 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 451 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 452 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 453 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 454 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 455 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 456 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 457 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 458 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 459 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 460 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 461 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 462 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 463 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 464 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 465 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 466 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 467 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 468 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 469 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 470 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 471 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 472 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 473 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 474 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 475 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 476 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 477 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 478 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 479 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 480 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 481 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 482 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 483 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 484 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 485 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 486 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 487 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 488 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 489 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 490 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 491 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 492 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 493 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 494 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 495 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 496 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 497 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 498 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 499 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 500 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 501 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 502 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 503 }; 504 505 static const u32 stoney_golden_settings_a11[] = 506 { 507 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 508 mmGB_GPU_ID, 0x0000000f, 0x00000000, 509 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 510 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 511 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 512 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 513 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 514 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 515 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, 516 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, 517 }; 518 519 static const u32 stoney_golden_common_all[] = 520 { 521 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 522 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, 523 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 524 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, 525 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 526 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 527 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 528 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, 529 }; 530 531 static const u32 stoney_mgcg_cgcg_init[] = 532 { 533 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 534 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 535 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 536 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 537 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 538 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 539 }; 540 541 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); 542 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); 543 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); 544 545 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) 546 { 547 switch (adev->asic_type) { 548 case CHIP_TOPAZ: 549 amdgpu_program_register_sequence(adev, 550 iceland_mgcg_cgcg_init, 551 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 552 amdgpu_program_register_sequence(adev, 553 golden_settings_iceland_a11, 554 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 555 amdgpu_program_register_sequence(adev, 556 iceland_golden_common_all, 557 (const u32)ARRAY_SIZE(iceland_golden_common_all)); 558 break; 559 case CHIP_FIJI: 560 amdgpu_program_register_sequence(adev, 561 fiji_mgcg_cgcg_init, 562 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 563 amdgpu_program_register_sequence(adev, 564 golden_settings_fiji_a10, 565 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 566 amdgpu_program_register_sequence(adev, 567 fiji_golden_common_all, 568 (const u32)ARRAY_SIZE(fiji_golden_common_all)); 569 break; 570 571 case CHIP_TONGA: 572 amdgpu_program_register_sequence(adev, 573 tonga_mgcg_cgcg_init, 574 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 575 amdgpu_program_register_sequence(adev, 576 golden_settings_tonga_a11, 577 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 578 amdgpu_program_register_sequence(adev, 579 tonga_golden_common_all, 580 (const u32)ARRAY_SIZE(tonga_golden_common_all)); 581 break; 582 case CHIP_CARRIZO: 583 amdgpu_program_register_sequence(adev, 584 cz_mgcg_cgcg_init, 585 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 586 amdgpu_program_register_sequence(adev, 587 cz_golden_settings_a11, 588 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 589 amdgpu_program_register_sequence(adev, 590 cz_golden_common_all, 591 (const u32)ARRAY_SIZE(cz_golden_common_all)); 592 break; 593 case CHIP_STONEY: 594 amdgpu_program_register_sequence(adev, 595 stoney_mgcg_cgcg_init, 596 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 597 amdgpu_program_register_sequence(adev, 598 stoney_golden_settings_a11, 599 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 600 amdgpu_program_register_sequence(adev, 601 stoney_golden_common_all, 602 (const u32)ARRAY_SIZE(stoney_golden_common_all)); 603 break; 604 default: 605 break; 606 } 607 } 608 609 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) 610 { 611 int i; 612 613 adev->gfx.scratch.num_reg = 7; 614 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 615 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 616 adev->gfx.scratch.free[i] = true; 617 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 618 } 619 } 620 621 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) 622 { 623 struct amdgpu_device *adev = ring->adev; 624 uint32_t scratch; 625 uint32_t tmp = 0; 626 unsigned i; 627 int r; 628 629 r = amdgpu_gfx_scratch_get(adev, &scratch); 630 if (r) { 631 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 632 return r; 633 } 634 WREG32(scratch, 0xCAFEDEAD); 635 r = amdgpu_ring_lock(ring, 3); 636 if (r) { 637 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 638 ring->idx, r); 639 amdgpu_gfx_scratch_free(adev, scratch); 640 return r; 641 } 642 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 643 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 644 amdgpu_ring_write(ring, 0xDEADBEEF); 645 amdgpu_ring_unlock_commit(ring); 646 647 for (i = 0; i < adev->usec_timeout; i++) { 648 tmp = RREG32(scratch); 649 if (tmp == 0xDEADBEEF) 650 break; 651 DRM_UDELAY(1); 652 } 653 if (i < adev->usec_timeout) { 654 DRM_INFO("ring test on %d succeeded in %d usecs\n", 655 ring->idx, i); 656 } else { 657 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 658 ring->idx, scratch, tmp); 659 r = -EINVAL; 660 } 661 amdgpu_gfx_scratch_free(adev, scratch); 662 return r; 663 } 664 665 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) 666 { 667 struct amdgpu_device *adev = ring->adev; 668 struct amdgpu_ib ib; 669 struct fence *f = NULL; 670 uint32_t scratch; 671 uint32_t tmp = 0; 672 unsigned i; 673 int r; 674 675 r = amdgpu_gfx_scratch_get(adev, &scratch); 676 if (r) { 677 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); 678 return r; 679 } 680 WREG32(scratch, 0xCAFEDEAD); 681 memset(&ib, 0, sizeof(ib)); 682 r = amdgpu_ib_get(ring, NULL, 256, &ib); 683 if (r) { 684 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 685 goto err1; 686 } 687 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 688 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 689 ib.ptr[2] = 0xDEADBEEF; 690 ib.length_dw = 3; 691 692 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, 693 AMDGPU_FENCE_OWNER_UNDEFINED, 694 &f); 695 if (r) 696 goto err2; 697 698 r = fence_wait(f, false); 699 if (r) { 700 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 701 goto err2; 702 } 703 for (i = 0; i < adev->usec_timeout; i++) { 704 tmp = RREG32(scratch); 705 if (tmp == 0xDEADBEEF) 706 break; 707 DRM_UDELAY(1); 708 } 709 if (i < adev->usec_timeout) { 710 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 711 ring->idx, i); 712 goto err2; 713 } else { 714 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 715 scratch, tmp); 716 r = -EINVAL; 717 } 718 err2: 719 fence_put(f); 720 amdgpu_ib_free(adev, &ib); 721 err1: 722 amdgpu_gfx_scratch_free(adev, scratch); 723 return r; 724 } 725 726 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 727 { 728 const char *chip_name; 729 char fw_name[30]; 730 int err; 731 struct amdgpu_firmware_info *info = NULL; 732 const struct common_firmware_header *header = NULL; 733 const struct gfx_firmware_header_v1_0 *cp_hdr; 734 735 DRM_DEBUG("\n"); 736 737 switch (adev->asic_type) { 738 case CHIP_TOPAZ: 739 chip_name = "topaz"; 740 break; 741 case CHIP_TONGA: 742 chip_name = "tonga"; 743 break; 744 case CHIP_CARRIZO: 745 chip_name = "carrizo"; 746 break; 747 case CHIP_FIJI: 748 chip_name = "fiji"; 749 break; 750 case CHIP_STONEY: 751 chip_name = "stoney"; 752 break; 753 default: 754 BUG(); 755 } 756 757 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 758 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 759 if (err) 760 goto out; 761 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 762 if (err) 763 goto out; 764 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 765 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 766 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 767 768 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 769 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 770 if (err) 771 goto out; 772 err = amdgpu_ucode_validate(adev->gfx.me_fw); 773 if (err) 774 goto out; 775 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 776 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 777 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 778 779 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 780 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 781 if (err) 782 goto out; 783 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 784 if (err) 785 goto out; 786 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 787 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 788 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 789 790 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 791 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 792 if (err) 793 goto out; 794 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 795 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 796 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 797 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 798 799 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 800 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 801 if (err) 802 goto out; 803 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 804 if (err) 805 goto out; 806 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 807 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 808 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 809 810 if (adev->asic_type != CHIP_STONEY) { 811 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 812 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 813 if (!err) { 814 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 815 if (err) 816 goto out; 817 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 818 adev->gfx.mec2_fw->data; 819 adev->gfx.mec2_fw_version = 820 le32_to_cpu(cp_hdr->header.ucode_version); 821 adev->gfx.mec2_feature_version = 822 le32_to_cpu(cp_hdr->ucode_feature_version); 823 } else { 824 err = 0; 825 adev->gfx.mec2_fw = NULL; 826 } 827 } 828 829 if (adev->firmware.smu_load) { 830 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 831 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 832 info->fw = adev->gfx.pfp_fw; 833 header = (const struct common_firmware_header *)info->fw->data; 834 adev->firmware.fw_size += 835 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 836 837 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 838 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 839 info->fw = adev->gfx.me_fw; 840 header = (const struct common_firmware_header *)info->fw->data; 841 adev->firmware.fw_size += 842 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 843 844 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 845 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 846 info->fw = adev->gfx.ce_fw; 847 header = (const struct common_firmware_header *)info->fw->data; 848 adev->firmware.fw_size += 849 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 850 851 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 852 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 853 info->fw = adev->gfx.rlc_fw; 854 header = (const struct common_firmware_header *)info->fw->data; 855 adev->firmware.fw_size += 856 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 857 858 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 859 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 860 info->fw = adev->gfx.mec_fw; 861 header = (const struct common_firmware_header *)info->fw->data; 862 adev->firmware.fw_size += 863 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 864 865 if (adev->gfx.mec2_fw) { 866 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 867 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 868 info->fw = adev->gfx.mec2_fw; 869 header = (const struct common_firmware_header *)info->fw->data; 870 adev->firmware.fw_size += 871 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 872 } 873 874 } 875 876 out: 877 if (err) { 878 dev_err(adev->dev, 879 "gfx8: Failed to load firmware \"%s\"\n", 880 fw_name); 881 release_firmware(adev->gfx.pfp_fw); 882 adev->gfx.pfp_fw = NULL; 883 release_firmware(adev->gfx.me_fw); 884 adev->gfx.me_fw = NULL; 885 release_firmware(adev->gfx.ce_fw); 886 adev->gfx.ce_fw = NULL; 887 release_firmware(adev->gfx.rlc_fw); 888 adev->gfx.rlc_fw = NULL; 889 release_firmware(adev->gfx.mec_fw); 890 adev->gfx.mec_fw = NULL; 891 release_firmware(adev->gfx.mec2_fw); 892 adev->gfx.mec2_fw = NULL; 893 } 894 return err; 895 } 896 897 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) 898 { 899 int r; 900 901 if (adev->gfx.mec.hpd_eop_obj) { 902 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 903 if (unlikely(r != 0)) 904 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 905 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 906 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 907 908 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 909 adev->gfx.mec.hpd_eop_obj = NULL; 910 } 911 } 912 913 #define MEC_HPD_SIZE 2048 914 915 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 916 { 917 int r; 918 u32 *hpd; 919 920 /* 921 * we assign only 1 pipe because all other pipes will 922 * be handled by KFD 923 */ 924 adev->gfx.mec.num_mec = 1; 925 adev->gfx.mec.num_pipe = 1; 926 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 927 928 if (adev->gfx.mec.hpd_eop_obj == NULL) { 929 r = amdgpu_bo_create(adev, 930 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 931 PAGE_SIZE, true, 932 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 933 &adev->gfx.mec.hpd_eop_obj); 934 if (r) { 935 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 936 return r; 937 } 938 } 939 940 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 941 if (unlikely(r != 0)) { 942 gfx_v8_0_mec_fini(adev); 943 return r; 944 } 945 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 946 &adev->gfx.mec.hpd_eop_gpu_addr); 947 if (r) { 948 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 949 gfx_v8_0_mec_fini(adev); 950 return r; 951 } 952 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 953 if (r) { 954 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 955 gfx_v8_0_mec_fini(adev); 956 return r; 957 } 958 959 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 960 961 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 962 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 963 964 return 0; 965 } 966 967 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) 968 { 969 u32 gb_addr_config; 970 u32 mc_shared_chmap, mc_arb_ramcfg; 971 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 972 u32 tmp; 973 974 switch (adev->asic_type) { 975 case CHIP_TOPAZ: 976 adev->gfx.config.max_shader_engines = 1; 977 adev->gfx.config.max_tile_pipes = 2; 978 adev->gfx.config.max_cu_per_sh = 6; 979 adev->gfx.config.max_sh_per_se = 1; 980 adev->gfx.config.max_backends_per_se = 2; 981 adev->gfx.config.max_texture_channel_caches = 2; 982 adev->gfx.config.max_gprs = 256; 983 adev->gfx.config.max_gs_threads = 32; 984 adev->gfx.config.max_hw_contexts = 8; 985 986 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 987 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 988 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 989 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 990 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; 991 break; 992 case CHIP_FIJI: 993 adev->gfx.config.max_shader_engines = 4; 994 adev->gfx.config.max_tile_pipes = 16; 995 adev->gfx.config.max_cu_per_sh = 16; 996 adev->gfx.config.max_sh_per_se = 1; 997 adev->gfx.config.max_backends_per_se = 4; 998 adev->gfx.config.max_texture_channel_caches = 16; 999 adev->gfx.config.max_gprs = 256; 1000 adev->gfx.config.max_gs_threads = 32; 1001 adev->gfx.config.max_hw_contexts = 8; 1002 1003 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1004 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1005 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1006 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1007 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1008 break; 1009 case CHIP_TONGA: 1010 adev->gfx.config.max_shader_engines = 4; 1011 adev->gfx.config.max_tile_pipes = 8; 1012 adev->gfx.config.max_cu_per_sh = 8; 1013 adev->gfx.config.max_sh_per_se = 1; 1014 adev->gfx.config.max_backends_per_se = 2; 1015 adev->gfx.config.max_texture_channel_caches = 8; 1016 adev->gfx.config.max_gprs = 256; 1017 adev->gfx.config.max_gs_threads = 32; 1018 adev->gfx.config.max_hw_contexts = 8; 1019 1020 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1021 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1022 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1023 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1024 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1025 break; 1026 case CHIP_CARRIZO: 1027 adev->gfx.config.max_shader_engines = 1; 1028 adev->gfx.config.max_tile_pipes = 2; 1029 adev->gfx.config.max_sh_per_se = 1; 1030 adev->gfx.config.max_backends_per_se = 2; 1031 1032 switch (adev->pdev->revision) { 1033 case 0xc4: 1034 case 0x84: 1035 case 0xc8: 1036 case 0xcc: 1037 case 0xe1: 1038 case 0xe3: 1039 /* B10 */ 1040 adev->gfx.config.max_cu_per_sh = 8; 1041 break; 1042 case 0xc5: 1043 case 0x81: 1044 case 0x85: 1045 case 0xc9: 1046 case 0xcd: 1047 case 0xe2: 1048 case 0xe4: 1049 /* B8 */ 1050 adev->gfx.config.max_cu_per_sh = 6; 1051 break; 1052 case 0xc6: 1053 case 0xca: 1054 case 0xce: 1055 case 0x88: 1056 /* B6 */ 1057 adev->gfx.config.max_cu_per_sh = 6; 1058 break; 1059 case 0xc7: 1060 case 0x87: 1061 case 0xcb: 1062 case 0xe5: 1063 case 0x89: 1064 default: 1065 /* B4 */ 1066 adev->gfx.config.max_cu_per_sh = 4; 1067 break; 1068 } 1069 1070 adev->gfx.config.max_texture_channel_caches = 2; 1071 adev->gfx.config.max_gprs = 256; 1072 adev->gfx.config.max_gs_threads = 32; 1073 adev->gfx.config.max_hw_contexts = 8; 1074 1075 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1076 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1077 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1078 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1079 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1080 break; 1081 case CHIP_STONEY: 1082 adev->gfx.config.max_shader_engines = 1; 1083 adev->gfx.config.max_tile_pipes = 2; 1084 adev->gfx.config.max_sh_per_se = 1; 1085 adev->gfx.config.max_backends_per_se = 1; 1086 1087 switch (adev->pdev->revision) { 1088 case 0xc0: 1089 case 0xc1: 1090 case 0xc2: 1091 case 0xc4: 1092 case 0xc8: 1093 case 0xc9: 1094 adev->gfx.config.max_cu_per_sh = 3; 1095 break; 1096 case 0xd0: 1097 case 0xd1: 1098 case 0xd2: 1099 default: 1100 adev->gfx.config.max_cu_per_sh = 2; 1101 break; 1102 } 1103 1104 adev->gfx.config.max_texture_channel_caches = 2; 1105 adev->gfx.config.max_gprs = 256; 1106 adev->gfx.config.max_gs_threads = 16; 1107 adev->gfx.config.max_hw_contexts = 8; 1108 1109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1111 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1113 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1114 break; 1115 default: 1116 adev->gfx.config.max_shader_engines = 2; 1117 adev->gfx.config.max_tile_pipes = 4; 1118 adev->gfx.config.max_cu_per_sh = 2; 1119 adev->gfx.config.max_sh_per_se = 1; 1120 adev->gfx.config.max_backends_per_se = 2; 1121 adev->gfx.config.max_texture_channel_caches = 4; 1122 adev->gfx.config.max_gprs = 256; 1123 adev->gfx.config.max_gs_threads = 32; 1124 adev->gfx.config.max_hw_contexts = 8; 1125 1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1130 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1131 break; 1132 } 1133 1134 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1135 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1136 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1137 1138 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1139 adev->gfx.config.mem_max_burst_length_bytes = 256; 1140 if (adev->flags & AMD_IS_APU) { 1141 /* Get memory bank mapping mode. */ 1142 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 1143 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1144 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1145 1146 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 1147 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1148 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1149 1150 /* Validate settings in case only one DIMM installed. */ 1151 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 1152 dimm00_addr_map = 0; 1153 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 1154 dimm01_addr_map = 0; 1155 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 1156 dimm10_addr_map = 0; 1157 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 1158 dimm11_addr_map = 0; 1159 1160 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 1161 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 1162 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 1163 adev->gfx.config.mem_row_size_in_kb = 2; 1164 else 1165 adev->gfx.config.mem_row_size_in_kb = 1; 1166 } else { 1167 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); 1168 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1169 if (adev->gfx.config.mem_row_size_in_kb > 4) 1170 adev->gfx.config.mem_row_size_in_kb = 4; 1171 } 1172 1173 adev->gfx.config.shader_engine_tile_size = 32; 1174 adev->gfx.config.num_gpus = 1; 1175 adev->gfx.config.multi_gpu_tile_size = 64; 1176 1177 /* fix up row size */ 1178 switch (adev->gfx.config.mem_row_size_in_kb) { 1179 case 1: 1180 default: 1181 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); 1182 break; 1183 case 2: 1184 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); 1185 break; 1186 case 4: 1187 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); 1188 break; 1189 } 1190 adev->gfx.config.gb_addr_config = gb_addr_config; 1191 } 1192 1193 static int gfx_v8_0_sw_init(void *handle) 1194 { 1195 int i, r; 1196 struct amdgpu_ring *ring; 1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1198 1199 /* EOP Event */ 1200 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 1201 if (r) 1202 return r; 1203 1204 /* Privileged reg */ 1205 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 1206 if (r) 1207 return r; 1208 1209 /* Privileged inst */ 1210 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 1211 if (r) 1212 return r; 1213 1214 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1215 1216 gfx_v8_0_scratch_init(adev); 1217 1218 r = gfx_v8_0_init_microcode(adev); 1219 if (r) { 1220 DRM_ERROR("Failed to load gfx firmware!\n"); 1221 return r; 1222 } 1223 1224 r = gfx_v8_0_mec_init(adev); 1225 if (r) { 1226 DRM_ERROR("Failed to init MEC BOs!\n"); 1227 return r; 1228 } 1229 1230 /* set up the gfx ring */ 1231 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1232 ring = &adev->gfx.gfx_ring[i]; 1233 ring->ring_obj = NULL; 1234 sprintf(ring->name, "gfx"); 1235 /* no gfx doorbells on iceland */ 1236 if (adev->asic_type != CHIP_TOPAZ) { 1237 ring->use_doorbell = true; 1238 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; 1239 } 1240 1241 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 1242 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 1243 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, 1244 AMDGPU_RING_TYPE_GFX); 1245 if (r) 1246 return r; 1247 } 1248 1249 /* set up the compute queues */ 1250 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1251 unsigned irq_type; 1252 1253 /* max 32 queues per MEC */ 1254 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 1255 DRM_ERROR("Too many (%d) compute rings!\n", i); 1256 break; 1257 } 1258 ring = &adev->gfx.compute_ring[i]; 1259 ring->ring_obj = NULL; 1260 ring->use_doorbell = true; 1261 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; 1262 ring->me = 1; /* first MEC */ 1263 ring->pipe = i / 8; 1264 ring->queue = i % 8; 1265 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 1266 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 1267 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1268 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 1269 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 1270 &adev->gfx.eop_irq, irq_type, 1271 AMDGPU_RING_TYPE_COMPUTE); 1272 if (r) 1273 return r; 1274 } 1275 1276 /* reserve GDS, GWS and OA resource for gfx */ 1277 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, 1278 PAGE_SIZE, true, 1279 AMDGPU_GEM_DOMAIN_GDS, 0, NULL, 1280 NULL, &adev->gds.gds_gfx_bo); 1281 if (r) 1282 return r; 1283 1284 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, 1285 PAGE_SIZE, true, 1286 AMDGPU_GEM_DOMAIN_GWS, 0, NULL, 1287 NULL, &adev->gds.gws_gfx_bo); 1288 if (r) 1289 return r; 1290 1291 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, 1292 PAGE_SIZE, true, 1293 AMDGPU_GEM_DOMAIN_OA, 0, NULL, 1294 NULL, &adev->gds.oa_gfx_bo); 1295 if (r) 1296 return r; 1297 1298 adev->gfx.ce_ram_size = 0x8000; 1299 1300 gfx_v8_0_gpu_early_init(adev); 1301 1302 return 0; 1303 } 1304 1305 static int gfx_v8_0_sw_fini(void *handle) 1306 { 1307 int i; 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309 1310 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 1311 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 1312 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); 1313 1314 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1315 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1316 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1317 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1318 1319 gfx_v8_0_mec_fini(adev); 1320 1321 return 0; 1322 } 1323 1324 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) 1325 { 1326 const u32 num_tile_mode_states = 32; 1327 const u32 num_secondary_tile_mode_states = 16; 1328 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 1329 1330 switch (adev->gfx.config.mem_row_size_in_kb) { 1331 case 1: 1332 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1333 break; 1334 case 2: 1335 default: 1336 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1337 break; 1338 case 4: 1339 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1340 break; 1341 } 1342 1343 switch (adev->asic_type) { 1344 case CHIP_TOPAZ: 1345 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1346 switch (reg_offset) { 1347 case 0: 1348 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1349 PIPE_CONFIG(ADDR_SURF_P2) | 1350 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1351 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1352 break; 1353 case 1: 1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1355 PIPE_CONFIG(ADDR_SURF_P2) | 1356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1357 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1358 break; 1359 case 2: 1360 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1361 PIPE_CONFIG(ADDR_SURF_P2) | 1362 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1363 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1364 break; 1365 case 3: 1366 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1367 PIPE_CONFIG(ADDR_SURF_P2) | 1368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1369 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1370 break; 1371 case 4: 1372 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1373 PIPE_CONFIG(ADDR_SURF_P2) | 1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1375 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1376 break; 1377 case 5: 1378 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1379 PIPE_CONFIG(ADDR_SURF_P2) | 1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1382 break; 1383 case 6: 1384 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1385 PIPE_CONFIG(ADDR_SURF_P2) | 1386 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1387 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1388 break; 1389 case 8: 1390 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1391 PIPE_CONFIG(ADDR_SURF_P2)); 1392 break; 1393 case 9: 1394 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1395 PIPE_CONFIG(ADDR_SURF_P2) | 1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1397 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1398 break; 1399 case 10: 1400 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1401 PIPE_CONFIG(ADDR_SURF_P2) | 1402 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1404 break; 1405 case 11: 1406 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1407 PIPE_CONFIG(ADDR_SURF_P2) | 1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1409 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1410 break; 1411 case 13: 1412 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1413 PIPE_CONFIG(ADDR_SURF_P2) | 1414 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1416 break; 1417 case 14: 1418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1419 PIPE_CONFIG(ADDR_SURF_P2) | 1420 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1421 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1422 break; 1423 case 15: 1424 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1425 PIPE_CONFIG(ADDR_SURF_P2) | 1426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1428 break; 1429 case 16: 1430 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1431 PIPE_CONFIG(ADDR_SURF_P2) | 1432 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1433 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1434 break; 1435 case 18: 1436 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1440 break; 1441 case 19: 1442 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1443 PIPE_CONFIG(ADDR_SURF_P2) | 1444 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1446 break; 1447 case 20: 1448 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1449 PIPE_CONFIG(ADDR_SURF_P2) | 1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1452 break; 1453 case 21: 1454 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1455 PIPE_CONFIG(ADDR_SURF_P2) | 1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1458 break; 1459 case 22: 1460 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1461 PIPE_CONFIG(ADDR_SURF_P2) | 1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1464 break; 1465 case 24: 1466 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1467 PIPE_CONFIG(ADDR_SURF_P2) | 1468 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1469 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1470 break; 1471 case 25: 1472 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1473 PIPE_CONFIG(ADDR_SURF_P2) | 1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1476 break; 1477 case 26: 1478 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1479 PIPE_CONFIG(ADDR_SURF_P2) | 1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1482 break; 1483 case 27: 1484 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1485 PIPE_CONFIG(ADDR_SURF_P2) | 1486 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1488 break; 1489 case 28: 1490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1491 PIPE_CONFIG(ADDR_SURF_P2) | 1492 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1493 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1494 break; 1495 case 29: 1496 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1497 PIPE_CONFIG(ADDR_SURF_P2) | 1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1499 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1500 break; 1501 case 7: 1502 case 12: 1503 case 17: 1504 case 23: 1505 /* unused idx */ 1506 continue; 1507 default: 1508 gb_tile_moden = 0; 1509 break; 1510 }; 1511 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1512 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1513 } 1514 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1515 switch (reg_offset) { 1516 case 0: 1517 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1520 NUM_BANKS(ADDR_SURF_8_BANK)); 1521 break; 1522 case 1: 1523 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1526 NUM_BANKS(ADDR_SURF_8_BANK)); 1527 break; 1528 case 2: 1529 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1532 NUM_BANKS(ADDR_SURF_8_BANK)); 1533 break; 1534 case 3: 1535 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1538 NUM_BANKS(ADDR_SURF_8_BANK)); 1539 break; 1540 case 4: 1541 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1544 NUM_BANKS(ADDR_SURF_8_BANK)); 1545 break; 1546 case 5: 1547 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1550 NUM_BANKS(ADDR_SURF_8_BANK)); 1551 break; 1552 case 6: 1553 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1556 NUM_BANKS(ADDR_SURF_8_BANK)); 1557 break; 1558 case 8: 1559 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1562 NUM_BANKS(ADDR_SURF_16_BANK)); 1563 break; 1564 case 9: 1565 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1568 NUM_BANKS(ADDR_SURF_16_BANK)); 1569 break; 1570 case 10: 1571 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1572 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1573 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1574 NUM_BANKS(ADDR_SURF_16_BANK)); 1575 break; 1576 case 11: 1577 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1580 NUM_BANKS(ADDR_SURF_16_BANK)); 1581 break; 1582 case 12: 1583 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1586 NUM_BANKS(ADDR_SURF_16_BANK)); 1587 break; 1588 case 13: 1589 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1592 NUM_BANKS(ADDR_SURF_16_BANK)); 1593 break; 1594 case 14: 1595 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1598 NUM_BANKS(ADDR_SURF_8_BANK)); 1599 break; 1600 case 7: 1601 /* unused idx */ 1602 continue; 1603 default: 1604 gb_tile_moden = 0; 1605 break; 1606 }; 1607 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1608 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1609 } 1610 case CHIP_FIJI: 1611 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1612 switch (reg_offset) { 1613 case 0: 1614 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1615 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1617 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1618 break; 1619 case 1: 1620 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1621 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1622 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1623 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1624 break; 1625 case 2: 1626 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1627 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1628 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1629 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1630 break; 1631 case 3: 1632 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1633 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1634 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1635 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1636 break; 1637 case 4: 1638 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1639 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1640 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1641 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1642 break; 1643 case 5: 1644 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1645 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1646 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1647 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1648 break; 1649 case 6: 1650 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1651 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1653 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1654 break; 1655 case 7: 1656 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1657 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1659 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1660 break; 1661 case 8: 1662 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1663 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1664 break; 1665 case 9: 1666 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1667 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1668 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1669 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1670 break; 1671 case 10: 1672 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1673 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1674 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1675 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1676 break; 1677 case 11: 1678 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1679 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1680 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1681 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1682 break; 1683 case 12: 1684 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1685 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1686 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1687 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1688 break; 1689 case 13: 1690 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1691 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1692 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1693 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1694 break; 1695 case 14: 1696 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1697 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1698 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1699 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1700 break; 1701 case 15: 1702 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1703 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1704 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1705 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1706 break; 1707 case 16: 1708 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1709 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1710 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1711 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1712 break; 1713 case 17: 1714 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1715 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1716 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1717 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1718 break; 1719 case 18: 1720 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1721 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1722 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1723 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1724 break; 1725 case 19: 1726 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1727 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1728 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1729 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1730 break; 1731 case 20: 1732 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1733 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1734 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1735 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1736 break; 1737 case 21: 1738 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1739 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1740 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1741 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1742 break; 1743 case 22: 1744 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1745 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1746 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1747 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1748 break; 1749 case 23: 1750 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1751 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1752 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1753 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1754 break; 1755 case 24: 1756 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1757 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1758 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1759 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1760 break; 1761 case 25: 1762 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1763 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1764 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1765 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1766 break; 1767 case 26: 1768 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1769 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1770 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1771 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1772 break; 1773 case 27: 1774 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1775 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1776 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1777 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1778 break; 1779 case 28: 1780 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1781 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1782 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1783 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1784 break; 1785 case 29: 1786 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1787 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1788 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1789 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1790 break; 1791 case 30: 1792 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1793 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1794 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1795 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1796 break; 1797 default: 1798 gb_tile_moden = 0; 1799 break; 1800 } 1801 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1802 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1803 } 1804 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1805 switch (reg_offset) { 1806 case 0: 1807 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1808 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1809 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1810 NUM_BANKS(ADDR_SURF_8_BANK)); 1811 break; 1812 case 1: 1813 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1816 NUM_BANKS(ADDR_SURF_8_BANK)); 1817 break; 1818 case 2: 1819 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1820 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1821 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1822 NUM_BANKS(ADDR_SURF_8_BANK)); 1823 break; 1824 case 3: 1825 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1828 NUM_BANKS(ADDR_SURF_8_BANK)); 1829 break; 1830 case 4: 1831 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1834 NUM_BANKS(ADDR_SURF_8_BANK)); 1835 break; 1836 case 5: 1837 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1838 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1839 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1840 NUM_BANKS(ADDR_SURF_8_BANK)); 1841 break; 1842 case 6: 1843 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1846 NUM_BANKS(ADDR_SURF_8_BANK)); 1847 break; 1848 case 8: 1849 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1850 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1851 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1852 NUM_BANKS(ADDR_SURF_8_BANK)); 1853 break; 1854 case 9: 1855 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1858 NUM_BANKS(ADDR_SURF_8_BANK)); 1859 break; 1860 case 10: 1861 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1864 NUM_BANKS(ADDR_SURF_8_BANK)); 1865 break; 1866 case 11: 1867 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1870 NUM_BANKS(ADDR_SURF_8_BANK)); 1871 break; 1872 case 12: 1873 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1876 NUM_BANKS(ADDR_SURF_8_BANK)); 1877 break; 1878 case 13: 1879 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1880 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1881 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1882 NUM_BANKS(ADDR_SURF_8_BANK)); 1883 break; 1884 case 14: 1885 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1888 NUM_BANKS(ADDR_SURF_4_BANK)); 1889 break; 1890 case 7: 1891 /* unused idx */ 1892 continue; 1893 default: 1894 gb_tile_moden = 0; 1895 break; 1896 } 1897 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1898 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1899 } 1900 break; 1901 case CHIP_TONGA: 1902 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1903 switch (reg_offset) { 1904 case 0: 1905 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1906 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1908 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1909 break; 1910 case 1: 1911 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1914 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1915 break; 1916 case 2: 1917 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1918 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1919 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1920 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1921 break; 1922 case 3: 1923 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1924 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1925 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1926 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1927 break; 1928 case 4: 1929 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1930 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1931 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1932 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1933 break; 1934 case 5: 1935 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1936 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1938 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1939 break; 1940 case 6: 1941 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1942 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1943 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1944 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1945 break; 1946 case 7: 1947 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1948 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1949 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1950 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1951 break; 1952 case 8: 1953 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1954 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 1955 break; 1956 case 9: 1957 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1959 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1961 break; 1962 case 10: 1963 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1964 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1965 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1966 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1967 break; 1968 case 11: 1969 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1971 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1973 break; 1974 case 12: 1975 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1976 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1977 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1978 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1979 break; 1980 case 13: 1981 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1983 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1985 break; 1986 case 14: 1987 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1988 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1989 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1990 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1991 break; 1992 case 15: 1993 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1994 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1995 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1997 break; 1998 case 16: 1999 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2000 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2001 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2002 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2003 break; 2004 case 17: 2005 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2006 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2007 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2009 break; 2010 case 18: 2011 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2012 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2013 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2014 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2015 break; 2016 case 19: 2017 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2018 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2019 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2020 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2021 break; 2022 case 20: 2023 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2024 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2025 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2026 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2027 break; 2028 case 21: 2029 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2030 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2031 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2032 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2033 break; 2034 case 22: 2035 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2036 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2037 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2038 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2039 break; 2040 case 23: 2041 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2042 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2043 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2044 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2045 break; 2046 case 24: 2047 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2048 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2049 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2050 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2051 break; 2052 case 25: 2053 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2054 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2055 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2056 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2057 break; 2058 case 26: 2059 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2060 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2061 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2062 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2063 break; 2064 case 27: 2065 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2066 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2067 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2068 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2069 break; 2070 case 28: 2071 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2072 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2073 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2074 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2075 break; 2076 case 29: 2077 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2078 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2079 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2081 break; 2082 case 30: 2083 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2085 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2086 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2087 break; 2088 default: 2089 gb_tile_moden = 0; 2090 break; 2091 }; 2092 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 2093 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 2094 } 2095 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 2096 switch (reg_offset) { 2097 case 0: 2098 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2101 NUM_BANKS(ADDR_SURF_16_BANK)); 2102 break; 2103 case 1: 2104 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2105 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2106 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2107 NUM_BANKS(ADDR_SURF_16_BANK)); 2108 break; 2109 case 2: 2110 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2113 NUM_BANKS(ADDR_SURF_16_BANK)); 2114 break; 2115 case 3: 2116 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2119 NUM_BANKS(ADDR_SURF_16_BANK)); 2120 break; 2121 case 4: 2122 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2123 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2124 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2125 NUM_BANKS(ADDR_SURF_16_BANK)); 2126 break; 2127 case 5: 2128 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2131 NUM_BANKS(ADDR_SURF_16_BANK)); 2132 break; 2133 case 6: 2134 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2137 NUM_BANKS(ADDR_SURF_16_BANK)); 2138 break; 2139 case 8: 2140 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2143 NUM_BANKS(ADDR_SURF_16_BANK)); 2144 break; 2145 case 9: 2146 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2149 NUM_BANKS(ADDR_SURF_16_BANK)); 2150 break; 2151 case 10: 2152 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2155 NUM_BANKS(ADDR_SURF_16_BANK)); 2156 break; 2157 case 11: 2158 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2161 NUM_BANKS(ADDR_SURF_16_BANK)); 2162 break; 2163 case 12: 2164 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2167 NUM_BANKS(ADDR_SURF_8_BANK)); 2168 break; 2169 case 13: 2170 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2173 NUM_BANKS(ADDR_SURF_4_BANK)); 2174 break; 2175 case 14: 2176 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2179 NUM_BANKS(ADDR_SURF_4_BANK)); 2180 break; 2181 case 7: 2182 /* unused idx */ 2183 continue; 2184 default: 2185 gb_tile_moden = 0; 2186 break; 2187 }; 2188 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 2189 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 2190 } 2191 break; 2192 case CHIP_STONEY: 2193 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 2194 switch (reg_offset) { 2195 case 0: 2196 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2197 PIPE_CONFIG(ADDR_SURF_P2) | 2198 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2199 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2200 break; 2201 case 1: 2202 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2203 PIPE_CONFIG(ADDR_SURF_P2) | 2204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2205 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2206 break; 2207 case 2: 2208 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2209 PIPE_CONFIG(ADDR_SURF_P2) | 2210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2212 break; 2213 case 3: 2214 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2215 PIPE_CONFIG(ADDR_SURF_P2) | 2216 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2217 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2218 break; 2219 case 4: 2220 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2221 PIPE_CONFIG(ADDR_SURF_P2) | 2222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2224 break; 2225 case 5: 2226 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2227 PIPE_CONFIG(ADDR_SURF_P2) | 2228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2229 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2230 break; 2231 case 6: 2232 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2233 PIPE_CONFIG(ADDR_SURF_P2) | 2234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2236 break; 2237 case 8: 2238 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2239 PIPE_CONFIG(ADDR_SURF_P2)); 2240 break; 2241 case 9: 2242 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2243 PIPE_CONFIG(ADDR_SURF_P2) | 2244 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2245 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2246 break; 2247 case 10: 2248 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2249 PIPE_CONFIG(ADDR_SURF_P2) | 2250 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2251 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2252 break; 2253 case 11: 2254 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2255 PIPE_CONFIG(ADDR_SURF_P2) | 2256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2257 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2258 break; 2259 case 13: 2260 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2261 PIPE_CONFIG(ADDR_SURF_P2) | 2262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2264 break; 2265 case 14: 2266 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2267 PIPE_CONFIG(ADDR_SURF_P2) | 2268 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2269 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2270 break; 2271 case 15: 2272 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2273 PIPE_CONFIG(ADDR_SURF_P2) | 2274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2276 break; 2277 case 16: 2278 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2279 PIPE_CONFIG(ADDR_SURF_P2) | 2280 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2282 break; 2283 case 18: 2284 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2285 PIPE_CONFIG(ADDR_SURF_P2) | 2286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2288 break; 2289 case 19: 2290 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2291 PIPE_CONFIG(ADDR_SURF_P2) | 2292 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2294 break; 2295 case 20: 2296 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2297 PIPE_CONFIG(ADDR_SURF_P2) | 2298 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2300 break; 2301 case 21: 2302 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2303 PIPE_CONFIG(ADDR_SURF_P2) | 2304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2306 break; 2307 case 22: 2308 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2309 PIPE_CONFIG(ADDR_SURF_P2) | 2310 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2311 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2312 break; 2313 case 24: 2314 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2315 PIPE_CONFIG(ADDR_SURF_P2) | 2316 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2318 break; 2319 case 25: 2320 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2321 PIPE_CONFIG(ADDR_SURF_P2) | 2322 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2323 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2324 break; 2325 case 26: 2326 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2327 PIPE_CONFIG(ADDR_SURF_P2) | 2328 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2330 break; 2331 case 27: 2332 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2333 PIPE_CONFIG(ADDR_SURF_P2) | 2334 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2336 break; 2337 case 28: 2338 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2339 PIPE_CONFIG(ADDR_SURF_P2) | 2340 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2341 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2342 break; 2343 case 29: 2344 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2345 PIPE_CONFIG(ADDR_SURF_P2) | 2346 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2348 break; 2349 case 7: 2350 case 12: 2351 case 17: 2352 case 23: 2353 /* unused idx */ 2354 continue; 2355 default: 2356 gb_tile_moden = 0; 2357 break; 2358 }; 2359 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 2360 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 2361 } 2362 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 2363 switch (reg_offset) { 2364 case 0: 2365 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2366 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2367 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2368 NUM_BANKS(ADDR_SURF_8_BANK)); 2369 break; 2370 case 1: 2371 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2374 NUM_BANKS(ADDR_SURF_8_BANK)); 2375 break; 2376 case 2: 2377 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2380 NUM_BANKS(ADDR_SURF_8_BANK)); 2381 break; 2382 case 3: 2383 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2386 NUM_BANKS(ADDR_SURF_8_BANK)); 2387 break; 2388 case 4: 2389 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2392 NUM_BANKS(ADDR_SURF_8_BANK)); 2393 break; 2394 case 5: 2395 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2396 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2397 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2398 NUM_BANKS(ADDR_SURF_8_BANK)); 2399 break; 2400 case 6: 2401 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2404 NUM_BANKS(ADDR_SURF_8_BANK)); 2405 break; 2406 case 8: 2407 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2410 NUM_BANKS(ADDR_SURF_16_BANK)); 2411 break; 2412 case 9: 2413 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2416 NUM_BANKS(ADDR_SURF_16_BANK)); 2417 break; 2418 case 10: 2419 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2420 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2421 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2422 NUM_BANKS(ADDR_SURF_16_BANK)); 2423 break; 2424 case 11: 2425 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2428 NUM_BANKS(ADDR_SURF_16_BANK)); 2429 break; 2430 case 12: 2431 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2434 NUM_BANKS(ADDR_SURF_16_BANK)); 2435 break; 2436 case 13: 2437 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2440 NUM_BANKS(ADDR_SURF_16_BANK)); 2441 break; 2442 case 14: 2443 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2446 NUM_BANKS(ADDR_SURF_8_BANK)); 2447 break; 2448 case 7: 2449 /* unused idx */ 2450 continue; 2451 default: 2452 gb_tile_moden = 0; 2453 break; 2454 }; 2455 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 2456 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 2457 } 2458 break; 2459 case CHIP_CARRIZO: 2460 default: 2461 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 2462 switch (reg_offset) { 2463 case 0: 2464 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2465 PIPE_CONFIG(ADDR_SURF_P2) | 2466 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2467 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2468 break; 2469 case 1: 2470 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2471 PIPE_CONFIG(ADDR_SURF_P2) | 2472 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2473 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2474 break; 2475 case 2: 2476 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2477 PIPE_CONFIG(ADDR_SURF_P2) | 2478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2479 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2480 break; 2481 case 3: 2482 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2483 PIPE_CONFIG(ADDR_SURF_P2) | 2484 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2485 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2486 break; 2487 case 4: 2488 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2489 PIPE_CONFIG(ADDR_SURF_P2) | 2490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2491 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2492 break; 2493 case 5: 2494 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2495 PIPE_CONFIG(ADDR_SURF_P2) | 2496 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2497 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2498 break; 2499 case 6: 2500 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2501 PIPE_CONFIG(ADDR_SURF_P2) | 2502 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2503 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2504 break; 2505 case 8: 2506 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2507 PIPE_CONFIG(ADDR_SURF_P2)); 2508 break; 2509 case 9: 2510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2511 PIPE_CONFIG(ADDR_SURF_P2) | 2512 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2513 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2514 break; 2515 case 10: 2516 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2517 PIPE_CONFIG(ADDR_SURF_P2) | 2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2519 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2520 break; 2521 case 11: 2522 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2523 PIPE_CONFIG(ADDR_SURF_P2) | 2524 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2525 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2526 break; 2527 case 13: 2528 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2529 PIPE_CONFIG(ADDR_SURF_P2) | 2530 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2531 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2532 break; 2533 case 14: 2534 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2535 PIPE_CONFIG(ADDR_SURF_P2) | 2536 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2537 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2538 break; 2539 case 15: 2540 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2541 PIPE_CONFIG(ADDR_SURF_P2) | 2542 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2543 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2544 break; 2545 case 16: 2546 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2547 PIPE_CONFIG(ADDR_SURF_P2) | 2548 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2549 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2550 break; 2551 case 18: 2552 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2553 PIPE_CONFIG(ADDR_SURF_P2) | 2554 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2555 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2556 break; 2557 case 19: 2558 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2559 PIPE_CONFIG(ADDR_SURF_P2) | 2560 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2561 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2562 break; 2563 case 20: 2564 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2565 PIPE_CONFIG(ADDR_SURF_P2) | 2566 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2567 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2568 break; 2569 case 21: 2570 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2571 PIPE_CONFIG(ADDR_SURF_P2) | 2572 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2573 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2574 break; 2575 case 22: 2576 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2577 PIPE_CONFIG(ADDR_SURF_P2) | 2578 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2579 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2580 break; 2581 case 24: 2582 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2583 PIPE_CONFIG(ADDR_SURF_P2) | 2584 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2585 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2586 break; 2587 case 25: 2588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2589 PIPE_CONFIG(ADDR_SURF_P2) | 2590 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2591 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2592 break; 2593 case 26: 2594 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2595 PIPE_CONFIG(ADDR_SURF_P2) | 2596 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2597 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2598 break; 2599 case 27: 2600 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2601 PIPE_CONFIG(ADDR_SURF_P2) | 2602 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2603 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2604 break; 2605 case 28: 2606 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2607 PIPE_CONFIG(ADDR_SURF_P2) | 2608 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2609 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2610 break; 2611 case 29: 2612 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2613 PIPE_CONFIG(ADDR_SURF_P2) | 2614 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2615 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2616 break; 2617 case 7: 2618 case 12: 2619 case 17: 2620 case 23: 2621 /* unused idx */ 2622 continue; 2623 default: 2624 gb_tile_moden = 0; 2625 break; 2626 }; 2627 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 2628 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 2629 } 2630 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 2631 switch (reg_offset) { 2632 case 0: 2633 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2636 NUM_BANKS(ADDR_SURF_8_BANK)); 2637 break; 2638 case 1: 2639 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2641 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2642 NUM_BANKS(ADDR_SURF_8_BANK)); 2643 break; 2644 case 2: 2645 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2648 NUM_BANKS(ADDR_SURF_8_BANK)); 2649 break; 2650 case 3: 2651 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2652 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2653 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2654 NUM_BANKS(ADDR_SURF_8_BANK)); 2655 break; 2656 case 4: 2657 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2658 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2659 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2660 NUM_BANKS(ADDR_SURF_8_BANK)); 2661 break; 2662 case 5: 2663 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2666 NUM_BANKS(ADDR_SURF_8_BANK)); 2667 break; 2668 case 6: 2669 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2672 NUM_BANKS(ADDR_SURF_8_BANK)); 2673 break; 2674 case 8: 2675 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2678 NUM_BANKS(ADDR_SURF_16_BANK)); 2679 break; 2680 case 9: 2681 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2682 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2683 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2684 NUM_BANKS(ADDR_SURF_16_BANK)); 2685 break; 2686 case 10: 2687 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2688 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2689 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2690 NUM_BANKS(ADDR_SURF_16_BANK)); 2691 break; 2692 case 11: 2693 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2696 NUM_BANKS(ADDR_SURF_16_BANK)); 2697 break; 2698 case 12: 2699 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2700 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2701 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2702 NUM_BANKS(ADDR_SURF_16_BANK)); 2703 break; 2704 case 13: 2705 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2708 NUM_BANKS(ADDR_SURF_16_BANK)); 2709 break; 2710 case 14: 2711 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2712 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2713 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2714 NUM_BANKS(ADDR_SURF_8_BANK)); 2715 break; 2716 case 7: 2717 /* unused idx */ 2718 continue; 2719 default: 2720 gb_tile_moden = 0; 2721 break; 2722 }; 2723 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 2724 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 2725 } 2726 } 2727 } 2728 2729 static u32 gfx_v8_0_create_bitmask(u32 bit_width) 2730 { 2731 u32 i, mask = 0; 2732 2733 for (i = 0; i < bit_width; i++) { 2734 mask <<= 1; 2735 mask |= 1; 2736 } 2737 return mask; 2738 } 2739 2740 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) 2741 { 2742 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2743 2744 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { 2745 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2746 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2747 } else if (se_num == 0xffffffff) { 2748 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2749 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2750 } else if (sh_num == 0xffffffff) { 2751 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2752 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2753 } else { 2754 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2755 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2756 } 2757 WREG32(mmGRBM_GFX_INDEX, data); 2758 } 2759 2760 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev, 2761 u32 max_rb_num_per_se, 2762 u32 sh_per_se) 2763 { 2764 u32 data, mask; 2765 2766 data = RREG32(mmCC_RB_BACKEND_DISABLE); 2767 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2768 2769 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 2770 2771 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2772 2773 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se); 2774 2775 return data & mask; 2776 } 2777 2778 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, 2779 u32 se_num, u32 sh_per_se, 2780 u32 max_rb_num_per_se) 2781 { 2782 int i, j; 2783 u32 data, mask; 2784 u32 disabled_rbs = 0; 2785 u32 enabled_rbs = 0; 2786 2787 mutex_lock(&adev->grbm_idx_mutex); 2788 for (i = 0; i < se_num; i++) { 2789 for (j = 0; j < sh_per_se; j++) { 2790 gfx_v8_0_select_se_sh(adev, i, j); 2791 data = gfx_v8_0_get_rb_disabled(adev, 2792 max_rb_num_per_se, sh_per_se); 2793 disabled_rbs |= data << ((i * sh_per_se + j) * 2794 RB_BITMAP_WIDTH_PER_SH); 2795 } 2796 } 2797 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2798 mutex_unlock(&adev->grbm_idx_mutex); 2799 2800 mask = 1; 2801 for (i = 0; i < max_rb_num_per_se * se_num; i++) { 2802 if (!(disabled_rbs & mask)) 2803 enabled_rbs |= mask; 2804 mask <<= 1; 2805 } 2806 2807 adev->gfx.config.backend_enable_mask = enabled_rbs; 2808 2809 mutex_lock(&adev->grbm_idx_mutex); 2810 for (i = 0; i < se_num; i++) { 2811 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); 2812 data = 0; 2813 for (j = 0; j < sh_per_se; j++) { 2814 switch (enabled_rbs & 3) { 2815 case 0: 2816 if (j == 0) 2817 data |= (RASTER_CONFIG_RB_MAP_3 << 2818 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); 2819 else 2820 data |= (RASTER_CONFIG_RB_MAP_0 << 2821 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); 2822 break; 2823 case 1: 2824 data |= (RASTER_CONFIG_RB_MAP_0 << 2825 (i * sh_per_se + j) * 2); 2826 break; 2827 case 2: 2828 data |= (RASTER_CONFIG_RB_MAP_3 << 2829 (i * sh_per_se + j) * 2); 2830 break; 2831 case 3: 2832 default: 2833 data |= (RASTER_CONFIG_RB_MAP_2 << 2834 (i * sh_per_se + j) * 2); 2835 break; 2836 } 2837 enabled_rbs >>= 2; 2838 } 2839 WREG32(mmPA_SC_RASTER_CONFIG, data); 2840 } 2841 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2842 mutex_unlock(&adev->grbm_idx_mutex); 2843 } 2844 2845 /** 2846 * gfx_v8_0_init_compute_vmid - gart enable 2847 * 2848 * @rdev: amdgpu_device pointer 2849 * 2850 * Initialize compute vmid sh_mem registers 2851 * 2852 */ 2853 #define DEFAULT_SH_MEM_BASES (0x6000) 2854 #define FIRST_COMPUTE_VMID (8) 2855 #define LAST_COMPUTE_VMID (16) 2856 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) 2857 { 2858 int i; 2859 uint32_t sh_mem_config; 2860 uint32_t sh_mem_bases; 2861 2862 /* 2863 * Configure apertures: 2864 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2865 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2866 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2867 */ 2868 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2869 2870 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << 2871 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | 2872 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2873 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | 2874 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | 2875 SH_MEM_CONFIG__PRIVATE_ATC_MASK; 2876 2877 mutex_lock(&adev->srbm_mutex); 2878 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 2879 vi_srbm_select(adev, 0, 0, 0, i); 2880 /* CP and shaders */ 2881 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 2882 WREG32(mmSH_MEM_APE1_BASE, 1); 2883 WREG32(mmSH_MEM_APE1_LIMIT, 0); 2884 WREG32(mmSH_MEM_BASES, sh_mem_bases); 2885 } 2886 vi_srbm_select(adev, 0, 0, 0, 0); 2887 mutex_unlock(&adev->srbm_mutex); 2888 } 2889 2890 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 2891 { 2892 u32 tmp; 2893 int i; 2894 2895 tmp = RREG32(mmGRBM_CNTL); 2896 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); 2897 WREG32(mmGRBM_CNTL, tmp); 2898 2899 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 2900 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 2901 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 2902 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, 2903 adev->gfx.config.gb_addr_config & 0x70); 2904 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, 2905 adev->gfx.config.gb_addr_config & 0x70); 2906 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 2907 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 2908 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 2909 2910 gfx_v8_0_tiling_mode_table_init(adev); 2911 2912 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, 2913 adev->gfx.config.max_sh_per_se, 2914 adev->gfx.config.max_backends_per_se); 2915 2916 /* XXX SH_MEM regs */ 2917 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2918 mutex_lock(&adev->srbm_mutex); 2919 for (i = 0; i < 16; i++) { 2920 vi_srbm_select(adev, 0, 0, 0, i); 2921 /* CP and shaders */ 2922 if (i == 0) { 2923 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); 2924 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 2925 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 2926 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2927 WREG32(mmSH_MEM_CONFIG, tmp); 2928 } else { 2929 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); 2930 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); 2931 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 2932 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2933 WREG32(mmSH_MEM_CONFIG, tmp); 2934 } 2935 2936 WREG32(mmSH_MEM_APE1_BASE, 1); 2937 WREG32(mmSH_MEM_APE1_LIMIT, 0); 2938 WREG32(mmSH_MEM_BASES, 0); 2939 } 2940 vi_srbm_select(adev, 0, 0, 0, 0); 2941 mutex_unlock(&adev->srbm_mutex); 2942 2943 gfx_v8_0_init_compute_vmid(adev); 2944 2945 mutex_lock(&adev->grbm_idx_mutex); 2946 /* 2947 * making sure that the following register writes will be broadcasted 2948 * to all the shaders 2949 */ 2950 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2951 2952 WREG32(mmPA_SC_FIFO_SIZE, 2953 (adev->gfx.config.sc_prim_fifo_size_frontend << 2954 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 2955 (adev->gfx.config.sc_prim_fifo_size_backend << 2956 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 2957 (adev->gfx.config.sc_hiz_tile_fifo_size << 2958 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 2959 (adev->gfx.config.sc_earlyz_tile_fifo_size << 2960 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 2961 mutex_unlock(&adev->grbm_idx_mutex); 2962 2963 } 2964 2965 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2966 { 2967 u32 i, j, k; 2968 u32 mask; 2969 2970 mutex_lock(&adev->grbm_idx_mutex); 2971 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2972 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2973 gfx_v8_0_select_se_sh(adev, i, j); 2974 for (k = 0; k < adev->usec_timeout; k++) { 2975 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2976 break; 2977 udelay(1); 2978 } 2979 } 2980 } 2981 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2982 mutex_unlock(&adev->grbm_idx_mutex); 2983 2984 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2985 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2986 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2987 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2988 for (k = 0; k < adev->usec_timeout; k++) { 2989 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2990 break; 2991 udelay(1); 2992 } 2993 } 2994 2995 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2996 bool enable) 2997 { 2998 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2999 3000 if (enable) { 3001 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1); 3002 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1); 3003 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1); 3004 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1); 3005 } else { 3006 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0); 3007 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0); 3008 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0); 3009 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0); 3010 } 3011 WREG32(mmCP_INT_CNTL_RING0, tmp); 3012 } 3013 3014 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) 3015 { 3016 u32 tmp = RREG32(mmRLC_CNTL); 3017 3018 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 3019 WREG32(mmRLC_CNTL, tmp); 3020 3021 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 3022 3023 gfx_v8_0_wait_for_rlc_serdes(adev); 3024 } 3025 3026 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) 3027 { 3028 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3029 3030 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3031 WREG32(mmGRBM_SOFT_RESET, tmp); 3032 udelay(50); 3033 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 3034 WREG32(mmGRBM_SOFT_RESET, tmp); 3035 udelay(50); 3036 } 3037 3038 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) 3039 { 3040 u32 tmp = RREG32(mmRLC_CNTL); 3041 3042 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); 3043 WREG32(mmRLC_CNTL, tmp); 3044 3045 /* carrizo do enable cp interrupt after cp inited */ 3046 if (!(adev->flags & AMD_IS_APU)) 3047 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 3048 3049 udelay(50); 3050 } 3051 3052 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) 3053 { 3054 const struct rlc_firmware_header_v2_0 *hdr; 3055 const __le32 *fw_data; 3056 unsigned i, fw_size; 3057 3058 if (!adev->gfx.rlc_fw) 3059 return -EINVAL; 3060 3061 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3062 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3063 3064 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 3065 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3066 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3067 3068 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3069 for (i = 0; i < fw_size; i++) 3070 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3071 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3072 3073 return 0; 3074 } 3075 3076 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 3077 { 3078 int r; 3079 3080 gfx_v8_0_rlc_stop(adev); 3081 3082 /* disable CG */ 3083 WREG32(mmRLC_CGCG_CGLS_CTRL, 0); 3084 3085 /* disable PG */ 3086 WREG32(mmRLC_PG_CNTL, 0); 3087 3088 gfx_v8_0_rlc_reset(adev); 3089 3090 if (!adev->firmware.smu_load) { 3091 /* legacy rlc firmware loading */ 3092 r = gfx_v8_0_rlc_load_microcode(adev); 3093 if (r) 3094 return r; 3095 } else { 3096 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3097 AMDGPU_UCODE_ID_RLC_G); 3098 if (r) 3099 return -EINVAL; 3100 } 3101 3102 gfx_v8_0_rlc_start(adev); 3103 3104 return 0; 3105 } 3106 3107 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3108 { 3109 int i; 3110 u32 tmp = RREG32(mmCP_ME_CNTL); 3111 3112 if (enable) { 3113 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); 3114 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); 3115 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); 3116 } else { 3117 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); 3118 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); 3119 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); 3120 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3121 adev->gfx.gfx_ring[i].ready = false; 3122 } 3123 WREG32(mmCP_ME_CNTL, tmp); 3124 udelay(50); 3125 } 3126 3127 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3128 { 3129 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3130 const struct gfx_firmware_header_v1_0 *ce_hdr; 3131 const struct gfx_firmware_header_v1_0 *me_hdr; 3132 const __le32 *fw_data; 3133 unsigned i, fw_size; 3134 3135 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3136 return -EINVAL; 3137 3138 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3139 adev->gfx.pfp_fw->data; 3140 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3141 adev->gfx.ce_fw->data; 3142 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3143 adev->gfx.me_fw->data; 3144 3145 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3146 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3147 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3148 3149 gfx_v8_0_cp_gfx_enable(adev, false); 3150 3151 /* PFP */ 3152 fw_data = (const __le32 *) 3153 (adev->gfx.pfp_fw->data + 3154 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3155 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3156 WREG32(mmCP_PFP_UCODE_ADDR, 0); 3157 for (i = 0; i < fw_size; i++) 3158 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3159 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3160 3161 /* CE */ 3162 fw_data = (const __le32 *) 3163 (adev->gfx.ce_fw->data + 3164 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3165 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3166 WREG32(mmCP_CE_UCODE_ADDR, 0); 3167 for (i = 0; i < fw_size; i++) 3168 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3169 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3170 3171 /* ME */ 3172 fw_data = (const __le32 *) 3173 (adev->gfx.me_fw->data + 3174 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3175 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3176 WREG32(mmCP_ME_RAM_WADDR, 0); 3177 for (i = 0; i < fw_size; i++) 3178 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3179 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3180 3181 return 0; 3182 } 3183 3184 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) 3185 { 3186 u32 count = 0; 3187 const struct cs_section_def *sect = NULL; 3188 const struct cs_extent_def *ext = NULL; 3189 3190 /* begin clear state */ 3191 count += 2; 3192 /* context control state */ 3193 count += 3; 3194 3195 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 3196 for (ext = sect->section; ext->extent != NULL; ++ext) { 3197 if (sect->id == SECT_CONTEXT) 3198 count += 2 + ext->reg_count; 3199 else 3200 return 0; 3201 } 3202 } 3203 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3204 count += 4; 3205 /* end clear state */ 3206 count += 2; 3207 /* clear state */ 3208 count += 2; 3209 3210 return count; 3211 } 3212 3213 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) 3214 { 3215 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3216 const struct cs_section_def *sect = NULL; 3217 const struct cs_extent_def *ext = NULL; 3218 int r, i; 3219 3220 /* init the CP */ 3221 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3222 WREG32(mmCP_ENDIAN_SWAP, 0); 3223 WREG32(mmCP_DEVICE_ID, 1); 3224 3225 gfx_v8_0_cp_gfx_enable(adev, true); 3226 3227 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4); 3228 if (r) { 3229 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3230 return r; 3231 } 3232 3233 /* clear state buffer */ 3234 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3235 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3236 3237 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3238 amdgpu_ring_write(ring, 0x80000000); 3239 amdgpu_ring_write(ring, 0x80000000); 3240 3241 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 3242 for (ext = sect->section; ext->extent != NULL; ++ext) { 3243 if (sect->id == SECT_CONTEXT) { 3244 amdgpu_ring_write(ring, 3245 PACKET3(PACKET3_SET_CONTEXT_REG, 3246 ext->reg_count)); 3247 amdgpu_ring_write(ring, 3248 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3249 for (i = 0; i < ext->reg_count; i++) 3250 amdgpu_ring_write(ring, ext->extent[i]); 3251 } 3252 } 3253 } 3254 3255 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 3256 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3257 switch (adev->asic_type) { 3258 case CHIP_TONGA: 3259 amdgpu_ring_write(ring, 0x16000012); 3260 amdgpu_ring_write(ring, 0x0000002A); 3261 break; 3262 case CHIP_FIJI: 3263 amdgpu_ring_write(ring, 0x3a00161a); 3264 amdgpu_ring_write(ring, 0x0000002e); 3265 break; 3266 case CHIP_TOPAZ: 3267 case CHIP_CARRIZO: 3268 amdgpu_ring_write(ring, 0x00000002); 3269 amdgpu_ring_write(ring, 0x00000000); 3270 break; 3271 case CHIP_STONEY: 3272 amdgpu_ring_write(ring, 0x00000000); 3273 amdgpu_ring_write(ring, 0x00000000); 3274 break; 3275 default: 3276 BUG(); 3277 } 3278 3279 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3280 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3281 3282 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3283 amdgpu_ring_write(ring, 0); 3284 3285 /* init the CE partitions */ 3286 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3287 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3288 amdgpu_ring_write(ring, 0x8000); 3289 amdgpu_ring_write(ring, 0x8000); 3290 3291 amdgpu_ring_unlock_commit(ring); 3292 3293 return 0; 3294 } 3295 3296 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) 3297 { 3298 struct amdgpu_ring *ring; 3299 u32 tmp; 3300 u32 rb_bufsz; 3301 u64 rb_addr, rptr_addr; 3302 int r; 3303 3304 /* Set the write pointer delay */ 3305 WREG32(mmCP_RB_WPTR_DELAY, 0); 3306 3307 /* set the RB to use vmid 0 */ 3308 WREG32(mmCP_RB_VMID, 0); 3309 3310 /* Set ring buffer size */ 3311 ring = &adev->gfx.gfx_ring[0]; 3312 rb_bufsz = order_base_2(ring->ring_size / 8); 3313 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3314 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3315 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); 3316 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); 3317 #ifdef __BIG_ENDIAN 3318 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3319 #endif 3320 WREG32(mmCP_RB0_CNTL, tmp); 3321 3322 /* Initialize the ring buffer's read and write pointers */ 3323 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 3324 ring->wptr = 0; 3325 WREG32(mmCP_RB0_WPTR, ring->wptr); 3326 3327 /* set the wb address wether it's enabled or not */ 3328 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3329 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3330 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 3331 3332 mdelay(1); 3333 WREG32(mmCP_RB0_CNTL, tmp); 3334 3335 rb_addr = ring->gpu_addr >> 8; 3336 WREG32(mmCP_RB0_BASE, rb_addr); 3337 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3338 3339 /* no gfx doorbells on iceland */ 3340 if (adev->asic_type != CHIP_TOPAZ) { 3341 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); 3342 if (ring->use_doorbell) { 3343 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3344 DOORBELL_OFFSET, ring->doorbell_index); 3345 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3346 DOORBELL_EN, 1); 3347 } else { 3348 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3349 DOORBELL_EN, 0); 3350 } 3351 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); 3352 3353 if (adev->asic_type == CHIP_TONGA) { 3354 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3355 DOORBELL_RANGE_LOWER, 3356 AMDGPU_DOORBELL_GFX_RING0); 3357 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3358 3359 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, 3360 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3361 } 3362 3363 } 3364 3365 /* start the ring */ 3366 gfx_v8_0_cp_gfx_start(adev); 3367 ring->ready = true; 3368 r = amdgpu_ring_test_ring(ring); 3369 if (r) { 3370 ring->ready = false; 3371 return r; 3372 } 3373 3374 return 0; 3375 } 3376 3377 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3378 { 3379 int i; 3380 3381 if (enable) { 3382 WREG32(mmCP_MEC_CNTL, 0); 3383 } else { 3384 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3385 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3386 adev->gfx.compute_ring[i].ready = false; 3387 } 3388 udelay(50); 3389 } 3390 3391 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev) 3392 { 3393 gfx_v8_0_cp_compute_enable(adev, true); 3394 3395 return 0; 3396 } 3397 3398 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3399 { 3400 const struct gfx_firmware_header_v1_0 *mec_hdr; 3401 const __le32 *fw_data; 3402 unsigned i, fw_size; 3403 3404 if (!adev->gfx.mec_fw) 3405 return -EINVAL; 3406 3407 gfx_v8_0_cp_compute_enable(adev, false); 3408 3409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3410 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3411 3412 fw_data = (const __le32 *) 3413 (adev->gfx.mec_fw->data + 3414 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3415 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 3416 3417 /* MEC1 */ 3418 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 3419 for (i = 0; i < fw_size; i++) 3420 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); 3421 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3422 3423 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3424 if (adev->gfx.mec2_fw) { 3425 const struct gfx_firmware_header_v1_0 *mec2_hdr; 3426 3427 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 3428 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 3429 3430 fw_data = (const __le32 *) 3431 (adev->gfx.mec2_fw->data + 3432 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 3433 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 3434 3435 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 3436 for (i = 0; i < fw_size; i++) 3437 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i)); 3438 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); 3439 } 3440 3441 return 0; 3442 } 3443 3444 struct vi_mqd { 3445 uint32_t header; /* ordinal0 */ 3446 uint32_t compute_dispatch_initiator; /* ordinal1 */ 3447 uint32_t compute_dim_x; /* ordinal2 */ 3448 uint32_t compute_dim_y; /* ordinal3 */ 3449 uint32_t compute_dim_z; /* ordinal4 */ 3450 uint32_t compute_start_x; /* ordinal5 */ 3451 uint32_t compute_start_y; /* ordinal6 */ 3452 uint32_t compute_start_z; /* ordinal7 */ 3453 uint32_t compute_num_thread_x; /* ordinal8 */ 3454 uint32_t compute_num_thread_y; /* ordinal9 */ 3455 uint32_t compute_num_thread_z; /* ordinal10 */ 3456 uint32_t compute_pipelinestat_enable; /* ordinal11 */ 3457 uint32_t compute_perfcount_enable; /* ordinal12 */ 3458 uint32_t compute_pgm_lo; /* ordinal13 */ 3459 uint32_t compute_pgm_hi; /* ordinal14 */ 3460 uint32_t compute_tba_lo; /* ordinal15 */ 3461 uint32_t compute_tba_hi; /* ordinal16 */ 3462 uint32_t compute_tma_lo; /* ordinal17 */ 3463 uint32_t compute_tma_hi; /* ordinal18 */ 3464 uint32_t compute_pgm_rsrc1; /* ordinal19 */ 3465 uint32_t compute_pgm_rsrc2; /* ordinal20 */ 3466 uint32_t compute_vmid; /* ordinal21 */ 3467 uint32_t compute_resource_limits; /* ordinal22 */ 3468 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */ 3469 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */ 3470 uint32_t compute_tmpring_size; /* ordinal25 */ 3471 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */ 3472 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */ 3473 uint32_t compute_restart_x; /* ordinal28 */ 3474 uint32_t compute_restart_y; /* ordinal29 */ 3475 uint32_t compute_restart_z; /* ordinal30 */ 3476 uint32_t compute_thread_trace_enable; /* ordinal31 */ 3477 uint32_t compute_misc_reserved; /* ordinal32 */ 3478 uint32_t compute_dispatch_id; /* ordinal33 */ 3479 uint32_t compute_threadgroup_id; /* ordinal34 */ 3480 uint32_t compute_relaunch; /* ordinal35 */ 3481 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */ 3482 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */ 3483 uint32_t compute_wave_restore_control; /* ordinal38 */ 3484 uint32_t reserved9; /* ordinal39 */ 3485 uint32_t reserved10; /* ordinal40 */ 3486 uint32_t reserved11; /* ordinal41 */ 3487 uint32_t reserved12; /* ordinal42 */ 3488 uint32_t reserved13; /* ordinal43 */ 3489 uint32_t reserved14; /* ordinal44 */ 3490 uint32_t reserved15; /* ordinal45 */ 3491 uint32_t reserved16; /* ordinal46 */ 3492 uint32_t reserved17; /* ordinal47 */ 3493 uint32_t reserved18; /* ordinal48 */ 3494 uint32_t reserved19; /* ordinal49 */ 3495 uint32_t reserved20; /* ordinal50 */ 3496 uint32_t reserved21; /* ordinal51 */ 3497 uint32_t reserved22; /* ordinal52 */ 3498 uint32_t reserved23; /* ordinal53 */ 3499 uint32_t reserved24; /* ordinal54 */ 3500 uint32_t reserved25; /* ordinal55 */ 3501 uint32_t reserved26; /* ordinal56 */ 3502 uint32_t reserved27; /* ordinal57 */ 3503 uint32_t reserved28; /* ordinal58 */ 3504 uint32_t reserved29; /* ordinal59 */ 3505 uint32_t reserved30; /* ordinal60 */ 3506 uint32_t reserved31; /* ordinal61 */ 3507 uint32_t reserved32; /* ordinal62 */ 3508 uint32_t reserved33; /* ordinal63 */ 3509 uint32_t reserved34; /* ordinal64 */ 3510 uint32_t compute_user_data_0; /* ordinal65 */ 3511 uint32_t compute_user_data_1; /* ordinal66 */ 3512 uint32_t compute_user_data_2; /* ordinal67 */ 3513 uint32_t compute_user_data_3; /* ordinal68 */ 3514 uint32_t compute_user_data_4; /* ordinal69 */ 3515 uint32_t compute_user_data_5; /* ordinal70 */ 3516 uint32_t compute_user_data_6; /* ordinal71 */ 3517 uint32_t compute_user_data_7; /* ordinal72 */ 3518 uint32_t compute_user_data_8; /* ordinal73 */ 3519 uint32_t compute_user_data_9; /* ordinal74 */ 3520 uint32_t compute_user_data_10; /* ordinal75 */ 3521 uint32_t compute_user_data_11; /* ordinal76 */ 3522 uint32_t compute_user_data_12; /* ordinal77 */ 3523 uint32_t compute_user_data_13; /* ordinal78 */ 3524 uint32_t compute_user_data_14; /* ordinal79 */ 3525 uint32_t compute_user_data_15; /* ordinal80 */ 3526 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */ 3527 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */ 3528 uint32_t reserved35; /* ordinal83 */ 3529 uint32_t reserved36; /* ordinal84 */ 3530 uint32_t reserved37; /* ordinal85 */ 3531 uint32_t cp_mqd_query_time_lo; /* ordinal86 */ 3532 uint32_t cp_mqd_query_time_hi; /* ordinal87 */ 3533 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */ 3534 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */ 3535 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */ 3536 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */ 3537 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */ 3538 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */ 3539 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */ 3540 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */ 3541 uint32_t reserved38; /* ordinal96 */ 3542 uint32_t reserved39; /* ordinal97 */ 3543 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */ 3544 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */ 3545 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */ 3546 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */ 3547 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */ 3548 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */ 3549 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */ 3550 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */ 3551 uint32_t reserved40; /* ordinal106 */ 3552 uint32_t reserved41; /* ordinal107 */ 3553 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */ 3554 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */ 3555 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */ 3556 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */ 3557 uint32_t reserved42; /* ordinal112 */ 3558 uint32_t reserved43; /* ordinal113 */ 3559 uint32_t cp_pq_exe_status_lo; /* ordinal114 */ 3560 uint32_t cp_pq_exe_status_hi; /* ordinal115 */ 3561 uint32_t cp_packet_id_lo; /* ordinal116 */ 3562 uint32_t cp_packet_id_hi; /* ordinal117 */ 3563 uint32_t cp_packet_exe_status_lo; /* ordinal118 */ 3564 uint32_t cp_packet_exe_status_hi; /* ordinal119 */ 3565 uint32_t gds_save_base_addr_lo; /* ordinal120 */ 3566 uint32_t gds_save_base_addr_hi; /* ordinal121 */ 3567 uint32_t gds_save_mask_lo; /* ordinal122 */ 3568 uint32_t gds_save_mask_hi; /* ordinal123 */ 3569 uint32_t ctx_save_base_addr_lo; /* ordinal124 */ 3570 uint32_t ctx_save_base_addr_hi; /* ordinal125 */ 3571 uint32_t reserved44; /* ordinal126 */ 3572 uint32_t reserved45; /* ordinal127 */ 3573 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */ 3574 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */ 3575 uint32_t cp_hqd_active; /* ordinal130 */ 3576 uint32_t cp_hqd_vmid; /* ordinal131 */ 3577 uint32_t cp_hqd_persistent_state; /* ordinal132 */ 3578 uint32_t cp_hqd_pipe_priority; /* ordinal133 */ 3579 uint32_t cp_hqd_queue_priority; /* ordinal134 */ 3580 uint32_t cp_hqd_quantum; /* ordinal135 */ 3581 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */ 3582 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */ 3583 uint32_t cp_hqd_pq_rptr; /* ordinal138 */ 3584 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */ 3585 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */ 3586 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */ 3587 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */ 3588 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */ 3589 uint32_t cp_hqd_pq_wptr; /* ordinal144 */ 3590 uint32_t cp_hqd_pq_control; /* ordinal145 */ 3591 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */ 3592 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */ 3593 uint32_t cp_hqd_ib_rptr; /* ordinal148 */ 3594 uint32_t cp_hqd_ib_control; /* ordinal149 */ 3595 uint32_t cp_hqd_iq_timer; /* ordinal150 */ 3596 uint32_t cp_hqd_iq_rptr; /* ordinal151 */ 3597 uint32_t cp_hqd_dequeue_request; /* ordinal152 */ 3598 uint32_t cp_hqd_dma_offload; /* ordinal153 */ 3599 uint32_t cp_hqd_sema_cmd; /* ordinal154 */ 3600 uint32_t cp_hqd_msg_type; /* ordinal155 */ 3601 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */ 3602 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */ 3603 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */ 3604 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */ 3605 uint32_t cp_hqd_hq_status0; /* ordinal160 */ 3606 uint32_t cp_hqd_hq_control0; /* ordinal161 */ 3607 uint32_t cp_mqd_control; /* ordinal162 */ 3608 uint32_t cp_hqd_hq_status1; /* ordinal163 */ 3609 uint32_t cp_hqd_hq_control1; /* ordinal164 */ 3610 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */ 3611 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */ 3612 uint32_t cp_hqd_eop_control; /* ordinal167 */ 3613 uint32_t cp_hqd_eop_rptr; /* ordinal168 */ 3614 uint32_t cp_hqd_eop_wptr; /* ordinal169 */ 3615 uint32_t cp_hqd_eop_done_events; /* ordinal170 */ 3616 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */ 3617 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */ 3618 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */ 3619 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */ 3620 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */ 3621 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */ 3622 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */ 3623 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */ 3624 uint32_t cp_hqd_error; /* ordinal179 */ 3625 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */ 3626 uint32_t cp_hqd_eop_dones; /* ordinal181 */ 3627 uint32_t reserved46; /* ordinal182 */ 3628 uint32_t reserved47; /* ordinal183 */ 3629 uint32_t reserved48; /* ordinal184 */ 3630 uint32_t reserved49; /* ordinal185 */ 3631 uint32_t reserved50; /* ordinal186 */ 3632 uint32_t reserved51; /* ordinal187 */ 3633 uint32_t reserved52; /* ordinal188 */ 3634 uint32_t reserved53; /* ordinal189 */ 3635 uint32_t reserved54; /* ordinal190 */ 3636 uint32_t reserved55; /* ordinal191 */ 3637 uint32_t iqtimer_pkt_header; /* ordinal192 */ 3638 uint32_t iqtimer_pkt_dw0; /* ordinal193 */ 3639 uint32_t iqtimer_pkt_dw1; /* ordinal194 */ 3640 uint32_t iqtimer_pkt_dw2; /* ordinal195 */ 3641 uint32_t iqtimer_pkt_dw3; /* ordinal196 */ 3642 uint32_t iqtimer_pkt_dw4; /* ordinal197 */ 3643 uint32_t iqtimer_pkt_dw5; /* ordinal198 */ 3644 uint32_t iqtimer_pkt_dw6; /* ordinal199 */ 3645 uint32_t iqtimer_pkt_dw7; /* ordinal200 */ 3646 uint32_t iqtimer_pkt_dw8; /* ordinal201 */ 3647 uint32_t iqtimer_pkt_dw9; /* ordinal202 */ 3648 uint32_t iqtimer_pkt_dw10; /* ordinal203 */ 3649 uint32_t iqtimer_pkt_dw11; /* ordinal204 */ 3650 uint32_t iqtimer_pkt_dw12; /* ordinal205 */ 3651 uint32_t iqtimer_pkt_dw13; /* ordinal206 */ 3652 uint32_t iqtimer_pkt_dw14; /* ordinal207 */ 3653 uint32_t iqtimer_pkt_dw15; /* ordinal208 */ 3654 uint32_t iqtimer_pkt_dw16; /* ordinal209 */ 3655 uint32_t iqtimer_pkt_dw17; /* ordinal210 */ 3656 uint32_t iqtimer_pkt_dw18; /* ordinal211 */ 3657 uint32_t iqtimer_pkt_dw19; /* ordinal212 */ 3658 uint32_t iqtimer_pkt_dw20; /* ordinal213 */ 3659 uint32_t iqtimer_pkt_dw21; /* ordinal214 */ 3660 uint32_t iqtimer_pkt_dw22; /* ordinal215 */ 3661 uint32_t iqtimer_pkt_dw23; /* ordinal216 */ 3662 uint32_t iqtimer_pkt_dw24; /* ordinal217 */ 3663 uint32_t iqtimer_pkt_dw25; /* ordinal218 */ 3664 uint32_t iqtimer_pkt_dw26; /* ordinal219 */ 3665 uint32_t iqtimer_pkt_dw27; /* ordinal220 */ 3666 uint32_t iqtimer_pkt_dw28; /* ordinal221 */ 3667 uint32_t iqtimer_pkt_dw29; /* ordinal222 */ 3668 uint32_t iqtimer_pkt_dw30; /* ordinal223 */ 3669 uint32_t iqtimer_pkt_dw31; /* ordinal224 */ 3670 uint32_t reserved56; /* ordinal225 */ 3671 uint32_t reserved57; /* ordinal226 */ 3672 uint32_t reserved58; /* ordinal227 */ 3673 uint32_t set_resources_header; /* ordinal228 */ 3674 uint32_t set_resources_dw1; /* ordinal229 */ 3675 uint32_t set_resources_dw2; /* ordinal230 */ 3676 uint32_t set_resources_dw3; /* ordinal231 */ 3677 uint32_t set_resources_dw4; /* ordinal232 */ 3678 uint32_t set_resources_dw5; /* ordinal233 */ 3679 uint32_t set_resources_dw6; /* ordinal234 */ 3680 uint32_t set_resources_dw7; /* ordinal235 */ 3681 uint32_t reserved59; /* ordinal236 */ 3682 uint32_t reserved60; /* ordinal237 */ 3683 uint32_t reserved61; /* ordinal238 */ 3684 uint32_t reserved62; /* ordinal239 */ 3685 uint32_t reserved63; /* ordinal240 */ 3686 uint32_t reserved64; /* ordinal241 */ 3687 uint32_t reserved65; /* ordinal242 */ 3688 uint32_t reserved66; /* ordinal243 */ 3689 uint32_t reserved67; /* ordinal244 */ 3690 uint32_t reserved68; /* ordinal245 */ 3691 uint32_t reserved69; /* ordinal246 */ 3692 uint32_t reserved70; /* ordinal247 */ 3693 uint32_t reserved71; /* ordinal248 */ 3694 uint32_t reserved72; /* ordinal249 */ 3695 uint32_t reserved73; /* ordinal250 */ 3696 uint32_t reserved74; /* ordinal251 */ 3697 uint32_t reserved75; /* ordinal252 */ 3698 uint32_t reserved76; /* ordinal253 */ 3699 uint32_t reserved77; /* ordinal254 */ 3700 uint32_t reserved78; /* ordinal255 */ 3701 3702 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */ 3703 }; 3704 3705 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) 3706 { 3707 int i, r; 3708 3709 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3710 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3711 3712 if (ring->mqd_obj) { 3713 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3714 if (unlikely(r != 0)) 3715 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 3716 3717 amdgpu_bo_unpin(ring->mqd_obj); 3718 amdgpu_bo_unreserve(ring->mqd_obj); 3719 3720 amdgpu_bo_unref(&ring->mqd_obj); 3721 ring->mqd_obj = NULL; 3722 } 3723 } 3724 } 3725 3726 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) 3727 { 3728 int r, i, j; 3729 u32 tmp; 3730 bool use_doorbell = true; 3731 u64 hqd_gpu_addr; 3732 u64 mqd_gpu_addr; 3733 u64 eop_gpu_addr; 3734 u64 wb_gpu_addr; 3735 u32 *buf; 3736 struct vi_mqd *mqd; 3737 3738 /* init the pipes */ 3739 mutex_lock(&adev->srbm_mutex); 3740 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 3741 int me = (i < 4) ? 1 : 2; 3742 int pipe = (i < 4) ? i : (i - 4); 3743 3744 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 3745 eop_gpu_addr >>= 8; 3746 3747 vi_srbm_select(adev, me, pipe, 0, 0); 3748 3749 /* write the EOP addr */ 3750 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); 3751 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); 3752 3753 /* set the VMID assigned */ 3754 WREG32(mmCP_HQD_VMID, 0); 3755 3756 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3757 tmp = RREG32(mmCP_HQD_EOP_CONTROL); 3758 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3759 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 3760 WREG32(mmCP_HQD_EOP_CONTROL, tmp); 3761 } 3762 vi_srbm_select(adev, 0, 0, 0, 0); 3763 mutex_unlock(&adev->srbm_mutex); 3764 3765 /* init the queues. Just two for now. */ 3766 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3767 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3768 3769 if (ring->mqd_obj == NULL) { 3770 r = amdgpu_bo_create(adev, 3771 sizeof(struct vi_mqd), 3772 PAGE_SIZE, true, 3773 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, 3774 NULL, &ring->mqd_obj); 3775 if (r) { 3776 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3777 return r; 3778 } 3779 } 3780 3781 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3782 if (unlikely(r != 0)) { 3783 gfx_v8_0_cp_compute_fini(adev); 3784 return r; 3785 } 3786 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 3787 &mqd_gpu_addr); 3788 if (r) { 3789 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 3790 gfx_v8_0_cp_compute_fini(adev); 3791 return r; 3792 } 3793 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 3794 if (r) { 3795 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 3796 gfx_v8_0_cp_compute_fini(adev); 3797 return r; 3798 } 3799 3800 /* init the mqd struct */ 3801 memset(buf, 0, sizeof(struct vi_mqd)); 3802 3803 mqd = (struct vi_mqd *)buf; 3804 mqd->header = 0xC0310800; 3805 mqd->compute_pipelinestat_enable = 0x00000001; 3806 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3807 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3808 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3809 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3810 mqd->compute_misc_reserved = 0x00000003; 3811 3812 mutex_lock(&adev->srbm_mutex); 3813 vi_srbm_select(adev, ring->me, 3814 ring->pipe, 3815 ring->queue, 0); 3816 3817 /* disable wptr polling */ 3818 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3819 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3820 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3821 3822 mqd->cp_hqd_eop_base_addr_lo = 3823 RREG32(mmCP_HQD_EOP_BASE_ADDR); 3824 mqd->cp_hqd_eop_base_addr_hi = 3825 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI); 3826 3827 /* enable doorbell? */ 3828 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3829 if (use_doorbell) { 3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 3831 } else { 3832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); 3833 } 3834 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); 3835 mqd->cp_hqd_pq_doorbell_control = tmp; 3836 3837 /* disable the queue if it's active */ 3838 mqd->cp_hqd_dequeue_request = 0; 3839 mqd->cp_hqd_pq_rptr = 0; 3840 mqd->cp_hqd_pq_wptr= 0; 3841 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 3842 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 3843 for (j = 0; j < adev->usec_timeout; j++) { 3844 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 3845 break; 3846 udelay(1); 3847 } 3848 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); 3849 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); 3850 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); 3851 } 3852 3853 /* set the pointer to the MQD */ 3854 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 3855 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3856 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 3857 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3858 3859 /* set MQD vmid to 0 */ 3860 tmp = RREG32(mmCP_MQD_CONTROL); 3861 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3862 WREG32(mmCP_MQD_CONTROL, tmp); 3863 mqd->cp_mqd_control = tmp; 3864 3865 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3866 hqd_gpu_addr = ring->gpu_addr >> 8; 3867 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3868 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3869 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 3870 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 3871 3872 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3873 tmp = RREG32(mmCP_HQD_PQ_CONTROL); 3874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3875 (order_base_2(ring->ring_size / 4) - 1)); 3876 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3877 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3878 #ifdef __BIG_ENDIAN 3879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3880 #endif 3881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3882 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3883 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3884 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3885 WREG32(mmCP_HQD_PQ_CONTROL, tmp); 3886 mqd->cp_hqd_pq_control = tmp; 3887 3888 /* set the wb address wether it's enabled or not */ 3889 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3890 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3891 mqd->cp_hqd_pq_rptr_report_addr_hi = 3892 upper_32_bits(wb_gpu_addr) & 0xffff; 3893 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3894 mqd->cp_hqd_pq_rptr_report_addr_lo); 3895 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3896 mqd->cp_hqd_pq_rptr_report_addr_hi); 3897 3898 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3899 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3900 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 3901 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3902 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); 3903 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3904 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3905 3906 /* enable the doorbell if requested */ 3907 if (use_doorbell) { 3908 if ((adev->asic_type == CHIP_CARRIZO) || 3909 (adev->asic_type == CHIP_FIJI) || 3910 (adev->asic_type == CHIP_STONEY)) { 3911 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, 3912 AMDGPU_DOORBELL_KIQ << 2); 3913 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, 3914 AMDGPU_DOORBELL_MEC_RING7 << 2); 3915 } 3916 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3918 DOORBELL_OFFSET, ring->doorbell_index); 3919 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 3920 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); 3921 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); 3922 mqd->cp_hqd_pq_doorbell_control = tmp; 3923 3924 } else { 3925 mqd->cp_hqd_pq_doorbell_control = 0; 3926 } 3927 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3928 mqd->cp_hqd_pq_doorbell_control); 3929 3930 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3931 ring->wptr = 0; 3932 mqd->cp_hqd_pq_wptr = ring->wptr; 3933 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); 3934 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3935 3936 /* set the vmid for the queue */ 3937 mqd->cp_hqd_vmid = 0; 3938 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3939 3940 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); 3941 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3942 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); 3943 mqd->cp_hqd_persistent_state = tmp; 3944 3945 /* activate the queue */ 3946 mqd->cp_hqd_active = 1; 3947 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 3948 3949 vi_srbm_select(adev, 0, 0, 0, 0); 3950 mutex_unlock(&adev->srbm_mutex); 3951 3952 amdgpu_bo_kunmap(ring->mqd_obj); 3953 amdgpu_bo_unreserve(ring->mqd_obj); 3954 } 3955 3956 if (use_doorbell) { 3957 tmp = RREG32(mmCP_PQ_STATUS); 3958 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3959 WREG32(mmCP_PQ_STATUS, tmp); 3960 } 3961 3962 r = gfx_v8_0_cp_compute_start(adev); 3963 if (r) 3964 return r; 3965 3966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3967 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3968 3969 ring->ready = true; 3970 r = amdgpu_ring_test_ring(ring); 3971 if (r) 3972 ring->ready = false; 3973 } 3974 3975 return 0; 3976 } 3977 3978 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) 3979 { 3980 int r; 3981 3982 if (!(adev->flags & AMD_IS_APU)) 3983 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 3984 3985 if (!adev->firmware.smu_load) { 3986 /* legacy firmware loading */ 3987 r = gfx_v8_0_cp_gfx_load_microcode(adev); 3988 if (r) 3989 return r; 3990 3991 r = gfx_v8_0_cp_compute_load_microcode(adev); 3992 if (r) 3993 return r; 3994 } else { 3995 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3996 AMDGPU_UCODE_ID_CP_CE); 3997 if (r) 3998 return -EINVAL; 3999 4000 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4001 AMDGPU_UCODE_ID_CP_PFP); 4002 if (r) 4003 return -EINVAL; 4004 4005 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4006 AMDGPU_UCODE_ID_CP_ME); 4007 if (r) 4008 return -EINVAL; 4009 4010 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4011 AMDGPU_UCODE_ID_CP_MEC1); 4012 if (r) 4013 return -EINVAL; 4014 } 4015 4016 r = gfx_v8_0_cp_gfx_resume(adev); 4017 if (r) 4018 return r; 4019 4020 r = gfx_v8_0_cp_compute_resume(adev); 4021 if (r) 4022 return r; 4023 4024 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 4025 4026 return 0; 4027 } 4028 4029 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) 4030 { 4031 gfx_v8_0_cp_gfx_enable(adev, enable); 4032 gfx_v8_0_cp_compute_enable(adev, enable); 4033 } 4034 4035 static int gfx_v8_0_hw_init(void *handle) 4036 { 4037 int r; 4038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4039 4040 gfx_v8_0_init_golden_registers(adev); 4041 4042 gfx_v8_0_gpu_init(adev); 4043 4044 r = gfx_v8_0_rlc_resume(adev); 4045 if (r) 4046 return r; 4047 4048 r = gfx_v8_0_cp_resume(adev); 4049 if (r) 4050 return r; 4051 4052 return r; 4053 } 4054 4055 static int gfx_v8_0_hw_fini(void *handle) 4056 { 4057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4058 4059 gfx_v8_0_cp_enable(adev, false); 4060 gfx_v8_0_rlc_stop(adev); 4061 gfx_v8_0_cp_compute_fini(adev); 4062 4063 return 0; 4064 } 4065 4066 static int gfx_v8_0_suspend(void *handle) 4067 { 4068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4069 4070 return gfx_v8_0_hw_fini(adev); 4071 } 4072 4073 static int gfx_v8_0_resume(void *handle) 4074 { 4075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4076 4077 return gfx_v8_0_hw_init(adev); 4078 } 4079 4080 static bool gfx_v8_0_is_idle(void *handle) 4081 { 4082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4083 4084 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 4085 return false; 4086 else 4087 return true; 4088 } 4089 4090 static int gfx_v8_0_wait_for_idle(void *handle) 4091 { 4092 unsigned i; 4093 u32 tmp; 4094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4095 4096 for (i = 0; i < adev->usec_timeout; i++) { 4097 /* read MC_STATUS */ 4098 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4099 4100 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4101 return 0; 4102 udelay(1); 4103 } 4104 return -ETIMEDOUT; 4105 } 4106 4107 static void gfx_v8_0_print_status(void *handle) 4108 { 4109 int i; 4110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4111 4112 dev_info(adev->dev, "GFX 8.x registers\n"); 4113 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 4114 RREG32(mmGRBM_STATUS)); 4115 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 4116 RREG32(mmGRBM_STATUS2)); 4117 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 4118 RREG32(mmGRBM_STATUS_SE0)); 4119 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 4120 RREG32(mmGRBM_STATUS_SE1)); 4121 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 4122 RREG32(mmGRBM_STATUS_SE2)); 4123 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 4124 RREG32(mmGRBM_STATUS_SE3)); 4125 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 4126 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 4127 RREG32(mmCP_STALLED_STAT1)); 4128 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 4129 RREG32(mmCP_STALLED_STAT2)); 4130 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 4131 RREG32(mmCP_STALLED_STAT3)); 4132 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 4133 RREG32(mmCP_CPF_BUSY_STAT)); 4134 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 4135 RREG32(mmCP_CPF_STALLED_STAT1)); 4136 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 4137 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 4138 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 4139 RREG32(mmCP_CPC_STALLED_STAT1)); 4140 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 4141 4142 for (i = 0; i < 32; i++) { 4143 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", 4144 i, RREG32(mmGB_TILE_MODE0 + (i * 4))); 4145 } 4146 for (i = 0; i < 16; i++) { 4147 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", 4148 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); 4149 } 4150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4151 dev_info(adev->dev, " se: %d\n", i); 4152 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); 4153 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", 4154 RREG32(mmPA_SC_RASTER_CONFIG)); 4155 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", 4156 RREG32(mmPA_SC_RASTER_CONFIG_1)); 4157 } 4158 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 4159 4160 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", 4161 RREG32(mmGB_ADDR_CONFIG)); 4162 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", 4163 RREG32(mmHDP_ADDR_CONFIG)); 4164 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", 4165 RREG32(mmDMIF_ADDR_CALC)); 4166 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", 4167 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); 4168 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", 4169 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); 4170 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 4171 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 4172 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 4173 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 4174 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 4175 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 4176 4177 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", 4178 RREG32(mmCP_MEQ_THRESHOLDS)); 4179 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", 4180 RREG32(mmSX_DEBUG_1)); 4181 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", 4182 RREG32(mmTA_CNTL_AUX)); 4183 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", 4184 RREG32(mmSPI_CONFIG_CNTL)); 4185 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", 4186 RREG32(mmSQ_CONFIG)); 4187 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", 4188 RREG32(mmDB_DEBUG)); 4189 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", 4190 RREG32(mmDB_DEBUG2)); 4191 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", 4192 RREG32(mmDB_DEBUG3)); 4193 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", 4194 RREG32(mmCB_HW_CONTROL)); 4195 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", 4196 RREG32(mmSPI_CONFIG_CNTL_1)); 4197 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", 4198 RREG32(mmPA_SC_FIFO_SIZE)); 4199 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", 4200 RREG32(mmVGT_NUM_INSTANCES)); 4201 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", 4202 RREG32(mmCP_PERFMON_CNTL)); 4203 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", 4204 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); 4205 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", 4206 RREG32(mmVGT_CACHE_INVALIDATION)); 4207 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", 4208 RREG32(mmVGT_GS_VERTEX_REUSE)); 4209 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", 4210 RREG32(mmPA_SC_LINE_STIPPLE_STATE)); 4211 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", 4212 RREG32(mmPA_CL_ENHANCE)); 4213 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", 4214 RREG32(mmPA_SC_ENHANCE)); 4215 4216 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", 4217 RREG32(mmCP_ME_CNTL)); 4218 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", 4219 RREG32(mmCP_MAX_CONTEXT)); 4220 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", 4221 RREG32(mmCP_ENDIAN_SWAP)); 4222 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", 4223 RREG32(mmCP_DEVICE_ID)); 4224 4225 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", 4226 RREG32(mmCP_SEM_WAIT_TIMER)); 4227 4228 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", 4229 RREG32(mmCP_RB_WPTR_DELAY)); 4230 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", 4231 RREG32(mmCP_RB_VMID)); 4232 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 4233 RREG32(mmCP_RB0_CNTL)); 4234 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", 4235 RREG32(mmCP_RB0_WPTR)); 4236 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", 4237 RREG32(mmCP_RB0_RPTR_ADDR)); 4238 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", 4239 RREG32(mmCP_RB0_RPTR_ADDR_HI)); 4240 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 4241 RREG32(mmCP_RB0_CNTL)); 4242 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", 4243 RREG32(mmCP_RB0_BASE)); 4244 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", 4245 RREG32(mmCP_RB0_BASE_HI)); 4246 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", 4247 RREG32(mmCP_MEC_CNTL)); 4248 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", 4249 RREG32(mmCP_CPF_DEBUG)); 4250 4251 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", 4252 RREG32(mmSCRATCH_ADDR)); 4253 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", 4254 RREG32(mmSCRATCH_UMSK)); 4255 4256 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", 4257 RREG32(mmCP_INT_CNTL_RING0)); 4258 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 4259 RREG32(mmRLC_LB_CNTL)); 4260 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", 4261 RREG32(mmRLC_CNTL)); 4262 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", 4263 RREG32(mmRLC_CGCG_CGLS_CTRL)); 4264 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", 4265 RREG32(mmRLC_LB_CNTR_INIT)); 4266 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", 4267 RREG32(mmRLC_LB_CNTR_MAX)); 4268 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", 4269 RREG32(mmRLC_LB_INIT_CU_MASK)); 4270 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", 4271 RREG32(mmRLC_LB_PARAMS)); 4272 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 4273 RREG32(mmRLC_LB_CNTL)); 4274 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", 4275 RREG32(mmRLC_MC_CNTL)); 4276 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", 4277 RREG32(mmRLC_UCODE_CNTL)); 4278 4279 mutex_lock(&adev->srbm_mutex); 4280 for (i = 0; i < 16; i++) { 4281 vi_srbm_select(adev, 0, 0, 0, i); 4282 dev_info(adev->dev, " VM %d:\n", i); 4283 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", 4284 RREG32(mmSH_MEM_CONFIG)); 4285 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", 4286 RREG32(mmSH_MEM_APE1_BASE)); 4287 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", 4288 RREG32(mmSH_MEM_APE1_LIMIT)); 4289 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", 4290 RREG32(mmSH_MEM_BASES)); 4291 } 4292 vi_srbm_select(adev, 0, 0, 0, 0); 4293 mutex_unlock(&adev->srbm_mutex); 4294 } 4295 4296 static int gfx_v8_0_soft_reset(void *handle) 4297 { 4298 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4299 u32 tmp; 4300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4301 4302 /* GRBM_STATUS */ 4303 tmp = RREG32(mmGRBM_STATUS); 4304 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4305 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4306 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4307 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4308 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4309 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 4310 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4311 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4312 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4313 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4314 } 4315 4316 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4317 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4318 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4319 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 4320 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 4321 } 4322 4323 /* GRBM_STATUS2 */ 4324 tmp = RREG32(mmGRBM_STATUS2); 4325 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4326 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4327 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4328 4329 /* SRBM_STATUS */ 4330 tmp = RREG32(mmSRBM_STATUS); 4331 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) 4332 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 4333 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 4334 4335 if (grbm_soft_reset || srbm_soft_reset) { 4336 gfx_v8_0_print_status((void *)adev); 4337 /* stop the rlc */ 4338 gfx_v8_0_rlc_stop(adev); 4339 4340 /* Disable GFX parsing/prefetching */ 4341 gfx_v8_0_cp_gfx_enable(adev, false); 4342 4343 /* Disable MEC parsing/prefetching */ 4344 /* XXX todo */ 4345 4346 if (grbm_soft_reset) { 4347 tmp = RREG32(mmGRBM_SOFT_RESET); 4348 tmp |= grbm_soft_reset; 4349 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4350 WREG32(mmGRBM_SOFT_RESET, tmp); 4351 tmp = RREG32(mmGRBM_SOFT_RESET); 4352 4353 udelay(50); 4354 4355 tmp &= ~grbm_soft_reset; 4356 WREG32(mmGRBM_SOFT_RESET, tmp); 4357 tmp = RREG32(mmGRBM_SOFT_RESET); 4358 } 4359 4360 if (srbm_soft_reset) { 4361 tmp = RREG32(mmSRBM_SOFT_RESET); 4362 tmp |= srbm_soft_reset; 4363 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4364 WREG32(mmSRBM_SOFT_RESET, tmp); 4365 tmp = RREG32(mmSRBM_SOFT_RESET); 4366 4367 udelay(50); 4368 4369 tmp &= ~srbm_soft_reset; 4370 WREG32(mmSRBM_SOFT_RESET, tmp); 4371 tmp = RREG32(mmSRBM_SOFT_RESET); 4372 } 4373 /* Wait a little for things to settle down */ 4374 udelay(50); 4375 gfx_v8_0_print_status((void *)adev); 4376 } 4377 return 0; 4378 } 4379 4380 /** 4381 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot 4382 * 4383 * @adev: amdgpu_device pointer 4384 * 4385 * Fetches a GPU clock counter snapshot. 4386 * Returns the 64 bit clock counter snapshot. 4387 */ 4388 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4389 { 4390 uint64_t clock; 4391 4392 mutex_lock(&adev->gfx.gpu_clock_mutex); 4393 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4394 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4395 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4396 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4397 return clock; 4398 } 4399 4400 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4401 uint32_t vmid, 4402 uint32_t gds_base, uint32_t gds_size, 4403 uint32_t gws_base, uint32_t gws_size, 4404 uint32_t oa_base, uint32_t oa_size) 4405 { 4406 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 4407 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 4408 4409 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 4410 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 4411 4412 oa_base = oa_base >> AMDGPU_OA_SHIFT; 4413 oa_size = oa_size >> AMDGPU_OA_SHIFT; 4414 4415 /* GDS Base */ 4416 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4417 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4418 WRITE_DATA_DST_SEL(0))); 4419 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4420 amdgpu_ring_write(ring, 0); 4421 amdgpu_ring_write(ring, gds_base); 4422 4423 /* GDS Size */ 4424 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4425 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4426 WRITE_DATA_DST_SEL(0))); 4427 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4428 amdgpu_ring_write(ring, 0); 4429 amdgpu_ring_write(ring, gds_size); 4430 4431 /* GWS */ 4432 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4433 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4434 WRITE_DATA_DST_SEL(0))); 4435 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4436 amdgpu_ring_write(ring, 0); 4437 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4438 4439 /* OA */ 4440 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4441 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4442 WRITE_DATA_DST_SEL(0))); 4443 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4444 amdgpu_ring_write(ring, 0); 4445 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4446 } 4447 4448 static int gfx_v8_0_early_init(void *handle) 4449 { 4450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4451 4452 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; 4453 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; 4454 gfx_v8_0_set_ring_funcs(adev); 4455 gfx_v8_0_set_irq_funcs(adev); 4456 gfx_v8_0_set_gds_init(adev); 4457 4458 return 0; 4459 } 4460 4461 static int gfx_v8_0_set_powergating_state(void *handle, 4462 enum amd_powergating_state state) 4463 { 4464 return 0; 4465 } 4466 4467 static int gfx_v8_0_set_clockgating_state(void *handle, 4468 enum amd_clockgating_state state) 4469 { 4470 return 0; 4471 } 4472 4473 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4474 { 4475 u32 rptr; 4476 4477 rptr = ring->adev->wb.wb[ring->rptr_offs]; 4478 4479 return rptr; 4480 } 4481 4482 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4483 { 4484 struct amdgpu_device *adev = ring->adev; 4485 u32 wptr; 4486 4487 if (ring->use_doorbell) 4488 /* XXX check if swapping is necessary on BE */ 4489 wptr = ring->adev->wb.wb[ring->wptr_offs]; 4490 else 4491 wptr = RREG32(mmCP_RB0_WPTR); 4492 4493 return wptr; 4494 } 4495 4496 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4497 { 4498 struct amdgpu_device *adev = ring->adev; 4499 4500 if (ring->use_doorbell) { 4501 /* XXX check if swapping is necessary on BE */ 4502 adev->wb.wb[ring->wptr_offs] = ring->wptr; 4503 WDOORBELL32(ring->doorbell_index, ring->wptr); 4504 } else { 4505 WREG32(mmCP_RB0_WPTR, ring->wptr); 4506 (void)RREG32(mmCP_RB0_WPTR); 4507 } 4508 } 4509 4510 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4511 { 4512 u32 ref_and_mask, reg_mem_engine; 4513 4514 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { 4515 switch (ring->me) { 4516 case 1: 4517 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 4518 break; 4519 case 2: 4520 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 4521 break; 4522 default: 4523 return; 4524 } 4525 reg_mem_engine = 0; 4526 } else { 4527 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 4528 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ 4529 } 4530 4531 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4532 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 4533 WAIT_REG_MEM_FUNCTION(3) | /* == */ 4534 reg_mem_engine)); 4535 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 4536 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 4537 amdgpu_ring_write(ring, ref_and_mask); 4538 amdgpu_ring_write(ring, ref_and_mask); 4539 amdgpu_ring_write(ring, 0x20); /* poll interval */ 4540 } 4541 4542 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4543 struct amdgpu_ib *ib) 4544 { 4545 bool need_ctx_switch = ring->current_ctx != ib->ctx; 4546 u32 header, control = 0; 4547 u32 next_rptr = ring->wptr + 5; 4548 4549 /* drop the CE preamble IB for the same context */ 4550 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) 4551 return; 4552 4553 if (need_ctx_switch) 4554 next_rptr += 2; 4555 4556 next_rptr += 4; 4557 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4558 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 4559 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 4560 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 4561 amdgpu_ring_write(ring, next_rptr); 4562 4563 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 4564 if (need_ctx_switch) { 4565 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4566 amdgpu_ring_write(ring, 0); 4567 } 4568 4569 if (ib->flags & AMDGPU_IB_FLAG_CE) 4570 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 4571 else 4572 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4573 4574 control |= ib->length_dw | 4575 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); 4576 4577 amdgpu_ring_write(ring, header); 4578 amdgpu_ring_write(ring, 4579 #ifdef __BIG_ENDIAN 4580 (2 << 0) | 4581 #endif 4582 (ib->gpu_addr & 0xFFFFFFFC)); 4583 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 4584 amdgpu_ring_write(ring, control); 4585 } 4586 4587 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4588 struct amdgpu_ib *ib) 4589 { 4590 u32 header, control = 0; 4591 u32 next_rptr = ring->wptr + 5; 4592 4593 control |= INDIRECT_BUFFER_VALID; 4594 4595 next_rptr += 4; 4596 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4597 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 4598 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 4599 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 4600 amdgpu_ring_write(ring, next_rptr); 4601 4602 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4603 4604 control |= ib->length_dw | 4605 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); 4606 4607 amdgpu_ring_write(ring, header); 4608 amdgpu_ring_write(ring, 4609 #ifdef __BIG_ENDIAN 4610 (2 << 0) | 4611 #endif 4612 (ib->gpu_addr & 0xFFFFFFFC)); 4613 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 4614 amdgpu_ring_write(ring, control); 4615 } 4616 4617 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 4618 u64 seq, unsigned flags) 4619 { 4620 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4621 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4622 4623 /* EVENT_WRITE_EOP - flush caches, send int */ 4624 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 4625 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 4626 EOP_TC_ACTION_EN | 4627 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4628 EVENT_INDEX(5))); 4629 amdgpu_ring_write(ring, addr & 0xfffffffc); 4630 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 4631 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 4632 amdgpu_ring_write(ring, lower_32_bits(seq)); 4633 amdgpu_ring_write(ring, upper_32_bits(seq)); 4634 4635 } 4636 4637 /** 4638 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring 4639 * 4640 * @ring: amdgpu ring buffer object 4641 * @semaphore: amdgpu semaphore object 4642 * @emit_wait: Is this a sempahore wait? 4643 * 4644 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 4645 * from running ahead of semaphore waits. 4646 */ 4647 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, 4648 struct amdgpu_semaphore *semaphore, 4649 bool emit_wait) 4650 { 4651 uint64_t addr = semaphore->gpu_addr; 4652 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 4653 4654 if (ring->adev->asic_type == CHIP_TOPAZ || 4655 ring->adev->asic_type == CHIP_TONGA || 4656 ring->adev->asic_type == CHIP_FIJI) 4657 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */ 4658 return false; 4659 else { 4660 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); 4661 amdgpu_ring_write(ring, lower_32_bits(addr)); 4662 amdgpu_ring_write(ring, upper_32_bits(addr)); 4663 amdgpu_ring_write(ring, sel); 4664 } 4665 4666 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { 4667 /* Prevent the PFP from running ahead of the semaphore wait */ 4668 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4669 amdgpu_ring_write(ring, 0x0); 4670 } 4671 4672 return true; 4673 } 4674 4675 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4676 unsigned vm_id, uint64_t pd_addr) 4677 { 4678 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 4679 uint32_t seq = ring->fence_drv.sync_seq[ring->idx]; 4680 uint64_t addr = ring->fence_drv.gpu_addr; 4681 4682 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4683 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 4684 WAIT_REG_MEM_FUNCTION(3))); /* equal */ 4685 amdgpu_ring_write(ring, addr & 0xfffffffc); 4686 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 4687 amdgpu_ring_write(ring, seq); 4688 amdgpu_ring_write(ring, 0xffffffff); 4689 amdgpu_ring_write(ring, 4); /* poll interval */ 4690 4691 if (usepfp) { 4692 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 4693 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4694 amdgpu_ring_write(ring, 0); 4695 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4696 amdgpu_ring_write(ring, 0); 4697 } 4698 4699 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4700 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 4701 WRITE_DATA_DST_SEL(0)) | 4702 WR_CONFIRM); 4703 if (vm_id < 8) { 4704 amdgpu_ring_write(ring, 4705 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 4706 } else { 4707 amdgpu_ring_write(ring, 4708 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 4709 } 4710 amdgpu_ring_write(ring, 0); 4711 amdgpu_ring_write(ring, pd_addr >> 12); 4712 4713 /* bits 0-15 are the VM contexts0-15 */ 4714 /* invalidate the cache */ 4715 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4716 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4717 WRITE_DATA_DST_SEL(0))); 4718 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 4719 amdgpu_ring_write(ring, 0); 4720 amdgpu_ring_write(ring, 1 << vm_id); 4721 4722 /* wait for the invalidate to complete */ 4723 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4724 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 4725 WAIT_REG_MEM_FUNCTION(0) | /* always */ 4726 WAIT_REG_MEM_ENGINE(0))); /* me */ 4727 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 4728 amdgpu_ring_write(ring, 0); 4729 amdgpu_ring_write(ring, 0); /* ref */ 4730 amdgpu_ring_write(ring, 0); /* mask */ 4731 amdgpu_ring_write(ring, 0x20); /* poll interval */ 4732 4733 /* compute doesn't have PFP */ 4734 if (usepfp) { 4735 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4736 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4737 amdgpu_ring_write(ring, 0x0); 4738 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4739 amdgpu_ring_write(ring, 0); 4740 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4741 amdgpu_ring_write(ring, 0); 4742 } 4743 } 4744 4745 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4746 { 4747 return ring->adev->wb.wb[ring->rptr_offs]; 4748 } 4749 4750 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4751 { 4752 return ring->adev->wb.wb[ring->wptr_offs]; 4753 } 4754 4755 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4756 { 4757 struct amdgpu_device *adev = ring->adev; 4758 4759 /* XXX check if swapping is necessary on BE */ 4760 adev->wb.wb[ring->wptr_offs] = ring->wptr; 4761 WDOORBELL32(ring->doorbell_index, ring->wptr); 4762 } 4763 4764 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 4765 u64 addr, u64 seq, 4766 unsigned flags) 4767 { 4768 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4769 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4770 4771 /* RELEASE_MEM - flush caches, send int */ 4772 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 4773 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 4774 EOP_TC_ACTION_EN | 4775 EOP_TC_WB_ACTION_EN | 4776 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4777 EVENT_INDEX(5))); 4778 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 4779 amdgpu_ring_write(ring, addr & 0xfffffffc); 4780 amdgpu_ring_write(ring, upper_32_bits(addr)); 4781 amdgpu_ring_write(ring, lower_32_bits(seq)); 4782 amdgpu_ring_write(ring, upper_32_bits(seq)); 4783 } 4784 4785 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4786 enum amdgpu_interrupt_state state) 4787 { 4788 u32 cp_int_cntl; 4789 4790 switch (state) { 4791 case AMDGPU_IRQ_STATE_DISABLE: 4792 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4793 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4794 TIME_STAMP_INT_ENABLE, 0); 4795 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4796 break; 4797 case AMDGPU_IRQ_STATE_ENABLE: 4798 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4799 cp_int_cntl = 4800 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4801 TIME_STAMP_INT_ENABLE, 1); 4802 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4803 break; 4804 default: 4805 break; 4806 } 4807 } 4808 4809 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4810 int me, int pipe, 4811 enum amdgpu_interrupt_state state) 4812 { 4813 u32 mec_int_cntl, mec_int_cntl_reg; 4814 4815 /* 4816 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4817 * handles the setting of interrupts for this specific pipe. All other 4818 * pipes' interrupts are set by amdkfd. 4819 */ 4820 4821 if (me == 1) { 4822 switch (pipe) { 4823 case 0: 4824 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4825 break; 4826 default: 4827 DRM_DEBUG("invalid pipe %d\n", pipe); 4828 return; 4829 } 4830 } else { 4831 DRM_DEBUG("invalid me %d\n", me); 4832 return; 4833 } 4834 4835 switch (state) { 4836 case AMDGPU_IRQ_STATE_DISABLE: 4837 mec_int_cntl = RREG32(mec_int_cntl_reg); 4838 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4839 TIME_STAMP_INT_ENABLE, 0); 4840 WREG32(mec_int_cntl_reg, mec_int_cntl); 4841 break; 4842 case AMDGPU_IRQ_STATE_ENABLE: 4843 mec_int_cntl = RREG32(mec_int_cntl_reg); 4844 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4845 TIME_STAMP_INT_ENABLE, 1); 4846 WREG32(mec_int_cntl_reg, mec_int_cntl); 4847 break; 4848 default: 4849 break; 4850 } 4851 } 4852 4853 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4854 struct amdgpu_irq_src *source, 4855 unsigned type, 4856 enum amdgpu_interrupt_state state) 4857 { 4858 u32 cp_int_cntl; 4859 4860 switch (state) { 4861 case AMDGPU_IRQ_STATE_DISABLE: 4862 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4863 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4864 PRIV_REG_INT_ENABLE, 0); 4865 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4866 break; 4867 case AMDGPU_IRQ_STATE_ENABLE: 4868 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4869 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4870 PRIV_REG_INT_ENABLE, 0); 4871 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4872 break; 4873 default: 4874 break; 4875 } 4876 4877 return 0; 4878 } 4879 4880 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4881 struct amdgpu_irq_src *source, 4882 unsigned type, 4883 enum amdgpu_interrupt_state state) 4884 { 4885 u32 cp_int_cntl; 4886 4887 switch (state) { 4888 case AMDGPU_IRQ_STATE_DISABLE: 4889 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4890 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4891 PRIV_INSTR_INT_ENABLE, 0); 4892 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4893 break; 4894 case AMDGPU_IRQ_STATE_ENABLE: 4895 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4897 PRIV_INSTR_INT_ENABLE, 1); 4898 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4899 break; 4900 default: 4901 break; 4902 } 4903 4904 return 0; 4905 } 4906 4907 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4908 struct amdgpu_irq_src *src, 4909 unsigned type, 4910 enum amdgpu_interrupt_state state) 4911 { 4912 switch (type) { 4913 case AMDGPU_CP_IRQ_GFX_EOP: 4914 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); 4915 break; 4916 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4917 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4918 break; 4919 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4920 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4921 break; 4922 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4923 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4924 break; 4925 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4926 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4927 break; 4928 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4929 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4930 break; 4931 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4932 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4933 break; 4934 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4935 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4936 break; 4937 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4938 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4939 break; 4940 default: 4941 break; 4942 } 4943 return 0; 4944 } 4945 4946 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, 4947 struct amdgpu_irq_src *source, 4948 struct amdgpu_iv_entry *entry) 4949 { 4950 int i; 4951 u8 me_id, pipe_id, queue_id; 4952 struct amdgpu_ring *ring; 4953 4954 DRM_DEBUG("IH: CP EOP\n"); 4955 me_id = (entry->ring_id & 0x0c) >> 2; 4956 pipe_id = (entry->ring_id & 0x03) >> 0; 4957 queue_id = (entry->ring_id & 0x70) >> 4; 4958 4959 switch (me_id) { 4960 case 0: 4961 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4962 break; 4963 case 1: 4964 case 2: 4965 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4966 ring = &adev->gfx.compute_ring[i]; 4967 /* Per-queue interrupt is supported for MEC starting from VI. 4968 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4969 */ 4970 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4971 amdgpu_fence_process(ring); 4972 } 4973 break; 4974 } 4975 return 0; 4976 } 4977 4978 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, 4979 struct amdgpu_irq_src *source, 4980 struct amdgpu_iv_entry *entry) 4981 { 4982 DRM_ERROR("Illegal register access in command stream\n"); 4983 schedule_work(&adev->reset_work); 4984 return 0; 4985 } 4986 4987 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, 4988 struct amdgpu_irq_src *source, 4989 struct amdgpu_iv_entry *entry) 4990 { 4991 DRM_ERROR("Illegal instruction in command stream\n"); 4992 schedule_work(&adev->reset_work); 4993 return 0; 4994 } 4995 4996 const struct amd_ip_funcs gfx_v8_0_ip_funcs = { 4997 .early_init = gfx_v8_0_early_init, 4998 .late_init = NULL, 4999 .sw_init = gfx_v8_0_sw_init, 5000 .sw_fini = gfx_v8_0_sw_fini, 5001 .hw_init = gfx_v8_0_hw_init, 5002 .hw_fini = gfx_v8_0_hw_fini, 5003 .suspend = gfx_v8_0_suspend, 5004 .resume = gfx_v8_0_resume, 5005 .is_idle = gfx_v8_0_is_idle, 5006 .wait_for_idle = gfx_v8_0_wait_for_idle, 5007 .soft_reset = gfx_v8_0_soft_reset, 5008 .print_status = gfx_v8_0_print_status, 5009 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 5010 .set_powergating_state = gfx_v8_0_set_powergating_state, 5011 }; 5012 5013 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 5014 .get_rptr = gfx_v8_0_ring_get_rptr_gfx, 5015 .get_wptr = gfx_v8_0_ring_get_wptr_gfx, 5016 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 5017 .parse_cs = NULL, 5018 .emit_ib = gfx_v8_0_ring_emit_ib_gfx, 5019 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 5020 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 5021 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 5022 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 5023 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 5024 .test_ring = gfx_v8_0_ring_test_ring, 5025 .test_ib = gfx_v8_0_ring_test_ib, 5026 .insert_nop = amdgpu_ring_insert_nop, 5027 }; 5028 5029 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 5030 .get_rptr = gfx_v8_0_ring_get_rptr_compute, 5031 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 5032 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 5033 .parse_cs = NULL, 5034 .emit_ib = gfx_v8_0_ring_emit_ib_compute, 5035 .emit_fence = gfx_v8_0_ring_emit_fence_compute, 5036 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 5037 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 5038 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 5039 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 5040 .test_ring = gfx_v8_0_ring_test_ring, 5041 .test_ib = gfx_v8_0_ring_test_ib, 5042 .insert_nop = amdgpu_ring_insert_nop, 5043 }; 5044 5045 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) 5046 { 5047 int i; 5048 5049 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5050 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; 5051 5052 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5053 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; 5054 } 5055 5056 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { 5057 .set = gfx_v8_0_set_eop_interrupt_state, 5058 .process = gfx_v8_0_eop_irq, 5059 }; 5060 5061 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { 5062 .set = gfx_v8_0_set_priv_reg_fault_state, 5063 .process = gfx_v8_0_priv_reg_irq, 5064 }; 5065 5066 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { 5067 .set = gfx_v8_0_set_priv_inst_fault_state, 5068 .process = gfx_v8_0_priv_inst_irq, 5069 }; 5070 5071 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) 5072 { 5073 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5074 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; 5075 5076 adev->gfx.priv_reg_irq.num_types = 1; 5077 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; 5078 5079 adev->gfx.priv_inst_irq.num_types = 1; 5080 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; 5081 } 5082 5083 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) 5084 { 5085 /* init asci gds info */ 5086 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 5087 adev->gds.gws.total_size = 64; 5088 adev->gds.oa.total_size = 16; 5089 5090 if (adev->gds.mem.total_size == 64 * 1024) { 5091 adev->gds.mem.gfx_partition_size = 4096; 5092 adev->gds.mem.cs_partition_size = 4096; 5093 5094 adev->gds.gws.gfx_partition_size = 4; 5095 adev->gds.gws.cs_partition_size = 4; 5096 5097 adev->gds.oa.gfx_partition_size = 4; 5098 adev->gds.oa.cs_partition_size = 1; 5099 } else { 5100 adev->gds.mem.gfx_partition_size = 1024; 5101 adev->gds.mem.cs_partition_size = 1024; 5102 5103 adev->gds.gws.gfx_partition_size = 16; 5104 adev->gds.gws.cs_partition_size = 16; 5105 5106 adev->gds.oa.gfx_partition_size = 4; 5107 adev->gds.oa.cs_partition_size = 4; 5108 } 5109 } 5110 5111 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev, 5112 u32 se, u32 sh) 5113 { 5114 u32 mask = 0, tmp, tmp1; 5115 int i; 5116 5117 gfx_v8_0_select_se_sh(adev, se, sh); 5118 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 5119 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 5120 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 5121 5122 tmp &= 0xffff0000; 5123 5124 tmp |= tmp1; 5125 tmp >>= 16; 5126 5127 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { 5128 mask <<= 1; 5129 mask |= 1; 5130 } 5131 5132 return (~tmp) & mask; 5133 } 5134 5135 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, 5136 struct amdgpu_cu_info *cu_info) 5137 { 5138 int i, j, k, counter, active_cu_number = 0; 5139 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5140 5141 if (!adev || !cu_info) 5142 return -EINVAL; 5143 5144 mutex_lock(&adev->grbm_idx_mutex); 5145 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5146 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5147 mask = 1; 5148 ao_bitmap = 0; 5149 counter = 0; 5150 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j); 5151 cu_info->bitmap[i][j] = bitmap; 5152 5153 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5154 if (bitmap & mask) { 5155 if (counter < 2) 5156 ao_bitmap |= mask; 5157 counter ++; 5158 } 5159 mask <<= 1; 5160 } 5161 active_cu_number += counter; 5162 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5163 } 5164 } 5165 5166 cu_info->number = active_cu_number; 5167 cu_info->ao_cu_mask = ao_cu_mask; 5168 mutex_unlock(&adev->grbm_idx_mutex); 5169 return 0; 5170 } 5171