1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "amdgpu_ring.h" 33 #include "vi.h" 34 #include "vi_structs.h" 35 #include "vid.h" 36 #include "amdgpu_ucode.h" 37 #include "amdgpu_atombios.h" 38 #include "atombios_i2c.h" 39 #include "clearstate_vi.h" 40 41 #include "gmc/gmc_8_2_d.h" 42 #include "gmc/gmc_8_2_sh_mask.h" 43 44 #include "oss/oss_3_0_d.h" 45 #include "oss/oss_3_0_sh_mask.h" 46 47 #include "bif/bif_5_0_d.h" 48 #include "bif/bif_5_0_sh_mask.h" 49 #include "gca/gfx_8_0_d.h" 50 #include "gca/gfx_8_0_enum.h" 51 #include "gca/gfx_8_0_sh_mask.h" 52 53 #include "dce/dce_10_0_d.h" 54 #include "dce/dce_10_0_sh_mask.h" 55 56 #include "smu/smu_7_1_3_d.h" 57 58 #include "ivsrcid/ivsrcid_vislands30.h" 59 60 #define GFX8_NUM_GFX_RINGS 1 61 #define GFX8_MEC_HPD_SIZE 4096 62 63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 67 68 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 69 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 70 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 71 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) 72 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 73 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) 74 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) 75 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) 76 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) 77 78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L 79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L 80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L 81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L 82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L 83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L 84 85 /* BPM SERDES CMD */ 86 #define SET_BPM_SERDES_CMD 1 87 #define CLE_BPM_SERDES_CMD 0 88 89 /* BPM Register Address*/ 90 enum { 91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */ 92 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */ 93 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */ 94 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */ 95 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */ 96 BPM_REG_FGCG_MAX 97 }; 98 99 #define RLC_FormatDirectRegListLength 14 100 101 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); 102 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); 103 MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); 104 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); 105 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); 106 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); 107 108 MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); 109 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); 110 MODULE_FIRMWARE("amdgpu/stoney_me.bin"); 111 MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); 112 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); 113 114 MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); 115 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); 116 MODULE_FIRMWARE("amdgpu/tonga_me.bin"); 117 MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); 118 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); 119 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/topaz_me.bin"); 124 MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); 126 127 MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); 128 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); 129 MODULE_FIRMWARE("amdgpu/fiji_me.bin"); 130 MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); 131 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); 132 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); 133 134 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); 135 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin"); 136 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); 137 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin"); 138 MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); 139 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin"); 140 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); 141 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin"); 142 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); 143 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin"); 144 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); 145 146 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); 147 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin"); 148 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); 149 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin"); 150 MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); 151 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin"); 152 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); 153 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin"); 154 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); 155 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin"); 156 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); 157 158 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin"); 159 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin"); 160 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin"); 161 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin"); 162 MODULE_FIRMWARE("amdgpu/polaris12_me.bin"); 163 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin"); 164 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin"); 165 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin"); 166 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin"); 167 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin"); 168 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin"); 169 170 MODULE_FIRMWARE("amdgpu/vegam_ce.bin"); 171 MODULE_FIRMWARE("amdgpu/vegam_pfp.bin"); 172 MODULE_FIRMWARE("amdgpu/vegam_me.bin"); 173 MODULE_FIRMWARE("amdgpu/vegam_mec.bin"); 174 MODULE_FIRMWARE("amdgpu/vegam_mec2.bin"); 175 MODULE_FIRMWARE("amdgpu/vegam_rlc.bin"); 176 177 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 178 { 179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 180 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 181 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 182 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 183 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 184 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 185 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 186 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 187 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 188 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 189 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 190 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 191 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 192 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 193 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 194 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 195 }; 196 197 static const u32 golden_settings_tonga_a11[] = 198 { 199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, 200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 201 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 202 mmGB_GPU_ID, 0x0000000f, 0x00000000, 203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 209 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, 212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 215 }; 216 217 static const u32 tonga_golden_common_all[] = 218 { 219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 227 }; 228 229 static const u32 tonga_mgcg_cgcg_init[] = 230 { 231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 306 }; 307 308 static const u32 golden_settings_vegam_a11[] = 309 { 310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208, 311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000, 312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 313 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a, 317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e, 318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, 320 mmSQ_CONFIG, 0x07f80000, 0x01180000, 321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 322 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 327 }; 328 329 static const u32 vegam_golden_common_all[] = 330 { 331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 337 }; 338 339 static const u32 golden_settings_polaris11_a11[] = 340 { 341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208, 342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000, 343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 344 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, 348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, 351 mmSQ_CONFIG, 0x07f80000, 0x01180000, 352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 353 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 358 }; 359 360 static const u32 polaris11_golden_common_all[] = 361 { 362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002, 364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 368 }; 369 370 static const u32 golden_settings_polaris10_a11[] = 371 { 372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, 373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208, 374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000, 375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 376 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, 380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a, 381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, 383 mmSQ_CONFIG, 0x07f80000, 0x07180000, 384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 385 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 389 }; 390 391 static const u32 polaris10_golden_common_all[] = 392 { 393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 401 }; 402 403 static const u32 fiji_golden_common_all[] = 404 { 405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, 407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, 408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, 415 }; 416 417 static const u32 golden_settings_fiji_a10[] = 418 { 419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 420 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 426 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, 429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 430 }; 431 432 static const u32 fiji_mgcg_cgcg_init[] = 433 { 434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 469 }; 470 471 static const u32 golden_settings_iceland_a11[] = 472 { 473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 474 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 475 mmDB_DEBUG3, 0xc0000000, 0xc0000000, 476 mmGB_GPU_ID, 0x0000000f, 0x00000000, 477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, 480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 484 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, 489 }; 490 491 static const u32 iceland_golden_common_all[] = 492 { 493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 501 }; 502 503 static const u32 iceland_mgcg_cgcg_init[] = 504 { 505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, 510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, 511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, 512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, 528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 569 }; 570 571 static const u32 cz_golden_settings_a11[] = 572 { 573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 574 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 575 mmGB_GPU_ID, 0x0000000f, 0x00000000, 576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, 577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000, 581 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, 584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 585 }; 586 587 static const u32 cz_golden_common_all[] = 588 { 589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 597 }; 598 599 static const u32 cz_mgcg_cgcg_init[] = 600 { 601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, 608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 676 }; 677 678 static const u32 stoney_golden_settings_a11[] = 679 { 680 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 681 mmGB_GPU_ID, 0x0000000f, 0x00000000, 682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 686 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, 689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, 690 }; 691 692 static const u32 stoney_golden_common_all[] = 693 { 694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, 696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, 698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 702 }; 703 704 static const u32 stoney_mgcg_cgcg_init[] = 705 { 706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 711 }; 712 713 714 static const char * const sq_edc_source_names[] = { 715 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred", 716 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch", 717 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return", 718 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR", 719 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS", 720 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS", 721 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA", 722 }; 723 724 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); 725 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); 726 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); 727 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); 728 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); 729 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); 730 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring); 731 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring); 732 733 #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL 734 #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L 735 736 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) 737 { 738 uint32_t data; 739 740 switch (adev->asic_type) { 741 case CHIP_TOPAZ: 742 amdgpu_device_program_register_sequence(adev, 743 iceland_mgcg_cgcg_init, 744 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 745 amdgpu_device_program_register_sequence(adev, 746 golden_settings_iceland_a11, 747 ARRAY_SIZE(golden_settings_iceland_a11)); 748 amdgpu_device_program_register_sequence(adev, 749 iceland_golden_common_all, 750 ARRAY_SIZE(iceland_golden_common_all)); 751 break; 752 case CHIP_FIJI: 753 amdgpu_device_program_register_sequence(adev, 754 fiji_mgcg_cgcg_init, 755 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 756 amdgpu_device_program_register_sequence(adev, 757 golden_settings_fiji_a10, 758 ARRAY_SIZE(golden_settings_fiji_a10)); 759 amdgpu_device_program_register_sequence(adev, 760 fiji_golden_common_all, 761 ARRAY_SIZE(fiji_golden_common_all)); 762 break; 763 764 case CHIP_TONGA: 765 amdgpu_device_program_register_sequence(adev, 766 tonga_mgcg_cgcg_init, 767 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 768 amdgpu_device_program_register_sequence(adev, 769 golden_settings_tonga_a11, 770 ARRAY_SIZE(golden_settings_tonga_a11)); 771 amdgpu_device_program_register_sequence(adev, 772 tonga_golden_common_all, 773 ARRAY_SIZE(tonga_golden_common_all)); 774 break; 775 case CHIP_VEGAM: 776 amdgpu_device_program_register_sequence(adev, 777 golden_settings_vegam_a11, 778 ARRAY_SIZE(golden_settings_vegam_a11)); 779 amdgpu_device_program_register_sequence(adev, 780 vegam_golden_common_all, 781 ARRAY_SIZE(vegam_golden_common_all)); 782 break; 783 case CHIP_POLARIS11: 784 case CHIP_POLARIS12: 785 amdgpu_device_program_register_sequence(adev, 786 golden_settings_polaris11_a11, 787 ARRAY_SIZE(golden_settings_polaris11_a11)); 788 amdgpu_device_program_register_sequence(adev, 789 polaris11_golden_common_all, 790 ARRAY_SIZE(polaris11_golden_common_all)); 791 break; 792 case CHIP_POLARIS10: 793 amdgpu_device_program_register_sequence(adev, 794 golden_settings_polaris10_a11, 795 ARRAY_SIZE(golden_settings_polaris10_a11)); 796 amdgpu_device_program_register_sequence(adev, 797 polaris10_golden_common_all, 798 ARRAY_SIZE(polaris10_golden_common_all)); 799 data = RREG32_SMC(ixCG_ACLK_CNTL); 800 data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK; 801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT; 802 WREG32_SMC(ixCG_ACLK_CNTL, data); 803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) && 804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || 805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || 806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) { 807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); 808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); 809 } 810 break; 811 case CHIP_CARRIZO: 812 amdgpu_device_program_register_sequence(adev, 813 cz_mgcg_cgcg_init, 814 ARRAY_SIZE(cz_mgcg_cgcg_init)); 815 amdgpu_device_program_register_sequence(adev, 816 cz_golden_settings_a11, 817 ARRAY_SIZE(cz_golden_settings_a11)); 818 amdgpu_device_program_register_sequence(adev, 819 cz_golden_common_all, 820 ARRAY_SIZE(cz_golden_common_all)); 821 break; 822 case CHIP_STONEY: 823 amdgpu_device_program_register_sequence(adev, 824 stoney_mgcg_cgcg_init, 825 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 826 amdgpu_device_program_register_sequence(adev, 827 stoney_golden_settings_a11, 828 ARRAY_SIZE(stoney_golden_settings_a11)); 829 amdgpu_device_program_register_sequence(adev, 830 stoney_golden_common_all, 831 ARRAY_SIZE(stoney_golden_common_all)); 832 break; 833 default: 834 break; 835 } 836 } 837 838 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) 839 { 840 struct amdgpu_device *adev = ring->adev; 841 uint32_t tmp = 0; 842 unsigned i; 843 int r; 844 845 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 846 r = amdgpu_ring_alloc(ring, 3); 847 if (r) 848 return r; 849 850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); 852 amdgpu_ring_write(ring, 0xDEADBEEF); 853 amdgpu_ring_commit(ring); 854 855 for (i = 0; i < adev->usec_timeout; i++) { 856 tmp = RREG32(mmSCRATCH_REG0); 857 if (tmp == 0xDEADBEEF) 858 break; 859 udelay(1); 860 } 861 862 if (i >= adev->usec_timeout) 863 r = -ETIMEDOUT; 864 865 return r; 866 } 867 868 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 869 { 870 struct amdgpu_device *adev = ring->adev; 871 struct amdgpu_ib ib; 872 struct dma_fence *f = NULL; 873 874 unsigned int index; 875 uint64_t gpu_addr; 876 uint32_t tmp; 877 long r; 878 879 r = amdgpu_device_wb_get(adev, &index); 880 if (r) 881 return r; 882 883 gpu_addr = adev->wb.gpu_addr + (index * 4); 884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 885 memset(&ib, 0, sizeof(ib)); 886 887 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 888 if (r) 889 goto err1; 890 891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 893 ib.ptr[2] = lower_32_bits(gpu_addr); 894 ib.ptr[3] = upper_32_bits(gpu_addr); 895 ib.ptr[4] = 0xDEADBEEF; 896 ib.length_dw = 5; 897 898 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 899 if (r) 900 goto err2; 901 902 r = dma_fence_wait_timeout(f, false, timeout); 903 if (r == 0) { 904 r = -ETIMEDOUT; 905 goto err2; 906 } else if (r < 0) { 907 goto err2; 908 } 909 910 tmp = adev->wb.wb[index]; 911 if (tmp == 0xDEADBEEF) 912 r = 0; 913 else 914 r = -EINVAL; 915 916 err2: 917 amdgpu_ib_free(adev, &ib, NULL); 918 dma_fence_put(f); 919 err1: 920 amdgpu_device_wb_free(adev, index); 921 return r; 922 } 923 924 925 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) 926 { 927 amdgpu_ucode_release(&adev->gfx.pfp_fw); 928 amdgpu_ucode_release(&adev->gfx.me_fw); 929 amdgpu_ucode_release(&adev->gfx.ce_fw); 930 amdgpu_ucode_release(&adev->gfx.rlc_fw); 931 amdgpu_ucode_release(&adev->gfx.mec_fw); 932 if ((adev->asic_type != CHIP_STONEY) && 933 (adev->asic_type != CHIP_TOPAZ)) 934 amdgpu_ucode_release(&adev->gfx.mec2_fw); 935 936 kfree(adev->gfx.rlc.register_list_format); 937 } 938 939 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 940 { 941 const char *chip_name; 942 int err; 943 struct amdgpu_firmware_info *info = NULL; 944 const struct common_firmware_header *header = NULL; 945 const struct gfx_firmware_header_v1_0 *cp_hdr; 946 const struct rlc_firmware_header_v2_0 *rlc_hdr; 947 unsigned int *tmp = NULL, i; 948 949 DRM_DEBUG("\n"); 950 951 switch (adev->asic_type) { 952 case CHIP_TOPAZ: 953 chip_name = "topaz"; 954 break; 955 case CHIP_TONGA: 956 chip_name = "tonga"; 957 break; 958 case CHIP_CARRIZO: 959 chip_name = "carrizo"; 960 break; 961 case CHIP_FIJI: 962 chip_name = "fiji"; 963 break; 964 case CHIP_STONEY: 965 chip_name = "stoney"; 966 break; 967 case CHIP_POLARIS10: 968 chip_name = "polaris10"; 969 break; 970 case CHIP_POLARIS11: 971 chip_name = "polaris11"; 972 break; 973 case CHIP_POLARIS12: 974 chip_name = "polaris12"; 975 break; 976 case CHIP_VEGAM: 977 chip_name = "vegam"; 978 break; 979 default: 980 BUG(); 981 } 982 983 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 984 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 985 "amdgpu/%s_pfp_2.bin", chip_name); 986 if (err == -ENODEV) { 987 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 988 "amdgpu/%s_pfp.bin", chip_name); 989 } 990 } else { 991 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 992 "amdgpu/%s_pfp.bin", chip_name); 993 } 994 if (err) 995 goto out; 996 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 997 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 998 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 999 1000 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1001 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 1002 "amdgpu/%s_me_2.bin", chip_name); 1003 if (err == -ENODEV) { 1004 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 1005 "amdgpu/%s_me.bin", chip_name); 1006 } 1007 } else { 1008 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 1009 "amdgpu/%s_me.bin", chip_name); 1010 } 1011 if (err) 1012 goto out; 1013 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1014 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1015 1016 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1017 1018 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1019 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 1020 "amdgpu/%s_ce_2.bin", chip_name); 1021 if (err == -ENODEV) { 1022 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 1023 "amdgpu/%s_ce.bin", chip_name); 1024 } 1025 } else { 1026 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 1027 "amdgpu/%s_ce.bin", chip_name); 1028 } 1029 if (err) 1030 goto out; 1031 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1032 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1033 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1034 1035 /* 1036 * Support for MCBP/Virtualization in combination with chained IBs is 1037 * formal released on feature version #46 1038 */ 1039 if (adev->gfx.ce_feature_version >= 46 && 1040 adev->gfx.pfp_feature_version >= 46) { 1041 adev->virt.chained_ib_support = true; 1042 DRM_INFO("Chained IB support enabled!\n"); 1043 } else 1044 adev->virt.chained_ib_support = false; 1045 1046 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 1047 "amdgpu/%s_rlc.bin", chip_name); 1048 if (err) 1049 goto out; 1050 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1051 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 1052 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 1053 1054 adev->gfx.rlc.save_and_restore_offset = 1055 le32_to_cpu(rlc_hdr->save_and_restore_offset); 1056 adev->gfx.rlc.clear_state_descriptor_offset = 1057 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 1058 adev->gfx.rlc.avail_scratch_ram_locations = 1059 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 1060 adev->gfx.rlc.reg_restore_list_size = 1061 le32_to_cpu(rlc_hdr->reg_restore_list_size); 1062 adev->gfx.rlc.reg_list_format_start = 1063 le32_to_cpu(rlc_hdr->reg_list_format_start); 1064 adev->gfx.rlc.reg_list_format_separate_start = 1065 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 1066 adev->gfx.rlc.starting_offsets_start = 1067 le32_to_cpu(rlc_hdr->starting_offsets_start); 1068 adev->gfx.rlc.reg_list_format_size_bytes = 1069 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 1070 adev->gfx.rlc.reg_list_size_bytes = 1071 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 1072 1073 adev->gfx.rlc.register_list_format = 1074 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 1075 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 1076 1077 if (!adev->gfx.rlc.register_list_format) { 1078 err = -ENOMEM; 1079 goto out; 1080 } 1081 1082 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1083 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 1084 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 1085 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 1086 1087 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 1088 1089 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1090 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 1091 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 1092 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 1093 1094 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1095 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 1096 "amdgpu/%s_mec_2.bin", chip_name); 1097 if (err == -ENODEV) { 1098 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 1099 "amdgpu/%s_mec.bin", chip_name); 1100 } 1101 } else { 1102 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 1103 "amdgpu/%s_mec.bin", chip_name); 1104 } 1105 if (err) 1106 goto out; 1107 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1108 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1109 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1110 1111 if ((adev->asic_type != CHIP_STONEY) && 1112 (adev->asic_type != CHIP_TOPAZ)) { 1113 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1114 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 1115 "amdgpu/%s_mec2_2.bin", chip_name); 1116 if (err == -ENODEV) { 1117 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 1118 "amdgpu/%s_mec2.bin", chip_name); 1119 } 1120 } else { 1121 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 1122 "amdgpu/%s_mec2.bin", chip_name); 1123 } 1124 if (!err) { 1125 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1126 adev->gfx.mec2_fw->data; 1127 adev->gfx.mec2_fw_version = 1128 le32_to_cpu(cp_hdr->header.ucode_version); 1129 adev->gfx.mec2_feature_version = 1130 le32_to_cpu(cp_hdr->ucode_feature_version); 1131 } else { 1132 err = 0; 1133 adev->gfx.mec2_fw = NULL; 1134 } 1135 } 1136 1137 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 1138 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 1139 info->fw = adev->gfx.pfp_fw; 1140 header = (const struct common_firmware_header *)info->fw->data; 1141 adev->firmware.fw_size += 1142 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1143 1144 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 1145 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 1146 info->fw = adev->gfx.me_fw; 1147 header = (const struct common_firmware_header *)info->fw->data; 1148 adev->firmware.fw_size += 1149 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1150 1151 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 1152 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 1153 info->fw = adev->gfx.ce_fw; 1154 header = (const struct common_firmware_header *)info->fw->data; 1155 adev->firmware.fw_size += 1156 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1157 1158 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 1159 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 1160 info->fw = adev->gfx.rlc_fw; 1161 header = (const struct common_firmware_header *)info->fw->data; 1162 adev->firmware.fw_size += 1163 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1164 1165 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 1166 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 1167 info->fw = adev->gfx.mec_fw; 1168 header = (const struct common_firmware_header *)info->fw->data; 1169 adev->firmware.fw_size += 1170 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1171 1172 /* we need account JT in */ 1173 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1174 adev->firmware.fw_size += 1175 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1176 1177 if (amdgpu_sriov_vf(adev)) { 1178 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE]; 1179 info->ucode_id = AMDGPU_UCODE_ID_STORAGE; 1180 info->fw = adev->gfx.mec_fw; 1181 adev->firmware.fw_size += 1182 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE); 1183 } 1184 1185 if (adev->gfx.mec2_fw) { 1186 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 1187 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 1188 info->fw = adev->gfx.mec2_fw; 1189 header = (const struct common_firmware_header *)info->fw->data; 1190 adev->firmware.fw_size += 1191 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1192 } 1193 1194 out: 1195 if (err) { 1196 dev_err(adev->dev, "gfx8: Failed to load firmware %s gfx firmware\n", chip_name); 1197 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1198 amdgpu_ucode_release(&adev->gfx.me_fw); 1199 amdgpu_ucode_release(&adev->gfx.ce_fw); 1200 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1201 amdgpu_ucode_release(&adev->gfx.mec_fw); 1202 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1203 } 1204 return err; 1205 } 1206 1207 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, 1208 volatile u32 *buffer) 1209 { 1210 u32 count = 0, i; 1211 const struct cs_section_def *sect = NULL; 1212 const struct cs_extent_def *ext = NULL; 1213 1214 if (adev->gfx.rlc.cs_data == NULL) 1215 return; 1216 if (buffer == NULL) 1217 return; 1218 1219 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1220 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1221 1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1223 buffer[count++] = cpu_to_le32(0x80000000); 1224 buffer[count++] = cpu_to_le32(0x80000000); 1225 1226 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1227 for (ext = sect->section; ext->extent != NULL; ++ext) { 1228 if (sect->id == SECT_CONTEXT) { 1229 buffer[count++] = 1230 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1231 buffer[count++] = cpu_to_le32(ext->reg_index - 1232 PACKET3_SET_CONTEXT_REG_START); 1233 for (i = 0; i < ext->reg_count; i++) 1234 buffer[count++] = cpu_to_le32(ext->extent[i]); 1235 } else { 1236 return; 1237 } 1238 } 1239 } 1240 1241 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1242 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - 1243 PACKET3_SET_CONTEXT_REG_START); 1244 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 1245 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); 1246 1247 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1248 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1249 1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1251 buffer[count++] = cpu_to_le32(0); 1252 } 1253 1254 static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev) 1255 { 1256 if (adev->asic_type == CHIP_CARRIZO) 1257 return 5; 1258 else 1259 return 4; 1260 } 1261 1262 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 1263 { 1264 const struct cs_section_def *cs_data; 1265 int r; 1266 1267 adev->gfx.rlc.cs_data = vi_cs_data; 1268 1269 cs_data = adev->gfx.rlc.cs_data; 1270 1271 if (cs_data) { 1272 /* init clear state block */ 1273 r = amdgpu_gfx_rlc_init_csb(adev); 1274 if (r) 1275 return r; 1276 } 1277 1278 if ((adev->asic_type == CHIP_CARRIZO) || 1279 (adev->asic_type == CHIP_STONEY)) { 1280 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1281 r = amdgpu_gfx_rlc_init_cpt(adev); 1282 if (r) 1283 return r; 1284 } 1285 1286 /* init spm vmid with 0xf */ 1287 if (adev->gfx.rlc.funcs->update_spm_vmid) 1288 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1289 1290 return 0; 1291 } 1292 1293 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) 1294 { 1295 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1296 } 1297 1298 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 1299 { 1300 int r; 1301 u32 *hpd; 1302 size_t mec_hpd_size; 1303 1304 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1305 1306 /* take ownership of the relevant compute queues */ 1307 amdgpu_gfx_compute_queue_acquire(adev); 1308 1309 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; 1310 if (mec_hpd_size) { 1311 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1312 AMDGPU_GEM_DOMAIN_VRAM | 1313 AMDGPU_GEM_DOMAIN_GTT, 1314 &adev->gfx.mec.hpd_eop_obj, 1315 &adev->gfx.mec.hpd_eop_gpu_addr, 1316 (void **)&hpd); 1317 if (r) { 1318 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1319 return r; 1320 } 1321 1322 memset(hpd, 0, mec_hpd_size); 1323 1324 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1325 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static const u32 vgpr_init_compute_shader[] = 1332 { 1333 0x7e000209, 0x7e020208, 1334 0x7e040207, 0x7e060206, 1335 0x7e080205, 0x7e0a0204, 1336 0x7e0c0203, 0x7e0e0202, 1337 0x7e100201, 0x7e120200, 1338 0x7e140209, 0x7e160208, 1339 0x7e180207, 0x7e1a0206, 1340 0x7e1c0205, 0x7e1e0204, 1341 0x7e200203, 0x7e220202, 1342 0x7e240201, 0x7e260200, 1343 0x7e280209, 0x7e2a0208, 1344 0x7e2c0207, 0x7e2e0206, 1345 0x7e300205, 0x7e320204, 1346 0x7e340203, 0x7e360202, 1347 0x7e380201, 0x7e3a0200, 1348 0x7e3c0209, 0x7e3e0208, 1349 0x7e400207, 0x7e420206, 1350 0x7e440205, 0x7e460204, 1351 0x7e480203, 0x7e4a0202, 1352 0x7e4c0201, 0x7e4e0200, 1353 0x7e500209, 0x7e520208, 1354 0x7e540207, 0x7e560206, 1355 0x7e580205, 0x7e5a0204, 1356 0x7e5c0203, 0x7e5e0202, 1357 0x7e600201, 0x7e620200, 1358 0x7e640209, 0x7e660208, 1359 0x7e680207, 0x7e6a0206, 1360 0x7e6c0205, 0x7e6e0204, 1361 0x7e700203, 0x7e720202, 1362 0x7e740201, 0x7e760200, 1363 0x7e780209, 0x7e7a0208, 1364 0x7e7c0207, 0x7e7e0206, 1365 0xbf8a0000, 0xbf810000, 1366 }; 1367 1368 static const u32 sgpr_init_compute_shader[] = 1369 { 1370 0xbe8a0100, 0xbe8c0102, 1371 0xbe8e0104, 0xbe900106, 1372 0xbe920108, 0xbe940100, 1373 0xbe960102, 0xbe980104, 1374 0xbe9a0106, 0xbe9c0108, 1375 0xbe9e0100, 0xbea00102, 1376 0xbea20104, 0xbea40106, 1377 0xbea60108, 0xbea80100, 1378 0xbeaa0102, 0xbeac0104, 1379 0xbeae0106, 0xbeb00108, 1380 0xbeb20100, 0xbeb40102, 1381 0xbeb60104, 0xbeb80106, 1382 0xbeba0108, 0xbebc0100, 1383 0xbebe0102, 0xbec00104, 1384 0xbec20106, 0xbec40108, 1385 0xbec60100, 0xbec80102, 1386 0xbee60004, 0xbee70005, 1387 0xbeea0006, 0xbeeb0007, 1388 0xbee80008, 0xbee90009, 1389 0xbefc0000, 0xbf8a0000, 1390 0xbf810000, 0x00000000, 1391 }; 1392 1393 static const u32 vgpr_init_regs[] = 1394 { 1395 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, 1396 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ 1397 mmCOMPUTE_NUM_THREAD_X, 256*4, 1398 mmCOMPUTE_NUM_THREAD_Y, 1, 1399 mmCOMPUTE_NUM_THREAD_Z, 1, 1400 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */ 1401 mmCOMPUTE_PGM_RSRC2, 20, 1402 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1403 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1404 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1405 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1406 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1407 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1408 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1409 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1410 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1411 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1412 }; 1413 1414 static const u32 sgpr1_init_regs[] = 1415 { 1416 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, 1417 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ 1418 mmCOMPUTE_NUM_THREAD_X, 256*5, 1419 mmCOMPUTE_NUM_THREAD_Y, 1, 1420 mmCOMPUTE_NUM_THREAD_Z, 1, 1421 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ 1422 mmCOMPUTE_PGM_RSRC2, 20, 1423 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1424 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1425 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1426 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1427 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1428 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1429 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1430 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1431 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1432 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1433 }; 1434 1435 static const u32 sgpr2_init_regs[] = 1436 { 1437 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0, 1438 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, 1439 mmCOMPUTE_NUM_THREAD_X, 256*5, 1440 mmCOMPUTE_NUM_THREAD_Y, 1, 1441 mmCOMPUTE_NUM_THREAD_Z, 1, 1442 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ 1443 mmCOMPUTE_PGM_RSRC2, 20, 1444 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1445 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1446 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1447 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1448 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1449 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1450 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1451 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1452 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1453 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1454 }; 1455 1456 static const u32 sec_ded_counter_registers[] = 1457 { 1458 mmCPC_EDC_ATC_CNT, 1459 mmCPC_EDC_SCRATCH_CNT, 1460 mmCPC_EDC_UCODE_CNT, 1461 mmCPF_EDC_ATC_CNT, 1462 mmCPF_EDC_ROQ_CNT, 1463 mmCPF_EDC_TAG_CNT, 1464 mmCPG_EDC_ATC_CNT, 1465 mmCPG_EDC_DMA_CNT, 1466 mmCPG_EDC_TAG_CNT, 1467 mmDC_EDC_CSINVOC_CNT, 1468 mmDC_EDC_RESTORE_CNT, 1469 mmDC_EDC_STATE_CNT, 1470 mmGDS_EDC_CNT, 1471 mmGDS_EDC_GRBM_CNT, 1472 mmGDS_EDC_OA_DED, 1473 mmSPI_EDC_CNT, 1474 mmSQC_ATC_EDC_GATCL1_CNT, 1475 mmSQC_EDC_CNT, 1476 mmSQ_EDC_DED_CNT, 1477 mmSQ_EDC_INFO, 1478 mmSQ_EDC_SEC_CNT, 1479 mmTCC_EDC_CNT, 1480 mmTCP_ATC_EDC_GATCL1_CNT, 1481 mmTCP_EDC_CNT, 1482 mmTD_EDC_CNT 1483 }; 1484 1485 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 1486 { 1487 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 1488 struct amdgpu_ib ib; 1489 struct dma_fence *f = NULL; 1490 int r, i; 1491 u32 tmp; 1492 unsigned total_size, vgpr_offset, sgpr_offset; 1493 u64 gpu_addr; 1494 1495 /* only supported on CZ */ 1496 if (adev->asic_type != CHIP_CARRIZO) 1497 return 0; 1498 1499 /* bail if the compute ring is not ready */ 1500 if (!ring->sched.ready) 1501 return 0; 1502 1503 tmp = RREG32(mmGB_EDC_MODE); 1504 WREG32(mmGB_EDC_MODE, 0); 1505 1506 total_size = 1507 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1508 total_size += 1509 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1510 total_size += 1511 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1512 total_size = ALIGN(total_size, 256); 1513 vgpr_offset = total_size; 1514 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256); 1515 sgpr_offset = total_size; 1516 total_size += sizeof(sgpr_init_compute_shader); 1517 1518 /* allocate an indirect buffer to put the commands in */ 1519 memset(&ib, 0, sizeof(ib)); 1520 r = amdgpu_ib_get(adev, NULL, total_size, 1521 AMDGPU_IB_POOL_DIRECT, &ib); 1522 if (r) { 1523 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 1524 return r; 1525 } 1526 1527 /* load the compute shaders */ 1528 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) 1529 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; 1530 1531 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 1532 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 1533 1534 /* init the ib length to 0 */ 1535 ib.length_dw = 0; 1536 1537 /* VGPR */ 1538 /* write the register state for the compute dispatch */ 1539 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { 1540 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1541 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; 1542 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1]; 1543 } 1544 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1545 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 1546 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1547 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1548 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1549 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1550 1551 /* write dispatch packet */ 1552 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1553 ib.ptr[ib.length_dw++] = 8; /* x */ 1554 ib.ptr[ib.length_dw++] = 1; /* y */ 1555 ib.ptr[ib.length_dw++] = 1; /* z */ 1556 ib.ptr[ib.length_dw++] = 1557 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1558 1559 /* write CS partial flush packet */ 1560 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1561 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1562 1563 /* SGPR1 */ 1564 /* write the register state for the compute dispatch */ 1565 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { 1566 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1567 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; 1568 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1]; 1569 } 1570 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1571 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 1572 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1573 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1574 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1575 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1576 1577 /* write dispatch packet */ 1578 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1579 ib.ptr[ib.length_dw++] = 8; /* x */ 1580 ib.ptr[ib.length_dw++] = 1; /* y */ 1581 ib.ptr[ib.length_dw++] = 1; /* z */ 1582 ib.ptr[ib.length_dw++] = 1583 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1584 1585 /* write CS partial flush packet */ 1586 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1587 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1588 1589 /* SGPR2 */ 1590 /* write the register state for the compute dispatch */ 1591 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { 1592 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1593 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; 1594 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1]; 1595 } 1596 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1597 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 1598 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1599 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1600 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1601 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1602 1603 /* write dispatch packet */ 1604 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1605 ib.ptr[ib.length_dw++] = 8; /* x */ 1606 ib.ptr[ib.length_dw++] = 1; /* y */ 1607 ib.ptr[ib.length_dw++] = 1; /* z */ 1608 ib.ptr[ib.length_dw++] = 1609 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1610 1611 /* write CS partial flush packet */ 1612 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1613 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1614 1615 /* shedule the ib on the ring */ 1616 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1617 if (r) { 1618 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 1619 goto fail; 1620 } 1621 1622 /* wait for the GPU to finish processing the IB */ 1623 r = dma_fence_wait(f, false); 1624 if (r) { 1625 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 1626 goto fail; 1627 } 1628 1629 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); 1630 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); 1631 WREG32(mmGB_EDC_MODE, tmp); 1632 1633 tmp = RREG32(mmCC_GC_EDC_CONFIG); 1634 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; 1635 WREG32(mmCC_GC_EDC_CONFIG, tmp); 1636 1637 1638 /* read back registers to clear the counters */ 1639 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) 1640 RREG32(sec_ded_counter_registers[i]); 1641 1642 fail: 1643 amdgpu_ib_free(adev, &ib, NULL); 1644 dma_fence_put(f); 1645 1646 return r; 1647 } 1648 1649 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) 1650 { 1651 u32 gb_addr_config; 1652 u32 mc_arb_ramcfg; 1653 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 1654 u32 tmp; 1655 int ret; 1656 1657 switch (adev->asic_type) { 1658 case CHIP_TOPAZ: 1659 adev->gfx.config.max_shader_engines = 1; 1660 adev->gfx.config.max_tile_pipes = 2; 1661 adev->gfx.config.max_cu_per_sh = 6; 1662 adev->gfx.config.max_sh_per_se = 1; 1663 adev->gfx.config.max_backends_per_se = 2; 1664 adev->gfx.config.max_texture_channel_caches = 2; 1665 adev->gfx.config.max_gprs = 256; 1666 adev->gfx.config.max_gs_threads = 32; 1667 adev->gfx.config.max_hw_contexts = 8; 1668 1669 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1670 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1671 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1672 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1673 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; 1674 break; 1675 case CHIP_FIJI: 1676 adev->gfx.config.max_shader_engines = 4; 1677 adev->gfx.config.max_tile_pipes = 16; 1678 adev->gfx.config.max_cu_per_sh = 16; 1679 adev->gfx.config.max_sh_per_se = 1; 1680 adev->gfx.config.max_backends_per_se = 4; 1681 adev->gfx.config.max_texture_channel_caches = 16; 1682 adev->gfx.config.max_gprs = 256; 1683 adev->gfx.config.max_gs_threads = 32; 1684 adev->gfx.config.max_hw_contexts = 8; 1685 1686 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1687 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1688 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1689 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1690 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1691 break; 1692 case CHIP_POLARIS11: 1693 case CHIP_POLARIS12: 1694 ret = amdgpu_atombios_get_gfx_info(adev); 1695 if (ret) 1696 return ret; 1697 adev->gfx.config.max_gprs = 256; 1698 adev->gfx.config.max_gs_threads = 32; 1699 adev->gfx.config.max_hw_contexts = 8; 1700 1701 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1702 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1703 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1704 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1705 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; 1706 break; 1707 case CHIP_POLARIS10: 1708 case CHIP_VEGAM: 1709 ret = amdgpu_atombios_get_gfx_info(adev); 1710 if (ret) 1711 return ret; 1712 adev->gfx.config.max_gprs = 256; 1713 adev->gfx.config.max_gs_threads = 32; 1714 adev->gfx.config.max_hw_contexts = 8; 1715 1716 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1717 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1718 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1719 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1720 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1721 break; 1722 case CHIP_TONGA: 1723 adev->gfx.config.max_shader_engines = 4; 1724 adev->gfx.config.max_tile_pipes = 8; 1725 adev->gfx.config.max_cu_per_sh = 8; 1726 adev->gfx.config.max_sh_per_se = 1; 1727 adev->gfx.config.max_backends_per_se = 2; 1728 adev->gfx.config.max_texture_channel_caches = 8; 1729 adev->gfx.config.max_gprs = 256; 1730 adev->gfx.config.max_gs_threads = 32; 1731 adev->gfx.config.max_hw_contexts = 8; 1732 1733 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1734 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1735 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1736 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1737 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1738 break; 1739 case CHIP_CARRIZO: 1740 adev->gfx.config.max_shader_engines = 1; 1741 adev->gfx.config.max_tile_pipes = 2; 1742 adev->gfx.config.max_sh_per_se = 1; 1743 adev->gfx.config.max_backends_per_se = 2; 1744 adev->gfx.config.max_cu_per_sh = 8; 1745 adev->gfx.config.max_texture_channel_caches = 2; 1746 adev->gfx.config.max_gprs = 256; 1747 adev->gfx.config.max_gs_threads = 32; 1748 adev->gfx.config.max_hw_contexts = 8; 1749 1750 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1751 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1752 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1753 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1754 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1755 break; 1756 case CHIP_STONEY: 1757 adev->gfx.config.max_shader_engines = 1; 1758 adev->gfx.config.max_tile_pipes = 2; 1759 adev->gfx.config.max_sh_per_se = 1; 1760 adev->gfx.config.max_backends_per_se = 1; 1761 adev->gfx.config.max_cu_per_sh = 3; 1762 adev->gfx.config.max_texture_channel_caches = 2; 1763 adev->gfx.config.max_gprs = 256; 1764 adev->gfx.config.max_gs_threads = 16; 1765 adev->gfx.config.max_hw_contexts = 8; 1766 1767 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1768 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1769 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1770 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1771 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1772 break; 1773 default: 1774 adev->gfx.config.max_shader_engines = 2; 1775 adev->gfx.config.max_tile_pipes = 4; 1776 adev->gfx.config.max_cu_per_sh = 2; 1777 adev->gfx.config.max_sh_per_se = 1; 1778 adev->gfx.config.max_backends_per_se = 2; 1779 adev->gfx.config.max_texture_channel_caches = 4; 1780 adev->gfx.config.max_gprs = 256; 1781 adev->gfx.config.max_gs_threads = 32; 1782 adev->gfx.config.max_hw_contexts = 8; 1783 1784 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1785 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1786 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1787 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1788 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1789 break; 1790 } 1791 1792 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1793 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1794 1795 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, 1796 MC_ARB_RAMCFG, NOOFBANK); 1797 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, 1798 MC_ARB_RAMCFG, NOOFRANKS); 1799 1800 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1801 adev->gfx.config.mem_max_burst_length_bytes = 256; 1802 if (adev->flags & AMD_IS_APU) { 1803 /* Get memory bank mapping mode. */ 1804 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 1805 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1806 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1807 1808 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 1809 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1810 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1811 1812 /* Validate settings in case only one DIMM installed. */ 1813 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 1814 dimm00_addr_map = 0; 1815 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 1816 dimm01_addr_map = 0; 1817 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 1818 dimm10_addr_map = 0; 1819 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 1820 dimm11_addr_map = 0; 1821 1822 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 1823 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 1824 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 1825 adev->gfx.config.mem_row_size_in_kb = 2; 1826 else 1827 adev->gfx.config.mem_row_size_in_kb = 1; 1828 } else { 1829 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); 1830 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1831 if (adev->gfx.config.mem_row_size_in_kb > 4) 1832 adev->gfx.config.mem_row_size_in_kb = 4; 1833 } 1834 1835 adev->gfx.config.shader_engine_tile_size = 32; 1836 adev->gfx.config.num_gpus = 1; 1837 adev->gfx.config.multi_gpu_tile_size = 64; 1838 1839 /* fix up row size */ 1840 switch (adev->gfx.config.mem_row_size_in_kb) { 1841 case 1: 1842 default: 1843 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); 1844 break; 1845 case 2: 1846 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); 1847 break; 1848 case 4: 1849 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); 1850 break; 1851 } 1852 adev->gfx.config.gb_addr_config = gb_addr_config; 1853 1854 return 0; 1855 } 1856 1857 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1858 int mec, int pipe, int queue) 1859 { 1860 int r; 1861 unsigned irq_type; 1862 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1863 unsigned int hw_prio; 1864 1865 ring = &adev->gfx.compute_ring[ring_id]; 1866 1867 /* mec0 is me1 */ 1868 ring->me = mec + 1; 1869 ring->pipe = pipe; 1870 ring->queue = queue; 1871 1872 ring->ring_obj = NULL; 1873 ring->use_doorbell = true; 1874 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 1875 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1876 + (ring_id * GFX8_MEC_HPD_SIZE); 1877 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1878 1879 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1880 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1881 + ring->pipe; 1882 1883 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1884 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 1885 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1886 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1887 hw_prio, NULL); 1888 if (r) 1889 return r; 1890 1891 1892 return 0; 1893 } 1894 1895 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work); 1896 1897 static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) 1898 { 1899 int i, j, k, r, ring_id; 1900 int xcc_id = 0; 1901 struct amdgpu_ring *ring; 1902 struct amdgpu_device *adev = ip_block->adev; 1903 1904 switch (adev->asic_type) { 1905 case CHIP_TONGA: 1906 case CHIP_CARRIZO: 1907 case CHIP_FIJI: 1908 case CHIP_POLARIS10: 1909 case CHIP_POLARIS11: 1910 case CHIP_POLARIS12: 1911 case CHIP_VEGAM: 1912 adev->gfx.mec.num_mec = 2; 1913 break; 1914 case CHIP_TOPAZ: 1915 case CHIP_STONEY: 1916 default: 1917 adev->gfx.mec.num_mec = 1; 1918 break; 1919 } 1920 1921 adev->gfx.mec.num_pipe_per_mec = 4; 1922 adev->gfx.mec.num_queue_per_pipe = 8; 1923 1924 /* EOP Event */ 1925 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); 1926 if (r) 1927 return r; 1928 1929 /* Privileged reg */ 1930 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT, 1931 &adev->gfx.priv_reg_irq); 1932 if (r) 1933 return r; 1934 1935 /* Privileged inst */ 1936 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT, 1937 &adev->gfx.priv_inst_irq); 1938 if (r) 1939 return r; 1940 1941 /* Add CP EDC/ECC irq */ 1942 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR, 1943 &adev->gfx.cp_ecc_error_irq); 1944 if (r) 1945 return r; 1946 1947 /* SQ interrupts. */ 1948 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG, 1949 &adev->gfx.sq_irq); 1950 if (r) { 1951 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r); 1952 return r; 1953 } 1954 1955 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); 1956 1957 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1958 1959 r = gfx_v8_0_init_microcode(adev); 1960 if (r) { 1961 DRM_ERROR("Failed to load gfx firmware!\n"); 1962 return r; 1963 } 1964 1965 r = adev->gfx.rlc.funcs->init(adev); 1966 if (r) { 1967 DRM_ERROR("Failed to init rlc BOs!\n"); 1968 return r; 1969 } 1970 1971 r = gfx_v8_0_mec_init(adev); 1972 if (r) { 1973 DRM_ERROR("Failed to init MEC BOs!\n"); 1974 return r; 1975 } 1976 1977 /* set up the gfx ring */ 1978 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1979 ring = &adev->gfx.gfx_ring[i]; 1980 ring->ring_obj = NULL; 1981 sprintf(ring->name, "gfx"); 1982 /* no gfx doorbells on iceland */ 1983 if (adev->asic_type != CHIP_TOPAZ) { 1984 ring->use_doorbell = true; 1985 ring->doorbell_index = adev->doorbell_index.gfx_ring0; 1986 } 1987 1988 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 1989 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 1990 AMDGPU_RING_PRIO_DEFAULT, NULL); 1991 if (r) 1992 return r; 1993 } 1994 1995 1996 /* set up the compute queues - allocate horizontally across pipes */ 1997 ring_id = 0; 1998 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1999 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2000 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2001 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 2002 k, j)) 2003 continue; 2004 2005 r = gfx_v8_0_compute_ring_init(adev, 2006 ring_id, 2007 i, k, j); 2008 if (r) 2009 return r; 2010 2011 ring_id++; 2012 } 2013 } 2014 } 2015 2016 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0); 2017 if (r) { 2018 DRM_ERROR("Failed to init KIQ BOs!\n"); 2019 return r; 2020 } 2021 2022 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 2023 if (r) 2024 return r; 2025 2026 /* create MQD for all compute queues as well as KIQ for SRIOV case */ 2027 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0); 2028 if (r) 2029 return r; 2030 2031 adev->gfx.ce_ram_size = 0x8000; 2032 2033 r = gfx_v8_0_gpu_early_init(adev); 2034 if (r) 2035 return r; 2036 2037 return 0; 2038 } 2039 2040 static int gfx_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) 2041 { 2042 struct amdgpu_device *adev = ip_block->adev; 2043 int i; 2044 2045 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2046 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2047 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2048 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2049 2050 amdgpu_gfx_mqd_sw_fini(adev, 0); 2051 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2052 amdgpu_gfx_kiq_fini(adev, 0); 2053 2054 gfx_v8_0_mec_fini(adev); 2055 amdgpu_gfx_rlc_fini(adev); 2056 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2057 &adev->gfx.rlc.clear_state_gpu_addr, 2058 (void **)&adev->gfx.rlc.cs_ptr); 2059 if ((adev->asic_type == CHIP_CARRIZO) || 2060 (adev->asic_type == CHIP_STONEY)) { 2061 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2062 &adev->gfx.rlc.cp_table_gpu_addr, 2063 (void **)&adev->gfx.rlc.cp_table_ptr); 2064 } 2065 gfx_v8_0_free_microcode(adev); 2066 2067 return 0; 2068 } 2069 2070 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) 2071 { 2072 uint32_t *modearray, *mod2array; 2073 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 2074 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 2075 u32 reg_offset; 2076 2077 modearray = adev->gfx.config.tile_mode_array; 2078 mod2array = adev->gfx.config.macrotile_mode_array; 2079 2080 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2081 modearray[reg_offset] = 0; 2082 2083 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2084 mod2array[reg_offset] = 0; 2085 2086 switch (adev->asic_type) { 2087 case CHIP_TOPAZ: 2088 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2089 PIPE_CONFIG(ADDR_SURF_P2) | 2090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2091 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2092 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2093 PIPE_CONFIG(ADDR_SURF_P2) | 2094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2095 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2096 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2097 PIPE_CONFIG(ADDR_SURF_P2) | 2098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2099 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2100 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2101 PIPE_CONFIG(ADDR_SURF_P2) | 2102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2103 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2104 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2105 PIPE_CONFIG(ADDR_SURF_P2) | 2106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2107 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2108 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2109 PIPE_CONFIG(ADDR_SURF_P2) | 2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2111 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2112 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2113 PIPE_CONFIG(ADDR_SURF_P2) | 2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2115 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2116 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2117 PIPE_CONFIG(ADDR_SURF_P2)); 2118 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2119 PIPE_CONFIG(ADDR_SURF_P2) | 2120 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2122 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2123 PIPE_CONFIG(ADDR_SURF_P2) | 2124 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2126 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2127 PIPE_CONFIG(ADDR_SURF_P2) | 2128 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2130 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2131 PIPE_CONFIG(ADDR_SURF_P2) | 2132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2134 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2135 PIPE_CONFIG(ADDR_SURF_P2) | 2136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2138 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2139 PIPE_CONFIG(ADDR_SURF_P2) | 2140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2142 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2143 PIPE_CONFIG(ADDR_SURF_P2) | 2144 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2145 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2146 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2147 PIPE_CONFIG(ADDR_SURF_P2) | 2148 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2150 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2151 PIPE_CONFIG(ADDR_SURF_P2) | 2152 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2154 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2155 PIPE_CONFIG(ADDR_SURF_P2) | 2156 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2157 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2158 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2159 PIPE_CONFIG(ADDR_SURF_P2) | 2160 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2161 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2162 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2163 PIPE_CONFIG(ADDR_SURF_P2) | 2164 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2165 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2166 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2167 PIPE_CONFIG(ADDR_SURF_P2) | 2168 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2170 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2171 PIPE_CONFIG(ADDR_SURF_P2) | 2172 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2174 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2175 PIPE_CONFIG(ADDR_SURF_P2) | 2176 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2177 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2178 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2179 PIPE_CONFIG(ADDR_SURF_P2) | 2180 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2182 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2183 PIPE_CONFIG(ADDR_SURF_P2) | 2184 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2185 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2186 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2187 PIPE_CONFIG(ADDR_SURF_P2) | 2188 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2189 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2190 2191 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2194 NUM_BANKS(ADDR_SURF_8_BANK)); 2195 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2198 NUM_BANKS(ADDR_SURF_8_BANK)); 2199 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2202 NUM_BANKS(ADDR_SURF_8_BANK)); 2203 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2206 NUM_BANKS(ADDR_SURF_8_BANK)); 2207 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2210 NUM_BANKS(ADDR_SURF_8_BANK)); 2211 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2214 NUM_BANKS(ADDR_SURF_8_BANK)); 2215 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2218 NUM_BANKS(ADDR_SURF_8_BANK)); 2219 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2222 NUM_BANKS(ADDR_SURF_16_BANK)); 2223 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2226 NUM_BANKS(ADDR_SURF_16_BANK)); 2227 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2230 NUM_BANKS(ADDR_SURF_16_BANK)); 2231 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2234 NUM_BANKS(ADDR_SURF_16_BANK)); 2235 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2238 NUM_BANKS(ADDR_SURF_16_BANK)); 2239 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2242 NUM_BANKS(ADDR_SURF_16_BANK)); 2243 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2246 NUM_BANKS(ADDR_SURF_8_BANK)); 2247 2248 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2249 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 2250 reg_offset != 23) 2251 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2252 2253 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2254 if (reg_offset != 7) 2255 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2256 2257 break; 2258 case CHIP_FIJI: 2259 case CHIP_VEGAM: 2260 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2263 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2264 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2267 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2268 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2271 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2272 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2274 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2275 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2276 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2279 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2280 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2283 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2284 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2285 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2287 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2288 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2289 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2291 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2292 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 2294 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2296 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2298 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2300 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2302 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2304 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2306 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2307 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2308 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2310 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2312 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2314 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2316 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2318 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2320 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2322 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2324 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2326 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2327 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2328 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2330 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2332 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2334 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2335 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2336 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2338 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2340 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2341 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2342 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2343 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2344 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2345 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2346 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2347 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2348 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2349 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2350 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2351 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2352 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2353 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2354 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2355 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2356 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2357 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2358 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2359 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2360 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2361 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2362 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2363 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2364 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2365 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2366 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2367 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2368 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2369 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2370 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2371 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2372 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2373 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2374 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2375 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2376 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2377 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2378 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2379 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2380 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2381 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2382 2383 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2386 NUM_BANKS(ADDR_SURF_8_BANK)); 2387 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2390 NUM_BANKS(ADDR_SURF_8_BANK)); 2391 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2394 NUM_BANKS(ADDR_SURF_8_BANK)); 2395 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2396 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2397 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2398 NUM_BANKS(ADDR_SURF_8_BANK)); 2399 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2402 NUM_BANKS(ADDR_SURF_8_BANK)); 2403 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2406 NUM_BANKS(ADDR_SURF_8_BANK)); 2407 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2410 NUM_BANKS(ADDR_SURF_8_BANK)); 2411 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2412 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2413 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2414 NUM_BANKS(ADDR_SURF_8_BANK)); 2415 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2418 NUM_BANKS(ADDR_SURF_8_BANK)); 2419 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2420 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2421 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2422 NUM_BANKS(ADDR_SURF_8_BANK)); 2423 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2426 NUM_BANKS(ADDR_SURF_8_BANK)); 2427 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2430 NUM_BANKS(ADDR_SURF_8_BANK)); 2431 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2434 NUM_BANKS(ADDR_SURF_8_BANK)); 2435 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2438 NUM_BANKS(ADDR_SURF_4_BANK)); 2439 2440 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2441 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2442 2443 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2444 if (reg_offset != 7) 2445 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2446 2447 break; 2448 case CHIP_TONGA: 2449 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2450 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2452 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2453 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2454 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2456 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2457 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2458 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2460 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2461 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2462 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2464 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2465 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2466 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2467 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2468 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2469 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2470 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2472 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2473 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2474 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2475 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2476 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2477 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2478 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2480 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2481 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2482 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 2483 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2484 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2485 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2487 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2488 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2489 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2491 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2492 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2493 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2494 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2495 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2496 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2497 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2498 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2499 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2501 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2503 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2505 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2507 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2509 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2510 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2511 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2513 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2514 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2515 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2516 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2517 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2518 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2519 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2521 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2522 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2523 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2525 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2526 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2527 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2529 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2530 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2531 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2532 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2533 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2534 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2535 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2536 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2537 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2538 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2539 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2540 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2541 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2542 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2543 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2544 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2545 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2546 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2547 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2548 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2549 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2550 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2551 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2552 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2553 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2554 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2555 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2556 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2557 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2558 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2559 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2560 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2561 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2563 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2564 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2565 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2566 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2567 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2568 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2569 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2570 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2571 2572 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2573 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2574 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2575 NUM_BANKS(ADDR_SURF_16_BANK)); 2576 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2579 NUM_BANKS(ADDR_SURF_16_BANK)); 2580 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2583 NUM_BANKS(ADDR_SURF_16_BANK)); 2584 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2587 NUM_BANKS(ADDR_SURF_16_BANK)); 2588 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2591 NUM_BANKS(ADDR_SURF_16_BANK)); 2592 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2595 NUM_BANKS(ADDR_SURF_16_BANK)); 2596 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2599 NUM_BANKS(ADDR_SURF_16_BANK)); 2600 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2603 NUM_BANKS(ADDR_SURF_16_BANK)); 2604 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2607 NUM_BANKS(ADDR_SURF_16_BANK)); 2608 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2611 NUM_BANKS(ADDR_SURF_16_BANK)); 2612 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2615 NUM_BANKS(ADDR_SURF_16_BANK)); 2616 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2619 NUM_BANKS(ADDR_SURF_8_BANK)); 2620 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2623 NUM_BANKS(ADDR_SURF_4_BANK)); 2624 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2627 NUM_BANKS(ADDR_SURF_4_BANK)); 2628 2629 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2630 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2631 2632 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2633 if (reg_offset != 7) 2634 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2635 2636 break; 2637 case CHIP_POLARIS11: 2638 case CHIP_POLARIS12: 2639 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2640 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2641 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2642 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2643 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2644 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2645 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2646 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2647 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2648 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2649 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2650 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2651 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2652 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2654 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2655 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2656 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2657 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2658 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2659 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2660 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2661 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2662 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2663 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2664 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2665 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2666 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2667 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2668 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2669 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2670 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2671 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2672 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 2673 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2674 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2675 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2676 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2677 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2678 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2679 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2680 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2681 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2682 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2683 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2684 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2685 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2686 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2687 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2688 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2689 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2691 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2692 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2693 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2695 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2696 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2697 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2699 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2700 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2701 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2703 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2704 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2705 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2707 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2708 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2709 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2711 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2712 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2713 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2715 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2716 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2717 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2718 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2719 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2720 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2721 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2722 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2723 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2724 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2725 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2726 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2727 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2728 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2729 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2730 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2731 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2732 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2733 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2734 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2735 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2736 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2737 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2738 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2739 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2740 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2741 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2742 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2743 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2744 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2745 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2746 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2747 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2748 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2749 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2750 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2751 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2752 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2753 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2754 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2755 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2756 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2757 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2758 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2759 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2760 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2761 2762 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2765 NUM_BANKS(ADDR_SURF_16_BANK)); 2766 2767 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2768 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2769 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2770 NUM_BANKS(ADDR_SURF_16_BANK)); 2771 2772 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2773 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2774 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2775 NUM_BANKS(ADDR_SURF_16_BANK)); 2776 2777 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2778 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2779 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2780 NUM_BANKS(ADDR_SURF_16_BANK)); 2781 2782 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2785 NUM_BANKS(ADDR_SURF_16_BANK)); 2786 2787 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2788 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2789 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2790 NUM_BANKS(ADDR_SURF_16_BANK)); 2791 2792 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2793 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2794 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2795 NUM_BANKS(ADDR_SURF_16_BANK)); 2796 2797 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2800 NUM_BANKS(ADDR_SURF_16_BANK)); 2801 2802 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2803 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2804 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2805 NUM_BANKS(ADDR_SURF_16_BANK)); 2806 2807 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2808 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2809 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2810 NUM_BANKS(ADDR_SURF_16_BANK)); 2811 2812 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2815 NUM_BANKS(ADDR_SURF_16_BANK)); 2816 2817 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2820 NUM_BANKS(ADDR_SURF_16_BANK)); 2821 2822 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2825 NUM_BANKS(ADDR_SURF_8_BANK)); 2826 2827 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2830 NUM_BANKS(ADDR_SURF_4_BANK)); 2831 2832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2833 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2834 2835 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2836 if (reg_offset != 7) 2837 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2838 2839 break; 2840 case CHIP_POLARIS10: 2841 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2842 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2843 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2844 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2845 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2846 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2848 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2849 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2850 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2852 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2853 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2854 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2855 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2856 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2857 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2858 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2860 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2861 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2862 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2864 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2865 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2866 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2868 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2869 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2870 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2872 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2873 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2874 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 2875 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2876 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2877 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2878 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2879 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2880 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2881 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2882 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2883 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2884 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2885 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2886 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2887 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2888 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2889 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2890 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2891 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2892 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2893 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2894 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2895 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2897 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2898 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2899 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2900 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2901 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2902 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2903 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2905 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2906 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2907 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2908 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2909 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2910 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2911 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2913 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2914 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2915 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2916 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2917 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2918 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2919 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2921 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2922 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2923 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2924 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2925 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2926 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2927 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2928 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2929 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2930 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2931 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2932 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2933 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2934 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2935 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2936 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2937 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2938 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2939 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2940 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2941 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2942 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2943 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2944 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2945 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2946 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2947 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2948 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2949 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2951 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2952 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2953 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2954 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2955 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2956 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2957 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2958 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2959 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2960 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2961 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2962 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2963 2964 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2967 NUM_BANKS(ADDR_SURF_16_BANK)); 2968 2969 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2970 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2971 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2972 NUM_BANKS(ADDR_SURF_16_BANK)); 2973 2974 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2977 NUM_BANKS(ADDR_SURF_16_BANK)); 2978 2979 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2982 NUM_BANKS(ADDR_SURF_16_BANK)); 2983 2984 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2985 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2986 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2987 NUM_BANKS(ADDR_SURF_16_BANK)); 2988 2989 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2992 NUM_BANKS(ADDR_SURF_16_BANK)); 2993 2994 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2995 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2996 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2997 NUM_BANKS(ADDR_SURF_16_BANK)); 2998 2999 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3002 NUM_BANKS(ADDR_SURF_16_BANK)); 3003 3004 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3007 NUM_BANKS(ADDR_SURF_16_BANK)); 3008 3009 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3012 NUM_BANKS(ADDR_SURF_16_BANK)); 3013 3014 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3017 NUM_BANKS(ADDR_SURF_16_BANK)); 3018 3019 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3022 NUM_BANKS(ADDR_SURF_8_BANK)); 3023 3024 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3025 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3026 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3027 NUM_BANKS(ADDR_SURF_4_BANK)); 3028 3029 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3032 NUM_BANKS(ADDR_SURF_4_BANK)); 3033 3034 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3035 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3036 3037 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3038 if (reg_offset != 7) 3039 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3040 3041 break; 3042 case CHIP_STONEY: 3043 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3044 PIPE_CONFIG(ADDR_SURF_P2) | 3045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 3046 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3047 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3048 PIPE_CONFIG(ADDR_SURF_P2) | 3049 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 3050 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3051 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3052 PIPE_CONFIG(ADDR_SURF_P2) | 3053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 3054 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3055 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3056 PIPE_CONFIG(ADDR_SURF_P2) | 3057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 3058 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3059 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3060 PIPE_CONFIG(ADDR_SURF_P2) | 3061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3063 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3064 PIPE_CONFIG(ADDR_SURF_P2) | 3065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3067 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3068 PIPE_CONFIG(ADDR_SURF_P2) | 3069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3071 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 3072 PIPE_CONFIG(ADDR_SURF_P2)); 3073 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3074 PIPE_CONFIG(ADDR_SURF_P2) | 3075 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3077 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3078 PIPE_CONFIG(ADDR_SURF_P2) | 3079 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3081 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3082 PIPE_CONFIG(ADDR_SURF_P2) | 3083 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3084 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3085 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3086 PIPE_CONFIG(ADDR_SURF_P2) | 3087 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3089 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3090 PIPE_CONFIG(ADDR_SURF_P2) | 3091 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3093 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 3094 PIPE_CONFIG(ADDR_SURF_P2) | 3095 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3096 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3097 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3098 PIPE_CONFIG(ADDR_SURF_P2) | 3099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3101 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3102 PIPE_CONFIG(ADDR_SURF_P2) | 3103 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3105 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3106 PIPE_CONFIG(ADDR_SURF_P2) | 3107 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3109 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3110 PIPE_CONFIG(ADDR_SURF_P2) | 3111 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3112 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3113 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 3114 PIPE_CONFIG(ADDR_SURF_P2) | 3115 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3116 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3117 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 3118 PIPE_CONFIG(ADDR_SURF_P2) | 3119 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3121 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3122 PIPE_CONFIG(ADDR_SURF_P2) | 3123 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3125 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 3126 PIPE_CONFIG(ADDR_SURF_P2) | 3127 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3129 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 3130 PIPE_CONFIG(ADDR_SURF_P2) | 3131 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3132 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3133 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3134 PIPE_CONFIG(ADDR_SURF_P2) | 3135 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3136 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3137 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3138 PIPE_CONFIG(ADDR_SURF_P2) | 3139 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3141 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3142 PIPE_CONFIG(ADDR_SURF_P2) | 3143 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3144 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3145 3146 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3149 NUM_BANKS(ADDR_SURF_8_BANK)); 3150 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3153 NUM_BANKS(ADDR_SURF_8_BANK)); 3154 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3157 NUM_BANKS(ADDR_SURF_8_BANK)); 3158 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3161 NUM_BANKS(ADDR_SURF_8_BANK)); 3162 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3165 NUM_BANKS(ADDR_SURF_8_BANK)); 3166 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3169 NUM_BANKS(ADDR_SURF_8_BANK)); 3170 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3173 NUM_BANKS(ADDR_SURF_8_BANK)); 3174 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3177 NUM_BANKS(ADDR_SURF_16_BANK)); 3178 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3181 NUM_BANKS(ADDR_SURF_16_BANK)); 3182 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3185 NUM_BANKS(ADDR_SURF_16_BANK)); 3186 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3189 NUM_BANKS(ADDR_SURF_16_BANK)); 3190 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3193 NUM_BANKS(ADDR_SURF_16_BANK)); 3194 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3197 NUM_BANKS(ADDR_SURF_16_BANK)); 3198 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3201 NUM_BANKS(ADDR_SURF_8_BANK)); 3202 3203 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3204 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 3205 reg_offset != 23) 3206 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3207 3208 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3209 if (reg_offset != 7) 3210 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3211 3212 break; 3213 default: 3214 dev_warn(adev->dev, 3215 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n", 3216 adev->asic_type); 3217 fallthrough; 3218 3219 case CHIP_CARRIZO: 3220 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3221 PIPE_CONFIG(ADDR_SURF_P2) | 3222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 3223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3224 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3225 PIPE_CONFIG(ADDR_SURF_P2) | 3226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 3227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3228 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3229 PIPE_CONFIG(ADDR_SURF_P2) | 3230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 3231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3232 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3233 PIPE_CONFIG(ADDR_SURF_P2) | 3234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 3235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3236 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3237 PIPE_CONFIG(ADDR_SURF_P2) | 3238 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3239 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3240 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3241 PIPE_CONFIG(ADDR_SURF_P2) | 3242 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3243 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3244 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3245 PIPE_CONFIG(ADDR_SURF_P2) | 3246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3247 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3248 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 3249 PIPE_CONFIG(ADDR_SURF_P2)); 3250 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3251 PIPE_CONFIG(ADDR_SURF_P2) | 3252 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3253 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3254 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3255 PIPE_CONFIG(ADDR_SURF_P2) | 3256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3257 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3258 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3259 PIPE_CONFIG(ADDR_SURF_P2) | 3260 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3261 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3262 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3263 PIPE_CONFIG(ADDR_SURF_P2) | 3264 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3265 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3266 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3267 PIPE_CONFIG(ADDR_SURF_P2) | 3268 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3269 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3270 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 3271 PIPE_CONFIG(ADDR_SURF_P2) | 3272 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3273 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3274 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3275 PIPE_CONFIG(ADDR_SURF_P2) | 3276 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3278 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3279 PIPE_CONFIG(ADDR_SURF_P2) | 3280 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3282 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3283 PIPE_CONFIG(ADDR_SURF_P2) | 3284 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3286 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3287 PIPE_CONFIG(ADDR_SURF_P2) | 3288 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3290 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 3291 PIPE_CONFIG(ADDR_SURF_P2) | 3292 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3294 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 3295 PIPE_CONFIG(ADDR_SURF_P2) | 3296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3298 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3299 PIPE_CONFIG(ADDR_SURF_P2) | 3300 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3302 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 3303 PIPE_CONFIG(ADDR_SURF_P2) | 3304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3306 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 3307 PIPE_CONFIG(ADDR_SURF_P2) | 3308 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3310 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3311 PIPE_CONFIG(ADDR_SURF_P2) | 3312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3314 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3315 PIPE_CONFIG(ADDR_SURF_P2) | 3316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3318 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3319 PIPE_CONFIG(ADDR_SURF_P2) | 3320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3322 3323 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3326 NUM_BANKS(ADDR_SURF_8_BANK)); 3327 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3330 NUM_BANKS(ADDR_SURF_8_BANK)); 3331 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3334 NUM_BANKS(ADDR_SURF_8_BANK)); 3335 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3338 NUM_BANKS(ADDR_SURF_8_BANK)); 3339 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3342 NUM_BANKS(ADDR_SURF_8_BANK)); 3343 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3346 NUM_BANKS(ADDR_SURF_8_BANK)); 3347 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3350 NUM_BANKS(ADDR_SURF_8_BANK)); 3351 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3354 NUM_BANKS(ADDR_SURF_16_BANK)); 3355 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3358 NUM_BANKS(ADDR_SURF_16_BANK)); 3359 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3362 NUM_BANKS(ADDR_SURF_16_BANK)); 3363 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3366 NUM_BANKS(ADDR_SURF_16_BANK)); 3367 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3370 NUM_BANKS(ADDR_SURF_16_BANK)); 3371 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3374 NUM_BANKS(ADDR_SURF_16_BANK)); 3375 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3378 NUM_BANKS(ADDR_SURF_8_BANK)); 3379 3380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3381 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 3382 reg_offset != 23) 3383 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3384 3385 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3386 if (reg_offset != 7) 3387 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3388 3389 break; 3390 } 3391 } 3392 3393 static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, 3394 u32 se_num, u32 sh_num, u32 instance, 3395 int xcc_id) 3396 { 3397 u32 data; 3398 3399 if (instance == 0xffffffff) 3400 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 3401 else 3402 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 3403 3404 if (se_num == 0xffffffff) 3405 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 3406 else 3407 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 3408 3409 if (sh_num == 0xffffffff) 3410 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 3411 else 3412 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 3413 3414 WREG32(mmGRBM_GFX_INDEX, data); 3415 } 3416 3417 static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev, 3418 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3419 { 3420 vi_srbm_select(adev, me, pipe, q, vm); 3421 } 3422 3423 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) 3424 { 3425 u32 data, mask; 3426 3427 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 3428 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 3429 3430 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 3431 3432 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 3433 adev->gfx.config.max_sh_per_se); 3434 3435 return (~data) & mask; 3436 } 3437 3438 static void 3439 gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 3440 { 3441 switch (adev->asic_type) { 3442 case CHIP_FIJI: 3443 case CHIP_VEGAM: 3444 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 3445 RB_XSEL2(1) | PKR_MAP(2) | 3446 PKR_XSEL(1) | PKR_YSEL(1) | 3447 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3); 3448 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 3449 SE_PAIR_YSEL(2); 3450 break; 3451 case CHIP_TONGA: 3452 case CHIP_POLARIS10: 3453 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 3454 SE_XSEL(1) | SE_YSEL(1); 3455 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) | 3456 SE_PAIR_YSEL(2); 3457 break; 3458 case CHIP_TOPAZ: 3459 case CHIP_CARRIZO: 3460 *rconf |= RB_MAP_PKR0(2); 3461 *rconf1 |= 0x0; 3462 break; 3463 case CHIP_POLARIS11: 3464 case CHIP_POLARIS12: 3465 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 3466 SE_XSEL(1) | SE_YSEL(1); 3467 *rconf1 |= 0x0; 3468 break; 3469 case CHIP_STONEY: 3470 *rconf |= 0x0; 3471 *rconf1 |= 0x0; 3472 break; 3473 default: 3474 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 3475 break; 3476 } 3477 } 3478 3479 static void 3480 gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev, 3481 u32 raster_config, u32 raster_config_1, 3482 unsigned rb_mask, unsigned num_rb) 3483 { 3484 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 3485 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 3486 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 3487 unsigned rb_per_se = num_rb / num_se; 3488 unsigned se_mask[4]; 3489 unsigned se; 3490 3491 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 3492 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 3493 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 3494 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 3495 3496 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 3497 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 3498 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 3499 3500 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 3501 (!se_mask[2] && !se_mask[3]))) { 3502 raster_config_1 &= ~SE_PAIR_MAP_MASK; 3503 3504 if (!se_mask[0] && !se_mask[1]) { 3505 raster_config_1 |= 3506 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 3507 } else { 3508 raster_config_1 |= 3509 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 3510 } 3511 } 3512 3513 for (se = 0; se < num_se; se++) { 3514 unsigned raster_config_se = raster_config; 3515 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 3516 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 3517 int idx = (se / 2) * 2; 3518 3519 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 3520 raster_config_se &= ~SE_MAP_MASK; 3521 3522 if (!se_mask[idx]) { 3523 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 3524 } else { 3525 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 3526 } 3527 } 3528 3529 pkr0_mask &= rb_mask; 3530 pkr1_mask &= rb_mask; 3531 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 3532 raster_config_se &= ~PKR_MAP_MASK; 3533 3534 if (!pkr0_mask) { 3535 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 3536 } else { 3537 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 3538 } 3539 } 3540 3541 if (rb_per_se >= 2) { 3542 unsigned rb0_mask = 1 << (se * rb_per_se); 3543 unsigned rb1_mask = rb0_mask << 1; 3544 3545 rb0_mask &= rb_mask; 3546 rb1_mask &= rb_mask; 3547 if (!rb0_mask || !rb1_mask) { 3548 raster_config_se &= ~RB_MAP_PKR0_MASK; 3549 3550 if (!rb0_mask) { 3551 raster_config_se |= 3552 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 3553 } else { 3554 raster_config_se |= 3555 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 3556 } 3557 } 3558 3559 if (rb_per_se > 2) { 3560 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 3561 rb1_mask = rb0_mask << 1; 3562 rb0_mask &= rb_mask; 3563 rb1_mask &= rb_mask; 3564 if (!rb0_mask || !rb1_mask) { 3565 raster_config_se &= ~RB_MAP_PKR1_MASK; 3566 3567 if (!rb0_mask) { 3568 raster_config_se |= 3569 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 3570 } else { 3571 raster_config_se |= 3572 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 3573 } 3574 } 3575 } 3576 } 3577 3578 /* GRBM_GFX_INDEX has a different offset on VI */ 3579 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 3580 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 3581 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 3582 } 3583 3584 /* GRBM_GFX_INDEX has a different offset on VI */ 3585 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3586 } 3587 3588 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) 3589 { 3590 int i, j; 3591 u32 data; 3592 u32 raster_config = 0, raster_config_1 = 0; 3593 u32 active_rbs = 0; 3594 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 3595 adev->gfx.config.max_sh_per_se; 3596 unsigned num_rb_pipes; 3597 3598 mutex_lock(&adev->grbm_idx_mutex); 3599 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3600 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3601 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3602 data = gfx_v8_0_get_rb_active_bitmap(adev); 3603 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 3604 rb_bitmap_width_per_sh); 3605 } 3606 } 3607 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3608 3609 adev->gfx.config.backend_enable_mask = active_rbs; 3610 adev->gfx.config.num_rbs = hweight32(active_rbs); 3611 3612 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 3613 adev->gfx.config.max_shader_engines, 16); 3614 3615 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1); 3616 3617 if (!adev->gfx.config.backend_enable_mask || 3618 adev->gfx.config.num_rbs >= num_rb_pipes) { 3619 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 3620 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 3621 } else { 3622 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 3623 adev->gfx.config.backend_enable_mask, 3624 num_rb_pipes); 3625 } 3626 3627 /* cache the values for userspace */ 3628 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3629 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3630 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3631 adev->gfx.config.rb_config[i][j].rb_backend_disable = 3632 RREG32(mmCC_RB_BACKEND_DISABLE); 3633 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 3634 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 3635 adev->gfx.config.rb_config[i][j].raster_config = 3636 RREG32(mmPA_SC_RASTER_CONFIG); 3637 adev->gfx.config.rb_config[i][j].raster_config_1 = 3638 RREG32(mmPA_SC_RASTER_CONFIG_1); 3639 } 3640 } 3641 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3642 mutex_unlock(&adev->grbm_idx_mutex); 3643 } 3644 3645 #define DEFAULT_SH_MEM_BASES (0x6000) 3646 /** 3647 * gfx_v8_0_init_compute_vmid - gart enable 3648 * 3649 * @adev: amdgpu_device pointer 3650 * 3651 * Initialize compute vmid sh_mem registers 3652 * 3653 */ 3654 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) 3655 { 3656 int i; 3657 uint32_t sh_mem_config; 3658 uint32_t sh_mem_bases; 3659 3660 /* 3661 * Configure apertures: 3662 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 3663 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 3664 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 3665 */ 3666 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 3667 3668 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << 3669 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | 3670 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 3671 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | 3672 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | 3673 SH_MEM_CONFIG__PRIVATE_ATC_MASK; 3674 3675 mutex_lock(&adev->srbm_mutex); 3676 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 3677 vi_srbm_select(adev, 0, 0, 0, i); 3678 /* CP and shaders */ 3679 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 3680 WREG32(mmSH_MEM_APE1_BASE, 1); 3681 WREG32(mmSH_MEM_APE1_LIMIT, 0); 3682 WREG32(mmSH_MEM_BASES, sh_mem_bases); 3683 } 3684 vi_srbm_select(adev, 0, 0, 0, 0); 3685 mutex_unlock(&adev->srbm_mutex); 3686 3687 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 3688 access. These should be enabled by FW for target VMIDs. */ 3689 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 3690 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 3691 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); 3692 WREG32(amdgpu_gds_reg_offset[i].gws, 0); 3693 WREG32(amdgpu_gds_reg_offset[i].oa, 0); 3694 } 3695 } 3696 3697 static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev) 3698 { 3699 int vmid; 3700 3701 /* 3702 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 3703 * access. Compute VMIDs should be enabled by FW for target VMIDs, 3704 * the driver can enable them for graphics. VMID0 should maintain 3705 * access so that HWS firmware can save/restore entries. 3706 */ 3707 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 3708 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 3709 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 3710 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 3711 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 3712 } 3713 } 3714 3715 static void gfx_v8_0_config_init(struct amdgpu_device *adev) 3716 { 3717 switch (adev->asic_type) { 3718 default: 3719 adev->gfx.config.double_offchip_lds_buf = 1; 3720 break; 3721 case CHIP_CARRIZO: 3722 case CHIP_STONEY: 3723 adev->gfx.config.double_offchip_lds_buf = 0; 3724 break; 3725 } 3726 } 3727 3728 static void gfx_v8_0_constants_init(struct amdgpu_device *adev) 3729 { 3730 u32 tmp, sh_static_mem_cfg; 3731 int i; 3732 3733 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); 3734 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 3735 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 3736 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 3737 3738 gfx_v8_0_tiling_mode_table_init(adev); 3739 gfx_v8_0_setup_rb(adev); 3740 gfx_v8_0_get_cu_info(adev); 3741 gfx_v8_0_config_init(adev); 3742 3743 /* XXX SH_MEM regs */ 3744 /* where to put LDS, scratch, GPUVM in FSA64 space */ 3745 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 3746 SWIZZLE_ENABLE, 1); 3747 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 3748 ELEMENT_SIZE, 1); 3749 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 3750 INDEX_STRIDE, 3); 3751 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 3752 3753 mutex_lock(&adev->srbm_mutex); 3754 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 3755 vi_srbm_select(adev, 0, 0, 0, i); 3756 /* CP and shaders */ 3757 if (i == 0) { 3758 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); 3759 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 3760 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 3761 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 3762 WREG32(mmSH_MEM_CONFIG, tmp); 3763 WREG32(mmSH_MEM_BASES, 0); 3764 } else { 3765 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); 3766 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 3767 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 3768 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 3769 WREG32(mmSH_MEM_CONFIG, tmp); 3770 tmp = adev->gmc.shared_aperture_start >> 48; 3771 WREG32(mmSH_MEM_BASES, tmp); 3772 } 3773 3774 WREG32(mmSH_MEM_APE1_BASE, 1); 3775 WREG32(mmSH_MEM_APE1_LIMIT, 0); 3776 } 3777 vi_srbm_select(adev, 0, 0, 0, 0); 3778 mutex_unlock(&adev->srbm_mutex); 3779 3780 gfx_v8_0_init_compute_vmid(adev); 3781 gfx_v8_0_init_gds_vmid(adev); 3782 3783 mutex_lock(&adev->grbm_idx_mutex); 3784 /* 3785 * making sure that the following register writes will be broadcasted 3786 * to all the shaders 3787 */ 3788 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3789 3790 WREG32(mmPA_SC_FIFO_SIZE, 3791 (adev->gfx.config.sc_prim_fifo_size_frontend << 3792 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 3793 (adev->gfx.config.sc_prim_fifo_size_backend << 3794 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 3795 (adev->gfx.config.sc_hiz_tile_fifo_size << 3796 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 3797 (adev->gfx.config.sc_earlyz_tile_fifo_size << 3798 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 3799 3800 tmp = RREG32(mmSPI_ARB_PRIORITY); 3801 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 3802 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 3803 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 3804 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 3805 WREG32(mmSPI_ARB_PRIORITY, tmp); 3806 3807 mutex_unlock(&adev->grbm_idx_mutex); 3808 3809 } 3810 3811 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3812 { 3813 u32 i, j, k; 3814 u32 mask; 3815 3816 mutex_lock(&adev->grbm_idx_mutex); 3817 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3818 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3819 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3820 for (k = 0; k < adev->usec_timeout; k++) { 3821 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3822 break; 3823 udelay(1); 3824 } 3825 if (k == adev->usec_timeout) { 3826 gfx_v8_0_select_se_sh(adev, 0xffffffff, 3827 0xffffffff, 0xffffffff, 0); 3828 mutex_unlock(&adev->grbm_idx_mutex); 3829 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 3830 i, j); 3831 return; 3832 } 3833 } 3834 } 3835 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3836 mutex_unlock(&adev->grbm_idx_mutex); 3837 3838 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3839 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3840 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3841 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3842 for (k = 0; k < adev->usec_timeout; k++) { 3843 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3844 break; 3845 udelay(1); 3846 } 3847 } 3848 3849 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3850 bool enable) 3851 { 3852 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3853 3854 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 3855 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 3856 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 3857 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 3858 3859 WREG32(mmCP_INT_CNTL_RING0, tmp); 3860 } 3861 3862 static void gfx_v8_0_init_csb(struct amdgpu_device *adev) 3863 { 3864 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 3865 /* csib */ 3866 WREG32(mmRLC_CSIB_ADDR_HI, 3867 adev->gfx.rlc.clear_state_gpu_addr >> 32); 3868 WREG32(mmRLC_CSIB_ADDR_LO, 3869 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 3870 WREG32(mmRLC_CSIB_LENGTH, 3871 adev->gfx.rlc.clear_state_size); 3872 } 3873 3874 static void gfx_v8_0_parse_ind_reg_list(int *register_list_format, 3875 int ind_offset, 3876 int list_size, 3877 int *unique_indices, 3878 int *indices_count, 3879 int max_indices, 3880 int *ind_start_offsets, 3881 int *offset_count, 3882 int max_offset) 3883 { 3884 int indices; 3885 bool new_entry = true; 3886 3887 for (; ind_offset < list_size; ind_offset++) { 3888 3889 if (new_entry) { 3890 new_entry = false; 3891 ind_start_offsets[*offset_count] = ind_offset; 3892 *offset_count = *offset_count + 1; 3893 BUG_ON(*offset_count >= max_offset); 3894 } 3895 3896 if (register_list_format[ind_offset] == 0xFFFFFFFF) { 3897 new_entry = true; 3898 continue; 3899 } 3900 3901 ind_offset += 2; 3902 3903 /* look for the matching indice */ 3904 for (indices = 0; 3905 indices < *indices_count; 3906 indices++) { 3907 if (unique_indices[indices] == 3908 register_list_format[ind_offset]) 3909 break; 3910 } 3911 3912 if (indices >= *indices_count) { 3913 unique_indices[*indices_count] = 3914 register_list_format[ind_offset]; 3915 indices = *indices_count; 3916 *indices_count = *indices_count + 1; 3917 BUG_ON(*indices_count >= max_indices); 3918 } 3919 3920 register_list_format[ind_offset] = indices; 3921 } 3922 } 3923 3924 static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) 3925 { 3926 int i, temp, data; 3927 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; 3928 int indices_count = 0; 3929 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 3930 int offset_count = 0; 3931 3932 int list_size; 3933 unsigned int *register_list_format = 3934 kmemdup(adev->gfx.rlc.register_list_format, 3935 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 3936 if (!register_list_format) 3937 return -ENOMEM; 3938 3939 gfx_v8_0_parse_ind_reg_list(register_list_format, 3940 RLC_FormatDirectRegListLength, 3941 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 3942 unique_indices, 3943 &indices_count, 3944 ARRAY_SIZE(unique_indices), 3945 indirect_start_offsets, 3946 &offset_count, 3947 ARRAY_SIZE(indirect_start_offsets)); 3948 3949 /* save and restore list */ 3950 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); 3951 3952 WREG32(mmRLC_SRM_ARAM_ADDR, 0); 3953 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 3954 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); 3955 3956 /* indirect list */ 3957 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); 3958 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) 3959 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]); 3960 3961 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 3962 list_size = list_size >> 1; 3963 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); 3964 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size); 3965 3966 /* starting offsets starts */ 3967 WREG32(mmRLC_GPM_SCRATCH_ADDR, 3968 adev->gfx.rlc.starting_offsets_start); 3969 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 3970 WREG32(mmRLC_GPM_SCRATCH_DATA, 3971 indirect_start_offsets[i]); 3972 3973 /* unique indices */ 3974 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; 3975 data = mmRLC_SRM_INDEX_CNTL_DATA_0; 3976 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) { 3977 if (unique_indices[i] != 0) { 3978 WREG32(temp + i, unique_indices[i] & 0x3FFFF); 3979 WREG32(data + i, unique_indices[i] >> 20); 3980 } 3981 } 3982 kfree(register_list_format); 3983 3984 return 0; 3985 } 3986 3987 static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) 3988 { 3989 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); 3990 } 3991 3992 static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) 3993 { 3994 uint32_t data; 3995 3996 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); 3997 3998 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); 3999 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); 4000 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); 4001 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); 4002 WREG32(mmRLC_PG_DELAY, data); 4003 4004 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); 4005 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); 4006 4007 } 4008 4009 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 4010 bool enable) 4011 { 4012 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); 4013 } 4014 4015 static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 4016 bool enable) 4017 { 4018 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); 4019 } 4020 4021 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) 4022 { 4023 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); 4024 } 4025 4026 static void gfx_v8_0_init_pg(struct amdgpu_device *adev) 4027 { 4028 if ((adev->asic_type == CHIP_CARRIZO) || 4029 (adev->asic_type == CHIP_STONEY)) { 4030 gfx_v8_0_init_csb(adev); 4031 gfx_v8_0_init_save_restore_list(adev); 4032 gfx_v8_0_enable_save_restore_machine(adev); 4033 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4034 gfx_v8_0_init_power_gating(adev); 4035 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4036 } else if ((adev->asic_type == CHIP_POLARIS11) || 4037 (adev->asic_type == CHIP_POLARIS12) || 4038 (adev->asic_type == CHIP_VEGAM)) { 4039 gfx_v8_0_init_csb(adev); 4040 gfx_v8_0_init_save_restore_list(adev); 4041 gfx_v8_0_enable_save_restore_machine(adev); 4042 gfx_v8_0_init_power_gating(adev); 4043 } 4044 4045 } 4046 4047 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) 4048 { 4049 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); 4050 4051 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 4052 gfx_v8_0_wait_for_rlc_serdes(adev); 4053 } 4054 4055 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) 4056 { 4057 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4058 udelay(50); 4059 4060 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 4061 udelay(50); 4062 } 4063 4064 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) 4065 { 4066 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); 4067 4068 /* carrizo do enable cp interrupt after cp inited */ 4069 if (!(adev->flags & AMD_IS_APU)) 4070 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 4071 4072 udelay(50); 4073 } 4074 4075 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 4076 { 4077 if (amdgpu_sriov_vf(adev)) { 4078 gfx_v8_0_init_csb(adev); 4079 return 0; 4080 } 4081 4082 adev->gfx.rlc.funcs->stop(adev); 4083 adev->gfx.rlc.funcs->reset(adev); 4084 gfx_v8_0_init_pg(adev); 4085 adev->gfx.rlc.funcs->start(adev); 4086 4087 return 0; 4088 } 4089 4090 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 4091 { 4092 u32 tmp = RREG32(mmCP_ME_CNTL); 4093 4094 if (enable) { 4095 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); 4096 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); 4097 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); 4098 } else { 4099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); 4100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); 4101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); 4102 } 4103 WREG32(mmCP_ME_CNTL, tmp); 4104 udelay(50); 4105 } 4106 4107 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) 4108 { 4109 u32 count = 0; 4110 const struct cs_section_def *sect = NULL; 4111 const struct cs_extent_def *ext = NULL; 4112 4113 /* begin clear state */ 4114 count += 2; 4115 /* context control state */ 4116 count += 3; 4117 4118 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 4119 for (ext = sect->section; ext->extent != NULL; ++ext) { 4120 if (sect->id == SECT_CONTEXT) 4121 count += 2 + ext->reg_count; 4122 else 4123 return 0; 4124 } 4125 } 4126 /* pa_sc_raster_config/pa_sc_raster_config1 */ 4127 count += 4; 4128 /* end clear state */ 4129 count += 2; 4130 /* clear state */ 4131 count += 2; 4132 4133 return count; 4134 } 4135 4136 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) 4137 { 4138 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 4139 const struct cs_section_def *sect = NULL; 4140 const struct cs_extent_def *ext = NULL; 4141 int r, i; 4142 4143 /* init the CP */ 4144 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 4145 WREG32(mmCP_ENDIAN_SWAP, 0); 4146 WREG32(mmCP_DEVICE_ID, 1); 4147 4148 gfx_v8_0_cp_gfx_enable(adev, true); 4149 4150 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4); 4151 if (r) { 4152 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 4153 return r; 4154 } 4155 4156 /* clear state buffer */ 4157 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4158 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4159 4160 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4161 amdgpu_ring_write(ring, 0x80000000); 4162 amdgpu_ring_write(ring, 0x80000000); 4163 4164 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 4165 for (ext = sect->section; ext->extent != NULL; ++ext) { 4166 if (sect->id == SECT_CONTEXT) { 4167 amdgpu_ring_write(ring, 4168 PACKET3(PACKET3_SET_CONTEXT_REG, 4169 ext->reg_count)); 4170 amdgpu_ring_write(ring, 4171 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4172 for (i = 0; i < ext->reg_count; i++) 4173 amdgpu_ring_write(ring, ext->extent[i]); 4174 } 4175 } 4176 } 4177 4178 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4179 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4180 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 4181 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 4182 4183 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4184 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 4185 4186 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 4187 amdgpu_ring_write(ring, 0); 4188 4189 /* init the CE partitions */ 4190 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 4191 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 4192 amdgpu_ring_write(ring, 0x8000); 4193 amdgpu_ring_write(ring, 0x8000); 4194 4195 amdgpu_ring_commit(ring); 4196 4197 return 0; 4198 } 4199 static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring) 4200 { 4201 u32 tmp; 4202 /* no gfx doorbells on iceland */ 4203 if (adev->asic_type == CHIP_TOPAZ) 4204 return; 4205 4206 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); 4207 4208 if (ring->use_doorbell) { 4209 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4210 DOORBELL_OFFSET, ring->doorbell_index); 4211 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4212 DOORBELL_HIT, 0); 4213 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4214 DOORBELL_EN, 1); 4215 } else { 4216 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 4217 } 4218 4219 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); 4220 4221 if (adev->flags & AMD_IS_APU) 4222 return; 4223 4224 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 4225 DOORBELL_RANGE_LOWER, 4226 adev->doorbell_index.gfx_ring0); 4227 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 4228 4229 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, 4230 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 4231 } 4232 4233 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) 4234 { 4235 struct amdgpu_ring *ring; 4236 u32 tmp; 4237 u32 rb_bufsz; 4238 u64 rb_addr, rptr_addr, wptr_gpu_addr; 4239 4240 /* Set the write pointer delay */ 4241 WREG32(mmCP_RB_WPTR_DELAY, 0); 4242 4243 /* set the RB to use vmid 0 */ 4244 WREG32(mmCP_RB_VMID, 0); 4245 4246 /* Set ring buffer size */ 4247 ring = &adev->gfx.gfx_ring[0]; 4248 rb_bufsz = order_base_2(ring->ring_size / 8); 4249 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 4250 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 4251 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); 4252 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); 4253 #ifdef __BIG_ENDIAN 4254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 4255 #endif 4256 WREG32(mmCP_RB0_CNTL, tmp); 4257 4258 /* Initialize the ring buffer's read and write pointers */ 4259 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 4260 ring->wptr = 0; 4261 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4262 4263 /* set the wb address whether it's enabled or not */ 4264 rptr_addr = ring->rptr_gpu_addr; 4265 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 4266 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 4267 4268 wptr_gpu_addr = ring->wptr_gpu_addr; 4269 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 4270 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 4271 mdelay(1); 4272 WREG32(mmCP_RB0_CNTL, tmp); 4273 4274 rb_addr = ring->gpu_addr >> 8; 4275 WREG32(mmCP_RB0_BASE, rb_addr); 4276 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 4277 4278 gfx_v8_0_set_cpg_door_bell(adev, ring); 4279 /* start the ring */ 4280 amdgpu_ring_clear_ring(ring); 4281 gfx_v8_0_cp_gfx_start(adev); 4282 4283 return 0; 4284 } 4285 4286 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 4287 { 4288 if (enable) { 4289 WREG32(mmCP_MEC_CNTL, 0); 4290 } else { 4291 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 4292 adev->gfx.kiq[0].ring.sched.ready = false; 4293 } 4294 udelay(50); 4295 } 4296 4297 /* KIQ functions */ 4298 static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring) 4299 { 4300 uint32_t tmp; 4301 struct amdgpu_device *adev = ring->adev; 4302 4303 /* tell RLC which is KIQ queue */ 4304 tmp = RREG32(mmRLC_CP_SCHEDULERS); 4305 tmp &= 0xffffff00; 4306 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4307 WREG32(mmRLC_CP_SCHEDULERS, tmp | 0x80); 4308 } 4309 4310 static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) 4311 { 4312 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 4313 uint64_t queue_mask = 0; 4314 int r, i; 4315 4316 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 4317 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap)) 4318 continue; 4319 4320 /* This situation may be hit in the future if a new HW 4321 * generation exposes more than 64 queues. If so, the 4322 * definition of queue_mask needs updating */ 4323 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 4324 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 4325 break; 4326 } 4327 4328 queue_mask |= (1ull << i); 4329 } 4330 4331 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); 4332 if (r) { 4333 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 4334 return r; 4335 } 4336 /* set resources */ 4337 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 4338 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ 4339 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 4340 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 4341 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 4342 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 4343 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 4344 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 4345 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4346 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 4347 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 4348 uint64_t wptr_addr = ring->wptr_gpu_addr; 4349 4350 /* map queues */ 4351 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 4352 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 4353 amdgpu_ring_write(kiq_ring, 4354 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 4355 amdgpu_ring_write(kiq_ring, 4356 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) | 4357 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 4358 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 4359 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */ 4360 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 4361 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 4362 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 4363 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 4364 } 4365 4366 amdgpu_ring_commit(kiq_ring); 4367 4368 return 0; 4369 } 4370 4371 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) 4372 { 4373 int i, r = 0; 4374 4375 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { 4376 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req); 4377 for (i = 0; i < adev->usec_timeout; i++) { 4378 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) 4379 break; 4380 udelay(1); 4381 } 4382 if (i == adev->usec_timeout) 4383 r = -ETIMEDOUT; 4384 } 4385 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 4386 WREG32(mmCP_HQD_PQ_RPTR, 0); 4387 WREG32(mmCP_HQD_PQ_WPTR, 0); 4388 4389 return r; 4390 } 4391 4392 static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd) 4393 { 4394 struct amdgpu_device *adev = ring->adev; 4395 4396 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4397 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 4398 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 4399 mqd->cp_hqd_queue_priority = 4400 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 4401 } 4402 } 4403 } 4404 4405 static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) 4406 { 4407 struct amdgpu_device *adev = ring->adev; 4408 struct vi_mqd *mqd = ring->mqd_ptr; 4409 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4410 uint32_t tmp; 4411 4412 mqd->header = 0xC0310800; 4413 mqd->compute_pipelinestat_enable = 0x00000001; 4414 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4415 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4416 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4417 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4418 mqd->compute_misc_reserved = 0x00000003; 4419 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr 4420 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); 4421 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr 4422 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); 4423 eop_base_addr = ring->eop_gpu_addr >> 8; 4424 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4425 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4426 4427 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4428 tmp = RREG32(mmCP_HQD_EOP_CONTROL); 4429 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4430 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1)); 4431 4432 mqd->cp_hqd_eop_control = tmp; 4433 4434 /* enable doorbell? */ 4435 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL), 4436 CP_HQD_PQ_DOORBELL_CONTROL, 4437 DOORBELL_EN, 4438 ring->use_doorbell ? 1 : 0); 4439 4440 mqd->cp_hqd_pq_doorbell_control = tmp; 4441 4442 /* set the pointer to the MQD */ 4443 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 4444 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 4445 4446 /* set MQD vmid to 0 */ 4447 tmp = RREG32(mmCP_MQD_CONTROL); 4448 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4449 mqd->cp_mqd_control = tmp; 4450 4451 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4452 hqd_gpu_addr = ring->gpu_addr >> 8; 4453 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4454 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4455 4456 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4457 tmp = RREG32(mmCP_HQD_PQ_CONTROL); 4458 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4459 (order_base_2(ring->ring_size / 4) - 1)); 4460 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4461 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4462 #ifdef __BIG_ENDIAN 4463 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4464 #endif 4465 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4466 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 4467 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4468 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4469 mqd->cp_hqd_pq_control = tmp; 4470 4471 /* set the wb address whether it's enabled or not */ 4472 wb_gpu_addr = ring->rptr_gpu_addr; 4473 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4474 mqd->cp_hqd_pq_rptr_report_addr_hi = 4475 upper_32_bits(wb_gpu_addr) & 0xffff; 4476 4477 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4478 wb_gpu_addr = ring->wptr_gpu_addr; 4479 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4480 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4481 4482 tmp = 0; 4483 /* enable the doorbell if requested */ 4484 if (ring->use_doorbell) { 4485 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 4486 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4487 DOORBELL_OFFSET, ring->doorbell_index); 4488 4489 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4490 DOORBELL_EN, 1); 4491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4492 DOORBELL_SOURCE, 0); 4493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4494 DOORBELL_HIT, 0); 4495 } 4496 4497 mqd->cp_hqd_pq_doorbell_control = tmp; 4498 4499 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4500 ring->wptr = 0; 4501 mqd->cp_hqd_pq_wptr = ring->wptr; 4502 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 4503 4504 /* set the vmid for the queue */ 4505 mqd->cp_hqd_vmid = 0; 4506 4507 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); 4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 4509 mqd->cp_hqd_persistent_state = tmp; 4510 4511 /* set MTYPE */ 4512 tmp = RREG32(mmCP_HQD_IB_CONTROL); 4513 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4514 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3); 4515 mqd->cp_hqd_ib_control = tmp; 4516 4517 tmp = RREG32(mmCP_HQD_IQ_TIMER); 4518 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3); 4519 mqd->cp_hqd_iq_timer = tmp; 4520 4521 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL); 4522 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3); 4523 mqd->cp_hqd_ctx_save_control = tmp; 4524 4525 /* defaults */ 4526 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR); 4527 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR); 4528 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO); 4529 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI); 4530 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET); 4531 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE); 4532 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); 4533 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE); 4534 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS); 4535 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR); 4536 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM); 4537 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES); 4538 4539 /* set static priority for a queue/ring */ 4540 gfx_v8_0_mqd_set_priority(ring, mqd); 4541 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 4542 4543 /* map_queues packet doesn't need activate the queue, 4544 * so only kiq need set this field. 4545 */ 4546 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 4547 mqd->cp_hqd_active = 1; 4548 4549 return 0; 4550 } 4551 4552 static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, 4553 struct vi_mqd *mqd) 4554 { 4555 uint32_t mqd_reg; 4556 uint32_t *mqd_data; 4557 4558 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */ 4559 mqd_data = &mqd->cp_mqd_base_addr_lo; 4560 4561 /* disable wptr polling */ 4562 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); 4563 4564 /* program all HQD registers */ 4565 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++) 4566 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4567 4568 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 4569 * This is safe since EOP RPTR==WPTR for any inactive HQD 4570 * on ASICs that do not support context-save. 4571 * EOP writes/reads can start anywhere in the ring. 4572 */ 4573 if (adev->asic_type != CHIP_TONGA) { 4574 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr); 4575 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr); 4576 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem); 4577 } 4578 4579 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++) 4580 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4581 4582 /* activate the HQD */ 4583 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 4584 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4585 4586 return 0; 4587 } 4588 4589 static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) 4590 { 4591 struct amdgpu_device *adev = ring->adev; 4592 struct vi_mqd *mqd = ring->mqd_ptr; 4593 4594 gfx_v8_0_kiq_setting(ring); 4595 4596 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4597 /* reset MQD to a clean status */ 4598 if (adev->gfx.kiq[0].mqd_backup) 4599 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation)); 4600 4601 /* reset ring buffer */ 4602 ring->wptr = 0; 4603 amdgpu_ring_clear_ring(ring); 4604 mutex_lock(&adev->srbm_mutex); 4605 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4606 gfx_v8_0_mqd_commit(adev, mqd); 4607 vi_srbm_select(adev, 0, 0, 0, 0); 4608 mutex_unlock(&adev->srbm_mutex); 4609 } else { 4610 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4611 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 4612 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 4613 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4614 amdgpu_ring_clear_ring(ring); 4615 mutex_lock(&adev->srbm_mutex); 4616 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4617 gfx_v8_0_mqd_init(ring); 4618 gfx_v8_0_mqd_commit(adev, mqd); 4619 vi_srbm_select(adev, 0, 0, 0, 0); 4620 mutex_unlock(&adev->srbm_mutex); 4621 4622 if (adev->gfx.kiq[0].mqd_backup) 4623 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation)); 4624 } 4625 4626 return 0; 4627 } 4628 4629 static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) 4630 { 4631 struct amdgpu_device *adev = ring->adev; 4632 struct vi_mqd *mqd = ring->mqd_ptr; 4633 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4634 4635 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4636 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4637 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 4638 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 4639 mutex_lock(&adev->srbm_mutex); 4640 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4641 gfx_v8_0_mqd_init(ring); 4642 vi_srbm_select(adev, 0, 0, 0, 0); 4643 mutex_unlock(&adev->srbm_mutex); 4644 4645 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4646 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); 4647 } else { 4648 /* restore MQD to a clean status */ 4649 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4650 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); 4651 /* reset ring buffer */ 4652 ring->wptr = 0; 4653 amdgpu_ring_clear_ring(ring); 4654 } 4655 return 0; 4656 } 4657 4658 static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev) 4659 { 4660 if (adev->asic_type > CHIP_TONGA) { 4661 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2); 4662 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2); 4663 } 4664 /* enable doorbells */ 4665 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4666 } 4667 4668 static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) 4669 { 4670 struct amdgpu_ring *ring; 4671 int r; 4672 4673 ring = &adev->gfx.kiq[0].ring; 4674 4675 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4676 if (unlikely(r != 0)) 4677 return r; 4678 4679 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4680 if (unlikely(r != 0)) { 4681 amdgpu_bo_unreserve(ring->mqd_obj); 4682 return r; 4683 } 4684 4685 gfx_v8_0_kiq_init_queue(ring); 4686 amdgpu_bo_kunmap(ring->mqd_obj); 4687 ring->mqd_ptr = NULL; 4688 amdgpu_bo_unreserve(ring->mqd_obj); 4689 return 0; 4690 } 4691 4692 static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev) 4693 { 4694 struct amdgpu_ring *ring = NULL; 4695 int r = 0, i; 4696 4697 gfx_v8_0_cp_compute_enable(adev, true); 4698 4699 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4700 ring = &adev->gfx.compute_ring[i]; 4701 4702 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4703 if (unlikely(r != 0)) 4704 goto done; 4705 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4706 if (!r) { 4707 r = gfx_v8_0_kcq_init_queue(ring); 4708 amdgpu_bo_kunmap(ring->mqd_obj); 4709 ring->mqd_ptr = NULL; 4710 } 4711 amdgpu_bo_unreserve(ring->mqd_obj); 4712 if (r) 4713 goto done; 4714 } 4715 4716 gfx_v8_0_set_mec_doorbell_range(adev); 4717 4718 r = gfx_v8_0_kiq_kcq_enable(adev); 4719 if (r) 4720 goto done; 4721 4722 done: 4723 return r; 4724 } 4725 4726 static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev) 4727 { 4728 int r, i; 4729 struct amdgpu_ring *ring; 4730 4731 /* collect all the ring_tests here, gfx, kiq, compute */ 4732 ring = &adev->gfx.gfx_ring[0]; 4733 r = amdgpu_ring_test_helper(ring); 4734 if (r) 4735 return r; 4736 4737 ring = &adev->gfx.kiq[0].ring; 4738 r = amdgpu_ring_test_helper(ring); 4739 if (r) 4740 return r; 4741 4742 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4743 ring = &adev->gfx.compute_ring[i]; 4744 amdgpu_ring_test_helper(ring); 4745 } 4746 4747 return 0; 4748 } 4749 4750 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) 4751 { 4752 int r; 4753 4754 if (!(adev->flags & AMD_IS_APU)) 4755 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 4756 4757 r = gfx_v8_0_kiq_resume(adev); 4758 if (r) 4759 return r; 4760 4761 r = gfx_v8_0_cp_gfx_resume(adev); 4762 if (r) 4763 return r; 4764 4765 r = gfx_v8_0_kcq_resume(adev); 4766 if (r) 4767 return r; 4768 4769 r = gfx_v8_0_cp_test_all_rings(adev); 4770 if (r) 4771 return r; 4772 4773 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 4774 4775 return 0; 4776 } 4777 4778 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) 4779 { 4780 gfx_v8_0_cp_gfx_enable(adev, enable); 4781 gfx_v8_0_cp_compute_enable(adev, enable); 4782 } 4783 4784 static int gfx_v8_0_hw_init(struct amdgpu_ip_block *ip_block) 4785 { 4786 int r; 4787 struct amdgpu_device *adev = ip_block->adev; 4788 4789 gfx_v8_0_init_golden_registers(adev); 4790 gfx_v8_0_constants_init(adev); 4791 4792 r = adev->gfx.rlc.funcs->resume(adev); 4793 if (r) 4794 return r; 4795 4796 r = gfx_v8_0_cp_resume(adev); 4797 4798 return r; 4799 } 4800 4801 static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev) 4802 { 4803 int r, i; 4804 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 4805 4806 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); 4807 if (r) 4808 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 4809 4810 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4811 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 4812 4813 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 4814 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 4815 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 4816 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 4817 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 4818 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 4819 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 4820 amdgpu_ring_write(kiq_ring, 0); 4821 amdgpu_ring_write(kiq_ring, 0); 4822 amdgpu_ring_write(kiq_ring, 0); 4823 } 4824 /* Submit unmap queue packet */ 4825 amdgpu_ring_commit(kiq_ring); 4826 /* 4827 * Ring test will do a basic scratch register change check. Just run 4828 * this to ensure that unmap queues that is submitted before got 4829 * processed successfully before returning. 4830 */ 4831 r = amdgpu_ring_test_helper(kiq_ring); 4832 if (r) 4833 DRM_ERROR("KCQ disable failed\n"); 4834 4835 return r; 4836 } 4837 4838 static bool gfx_v8_0_is_idle(void *handle) 4839 { 4840 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4841 4842 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) 4843 || RREG32(mmGRBM_STATUS2) != 0x8) 4844 return false; 4845 else 4846 return true; 4847 } 4848 4849 static bool gfx_v8_0_rlc_is_idle(void *handle) 4850 { 4851 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4852 4853 if (RREG32(mmGRBM_STATUS2) != 0x8) 4854 return false; 4855 else 4856 return true; 4857 } 4858 4859 static int gfx_v8_0_wait_for_rlc_idle(void *handle) 4860 { 4861 unsigned int i; 4862 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4863 4864 for (i = 0; i < adev->usec_timeout; i++) { 4865 if (gfx_v8_0_rlc_is_idle(handle)) 4866 return 0; 4867 4868 udelay(1); 4869 } 4870 return -ETIMEDOUT; 4871 } 4872 4873 static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4874 { 4875 unsigned int i; 4876 struct amdgpu_device *adev = ip_block->adev; 4877 4878 for (i = 0; i < adev->usec_timeout; i++) { 4879 if (gfx_v8_0_is_idle(adev)) 4880 return 0; 4881 4882 udelay(1); 4883 } 4884 return -ETIMEDOUT; 4885 } 4886 4887 static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) 4888 { 4889 struct amdgpu_device *adev = ip_block->adev; 4890 4891 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4892 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4893 4894 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 4895 4896 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); 4897 4898 /* disable KCQ to avoid CPC touch memory not valid anymore */ 4899 gfx_v8_0_kcq_disable(adev); 4900 4901 if (amdgpu_sriov_vf(adev)) { 4902 pr_debug("For SRIOV client, shouldn't do anything.\n"); 4903 return 0; 4904 } 4905 4906 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4907 if (!gfx_v8_0_wait_for_idle(ip_block)) 4908 gfx_v8_0_cp_enable(adev, false); 4909 else 4910 pr_err("cp is busy, skip halt cp\n"); 4911 if (!gfx_v8_0_wait_for_rlc_idle(adev)) 4912 adev->gfx.rlc.funcs->stop(adev); 4913 else 4914 pr_err("rlc is busy, skip halt rlc\n"); 4915 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4916 4917 return 0; 4918 } 4919 4920 static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block) 4921 { 4922 return gfx_v8_0_hw_fini(ip_block); 4923 } 4924 4925 static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block) 4926 { 4927 return gfx_v8_0_hw_init(ip_block); 4928 } 4929 4930 static bool gfx_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 4931 { 4932 struct amdgpu_device *adev = ip_block->adev; 4933 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4934 u32 tmp; 4935 4936 /* GRBM_STATUS */ 4937 tmp = RREG32(mmGRBM_STATUS); 4938 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4939 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4940 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4941 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4942 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4943 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK | 4944 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4945 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4946 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4947 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4948 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4949 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 4950 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 4951 } 4952 4953 /* GRBM_STATUS2 */ 4954 tmp = RREG32(mmGRBM_STATUS2); 4955 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4956 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4957 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4958 4959 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || 4960 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || 4961 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) { 4962 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4963 SOFT_RESET_CPF, 1); 4964 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4965 SOFT_RESET_CPC, 1); 4966 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4967 SOFT_RESET_CPG, 1); 4968 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 4969 SOFT_RESET_GRBM, 1); 4970 } 4971 4972 /* SRBM_STATUS */ 4973 tmp = RREG32(mmSRBM_STATUS); 4974 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) 4975 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 4976 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 4977 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY)) 4978 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 4979 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 4980 4981 if (grbm_soft_reset || srbm_soft_reset) { 4982 adev->gfx.grbm_soft_reset = grbm_soft_reset; 4983 adev->gfx.srbm_soft_reset = srbm_soft_reset; 4984 return true; 4985 } else { 4986 adev->gfx.grbm_soft_reset = 0; 4987 adev->gfx.srbm_soft_reset = 0; 4988 return false; 4989 } 4990 } 4991 4992 static int gfx_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 4993 { 4994 struct amdgpu_device *adev = ip_block->adev; 4995 u32 grbm_soft_reset = 0; 4996 4997 if ((!adev->gfx.grbm_soft_reset) && 4998 (!adev->gfx.srbm_soft_reset)) 4999 return 0; 5000 5001 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5002 5003 /* stop the rlc */ 5004 adev->gfx.rlc.funcs->stop(adev); 5005 5006 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5007 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) 5008 /* Disable GFX parsing/prefetching */ 5009 gfx_v8_0_cp_gfx_enable(adev, false); 5010 5011 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5012 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || 5013 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || 5014 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { 5015 int i; 5016 5017 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5018 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 5019 5020 mutex_lock(&adev->srbm_mutex); 5021 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5022 gfx_v8_0_deactivate_hqd(adev, 2); 5023 vi_srbm_select(adev, 0, 0, 0, 0); 5024 mutex_unlock(&adev->srbm_mutex); 5025 } 5026 /* Disable MEC parsing/prefetching */ 5027 gfx_v8_0_cp_compute_enable(adev, false); 5028 } 5029 5030 return 0; 5031 } 5032 5033 static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) 5034 { 5035 struct amdgpu_device *adev = ip_block->adev; 5036 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5037 u32 tmp; 5038 5039 if ((!adev->gfx.grbm_soft_reset) && 5040 (!adev->gfx.srbm_soft_reset)) 5041 return 0; 5042 5043 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5044 srbm_soft_reset = adev->gfx.srbm_soft_reset; 5045 5046 if (grbm_soft_reset || srbm_soft_reset) { 5047 tmp = RREG32(mmGMCON_DEBUG); 5048 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1); 5049 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1); 5050 WREG32(mmGMCON_DEBUG, tmp); 5051 udelay(50); 5052 } 5053 5054 if (grbm_soft_reset) { 5055 tmp = RREG32(mmGRBM_SOFT_RESET); 5056 tmp |= grbm_soft_reset; 5057 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 5058 WREG32(mmGRBM_SOFT_RESET, tmp); 5059 tmp = RREG32(mmGRBM_SOFT_RESET); 5060 5061 udelay(50); 5062 5063 tmp &= ~grbm_soft_reset; 5064 WREG32(mmGRBM_SOFT_RESET, tmp); 5065 tmp = RREG32(mmGRBM_SOFT_RESET); 5066 } 5067 5068 if (srbm_soft_reset) { 5069 tmp = RREG32(mmSRBM_SOFT_RESET); 5070 tmp |= srbm_soft_reset; 5071 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 5072 WREG32(mmSRBM_SOFT_RESET, tmp); 5073 tmp = RREG32(mmSRBM_SOFT_RESET); 5074 5075 udelay(50); 5076 5077 tmp &= ~srbm_soft_reset; 5078 WREG32(mmSRBM_SOFT_RESET, tmp); 5079 tmp = RREG32(mmSRBM_SOFT_RESET); 5080 } 5081 5082 if (grbm_soft_reset || srbm_soft_reset) { 5083 tmp = RREG32(mmGMCON_DEBUG); 5084 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); 5085 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); 5086 WREG32(mmGMCON_DEBUG, tmp); 5087 } 5088 5089 /* Wait a little for things to settle down */ 5090 udelay(50); 5091 5092 return 0; 5093 } 5094 5095 static int gfx_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5096 { 5097 struct amdgpu_device *adev = ip_block->adev; 5098 u32 grbm_soft_reset = 0; 5099 5100 if ((!adev->gfx.grbm_soft_reset) && 5101 (!adev->gfx.srbm_soft_reset)) 5102 return 0; 5103 5104 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5105 5106 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5107 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || 5108 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || 5109 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { 5110 int i; 5111 5112 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5113 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 5114 5115 mutex_lock(&adev->srbm_mutex); 5116 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5117 gfx_v8_0_deactivate_hqd(adev, 2); 5118 vi_srbm_select(adev, 0, 0, 0, 0); 5119 mutex_unlock(&adev->srbm_mutex); 5120 } 5121 gfx_v8_0_kiq_resume(adev); 5122 gfx_v8_0_kcq_resume(adev); 5123 } 5124 5125 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5126 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) 5127 gfx_v8_0_cp_gfx_resume(adev); 5128 5129 gfx_v8_0_cp_test_all_rings(adev); 5130 5131 adev->gfx.rlc.funcs->start(adev); 5132 5133 return 0; 5134 } 5135 5136 /** 5137 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot 5138 * 5139 * @adev: amdgpu_device pointer 5140 * 5141 * Fetches a GPU clock counter snapshot. 5142 * Returns the 64 bit clock counter snapshot. 5143 */ 5144 static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5145 { 5146 uint64_t clock; 5147 5148 mutex_lock(&adev->gfx.gpu_clock_mutex); 5149 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 5150 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 5151 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 5152 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5153 return clock; 5154 } 5155 5156 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5157 uint32_t vmid, 5158 uint32_t gds_base, uint32_t gds_size, 5159 uint32_t gws_base, uint32_t gws_size, 5160 uint32_t oa_base, uint32_t oa_size) 5161 { 5162 /* GDS Base */ 5163 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5164 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5165 WRITE_DATA_DST_SEL(0))); 5166 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 5167 amdgpu_ring_write(ring, 0); 5168 amdgpu_ring_write(ring, gds_base); 5169 5170 /* GDS Size */ 5171 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5172 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5173 WRITE_DATA_DST_SEL(0))); 5174 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 5175 amdgpu_ring_write(ring, 0); 5176 amdgpu_ring_write(ring, gds_size); 5177 5178 /* GWS */ 5179 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5180 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5181 WRITE_DATA_DST_SEL(0))); 5182 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 5183 amdgpu_ring_write(ring, 0); 5184 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5185 5186 /* OA */ 5187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5188 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5189 WRITE_DATA_DST_SEL(0))); 5190 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 5191 amdgpu_ring_write(ring, 0); 5192 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 5193 } 5194 5195 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 5196 { 5197 WREG32(mmSQ_IND_INDEX, 5198 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5199 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5200 (address << SQ_IND_INDEX__INDEX__SHIFT) | 5201 (SQ_IND_INDEX__FORCE_READ_MASK)); 5202 return RREG32(mmSQ_IND_DATA); 5203 } 5204 5205 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 5206 uint32_t wave, uint32_t thread, 5207 uint32_t regno, uint32_t num, uint32_t *out) 5208 { 5209 WREG32(mmSQ_IND_INDEX, 5210 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5211 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5212 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 5213 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 5214 (SQ_IND_INDEX__FORCE_READ_MASK) | 5215 (SQ_IND_INDEX__AUTO_INCR_MASK)); 5216 while (num--) 5217 *(out++) = RREG32(mmSQ_IND_DATA); 5218 } 5219 5220 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 5221 { 5222 /* type 0 wave data */ 5223 dst[(*no_fields)++] = 0; 5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 5226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 5227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 5228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 5229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 5230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 5231 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 5232 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 5233 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 5234 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 5235 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 5236 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 5237 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 5238 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 5239 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 5240 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 5241 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 5242 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 5243 } 5244 5245 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 5246 uint32_t wave, uint32_t start, 5247 uint32_t size, uint32_t *dst) 5248 { 5249 wave_read_regs( 5250 adev, simd, wave, 0, 5251 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 5252 } 5253 5254 5255 static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { 5256 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, 5257 .select_se_sh = &gfx_v8_0_select_se_sh, 5258 .read_wave_data = &gfx_v8_0_read_wave_data, 5259 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs, 5260 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q 5261 }; 5262 5263 static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) 5264 { 5265 struct amdgpu_device *adev = ip_block->adev; 5266 5267 adev->gfx.xcc_mask = 1; 5268 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; 5269 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5270 AMDGPU_MAX_COMPUTE_RINGS); 5271 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; 5272 gfx_v8_0_set_ring_funcs(adev); 5273 gfx_v8_0_set_irq_funcs(adev); 5274 gfx_v8_0_set_gds_init(adev); 5275 gfx_v8_0_set_rlc_funcs(adev); 5276 5277 return 0; 5278 } 5279 5280 static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) 5281 { 5282 struct amdgpu_device *adev = ip_block->adev; 5283 int r; 5284 5285 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5286 if (r) 5287 return r; 5288 5289 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5290 if (r) 5291 return r; 5292 5293 /* requires IBs so do in late init after IB pool is initialized */ 5294 r = gfx_v8_0_do_edc_gpr_workarounds(adev); 5295 if (r) 5296 return r; 5297 5298 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 5299 if (r) { 5300 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r); 5301 return r; 5302 } 5303 5304 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); 5305 if (r) { 5306 DRM_ERROR( 5307 "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n", 5308 r); 5309 return r; 5310 } 5311 5312 return 0; 5313 } 5314 5315 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 5316 bool enable) 5317 { 5318 if ((adev->asic_type == CHIP_POLARIS11) || 5319 (adev->asic_type == CHIP_POLARIS12) || 5320 (adev->asic_type == CHIP_VEGAM)) 5321 /* Send msg to SMU via Powerplay */ 5322 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0); 5323 5324 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); 5325 } 5326 5327 static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 5328 bool enable) 5329 { 5330 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); 5331 } 5332 5333 static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, 5334 bool enable) 5335 { 5336 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); 5337 } 5338 5339 static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 5340 bool enable) 5341 { 5342 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); 5343 } 5344 5345 static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev, 5346 bool enable) 5347 { 5348 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); 5349 5350 /* Read any GFX register to wake up GFX. */ 5351 if (!enable) 5352 RREG32(mmDB_RENDER_CONTROL); 5353 } 5354 5355 static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev, 5356 bool enable) 5357 { 5358 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 5359 cz_enable_gfx_cg_power_gating(adev, true); 5360 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 5361 cz_enable_gfx_pipeline_power_gating(adev, true); 5362 } else { 5363 cz_enable_gfx_cg_power_gating(adev, false); 5364 cz_enable_gfx_pipeline_power_gating(adev, false); 5365 } 5366 } 5367 5368 static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5369 enum amd_powergating_state state) 5370 { 5371 struct amdgpu_device *adev = ip_block->adev; 5372 bool enable = (state == AMD_PG_STATE_GATE); 5373 5374 if (amdgpu_sriov_vf(adev)) 5375 return 0; 5376 5377 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG | 5378 AMD_PG_SUPPORT_RLC_SMU_HS | 5379 AMD_PG_SUPPORT_CP | 5380 AMD_PG_SUPPORT_GFX_DMG)) 5381 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5382 switch (adev->asic_type) { 5383 case CHIP_CARRIZO: 5384 case CHIP_STONEY: 5385 5386 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5387 cz_enable_sck_slow_down_on_power_up(adev, true); 5388 cz_enable_sck_slow_down_on_power_down(adev, true); 5389 } else { 5390 cz_enable_sck_slow_down_on_power_up(adev, false); 5391 cz_enable_sck_slow_down_on_power_down(adev, false); 5392 } 5393 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5394 cz_enable_cp_power_gating(adev, true); 5395 else 5396 cz_enable_cp_power_gating(adev, false); 5397 5398 cz_update_gfx_cg_power_gating(adev, enable); 5399 5400 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5401 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); 5402 else 5403 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false); 5404 5405 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 5406 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true); 5407 else 5408 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false); 5409 break; 5410 case CHIP_POLARIS11: 5411 case CHIP_POLARIS12: 5412 case CHIP_VEGAM: 5413 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5414 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); 5415 else 5416 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false); 5417 5418 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 5419 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true); 5420 else 5421 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false); 5422 5423 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable) 5424 polaris11_enable_gfx_quick_mg_power_gating(adev, true); 5425 else 5426 polaris11_enable_gfx_quick_mg_power_gating(adev, false); 5427 break; 5428 default: 5429 break; 5430 } 5431 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG | 5432 AMD_PG_SUPPORT_RLC_SMU_HS | 5433 AMD_PG_SUPPORT_CP | 5434 AMD_PG_SUPPORT_GFX_DMG)) 5435 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5436 return 0; 5437 } 5438 5439 static void gfx_v8_0_get_clockgating_state(void *handle, u64 *flags) 5440 { 5441 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5442 int data; 5443 5444 if (amdgpu_sriov_vf(adev)) 5445 *flags = 0; 5446 5447 /* AMD_CG_SUPPORT_GFX_MGCG */ 5448 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5449 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK)) 5450 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5451 5452 /* AMD_CG_SUPPORT_GFX_CGLG */ 5453 data = RREG32(mmRLC_CGCG_CGLS_CTRL); 5454 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5455 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5456 5457 /* AMD_CG_SUPPORT_GFX_CGLS */ 5458 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5459 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5460 5461 /* AMD_CG_SUPPORT_GFX_CGTS */ 5462 data = RREG32(mmCGTS_SM_CTRL_REG); 5463 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK)) 5464 *flags |= AMD_CG_SUPPORT_GFX_CGTS; 5465 5466 /* AMD_CG_SUPPORT_GFX_CGTS_LS */ 5467 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK)) 5468 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS; 5469 5470 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5471 data = RREG32(mmRLC_MEM_SLP_CNTL); 5472 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5473 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5474 5475 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5476 data = RREG32(mmCP_MEM_SLP_CNTL); 5477 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5478 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5479 } 5480 5481 static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, 5482 uint32_t reg_addr, uint32_t cmd) 5483 { 5484 uint32_t data; 5485 5486 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5487 5488 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 5489 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 5490 5491 data = RREG32(mmRLC_SERDES_WR_CTRL); 5492 if (adev->asic_type == CHIP_STONEY) 5493 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | 5494 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | 5495 RLC_SERDES_WR_CTRL__P1_SELECT_MASK | 5496 RLC_SERDES_WR_CTRL__P2_SELECT_MASK | 5497 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | 5498 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | 5499 RLC_SERDES_WR_CTRL__POWER_UP_MASK | 5500 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | 5501 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); 5502 else 5503 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | 5504 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | 5505 RLC_SERDES_WR_CTRL__P1_SELECT_MASK | 5506 RLC_SERDES_WR_CTRL__P2_SELECT_MASK | 5507 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | 5508 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | 5509 RLC_SERDES_WR_CTRL__POWER_UP_MASK | 5510 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | 5511 RLC_SERDES_WR_CTRL__BPM_DATA_MASK | 5512 RLC_SERDES_WR_CTRL__REG_ADDR_MASK | 5513 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); 5514 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK | 5515 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | 5516 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | 5517 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); 5518 5519 WREG32(mmRLC_SERDES_WR_CTRL, data); 5520 } 5521 5522 #define MSG_ENTER_RLC_SAFE_MODE 1 5523 #define MSG_EXIT_RLC_SAFE_MODE 0 5524 #define RLC_GPR_REG2__REQ_MASK 0x00000001 5525 #define RLC_GPR_REG2__REQ__SHIFT 0 5526 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001 5527 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e 5528 5529 static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev) 5530 { 5531 uint32_t rlc_setting; 5532 5533 rlc_setting = RREG32(mmRLC_CNTL); 5534 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 5535 return false; 5536 5537 return true; 5538 } 5539 5540 static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5541 { 5542 uint32_t data; 5543 unsigned i; 5544 data = RREG32(mmRLC_CNTL); 5545 data |= RLC_SAFE_MODE__CMD_MASK; 5546 data &= ~RLC_SAFE_MODE__MESSAGE_MASK; 5547 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5548 WREG32(mmRLC_SAFE_MODE, data); 5549 5550 /* wait for RLC_SAFE_MODE */ 5551 for (i = 0; i < adev->usec_timeout; i++) { 5552 if ((RREG32(mmRLC_GPM_STAT) & 5553 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | 5554 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == 5555 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | 5556 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) 5557 break; 5558 udelay(1); 5559 } 5560 for (i = 0; i < adev->usec_timeout; i++) { 5561 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 5562 break; 5563 udelay(1); 5564 } 5565 } 5566 5567 static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5568 { 5569 uint32_t data; 5570 unsigned i; 5571 5572 data = RREG32(mmRLC_CNTL); 5573 data |= RLC_SAFE_MODE__CMD_MASK; 5574 data &= ~RLC_SAFE_MODE__MESSAGE_MASK; 5575 WREG32(mmRLC_SAFE_MODE, data); 5576 5577 for (i = 0; i < adev->usec_timeout; i++) { 5578 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 5579 break; 5580 udelay(1); 5581 } 5582 } 5583 5584 static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5585 { 5586 u32 data; 5587 5588 amdgpu_gfx_off_ctrl(adev, false); 5589 5590 if (amdgpu_sriov_is_pp_one_vf(adev)) 5591 data = RREG32_NO_KIQ(mmRLC_SPM_VMID); 5592 else 5593 data = RREG32(mmRLC_SPM_VMID); 5594 5595 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK; 5596 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT; 5597 5598 if (amdgpu_sriov_is_pp_one_vf(adev)) 5599 WREG32_NO_KIQ(mmRLC_SPM_VMID, data); 5600 else 5601 WREG32(mmRLC_SPM_VMID, data); 5602 5603 amdgpu_gfx_off_ctrl(adev, true); 5604 } 5605 5606 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = { 5607 .is_rlc_enabled = gfx_v8_0_is_rlc_enabled, 5608 .set_safe_mode = gfx_v8_0_set_safe_mode, 5609 .unset_safe_mode = gfx_v8_0_unset_safe_mode, 5610 .init = gfx_v8_0_rlc_init, 5611 .get_csb_size = gfx_v8_0_get_csb_size, 5612 .get_csb_buffer = gfx_v8_0_get_csb_buffer, 5613 .get_cp_table_num = gfx_v8_0_cp_jump_table_num, 5614 .resume = gfx_v8_0_rlc_resume, 5615 .stop = gfx_v8_0_rlc_stop, 5616 .reset = gfx_v8_0_rlc_reset, 5617 .start = gfx_v8_0_rlc_start, 5618 .update_spm_vmid = gfx_v8_0_update_spm_vmid 5619 }; 5620 5621 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5622 bool enable) 5623 { 5624 uint32_t temp, data; 5625 5626 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5627 5628 /* It is disabled by HW by default */ 5629 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 5630 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5631 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) 5632 /* 1 - RLC memory Light sleep */ 5633 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1); 5634 5635 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) 5636 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1); 5637 } 5638 5639 /* 3 - RLC_CGTT_MGCG_OVERRIDE */ 5640 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5641 if (adev->flags & AMD_IS_APU) 5642 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5643 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5644 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK); 5645 else 5646 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5647 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5648 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | 5649 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); 5650 5651 if (temp != data) 5652 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 5653 5654 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5655 gfx_v8_0_wait_for_rlc_serdes(adev); 5656 5657 /* 5 - clear mgcg override */ 5658 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD); 5659 5660 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 5661 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */ 5662 temp = data = RREG32(mmCGTS_SM_CTRL_REG); 5663 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK); 5664 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 5665 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 5666 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 5667 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 5668 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 5669 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 5670 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 5671 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 5672 if (temp != data) 5673 WREG32(mmCGTS_SM_CTRL_REG, data); 5674 } 5675 udelay(50); 5676 5677 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5678 gfx_v8_0_wait_for_rlc_serdes(adev); 5679 } else { 5680 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */ 5681 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5682 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5683 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5684 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | 5685 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); 5686 if (temp != data) 5687 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 5688 5689 /* 2 - disable MGLS in RLC */ 5690 data = RREG32(mmRLC_MEM_SLP_CNTL); 5691 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 5692 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 5693 WREG32(mmRLC_MEM_SLP_CNTL, data); 5694 } 5695 5696 /* 3 - disable MGLS in CP */ 5697 data = RREG32(mmCP_MEM_SLP_CNTL); 5698 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 5699 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 5700 WREG32(mmCP_MEM_SLP_CNTL, data); 5701 } 5702 5703 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */ 5704 temp = data = RREG32(mmCGTS_SM_CTRL_REG); 5705 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK | 5706 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK); 5707 if (temp != data) 5708 WREG32(mmCGTS_SM_CTRL_REG, data); 5709 5710 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5711 gfx_v8_0_wait_for_rlc_serdes(adev); 5712 5713 /* 6 - set mgcg override */ 5714 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD); 5715 5716 udelay(50); 5717 5718 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5719 gfx_v8_0_wait_for_rlc_serdes(adev); 5720 } 5721 5722 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5723 } 5724 5725 static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5726 bool enable) 5727 { 5728 uint32_t temp, temp1, data, data1; 5729 5730 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 5731 5732 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5733 5734 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 5735 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5736 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK; 5737 if (temp1 != data1) 5738 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5739 5740 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5741 gfx_v8_0_wait_for_rlc_serdes(adev); 5742 5743 /* 2 - clear cgcg override */ 5744 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); 5745 5746 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5747 gfx_v8_0_wait_for_rlc_serdes(adev); 5748 5749 /* 3 - write cmd to set CGLS */ 5750 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); 5751 5752 /* 4 - enable cgcg */ 5753 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5754 5755 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5756 /* enable cgls*/ 5757 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5758 5759 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5760 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK; 5761 5762 if (temp1 != data1) 5763 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5764 } else { 5765 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5766 } 5767 5768 if (temp != data) 5769 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 5770 5771 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/ 5772 * Cmp_busy/GFX_Idle interrupts 5773 */ 5774 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 5775 } else { 5776 /* disable cntx_empty_int_enable & GFX Idle interrupt */ 5777 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 5778 5779 /* TEST CGCG */ 5780 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5781 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK | 5782 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK); 5783 if (temp1 != data1) 5784 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5785 5786 /* read gfx register to wake up cgcg */ 5787 RREG32(mmCB_CGTT_SCLK_CTRL); 5788 RREG32(mmCB_CGTT_SCLK_CTRL); 5789 RREG32(mmCB_CGTT_SCLK_CTRL); 5790 RREG32(mmCB_CGTT_SCLK_CTRL); 5791 5792 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5793 gfx_v8_0_wait_for_rlc_serdes(adev); 5794 5795 /* write cmd to Set CGCG Override */ 5796 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD); 5797 5798 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5799 gfx_v8_0_wait_for_rlc_serdes(adev); 5800 5801 /* write cmd to Clear CGLS */ 5802 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD); 5803 5804 /* disable cgcg, cgls should be disabled too. */ 5805 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | 5806 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 5807 if (temp != data) 5808 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 5809 /* enable interrupts again for PG */ 5810 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 5811 } 5812 5813 gfx_v8_0_wait_for_rlc_serdes(adev); 5814 5815 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5816 } 5817 static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5818 bool enable) 5819 { 5820 if (enable) { 5821 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS) 5822 * === MGCG + MGLS + TS(CG/LS) === 5823 */ 5824 gfx_v8_0_update_medium_grain_clock_gating(adev, enable); 5825 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); 5826 } else { 5827 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS) 5828 * === CGCG + CGLS === 5829 */ 5830 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); 5831 gfx_v8_0_update_medium_grain_clock_gating(adev, enable); 5832 } 5833 return 0; 5834 } 5835 5836 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 5837 enum amd_clockgating_state state) 5838 { 5839 uint32_t msg_id, pp_state = 0; 5840 uint32_t pp_support_state = 0; 5841 5842 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 5843 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5844 pp_support_state = PP_STATE_SUPPORT_LS; 5845 pp_state = PP_STATE_LS; 5846 } 5847 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5848 pp_support_state |= PP_STATE_SUPPORT_CG; 5849 pp_state |= PP_STATE_CG; 5850 } 5851 if (state == AMD_CG_STATE_UNGATE) 5852 pp_state = 0; 5853 5854 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5855 PP_BLOCK_GFX_CG, 5856 pp_support_state, 5857 pp_state); 5858 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5859 } 5860 5861 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 5862 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5863 pp_support_state = PP_STATE_SUPPORT_LS; 5864 pp_state = PP_STATE_LS; 5865 } 5866 5867 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5868 pp_support_state |= PP_STATE_SUPPORT_CG; 5869 pp_state |= PP_STATE_CG; 5870 } 5871 5872 if (state == AMD_CG_STATE_UNGATE) 5873 pp_state = 0; 5874 5875 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5876 PP_BLOCK_GFX_MG, 5877 pp_support_state, 5878 pp_state); 5879 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5880 } 5881 5882 return 0; 5883 } 5884 5885 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 5886 enum amd_clockgating_state state) 5887 { 5888 5889 uint32_t msg_id, pp_state = 0; 5890 uint32_t pp_support_state = 0; 5891 5892 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 5893 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5894 pp_support_state = PP_STATE_SUPPORT_LS; 5895 pp_state = PP_STATE_LS; 5896 } 5897 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5898 pp_support_state |= PP_STATE_SUPPORT_CG; 5899 pp_state |= PP_STATE_CG; 5900 } 5901 if (state == AMD_CG_STATE_UNGATE) 5902 pp_state = 0; 5903 5904 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5905 PP_BLOCK_GFX_CG, 5906 pp_support_state, 5907 pp_state); 5908 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5909 } 5910 5911 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) { 5912 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5913 pp_support_state = PP_STATE_SUPPORT_LS; 5914 pp_state = PP_STATE_LS; 5915 } 5916 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5917 pp_support_state |= PP_STATE_SUPPORT_CG; 5918 pp_state |= PP_STATE_CG; 5919 } 5920 if (state == AMD_CG_STATE_UNGATE) 5921 pp_state = 0; 5922 5923 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5924 PP_BLOCK_GFX_3D, 5925 pp_support_state, 5926 pp_state); 5927 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5928 } 5929 5930 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 5931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5932 pp_support_state = PP_STATE_SUPPORT_LS; 5933 pp_state = PP_STATE_LS; 5934 } 5935 5936 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5937 pp_support_state |= PP_STATE_SUPPORT_CG; 5938 pp_state |= PP_STATE_CG; 5939 } 5940 5941 if (state == AMD_CG_STATE_UNGATE) 5942 pp_state = 0; 5943 5944 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5945 PP_BLOCK_GFX_MG, 5946 pp_support_state, 5947 pp_state); 5948 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5949 } 5950 5951 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 5952 pp_support_state = PP_STATE_SUPPORT_LS; 5953 5954 if (state == AMD_CG_STATE_UNGATE) 5955 pp_state = 0; 5956 else 5957 pp_state = PP_STATE_LS; 5958 5959 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5960 PP_BLOCK_GFX_RLC, 5961 pp_support_state, 5962 pp_state); 5963 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5964 } 5965 5966 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 5967 pp_support_state = PP_STATE_SUPPORT_LS; 5968 5969 if (state == AMD_CG_STATE_UNGATE) 5970 pp_state = 0; 5971 else 5972 pp_state = PP_STATE_LS; 5973 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5974 PP_BLOCK_GFX_CP, 5975 pp_support_state, 5976 pp_state); 5977 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5978 } 5979 5980 return 0; 5981 } 5982 5983 static int gfx_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5984 enum amd_clockgating_state state) 5985 { 5986 struct amdgpu_device *adev = ip_block->adev; 5987 5988 if (amdgpu_sriov_vf(adev)) 5989 return 0; 5990 5991 switch (adev->asic_type) { 5992 case CHIP_FIJI: 5993 case CHIP_CARRIZO: 5994 case CHIP_STONEY: 5995 gfx_v8_0_update_gfx_clock_gating(adev, 5996 state == AMD_CG_STATE_GATE); 5997 break; 5998 case CHIP_TONGA: 5999 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state); 6000 break; 6001 case CHIP_POLARIS10: 6002 case CHIP_POLARIS11: 6003 case CHIP_POLARIS12: 6004 case CHIP_VEGAM: 6005 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state); 6006 break; 6007 default: 6008 break; 6009 } 6010 return 0; 6011 } 6012 6013 static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring) 6014 { 6015 return *ring->rptr_cpu_addr; 6016 } 6017 6018 static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 6019 { 6020 struct amdgpu_device *adev = ring->adev; 6021 6022 if (ring->use_doorbell) 6023 /* XXX check if swapping is necessary on BE */ 6024 return *ring->wptr_cpu_addr; 6025 else 6026 return RREG32(mmCP_RB0_WPTR); 6027 } 6028 6029 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 6030 { 6031 struct amdgpu_device *adev = ring->adev; 6032 6033 if (ring->use_doorbell) { 6034 /* XXX check if swapping is necessary on BE */ 6035 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 6036 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 6037 } else { 6038 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6039 (void)RREG32(mmCP_RB0_WPTR); 6040 } 6041 } 6042 6043 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 6044 { 6045 u32 ref_and_mask, reg_mem_engine; 6046 6047 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || 6048 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { 6049 switch (ring->me) { 6050 case 1: 6051 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 6052 break; 6053 case 2: 6054 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 6055 break; 6056 default: 6057 return; 6058 } 6059 reg_mem_engine = 0; 6060 } else { 6061 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 6062 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ 6063 } 6064 6065 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6066 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 6067 WAIT_REG_MEM_FUNCTION(3) | /* == */ 6068 reg_mem_engine)); 6069 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 6070 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 6071 amdgpu_ring_write(ring, ref_and_mask); 6072 amdgpu_ring_write(ring, ref_and_mask); 6073 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6074 } 6075 6076 static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 6077 { 6078 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 6079 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 6080 EVENT_INDEX(4)); 6081 6082 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 6083 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 6084 EVENT_INDEX(0)); 6085 } 6086 6087 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 6088 struct amdgpu_job *job, 6089 struct amdgpu_ib *ib, 6090 uint32_t flags) 6091 { 6092 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 6093 u32 header, control = 0; 6094 6095 if (ib->flags & AMDGPU_IB_FLAG_CE) 6096 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 6097 else 6098 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 6099 6100 control |= ib->length_dw | (vmid << 24); 6101 6102 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 6103 control |= INDIRECT_BUFFER_PRE_ENB(1); 6104 6105 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 6106 gfx_v8_0_ring_emit_de_meta(ring); 6107 } 6108 6109 amdgpu_ring_write(ring, header); 6110 amdgpu_ring_write(ring, 6111 #ifdef __BIG_ENDIAN 6112 (2 << 0) | 6113 #endif 6114 (ib->gpu_addr & 0xFFFFFFFC)); 6115 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 6116 amdgpu_ring_write(ring, control); 6117 } 6118 6119 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 6120 struct amdgpu_job *job, 6121 struct amdgpu_ib *ib, 6122 uint32_t flags) 6123 { 6124 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 6125 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 6126 6127 /* Currently, there is a high possibility to get wave ID mismatch 6128 * between ME and GDS, leading to a hw deadlock, because ME generates 6129 * different wave IDs than the GDS expects. This situation happens 6130 * randomly when at least 5 compute pipes use GDS ordered append. 6131 * The wave IDs generated by ME are also wrong after suspend/resume. 6132 * Those are probably bugs somewhere else in the kernel driver. 6133 * 6134 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 6135 * GDS to 0 for this ring (me/pipe). 6136 */ 6137 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 6138 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 6139 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 6140 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 6141 } 6142 6143 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 6144 amdgpu_ring_write(ring, 6145 #ifdef __BIG_ENDIAN 6146 (2 << 0) | 6147 #endif 6148 (ib->gpu_addr & 0xFFFFFFFC)); 6149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 6150 amdgpu_ring_write(ring, control); 6151 } 6152 6153 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 6154 u64 seq, unsigned flags) 6155 { 6156 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 6157 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 6158 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 6159 6160 /* Workaround for cache flush problems. First send a dummy EOP 6161 * event down the pipe with seq one below. 6162 */ 6163 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 6164 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 6165 EOP_TC_ACTION_EN | 6166 EOP_TC_WB_ACTION_EN | 6167 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6168 EVENT_INDEX(5))); 6169 amdgpu_ring_write(ring, addr & 0xfffffffc); 6170 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 6171 DATA_SEL(1) | INT_SEL(0)); 6172 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 6173 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 6174 6175 /* Then send the real EOP event down the pipe: 6176 * EVENT_WRITE_EOP - flush caches, send int */ 6177 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 6178 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 6179 EOP_TC_ACTION_EN | 6180 EOP_TC_WB_ACTION_EN | 6181 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6182 EVENT_INDEX(5) | 6183 (exec ? EOP_EXEC : 0))); 6184 amdgpu_ring_write(ring, addr & 0xfffffffc); 6185 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 6186 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 6187 amdgpu_ring_write(ring, lower_32_bits(seq)); 6188 amdgpu_ring_write(ring, upper_32_bits(seq)); 6189 6190 } 6191 6192 static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 6193 { 6194 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6195 uint32_t seq = ring->fence_drv.sync_seq; 6196 uint64_t addr = ring->fence_drv.gpu_addr; 6197 6198 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6199 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 6200 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 6201 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 6202 amdgpu_ring_write(ring, addr & 0xfffffffc); 6203 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 6204 amdgpu_ring_write(ring, seq); 6205 amdgpu_ring_write(ring, 0xffffffff); 6206 amdgpu_ring_write(ring, 4); /* poll interval */ 6207 } 6208 6209 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 6210 unsigned vmid, uint64_t pd_addr) 6211 { 6212 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6213 6214 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 6215 6216 /* wait for the invalidate to complete */ 6217 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6218 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 6219 WAIT_REG_MEM_FUNCTION(0) | /* always */ 6220 WAIT_REG_MEM_ENGINE(0))); /* me */ 6221 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 6222 amdgpu_ring_write(ring, 0); 6223 amdgpu_ring_write(ring, 0); /* ref */ 6224 amdgpu_ring_write(ring, 0); /* mask */ 6225 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6226 6227 /* compute doesn't have PFP */ 6228 if (usepfp) { 6229 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 6230 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 6231 amdgpu_ring_write(ring, 0x0); 6232 } 6233 } 6234 6235 static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 6236 { 6237 return *ring->wptr_cpu_addr; 6238 } 6239 6240 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 6241 { 6242 struct amdgpu_device *adev = ring->adev; 6243 6244 /* XXX check if swapping is necessary on BE */ 6245 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 6246 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 6247 } 6248 6249 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 6250 u64 addr, u64 seq, 6251 unsigned flags) 6252 { 6253 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 6254 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 6255 6256 /* RELEASE_MEM - flush caches, send int */ 6257 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 6258 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 6259 EOP_TC_ACTION_EN | 6260 EOP_TC_WB_ACTION_EN | 6261 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6262 EVENT_INDEX(5))); 6263 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 6264 amdgpu_ring_write(ring, addr & 0xfffffffc); 6265 amdgpu_ring_write(ring, upper_32_bits(addr)); 6266 amdgpu_ring_write(ring, lower_32_bits(seq)); 6267 amdgpu_ring_write(ring, upper_32_bits(seq)); 6268 } 6269 6270 static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 6271 u64 seq, unsigned int flags) 6272 { 6273 /* we only allocate 32bit for each seq wb address */ 6274 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 6275 6276 /* write fence seq to the "addr" */ 6277 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6278 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6279 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 6280 amdgpu_ring_write(ring, lower_32_bits(addr)); 6281 amdgpu_ring_write(ring, upper_32_bits(addr)); 6282 amdgpu_ring_write(ring, lower_32_bits(seq)); 6283 6284 if (flags & AMDGPU_FENCE_FLAG_INT) { 6285 /* set register to trigger INT */ 6286 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6287 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6288 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 6289 amdgpu_ring_write(ring, mmCPC_INT_STATUS); 6290 amdgpu_ring_write(ring, 0); 6291 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 6292 } 6293 } 6294 6295 static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring) 6296 { 6297 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 6298 amdgpu_ring_write(ring, 0); 6299 } 6300 6301 static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 6302 { 6303 uint32_t dw2 = 0; 6304 6305 if (amdgpu_sriov_vf(ring->adev)) 6306 gfx_v8_0_ring_emit_ce_meta(ring); 6307 6308 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6309 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6310 gfx_v8_0_ring_emit_vgt_flush(ring); 6311 /* set load_global_config & load_global_uconfig */ 6312 dw2 |= 0x8001; 6313 /* set load_cs_sh_regs */ 6314 dw2 |= 0x01000000; 6315 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 6316 dw2 |= 0x10002; 6317 6318 /* set load_ce_ram if preamble presented */ 6319 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 6320 dw2 |= 0x10000000; 6321 } else { 6322 /* still load_ce_ram if this is the first time preamble presented 6323 * although there is no context switch happens. 6324 */ 6325 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 6326 dw2 |= 0x10000000; 6327 } 6328 6329 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6330 amdgpu_ring_write(ring, dw2); 6331 amdgpu_ring_write(ring, 0); 6332 } 6333 6334 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 6335 uint64_t addr) 6336 { 6337 unsigned ret; 6338 6339 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6340 amdgpu_ring_write(ring, lower_32_bits(addr)); 6341 amdgpu_ring_write(ring, upper_32_bits(addr)); 6342 /* discard following DWs if *cond_exec_gpu_addr==0 */ 6343 amdgpu_ring_write(ring, 0); 6344 ret = ring->wptr & ring->buf_mask; 6345 /* patch dummy value later */ 6346 amdgpu_ring_write(ring, 0); 6347 return ret; 6348 } 6349 6350 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6351 uint32_t reg_val_offs) 6352 { 6353 struct amdgpu_device *adev = ring->adev; 6354 6355 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6356 amdgpu_ring_write(ring, 0 | /* src: register*/ 6357 (5 << 8) | /* dst: memory */ 6358 (1 << 20)); /* write confirm */ 6359 amdgpu_ring_write(ring, reg); 6360 amdgpu_ring_write(ring, 0); 6361 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6362 reg_val_offs * 4)); 6363 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6364 reg_val_offs * 4)); 6365 } 6366 6367 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6368 uint32_t val) 6369 { 6370 uint32_t cmd; 6371 6372 switch (ring->funcs->type) { 6373 case AMDGPU_RING_TYPE_GFX: 6374 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6375 break; 6376 case AMDGPU_RING_TYPE_KIQ: 6377 cmd = 1 << 16; /* no inc addr */ 6378 break; 6379 default: 6380 cmd = WR_CONFIRM; 6381 break; 6382 } 6383 6384 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6385 amdgpu_ring_write(ring, cmd); 6386 amdgpu_ring_write(ring, reg); 6387 amdgpu_ring_write(ring, 0); 6388 amdgpu_ring_write(ring, val); 6389 } 6390 6391 static void gfx_v8_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 6392 int mem_space, int opt, uint32_t addr0, 6393 uint32_t addr1, uint32_t ref, uint32_t mask, 6394 uint32_t inv) 6395 { 6396 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6397 amdgpu_ring_write(ring, 6398 /* memory (1) or register (0) */ 6399 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 6400 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 6401 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 6402 WAIT_REG_MEM_ENGINE(eng_sel))); 6403 6404 if (mem_space) 6405 BUG_ON(addr0 & 0x3); /* Dword align */ 6406 amdgpu_ring_write(ring, addr0); 6407 amdgpu_ring_write(ring, addr1); 6408 amdgpu_ring_write(ring, ref); 6409 amdgpu_ring_write(ring, mask); 6410 amdgpu_ring_write(ring, inv); /* poll interval */ 6411 } 6412 6413 static void gfx_v8_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6414 uint32_t val, uint32_t mask) 6415 { 6416 gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6417 } 6418 6419 static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 6420 { 6421 struct amdgpu_device *adev = ring->adev; 6422 uint32_t value = 0; 6423 6424 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6425 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6426 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6427 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6428 WREG32(mmSQ_CMD, value); 6429 } 6430 6431 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6432 enum amdgpu_interrupt_state state) 6433 { 6434 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 6435 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6436 } 6437 6438 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6439 int me, int pipe, 6440 enum amdgpu_interrupt_state state) 6441 { 6442 u32 mec_int_cntl, mec_int_cntl_reg; 6443 6444 /* 6445 * amdgpu controls only the first MEC. That's why this function only 6446 * handles the setting of interrupts for this specific MEC. All other 6447 * pipes' interrupts are set by amdkfd. 6448 */ 6449 6450 if (me == 1) { 6451 switch (pipe) { 6452 case 0: 6453 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 6454 break; 6455 case 1: 6456 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 6457 break; 6458 case 2: 6459 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 6460 break; 6461 case 3: 6462 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 6463 break; 6464 default: 6465 DRM_DEBUG("invalid pipe %d\n", pipe); 6466 return; 6467 } 6468 } else { 6469 DRM_DEBUG("invalid me %d\n", me); 6470 return; 6471 } 6472 6473 switch (state) { 6474 case AMDGPU_IRQ_STATE_DISABLE: 6475 mec_int_cntl = RREG32(mec_int_cntl_reg); 6476 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6477 WREG32(mec_int_cntl_reg, mec_int_cntl); 6478 break; 6479 case AMDGPU_IRQ_STATE_ENABLE: 6480 mec_int_cntl = RREG32(mec_int_cntl_reg); 6481 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6482 WREG32(mec_int_cntl_reg, mec_int_cntl); 6483 break; 6484 default: 6485 break; 6486 } 6487 } 6488 6489 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6490 struct amdgpu_irq_src *source, 6491 unsigned type, 6492 enum amdgpu_interrupt_state state) 6493 { 6494 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, 6495 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6496 6497 return 0; 6498 } 6499 6500 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6501 struct amdgpu_irq_src *source, 6502 unsigned type, 6503 enum amdgpu_interrupt_state state) 6504 { 6505 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, 6506 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6507 6508 return 0; 6509 } 6510 6511 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6512 struct amdgpu_irq_src *src, 6513 unsigned type, 6514 enum amdgpu_interrupt_state state) 6515 { 6516 switch (type) { 6517 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6518 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); 6519 break; 6520 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6521 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6522 break; 6523 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6524 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6525 break; 6526 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6527 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6528 break; 6529 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6530 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6531 break; 6532 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 6533 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 6534 break; 6535 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 6536 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 6537 break; 6538 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 6539 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 6540 break; 6541 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 6542 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 6543 break; 6544 default: 6545 break; 6546 } 6547 return 0; 6548 } 6549 6550 static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev, 6551 struct amdgpu_irq_src *source, 6552 unsigned int type, 6553 enum amdgpu_interrupt_state state) 6554 { 6555 int enable_flag; 6556 6557 switch (state) { 6558 case AMDGPU_IRQ_STATE_DISABLE: 6559 enable_flag = 0; 6560 break; 6561 6562 case AMDGPU_IRQ_STATE_ENABLE: 6563 enable_flag = 1; 6564 break; 6565 6566 default: 6567 return -EINVAL; 6568 } 6569 6570 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag); 6571 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); 6572 WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag); 6573 WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag); 6574 WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag); 6575 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6576 enable_flag); 6577 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6578 enable_flag); 6579 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6580 enable_flag); 6581 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6582 enable_flag); 6583 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6584 enable_flag); 6585 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6586 enable_flag); 6587 WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6588 enable_flag); 6589 WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, 6590 enable_flag); 6591 6592 return 0; 6593 } 6594 6595 static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev, 6596 struct amdgpu_irq_src *source, 6597 unsigned int type, 6598 enum amdgpu_interrupt_state state) 6599 { 6600 int enable_flag; 6601 6602 switch (state) { 6603 case AMDGPU_IRQ_STATE_DISABLE: 6604 enable_flag = 1; 6605 break; 6606 6607 case AMDGPU_IRQ_STATE_ENABLE: 6608 enable_flag = 0; 6609 break; 6610 6611 default: 6612 return -EINVAL; 6613 } 6614 6615 WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL, 6616 enable_flag); 6617 6618 return 0; 6619 } 6620 6621 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, 6622 struct amdgpu_irq_src *source, 6623 struct amdgpu_iv_entry *entry) 6624 { 6625 int i; 6626 u8 me_id, pipe_id, queue_id; 6627 struct amdgpu_ring *ring; 6628 6629 DRM_DEBUG("IH: CP EOP\n"); 6630 me_id = (entry->ring_id & 0x0c) >> 2; 6631 pipe_id = (entry->ring_id & 0x03) >> 0; 6632 queue_id = (entry->ring_id & 0x70) >> 4; 6633 6634 switch (me_id) { 6635 case 0: 6636 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6637 break; 6638 case 1: 6639 case 2: 6640 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6641 ring = &adev->gfx.compute_ring[i]; 6642 /* Per-queue interrupt is supported for MEC starting from VI. 6643 * The interrupt can only be enabled/disabled per pipe instead of per queue. 6644 */ 6645 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 6646 amdgpu_fence_process(ring); 6647 } 6648 break; 6649 } 6650 return 0; 6651 } 6652 6653 static void gfx_v8_0_fault(struct amdgpu_device *adev, 6654 struct amdgpu_iv_entry *entry) 6655 { 6656 u8 me_id, pipe_id, queue_id; 6657 struct amdgpu_ring *ring; 6658 int i; 6659 6660 me_id = (entry->ring_id & 0x0c) >> 2; 6661 pipe_id = (entry->ring_id & 0x03) >> 0; 6662 queue_id = (entry->ring_id & 0x70) >> 4; 6663 6664 switch (me_id) { 6665 case 0: 6666 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 6667 break; 6668 case 1: 6669 case 2: 6670 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6671 ring = &adev->gfx.compute_ring[i]; 6672 if (ring->me == me_id && ring->pipe == pipe_id && 6673 ring->queue == queue_id) 6674 drm_sched_fault(&ring->sched); 6675 } 6676 break; 6677 } 6678 } 6679 6680 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, 6681 struct amdgpu_irq_src *source, 6682 struct amdgpu_iv_entry *entry) 6683 { 6684 DRM_ERROR("Illegal register access in command stream\n"); 6685 gfx_v8_0_fault(adev, entry); 6686 return 0; 6687 } 6688 6689 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, 6690 struct amdgpu_irq_src *source, 6691 struct amdgpu_iv_entry *entry) 6692 { 6693 DRM_ERROR("Illegal instruction in command stream\n"); 6694 gfx_v8_0_fault(adev, entry); 6695 return 0; 6696 } 6697 6698 static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev, 6699 struct amdgpu_irq_src *source, 6700 struct amdgpu_iv_entry *entry) 6701 { 6702 DRM_ERROR("CP EDC/ECC error detected."); 6703 return 0; 6704 } 6705 6706 static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data, 6707 bool from_wq) 6708 { 6709 u32 enc, se_id, sh_id, cu_id; 6710 char type[20]; 6711 int sq_edc_source = -1; 6712 6713 enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING); 6714 se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID); 6715 6716 switch (enc) { 6717 case 0: 6718 DRM_INFO("SQ general purpose intr detected:" 6719 "se_id %d, immed_overflow %d, host_reg_overflow %d," 6720 "host_cmd_overflow %d, cmd_timestamp %d," 6721 "reg_timestamp %d, thread_trace_buff_full %d," 6722 "wlt %d, thread_trace %d.\n", 6723 se_id, 6724 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW), 6725 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW), 6726 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW), 6727 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP), 6728 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP), 6729 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL), 6730 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT), 6731 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE) 6732 ); 6733 break; 6734 case 1: 6735 case 2: 6736 6737 cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID); 6738 sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID); 6739 6740 /* 6741 * This function can be called either directly from ISR 6742 * or from BH in which case we can access SQ_EDC_INFO 6743 * instance 6744 */ 6745 if (from_wq) { 6746 mutex_lock(&adev->grbm_idx_mutex); 6747 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0); 6748 6749 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE); 6750 6751 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6752 mutex_unlock(&adev->grbm_idx_mutex); 6753 } 6754 6755 if (enc == 1) 6756 sprintf(type, "instruction intr"); 6757 else 6758 sprintf(type, "EDC/ECC error"); 6759 6760 DRM_INFO( 6761 "SQ %s detected: " 6762 "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d " 6763 "trap %s, sq_ed_info.source %s.\n", 6764 type, se_id, sh_id, cu_id, 6765 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID), 6766 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID), 6767 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID), 6768 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false", 6769 (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable" 6770 ); 6771 break; 6772 default: 6773 DRM_ERROR("SQ invalid encoding type\n."); 6774 } 6775 } 6776 6777 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work) 6778 { 6779 6780 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); 6781 struct sq_work *sq_work = container_of(work, struct sq_work, work); 6782 6783 gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true); 6784 } 6785 6786 static int gfx_v8_0_sq_irq(struct amdgpu_device *adev, 6787 struct amdgpu_irq_src *source, 6788 struct amdgpu_iv_entry *entry) 6789 { 6790 unsigned ih_data = entry->src_data[0]; 6791 6792 /* 6793 * Try to submit work so SQ_EDC_INFO can be accessed from 6794 * BH. If previous work submission hasn't finished yet 6795 * just print whatever info is possible directly from the ISR. 6796 */ 6797 if (work_pending(&adev->gfx.sq_work.work)) { 6798 gfx_v8_0_parse_sq_irq(adev, ih_data, false); 6799 } else { 6800 adev->gfx.sq_work.ih_data = ih_data; 6801 schedule_work(&adev->gfx.sq_work.work); 6802 } 6803 6804 return 0; 6805 } 6806 6807 static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring) 6808 { 6809 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 6810 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 6811 PACKET3_TC_ACTION_ENA | 6812 PACKET3_SH_KCACHE_ACTION_ENA | 6813 PACKET3_SH_ICACHE_ACTION_ENA | 6814 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */ 6815 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6816 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6817 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 6818 } 6819 6820 static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) 6821 { 6822 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6823 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 6824 PACKET3_TC_ACTION_ENA | 6825 PACKET3_SH_KCACHE_ACTION_ENA | 6826 PACKET3_SH_ICACHE_ACTION_ENA | 6827 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */ 6828 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6829 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ 6830 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6831 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6832 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 6833 } 6834 6835 6836 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6837 #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f 6838 static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6839 uint32_t pipe, bool enable) 6840 { 6841 uint32_t val; 6842 uint32_t wcl_cs_reg; 6843 6844 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT; 6845 6846 switch (pipe) { 6847 case 0: 6848 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0; 6849 break; 6850 case 1: 6851 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1; 6852 break; 6853 case 2: 6854 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2; 6855 break; 6856 case 3: 6857 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; 6858 break; 6859 default: 6860 DRM_DEBUG("invalid pipe %d\n", pipe); 6861 return; 6862 } 6863 6864 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6865 6866 } 6867 6868 #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff 6869 static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6870 { 6871 struct amdgpu_device *adev = ring->adev; 6872 uint32_t val; 6873 int i; 6874 6875 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6876 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6877 * around 25% of gpu resources. 6878 */ 6879 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6880 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); 6881 6882 /* Restrict waves for normal/low priority compute queues as well 6883 * to get best QoS for high priority compute jobs. 6884 * 6885 * amdgpu controls only 1st ME(0-3 CS pipes). 6886 */ 6887 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6888 if (i != ring->pipe) 6889 gfx_v8_0_emit_wave_limit_cs(ring, i, enable); 6890 6891 } 6892 6893 } 6894 6895 static int gfx_v8_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 6896 { 6897 struct amdgpu_device *adev = ring->adev; 6898 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6899 struct amdgpu_ring *kiq_ring = &kiq->ring; 6900 unsigned long flags; 6901 u32 tmp; 6902 int r; 6903 6904 if (amdgpu_sriov_vf(adev)) 6905 return -EINVAL; 6906 6907 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6908 return -EINVAL; 6909 6910 spin_lock_irqsave(&kiq->ring_lock, flags); 6911 6912 if (amdgpu_ring_alloc(kiq_ring, 5)) { 6913 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6914 return -ENOMEM; 6915 } 6916 6917 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 6918 gfx_v8_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp); 6919 amdgpu_ring_commit(kiq_ring); 6920 6921 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6922 6923 r = amdgpu_ring_test_ring(kiq_ring); 6924 if (r) 6925 return r; 6926 6927 if (amdgpu_ring_alloc(ring, 7 + 12 + 5)) 6928 return -ENOMEM; 6929 gfx_v8_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr, 6930 ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC); 6931 gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff); 6932 gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0); 6933 6934 return amdgpu_ring_test_ring(ring); 6935 } 6936 6937 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { 6938 .name = "gfx_v8_0", 6939 .early_init = gfx_v8_0_early_init, 6940 .late_init = gfx_v8_0_late_init, 6941 .sw_init = gfx_v8_0_sw_init, 6942 .sw_fini = gfx_v8_0_sw_fini, 6943 .hw_init = gfx_v8_0_hw_init, 6944 .hw_fini = gfx_v8_0_hw_fini, 6945 .suspend = gfx_v8_0_suspend, 6946 .resume = gfx_v8_0_resume, 6947 .is_idle = gfx_v8_0_is_idle, 6948 .wait_for_idle = gfx_v8_0_wait_for_idle, 6949 .check_soft_reset = gfx_v8_0_check_soft_reset, 6950 .pre_soft_reset = gfx_v8_0_pre_soft_reset, 6951 .soft_reset = gfx_v8_0_soft_reset, 6952 .post_soft_reset = gfx_v8_0_post_soft_reset, 6953 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 6954 .set_powergating_state = gfx_v8_0_set_powergating_state, 6955 .get_clockgating_state = gfx_v8_0_get_clockgating_state, 6956 }; 6957 6958 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 6959 .type = AMDGPU_RING_TYPE_GFX, 6960 .align_mask = 0xff, 6961 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6962 .support_64bit_ptrs = false, 6963 .get_rptr = gfx_v8_0_ring_get_rptr, 6964 .get_wptr = gfx_v8_0_ring_get_wptr_gfx, 6965 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 6966 .emit_frame_size = /* maximum 215dw if count 16 IBs in */ 6967 5 + /* COND_EXEC */ 6968 7 + /* PIPELINE_SYNC */ 6969 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */ 6970 12 + /* FENCE for VM_FLUSH */ 6971 20 + /* GDS switch */ 6972 4 + /* double SWITCH_BUFFER, 6973 the first COND_EXEC jump to the place just 6974 prior to this double SWITCH_BUFFER */ 6975 5 + /* COND_EXEC */ 6976 7 + /* HDP_flush */ 6977 4 + /* VGT_flush */ 6978 14 + /* CE_META */ 6979 31 + /* DE_META */ 6980 3 + /* CNTX_CTRL */ 6981 5 + /* HDP_INVL */ 6982 12 + 12 + /* FENCE x2 */ 6983 2 + /* SWITCH_BUFFER */ 6984 5, /* SURFACE_SYNC */ 6985 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ 6986 .emit_ib = gfx_v8_0_ring_emit_ib_gfx, 6987 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 6988 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, 6989 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 6990 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 6991 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 6992 .test_ring = gfx_v8_0_ring_test_ring, 6993 .test_ib = gfx_v8_0_ring_test_ib, 6994 .insert_nop = amdgpu_ring_insert_nop, 6995 .pad_ib = amdgpu_ring_generic_pad_ib, 6996 .emit_switch_buffer = gfx_v8_ring_emit_sb, 6997 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, 6998 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, 6999 .emit_wreg = gfx_v8_0_ring_emit_wreg, 7000 .soft_recovery = gfx_v8_0_ring_soft_recovery, 7001 .emit_mem_sync = gfx_v8_0_emit_mem_sync, 7002 .reset = gfx_v8_0_reset_kgq, 7003 }; 7004 7005 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 7006 .type = AMDGPU_RING_TYPE_COMPUTE, 7007 .align_mask = 0xff, 7008 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7009 .support_64bit_ptrs = false, 7010 .get_rptr = gfx_v8_0_ring_get_rptr, 7011 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 7012 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 7013 .emit_frame_size = 7014 20 + /* gfx_v8_0_ring_emit_gds_switch */ 7015 7 + /* gfx_v8_0_ring_emit_hdp_flush */ 7016 5 + /* hdp_invalidate */ 7017 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 7018 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */ 7019 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ 7020 7 + /* gfx_v8_0_emit_mem_sync_compute */ 7021 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 7022 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 7023 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */ 7024 .emit_ib = gfx_v8_0_ring_emit_ib_compute, 7025 .emit_fence = gfx_v8_0_ring_emit_fence_compute, 7026 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, 7027 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 7028 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 7029 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 7030 .test_ring = gfx_v8_0_ring_test_ring, 7031 .test_ib = gfx_v8_0_ring_test_ib, 7032 .insert_nop = amdgpu_ring_insert_nop, 7033 .pad_ib = amdgpu_ring_generic_pad_ib, 7034 .emit_wreg = gfx_v8_0_ring_emit_wreg, 7035 .soft_recovery = gfx_v8_0_ring_soft_recovery, 7036 .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute, 7037 .emit_wave_limit = gfx_v8_0_emit_wave_limit, 7038 }; 7039 7040 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { 7041 .type = AMDGPU_RING_TYPE_KIQ, 7042 .align_mask = 0xff, 7043 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7044 .support_64bit_ptrs = false, 7045 .get_rptr = gfx_v8_0_ring_get_rptr, 7046 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 7047 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 7048 .emit_frame_size = 7049 20 + /* gfx_v8_0_ring_emit_gds_switch */ 7050 7 + /* gfx_v8_0_ring_emit_hdp_flush */ 7051 5 + /* hdp_invalidate */ 7052 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 7053 17 + /* gfx_v8_0_ring_emit_vm_flush */ 7054 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7055 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */ 7056 .emit_fence = gfx_v8_0_ring_emit_fence_kiq, 7057 .test_ring = gfx_v8_0_ring_test_ring, 7058 .insert_nop = amdgpu_ring_insert_nop, 7059 .pad_ib = amdgpu_ring_generic_pad_ib, 7060 .emit_rreg = gfx_v8_0_ring_emit_rreg, 7061 .emit_wreg = gfx_v8_0_ring_emit_wreg, 7062 }; 7063 7064 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) 7065 { 7066 int i; 7067 7068 adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq; 7069 7070 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7071 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; 7072 7073 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7074 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; 7075 } 7076 7077 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { 7078 .set = gfx_v8_0_set_eop_interrupt_state, 7079 .process = gfx_v8_0_eop_irq, 7080 }; 7081 7082 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { 7083 .set = gfx_v8_0_set_priv_reg_fault_state, 7084 .process = gfx_v8_0_priv_reg_irq, 7085 }; 7086 7087 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { 7088 .set = gfx_v8_0_set_priv_inst_fault_state, 7089 .process = gfx_v8_0_priv_inst_irq, 7090 }; 7091 7092 static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = { 7093 .set = gfx_v8_0_set_cp_ecc_int_state, 7094 .process = gfx_v8_0_cp_ecc_error_irq, 7095 }; 7096 7097 static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = { 7098 .set = gfx_v8_0_set_sq_int_state, 7099 .process = gfx_v8_0_sq_irq, 7100 }; 7101 7102 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) 7103 { 7104 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7105 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; 7106 7107 adev->gfx.priv_reg_irq.num_types = 1; 7108 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; 7109 7110 adev->gfx.priv_inst_irq.num_types = 1; 7111 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; 7112 7113 adev->gfx.cp_ecc_error_irq.num_types = 1; 7114 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; 7115 7116 adev->gfx.sq_irq.num_types = 1; 7117 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; 7118 } 7119 7120 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev) 7121 { 7122 adev->gfx.rlc.funcs = &iceland_rlc_funcs; 7123 } 7124 7125 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) 7126 { 7127 /* init asci gds info */ 7128 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 7129 adev->gds.gws_size = 64; 7130 adev->gds.oa_size = 16; 7131 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 7132 } 7133 7134 static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7135 u32 bitmap) 7136 { 7137 u32 data; 7138 7139 if (!bitmap) 7140 return; 7141 7142 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7143 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7144 7145 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 7146 } 7147 7148 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7149 { 7150 u32 data, mask; 7151 7152 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 7153 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 7154 7155 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7156 7157 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 7158 } 7159 7160 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) 7161 { 7162 int i, j, k, counter, active_cu_number = 0; 7163 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7164 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 7165 unsigned disable_masks[4 * 2]; 7166 u32 ao_cu_num; 7167 7168 memset(cu_info, 0, sizeof(*cu_info)); 7169 7170 if (adev->flags & AMD_IS_APU) 7171 ao_cu_num = 2; 7172 else 7173 ao_cu_num = adev->gfx.config.max_cu_per_sh; 7174 7175 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 7176 7177 mutex_lock(&adev->grbm_idx_mutex); 7178 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7179 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7180 mask = 1; 7181 ao_bitmap = 0; 7182 counter = 0; 7183 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7184 if (i < 4 && j < 2) 7185 gfx_v8_0_set_user_cu_inactive_bitmap( 7186 adev, disable_masks[i * 2 + j]); 7187 bitmap = gfx_v8_0_get_cu_active_bitmap(adev); 7188 cu_info->bitmap[0][i][j] = bitmap; 7189 7190 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7191 if (bitmap & mask) { 7192 if (counter < ao_cu_num) 7193 ao_bitmap |= mask; 7194 counter ++; 7195 } 7196 mask <<= 1; 7197 } 7198 active_cu_number += counter; 7199 if (i < 2 && j < 2) 7200 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7201 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 7202 } 7203 } 7204 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7205 mutex_unlock(&adev->grbm_idx_mutex); 7206 7207 cu_info->number = active_cu_number; 7208 cu_info->ao_cu_mask = ao_cu_mask; 7209 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7210 cu_info->max_waves_per_simd = 10; 7211 cu_info->max_scratch_slots_per_cu = 32; 7212 cu_info->wave_front_size = 64; 7213 cu_info->lds_size = 64; 7214 } 7215 7216 const struct amdgpu_ip_block_version gfx_v8_0_ip_block = 7217 { 7218 .type = AMD_IP_BLOCK_TYPE_GFX, 7219 .major = 8, 7220 .minor = 0, 7221 .rev = 0, 7222 .funcs = &gfx_v8_0_ip_funcs, 7223 }; 7224 7225 const struct amdgpu_ip_block_version gfx_v8_1_ip_block = 7226 { 7227 .type = AMD_IP_BLOCK_TYPE_GFX, 7228 .major = 8, 7229 .minor = 1, 7230 .rev = 0, 7231 .funcs = &gfx_v8_0_ip_funcs, 7232 }; 7233 7234 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 7235 { 7236 uint64_t ce_payload_addr; 7237 int cnt_ce; 7238 union { 7239 struct vi_ce_ib_state regular; 7240 struct vi_ce_ib_state_chained_ib chained; 7241 } ce_payload = {}; 7242 7243 if (ring->adev->virt.chained_ib_support) { 7244 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) + 7245 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); 7246 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2; 7247 } else { 7248 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) + 7249 offsetof(struct vi_gfx_meta_data, ce_payload); 7250 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2; 7251 } 7252 7253 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce)); 7254 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 7255 WRITE_DATA_DST_SEL(8) | 7256 WR_CONFIRM) | 7257 WRITE_DATA_CACHE_POLICY(0)); 7258 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr)); 7259 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr)); 7260 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2); 7261 } 7262 7263 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring) 7264 { 7265 uint64_t de_payload_addr, gds_addr, csa_addr; 7266 int cnt_de; 7267 union { 7268 struct vi_de_ib_state regular; 7269 struct vi_de_ib_state_chained_ib chained; 7270 } de_payload = {}; 7271 7272 csa_addr = amdgpu_csa_vaddr(ring->adev); 7273 gds_addr = csa_addr + 4096; 7274 if (ring->adev->virt.chained_ib_support) { 7275 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr); 7276 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr); 7277 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload); 7278 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2; 7279 } else { 7280 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr); 7281 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr); 7282 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload); 7283 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2; 7284 } 7285 7286 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de)); 7287 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 7288 WRITE_DATA_DST_SEL(8) | 7289 WR_CONFIRM) | 7290 WRITE_DATA_CACHE_POLICY(0)); 7291 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr)); 7292 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr)); 7293 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2); 7294 } 7295