1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ih.h" 27 #include "amdgpu_gfx.h" 28 #include "cikd.h" 29 #include "cik.h" 30 #include "atom.h" 31 #include "amdgpu_ucode.h" 32 #include "clearstate_ci.h" 33 34 #include "dce/dce_8_0_d.h" 35 #include "dce/dce_8_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gca/gfx_7_0_d.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "gca/gfx_7_2_sh_mask.h" 43 44 #include "gmc/gmc_7_0_d.h" 45 #include "gmc/gmc_7_0_sh_mask.h" 46 47 #include "oss/oss_2_0_d.h" 48 #include "oss/oss_2_0_sh_mask.h" 49 50 #define GFX7_NUM_GFX_RINGS 1 51 #define GFX7_NUM_COMPUTE_RINGS 8 52 53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); 58 MODULE_FIRMWARE("radeon/bonaire_me.bin"); 59 MODULE_FIRMWARE("radeon/bonaire_ce.bin"); 60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); 61 MODULE_FIRMWARE("radeon/bonaire_mec.bin"); 62 63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); 64 MODULE_FIRMWARE("radeon/hawaii_me.bin"); 65 MODULE_FIRMWARE("radeon/hawaii_ce.bin"); 66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); 67 MODULE_FIRMWARE("radeon/hawaii_mec.bin"); 68 69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); 70 MODULE_FIRMWARE("radeon/kaveri_me.bin"); 71 MODULE_FIRMWARE("radeon/kaveri_ce.bin"); 72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); 73 MODULE_FIRMWARE("radeon/kaveri_mec.bin"); 74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); 75 76 MODULE_FIRMWARE("radeon/kabini_pfp.bin"); 77 MODULE_FIRMWARE("radeon/kabini_me.bin"); 78 MODULE_FIRMWARE("radeon/kabini_ce.bin"); 79 MODULE_FIRMWARE("radeon/kabini_rlc.bin"); 80 MODULE_FIRMWARE("radeon/kabini_mec.bin"); 81 82 MODULE_FIRMWARE("radeon/mullins_pfp.bin"); 83 MODULE_FIRMWARE("radeon/mullins_me.bin"); 84 MODULE_FIRMWARE("radeon/mullins_ce.bin"); 85 MODULE_FIRMWARE("radeon/mullins_rlc.bin"); 86 MODULE_FIRMWARE("radeon/mullins_mec.bin"); 87 88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 89 { 90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 106 }; 107 108 static const u32 spectre_rlc_save_restore_register_list[] = 109 { 110 (0x0e00 << 16) | (0xc12c >> 2), 111 0x00000000, 112 (0x0e00 << 16) | (0xc140 >> 2), 113 0x00000000, 114 (0x0e00 << 16) | (0xc150 >> 2), 115 0x00000000, 116 (0x0e00 << 16) | (0xc15c >> 2), 117 0x00000000, 118 (0x0e00 << 16) | (0xc168 >> 2), 119 0x00000000, 120 (0x0e00 << 16) | (0xc170 >> 2), 121 0x00000000, 122 (0x0e00 << 16) | (0xc178 >> 2), 123 0x00000000, 124 (0x0e00 << 16) | (0xc204 >> 2), 125 0x00000000, 126 (0x0e00 << 16) | (0xc2b4 >> 2), 127 0x00000000, 128 (0x0e00 << 16) | (0xc2b8 >> 2), 129 0x00000000, 130 (0x0e00 << 16) | (0xc2bc >> 2), 131 0x00000000, 132 (0x0e00 << 16) | (0xc2c0 >> 2), 133 0x00000000, 134 (0x0e00 << 16) | (0x8228 >> 2), 135 0x00000000, 136 (0x0e00 << 16) | (0x829c >> 2), 137 0x00000000, 138 (0x0e00 << 16) | (0x869c >> 2), 139 0x00000000, 140 (0x0600 << 16) | (0x98f4 >> 2), 141 0x00000000, 142 (0x0e00 << 16) | (0x98f8 >> 2), 143 0x00000000, 144 (0x0e00 << 16) | (0x9900 >> 2), 145 0x00000000, 146 (0x0e00 << 16) | (0xc260 >> 2), 147 0x00000000, 148 (0x0e00 << 16) | (0x90e8 >> 2), 149 0x00000000, 150 (0x0e00 << 16) | (0x3c000 >> 2), 151 0x00000000, 152 (0x0e00 << 16) | (0x3c00c >> 2), 153 0x00000000, 154 (0x0e00 << 16) | (0x8c1c >> 2), 155 0x00000000, 156 (0x0e00 << 16) | (0x9700 >> 2), 157 0x00000000, 158 (0x0e00 << 16) | (0xcd20 >> 2), 159 0x00000000, 160 (0x4e00 << 16) | (0xcd20 >> 2), 161 0x00000000, 162 (0x5e00 << 16) | (0xcd20 >> 2), 163 0x00000000, 164 (0x6e00 << 16) | (0xcd20 >> 2), 165 0x00000000, 166 (0x7e00 << 16) | (0xcd20 >> 2), 167 0x00000000, 168 (0x8e00 << 16) | (0xcd20 >> 2), 169 0x00000000, 170 (0x9e00 << 16) | (0xcd20 >> 2), 171 0x00000000, 172 (0xae00 << 16) | (0xcd20 >> 2), 173 0x00000000, 174 (0xbe00 << 16) | (0xcd20 >> 2), 175 0x00000000, 176 (0x0e00 << 16) | (0x89bc >> 2), 177 0x00000000, 178 (0x0e00 << 16) | (0x8900 >> 2), 179 0x00000000, 180 0x3, 181 (0x0e00 << 16) | (0xc130 >> 2), 182 0x00000000, 183 (0x0e00 << 16) | (0xc134 >> 2), 184 0x00000000, 185 (0x0e00 << 16) | (0xc1fc >> 2), 186 0x00000000, 187 (0x0e00 << 16) | (0xc208 >> 2), 188 0x00000000, 189 (0x0e00 << 16) | (0xc264 >> 2), 190 0x00000000, 191 (0x0e00 << 16) | (0xc268 >> 2), 192 0x00000000, 193 (0x0e00 << 16) | (0xc26c >> 2), 194 0x00000000, 195 (0x0e00 << 16) | (0xc270 >> 2), 196 0x00000000, 197 (0x0e00 << 16) | (0xc274 >> 2), 198 0x00000000, 199 (0x0e00 << 16) | (0xc278 >> 2), 200 0x00000000, 201 (0x0e00 << 16) | (0xc27c >> 2), 202 0x00000000, 203 (0x0e00 << 16) | (0xc280 >> 2), 204 0x00000000, 205 (0x0e00 << 16) | (0xc284 >> 2), 206 0x00000000, 207 (0x0e00 << 16) | (0xc288 >> 2), 208 0x00000000, 209 (0x0e00 << 16) | (0xc28c >> 2), 210 0x00000000, 211 (0x0e00 << 16) | (0xc290 >> 2), 212 0x00000000, 213 (0x0e00 << 16) | (0xc294 >> 2), 214 0x00000000, 215 (0x0e00 << 16) | (0xc298 >> 2), 216 0x00000000, 217 (0x0e00 << 16) | (0xc29c >> 2), 218 0x00000000, 219 (0x0e00 << 16) | (0xc2a0 >> 2), 220 0x00000000, 221 (0x0e00 << 16) | (0xc2a4 >> 2), 222 0x00000000, 223 (0x0e00 << 16) | (0xc2a8 >> 2), 224 0x00000000, 225 (0x0e00 << 16) | (0xc2ac >> 2), 226 0x00000000, 227 (0x0e00 << 16) | (0xc2b0 >> 2), 228 0x00000000, 229 (0x0e00 << 16) | (0x301d0 >> 2), 230 0x00000000, 231 (0x0e00 << 16) | (0x30238 >> 2), 232 0x00000000, 233 (0x0e00 << 16) | (0x30250 >> 2), 234 0x00000000, 235 (0x0e00 << 16) | (0x30254 >> 2), 236 0x00000000, 237 (0x0e00 << 16) | (0x30258 >> 2), 238 0x00000000, 239 (0x0e00 << 16) | (0x3025c >> 2), 240 0x00000000, 241 (0x4e00 << 16) | (0xc900 >> 2), 242 0x00000000, 243 (0x5e00 << 16) | (0xc900 >> 2), 244 0x00000000, 245 (0x6e00 << 16) | (0xc900 >> 2), 246 0x00000000, 247 (0x7e00 << 16) | (0xc900 >> 2), 248 0x00000000, 249 (0x8e00 << 16) | (0xc900 >> 2), 250 0x00000000, 251 (0x9e00 << 16) | (0xc900 >> 2), 252 0x00000000, 253 (0xae00 << 16) | (0xc900 >> 2), 254 0x00000000, 255 (0xbe00 << 16) | (0xc900 >> 2), 256 0x00000000, 257 (0x4e00 << 16) | (0xc904 >> 2), 258 0x00000000, 259 (0x5e00 << 16) | (0xc904 >> 2), 260 0x00000000, 261 (0x6e00 << 16) | (0xc904 >> 2), 262 0x00000000, 263 (0x7e00 << 16) | (0xc904 >> 2), 264 0x00000000, 265 (0x8e00 << 16) | (0xc904 >> 2), 266 0x00000000, 267 (0x9e00 << 16) | (0xc904 >> 2), 268 0x00000000, 269 (0xae00 << 16) | (0xc904 >> 2), 270 0x00000000, 271 (0xbe00 << 16) | (0xc904 >> 2), 272 0x00000000, 273 (0x4e00 << 16) | (0xc908 >> 2), 274 0x00000000, 275 (0x5e00 << 16) | (0xc908 >> 2), 276 0x00000000, 277 (0x6e00 << 16) | (0xc908 >> 2), 278 0x00000000, 279 (0x7e00 << 16) | (0xc908 >> 2), 280 0x00000000, 281 (0x8e00 << 16) | (0xc908 >> 2), 282 0x00000000, 283 (0x9e00 << 16) | (0xc908 >> 2), 284 0x00000000, 285 (0xae00 << 16) | (0xc908 >> 2), 286 0x00000000, 287 (0xbe00 << 16) | (0xc908 >> 2), 288 0x00000000, 289 (0x4e00 << 16) | (0xc90c >> 2), 290 0x00000000, 291 (0x5e00 << 16) | (0xc90c >> 2), 292 0x00000000, 293 (0x6e00 << 16) | (0xc90c >> 2), 294 0x00000000, 295 (0x7e00 << 16) | (0xc90c >> 2), 296 0x00000000, 297 (0x8e00 << 16) | (0xc90c >> 2), 298 0x00000000, 299 (0x9e00 << 16) | (0xc90c >> 2), 300 0x00000000, 301 (0xae00 << 16) | (0xc90c >> 2), 302 0x00000000, 303 (0xbe00 << 16) | (0xc90c >> 2), 304 0x00000000, 305 (0x4e00 << 16) | (0xc910 >> 2), 306 0x00000000, 307 (0x5e00 << 16) | (0xc910 >> 2), 308 0x00000000, 309 (0x6e00 << 16) | (0xc910 >> 2), 310 0x00000000, 311 (0x7e00 << 16) | (0xc910 >> 2), 312 0x00000000, 313 (0x8e00 << 16) | (0xc910 >> 2), 314 0x00000000, 315 (0x9e00 << 16) | (0xc910 >> 2), 316 0x00000000, 317 (0xae00 << 16) | (0xc910 >> 2), 318 0x00000000, 319 (0xbe00 << 16) | (0xc910 >> 2), 320 0x00000000, 321 (0x0e00 << 16) | (0xc99c >> 2), 322 0x00000000, 323 (0x0e00 << 16) | (0x9834 >> 2), 324 0x00000000, 325 (0x0000 << 16) | (0x30f00 >> 2), 326 0x00000000, 327 (0x0001 << 16) | (0x30f00 >> 2), 328 0x00000000, 329 (0x0000 << 16) | (0x30f04 >> 2), 330 0x00000000, 331 (0x0001 << 16) | (0x30f04 >> 2), 332 0x00000000, 333 (0x0000 << 16) | (0x30f08 >> 2), 334 0x00000000, 335 (0x0001 << 16) | (0x30f08 >> 2), 336 0x00000000, 337 (0x0000 << 16) | (0x30f0c >> 2), 338 0x00000000, 339 (0x0001 << 16) | (0x30f0c >> 2), 340 0x00000000, 341 (0x0600 << 16) | (0x9b7c >> 2), 342 0x00000000, 343 (0x0e00 << 16) | (0x8a14 >> 2), 344 0x00000000, 345 (0x0e00 << 16) | (0x8a18 >> 2), 346 0x00000000, 347 (0x0600 << 16) | (0x30a00 >> 2), 348 0x00000000, 349 (0x0e00 << 16) | (0x8bf0 >> 2), 350 0x00000000, 351 (0x0e00 << 16) | (0x8bcc >> 2), 352 0x00000000, 353 (0x0e00 << 16) | (0x8b24 >> 2), 354 0x00000000, 355 (0x0e00 << 16) | (0x30a04 >> 2), 356 0x00000000, 357 (0x0600 << 16) | (0x30a10 >> 2), 358 0x00000000, 359 (0x0600 << 16) | (0x30a14 >> 2), 360 0x00000000, 361 (0x0600 << 16) | (0x30a18 >> 2), 362 0x00000000, 363 (0x0600 << 16) | (0x30a2c >> 2), 364 0x00000000, 365 (0x0e00 << 16) | (0xc700 >> 2), 366 0x00000000, 367 (0x0e00 << 16) | (0xc704 >> 2), 368 0x00000000, 369 (0x0e00 << 16) | (0xc708 >> 2), 370 0x00000000, 371 (0x0e00 << 16) | (0xc768 >> 2), 372 0x00000000, 373 (0x0400 << 16) | (0xc770 >> 2), 374 0x00000000, 375 (0x0400 << 16) | (0xc774 >> 2), 376 0x00000000, 377 (0x0400 << 16) | (0xc778 >> 2), 378 0x00000000, 379 (0x0400 << 16) | (0xc77c >> 2), 380 0x00000000, 381 (0x0400 << 16) | (0xc780 >> 2), 382 0x00000000, 383 (0x0400 << 16) | (0xc784 >> 2), 384 0x00000000, 385 (0x0400 << 16) | (0xc788 >> 2), 386 0x00000000, 387 (0x0400 << 16) | (0xc78c >> 2), 388 0x00000000, 389 (0x0400 << 16) | (0xc798 >> 2), 390 0x00000000, 391 (0x0400 << 16) | (0xc79c >> 2), 392 0x00000000, 393 (0x0400 << 16) | (0xc7a0 >> 2), 394 0x00000000, 395 (0x0400 << 16) | (0xc7a4 >> 2), 396 0x00000000, 397 (0x0400 << 16) | (0xc7a8 >> 2), 398 0x00000000, 399 (0x0400 << 16) | (0xc7ac >> 2), 400 0x00000000, 401 (0x0400 << 16) | (0xc7b0 >> 2), 402 0x00000000, 403 (0x0400 << 16) | (0xc7b4 >> 2), 404 0x00000000, 405 (0x0e00 << 16) | (0x9100 >> 2), 406 0x00000000, 407 (0x0e00 << 16) | (0x3c010 >> 2), 408 0x00000000, 409 (0x0e00 << 16) | (0x92a8 >> 2), 410 0x00000000, 411 (0x0e00 << 16) | (0x92ac >> 2), 412 0x00000000, 413 (0x0e00 << 16) | (0x92b4 >> 2), 414 0x00000000, 415 (0x0e00 << 16) | (0x92b8 >> 2), 416 0x00000000, 417 (0x0e00 << 16) | (0x92bc >> 2), 418 0x00000000, 419 (0x0e00 << 16) | (0x92c0 >> 2), 420 0x00000000, 421 (0x0e00 << 16) | (0x92c4 >> 2), 422 0x00000000, 423 (0x0e00 << 16) | (0x92c8 >> 2), 424 0x00000000, 425 (0x0e00 << 16) | (0x92cc >> 2), 426 0x00000000, 427 (0x0e00 << 16) | (0x92d0 >> 2), 428 0x00000000, 429 (0x0e00 << 16) | (0x8c00 >> 2), 430 0x00000000, 431 (0x0e00 << 16) | (0x8c04 >> 2), 432 0x00000000, 433 (0x0e00 << 16) | (0x8c20 >> 2), 434 0x00000000, 435 (0x0e00 << 16) | (0x8c38 >> 2), 436 0x00000000, 437 (0x0e00 << 16) | (0x8c3c >> 2), 438 0x00000000, 439 (0x0e00 << 16) | (0xae00 >> 2), 440 0x00000000, 441 (0x0e00 << 16) | (0x9604 >> 2), 442 0x00000000, 443 (0x0e00 << 16) | (0xac08 >> 2), 444 0x00000000, 445 (0x0e00 << 16) | (0xac0c >> 2), 446 0x00000000, 447 (0x0e00 << 16) | (0xac10 >> 2), 448 0x00000000, 449 (0x0e00 << 16) | (0xac14 >> 2), 450 0x00000000, 451 (0x0e00 << 16) | (0xac58 >> 2), 452 0x00000000, 453 (0x0e00 << 16) | (0xac68 >> 2), 454 0x00000000, 455 (0x0e00 << 16) | (0xac6c >> 2), 456 0x00000000, 457 (0x0e00 << 16) | (0xac70 >> 2), 458 0x00000000, 459 (0x0e00 << 16) | (0xac74 >> 2), 460 0x00000000, 461 (0x0e00 << 16) | (0xac78 >> 2), 462 0x00000000, 463 (0x0e00 << 16) | (0xac7c >> 2), 464 0x00000000, 465 (0x0e00 << 16) | (0xac80 >> 2), 466 0x00000000, 467 (0x0e00 << 16) | (0xac84 >> 2), 468 0x00000000, 469 (0x0e00 << 16) | (0xac88 >> 2), 470 0x00000000, 471 (0x0e00 << 16) | (0xac8c >> 2), 472 0x00000000, 473 (0x0e00 << 16) | (0x970c >> 2), 474 0x00000000, 475 (0x0e00 << 16) | (0x9714 >> 2), 476 0x00000000, 477 (0x0e00 << 16) | (0x9718 >> 2), 478 0x00000000, 479 (0x0e00 << 16) | (0x971c >> 2), 480 0x00000000, 481 (0x0e00 << 16) | (0x31068 >> 2), 482 0x00000000, 483 (0x4e00 << 16) | (0x31068 >> 2), 484 0x00000000, 485 (0x5e00 << 16) | (0x31068 >> 2), 486 0x00000000, 487 (0x6e00 << 16) | (0x31068 >> 2), 488 0x00000000, 489 (0x7e00 << 16) | (0x31068 >> 2), 490 0x00000000, 491 (0x8e00 << 16) | (0x31068 >> 2), 492 0x00000000, 493 (0x9e00 << 16) | (0x31068 >> 2), 494 0x00000000, 495 (0xae00 << 16) | (0x31068 >> 2), 496 0x00000000, 497 (0xbe00 << 16) | (0x31068 >> 2), 498 0x00000000, 499 (0x0e00 << 16) | (0xcd10 >> 2), 500 0x00000000, 501 (0x0e00 << 16) | (0xcd14 >> 2), 502 0x00000000, 503 (0x0e00 << 16) | (0x88b0 >> 2), 504 0x00000000, 505 (0x0e00 << 16) | (0x88b4 >> 2), 506 0x00000000, 507 (0x0e00 << 16) | (0x88b8 >> 2), 508 0x00000000, 509 (0x0e00 << 16) | (0x88bc >> 2), 510 0x00000000, 511 (0x0400 << 16) | (0x89c0 >> 2), 512 0x00000000, 513 (0x0e00 << 16) | (0x88c4 >> 2), 514 0x00000000, 515 (0x0e00 << 16) | (0x88c8 >> 2), 516 0x00000000, 517 (0x0e00 << 16) | (0x88d0 >> 2), 518 0x00000000, 519 (0x0e00 << 16) | (0x88d4 >> 2), 520 0x00000000, 521 (0x0e00 << 16) | (0x88d8 >> 2), 522 0x00000000, 523 (0x0e00 << 16) | (0x8980 >> 2), 524 0x00000000, 525 (0x0e00 << 16) | (0x30938 >> 2), 526 0x00000000, 527 (0x0e00 << 16) | (0x3093c >> 2), 528 0x00000000, 529 (0x0e00 << 16) | (0x30940 >> 2), 530 0x00000000, 531 (0x0e00 << 16) | (0x89a0 >> 2), 532 0x00000000, 533 (0x0e00 << 16) | (0x30900 >> 2), 534 0x00000000, 535 (0x0e00 << 16) | (0x30904 >> 2), 536 0x00000000, 537 (0x0e00 << 16) | (0x89b4 >> 2), 538 0x00000000, 539 (0x0e00 << 16) | (0x3c210 >> 2), 540 0x00000000, 541 (0x0e00 << 16) | (0x3c214 >> 2), 542 0x00000000, 543 (0x0e00 << 16) | (0x3c218 >> 2), 544 0x00000000, 545 (0x0e00 << 16) | (0x8904 >> 2), 546 0x00000000, 547 0x5, 548 (0x0e00 << 16) | (0x8c28 >> 2), 549 (0x0e00 << 16) | (0x8c2c >> 2), 550 (0x0e00 << 16) | (0x8c30 >> 2), 551 (0x0e00 << 16) | (0x8c34 >> 2), 552 (0x0e00 << 16) | (0x9600 >> 2), 553 }; 554 555 static const u32 kalindi_rlc_save_restore_register_list[] = 556 { 557 (0x0e00 << 16) | (0xc12c >> 2), 558 0x00000000, 559 (0x0e00 << 16) | (0xc140 >> 2), 560 0x00000000, 561 (0x0e00 << 16) | (0xc150 >> 2), 562 0x00000000, 563 (0x0e00 << 16) | (0xc15c >> 2), 564 0x00000000, 565 (0x0e00 << 16) | (0xc168 >> 2), 566 0x00000000, 567 (0x0e00 << 16) | (0xc170 >> 2), 568 0x00000000, 569 (0x0e00 << 16) | (0xc204 >> 2), 570 0x00000000, 571 (0x0e00 << 16) | (0xc2b4 >> 2), 572 0x00000000, 573 (0x0e00 << 16) | (0xc2b8 >> 2), 574 0x00000000, 575 (0x0e00 << 16) | (0xc2bc >> 2), 576 0x00000000, 577 (0x0e00 << 16) | (0xc2c0 >> 2), 578 0x00000000, 579 (0x0e00 << 16) | (0x8228 >> 2), 580 0x00000000, 581 (0x0e00 << 16) | (0x829c >> 2), 582 0x00000000, 583 (0x0e00 << 16) | (0x869c >> 2), 584 0x00000000, 585 (0x0600 << 16) | (0x98f4 >> 2), 586 0x00000000, 587 (0x0e00 << 16) | (0x98f8 >> 2), 588 0x00000000, 589 (0x0e00 << 16) | (0x9900 >> 2), 590 0x00000000, 591 (0x0e00 << 16) | (0xc260 >> 2), 592 0x00000000, 593 (0x0e00 << 16) | (0x90e8 >> 2), 594 0x00000000, 595 (0x0e00 << 16) | (0x3c000 >> 2), 596 0x00000000, 597 (0x0e00 << 16) | (0x3c00c >> 2), 598 0x00000000, 599 (0x0e00 << 16) | (0x8c1c >> 2), 600 0x00000000, 601 (0x0e00 << 16) | (0x9700 >> 2), 602 0x00000000, 603 (0x0e00 << 16) | (0xcd20 >> 2), 604 0x00000000, 605 (0x4e00 << 16) | (0xcd20 >> 2), 606 0x00000000, 607 (0x5e00 << 16) | (0xcd20 >> 2), 608 0x00000000, 609 (0x6e00 << 16) | (0xcd20 >> 2), 610 0x00000000, 611 (0x7e00 << 16) | (0xcd20 >> 2), 612 0x00000000, 613 (0x0e00 << 16) | (0x89bc >> 2), 614 0x00000000, 615 (0x0e00 << 16) | (0x8900 >> 2), 616 0x00000000, 617 0x3, 618 (0x0e00 << 16) | (0xc130 >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0xc134 >> 2), 621 0x00000000, 622 (0x0e00 << 16) | (0xc1fc >> 2), 623 0x00000000, 624 (0x0e00 << 16) | (0xc208 >> 2), 625 0x00000000, 626 (0x0e00 << 16) | (0xc264 >> 2), 627 0x00000000, 628 (0x0e00 << 16) | (0xc268 >> 2), 629 0x00000000, 630 (0x0e00 << 16) | (0xc26c >> 2), 631 0x00000000, 632 (0x0e00 << 16) | (0xc270 >> 2), 633 0x00000000, 634 (0x0e00 << 16) | (0xc274 >> 2), 635 0x00000000, 636 (0x0e00 << 16) | (0xc28c >> 2), 637 0x00000000, 638 (0x0e00 << 16) | (0xc290 >> 2), 639 0x00000000, 640 (0x0e00 << 16) | (0xc294 >> 2), 641 0x00000000, 642 (0x0e00 << 16) | (0xc298 >> 2), 643 0x00000000, 644 (0x0e00 << 16) | (0xc2a0 >> 2), 645 0x00000000, 646 (0x0e00 << 16) | (0xc2a4 >> 2), 647 0x00000000, 648 (0x0e00 << 16) | (0xc2a8 >> 2), 649 0x00000000, 650 (0x0e00 << 16) | (0xc2ac >> 2), 651 0x00000000, 652 (0x0e00 << 16) | (0x301d0 >> 2), 653 0x00000000, 654 (0x0e00 << 16) | (0x30238 >> 2), 655 0x00000000, 656 (0x0e00 << 16) | (0x30250 >> 2), 657 0x00000000, 658 (0x0e00 << 16) | (0x30254 >> 2), 659 0x00000000, 660 (0x0e00 << 16) | (0x30258 >> 2), 661 0x00000000, 662 (0x0e00 << 16) | (0x3025c >> 2), 663 0x00000000, 664 (0x4e00 << 16) | (0xc900 >> 2), 665 0x00000000, 666 (0x5e00 << 16) | (0xc900 >> 2), 667 0x00000000, 668 (0x6e00 << 16) | (0xc900 >> 2), 669 0x00000000, 670 (0x7e00 << 16) | (0xc900 >> 2), 671 0x00000000, 672 (0x4e00 << 16) | (0xc904 >> 2), 673 0x00000000, 674 (0x5e00 << 16) | (0xc904 >> 2), 675 0x00000000, 676 (0x6e00 << 16) | (0xc904 >> 2), 677 0x00000000, 678 (0x7e00 << 16) | (0xc904 >> 2), 679 0x00000000, 680 (0x4e00 << 16) | (0xc908 >> 2), 681 0x00000000, 682 (0x5e00 << 16) | (0xc908 >> 2), 683 0x00000000, 684 (0x6e00 << 16) | (0xc908 >> 2), 685 0x00000000, 686 (0x7e00 << 16) | (0xc908 >> 2), 687 0x00000000, 688 (0x4e00 << 16) | (0xc90c >> 2), 689 0x00000000, 690 (0x5e00 << 16) | (0xc90c >> 2), 691 0x00000000, 692 (0x6e00 << 16) | (0xc90c >> 2), 693 0x00000000, 694 (0x7e00 << 16) | (0xc90c >> 2), 695 0x00000000, 696 (0x4e00 << 16) | (0xc910 >> 2), 697 0x00000000, 698 (0x5e00 << 16) | (0xc910 >> 2), 699 0x00000000, 700 (0x6e00 << 16) | (0xc910 >> 2), 701 0x00000000, 702 (0x7e00 << 16) | (0xc910 >> 2), 703 0x00000000, 704 (0x0e00 << 16) | (0xc99c >> 2), 705 0x00000000, 706 (0x0e00 << 16) | (0x9834 >> 2), 707 0x00000000, 708 (0x0000 << 16) | (0x30f00 >> 2), 709 0x00000000, 710 (0x0000 << 16) | (0x30f04 >> 2), 711 0x00000000, 712 (0x0000 << 16) | (0x30f08 >> 2), 713 0x00000000, 714 (0x0000 << 16) | (0x30f0c >> 2), 715 0x00000000, 716 (0x0600 << 16) | (0x9b7c >> 2), 717 0x00000000, 718 (0x0e00 << 16) | (0x8a14 >> 2), 719 0x00000000, 720 (0x0e00 << 16) | (0x8a18 >> 2), 721 0x00000000, 722 (0x0600 << 16) | (0x30a00 >> 2), 723 0x00000000, 724 (0x0e00 << 16) | (0x8bf0 >> 2), 725 0x00000000, 726 (0x0e00 << 16) | (0x8bcc >> 2), 727 0x00000000, 728 (0x0e00 << 16) | (0x8b24 >> 2), 729 0x00000000, 730 (0x0e00 << 16) | (0x30a04 >> 2), 731 0x00000000, 732 (0x0600 << 16) | (0x30a10 >> 2), 733 0x00000000, 734 (0x0600 << 16) | (0x30a14 >> 2), 735 0x00000000, 736 (0x0600 << 16) | (0x30a18 >> 2), 737 0x00000000, 738 (0x0600 << 16) | (0x30a2c >> 2), 739 0x00000000, 740 (0x0e00 << 16) | (0xc700 >> 2), 741 0x00000000, 742 (0x0e00 << 16) | (0xc704 >> 2), 743 0x00000000, 744 (0x0e00 << 16) | (0xc708 >> 2), 745 0x00000000, 746 (0x0e00 << 16) | (0xc768 >> 2), 747 0x00000000, 748 (0x0400 << 16) | (0xc770 >> 2), 749 0x00000000, 750 (0x0400 << 16) | (0xc774 >> 2), 751 0x00000000, 752 (0x0400 << 16) | (0xc798 >> 2), 753 0x00000000, 754 (0x0400 << 16) | (0xc79c >> 2), 755 0x00000000, 756 (0x0e00 << 16) | (0x9100 >> 2), 757 0x00000000, 758 (0x0e00 << 16) | (0x3c010 >> 2), 759 0x00000000, 760 (0x0e00 << 16) | (0x8c00 >> 2), 761 0x00000000, 762 (0x0e00 << 16) | (0x8c04 >> 2), 763 0x00000000, 764 (0x0e00 << 16) | (0x8c20 >> 2), 765 0x00000000, 766 (0x0e00 << 16) | (0x8c38 >> 2), 767 0x00000000, 768 (0x0e00 << 16) | (0x8c3c >> 2), 769 0x00000000, 770 (0x0e00 << 16) | (0xae00 >> 2), 771 0x00000000, 772 (0x0e00 << 16) | (0x9604 >> 2), 773 0x00000000, 774 (0x0e00 << 16) | (0xac08 >> 2), 775 0x00000000, 776 (0x0e00 << 16) | (0xac0c >> 2), 777 0x00000000, 778 (0x0e00 << 16) | (0xac10 >> 2), 779 0x00000000, 780 (0x0e00 << 16) | (0xac14 >> 2), 781 0x00000000, 782 (0x0e00 << 16) | (0xac58 >> 2), 783 0x00000000, 784 (0x0e00 << 16) | (0xac68 >> 2), 785 0x00000000, 786 (0x0e00 << 16) | (0xac6c >> 2), 787 0x00000000, 788 (0x0e00 << 16) | (0xac70 >> 2), 789 0x00000000, 790 (0x0e00 << 16) | (0xac74 >> 2), 791 0x00000000, 792 (0x0e00 << 16) | (0xac78 >> 2), 793 0x00000000, 794 (0x0e00 << 16) | (0xac7c >> 2), 795 0x00000000, 796 (0x0e00 << 16) | (0xac80 >> 2), 797 0x00000000, 798 (0x0e00 << 16) | (0xac84 >> 2), 799 0x00000000, 800 (0x0e00 << 16) | (0xac88 >> 2), 801 0x00000000, 802 (0x0e00 << 16) | (0xac8c >> 2), 803 0x00000000, 804 (0x0e00 << 16) | (0x970c >> 2), 805 0x00000000, 806 (0x0e00 << 16) | (0x9714 >> 2), 807 0x00000000, 808 (0x0e00 << 16) | (0x9718 >> 2), 809 0x00000000, 810 (0x0e00 << 16) | (0x971c >> 2), 811 0x00000000, 812 (0x0e00 << 16) | (0x31068 >> 2), 813 0x00000000, 814 (0x4e00 << 16) | (0x31068 >> 2), 815 0x00000000, 816 (0x5e00 << 16) | (0x31068 >> 2), 817 0x00000000, 818 (0x6e00 << 16) | (0x31068 >> 2), 819 0x00000000, 820 (0x7e00 << 16) | (0x31068 >> 2), 821 0x00000000, 822 (0x0e00 << 16) | (0xcd10 >> 2), 823 0x00000000, 824 (0x0e00 << 16) | (0xcd14 >> 2), 825 0x00000000, 826 (0x0e00 << 16) | (0x88b0 >> 2), 827 0x00000000, 828 (0x0e00 << 16) | (0x88b4 >> 2), 829 0x00000000, 830 (0x0e00 << 16) | (0x88b8 >> 2), 831 0x00000000, 832 (0x0e00 << 16) | (0x88bc >> 2), 833 0x00000000, 834 (0x0400 << 16) | (0x89c0 >> 2), 835 0x00000000, 836 (0x0e00 << 16) | (0x88c4 >> 2), 837 0x00000000, 838 (0x0e00 << 16) | (0x88c8 >> 2), 839 0x00000000, 840 (0x0e00 << 16) | (0x88d0 >> 2), 841 0x00000000, 842 (0x0e00 << 16) | (0x88d4 >> 2), 843 0x00000000, 844 (0x0e00 << 16) | (0x88d8 >> 2), 845 0x00000000, 846 (0x0e00 << 16) | (0x8980 >> 2), 847 0x00000000, 848 (0x0e00 << 16) | (0x30938 >> 2), 849 0x00000000, 850 (0x0e00 << 16) | (0x3093c >> 2), 851 0x00000000, 852 (0x0e00 << 16) | (0x30940 >> 2), 853 0x00000000, 854 (0x0e00 << 16) | (0x89a0 >> 2), 855 0x00000000, 856 (0x0e00 << 16) | (0x30900 >> 2), 857 0x00000000, 858 (0x0e00 << 16) | (0x30904 >> 2), 859 0x00000000, 860 (0x0e00 << 16) | (0x89b4 >> 2), 861 0x00000000, 862 (0x0e00 << 16) | (0x3e1fc >> 2), 863 0x00000000, 864 (0x0e00 << 16) | (0x3c210 >> 2), 865 0x00000000, 866 (0x0e00 << 16) | (0x3c214 >> 2), 867 0x00000000, 868 (0x0e00 << 16) | (0x3c218 >> 2), 869 0x00000000, 870 (0x0e00 << 16) | (0x8904 >> 2), 871 0x00000000, 872 0x5, 873 (0x0e00 << 16) | (0x8c28 >> 2), 874 (0x0e00 << 16) | (0x8c2c >> 2), 875 (0x0e00 << 16) | (0x8c30 >> 2), 876 (0x0e00 << 16) | (0x8c34 >> 2), 877 (0x0e00 << 16) | (0x9600 >> 2), 878 }; 879 880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); 883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 885 886 /* 887 * Core functions 888 */ 889 /** 890 * gfx_v7_0_init_microcode - load ucode images from disk 891 * 892 * @adev: amdgpu_device pointer 893 * 894 * Use the firmware interface to load the ucode images into 895 * the driver (not loaded into hw). 896 * Returns 0 on success, error on failure. 897 */ 898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 899 { 900 const char *chip_name; 901 char fw_name[30]; 902 int err; 903 904 DRM_DEBUG("\n"); 905 906 switch (adev->asic_type) { 907 case CHIP_BONAIRE: 908 chip_name = "bonaire"; 909 break; 910 case CHIP_HAWAII: 911 chip_name = "hawaii"; 912 break; 913 case CHIP_KAVERI: 914 chip_name = "kaveri"; 915 break; 916 case CHIP_KABINI: 917 chip_name = "kabini"; 918 break; 919 case CHIP_MULLINS: 920 chip_name = "mullins"; 921 break; 922 default: BUG(); 923 } 924 925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 927 if (err) 928 goto out; 929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 930 if (err) 931 goto out; 932 933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 935 if (err) 936 goto out; 937 err = amdgpu_ucode_validate(adev->gfx.me_fw); 938 if (err) 939 goto out; 940 941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 943 if (err) 944 goto out; 945 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 946 if (err) 947 goto out; 948 949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); 950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 951 if (err) 952 goto out; 953 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 954 if (err) 955 goto out; 956 957 if (adev->asic_type == CHIP_KAVERI) { 958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); 959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 960 if (err) 961 goto out; 962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 963 if (err) 964 goto out; 965 } 966 967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 969 if (err) 970 goto out; 971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 972 973 out: 974 if (err) { 975 printk(KERN_ERR 976 "gfx7: Failed to load firmware \"%s\"\n", 977 fw_name); 978 release_firmware(adev->gfx.pfp_fw); 979 adev->gfx.pfp_fw = NULL; 980 release_firmware(adev->gfx.me_fw); 981 adev->gfx.me_fw = NULL; 982 release_firmware(adev->gfx.ce_fw); 983 adev->gfx.ce_fw = NULL; 984 release_firmware(adev->gfx.mec_fw); 985 adev->gfx.mec_fw = NULL; 986 release_firmware(adev->gfx.mec2_fw); 987 adev->gfx.mec2_fw = NULL; 988 release_firmware(adev->gfx.rlc_fw); 989 adev->gfx.rlc_fw = NULL; 990 } 991 return err; 992 } 993 994 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 995 { 996 release_firmware(adev->gfx.pfp_fw); 997 adev->gfx.pfp_fw = NULL; 998 release_firmware(adev->gfx.me_fw); 999 adev->gfx.me_fw = NULL; 1000 release_firmware(adev->gfx.ce_fw); 1001 adev->gfx.ce_fw = NULL; 1002 release_firmware(adev->gfx.mec_fw); 1003 adev->gfx.mec_fw = NULL; 1004 release_firmware(adev->gfx.mec2_fw); 1005 adev->gfx.mec2_fw = NULL; 1006 release_firmware(adev->gfx.rlc_fw); 1007 adev->gfx.rlc_fw = NULL; 1008 } 1009 1010 /** 1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1012 * 1013 * @adev: amdgpu_device pointer 1014 * 1015 * Starting with SI, the tiling setup is done globally in a 1016 * set of 32 tiling modes. Rather than selecting each set of 1017 * parameters per surface as on older asics, we just select 1018 * which index in the tiling table we want to use, and the 1019 * surface uses those parameters (CIK). 1020 */ 1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1022 { 1023 const u32 num_tile_mode_states = 1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1025 const u32 num_secondary_tile_mode_states = 1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1027 u32 reg_offset, split_equal_to_row_size; 1028 uint32_t *tile, *macrotile; 1029 1030 tile = adev->gfx.config.tile_mode_array; 1031 macrotile = adev->gfx.config.macrotile_mode_array; 1032 1033 switch (adev->gfx.config.mem_row_size_in_kb) { 1034 case 1: 1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1036 break; 1037 case 2: 1038 default: 1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1040 break; 1041 case 4: 1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1043 break; 1044 } 1045 1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1047 tile[reg_offset] = 0; 1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1049 macrotile[reg_offset] = 0; 1050 1051 switch (adev->asic_type) { 1052 case CHIP_BONAIRE: 1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1072 TILE_SPLIT(split_equal_to_row_size)); 1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1079 TILE_SPLIT(split_equal_to_row_size)); 1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1082 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1155 1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1159 NUM_BANKS(ADDR_SURF_16_BANK)); 1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1163 NUM_BANKS(ADDR_SURF_16_BANK)); 1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1167 NUM_BANKS(ADDR_SURF_16_BANK)); 1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1171 NUM_BANKS(ADDR_SURF_16_BANK)); 1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1175 NUM_BANKS(ADDR_SURF_16_BANK)); 1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1179 NUM_BANKS(ADDR_SURF_8_BANK)); 1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1183 NUM_BANKS(ADDR_SURF_4_BANK)); 1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1187 NUM_BANKS(ADDR_SURF_16_BANK)); 1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1191 NUM_BANKS(ADDR_SURF_16_BANK)); 1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1195 NUM_BANKS(ADDR_SURF_16_BANK)); 1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1199 NUM_BANKS(ADDR_SURF_16_BANK)); 1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1203 NUM_BANKS(ADDR_SURF_16_BANK)); 1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1207 NUM_BANKS(ADDR_SURF_8_BANK)); 1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1211 NUM_BANKS(ADDR_SURF_4_BANK)); 1212 1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1216 if (reg_offset != 7) 1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1218 break; 1219 case CHIP_HAWAII: 1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1239 TILE_SPLIT(split_equal_to_row_size)); 1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1243 TILE_SPLIT(split_equal_to_row_size)); 1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1247 TILE_SPLIT(split_equal_to_row_size)); 1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1251 TILE_SPLIT(split_equal_to_row_size)); 1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1338 1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1342 NUM_BANKS(ADDR_SURF_16_BANK)); 1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1346 NUM_BANKS(ADDR_SURF_16_BANK)); 1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1350 NUM_BANKS(ADDR_SURF_16_BANK)); 1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1354 NUM_BANKS(ADDR_SURF_16_BANK)); 1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1358 NUM_BANKS(ADDR_SURF_8_BANK)); 1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1362 NUM_BANKS(ADDR_SURF_4_BANK)); 1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1366 NUM_BANKS(ADDR_SURF_4_BANK)); 1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1370 NUM_BANKS(ADDR_SURF_16_BANK)); 1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1374 NUM_BANKS(ADDR_SURF_16_BANK)); 1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1378 NUM_BANKS(ADDR_SURF_16_BANK)); 1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1382 NUM_BANKS(ADDR_SURF_8_BANK)); 1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1386 NUM_BANKS(ADDR_SURF_16_BANK)); 1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1390 NUM_BANKS(ADDR_SURF_8_BANK)); 1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1394 NUM_BANKS(ADDR_SURF_4_BANK)); 1395 1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1399 if (reg_offset != 7) 1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1401 break; 1402 case CHIP_KABINI: 1403 case CHIP_KAVERI: 1404 case CHIP_MULLINS: 1405 default: 1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1407 PIPE_CONFIG(ADDR_SURF_P2) | 1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1411 PIPE_CONFIG(ADDR_SURF_P2) | 1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1415 PIPE_CONFIG(ADDR_SURF_P2) | 1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1419 PIPE_CONFIG(ADDR_SURF_P2) | 1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1423 PIPE_CONFIG(ADDR_SURF_P2) | 1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1425 TILE_SPLIT(split_equal_to_row_size)); 1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1427 PIPE_CONFIG(ADDR_SURF_P2) | 1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1430 PIPE_CONFIG(ADDR_SURF_P2) | 1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1432 TILE_SPLIT(split_equal_to_row_size)); 1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1435 PIPE_CONFIG(ADDR_SURF_P2)); 1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1444 PIPE_CONFIG(ADDR_SURF_P2) | 1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1449 PIPE_CONFIG(ADDR_SURF_P2) | 1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1452 PIPE_CONFIG(ADDR_SURF_P2) | 1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1456 PIPE_CONFIG(ADDR_SURF_P2) | 1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1460 PIPE_CONFIG(ADDR_SURF_P2) | 1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1465 PIPE_CONFIG(ADDR_SURF_P2) | 1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1469 PIPE_CONFIG(ADDR_SURF_P2) | 1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1472 PIPE_CONFIG(ADDR_SURF_P2) | 1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1476 PIPE_CONFIG(ADDR_SURF_P2) | 1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1480 PIPE_CONFIG(ADDR_SURF_P2) | 1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1485 PIPE_CONFIG(ADDR_SURF_P2) | 1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1489 PIPE_CONFIG(ADDR_SURF_P2) | 1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1493 PIPE_CONFIG(ADDR_SURF_P2) | 1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1497 PIPE_CONFIG(ADDR_SURF_P2) | 1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1500 PIPE_CONFIG(ADDR_SURF_P2) | 1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1504 PIPE_CONFIG(ADDR_SURF_P2) | 1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1508 1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1512 NUM_BANKS(ADDR_SURF_8_BANK)); 1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1516 NUM_BANKS(ADDR_SURF_8_BANK)); 1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1520 NUM_BANKS(ADDR_SURF_8_BANK)); 1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1524 NUM_BANKS(ADDR_SURF_8_BANK)); 1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1528 NUM_BANKS(ADDR_SURF_8_BANK)); 1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1532 NUM_BANKS(ADDR_SURF_8_BANK)); 1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1536 NUM_BANKS(ADDR_SURF_8_BANK)); 1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1540 NUM_BANKS(ADDR_SURF_16_BANK)); 1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1544 NUM_BANKS(ADDR_SURF_16_BANK)); 1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1548 NUM_BANKS(ADDR_SURF_16_BANK)); 1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1552 NUM_BANKS(ADDR_SURF_16_BANK)); 1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1556 NUM_BANKS(ADDR_SURF_16_BANK)); 1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1560 NUM_BANKS(ADDR_SURF_16_BANK)); 1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1564 NUM_BANKS(ADDR_SURF_8_BANK)); 1565 1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1569 if (reg_offset != 7) 1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1571 break; 1572 } 1573 } 1574 1575 /** 1576 * gfx_v7_0_select_se_sh - select which SE, SH to address 1577 * 1578 * @adev: amdgpu_device pointer 1579 * @se_num: shader engine to address 1580 * @sh_num: sh block to address 1581 * 1582 * Select which SE, SH combinations to address. Certain 1583 * registers are instanced per SE or SH. 0xffffffff means 1584 * broadcast to all SEs or SHs (CIK). 1585 */ 1586 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1587 u32 se_num, u32 sh_num, u32 instance) 1588 { 1589 u32 data; 1590 1591 if (instance == 0xffffffff) 1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1593 else 1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1595 1596 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1599 else if (se_num == 0xffffffff) 1600 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1601 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1602 else if (sh_num == 0xffffffff) 1603 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1604 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1605 else 1606 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1607 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1608 WREG32(mmGRBM_GFX_INDEX, data); 1609 } 1610 1611 /** 1612 * gfx_v7_0_create_bitmask - create a bitmask 1613 * 1614 * @bit_width: length of the mask 1615 * 1616 * create a variable length bit mask (CIK). 1617 * Returns the bitmask. 1618 */ 1619 static u32 gfx_v7_0_create_bitmask(u32 bit_width) 1620 { 1621 return (u32)((1ULL << bit_width) - 1); 1622 } 1623 1624 /** 1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1626 * 1627 * @adev: amdgpu_device pointer 1628 * 1629 * Calculates the bitmask of enabled RBs (CIK). 1630 * Returns the enabled RB bitmask. 1631 */ 1632 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1633 { 1634 u32 data, mask; 1635 1636 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1637 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1638 1639 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1640 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1641 1642 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / 1643 adev->gfx.config.max_sh_per_se); 1644 1645 return (~data) & mask; 1646 } 1647 1648 static void 1649 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1650 { 1651 switch (adev->asic_type) { 1652 case CHIP_BONAIRE: 1653 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1654 SE_XSEL(1) | SE_YSEL(1); 1655 *rconf1 |= 0x0; 1656 break; 1657 case CHIP_HAWAII: 1658 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1661 SE_YSEL(3); 1662 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1663 SE_PAIR_YSEL(2); 1664 break; 1665 case CHIP_KAVERI: 1666 *rconf |= RB_MAP_PKR0(2); 1667 *rconf1 |= 0x0; 1668 break; 1669 case CHIP_KABINI: 1670 case CHIP_MULLINS: 1671 *rconf |= 0x0; 1672 *rconf1 |= 0x0; 1673 break; 1674 default: 1675 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1676 break; 1677 } 1678 } 1679 1680 static void 1681 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1682 u32 raster_config, u32 raster_config_1, 1683 unsigned rb_mask, unsigned num_rb) 1684 { 1685 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1686 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1687 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1688 unsigned rb_per_se = num_rb / num_se; 1689 unsigned se_mask[4]; 1690 unsigned se; 1691 1692 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1693 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1694 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1695 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1696 1697 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1698 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1699 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1700 1701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1702 (!se_mask[2] && !se_mask[3]))) { 1703 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1704 1705 if (!se_mask[0] && !se_mask[1]) { 1706 raster_config_1 |= 1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1708 } else { 1709 raster_config_1 |= 1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1711 } 1712 } 1713 1714 for (se = 0; se < num_se; se++) { 1715 unsigned raster_config_se = raster_config; 1716 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1717 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1718 int idx = (se / 2) * 2; 1719 1720 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1721 raster_config_se &= ~SE_MAP_MASK; 1722 1723 if (!se_mask[idx]) { 1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1725 } else { 1726 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1727 } 1728 } 1729 1730 pkr0_mask &= rb_mask; 1731 pkr1_mask &= rb_mask; 1732 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1733 raster_config_se &= ~PKR_MAP_MASK; 1734 1735 if (!pkr0_mask) { 1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1737 } else { 1738 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1739 } 1740 } 1741 1742 if (rb_per_se >= 2) { 1743 unsigned rb0_mask = 1 << (se * rb_per_se); 1744 unsigned rb1_mask = rb0_mask << 1; 1745 1746 rb0_mask &= rb_mask; 1747 rb1_mask &= rb_mask; 1748 if (!rb0_mask || !rb1_mask) { 1749 raster_config_se &= ~RB_MAP_PKR0_MASK; 1750 1751 if (!rb0_mask) { 1752 raster_config_se |= 1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1754 } else { 1755 raster_config_se |= 1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1757 } 1758 } 1759 1760 if (rb_per_se > 2) { 1761 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1762 rb1_mask = rb0_mask << 1; 1763 rb0_mask &= rb_mask; 1764 rb1_mask &= rb_mask; 1765 if (!rb0_mask || !rb1_mask) { 1766 raster_config_se &= ~RB_MAP_PKR1_MASK; 1767 1768 if (!rb0_mask) { 1769 raster_config_se |= 1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1771 } else { 1772 raster_config_se |= 1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1774 } 1775 } 1776 } 1777 } 1778 1779 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1780 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1781 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1782 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1783 } 1784 1785 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1786 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1787 } 1788 1789 /** 1790 * gfx_v7_0_setup_rb - setup the RBs on the asic 1791 * 1792 * @adev: amdgpu_device pointer 1793 * @se_num: number of SEs (shader engines) for the asic 1794 * @sh_per_se: number of SH blocks per SE for the asic 1795 * 1796 * Configures per-SE/SH RB registers (CIK). 1797 */ 1798 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1799 { 1800 int i, j; 1801 u32 data; 1802 u32 raster_config = 0, raster_config_1 = 0; 1803 u32 active_rbs = 0; 1804 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1805 adev->gfx.config.max_sh_per_se; 1806 unsigned num_rb_pipes; 1807 1808 mutex_lock(&adev->grbm_idx_mutex); 1809 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1810 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1811 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1812 data = gfx_v7_0_get_rb_active_bitmap(adev); 1813 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1814 rb_bitmap_width_per_sh); 1815 } 1816 } 1817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1818 1819 adev->gfx.config.backend_enable_mask = active_rbs; 1820 adev->gfx.config.num_rbs = hweight32(active_rbs); 1821 1822 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1823 adev->gfx.config.max_shader_engines, 16); 1824 1825 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1826 1827 if (!adev->gfx.config.backend_enable_mask || 1828 adev->gfx.config.num_rbs >= num_rb_pipes) { 1829 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1830 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1831 } else { 1832 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1833 adev->gfx.config.backend_enable_mask, 1834 num_rb_pipes); 1835 } 1836 mutex_unlock(&adev->grbm_idx_mutex); 1837 } 1838 1839 /** 1840 * gmc_v7_0_init_compute_vmid - gart enable 1841 * 1842 * @rdev: amdgpu_device pointer 1843 * 1844 * Initialize compute vmid sh_mem registers 1845 * 1846 */ 1847 #define DEFAULT_SH_MEM_BASES (0x6000) 1848 #define FIRST_COMPUTE_VMID (8) 1849 #define LAST_COMPUTE_VMID (16) 1850 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1851 { 1852 int i; 1853 uint32_t sh_mem_config; 1854 uint32_t sh_mem_bases; 1855 1856 /* 1857 * Configure apertures: 1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1861 */ 1862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1863 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1865 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1866 mutex_lock(&adev->srbm_mutex); 1867 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1868 cik_srbm_select(adev, 0, 0, 0, i); 1869 /* CP and shaders */ 1870 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1871 WREG32(mmSH_MEM_APE1_BASE, 1); 1872 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1873 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1874 } 1875 cik_srbm_select(adev, 0, 0, 0, 0); 1876 mutex_unlock(&adev->srbm_mutex); 1877 } 1878 1879 /** 1880 * gfx_v7_0_gpu_init - setup the 3D engine 1881 * 1882 * @adev: amdgpu_device pointer 1883 * 1884 * Configures the 3D engine and tiling configuration 1885 * registers so that the 3D engine is usable. 1886 */ 1887 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 1888 { 1889 u32 tmp, sh_mem_cfg; 1890 int i; 1891 1892 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1893 1894 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1895 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1896 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1897 1898 gfx_v7_0_tiling_mode_table_init(adev); 1899 1900 gfx_v7_0_setup_rb(adev); 1901 gfx_v7_0_get_cu_info(adev); 1902 1903 /* set HW defaults for 3D engine */ 1904 WREG32(mmCP_MEQ_THRESHOLDS, 1905 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1906 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1907 1908 mutex_lock(&adev->grbm_idx_mutex); 1909 /* 1910 * making sure that the following register writes will be broadcasted 1911 * to all the shaders 1912 */ 1913 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1914 1915 /* XXX SH_MEM regs */ 1916 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1917 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1918 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1919 1920 mutex_lock(&adev->srbm_mutex); 1921 for (i = 0; i < 16; i++) { 1922 cik_srbm_select(adev, 0, 0, 0, i); 1923 /* CP and shaders */ 1924 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1925 WREG32(mmSH_MEM_APE1_BASE, 1); 1926 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1927 WREG32(mmSH_MEM_BASES, 0); 1928 } 1929 cik_srbm_select(adev, 0, 0, 0, 0); 1930 mutex_unlock(&adev->srbm_mutex); 1931 1932 gmc_v7_0_init_compute_vmid(adev); 1933 1934 WREG32(mmSX_DEBUG_1, 0x20); 1935 1936 WREG32(mmTA_CNTL_AUX, 0x00010000); 1937 1938 tmp = RREG32(mmSPI_CONFIG_CNTL); 1939 tmp |= 0x03000000; 1940 WREG32(mmSPI_CONFIG_CNTL, tmp); 1941 1942 WREG32(mmSQ_CONFIG, 1); 1943 1944 WREG32(mmDB_DEBUG, 0); 1945 1946 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1947 tmp |= 0x00000400; 1948 WREG32(mmDB_DEBUG2, tmp); 1949 1950 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1951 tmp |= 0x00020200; 1952 WREG32(mmDB_DEBUG3, tmp); 1953 1954 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1955 tmp |= 0x00018208; 1956 WREG32(mmCB_HW_CONTROL, tmp); 1957 1958 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1959 1960 WREG32(mmPA_SC_FIFO_SIZE, 1961 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1962 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1963 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1964 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1965 1966 WREG32(mmVGT_NUM_INSTANCES, 1); 1967 1968 WREG32(mmCP_PERFMON_CNTL, 0); 1969 1970 WREG32(mmSQ_CONFIG, 0); 1971 1972 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1973 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1974 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1975 1976 WREG32(mmVGT_CACHE_INVALIDATION, 1977 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1978 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1979 1980 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1981 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1982 1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 1986 mutex_unlock(&adev->grbm_idx_mutex); 1987 1988 udelay(50); 1989 } 1990 1991 /* 1992 * GPU scratch registers helpers function. 1993 */ 1994 /** 1995 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 1996 * 1997 * @adev: amdgpu_device pointer 1998 * 1999 * Set up the number and offset of the CP scratch registers. 2000 * NOTE: use of CP scratch registers is a legacy inferface and 2001 * is not used by default on newer asics (r6xx+). On newer asics, 2002 * memory buffers are used for fences rather than scratch regs. 2003 */ 2004 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 2005 { 2006 int i; 2007 2008 adev->gfx.scratch.num_reg = 7; 2009 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 2010 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 2011 adev->gfx.scratch.free[i] = true; 2012 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 2013 } 2014 } 2015 2016 /** 2017 * gfx_v7_0_ring_test_ring - basic gfx ring test 2018 * 2019 * @adev: amdgpu_device pointer 2020 * @ring: amdgpu_ring structure holding ring information 2021 * 2022 * Allocate a scratch register and write to it using the gfx ring (CIK). 2023 * Provides a basic gfx ring test to verify that the ring is working. 2024 * Used by gfx_v7_0_cp_gfx_resume(); 2025 * Returns 0 on success, error on failure. 2026 */ 2027 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2028 { 2029 struct amdgpu_device *adev = ring->adev; 2030 uint32_t scratch; 2031 uint32_t tmp = 0; 2032 unsigned i; 2033 int r; 2034 2035 r = amdgpu_gfx_scratch_get(adev, &scratch); 2036 if (r) { 2037 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 2038 return r; 2039 } 2040 WREG32(scratch, 0xCAFEDEAD); 2041 r = amdgpu_ring_alloc(ring, 3); 2042 if (r) { 2043 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 2044 amdgpu_gfx_scratch_free(adev, scratch); 2045 return r; 2046 } 2047 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2048 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2049 amdgpu_ring_write(ring, 0xDEADBEEF); 2050 amdgpu_ring_commit(ring); 2051 2052 for (i = 0; i < adev->usec_timeout; i++) { 2053 tmp = RREG32(scratch); 2054 if (tmp == 0xDEADBEEF) 2055 break; 2056 DRM_UDELAY(1); 2057 } 2058 if (i < adev->usec_timeout) { 2059 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2060 } else { 2061 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2062 ring->idx, scratch, tmp); 2063 r = -EINVAL; 2064 } 2065 amdgpu_gfx_scratch_free(adev, scratch); 2066 return r; 2067 } 2068 2069 /** 2070 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 2071 * 2072 * @adev: amdgpu_device pointer 2073 * @ridx: amdgpu ring index 2074 * 2075 * Emits an hdp flush on the cp. 2076 */ 2077 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2078 { 2079 u32 ref_and_mask; 2080 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2081 2082 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2083 switch (ring->me) { 2084 case 1: 2085 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2086 break; 2087 case 2: 2088 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2089 break; 2090 default: 2091 return; 2092 } 2093 } else { 2094 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2095 } 2096 2097 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2098 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2099 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2100 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2101 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2102 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2103 amdgpu_ring_write(ring, ref_and_mask); 2104 amdgpu_ring_write(ring, ref_and_mask); 2105 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2106 } 2107 2108 /** 2109 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 2110 * 2111 * @adev: amdgpu_device pointer 2112 * @ridx: amdgpu ring index 2113 * 2114 * Emits an hdp invalidate on the cp. 2115 */ 2116 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 2117 { 2118 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2119 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2120 WRITE_DATA_DST_SEL(0) | 2121 WR_CONFIRM)); 2122 amdgpu_ring_write(ring, mmHDP_DEBUG0); 2123 amdgpu_ring_write(ring, 0); 2124 amdgpu_ring_write(ring, 1); 2125 } 2126 2127 /** 2128 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2129 * 2130 * @adev: amdgpu_device pointer 2131 * @fence: amdgpu fence object 2132 * 2133 * Emits a fence sequnce number on the gfx ring and flushes 2134 * GPU caches. 2135 */ 2136 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2137 u64 seq, unsigned flags) 2138 { 2139 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2140 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2141 /* Workaround for cache flush problems. First send a dummy EOP 2142 * event down the pipe with seq one below. 2143 */ 2144 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2145 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2146 EOP_TC_ACTION_EN | 2147 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2148 EVENT_INDEX(5))); 2149 amdgpu_ring_write(ring, addr & 0xfffffffc); 2150 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2151 DATA_SEL(1) | INT_SEL(0)); 2152 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2153 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2154 2155 /* Then send the real EOP event down the pipe. */ 2156 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2157 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2158 EOP_TC_ACTION_EN | 2159 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2160 EVENT_INDEX(5))); 2161 amdgpu_ring_write(ring, addr & 0xfffffffc); 2162 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2163 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2164 amdgpu_ring_write(ring, lower_32_bits(seq)); 2165 amdgpu_ring_write(ring, upper_32_bits(seq)); 2166 } 2167 2168 /** 2169 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2170 * 2171 * @adev: amdgpu_device pointer 2172 * @fence: amdgpu fence object 2173 * 2174 * Emits a fence sequnce number on the compute ring and flushes 2175 * GPU caches. 2176 */ 2177 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2178 u64 addr, u64 seq, 2179 unsigned flags) 2180 { 2181 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2182 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2183 2184 /* RELEASE_MEM - flush caches, send int */ 2185 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2186 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2187 EOP_TC_ACTION_EN | 2188 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2189 EVENT_INDEX(5))); 2190 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2191 amdgpu_ring_write(ring, addr & 0xfffffffc); 2192 amdgpu_ring_write(ring, upper_32_bits(addr)); 2193 amdgpu_ring_write(ring, lower_32_bits(seq)); 2194 amdgpu_ring_write(ring, upper_32_bits(seq)); 2195 } 2196 2197 /* 2198 * IB stuff 2199 */ 2200 /** 2201 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2202 * 2203 * @ring: amdgpu_ring structure holding ring information 2204 * @ib: amdgpu indirect buffer object 2205 * 2206 * Emits an DE (drawing engine) or CE (constant engine) IB 2207 * on the gfx ring. IBs are usually generated by userspace 2208 * acceleration drivers and submitted to the kernel for 2209 * sheduling on the ring. This function schedules the IB 2210 * on the gfx ring for execution by the GPU. 2211 */ 2212 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2213 struct amdgpu_ib *ib, 2214 unsigned vm_id, bool ctx_switch) 2215 { 2216 u32 header, control = 0; 2217 2218 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2219 if (ctx_switch) { 2220 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2221 amdgpu_ring_write(ring, 0); 2222 } 2223 2224 if (ib->flags & AMDGPU_IB_FLAG_CE) 2225 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2226 else 2227 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2228 2229 control |= ib->length_dw | (vm_id << 24); 2230 2231 amdgpu_ring_write(ring, header); 2232 amdgpu_ring_write(ring, 2233 #ifdef __BIG_ENDIAN 2234 (2 << 0) | 2235 #endif 2236 (ib->gpu_addr & 0xFFFFFFFC)); 2237 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2238 amdgpu_ring_write(ring, control); 2239 } 2240 2241 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2242 struct amdgpu_ib *ib, 2243 unsigned vm_id, bool ctx_switch) 2244 { 2245 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 2246 2247 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2248 amdgpu_ring_write(ring, 2249 #ifdef __BIG_ENDIAN 2250 (2 << 0) | 2251 #endif 2252 (ib->gpu_addr & 0xFFFFFFFC)); 2253 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2254 amdgpu_ring_write(ring, control); 2255 } 2256 2257 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2258 { 2259 uint32_t dw2 = 0; 2260 2261 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2262 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2263 /* set load_global_config & load_global_uconfig */ 2264 dw2 |= 0x8001; 2265 /* set load_cs_sh_regs */ 2266 dw2 |= 0x01000000; 2267 /* set load_per_context_state & load_gfx_sh_regs */ 2268 dw2 |= 0x10002; 2269 } 2270 2271 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2272 amdgpu_ring_write(ring, dw2); 2273 amdgpu_ring_write(ring, 0); 2274 } 2275 2276 /** 2277 * gfx_v7_0_ring_test_ib - basic ring IB test 2278 * 2279 * @ring: amdgpu_ring structure holding ring information 2280 * 2281 * Allocate an IB and execute it on the gfx ring (CIK). 2282 * Provides a basic gfx ring test to verify that IBs are working. 2283 * Returns 0 on success, error on failure. 2284 */ 2285 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2286 { 2287 struct amdgpu_device *adev = ring->adev; 2288 struct amdgpu_ib ib; 2289 struct dma_fence *f = NULL; 2290 uint32_t scratch; 2291 uint32_t tmp = 0; 2292 long r; 2293 2294 r = amdgpu_gfx_scratch_get(adev, &scratch); 2295 if (r) { 2296 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 2297 return r; 2298 } 2299 WREG32(scratch, 0xCAFEDEAD); 2300 memset(&ib, 0, sizeof(ib)); 2301 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2302 if (r) { 2303 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 2304 goto err1; 2305 } 2306 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2307 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2308 ib.ptr[2] = 0xDEADBEEF; 2309 ib.length_dw = 3; 2310 2311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); 2312 if (r) 2313 goto err2; 2314 2315 r = dma_fence_wait_timeout(f, false, timeout); 2316 if (r == 0) { 2317 DRM_ERROR("amdgpu: IB test timed out\n"); 2318 r = -ETIMEDOUT; 2319 goto err2; 2320 } else if (r < 0) { 2321 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 2322 goto err2; 2323 } 2324 tmp = RREG32(scratch); 2325 if (tmp == 0xDEADBEEF) { 2326 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 2327 r = 0; 2328 } else { 2329 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 2330 scratch, tmp); 2331 r = -EINVAL; 2332 } 2333 2334 err2: 2335 amdgpu_ib_free(adev, &ib, NULL); 2336 dma_fence_put(f); 2337 err1: 2338 amdgpu_gfx_scratch_free(adev, scratch); 2339 return r; 2340 } 2341 2342 /* 2343 * CP. 2344 * On CIK, gfx and compute now have independant command processors. 2345 * 2346 * GFX 2347 * Gfx consists of a single ring and can process both gfx jobs and 2348 * compute jobs. The gfx CP consists of three microengines (ME): 2349 * PFP - Pre-Fetch Parser 2350 * ME - Micro Engine 2351 * CE - Constant Engine 2352 * The PFP and ME make up what is considered the Drawing Engine (DE). 2353 * The CE is an asynchronous engine used for updating buffer desciptors 2354 * used by the DE so that they can be loaded into cache in parallel 2355 * while the DE is processing state update packets. 2356 * 2357 * Compute 2358 * The compute CP consists of two microengines (ME): 2359 * MEC1 - Compute MicroEngine 1 2360 * MEC2 - Compute MicroEngine 2 2361 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2362 * The queues are exposed to userspace and are programmed directly 2363 * by the compute runtime. 2364 */ 2365 /** 2366 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2367 * 2368 * @adev: amdgpu_device pointer 2369 * @enable: enable or disable the MEs 2370 * 2371 * Halts or unhalts the gfx MEs. 2372 */ 2373 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2374 { 2375 int i; 2376 2377 if (enable) { 2378 WREG32(mmCP_ME_CNTL, 0); 2379 } else { 2380 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2381 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2382 adev->gfx.gfx_ring[i].ready = false; 2383 } 2384 udelay(50); 2385 } 2386 2387 /** 2388 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2389 * 2390 * @adev: amdgpu_device pointer 2391 * 2392 * Loads the gfx PFP, ME, and CE ucode. 2393 * Returns 0 for success, -EINVAL if the ucode is not available. 2394 */ 2395 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2396 { 2397 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2398 const struct gfx_firmware_header_v1_0 *ce_hdr; 2399 const struct gfx_firmware_header_v1_0 *me_hdr; 2400 const __le32 *fw_data; 2401 unsigned i, fw_size; 2402 2403 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2404 return -EINVAL; 2405 2406 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2407 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2408 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2409 2410 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2411 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2412 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2413 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2414 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2415 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2416 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2417 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2418 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2419 2420 gfx_v7_0_cp_gfx_enable(adev, false); 2421 2422 /* PFP */ 2423 fw_data = (const __le32 *) 2424 (adev->gfx.pfp_fw->data + 2425 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2426 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2427 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2428 for (i = 0; i < fw_size; i++) 2429 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2430 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2431 2432 /* CE */ 2433 fw_data = (const __le32 *) 2434 (adev->gfx.ce_fw->data + 2435 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2436 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2437 WREG32(mmCP_CE_UCODE_ADDR, 0); 2438 for (i = 0; i < fw_size; i++) 2439 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2440 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2441 2442 /* ME */ 2443 fw_data = (const __le32 *) 2444 (adev->gfx.me_fw->data + 2445 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2446 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2447 WREG32(mmCP_ME_RAM_WADDR, 0); 2448 for (i = 0; i < fw_size; i++) 2449 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2450 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2451 2452 return 0; 2453 } 2454 2455 /** 2456 * gfx_v7_0_cp_gfx_start - start the gfx ring 2457 * 2458 * @adev: amdgpu_device pointer 2459 * 2460 * Enables the ring and loads the clear state context and other 2461 * packets required to init the ring. 2462 * Returns 0 for success, error for failure. 2463 */ 2464 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2465 { 2466 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2467 const struct cs_section_def *sect = NULL; 2468 const struct cs_extent_def *ext = NULL; 2469 int r, i; 2470 2471 /* init the CP */ 2472 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2473 WREG32(mmCP_ENDIAN_SWAP, 0); 2474 WREG32(mmCP_DEVICE_ID, 1); 2475 2476 gfx_v7_0_cp_gfx_enable(adev, true); 2477 2478 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2479 if (r) { 2480 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2481 return r; 2482 } 2483 2484 /* init the CE partitions. CE only used for gfx on CIK */ 2485 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2486 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2487 amdgpu_ring_write(ring, 0x8000); 2488 amdgpu_ring_write(ring, 0x8000); 2489 2490 /* clear state buffer */ 2491 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2492 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2493 2494 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2495 amdgpu_ring_write(ring, 0x80000000); 2496 amdgpu_ring_write(ring, 0x80000000); 2497 2498 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2499 for (ext = sect->section; ext->extent != NULL; ++ext) { 2500 if (sect->id == SECT_CONTEXT) { 2501 amdgpu_ring_write(ring, 2502 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2503 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2504 for (i = 0; i < ext->reg_count; i++) 2505 amdgpu_ring_write(ring, ext->extent[i]); 2506 } 2507 } 2508 } 2509 2510 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2511 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2512 switch (adev->asic_type) { 2513 case CHIP_BONAIRE: 2514 amdgpu_ring_write(ring, 0x16000012); 2515 amdgpu_ring_write(ring, 0x00000000); 2516 break; 2517 case CHIP_KAVERI: 2518 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2519 amdgpu_ring_write(ring, 0x00000000); 2520 break; 2521 case CHIP_KABINI: 2522 case CHIP_MULLINS: 2523 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2524 amdgpu_ring_write(ring, 0x00000000); 2525 break; 2526 case CHIP_HAWAII: 2527 amdgpu_ring_write(ring, 0x3a00161a); 2528 amdgpu_ring_write(ring, 0x0000002e); 2529 break; 2530 default: 2531 amdgpu_ring_write(ring, 0x00000000); 2532 amdgpu_ring_write(ring, 0x00000000); 2533 break; 2534 } 2535 2536 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2537 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2538 2539 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2540 amdgpu_ring_write(ring, 0); 2541 2542 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2543 amdgpu_ring_write(ring, 0x00000316); 2544 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2545 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2546 2547 amdgpu_ring_commit(ring); 2548 2549 return 0; 2550 } 2551 2552 /** 2553 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2554 * 2555 * @adev: amdgpu_device pointer 2556 * 2557 * Program the location and size of the gfx ring buffer 2558 * and test it to make sure it's working. 2559 * Returns 0 for success, error for failure. 2560 */ 2561 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2562 { 2563 struct amdgpu_ring *ring; 2564 u32 tmp; 2565 u32 rb_bufsz; 2566 u64 rb_addr, rptr_addr; 2567 int r; 2568 2569 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2570 if (adev->asic_type != CHIP_HAWAII) 2571 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2572 2573 /* Set the write pointer delay */ 2574 WREG32(mmCP_RB_WPTR_DELAY, 0); 2575 2576 /* set the RB to use vmid 0 */ 2577 WREG32(mmCP_RB_VMID, 0); 2578 2579 WREG32(mmSCRATCH_ADDR, 0); 2580 2581 /* ring 0 - compute and gfx */ 2582 /* Set ring buffer size */ 2583 ring = &adev->gfx.gfx_ring[0]; 2584 rb_bufsz = order_base_2(ring->ring_size / 8); 2585 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2586 #ifdef __BIG_ENDIAN 2587 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2588 #endif 2589 WREG32(mmCP_RB0_CNTL, tmp); 2590 2591 /* Initialize the ring buffer's read and write pointers */ 2592 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2593 ring->wptr = 0; 2594 WREG32(mmCP_RB0_WPTR, ring->wptr); 2595 2596 /* set the wb address wether it's enabled or not */ 2597 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2598 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2599 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2600 2601 /* scratch register shadowing is no longer supported */ 2602 WREG32(mmSCRATCH_UMSK, 0); 2603 2604 mdelay(1); 2605 WREG32(mmCP_RB0_CNTL, tmp); 2606 2607 rb_addr = ring->gpu_addr >> 8; 2608 WREG32(mmCP_RB0_BASE, rb_addr); 2609 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2610 2611 /* start the ring */ 2612 gfx_v7_0_cp_gfx_start(adev); 2613 ring->ready = true; 2614 r = amdgpu_ring_test_ring(ring); 2615 if (r) { 2616 ring->ready = false; 2617 return r; 2618 } 2619 2620 return 0; 2621 } 2622 2623 static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2624 { 2625 return ring->adev->wb.wb[ring->rptr_offs]; 2626 } 2627 2628 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2629 { 2630 struct amdgpu_device *adev = ring->adev; 2631 2632 return RREG32(mmCP_RB0_WPTR); 2633 } 2634 2635 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2636 { 2637 struct amdgpu_device *adev = ring->adev; 2638 2639 WREG32(mmCP_RB0_WPTR, ring->wptr); 2640 (void)RREG32(mmCP_RB0_WPTR); 2641 } 2642 2643 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2644 { 2645 /* XXX check if swapping is necessary on BE */ 2646 return ring->adev->wb.wb[ring->wptr_offs]; 2647 } 2648 2649 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2650 { 2651 struct amdgpu_device *adev = ring->adev; 2652 2653 /* XXX check if swapping is necessary on BE */ 2654 adev->wb.wb[ring->wptr_offs] = ring->wptr; 2655 WDOORBELL32(ring->doorbell_index, ring->wptr); 2656 } 2657 2658 /** 2659 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2660 * 2661 * @adev: amdgpu_device pointer 2662 * @enable: enable or disable the MEs 2663 * 2664 * Halts or unhalts the compute MEs. 2665 */ 2666 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2667 { 2668 int i; 2669 2670 if (enable) { 2671 WREG32(mmCP_MEC_CNTL, 0); 2672 } else { 2673 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2674 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2675 adev->gfx.compute_ring[i].ready = false; 2676 } 2677 udelay(50); 2678 } 2679 2680 /** 2681 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2682 * 2683 * @adev: amdgpu_device pointer 2684 * 2685 * Loads the compute MEC1&2 ucode. 2686 * Returns 0 for success, -EINVAL if the ucode is not available. 2687 */ 2688 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2689 { 2690 const struct gfx_firmware_header_v1_0 *mec_hdr; 2691 const __le32 *fw_data; 2692 unsigned i, fw_size; 2693 2694 if (!adev->gfx.mec_fw) 2695 return -EINVAL; 2696 2697 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2698 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2699 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2700 adev->gfx.mec_feature_version = le32_to_cpu( 2701 mec_hdr->ucode_feature_version); 2702 2703 gfx_v7_0_cp_compute_enable(adev, false); 2704 2705 /* MEC1 */ 2706 fw_data = (const __le32 *) 2707 (adev->gfx.mec_fw->data + 2708 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2709 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2710 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2711 for (i = 0; i < fw_size; i++) 2712 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2713 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2714 2715 if (adev->asic_type == CHIP_KAVERI) { 2716 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2717 2718 if (!adev->gfx.mec2_fw) 2719 return -EINVAL; 2720 2721 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2722 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2723 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2724 adev->gfx.mec2_feature_version = le32_to_cpu( 2725 mec2_hdr->ucode_feature_version); 2726 2727 /* MEC2 */ 2728 fw_data = (const __le32 *) 2729 (adev->gfx.mec2_fw->data + 2730 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2731 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2732 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2733 for (i = 0; i < fw_size; i++) 2734 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2735 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2736 } 2737 2738 return 0; 2739 } 2740 2741 /** 2742 * gfx_v7_0_cp_compute_fini - stop the compute queues 2743 * 2744 * @adev: amdgpu_device pointer 2745 * 2746 * Stop the compute queues and tear down the driver queue 2747 * info. 2748 */ 2749 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2750 { 2751 int i, r; 2752 2753 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2754 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2755 2756 if (ring->mqd_obj) { 2757 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2758 if (unlikely(r != 0)) 2759 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 2760 2761 amdgpu_bo_unpin(ring->mqd_obj); 2762 amdgpu_bo_unreserve(ring->mqd_obj); 2763 2764 amdgpu_bo_unref(&ring->mqd_obj); 2765 ring->mqd_obj = NULL; 2766 } 2767 } 2768 } 2769 2770 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2771 { 2772 int r; 2773 2774 if (adev->gfx.mec.hpd_eop_obj) { 2775 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2776 if (unlikely(r != 0)) 2777 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 2778 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 2779 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2780 2781 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 2782 adev->gfx.mec.hpd_eop_obj = NULL; 2783 } 2784 } 2785 2786 #define MEC_HPD_SIZE 2048 2787 2788 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2789 { 2790 int r; 2791 u32 *hpd; 2792 2793 /* 2794 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total 2795 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total 2796 * Nonetheless, we assign only 1 pipe because all other pipes will 2797 * be handled by KFD 2798 */ 2799 adev->gfx.mec.num_mec = 1; 2800 adev->gfx.mec.num_pipe = 1; 2801 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 2802 2803 if (adev->gfx.mec.hpd_eop_obj == NULL) { 2804 r = amdgpu_bo_create(adev, 2805 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 2806 PAGE_SIZE, true, 2807 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2808 &adev->gfx.mec.hpd_eop_obj); 2809 if (r) { 2810 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 2811 return r; 2812 } 2813 } 2814 2815 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2816 if (unlikely(r != 0)) { 2817 gfx_v7_0_mec_fini(adev); 2818 return r; 2819 } 2820 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 2821 &adev->gfx.mec.hpd_eop_gpu_addr); 2822 if (r) { 2823 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 2824 gfx_v7_0_mec_fini(adev); 2825 return r; 2826 } 2827 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 2828 if (r) { 2829 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 2830 gfx_v7_0_mec_fini(adev); 2831 return r; 2832 } 2833 2834 /* clear memory. Not sure if this is required or not */ 2835 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 2836 2837 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2838 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2839 2840 return 0; 2841 } 2842 2843 struct hqd_registers 2844 { 2845 u32 cp_mqd_base_addr; 2846 u32 cp_mqd_base_addr_hi; 2847 u32 cp_hqd_active; 2848 u32 cp_hqd_vmid; 2849 u32 cp_hqd_persistent_state; 2850 u32 cp_hqd_pipe_priority; 2851 u32 cp_hqd_queue_priority; 2852 u32 cp_hqd_quantum; 2853 u32 cp_hqd_pq_base; 2854 u32 cp_hqd_pq_base_hi; 2855 u32 cp_hqd_pq_rptr; 2856 u32 cp_hqd_pq_rptr_report_addr; 2857 u32 cp_hqd_pq_rptr_report_addr_hi; 2858 u32 cp_hqd_pq_wptr_poll_addr; 2859 u32 cp_hqd_pq_wptr_poll_addr_hi; 2860 u32 cp_hqd_pq_doorbell_control; 2861 u32 cp_hqd_pq_wptr; 2862 u32 cp_hqd_pq_control; 2863 u32 cp_hqd_ib_base_addr; 2864 u32 cp_hqd_ib_base_addr_hi; 2865 u32 cp_hqd_ib_rptr; 2866 u32 cp_hqd_ib_control; 2867 u32 cp_hqd_iq_timer; 2868 u32 cp_hqd_iq_rptr; 2869 u32 cp_hqd_dequeue_request; 2870 u32 cp_hqd_dma_offload; 2871 u32 cp_hqd_sema_cmd; 2872 u32 cp_hqd_msg_type; 2873 u32 cp_hqd_atomic0_preop_lo; 2874 u32 cp_hqd_atomic0_preop_hi; 2875 u32 cp_hqd_atomic1_preop_lo; 2876 u32 cp_hqd_atomic1_preop_hi; 2877 u32 cp_hqd_hq_scheduler0; 2878 u32 cp_hqd_hq_scheduler1; 2879 u32 cp_mqd_control; 2880 }; 2881 2882 struct bonaire_mqd 2883 { 2884 u32 header; 2885 u32 dispatch_initiator; 2886 u32 dimensions[3]; 2887 u32 start_idx[3]; 2888 u32 num_threads[3]; 2889 u32 pipeline_stat_enable; 2890 u32 perf_counter_enable; 2891 u32 pgm[2]; 2892 u32 tba[2]; 2893 u32 tma[2]; 2894 u32 pgm_rsrc[2]; 2895 u32 vmid; 2896 u32 resource_limits; 2897 u32 static_thread_mgmt01[2]; 2898 u32 tmp_ring_size; 2899 u32 static_thread_mgmt23[2]; 2900 u32 restart[3]; 2901 u32 thread_trace_enable; 2902 u32 reserved1; 2903 u32 user_data[16]; 2904 u32 vgtcs_invoke_count[2]; 2905 struct hqd_registers queue_state; 2906 u32 dequeue_cntr; 2907 u32 interrupt_queue[64]; 2908 }; 2909 2910 /** 2911 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 2912 * 2913 * @adev: amdgpu_device pointer 2914 * 2915 * Program the compute queues and test them to make sure they 2916 * are working. 2917 * Returns 0 for success, error for failure. 2918 */ 2919 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 2920 { 2921 int r, i, j; 2922 u32 tmp; 2923 bool use_doorbell = true; 2924 u64 hqd_gpu_addr; 2925 u64 mqd_gpu_addr; 2926 u64 eop_gpu_addr; 2927 u64 wb_gpu_addr; 2928 u32 *buf; 2929 struct bonaire_mqd *mqd; 2930 struct amdgpu_ring *ring; 2931 2932 /* fix up chicken bits */ 2933 tmp = RREG32(mmCP_CPF_DEBUG); 2934 tmp |= (1 << 23); 2935 WREG32(mmCP_CPF_DEBUG, tmp); 2936 2937 /* init the pipes */ 2938 mutex_lock(&adev->srbm_mutex); 2939 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 2940 int me = (i < 4) ? 1 : 2; 2941 int pipe = (i < 4) ? i : (i - 4); 2942 2943 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); 2944 2945 cik_srbm_select(adev, me, pipe, 0, 0); 2946 2947 /* write the EOP addr */ 2948 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2949 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2950 2951 /* set the VMID assigned */ 2952 WREG32(mmCP_HPD_EOP_VMID, 0); 2953 2954 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2955 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2956 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2957 tmp |= order_base_2(MEC_HPD_SIZE / 8); 2958 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2959 } 2960 cik_srbm_select(adev, 0, 0, 0, 0); 2961 mutex_unlock(&adev->srbm_mutex); 2962 2963 /* init the queues. Just two for now. */ 2964 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2965 ring = &adev->gfx.compute_ring[i]; 2966 2967 if (ring->mqd_obj == NULL) { 2968 r = amdgpu_bo_create(adev, 2969 sizeof(struct bonaire_mqd), 2970 PAGE_SIZE, true, 2971 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2972 &ring->mqd_obj); 2973 if (r) { 2974 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 2975 return r; 2976 } 2977 } 2978 2979 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2980 if (unlikely(r != 0)) { 2981 gfx_v7_0_cp_compute_fini(adev); 2982 return r; 2983 } 2984 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 2985 &mqd_gpu_addr); 2986 if (r) { 2987 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 2988 gfx_v7_0_cp_compute_fini(adev); 2989 return r; 2990 } 2991 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 2992 if (r) { 2993 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 2994 gfx_v7_0_cp_compute_fini(adev); 2995 return r; 2996 } 2997 2998 /* init the mqd struct */ 2999 memset(buf, 0, sizeof(struct bonaire_mqd)); 3000 3001 mqd = (struct bonaire_mqd *)buf; 3002 mqd->header = 0xC0310800; 3003 mqd->static_thread_mgmt01[0] = 0xffffffff; 3004 mqd->static_thread_mgmt01[1] = 0xffffffff; 3005 mqd->static_thread_mgmt23[0] = 0xffffffff; 3006 mqd->static_thread_mgmt23[1] = 0xffffffff; 3007 3008 mutex_lock(&adev->srbm_mutex); 3009 cik_srbm_select(adev, ring->me, 3010 ring->pipe, 3011 ring->queue, 0); 3012 3013 /* disable wptr polling */ 3014 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3015 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; 3016 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3017 3018 /* enable doorbell? */ 3019 mqd->queue_state.cp_hqd_pq_doorbell_control = 3020 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3021 if (use_doorbell) 3022 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3023 else 3024 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3025 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3026 mqd->queue_state.cp_hqd_pq_doorbell_control); 3027 3028 /* disable the queue if it's active */ 3029 mqd->queue_state.cp_hqd_dequeue_request = 0; 3030 mqd->queue_state.cp_hqd_pq_rptr = 0; 3031 mqd->queue_state.cp_hqd_pq_wptr= 0; 3032 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 3033 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 3034 for (j = 0; j < adev->usec_timeout; j++) { 3035 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 3036 break; 3037 udelay(1); 3038 } 3039 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); 3040 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); 3041 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 3042 } 3043 3044 /* set the pointer to the MQD */ 3045 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; 3046 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3047 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); 3048 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); 3049 /* set MQD vmid to 0 */ 3050 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 3051 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 3052 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); 3053 3054 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3055 hqd_gpu_addr = ring->gpu_addr >> 8; 3056 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; 3057 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3058 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); 3059 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); 3060 3061 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3062 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 3063 mqd->queue_state.cp_hqd_pq_control &= 3064 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 3065 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 3066 3067 mqd->queue_state.cp_hqd_pq_control |= 3068 order_base_2(ring->ring_size / 8); 3069 mqd->queue_state.cp_hqd_pq_control |= 3070 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 3071 #ifdef __BIG_ENDIAN 3072 mqd->queue_state.cp_hqd_pq_control |= 3073 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 3074 #endif 3075 mqd->queue_state.cp_hqd_pq_control &= 3076 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 3077 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 3078 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 3079 mqd->queue_state.cp_hqd_pq_control |= 3080 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 3081 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 3082 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); 3083 3084 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3085 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3086 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 3087 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3088 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); 3089 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3090 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); 3091 3092 /* set the wb address wether it's enabled or not */ 3093 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3094 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; 3095 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = 3096 upper_32_bits(wb_gpu_addr) & 0xffff; 3097 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3098 mqd->queue_state.cp_hqd_pq_rptr_report_addr); 3099 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3100 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); 3101 3102 /* enable the doorbell if requested */ 3103 if (use_doorbell) { 3104 mqd->queue_state.cp_hqd_pq_doorbell_control = 3105 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3106 mqd->queue_state.cp_hqd_pq_doorbell_control &= 3107 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 3108 mqd->queue_state.cp_hqd_pq_doorbell_control |= 3109 (ring->doorbell_index << 3110 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 3111 mqd->queue_state.cp_hqd_pq_doorbell_control |= 3112 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3113 mqd->queue_state.cp_hqd_pq_doorbell_control &= 3114 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 3115 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 3116 3117 } else { 3118 mqd->queue_state.cp_hqd_pq_doorbell_control = 0; 3119 } 3120 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3121 mqd->queue_state.cp_hqd_pq_doorbell_control); 3122 3123 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3124 ring->wptr = 0; 3125 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; 3126 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 3127 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3128 3129 /* set the vmid for the queue */ 3130 mqd->queue_state.cp_hqd_vmid = 0; 3131 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); 3132 3133 /* activate the queue */ 3134 mqd->queue_state.cp_hqd_active = 1; 3135 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 3136 3137 cik_srbm_select(adev, 0, 0, 0, 0); 3138 mutex_unlock(&adev->srbm_mutex); 3139 3140 amdgpu_bo_kunmap(ring->mqd_obj); 3141 amdgpu_bo_unreserve(ring->mqd_obj); 3142 3143 ring->ready = true; 3144 } 3145 3146 gfx_v7_0_cp_compute_enable(adev, true); 3147 3148 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3149 ring = &adev->gfx.compute_ring[i]; 3150 3151 r = amdgpu_ring_test_ring(ring); 3152 if (r) 3153 ring->ready = false; 3154 } 3155 3156 return 0; 3157 } 3158 3159 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3160 { 3161 gfx_v7_0_cp_gfx_enable(adev, enable); 3162 gfx_v7_0_cp_compute_enable(adev, enable); 3163 } 3164 3165 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3166 { 3167 int r; 3168 3169 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3170 if (r) 3171 return r; 3172 r = gfx_v7_0_cp_compute_load_microcode(adev); 3173 if (r) 3174 return r; 3175 3176 return 0; 3177 } 3178 3179 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3180 bool enable) 3181 { 3182 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3183 3184 if (enable) 3185 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3186 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3187 else 3188 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3189 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3190 WREG32(mmCP_INT_CNTL_RING0, tmp); 3191 } 3192 3193 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3194 { 3195 int r; 3196 3197 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3198 3199 r = gfx_v7_0_cp_load_microcode(adev); 3200 if (r) 3201 return r; 3202 3203 r = gfx_v7_0_cp_gfx_resume(adev); 3204 if (r) 3205 return r; 3206 r = gfx_v7_0_cp_compute_resume(adev); 3207 if (r) 3208 return r; 3209 3210 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3211 3212 return 0; 3213 } 3214 3215 /** 3216 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3217 * 3218 * @ring: the ring to emmit the commands to 3219 * 3220 * Sync the command pipeline with the PFP. E.g. wait for everything 3221 * to be completed. 3222 */ 3223 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3224 { 3225 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3226 uint32_t seq = ring->fence_drv.sync_seq; 3227 uint64_t addr = ring->fence_drv.gpu_addr; 3228 3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3230 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3231 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3232 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3233 amdgpu_ring_write(ring, addr & 0xfffffffc); 3234 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3235 amdgpu_ring_write(ring, seq); 3236 amdgpu_ring_write(ring, 0xffffffff); 3237 amdgpu_ring_write(ring, 4); /* poll interval */ 3238 3239 if (usepfp) { 3240 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3241 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3242 amdgpu_ring_write(ring, 0); 3243 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3244 amdgpu_ring_write(ring, 0); 3245 } 3246 } 3247 3248 /* 3249 * vm 3250 * VMID 0 is the physical GPU addresses as used by the kernel. 3251 * VMIDs 1-15 are used for userspace clients and are handled 3252 * by the amdgpu vm/hsa code. 3253 */ 3254 /** 3255 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3256 * 3257 * @adev: amdgpu_device pointer 3258 * 3259 * Update the page table base and flush the VM TLB 3260 * using the CP (CIK). 3261 */ 3262 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3263 unsigned vm_id, uint64_t pd_addr) 3264 { 3265 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3266 3267 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3268 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3269 WRITE_DATA_DST_SEL(0))); 3270 if (vm_id < 8) { 3271 amdgpu_ring_write(ring, 3272 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3273 } else { 3274 amdgpu_ring_write(ring, 3275 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3276 } 3277 amdgpu_ring_write(ring, 0); 3278 amdgpu_ring_write(ring, pd_addr >> 12); 3279 3280 /* bits 0-15 are the VM contexts0-15 */ 3281 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3282 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3283 WRITE_DATA_DST_SEL(0))); 3284 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3285 amdgpu_ring_write(ring, 0); 3286 amdgpu_ring_write(ring, 1 << vm_id); 3287 3288 /* wait for the invalidate to complete */ 3289 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3290 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3291 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3292 WAIT_REG_MEM_ENGINE(0))); /* me */ 3293 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3294 amdgpu_ring_write(ring, 0); 3295 amdgpu_ring_write(ring, 0); /* ref */ 3296 amdgpu_ring_write(ring, 0); /* mask */ 3297 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3298 3299 /* compute doesn't have PFP */ 3300 if (usepfp) { 3301 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3302 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3303 amdgpu_ring_write(ring, 0x0); 3304 3305 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3306 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3307 amdgpu_ring_write(ring, 0); 3308 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3309 amdgpu_ring_write(ring, 0); 3310 } 3311 } 3312 3313 /* 3314 * RLC 3315 * The RLC is a multi-purpose microengine that handles a 3316 * variety of functions. 3317 */ 3318 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) 3319 { 3320 int r; 3321 3322 /* save restore block */ 3323 if (adev->gfx.rlc.save_restore_obj) { 3324 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3325 if (unlikely(r != 0)) 3326 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); 3327 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); 3328 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3329 3330 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); 3331 adev->gfx.rlc.save_restore_obj = NULL; 3332 } 3333 3334 /* clear state block */ 3335 if (adev->gfx.rlc.clear_state_obj) { 3336 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3337 if (unlikely(r != 0)) 3338 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); 3339 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 3340 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3341 3342 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 3343 adev->gfx.rlc.clear_state_obj = NULL; 3344 } 3345 3346 /* clear state block */ 3347 if (adev->gfx.rlc.cp_table_obj) { 3348 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3349 if (unlikely(r != 0)) 3350 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3351 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); 3352 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3353 3354 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); 3355 adev->gfx.rlc.cp_table_obj = NULL; 3356 } 3357 } 3358 3359 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3360 { 3361 const u32 *src_ptr; 3362 volatile u32 *dst_ptr; 3363 u32 dws, i; 3364 const struct cs_section_def *cs_data; 3365 int r; 3366 3367 /* allocate rlc buffers */ 3368 if (adev->flags & AMD_IS_APU) { 3369 if (adev->asic_type == CHIP_KAVERI) { 3370 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3371 adev->gfx.rlc.reg_list_size = 3372 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3373 } else { 3374 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3375 adev->gfx.rlc.reg_list_size = 3376 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3377 } 3378 } 3379 adev->gfx.rlc.cs_data = ci_cs_data; 3380 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3381 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3382 3383 src_ptr = adev->gfx.rlc.reg_list; 3384 dws = adev->gfx.rlc.reg_list_size; 3385 dws += (5 * 16) + 48 + 48 + 64; 3386 3387 cs_data = adev->gfx.rlc.cs_data; 3388 3389 if (src_ptr) { 3390 /* save restore block */ 3391 if (adev->gfx.rlc.save_restore_obj == NULL) { 3392 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3393 AMDGPU_GEM_DOMAIN_VRAM, 3394 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3395 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3396 NULL, NULL, 3397 &adev->gfx.rlc.save_restore_obj); 3398 if (r) { 3399 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); 3400 return r; 3401 } 3402 } 3403 3404 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3405 if (unlikely(r != 0)) { 3406 gfx_v7_0_rlc_fini(adev); 3407 return r; 3408 } 3409 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, 3410 &adev->gfx.rlc.save_restore_gpu_addr); 3411 if (r) { 3412 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3413 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); 3414 gfx_v7_0_rlc_fini(adev); 3415 return r; 3416 } 3417 3418 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); 3419 if (r) { 3420 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); 3421 gfx_v7_0_rlc_fini(adev); 3422 return r; 3423 } 3424 /* write the sr buffer */ 3425 dst_ptr = adev->gfx.rlc.sr_ptr; 3426 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3427 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 3428 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 3429 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3430 } 3431 3432 if (cs_data) { 3433 /* clear state block */ 3434 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); 3435 3436 if (adev->gfx.rlc.clear_state_obj == NULL) { 3437 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3438 AMDGPU_GEM_DOMAIN_VRAM, 3439 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3440 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3441 NULL, NULL, 3442 &adev->gfx.rlc.clear_state_obj); 3443 if (r) { 3444 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 3445 gfx_v7_0_rlc_fini(adev); 3446 return r; 3447 } 3448 } 3449 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3450 if (unlikely(r != 0)) { 3451 gfx_v7_0_rlc_fini(adev); 3452 return r; 3453 } 3454 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, 3455 &adev->gfx.rlc.clear_state_gpu_addr); 3456 if (r) { 3457 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3458 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); 3459 gfx_v7_0_rlc_fini(adev); 3460 return r; 3461 } 3462 3463 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); 3464 if (r) { 3465 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); 3466 gfx_v7_0_rlc_fini(adev); 3467 return r; 3468 } 3469 /* set up the cs buffer */ 3470 dst_ptr = adev->gfx.rlc.cs_ptr; 3471 gfx_v7_0_get_csb_buffer(adev, dst_ptr); 3472 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 3473 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3474 } 3475 3476 if (adev->gfx.rlc.cp_table_size) { 3477 if (adev->gfx.rlc.cp_table_obj == NULL) { 3478 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, 3479 AMDGPU_GEM_DOMAIN_VRAM, 3480 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3481 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3482 NULL, NULL, 3483 &adev->gfx.rlc.cp_table_obj); 3484 if (r) { 3485 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 3486 gfx_v7_0_rlc_fini(adev); 3487 return r; 3488 } 3489 } 3490 3491 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3492 if (unlikely(r != 0)) { 3493 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3494 gfx_v7_0_rlc_fini(adev); 3495 return r; 3496 } 3497 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, 3498 &adev->gfx.rlc.cp_table_gpu_addr); 3499 if (r) { 3500 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3501 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); 3502 gfx_v7_0_rlc_fini(adev); 3503 return r; 3504 } 3505 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); 3506 if (r) { 3507 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); 3508 gfx_v7_0_rlc_fini(adev); 3509 return r; 3510 } 3511 3512 gfx_v7_0_init_cp_pg_table(adev); 3513 3514 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 3515 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3516 3517 } 3518 3519 return 0; 3520 } 3521 3522 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3523 { 3524 u32 tmp; 3525 3526 tmp = RREG32(mmRLC_LB_CNTL); 3527 if (enable) 3528 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3529 else 3530 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3531 WREG32(mmRLC_LB_CNTL, tmp); 3532 } 3533 3534 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3535 { 3536 u32 i, j, k; 3537 u32 mask; 3538 3539 mutex_lock(&adev->grbm_idx_mutex); 3540 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3541 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3542 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3543 for (k = 0; k < adev->usec_timeout; k++) { 3544 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3545 break; 3546 udelay(1); 3547 } 3548 } 3549 } 3550 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3551 mutex_unlock(&adev->grbm_idx_mutex); 3552 3553 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3554 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3555 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3556 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3557 for (k = 0; k < adev->usec_timeout; k++) { 3558 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3559 break; 3560 udelay(1); 3561 } 3562 } 3563 3564 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3565 { 3566 u32 tmp; 3567 3568 tmp = RREG32(mmRLC_CNTL); 3569 if (tmp != rlc) 3570 WREG32(mmRLC_CNTL, rlc); 3571 } 3572 3573 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3574 { 3575 u32 data, orig; 3576 3577 orig = data = RREG32(mmRLC_CNTL); 3578 3579 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3580 u32 i; 3581 3582 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3583 WREG32(mmRLC_CNTL, data); 3584 3585 for (i = 0; i < adev->usec_timeout; i++) { 3586 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3587 break; 3588 udelay(1); 3589 } 3590 3591 gfx_v7_0_wait_for_rlc_serdes(adev); 3592 } 3593 3594 return orig; 3595 } 3596 3597 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3598 { 3599 u32 tmp, i, mask; 3600 3601 tmp = 0x1 | (1 << 1); 3602 WREG32(mmRLC_GPR_REG2, tmp); 3603 3604 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3605 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3606 for (i = 0; i < adev->usec_timeout; i++) { 3607 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3608 break; 3609 udelay(1); 3610 } 3611 3612 for (i = 0; i < adev->usec_timeout; i++) { 3613 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3614 break; 3615 udelay(1); 3616 } 3617 } 3618 3619 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3620 { 3621 u32 tmp; 3622 3623 tmp = 0x1 | (0 << 1); 3624 WREG32(mmRLC_GPR_REG2, tmp); 3625 } 3626 3627 /** 3628 * gfx_v7_0_rlc_stop - stop the RLC ME 3629 * 3630 * @adev: amdgpu_device pointer 3631 * 3632 * Halt the RLC ME (MicroEngine) (CIK). 3633 */ 3634 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3635 { 3636 WREG32(mmRLC_CNTL, 0); 3637 3638 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3639 3640 gfx_v7_0_wait_for_rlc_serdes(adev); 3641 } 3642 3643 /** 3644 * gfx_v7_0_rlc_start - start the RLC ME 3645 * 3646 * @adev: amdgpu_device pointer 3647 * 3648 * Unhalt the RLC ME (MicroEngine) (CIK). 3649 */ 3650 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3651 { 3652 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3653 3654 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3655 3656 udelay(50); 3657 } 3658 3659 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3660 { 3661 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3662 3663 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3664 WREG32(mmGRBM_SOFT_RESET, tmp); 3665 udelay(50); 3666 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3667 WREG32(mmGRBM_SOFT_RESET, tmp); 3668 udelay(50); 3669 } 3670 3671 /** 3672 * gfx_v7_0_rlc_resume - setup the RLC hw 3673 * 3674 * @adev: amdgpu_device pointer 3675 * 3676 * Initialize the RLC registers, load the ucode, 3677 * and start the RLC (CIK). 3678 * Returns 0 for success, -EINVAL if the ucode is not available. 3679 */ 3680 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3681 { 3682 const struct rlc_firmware_header_v1_0 *hdr; 3683 const __le32 *fw_data; 3684 unsigned i, fw_size; 3685 u32 tmp; 3686 3687 if (!adev->gfx.rlc_fw) 3688 return -EINVAL; 3689 3690 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3691 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3692 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3693 adev->gfx.rlc_feature_version = le32_to_cpu( 3694 hdr->ucode_feature_version); 3695 3696 gfx_v7_0_rlc_stop(adev); 3697 3698 /* disable CG */ 3699 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3700 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3701 3702 gfx_v7_0_rlc_reset(adev); 3703 3704 gfx_v7_0_init_pg(adev); 3705 3706 WREG32(mmRLC_LB_CNTR_INIT, 0); 3707 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3708 3709 mutex_lock(&adev->grbm_idx_mutex); 3710 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3711 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3712 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3713 WREG32(mmRLC_LB_CNTL, 0x80000004); 3714 mutex_unlock(&adev->grbm_idx_mutex); 3715 3716 WREG32(mmRLC_MC_CNTL, 0); 3717 WREG32(mmRLC_UCODE_CNTL, 0); 3718 3719 fw_data = (const __le32 *) 3720 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3721 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3722 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3723 for (i = 0; i < fw_size; i++) 3724 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3725 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3726 3727 /* XXX - find out what chips support lbpw */ 3728 gfx_v7_0_enable_lbpw(adev, false); 3729 3730 if (adev->asic_type == CHIP_BONAIRE) 3731 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3732 3733 gfx_v7_0_rlc_start(adev); 3734 3735 return 0; 3736 } 3737 3738 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3739 { 3740 u32 data, orig, tmp, tmp2; 3741 3742 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3743 3744 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3745 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3746 3747 tmp = gfx_v7_0_halt_rlc(adev); 3748 3749 mutex_lock(&adev->grbm_idx_mutex); 3750 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3751 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3752 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3753 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3754 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3755 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3756 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3757 mutex_unlock(&adev->grbm_idx_mutex); 3758 3759 gfx_v7_0_update_rlc(adev, tmp); 3760 3761 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3762 } else { 3763 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3764 3765 RREG32(mmCB_CGTT_SCLK_CTRL); 3766 RREG32(mmCB_CGTT_SCLK_CTRL); 3767 RREG32(mmCB_CGTT_SCLK_CTRL); 3768 RREG32(mmCB_CGTT_SCLK_CTRL); 3769 3770 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3771 } 3772 3773 if (orig != data) 3774 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3775 3776 } 3777 3778 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3779 { 3780 u32 data, orig, tmp = 0; 3781 3782 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3783 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3784 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3785 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3786 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3787 if (orig != data) 3788 WREG32(mmCP_MEM_SLP_CNTL, data); 3789 } 3790 } 3791 3792 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3793 data |= 0x00000001; 3794 data &= 0xfffffffd; 3795 if (orig != data) 3796 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3797 3798 tmp = gfx_v7_0_halt_rlc(adev); 3799 3800 mutex_lock(&adev->grbm_idx_mutex); 3801 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3802 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3803 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3804 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3805 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3806 WREG32(mmRLC_SERDES_WR_CTRL, data); 3807 mutex_unlock(&adev->grbm_idx_mutex); 3808 3809 gfx_v7_0_update_rlc(adev, tmp); 3810 3811 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3812 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3813 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3814 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3815 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3816 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3817 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3818 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3819 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3820 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3821 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3822 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3823 if (orig != data) 3824 WREG32(mmCGTS_SM_CTRL_REG, data); 3825 } 3826 } else { 3827 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3828 data |= 0x00000003; 3829 if (orig != data) 3830 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3831 3832 data = RREG32(mmRLC_MEM_SLP_CNTL); 3833 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3834 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3835 WREG32(mmRLC_MEM_SLP_CNTL, data); 3836 } 3837 3838 data = RREG32(mmCP_MEM_SLP_CNTL); 3839 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3840 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3841 WREG32(mmCP_MEM_SLP_CNTL, data); 3842 } 3843 3844 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3845 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3846 if (orig != data) 3847 WREG32(mmCGTS_SM_CTRL_REG, data); 3848 3849 tmp = gfx_v7_0_halt_rlc(adev); 3850 3851 mutex_lock(&adev->grbm_idx_mutex); 3852 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3853 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3854 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3855 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3856 WREG32(mmRLC_SERDES_WR_CTRL, data); 3857 mutex_unlock(&adev->grbm_idx_mutex); 3858 3859 gfx_v7_0_update_rlc(adev, tmp); 3860 } 3861 } 3862 3863 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3864 bool enable) 3865 { 3866 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3867 /* order matters! */ 3868 if (enable) { 3869 gfx_v7_0_enable_mgcg(adev, true); 3870 gfx_v7_0_enable_cgcg(adev, true); 3871 } else { 3872 gfx_v7_0_enable_cgcg(adev, false); 3873 gfx_v7_0_enable_mgcg(adev, false); 3874 } 3875 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3876 } 3877 3878 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3879 bool enable) 3880 { 3881 u32 data, orig; 3882 3883 orig = data = RREG32(mmRLC_PG_CNTL); 3884 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3885 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3886 else 3887 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3888 if (orig != data) 3889 WREG32(mmRLC_PG_CNTL, data); 3890 } 3891 3892 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3893 bool enable) 3894 { 3895 u32 data, orig; 3896 3897 orig = data = RREG32(mmRLC_PG_CNTL); 3898 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3899 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3900 else 3901 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3902 if (orig != data) 3903 WREG32(mmRLC_PG_CNTL, data); 3904 } 3905 3906 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3907 { 3908 u32 data, orig; 3909 3910 orig = data = RREG32(mmRLC_PG_CNTL); 3911 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3912 data &= ~0x8000; 3913 else 3914 data |= 0x8000; 3915 if (orig != data) 3916 WREG32(mmRLC_PG_CNTL, data); 3917 } 3918 3919 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3920 { 3921 u32 data, orig; 3922 3923 orig = data = RREG32(mmRLC_PG_CNTL); 3924 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3925 data &= ~0x2000; 3926 else 3927 data |= 0x2000; 3928 if (orig != data) 3929 WREG32(mmRLC_PG_CNTL, data); 3930 } 3931 3932 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) 3933 { 3934 const __le32 *fw_data; 3935 volatile u32 *dst_ptr; 3936 int me, i, max_me = 4; 3937 u32 bo_offset = 0; 3938 u32 table_offset, table_size; 3939 3940 if (adev->asic_type == CHIP_KAVERI) 3941 max_me = 5; 3942 3943 if (adev->gfx.rlc.cp_table_ptr == NULL) 3944 return; 3945 3946 /* write the cp table buffer */ 3947 dst_ptr = adev->gfx.rlc.cp_table_ptr; 3948 for (me = 0; me < max_me; me++) { 3949 if (me == 0) { 3950 const struct gfx_firmware_header_v1_0 *hdr = 3951 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3952 fw_data = (const __le32 *) 3953 (adev->gfx.ce_fw->data + 3954 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3955 table_offset = le32_to_cpu(hdr->jt_offset); 3956 table_size = le32_to_cpu(hdr->jt_size); 3957 } else if (me == 1) { 3958 const struct gfx_firmware_header_v1_0 *hdr = 3959 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3960 fw_data = (const __le32 *) 3961 (adev->gfx.pfp_fw->data + 3962 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3963 table_offset = le32_to_cpu(hdr->jt_offset); 3964 table_size = le32_to_cpu(hdr->jt_size); 3965 } else if (me == 2) { 3966 const struct gfx_firmware_header_v1_0 *hdr = 3967 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3968 fw_data = (const __le32 *) 3969 (adev->gfx.me_fw->data + 3970 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3971 table_offset = le32_to_cpu(hdr->jt_offset); 3972 table_size = le32_to_cpu(hdr->jt_size); 3973 } else if (me == 3) { 3974 const struct gfx_firmware_header_v1_0 *hdr = 3975 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3976 fw_data = (const __le32 *) 3977 (adev->gfx.mec_fw->data + 3978 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3979 table_offset = le32_to_cpu(hdr->jt_offset); 3980 table_size = le32_to_cpu(hdr->jt_size); 3981 } else { 3982 const struct gfx_firmware_header_v1_0 *hdr = 3983 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 3984 fw_data = (const __le32 *) 3985 (adev->gfx.mec2_fw->data + 3986 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3987 table_offset = le32_to_cpu(hdr->jt_offset); 3988 table_size = le32_to_cpu(hdr->jt_size); 3989 } 3990 3991 for (i = 0; i < table_size; i ++) { 3992 dst_ptr[bo_offset + i] = 3993 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 3994 } 3995 3996 bo_offset += table_size; 3997 } 3998 } 3999 4000 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 4001 bool enable) 4002 { 4003 u32 data, orig; 4004 4005 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 4006 orig = data = RREG32(mmRLC_PG_CNTL); 4007 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 4008 if (orig != data) 4009 WREG32(mmRLC_PG_CNTL, data); 4010 4011 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 4012 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 4013 if (orig != data) 4014 WREG32(mmRLC_AUTO_PG_CTRL, data); 4015 } else { 4016 orig = data = RREG32(mmRLC_PG_CNTL); 4017 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 4018 if (orig != data) 4019 WREG32(mmRLC_PG_CNTL, data); 4020 4021 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 4022 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 4023 if (orig != data) 4024 WREG32(mmRLC_AUTO_PG_CTRL, data); 4025 4026 data = RREG32(mmDB_RENDER_CONTROL); 4027 } 4028 } 4029 4030 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4031 u32 bitmap) 4032 { 4033 u32 data; 4034 4035 if (!bitmap) 4036 return; 4037 4038 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4039 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4040 4041 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 4042 } 4043 4044 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4045 { 4046 u32 data, mask; 4047 4048 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 4049 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 4050 4051 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4052 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4053 4054 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 4055 4056 return (~data) & mask; 4057 } 4058 4059 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 4060 { 4061 u32 tmp; 4062 4063 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4064 4065 tmp = RREG32(mmRLC_MAX_PG_CU); 4066 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 4067 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 4068 WREG32(mmRLC_MAX_PG_CU, tmp); 4069 } 4070 4071 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 4072 bool enable) 4073 { 4074 u32 data, orig; 4075 4076 orig = data = RREG32(mmRLC_PG_CNTL); 4077 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 4078 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4079 else 4080 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4081 if (orig != data) 4082 WREG32(mmRLC_PG_CNTL, data); 4083 } 4084 4085 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 4086 bool enable) 4087 { 4088 u32 data, orig; 4089 4090 orig = data = RREG32(mmRLC_PG_CNTL); 4091 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 4092 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4093 else 4094 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4095 if (orig != data) 4096 WREG32(mmRLC_PG_CNTL, data); 4097 } 4098 4099 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 4100 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 4101 4102 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 4103 { 4104 u32 data, orig; 4105 u32 i; 4106 4107 if (adev->gfx.rlc.cs_data) { 4108 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 4109 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 4110 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 4111 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 4112 } else { 4113 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 4114 for (i = 0; i < 3; i++) 4115 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 4116 } 4117 if (adev->gfx.rlc.reg_list) { 4118 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 4119 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 4120 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 4121 } 4122 4123 orig = data = RREG32(mmRLC_PG_CNTL); 4124 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 4125 if (orig != data) 4126 WREG32(mmRLC_PG_CNTL, data); 4127 4128 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 4129 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4130 4131 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 4132 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 4133 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4134 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 4135 4136 data = 0x10101010; 4137 WREG32(mmRLC_PG_DELAY, data); 4138 4139 data = RREG32(mmRLC_PG_DELAY_2); 4140 data &= ~0xff; 4141 data |= 0x3; 4142 WREG32(mmRLC_PG_DELAY_2, data); 4143 4144 data = RREG32(mmRLC_AUTO_PG_CTRL); 4145 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 4146 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 4147 WREG32(mmRLC_AUTO_PG_CTRL, data); 4148 4149 } 4150 4151 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 4152 { 4153 gfx_v7_0_enable_gfx_cgpg(adev, enable); 4154 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 4155 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 4156 } 4157 4158 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 4159 { 4160 u32 count = 0; 4161 const struct cs_section_def *sect = NULL; 4162 const struct cs_extent_def *ext = NULL; 4163 4164 if (adev->gfx.rlc.cs_data == NULL) 4165 return 0; 4166 4167 /* begin clear state */ 4168 count += 2; 4169 /* context control state */ 4170 count += 3; 4171 4172 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4173 for (ext = sect->section; ext->extent != NULL; ++ext) { 4174 if (sect->id == SECT_CONTEXT) 4175 count += 2 + ext->reg_count; 4176 else 4177 return 0; 4178 } 4179 } 4180 /* pa_sc_raster_config/pa_sc_raster_config1 */ 4181 count += 4; 4182 /* end clear state */ 4183 count += 2; 4184 /* clear state */ 4185 count += 2; 4186 4187 return count; 4188 } 4189 4190 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 4191 volatile u32 *buffer) 4192 { 4193 u32 count = 0, i; 4194 const struct cs_section_def *sect = NULL; 4195 const struct cs_extent_def *ext = NULL; 4196 4197 if (adev->gfx.rlc.cs_data == NULL) 4198 return; 4199 if (buffer == NULL) 4200 return; 4201 4202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4203 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4204 4205 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4206 buffer[count++] = cpu_to_le32(0x80000000); 4207 buffer[count++] = cpu_to_le32(0x80000000); 4208 4209 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4210 for (ext = sect->section; ext->extent != NULL; ++ext) { 4211 if (sect->id == SECT_CONTEXT) { 4212 buffer[count++] = 4213 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4214 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4215 for (i = 0; i < ext->reg_count; i++) 4216 buffer[count++] = cpu_to_le32(ext->extent[i]); 4217 } else { 4218 return; 4219 } 4220 } 4221 } 4222 4223 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4224 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4225 switch (adev->asic_type) { 4226 case CHIP_BONAIRE: 4227 buffer[count++] = cpu_to_le32(0x16000012); 4228 buffer[count++] = cpu_to_le32(0x00000000); 4229 break; 4230 case CHIP_KAVERI: 4231 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4232 buffer[count++] = cpu_to_le32(0x00000000); 4233 break; 4234 case CHIP_KABINI: 4235 case CHIP_MULLINS: 4236 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4237 buffer[count++] = cpu_to_le32(0x00000000); 4238 break; 4239 case CHIP_HAWAII: 4240 buffer[count++] = cpu_to_le32(0x3a00161a); 4241 buffer[count++] = cpu_to_le32(0x0000002e); 4242 break; 4243 default: 4244 buffer[count++] = cpu_to_le32(0x00000000); 4245 buffer[count++] = cpu_to_le32(0x00000000); 4246 break; 4247 } 4248 4249 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4250 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4251 4252 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4253 buffer[count++] = cpu_to_le32(0); 4254 } 4255 4256 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4257 { 4258 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4259 AMD_PG_SUPPORT_GFX_SMG | 4260 AMD_PG_SUPPORT_GFX_DMG | 4261 AMD_PG_SUPPORT_CP | 4262 AMD_PG_SUPPORT_GDS | 4263 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4264 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4265 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4266 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4267 gfx_v7_0_init_gfx_cgpg(adev); 4268 gfx_v7_0_enable_cp_pg(adev, true); 4269 gfx_v7_0_enable_gds_pg(adev, true); 4270 } 4271 gfx_v7_0_init_ao_cu_mask(adev); 4272 gfx_v7_0_update_gfx_pg(adev, true); 4273 } 4274 } 4275 4276 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4277 { 4278 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4279 AMD_PG_SUPPORT_GFX_SMG | 4280 AMD_PG_SUPPORT_GFX_DMG | 4281 AMD_PG_SUPPORT_CP | 4282 AMD_PG_SUPPORT_GDS | 4283 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4284 gfx_v7_0_update_gfx_pg(adev, false); 4285 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4286 gfx_v7_0_enable_cp_pg(adev, false); 4287 gfx_v7_0_enable_gds_pg(adev, false); 4288 } 4289 } 4290 } 4291 4292 /** 4293 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4294 * 4295 * @adev: amdgpu_device pointer 4296 * 4297 * Fetches a GPU clock counter snapshot (SI). 4298 * Returns the 64 bit clock counter snapshot. 4299 */ 4300 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4301 { 4302 uint64_t clock; 4303 4304 mutex_lock(&adev->gfx.gpu_clock_mutex); 4305 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4306 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4307 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4308 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4309 return clock; 4310 } 4311 4312 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4313 uint32_t vmid, 4314 uint32_t gds_base, uint32_t gds_size, 4315 uint32_t gws_base, uint32_t gws_size, 4316 uint32_t oa_base, uint32_t oa_size) 4317 { 4318 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 4319 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 4320 4321 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 4322 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 4323 4324 oa_base = oa_base >> AMDGPU_OA_SHIFT; 4325 oa_size = oa_size >> AMDGPU_OA_SHIFT; 4326 4327 /* GDS Base */ 4328 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4329 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4330 WRITE_DATA_DST_SEL(0))); 4331 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4332 amdgpu_ring_write(ring, 0); 4333 amdgpu_ring_write(ring, gds_base); 4334 4335 /* GDS Size */ 4336 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4337 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4338 WRITE_DATA_DST_SEL(0))); 4339 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4340 amdgpu_ring_write(ring, 0); 4341 amdgpu_ring_write(ring, gds_size); 4342 4343 /* GWS */ 4344 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4345 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4346 WRITE_DATA_DST_SEL(0))); 4347 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4348 amdgpu_ring_write(ring, 0); 4349 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4350 4351 /* OA */ 4352 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4353 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4354 WRITE_DATA_DST_SEL(0))); 4355 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4356 amdgpu_ring_write(ring, 0); 4357 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4358 } 4359 4360 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4361 { 4362 WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); 4363 return RREG32(mmSQ_IND_DATA); 4364 } 4365 4366 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4367 { 4368 /* type 0 wave data */ 4369 dst[(*no_fields)++] = 0; 4370 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4371 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4372 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4373 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4374 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4375 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4376 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4377 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4378 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4379 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4380 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4381 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4382 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4383 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4384 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4385 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4386 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4387 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4388 } 4389 4390 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4391 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4392 .select_se_sh = &gfx_v7_0_select_se_sh, 4393 .read_wave_data = &gfx_v7_0_read_wave_data, 4394 }; 4395 4396 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4397 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode, 4398 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode 4399 }; 4400 4401 static int gfx_v7_0_early_init(void *handle) 4402 { 4403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4404 4405 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4406 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; 4407 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4408 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4409 gfx_v7_0_set_ring_funcs(adev); 4410 gfx_v7_0_set_irq_funcs(adev); 4411 gfx_v7_0_set_gds_init(adev); 4412 4413 return 0; 4414 } 4415 4416 static int gfx_v7_0_late_init(void *handle) 4417 { 4418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4419 int r; 4420 4421 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4422 if (r) 4423 return r; 4424 4425 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4426 if (r) 4427 return r; 4428 4429 return 0; 4430 } 4431 4432 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4433 { 4434 u32 gb_addr_config; 4435 u32 mc_shared_chmap, mc_arb_ramcfg; 4436 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4437 u32 tmp; 4438 4439 switch (adev->asic_type) { 4440 case CHIP_BONAIRE: 4441 adev->gfx.config.max_shader_engines = 2; 4442 adev->gfx.config.max_tile_pipes = 4; 4443 adev->gfx.config.max_cu_per_sh = 7; 4444 adev->gfx.config.max_sh_per_se = 1; 4445 adev->gfx.config.max_backends_per_se = 2; 4446 adev->gfx.config.max_texture_channel_caches = 4; 4447 adev->gfx.config.max_gprs = 256; 4448 adev->gfx.config.max_gs_threads = 32; 4449 adev->gfx.config.max_hw_contexts = 8; 4450 4451 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4452 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4453 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4454 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4455 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4456 break; 4457 case CHIP_HAWAII: 4458 adev->gfx.config.max_shader_engines = 4; 4459 adev->gfx.config.max_tile_pipes = 16; 4460 adev->gfx.config.max_cu_per_sh = 11; 4461 adev->gfx.config.max_sh_per_se = 1; 4462 adev->gfx.config.max_backends_per_se = 4; 4463 adev->gfx.config.max_texture_channel_caches = 16; 4464 adev->gfx.config.max_gprs = 256; 4465 adev->gfx.config.max_gs_threads = 32; 4466 adev->gfx.config.max_hw_contexts = 8; 4467 4468 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4469 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4470 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4471 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4472 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4473 break; 4474 case CHIP_KAVERI: 4475 adev->gfx.config.max_shader_engines = 1; 4476 adev->gfx.config.max_tile_pipes = 4; 4477 if ((adev->pdev->device == 0x1304) || 4478 (adev->pdev->device == 0x1305) || 4479 (adev->pdev->device == 0x130C) || 4480 (adev->pdev->device == 0x130F) || 4481 (adev->pdev->device == 0x1310) || 4482 (adev->pdev->device == 0x1311) || 4483 (adev->pdev->device == 0x131C)) { 4484 adev->gfx.config.max_cu_per_sh = 8; 4485 adev->gfx.config.max_backends_per_se = 2; 4486 } else if ((adev->pdev->device == 0x1309) || 4487 (adev->pdev->device == 0x130A) || 4488 (adev->pdev->device == 0x130D) || 4489 (adev->pdev->device == 0x1313) || 4490 (adev->pdev->device == 0x131D)) { 4491 adev->gfx.config.max_cu_per_sh = 6; 4492 adev->gfx.config.max_backends_per_se = 2; 4493 } else if ((adev->pdev->device == 0x1306) || 4494 (adev->pdev->device == 0x1307) || 4495 (adev->pdev->device == 0x130B) || 4496 (adev->pdev->device == 0x130E) || 4497 (adev->pdev->device == 0x1315) || 4498 (adev->pdev->device == 0x131B)) { 4499 adev->gfx.config.max_cu_per_sh = 4; 4500 adev->gfx.config.max_backends_per_se = 1; 4501 } else { 4502 adev->gfx.config.max_cu_per_sh = 3; 4503 adev->gfx.config.max_backends_per_se = 1; 4504 } 4505 adev->gfx.config.max_sh_per_se = 1; 4506 adev->gfx.config.max_texture_channel_caches = 4; 4507 adev->gfx.config.max_gprs = 256; 4508 adev->gfx.config.max_gs_threads = 16; 4509 adev->gfx.config.max_hw_contexts = 8; 4510 4511 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4512 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4513 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4514 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4515 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4516 break; 4517 case CHIP_KABINI: 4518 case CHIP_MULLINS: 4519 default: 4520 adev->gfx.config.max_shader_engines = 1; 4521 adev->gfx.config.max_tile_pipes = 2; 4522 adev->gfx.config.max_cu_per_sh = 2; 4523 adev->gfx.config.max_sh_per_se = 1; 4524 adev->gfx.config.max_backends_per_se = 1; 4525 adev->gfx.config.max_texture_channel_caches = 2; 4526 adev->gfx.config.max_gprs = 256; 4527 adev->gfx.config.max_gs_threads = 16; 4528 adev->gfx.config.max_hw_contexts = 8; 4529 4530 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4531 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4532 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4533 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4534 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4535 break; 4536 } 4537 4538 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 4539 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4540 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4541 4542 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4543 adev->gfx.config.mem_max_burst_length_bytes = 256; 4544 if (adev->flags & AMD_IS_APU) { 4545 /* Get memory bank mapping mode. */ 4546 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4547 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4548 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4549 4550 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4551 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4552 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4553 4554 /* Validate settings in case only one DIMM installed. */ 4555 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4556 dimm00_addr_map = 0; 4557 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4558 dimm01_addr_map = 0; 4559 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4560 dimm10_addr_map = 0; 4561 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4562 dimm11_addr_map = 0; 4563 4564 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4565 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4566 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4567 adev->gfx.config.mem_row_size_in_kb = 2; 4568 else 4569 adev->gfx.config.mem_row_size_in_kb = 1; 4570 } else { 4571 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4572 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4573 if (adev->gfx.config.mem_row_size_in_kb > 4) 4574 adev->gfx.config.mem_row_size_in_kb = 4; 4575 } 4576 /* XXX use MC settings? */ 4577 adev->gfx.config.shader_engine_tile_size = 32; 4578 adev->gfx.config.num_gpus = 1; 4579 adev->gfx.config.multi_gpu_tile_size = 64; 4580 4581 /* fix up row size */ 4582 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4583 switch (adev->gfx.config.mem_row_size_in_kb) { 4584 case 1: 4585 default: 4586 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4587 break; 4588 case 2: 4589 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4590 break; 4591 case 4: 4592 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4593 break; 4594 } 4595 adev->gfx.config.gb_addr_config = gb_addr_config; 4596 } 4597 4598 static int gfx_v7_0_sw_init(void *handle) 4599 { 4600 struct amdgpu_ring *ring; 4601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4602 int i, r; 4603 4604 /* EOP Event */ 4605 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 4606 if (r) 4607 return r; 4608 4609 /* Privileged reg */ 4610 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 4611 if (r) 4612 return r; 4613 4614 /* Privileged inst */ 4615 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 4616 if (r) 4617 return r; 4618 4619 gfx_v7_0_scratch_init(adev); 4620 4621 r = gfx_v7_0_init_microcode(adev); 4622 if (r) { 4623 DRM_ERROR("Failed to load gfx firmware!\n"); 4624 return r; 4625 } 4626 4627 r = gfx_v7_0_rlc_init(adev); 4628 if (r) { 4629 DRM_ERROR("Failed to init rlc BOs!\n"); 4630 return r; 4631 } 4632 4633 /* allocate mec buffers */ 4634 r = gfx_v7_0_mec_init(adev); 4635 if (r) { 4636 DRM_ERROR("Failed to init MEC BOs!\n"); 4637 return r; 4638 } 4639 4640 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4641 ring = &adev->gfx.gfx_ring[i]; 4642 ring->ring_obj = NULL; 4643 sprintf(ring->name, "gfx"); 4644 r = amdgpu_ring_init(adev, ring, 1024, 4645 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 4646 if (r) 4647 return r; 4648 } 4649 4650 /* set up the compute queues */ 4651 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4652 unsigned irq_type; 4653 4654 /* max 32 queues per MEC */ 4655 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 4656 DRM_ERROR("Too many (%d) compute rings!\n", i); 4657 break; 4658 } 4659 ring = &adev->gfx.compute_ring[i]; 4660 ring->ring_obj = NULL; 4661 ring->use_doorbell = true; 4662 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; 4663 ring->me = 1; /* first MEC */ 4664 ring->pipe = i / 8; 4665 ring->queue = i % 8; 4666 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4667 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 4668 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4669 r = amdgpu_ring_init(adev, ring, 1024, 4670 &adev->gfx.eop_irq, irq_type); 4671 if (r) 4672 return r; 4673 } 4674 4675 /* reserve GDS, GWS and OA resource for gfx */ 4676 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 4677 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 4678 &adev->gds.gds_gfx_bo, NULL, NULL); 4679 if (r) 4680 return r; 4681 4682 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 4683 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 4684 &adev->gds.gws_gfx_bo, NULL, NULL); 4685 if (r) 4686 return r; 4687 4688 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 4689 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 4690 &adev->gds.oa_gfx_bo, NULL, NULL); 4691 if (r) 4692 return r; 4693 4694 adev->gfx.ce_ram_size = 0x8000; 4695 4696 gfx_v7_0_gpu_early_init(adev); 4697 4698 return r; 4699 } 4700 4701 static int gfx_v7_0_sw_fini(void *handle) 4702 { 4703 int i; 4704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4705 4706 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 4707 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 4708 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 4709 4710 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4711 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4712 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4713 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4714 4715 gfx_v7_0_cp_compute_fini(adev); 4716 gfx_v7_0_rlc_fini(adev); 4717 gfx_v7_0_mec_fini(adev); 4718 gfx_v7_0_free_microcode(adev); 4719 4720 return 0; 4721 } 4722 4723 static int gfx_v7_0_hw_init(void *handle) 4724 { 4725 int r; 4726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4727 4728 gfx_v7_0_gpu_init(adev); 4729 4730 /* init rlc */ 4731 r = gfx_v7_0_rlc_resume(adev); 4732 if (r) 4733 return r; 4734 4735 r = gfx_v7_0_cp_resume(adev); 4736 if (r) 4737 return r; 4738 4739 return r; 4740 } 4741 4742 static int gfx_v7_0_hw_fini(void *handle) 4743 { 4744 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4745 4746 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4747 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4748 gfx_v7_0_cp_enable(adev, false); 4749 gfx_v7_0_rlc_stop(adev); 4750 gfx_v7_0_fini_pg(adev); 4751 4752 return 0; 4753 } 4754 4755 static int gfx_v7_0_suspend(void *handle) 4756 { 4757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4758 4759 return gfx_v7_0_hw_fini(adev); 4760 } 4761 4762 static int gfx_v7_0_resume(void *handle) 4763 { 4764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4765 4766 return gfx_v7_0_hw_init(adev); 4767 } 4768 4769 static bool gfx_v7_0_is_idle(void *handle) 4770 { 4771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4772 4773 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4774 return false; 4775 else 4776 return true; 4777 } 4778 4779 static int gfx_v7_0_wait_for_idle(void *handle) 4780 { 4781 unsigned i; 4782 u32 tmp; 4783 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4784 4785 for (i = 0; i < adev->usec_timeout; i++) { 4786 /* read MC_STATUS */ 4787 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4788 4789 if (!tmp) 4790 return 0; 4791 udelay(1); 4792 } 4793 return -ETIMEDOUT; 4794 } 4795 4796 static int gfx_v7_0_soft_reset(void *handle) 4797 { 4798 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4799 u32 tmp; 4800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4801 4802 /* GRBM_STATUS */ 4803 tmp = RREG32(mmGRBM_STATUS); 4804 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4805 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4806 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4807 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4808 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4809 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4810 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4811 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4812 4813 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4814 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4815 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4816 } 4817 4818 /* GRBM_STATUS2 */ 4819 tmp = RREG32(mmGRBM_STATUS2); 4820 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4821 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4822 4823 /* SRBM_STATUS */ 4824 tmp = RREG32(mmSRBM_STATUS); 4825 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4826 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4827 4828 if (grbm_soft_reset || srbm_soft_reset) { 4829 /* disable CG/PG */ 4830 gfx_v7_0_fini_pg(adev); 4831 gfx_v7_0_update_cg(adev, false); 4832 4833 /* stop the rlc */ 4834 gfx_v7_0_rlc_stop(adev); 4835 4836 /* Disable GFX parsing/prefetching */ 4837 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4838 4839 /* Disable MEC parsing/prefetching */ 4840 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4841 4842 if (grbm_soft_reset) { 4843 tmp = RREG32(mmGRBM_SOFT_RESET); 4844 tmp |= grbm_soft_reset; 4845 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4846 WREG32(mmGRBM_SOFT_RESET, tmp); 4847 tmp = RREG32(mmGRBM_SOFT_RESET); 4848 4849 udelay(50); 4850 4851 tmp &= ~grbm_soft_reset; 4852 WREG32(mmGRBM_SOFT_RESET, tmp); 4853 tmp = RREG32(mmGRBM_SOFT_RESET); 4854 } 4855 4856 if (srbm_soft_reset) { 4857 tmp = RREG32(mmSRBM_SOFT_RESET); 4858 tmp |= srbm_soft_reset; 4859 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4860 WREG32(mmSRBM_SOFT_RESET, tmp); 4861 tmp = RREG32(mmSRBM_SOFT_RESET); 4862 4863 udelay(50); 4864 4865 tmp &= ~srbm_soft_reset; 4866 WREG32(mmSRBM_SOFT_RESET, tmp); 4867 tmp = RREG32(mmSRBM_SOFT_RESET); 4868 } 4869 /* Wait a little for things to settle down */ 4870 udelay(50); 4871 } 4872 return 0; 4873 } 4874 4875 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4876 enum amdgpu_interrupt_state state) 4877 { 4878 u32 cp_int_cntl; 4879 4880 switch (state) { 4881 case AMDGPU_IRQ_STATE_DISABLE: 4882 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4883 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4884 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4885 break; 4886 case AMDGPU_IRQ_STATE_ENABLE: 4887 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4888 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4889 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4890 break; 4891 default: 4892 break; 4893 } 4894 } 4895 4896 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4897 int me, int pipe, 4898 enum amdgpu_interrupt_state state) 4899 { 4900 u32 mec_int_cntl, mec_int_cntl_reg; 4901 4902 /* 4903 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4904 * handles the setting of interrupts for this specific pipe. All other 4905 * pipes' interrupts are set by amdkfd. 4906 */ 4907 4908 if (me == 1) { 4909 switch (pipe) { 4910 case 0: 4911 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4912 break; 4913 default: 4914 DRM_DEBUG("invalid pipe %d\n", pipe); 4915 return; 4916 } 4917 } else { 4918 DRM_DEBUG("invalid me %d\n", me); 4919 return; 4920 } 4921 4922 switch (state) { 4923 case AMDGPU_IRQ_STATE_DISABLE: 4924 mec_int_cntl = RREG32(mec_int_cntl_reg); 4925 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4926 WREG32(mec_int_cntl_reg, mec_int_cntl); 4927 break; 4928 case AMDGPU_IRQ_STATE_ENABLE: 4929 mec_int_cntl = RREG32(mec_int_cntl_reg); 4930 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4931 WREG32(mec_int_cntl_reg, mec_int_cntl); 4932 break; 4933 default: 4934 break; 4935 } 4936 } 4937 4938 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4939 struct amdgpu_irq_src *src, 4940 unsigned type, 4941 enum amdgpu_interrupt_state state) 4942 { 4943 u32 cp_int_cntl; 4944 4945 switch (state) { 4946 case AMDGPU_IRQ_STATE_DISABLE: 4947 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4948 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4949 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4950 break; 4951 case AMDGPU_IRQ_STATE_ENABLE: 4952 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4953 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4954 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4955 break; 4956 default: 4957 break; 4958 } 4959 4960 return 0; 4961 } 4962 4963 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4964 struct amdgpu_irq_src *src, 4965 unsigned type, 4966 enum amdgpu_interrupt_state state) 4967 { 4968 u32 cp_int_cntl; 4969 4970 switch (state) { 4971 case AMDGPU_IRQ_STATE_DISABLE: 4972 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4973 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4974 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4975 break; 4976 case AMDGPU_IRQ_STATE_ENABLE: 4977 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4978 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4979 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4980 break; 4981 default: 4982 break; 4983 } 4984 4985 return 0; 4986 } 4987 4988 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4989 struct amdgpu_irq_src *src, 4990 unsigned type, 4991 enum amdgpu_interrupt_state state) 4992 { 4993 switch (type) { 4994 case AMDGPU_CP_IRQ_GFX_EOP: 4995 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4996 break; 4997 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4998 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4999 break; 5000 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5001 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5002 break; 5003 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5004 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5005 break; 5006 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5007 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5008 break; 5009 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5010 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5011 break; 5012 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5013 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5014 break; 5015 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5016 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5017 break; 5018 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5019 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5020 break; 5021 default: 5022 break; 5023 } 5024 return 0; 5025 } 5026 5027 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 5028 struct amdgpu_irq_src *source, 5029 struct amdgpu_iv_entry *entry) 5030 { 5031 u8 me_id, pipe_id; 5032 struct amdgpu_ring *ring; 5033 int i; 5034 5035 DRM_DEBUG("IH: CP EOP\n"); 5036 me_id = (entry->ring_id & 0x0c) >> 2; 5037 pipe_id = (entry->ring_id & 0x03) >> 0; 5038 switch (me_id) { 5039 case 0: 5040 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5041 break; 5042 case 1: 5043 case 2: 5044 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5045 ring = &adev->gfx.compute_ring[i]; 5046 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 5047 amdgpu_fence_process(ring); 5048 } 5049 break; 5050 } 5051 return 0; 5052 } 5053 5054 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 5055 struct amdgpu_irq_src *source, 5056 struct amdgpu_iv_entry *entry) 5057 { 5058 DRM_ERROR("Illegal register access in command stream\n"); 5059 schedule_work(&adev->reset_work); 5060 return 0; 5061 } 5062 5063 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 5064 struct amdgpu_irq_src *source, 5065 struct amdgpu_iv_entry *entry) 5066 { 5067 DRM_ERROR("Illegal instruction in command stream\n"); 5068 // XXX soft reset the gfx block only 5069 schedule_work(&adev->reset_work); 5070 return 0; 5071 } 5072 5073 static int gfx_v7_0_set_clockgating_state(void *handle, 5074 enum amd_clockgating_state state) 5075 { 5076 bool gate = false; 5077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5078 5079 if (state == AMD_CG_STATE_GATE) 5080 gate = true; 5081 5082 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 5083 /* order matters! */ 5084 if (gate) { 5085 gfx_v7_0_enable_mgcg(adev, true); 5086 gfx_v7_0_enable_cgcg(adev, true); 5087 } else { 5088 gfx_v7_0_enable_cgcg(adev, false); 5089 gfx_v7_0_enable_mgcg(adev, false); 5090 } 5091 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 5092 5093 return 0; 5094 } 5095 5096 static int gfx_v7_0_set_powergating_state(void *handle, 5097 enum amd_powergating_state state) 5098 { 5099 bool gate = false; 5100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5101 5102 if (state == AMD_PG_STATE_GATE) 5103 gate = true; 5104 5105 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 5106 AMD_PG_SUPPORT_GFX_SMG | 5107 AMD_PG_SUPPORT_GFX_DMG | 5108 AMD_PG_SUPPORT_CP | 5109 AMD_PG_SUPPORT_GDS | 5110 AMD_PG_SUPPORT_RLC_SMU_HS)) { 5111 gfx_v7_0_update_gfx_pg(adev, gate); 5112 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 5113 gfx_v7_0_enable_cp_pg(adev, gate); 5114 gfx_v7_0_enable_gds_pg(adev, gate); 5115 } 5116 } 5117 5118 return 0; 5119 } 5120 5121 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5122 .name = "gfx_v7_0", 5123 .early_init = gfx_v7_0_early_init, 5124 .late_init = gfx_v7_0_late_init, 5125 .sw_init = gfx_v7_0_sw_init, 5126 .sw_fini = gfx_v7_0_sw_fini, 5127 .hw_init = gfx_v7_0_hw_init, 5128 .hw_fini = gfx_v7_0_hw_fini, 5129 .suspend = gfx_v7_0_suspend, 5130 .resume = gfx_v7_0_resume, 5131 .is_idle = gfx_v7_0_is_idle, 5132 .wait_for_idle = gfx_v7_0_wait_for_idle, 5133 .soft_reset = gfx_v7_0_soft_reset, 5134 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5135 .set_powergating_state = gfx_v7_0_set_powergating_state, 5136 }; 5137 5138 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5139 .type = AMDGPU_RING_TYPE_GFX, 5140 .align_mask = 0xff, 5141 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5142 .get_rptr = gfx_v7_0_ring_get_rptr, 5143 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5144 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5145 .emit_frame_size = 5146 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5147 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5148 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5149 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5150 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5151 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5152 3, /* gfx_v7_ring_emit_cntxcntl */ 5153 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5154 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5155 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5156 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5157 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5158 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5159 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5160 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5161 .test_ring = gfx_v7_0_ring_test_ring, 5162 .test_ib = gfx_v7_0_ring_test_ib, 5163 .insert_nop = amdgpu_ring_insert_nop, 5164 .pad_ib = amdgpu_ring_generic_pad_ib, 5165 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5166 }; 5167 5168 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5169 .type = AMDGPU_RING_TYPE_COMPUTE, 5170 .align_mask = 0xff, 5171 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5172 .get_rptr = gfx_v7_0_ring_get_rptr, 5173 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5174 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5175 .emit_frame_size = 5176 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5177 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5178 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5179 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5180 17 + /* gfx_v7_0_ring_emit_vm_flush */ 5181 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5182 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */ 5183 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5184 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5185 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5186 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5187 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5188 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5189 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5190 .test_ring = gfx_v7_0_ring_test_ring, 5191 .test_ib = gfx_v7_0_ring_test_ib, 5192 .insert_nop = amdgpu_ring_insert_nop, 5193 .pad_ib = amdgpu_ring_generic_pad_ib, 5194 }; 5195 5196 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5197 { 5198 int i; 5199 5200 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5201 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5202 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5203 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5204 } 5205 5206 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5207 .set = gfx_v7_0_set_eop_interrupt_state, 5208 .process = gfx_v7_0_eop_irq, 5209 }; 5210 5211 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5212 .set = gfx_v7_0_set_priv_reg_fault_state, 5213 .process = gfx_v7_0_priv_reg_irq, 5214 }; 5215 5216 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5217 .set = gfx_v7_0_set_priv_inst_fault_state, 5218 .process = gfx_v7_0_priv_inst_irq, 5219 }; 5220 5221 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5222 { 5223 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5224 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5225 5226 adev->gfx.priv_reg_irq.num_types = 1; 5227 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5228 5229 adev->gfx.priv_inst_irq.num_types = 1; 5230 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5231 } 5232 5233 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5234 { 5235 /* init asci gds info */ 5236 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 5237 adev->gds.gws.total_size = 64; 5238 adev->gds.oa.total_size = 16; 5239 5240 if (adev->gds.mem.total_size == 64 * 1024) { 5241 adev->gds.mem.gfx_partition_size = 4096; 5242 adev->gds.mem.cs_partition_size = 4096; 5243 5244 adev->gds.gws.gfx_partition_size = 4; 5245 adev->gds.gws.cs_partition_size = 4; 5246 5247 adev->gds.oa.gfx_partition_size = 4; 5248 adev->gds.oa.cs_partition_size = 1; 5249 } else { 5250 adev->gds.mem.gfx_partition_size = 1024; 5251 adev->gds.mem.cs_partition_size = 1024; 5252 5253 adev->gds.gws.gfx_partition_size = 16; 5254 adev->gds.gws.cs_partition_size = 16; 5255 5256 adev->gds.oa.gfx_partition_size = 4; 5257 adev->gds.oa.cs_partition_size = 4; 5258 } 5259 } 5260 5261 5262 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5263 { 5264 int i, j, k, counter, active_cu_number = 0; 5265 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5266 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5267 unsigned disable_masks[4 * 2]; 5268 5269 memset(cu_info, 0, sizeof(*cu_info)); 5270 5271 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5272 5273 mutex_lock(&adev->grbm_idx_mutex); 5274 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5275 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5276 mask = 1; 5277 ao_bitmap = 0; 5278 counter = 0; 5279 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5280 if (i < 4 && j < 2) 5281 gfx_v7_0_set_user_cu_inactive_bitmap( 5282 adev, disable_masks[i * 2 + j]); 5283 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5284 cu_info->bitmap[i][j] = bitmap; 5285 5286 for (k = 0; k < 16; k ++) { 5287 if (bitmap & mask) { 5288 if (counter < 2) 5289 ao_bitmap |= mask; 5290 counter ++; 5291 } 5292 mask <<= 1; 5293 } 5294 active_cu_number += counter; 5295 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5296 } 5297 } 5298 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5299 mutex_unlock(&adev->grbm_idx_mutex); 5300 5301 cu_info->number = active_cu_number; 5302 cu_info->ao_cu_mask = ao_cu_mask; 5303 } 5304 5305 const struct amdgpu_ip_block_version gfx_v7_0_ip_block = 5306 { 5307 .type = AMD_IP_BLOCK_TYPE_GFX, 5308 .major = 7, 5309 .minor = 0, 5310 .rev = 0, 5311 .funcs = &gfx_v7_0_ip_funcs, 5312 }; 5313 5314 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5315 { 5316 .type = AMD_IP_BLOCK_TYPE_GFX, 5317 .major = 7, 5318 .minor = 1, 5319 .rev = 0, 5320 .funcs = &gfx_v7_0_ip_funcs, 5321 }; 5322 5323 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5324 { 5325 .type = AMD_IP_BLOCK_TYPE_GFX, 5326 .major = 7, 5327 .minor = 2, 5328 .rev = 0, 5329 .funcs = &gfx_v7_0_ip_funcs, 5330 }; 5331 5332 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5333 { 5334 .type = AMD_IP_BLOCK_TYPE_GFX, 5335 .major = 7, 5336 .minor = 3, 5337 .rev = 0, 5338 .funcs = &gfx_v7_0_ip_funcs, 5339 }; 5340