1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_ih.h" 29 #include "amdgpu_gfx.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "cik_structs.h" 33 #include "atom.h" 34 #include "amdgpu_ucode.h" 35 #include "clearstate_ci.h" 36 37 #include "dce/dce_8_0_d.h" 38 #include "dce/dce_8_0_sh_mask.h" 39 40 #include "bif/bif_4_1_d.h" 41 #include "bif/bif_4_1_sh_mask.h" 42 43 #include "gca/gfx_7_0_d.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "gca/gfx_7_2_sh_mask.h" 46 47 #include "gmc/gmc_7_0_d.h" 48 #include "gmc/gmc_7_0_sh_mask.h" 49 50 #include "oss/oss_2_0_d.h" 51 #include "oss/oss_2_0_sh_mask.h" 52 53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ 54 55 #define GFX7_NUM_GFX_RINGS 1 56 #define GFX7_MEC_HPD_SIZE 2048 57 58 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 59 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 60 61 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 62 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 63 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 64 65 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin"); 66 MODULE_FIRMWARE("amdgpu/bonaire_me.bin"); 67 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin"); 68 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin"); 69 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin"); 70 71 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin"); 72 MODULE_FIRMWARE("amdgpu/hawaii_me.bin"); 73 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin"); 74 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin"); 75 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin"); 76 77 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/kaveri_me.bin"); 79 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin"); 80 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin"); 81 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin"); 83 84 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/kabini_me.bin"); 86 MODULE_FIRMWARE("amdgpu/kabini_ce.bin"); 87 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/kabini_mec.bin"); 89 90 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/mullins_me.bin"); 92 MODULE_FIRMWARE("amdgpu/mullins_ce.bin"); 93 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin"); 94 MODULE_FIRMWARE("amdgpu/mullins_mec.bin"); 95 96 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { 97 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 98 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 99 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 100 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 101 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 102 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 103 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 104 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 105 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 106 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 107 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 108 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 109 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 110 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 111 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 112 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 113 }; 114 115 static const u32 spectre_rlc_save_restore_register_list[] = { 116 (0x0e00 << 16) | (0xc12c >> 2), 117 0x00000000, 118 (0x0e00 << 16) | (0xc140 >> 2), 119 0x00000000, 120 (0x0e00 << 16) | (0xc150 >> 2), 121 0x00000000, 122 (0x0e00 << 16) | (0xc15c >> 2), 123 0x00000000, 124 (0x0e00 << 16) | (0xc168 >> 2), 125 0x00000000, 126 (0x0e00 << 16) | (0xc170 >> 2), 127 0x00000000, 128 (0x0e00 << 16) | (0xc178 >> 2), 129 0x00000000, 130 (0x0e00 << 16) | (0xc204 >> 2), 131 0x00000000, 132 (0x0e00 << 16) | (0xc2b4 >> 2), 133 0x00000000, 134 (0x0e00 << 16) | (0xc2b8 >> 2), 135 0x00000000, 136 (0x0e00 << 16) | (0xc2bc >> 2), 137 0x00000000, 138 (0x0e00 << 16) | (0xc2c0 >> 2), 139 0x00000000, 140 (0x0e00 << 16) | (0x8228 >> 2), 141 0x00000000, 142 (0x0e00 << 16) | (0x829c >> 2), 143 0x00000000, 144 (0x0e00 << 16) | (0x869c >> 2), 145 0x00000000, 146 (0x0600 << 16) | (0x98f4 >> 2), 147 0x00000000, 148 (0x0e00 << 16) | (0x98f8 >> 2), 149 0x00000000, 150 (0x0e00 << 16) | (0x9900 >> 2), 151 0x00000000, 152 (0x0e00 << 16) | (0xc260 >> 2), 153 0x00000000, 154 (0x0e00 << 16) | (0x90e8 >> 2), 155 0x00000000, 156 (0x0e00 << 16) | (0x3c000 >> 2), 157 0x00000000, 158 (0x0e00 << 16) | (0x3c00c >> 2), 159 0x00000000, 160 (0x0e00 << 16) | (0x8c1c >> 2), 161 0x00000000, 162 (0x0e00 << 16) | (0x9700 >> 2), 163 0x00000000, 164 (0x0e00 << 16) | (0xcd20 >> 2), 165 0x00000000, 166 (0x4e00 << 16) | (0xcd20 >> 2), 167 0x00000000, 168 (0x5e00 << 16) | (0xcd20 >> 2), 169 0x00000000, 170 (0x6e00 << 16) | (0xcd20 >> 2), 171 0x00000000, 172 (0x7e00 << 16) | (0xcd20 >> 2), 173 0x00000000, 174 (0x8e00 << 16) | (0xcd20 >> 2), 175 0x00000000, 176 (0x9e00 << 16) | (0xcd20 >> 2), 177 0x00000000, 178 (0xae00 << 16) | (0xcd20 >> 2), 179 0x00000000, 180 (0xbe00 << 16) | (0xcd20 >> 2), 181 0x00000000, 182 (0x0e00 << 16) | (0x89bc >> 2), 183 0x00000000, 184 (0x0e00 << 16) | (0x8900 >> 2), 185 0x00000000, 186 0x3, 187 (0x0e00 << 16) | (0xc130 >> 2), 188 0x00000000, 189 (0x0e00 << 16) | (0xc134 >> 2), 190 0x00000000, 191 (0x0e00 << 16) | (0xc1fc >> 2), 192 0x00000000, 193 (0x0e00 << 16) | (0xc208 >> 2), 194 0x00000000, 195 (0x0e00 << 16) | (0xc264 >> 2), 196 0x00000000, 197 (0x0e00 << 16) | (0xc268 >> 2), 198 0x00000000, 199 (0x0e00 << 16) | (0xc26c >> 2), 200 0x00000000, 201 (0x0e00 << 16) | (0xc270 >> 2), 202 0x00000000, 203 (0x0e00 << 16) | (0xc274 >> 2), 204 0x00000000, 205 (0x0e00 << 16) | (0xc278 >> 2), 206 0x00000000, 207 (0x0e00 << 16) | (0xc27c >> 2), 208 0x00000000, 209 (0x0e00 << 16) | (0xc280 >> 2), 210 0x00000000, 211 (0x0e00 << 16) | (0xc284 >> 2), 212 0x00000000, 213 (0x0e00 << 16) | (0xc288 >> 2), 214 0x00000000, 215 (0x0e00 << 16) | (0xc28c >> 2), 216 0x00000000, 217 (0x0e00 << 16) | (0xc290 >> 2), 218 0x00000000, 219 (0x0e00 << 16) | (0xc294 >> 2), 220 0x00000000, 221 (0x0e00 << 16) | (0xc298 >> 2), 222 0x00000000, 223 (0x0e00 << 16) | (0xc29c >> 2), 224 0x00000000, 225 (0x0e00 << 16) | (0xc2a0 >> 2), 226 0x00000000, 227 (0x0e00 << 16) | (0xc2a4 >> 2), 228 0x00000000, 229 (0x0e00 << 16) | (0xc2a8 >> 2), 230 0x00000000, 231 (0x0e00 << 16) | (0xc2ac >> 2), 232 0x00000000, 233 (0x0e00 << 16) | (0xc2b0 >> 2), 234 0x00000000, 235 (0x0e00 << 16) | (0x301d0 >> 2), 236 0x00000000, 237 (0x0e00 << 16) | (0x30238 >> 2), 238 0x00000000, 239 (0x0e00 << 16) | (0x30250 >> 2), 240 0x00000000, 241 (0x0e00 << 16) | (0x30254 >> 2), 242 0x00000000, 243 (0x0e00 << 16) | (0x30258 >> 2), 244 0x00000000, 245 (0x0e00 << 16) | (0x3025c >> 2), 246 0x00000000, 247 (0x4e00 << 16) | (0xc900 >> 2), 248 0x00000000, 249 (0x5e00 << 16) | (0xc900 >> 2), 250 0x00000000, 251 (0x6e00 << 16) | (0xc900 >> 2), 252 0x00000000, 253 (0x7e00 << 16) | (0xc900 >> 2), 254 0x00000000, 255 (0x8e00 << 16) | (0xc900 >> 2), 256 0x00000000, 257 (0x9e00 << 16) | (0xc900 >> 2), 258 0x00000000, 259 (0xae00 << 16) | (0xc900 >> 2), 260 0x00000000, 261 (0xbe00 << 16) | (0xc900 >> 2), 262 0x00000000, 263 (0x4e00 << 16) | (0xc904 >> 2), 264 0x00000000, 265 (0x5e00 << 16) | (0xc904 >> 2), 266 0x00000000, 267 (0x6e00 << 16) | (0xc904 >> 2), 268 0x00000000, 269 (0x7e00 << 16) | (0xc904 >> 2), 270 0x00000000, 271 (0x8e00 << 16) | (0xc904 >> 2), 272 0x00000000, 273 (0x9e00 << 16) | (0xc904 >> 2), 274 0x00000000, 275 (0xae00 << 16) | (0xc904 >> 2), 276 0x00000000, 277 (0xbe00 << 16) | (0xc904 >> 2), 278 0x00000000, 279 (0x4e00 << 16) | (0xc908 >> 2), 280 0x00000000, 281 (0x5e00 << 16) | (0xc908 >> 2), 282 0x00000000, 283 (0x6e00 << 16) | (0xc908 >> 2), 284 0x00000000, 285 (0x7e00 << 16) | (0xc908 >> 2), 286 0x00000000, 287 (0x8e00 << 16) | (0xc908 >> 2), 288 0x00000000, 289 (0x9e00 << 16) | (0xc908 >> 2), 290 0x00000000, 291 (0xae00 << 16) | (0xc908 >> 2), 292 0x00000000, 293 (0xbe00 << 16) | (0xc908 >> 2), 294 0x00000000, 295 (0x4e00 << 16) | (0xc90c >> 2), 296 0x00000000, 297 (0x5e00 << 16) | (0xc90c >> 2), 298 0x00000000, 299 (0x6e00 << 16) | (0xc90c >> 2), 300 0x00000000, 301 (0x7e00 << 16) | (0xc90c >> 2), 302 0x00000000, 303 (0x8e00 << 16) | (0xc90c >> 2), 304 0x00000000, 305 (0x9e00 << 16) | (0xc90c >> 2), 306 0x00000000, 307 (0xae00 << 16) | (0xc90c >> 2), 308 0x00000000, 309 (0xbe00 << 16) | (0xc90c >> 2), 310 0x00000000, 311 (0x4e00 << 16) | (0xc910 >> 2), 312 0x00000000, 313 (0x5e00 << 16) | (0xc910 >> 2), 314 0x00000000, 315 (0x6e00 << 16) | (0xc910 >> 2), 316 0x00000000, 317 (0x7e00 << 16) | (0xc910 >> 2), 318 0x00000000, 319 (0x8e00 << 16) | (0xc910 >> 2), 320 0x00000000, 321 (0x9e00 << 16) | (0xc910 >> 2), 322 0x00000000, 323 (0xae00 << 16) | (0xc910 >> 2), 324 0x00000000, 325 (0xbe00 << 16) | (0xc910 >> 2), 326 0x00000000, 327 (0x0e00 << 16) | (0xc99c >> 2), 328 0x00000000, 329 (0x0e00 << 16) | (0x9834 >> 2), 330 0x00000000, 331 (0x0000 << 16) | (0x30f00 >> 2), 332 0x00000000, 333 (0x0001 << 16) | (0x30f00 >> 2), 334 0x00000000, 335 (0x0000 << 16) | (0x30f04 >> 2), 336 0x00000000, 337 (0x0001 << 16) | (0x30f04 >> 2), 338 0x00000000, 339 (0x0000 << 16) | (0x30f08 >> 2), 340 0x00000000, 341 (0x0001 << 16) | (0x30f08 >> 2), 342 0x00000000, 343 (0x0000 << 16) | (0x30f0c >> 2), 344 0x00000000, 345 (0x0001 << 16) | (0x30f0c >> 2), 346 0x00000000, 347 (0x0600 << 16) | (0x9b7c >> 2), 348 0x00000000, 349 (0x0e00 << 16) | (0x8a14 >> 2), 350 0x00000000, 351 (0x0e00 << 16) | (0x8a18 >> 2), 352 0x00000000, 353 (0x0600 << 16) | (0x30a00 >> 2), 354 0x00000000, 355 (0x0e00 << 16) | (0x8bf0 >> 2), 356 0x00000000, 357 (0x0e00 << 16) | (0x8bcc >> 2), 358 0x00000000, 359 (0x0e00 << 16) | (0x8b24 >> 2), 360 0x00000000, 361 (0x0e00 << 16) | (0x30a04 >> 2), 362 0x00000000, 363 (0x0600 << 16) | (0x30a10 >> 2), 364 0x00000000, 365 (0x0600 << 16) | (0x30a14 >> 2), 366 0x00000000, 367 (0x0600 << 16) | (0x30a18 >> 2), 368 0x00000000, 369 (0x0600 << 16) | (0x30a2c >> 2), 370 0x00000000, 371 (0x0e00 << 16) | (0xc700 >> 2), 372 0x00000000, 373 (0x0e00 << 16) | (0xc704 >> 2), 374 0x00000000, 375 (0x0e00 << 16) | (0xc708 >> 2), 376 0x00000000, 377 (0x0e00 << 16) | (0xc768 >> 2), 378 0x00000000, 379 (0x0400 << 16) | (0xc770 >> 2), 380 0x00000000, 381 (0x0400 << 16) | (0xc774 >> 2), 382 0x00000000, 383 (0x0400 << 16) | (0xc778 >> 2), 384 0x00000000, 385 (0x0400 << 16) | (0xc77c >> 2), 386 0x00000000, 387 (0x0400 << 16) | (0xc780 >> 2), 388 0x00000000, 389 (0x0400 << 16) | (0xc784 >> 2), 390 0x00000000, 391 (0x0400 << 16) | (0xc788 >> 2), 392 0x00000000, 393 (0x0400 << 16) | (0xc78c >> 2), 394 0x00000000, 395 (0x0400 << 16) | (0xc798 >> 2), 396 0x00000000, 397 (0x0400 << 16) | (0xc79c >> 2), 398 0x00000000, 399 (0x0400 << 16) | (0xc7a0 >> 2), 400 0x00000000, 401 (0x0400 << 16) | (0xc7a4 >> 2), 402 0x00000000, 403 (0x0400 << 16) | (0xc7a8 >> 2), 404 0x00000000, 405 (0x0400 << 16) | (0xc7ac >> 2), 406 0x00000000, 407 (0x0400 << 16) | (0xc7b0 >> 2), 408 0x00000000, 409 (0x0400 << 16) | (0xc7b4 >> 2), 410 0x00000000, 411 (0x0e00 << 16) | (0x9100 >> 2), 412 0x00000000, 413 (0x0e00 << 16) | (0x3c010 >> 2), 414 0x00000000, 415 (0x0e00 << 16) | (0x92a8 >> 2), 416 0x00000000, 417 (0x0e00 << 16) | (0x92ac >> 2), 418 0x00000000, 419 (0x0e00 << 16) | (0x92b4 >> 2), 420 0x00000000, 421 (0x0e00 << 16) | (0x92b8 >> 2), 422 0x00000000, 423 (0x0e00 << 16) | (0x92bc >> 2), 424 0x00000000, 425 (0x0e00 << 16) | (0x92c0 >> 2), 426 0x00000000, 427 (0x0e00 << 16) | (0x92c4 >> 2), 428 0x00000000, 429 (0x0e00 << 16) | (0x92c8 >> 2), 430 0x00000000, 431 (0x0e00 << 16) | (0x92cc >> 2), 432 0x00000000, 433 (0x0e00 << 16) | (0x92d0 >> 2), 434 0x00000000, 435 (0x0e00 << 16) | (0x8c00 >> 2), 436 0x00000000, 437 (0x0e00 << 16) | (0x8c04 >> 2), 438 0x00000000, 439 (0x0e00 << 16) | (0x8c20 >> 2), 440 0x00000000, 441 (0x0e00 << 16) | (0x8c38 >> 2), 442 0x00000000, 443 (0x0e00 << 16) | (0x8c3c >> 2), 444 0x00000000, 445 (0x0e00 << 16) | (0xae00 >> 2), 446 0x00000000, 447 (0x0e00 << 16) | (0x9604 >> 2), 448 0x00000000, 449 (0x0e00 << 16) | (0xac08 >> 2), 450 0x00000000, 451 (0x0e00 << 16) | (0xac0c >> 2), 452 0x00000000, 453 (0x0e00 << 16) | (0xac10 >> 2), 454 0x00000000, 455 (0x0e00 << 16) | (0xac14 >> 2), 456 0x00000000, 457 (0x0e00 << 16) | (0xac58 >> 2), 458 0x00000000, 459 (0x0e00 << 16) | (0xac68 >> 2), 460 0x00000000, 461 (0x0e00 << 16) | (0xac6c >> 2), 462 0x00000000, 463 (0x0e00 << 16) | (0xac70 >> 2), 464 0x00000000, 465 (0x0e00 << 16) | (0xac74 >> 2), 466 0x00000000, 467 (0x0e00 << 16) | (0xac78 >> 2), 468 0x00000000, 469 (0x0e00 << 16) | (0xac7c >> 2), 470 0x00000000, 471 (0x0e00 << 16) | (0xac80 >> 2), 472 0x00000000, 473 (0x0e00 << 16) | (0xac84 >> 2), 474 0x00000000, 475 (0x0e00 << 16) | (0xac88 >> 2), 476 0x00000000, 477 (0x0e00 << 16) | (0xac8c >> 2), 478 0x00000000, 479 (0x0e00 << 16) | (0x970c >> 2), 480 0x00000000, 481 (0x0e00 << 16) | (0x9714 >> 2), 482 0x00000000, 483 (0x0e00 << 16) | (0x9718 >> 2), 484 0x00000000, 485 (0x0e00 << 16) | (0x971c >> 2), 486 0x00000000, 487 (0x0e00 << 16) | (0x31068 >> 2), 488 0x00000000, 489 (0x4e00 << 16) | (0x31068 >> 2), 490 0x00000000, 491 (0x5e00 << 16) | (0x31068 >> 2), 492 0x00000000, 493 (0x6e00 << 16) | (0x31068 >> 2), 494 0x00000000, 495 (0x7e00 << 16) | (0x31068 >> 2), 496 0x00000000, 497 (0x8e00 << 16) | (0x31068 >> 2), 498 0x00000000, 499 (0x9e00 << 16) | (0x31068 >> 2), 500 0x00000000, 501 (0xae00 << 16) | (0x31068 >> 2), 502 0x00000000, 503 (0xbe00 << 16) | (0x31068 >> 2), 504 0x00000000, 505 (0x0e00 << 16) | (0xcd10 >> 2), 506 0x00000000, 507 (0x0e00 << 16) | (0xcd14 >> 2), 508 0x00000000, 509 (0x0e00 << 16) | (0x88b0 >> 2), 510 0x00000000, 511 (0x0e00 << 16) | (0x88b4 >> 2), 512 0x00000000, 513 (0x0e00 << 16) | (0x88b8 >> 2), 514 0x00000000, 515 (0x0e00 << 16) | (0x88bc >> 2), 516 0x00000000, 517 (0x0400 << 16) | (0x89c0 >> 2), 518 0x00000000, 519 (0x0e00 << 16) | (0x88c4 >> 2), 520 0x00000000, 521 (0x0e00 << 16) | (0x88c8 >> 2), 522 0x00000000, 523 (0x0e00 << 16) | (0x88d0 >> 2), 524 0x00000000, 525 (0x0e00 << 16) | (0x88d4 >> 2), 526 0x00000000, 527 (0x0e00 << 16) | (0x88d8 >> 2), 528 0x00000000, 529 (0x0e00 << 16) | (0x8980 >> 2), 530 0x00000000, 531 (0x0e00 << 16) | (0x30938 >> 2), 532 0x00000000, 533 (0x0e00 << 16) | (0x3093c >> 2), 534 0x00000000, 535 (0x0e00 << 16) | (0x30940 >> 2), 536 0x00000000, 537 (0x0e00 << 16) | (0x89a0 >> 2), 538 0x00000000, 539 (0x0e00 << 16) | (0x30900 >> 2), 540 0x00000000, 541 (0x0e00 << 16) | (0x30904 >> 2), 542 0x00000000, 543 (0x0e00 << 16) | (0x89b4 >> 2), 544 0x00000000, 545 (0x0e00 << 16) | (0x3c210 >> 2), 546 0x00000000, 547 (0x0e00 << 16) | (0x3c214 >> 2), 548 0x00000000, 549 (0x0e00 << 16) | (0x3c218 >> 2), 550 0x00000000, 551 (0x0e00 << 16) | (0x8904 >> 2), 552 0x00000000, 553 0x5, 554 (0x0e00 << 16) | (0x8c28 >> 2), 555 (0x0e00 << 16) | (0x8c2c >> 2), 556 (0x0e00 << 16) | (0x8c30 >> 2), 557 (0x0e00 << 16) | (0x8c34 >> 2), 558 (0x0e00 << 16) | (0x9600 >> 2), 559 }; 560 561 static const u32 kalindi_rlc_save_restore_register_list[] = { 562 (0x0e00 << 16) | (0xc12c >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc140 >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc150 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc15c >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc168 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc170 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc204 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2b4 >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2b8 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0xc2bc >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0xc2c0 >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x8228 >> 2), 585 0x00000000, 586 (0x0e00 << 16) | (0x829c >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x869c >> 2), 589 0x00000000, 590 (0x0600 << 16) | (0x98f4 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0x98f8 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x9900 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0xc260 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x90e8 >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x3c000 >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x3c00c >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0x8c1c >> 2), 605 0x00000000, 606 (0x0e00 << 16) | (0x9700 >> 2), 607 0x00000000, 608 (0x0e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x4e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x5e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x6e00 << 16) | (0xcd20 >> 2), 615 0x00000000, 616 (0x7e00 << 16) | (0xcd20 >> 2), 617 0x00000000, 618 (0x0e00 << 16) | (0x89bc >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0x8900 >> 2), 621 0x00000000, 622 0x3, 623 (0x0e00 << 16) | (0xc130 >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc134 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc1fc >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc208 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc264 >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc268 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc26c >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc270 >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc274 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc28c >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc290 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc294 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc298 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a0 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2a4 >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0xc2a8 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0xc2ac >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x301d0 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30238 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30250 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x30254 >> 2), 664 0x00000000, 665 (0x0e00 << 16) | (0x30258 >> 2), 666 0x00000000, 667 (0x0e00 << 16) | (0x3025c >> 2), 668 0x00000000, 669 (0x4e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x5e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x6e00 << 16) | (0xc900 >> 2), 674 0x00000000, 675 (0x7e00 << 16) | (0xc900 >> 2), 676 0x00000000, 677 (0x4e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x5e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x6e00 << 16) | (0xc904 >> 2), 682 0x00000000, 683 (0x7e00 << 16) | (0xc904 >> 2), 684 0x00000000, 685 (0x4e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x5e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x6e00 << 16) | (0xc908 >> 2), 690 0x00000000, 691 (0x7e00 << 16) | (0xc908 >> 2), 692 0x00000000, 693 (0x4e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x5e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x6e00 << 16) | (0xc90c >> 2), 698 0x00000000, 699 (0x7e00 << 16) | (0xc90c >> 2), 700 0x00000000, 701 (0x4e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x5e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x6e00 << 16) | (0xc910 >> 2), 706 0x00000000, 707 (0x7e00 << 16) | (0xc910 >> 2), 708 0x00000000, 709 (0x0e00 << 16) | (0xc99c >> 2), 710 0x00000000, 711 (0x0e00 << 16) | (0x9834 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f00 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f04 >> 2), 716 0x00000000, 717 (0x0000 << 16) | (0x30f08 >> 2), 718 0x00000000, 719 (0x0000 << 16) | (0x30f0c >> 2), 720 0x00000000, 721 (0x0600 << 16) | (0x9b7c >> 2), 722 0x00000000, 723 (0x0e00 << 16) | (0x8a14 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8a18 >> 2), 726 0x00000000, 727 (0x0600 << 16) | (0x30a00 >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8bf0 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x8bcc >> 2), 732 0x00000000, 733 (0x0e00 << 16) | (0x8b24 >> 2), 734 0x00000000, 735 (0x0e00 << 16) | (0x30a04 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a10 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a14 >> 2), 740 0x00000000, 741 (0x0600 << 16) | (0x30a18 >> 2), 742 0x00000000, 743 (0x0600 << 16) | (0x30a2c >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc700 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc704 >> 2), 748 0x00000000, 749 (0x0e00 << 16) | (0xc708 >> 2), 750 0x00000000, 751 (0x0e00 << 16) | (0xc768 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc770 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc774 >> 2), 756 0x00000000, 757 (0x0400 << 16) | (0xc798 >> 2), 758 0x00000000, 759 (0x0400 << 16) | (0xc79c >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x9100 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x3c010 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c00 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c04 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c20 >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0x8c38 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x8c3c >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xae00 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0x9604 >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac08 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac0c >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac10 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac14 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac58 >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac68 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac6c >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac70 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac74 >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac78 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac7c >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac80 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac84 >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0xac88 >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0xac8c >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x970c >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x9714 >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x9718 >> 2), 814 0x00000000, 815 (0x0e00 << 16) | (0x971c >> 2), 816 0x00000000, 817 (0x0e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x4e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x5e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x6e00 << 16) | (0x31068 >> 2), 824 0x00000000, 825 (0x7e00 << 16) | (0x31068 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0xcd10 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0xcd14 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b0 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88b4 >> 2), 834 0x00000000, 835 (0x0e00 << 16) | (0x88b8 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88bc >> 2), 838 0x00000000, 839 (0x0400 << 16) | (0x89c0 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88c4 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88c8 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d0 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x88d4 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x88d8 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x8980 >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30938 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x3093c >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30940 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x89a0 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x30900 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x30904 >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x89b4 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3e1fc >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c210 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x3c214 >> 2), 872 0x00000000, 873 (0x0e00 << 16) | (0x3c218 >> 2), 874 0x00000000, 875 (0x0e00 << 16) | (0x8904 >> 2), 876 0x00000000, 877 0x5, 878 (0x0e00 << 16) | (0x8c28 >> 2), 879 (0x0e00 << 16) | (0x8c2c >> 2), 880 (0x0e00 << 16) | (0x8c30 >> 2), 881 (0x0e00 << 16) | (0x8c34 >> 2), 882 (0x0e00 << 16) | (0x9600 >> 2), 883 }; 884 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 886 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 889 890 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 891 { 892 amdgpu_ucode_release(&adev->gfx.pfp_fw); 893 amdgpu_ucode_release(&adev->gfx.me_fw); 894 amdgpu_ucode_release(&adev->gfx.ce_fw); 895 amdgpu_ucode_release(&adev->gfx.mec_fw); 896 amdgpu_ucode_release(&adev->gfx.mec2_fw); 897 amdgpu_ucode_release(&adev->gfx.rlc_fw); 898 } 899 900 /* 901 * Core functions 902 */ 903 /** 904 * gfx_v7_0_init_microcode - load ucode images from disk 905 * 906 * @adev: amdgpu_device pointer 907 * 908 * Use the firmware interface to load the ucode images into 909 * the driver (not loaded into hw). 910 * Returns 0 on success, error on failure. 911 */ 912 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 913 { 914 const char *chip_name; 915 int err; 916 917 DRM_DEBUG("\n"); 918 919 switch (adev->asic_type) { 920 case CHIP_BONAIRE: 921 chip_name = "bonaire"; 922 break; 923 case CHIP_HAWAII: 924 chip_name = "hawaii"; 925 break; 926 case CHIP_KAVERI: 927 chip_name = "kaveri"; 928 break; 929 case CHIP_KABINI: 930 chip_name = "kabini"; 931 break; 932 case CHIP_MULLINS: 933 chip_name = "mullins"; 934 break; 935 default: 936 dev_warn(adev->dev, "Unsupported asic_type 0x%08x\n", adev->asic_type); 937 return -EINVAL; 938 } 939 940 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 941 AMDGPU_UCODE_REQUIRED, 942 "amdgpu/%s_pfp.bin", chip_name); 943 if (err) 944 goto out; 945 946 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 947 AMDGPU_UCODE_REQUIRED, 948 "amdgpu/%s_me.bin", chip_name); 949 if (err) 950 goto out; 951 952 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 953 AMDGPU_UCODE_REQUIRED, 954 "amdgpu/%s_ce.bin", chip_name); 955 if (err) 956 goto out; 957 958 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 959 AMDGPU_UCODE_REQUIRED, 960 "amdgpu/%s_mec.bin", chip_name); 961 if (err) 962 goto out; 963 964 if (adev->asic_type == CHIP_KAVERI) { 965 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 966 AMDGPU_UCODE_REQUIRED, 967 "amdgpu/%s_mec2.bin", chip_name); 968 if (err) 969 goto out; 970 } 971 972 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 973 AMDGPU_UCODE_REQUIRED, 974 "amdgpu/%s_rlc.bin", chip_name); 975 out: 976 if (err) { 977 pr_err("gfx7: Failed to load firmware %s gfx firmware\n", chip_name); 978 gfx_v7_0_free_microcode(adev); 979 } 980 return err; 981 } 982 983 /** 984 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 985 * 986 * @adev: amdgpu_device pointer 987 * 988 * Starting with SI, the tiling setup is done globally in a 989 * set of 32 tiling modes. Rather than selecting each set of 990 * parameters per surface as on older asics, we just select 991 * which index in the tiling table we want to use, and the 992 * surface uses those parameters (CIK). 993 */ 994 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 995 { 996 const u32 num_tile_mode_states = 997 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 998 const u32 num_secondary_tile_mode_states = 999 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1000 u32 reg_offset, split_equal_to_row_size; 1001 uint32_t *tile, *macrotile; 1002 1003 tile = adev->gfx.config.tile_mode_array; 1004 macrotile = adev->gfx.config.macrotile_mode_array; 1005 1006 switch (adev->gfx.config.mem_row_size_in_kb) { 1007 case 1: 1008 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1009 break; 1010 case 2: 1011 default: 1012 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1013 break; 1014 case 4: 1015 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1016 break; 1017 } 1018 1019 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1020 tile[reg_offset] = 0; 1021 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1022 macrotile[reg_offset] = 0; 1023 1024 switch (adev->asic_type) { 1025 case CHIP_BONAIRE: 1026 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1027 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1029 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1030 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1031 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1032 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1033 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1034 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1035 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1037 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1038 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1039 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1041 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1042 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1043 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1045 TILE_SPLIT(split_equal_to_row_size)); 1046 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1047 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1049 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1051 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1052 TILE_SPLIT(split_equal_to_row_size)); 1053 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1054 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1055 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1056 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1057 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1058 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1059 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1061 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1062 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1063 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1065 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1066 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1067 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1068 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1069 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1070 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1071 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1072 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1073 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1074 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1075 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1077 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1078 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1079 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1083 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1084 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1085 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1086 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1087 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1088 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1089 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1090 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1091 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1092 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1093 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1095 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1099 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1102 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1103 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1104 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1105 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1106 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1108 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1109 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1110 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1111 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1112 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1113 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1114 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1116 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1117 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1118 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1119 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1121 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1123 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1125 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1127 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1128 1129 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1130 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1132 NUM_BANKS(ADDR_SURF_16_BANK)); 1133 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1136 NUM_BANKS(ADDR_SURF_16_BANK)); 1137 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1140 NUM_BANKS(ADDR_SURF_16_BANK)); 1141 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1142 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1144 NUM_BANKS(ADDR_SURF_16_BANK)); 1145 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1148 NUM_BANKS(ADDR_SURF_16_BANK)); 1149 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1152 NUM_BANKS(ADDR_SURF_8_BANK)); 1153 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1156 NUM_BANKS(ADDR_SURF_4_BANK)); 1157 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1160 NUM_BANKS(ADDR_SURF_16_BANK)); 1161 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1164 NUM_BANKS(ADDR_SURF_16_BANK)); 1165 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1168 NUM_BANKS(ADDR_SURF_16_BANK)); 1169 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1172 NUM_BANKS(ADDR_SURF_16_BANK)); 1173 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1176 NUM_BANKS(ADDR_SURF_16_BANK)); 1177 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1180 NUM_BANKS(ADDR_SURF_8_BANK)); 1181 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1184 NUM_BANKS(ADDR_SURF_4_BANK)); 1185 1186 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1187 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1188 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1189 if (reg_offset != 7) 1190 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1191 break; 1192 case CHIP_HAWAII: 1193 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1194 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1195 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1196 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1197 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1198 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1199 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1200 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1201 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1202 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1204 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1205 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1206 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1207 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1208 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1209 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1210 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1212 TILE_SPLIT(split_equal_to_row_size)); 1213 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1214 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1216 TILE_SPLIT(split_equal_to_row_size)); 1217 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1218 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1220 TILE_SPLIT(split_equal_to_row_size)); 1221 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1222 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1224 TILE_SPLIT(split_equal_to_row_size)); 1225 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1226 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1227 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1229 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1230 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1231 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1232 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1233 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1234 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1235 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1237 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1238 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1239 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1241 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1242 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1243 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1244 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1245 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1247 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1249 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1250 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1251 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1253 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1256 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1257 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1258 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1259 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1261 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1263 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1265 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1266 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1267 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1268 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1272 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1276 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1280 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1281 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1284 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1285 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1288 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1292 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1295 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1296 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1297 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1298 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1299 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1301 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1303 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1305 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1307 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1311 1312 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1313 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1314 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1315 NUM_BANKS(ADDR_SURF_16_BANK)); 1316 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1319 NUM_BANKS(ADDR_SURF_16_BANK)); 1320 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1321 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1322 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1323 NUM_BANKS(ADDR_SURF_16_BANK)); 1324 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1325 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1326 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1327 NUM_BANKS(ADDR_SURF_16_BANK)); 1328 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1329 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1330 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1331 NUM_BANKS(ADDR_SURF_8_BANK)); 1332 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1333 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1334 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1335 NUM_BANKS(ADDR_SURF_4_BANK)); 1336 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1337 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1338 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1339 NUM_BANKS(ADDR_SURF_4_BANK)); 1340 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1341 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1342 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1343 NUM_BANKS(ADDR_SURF_16_BANK)); 1344 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1345 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1346 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1347 NUM_BANKS(ADDR_SURF_16_BANK)); 1348 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1349 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1350 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1351 NUM_BANKS(ADDR_SURF_16_BANK)); 1352 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1353 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1354 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1355 NUM_BANKS(ADDR_SURF_8_BANK)); 1356 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1359 NUM_BANKS(ADDR_SURF_16_BANK)); 1360 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1361 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1362 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1363 NUM_BANKS(ADDR_SURF_8_BANK)); 1364 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1365 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1366 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1367 NUM_BANKS(ADDR_SURF_4_BANK)); 1368 1369 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1370 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1371 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1372 if (reg_offset != 7) 1373 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1374 break; 1375 case CHIP_KABINI: 1376 case CHIP_KAVERI: 1377 case CHIP_MULLINS: 1378 default: 1379 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1380 PIPE_CONFIG(ADDR_SURF_P2) | 1381 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1382 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1383 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1384 PIPE_CONFIG(ADDR_SURF_P2) | 1385 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1386 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1387 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1388 PIPE_CONFIG(ADDR_SURF_P2) | 1389 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1390 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1391 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1392 PIPE_CONFIG(ADDR_SURF_P2) | 1393 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1394 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1395 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1396 PIPE_CONFIG(ADDR_SURF_P2) | 1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1398 TILE_SPLIT(split_equal_to_row_size)); 1399 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1400 PIPE_CONFIG(ADDR_SURF_P2) | 1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1402 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1403 PIPE_CONFIG(ADDR_SURF_P2) | 1404 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1405 TILE_SPLIT(split_equal_to_row_size)); 1406 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1407 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1408 PIPE_CONFIG(ADDR_SURF_P2)); 1409 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1410 PIPE_CONFIG(ADDR_SURF_P2) | 1411 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1412 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1413 PIPE_CONFIG(ADDR_SURF_P2) | 1414 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1416 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1417 PIPE_CONFIG(ADDR_SURF_P2) | 1418 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1420 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1421 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1422 PIPE_CONFIG(ADDR_SURF_P2) | 1423 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1424 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1425 PIPE_CONFIG(ADDR_SURF_P2) | 1426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1428 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1429 PIPE_CONFIG(ADDR_SURF_P2) | 1430 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1432 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1433 PIPE_CONFIG(ADDR_SURF_P2) | 1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1436 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1437 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1438 PIPE_CONFIG(ADDR_SURF_P2) | 1439 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1440 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1441 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1442 PIPE_CONFIG(ADDR_SURF_P2) | 1443 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1444 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1445 PIPE_CONFIG(ADDR_SURF_P2) | 1446 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1447 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1448 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1449 PIPE_CONFIG(ADDR_SURF_P2) | 1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1452 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1453 PIPE_CONFIG(ADDR_SURF_P2) | 1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1456 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1457 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1458 PIPE_CONFIG(ADDR_SURF_P2) | 1459 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1461 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1462 PIPE_CONFIG(ADDR_SURF_P2) | 1463 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1465 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1466 PIPE_CONFIG(ADDR_SURF_P2) | 1467 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1469 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1470 PIPE_CONFIG(ADDR_SURF_P2) | 1471 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1472 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1473 PIPE_CONFIG(ADDR_SURF_P2) | 1474 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1476 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1477 PIPE_CONFIG(ADDR_SURF_P2) | 1478 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1480 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1481 1482 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1483 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1484 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1485 NUM_BANKS(ADDR_SURF_8_BANK)); 1486 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1489 NUM_BANKS(ADDR_SURF_8_BANK)); 1490 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1493 NUM_BANKS(ADDR_SURF_8_BANK)); 1494 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1495 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1496 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1497 NUM_BANKS(ADDR_SURF_8_BANK)); 1498 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1501 NUM_BANKS(ADDR_SURF_8_BANK)); 1502 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1505 NUM_BANKS(ADDR_SURF_8_BANK)); 1506 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1509 NUM_BANKS(ADDR_SURF_8_BANK)); 1510 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1513 NUM_BANKS(ADDR_SURF_16_BANK)); 1514 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1517 NUM_BANKS(ADDR_SURF_16_BANK)); 1518 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1521 NUM_BANKS(ADDR_SURF_16_BANK)); 1522 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1525 NUM_BANKS(ADDR_SURF_16_BANK)); 1526 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1529 NUM_BANKS(ADDR_SURF_16_BANK)); 1530 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1533 NUM_BANKS(ADDR_SURF_16_BANK)); 1534 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1537 NUM_BANKS(ADDR_SURF_8_BANK)); 1538 1539 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1540 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1541 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1542 if (reg_offset != 7) 1543 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1544 break; 1545 } 1546 } 1547 1548 /** 1549 * gfx_v7_0_select_se_sh - select which SE, SH to address 1550 * 1551 * @adev: amdgpu_device pointer 1552 * @se_num: shader engine to address 1553 * @sh_num: sh block to address 1554 * @instance: Certain registers are instanced per SE or SH. 1555 * 0xffffffff means broadcast to all SEs or SHs (CIK). 1556 * @xcc_id: xcc accelerated compute core id 1557 * Select which SE, SH combinations to address. 1558 */ 1559 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1560 u32 se_num, u32 sh_num, u32 instance, 1561 int xcc_id) 1562 { 1563 u32 data; 1564 1565 if (instance == 0xffffffff) 1566 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1567 else 1568 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1569 1570 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1571 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1572 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1573 else if (se_num == 0xffffffff) 1574 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1575 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1576 else if (sh_num == 0xffffffff) 1577 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1578 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1579 else 1580 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1581 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1582 WREG32(mmGRBM_GFX_INDEX, data); 1583 } 1584 1585 /** 1586 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1587 * 1588 * @adev: amdgpu_device pointer 1589 * 1590 * Calculates the bitmask of enabled RBs (CIK). 1591 * Returns the enabled RB bitmask. 1592 */ 1593 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1594 { 1595 u32 data, mask; 1596 1597 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1598 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1599 1600 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1601 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1602 1603 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1604 adev->gfx.config.max_sh_per_se); 1605 1606 return (~data) & mask; 1607 } 1608 1609 static void 1610 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1611 { 1612 switch (adev->asic_type) { 1613 case CHIP_BONAIRE: 1614 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1615 SE_XSEL(1) | SE_YSEL(1); 1616 *rconf1 |= 0x0; 1617 break; 1618 case CHIP_HAWAII: 1619 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1620 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1621 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1622 SE_YSEL(3); 1623 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1624 SE_PAIR_YSEL(2); 1625 break; 1626 case CHIP_KAVERI: 1627 *rconf |= RB_MAP_PKR0(2); 1628 *rconf1 |= 0x0; 1629 break; 1630 case CHIP_KABINI: 1631 case CHIP_MULLINS: 1632 *rconf |= 0x0; 1633 *rconf1 |= 0x0; 1634 break; 1635 default: 1636 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1637 break; 1638 } 1639 } 1640 1641 static void 1642 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1643 u32 raster_config, u32 raster_config_1, 1644 unsigned rb_mask, unsigned num_rb) 1645 { 1646 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1647 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1648 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1649 unsigned rb_per_se = num_rb / num_se; 1650 unsigned se_mask[4]; 1651 unsigned se; 1652 1653 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1654 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1655 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1656 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1657 1658 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1659 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1660 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1661 1662 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1663 (!se_mask[2] && !se_mask[3]))) { 1664 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1665 1666 if (!se_mask[0] && !se_mask[1]) { 1667 raster_config_1 |= 1668 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1669 } else { 1670 raster_config_1 |= 1671 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1672 } 1673 } 1674 1675 for (se = 0; se < num_se; se++) { 1676 unsigned raster_config_se = raster_config; 1677 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1678 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1679 int idx = (se / 2) * 2; 1680 1681 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1682 raster_config_se &= ~SE_MAP_MASK; 1683 1684 if (!se_mask[idx]) { 1685 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1686 } else { 1687 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1688 } 1689 } 1690 1691 pkr0_mask &= rb_mask; 1692 pkr1_mask &= rb_mask; 1693 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1694 raster_config_se &= ~PKR_MAP_MASK; 1695 1696 if (!pkr0_mask) { 1697 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1698 } else { 1699 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1700 } 1701 } 1702 1703 if (rb_per_se >= 2) { 1704 unsigned rb0_mask = 1 << (se * rb_per_se); 1705 unsigned rb1_mask = rb0_mask << 1; 1706 1707 rb0_mask &= rb_mask; 1708 rb1_mask &= rb_mask; 1709 if (!rb0_mask || !rb1_mask) { 1710 raster_config_se &= ~RB_MAP_PKR0_MASK; 1711 1712 if (!rb0_mask) { 1713 raster_config_se |= 1714 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1715 } else { 1716 raster_config_se |= 1717 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1718 } 1719 } 1720 1721 if (rb_per_se > 2) { 1722 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1723 rb1_mask = rb0_mask << 1; 1724 rb0_mask &= rb_mask; 1725 rb1_mask &= rb_mask; 1726 if (!rb0_mask || !rb1_mask) { 1727 raster_config_se &= ~RB_MAP_PKR1_MASK; 1728 1729 if (!rb0_mask) { 1730 raster_config_se |= 1731 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1732 } else { 1733 raster_config_se |= 1734 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1735 } 1736 } 1737 } 1738 } 1739 1740 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1741 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1742 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1743 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1744 } 1745 1746 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1747 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1748 } 1749 1750 /** 1751 * gfx_v7_0_setup_rb - setup the RBs on the asic 1752 * 1753 * @adev: amdgpu_device pointer 1754 * 1755 * Configures per-SE/SH RB registers (CIK). 1756 */ 1757 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1758 { 1759 int i, j; 1760 u32 data; 1761 u32 raster_config = 0, raster_config_1 = 0; 1762 u32 active_rbs = 0; 1763 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1764 adev->gfx.config.max_sh_per_se; 1765 unsigned num_rb_pipes; 1766 1767 mutex_lock(&adev->grbm_idx_mutex); 1768 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1769 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1770 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1771 data = gfx_v7_0_get_rb_active_bitmap(adev); 1772 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1773 rb_bitmap_width_per_sh); 1774 } 1775 } 1776 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1777 1778 adev->gfx.config.backend_enable_mask = active_rbs; 1779 adev->gfx.config.num_rbs = hweight32(active_rbs); 1780 1781 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1782 adev->gfx.config.max_shader_engines, 16); 1783 1784 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1785 1786 if (!adev->gfx.config.backend_enable_mask || 1787 adev->gfx.config.num_rbs >= num_rb_pipes) { 1788 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1789 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1790 } else { 1791 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1792 adev->gfx.config.backend_enable_mask, 1793 num_rb_pipes); 1794 } 1795 1796 /* cache the values for userspace */ 1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1799 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1800 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1801 RREG32(mmCC_RB_BACKEND_DISABLE); 1802 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1803 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1804 adev->gfx.config.rb_config[i][j].raster_config = 1805 RREG32(mmPA_SC_RASTER_CONFIG); 1806 adev->gfx.config.rb_config[i][j].raster_config_1 = 1807 RREG32(mmPA_SC_RASTER_CONFIG_1); 1808 } 1809 } 1810 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1811 mutex_unlock(&adev->grbm_idx_mutex); 1812 } 1813 1814 #define DEFAULT_SH_MEM_BASES (0x6000) 1815 /** 1816 * gfx_v7_0_init_compute_vmid - gart enable 1817 * 1818 * @adev: amdgpu_device pointer 1819 * 1820 * Initialize compute vmid sh_mem registers 1821 * 1822 */ 1823 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1824 { 1825 int i; 1826 uint32_t sh_mem_config; 1827 uint32_t sh_mem_bases; 1828 1829 /* 1830 * Configure apertures: 1831 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1832 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1833 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1834 */ 1835 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1836 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1837 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1838 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1839 mutex_lock(&adev->srbm_mutex); 1840 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1841 cik_srbm_select(adev, 0, 0, 0, i); 1842 /* CP and shaders */ 1843 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1844 WREG32(mmSH_MEM_APE1_BASE, 1); 1845 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1846 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1847 } 1848 cik_srbm_select(adev, 0, 0, 0, 0); 1849 mutex_unlock(&adev->srbm_mutex); 1850 1851 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1852 access. These should be enabled by FW for target VMIDs. */ 1853 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1854 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 1855 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); 1856 WREG32(amdgpu_gds_reg_offset[i].gws, 0); 1857 WREG32(amdgpu_gds_reg_offset[i].oa, 0); 1858 } 1859 } 1860 1861 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) 1862 { 1863 int vmid; 1864 1865 /* 1866 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1867 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1868 * the driver can enable them for graphics. VMID0 should maintain 1869 * access so that HWS firmware can save/restore entries. 1870 */ 1871 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1872 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 1873 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 1874 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 1875 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 1876 } 1877 } 1878 1879 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1880 { 1881 adev->gfx.config.double_offchip_lds_buf = 1; 1882 } 1883 1884 /** 1885 * gfx_v7_0_constants_init - setup the 3D engine 1886 * 1887 * @adev: amdgpu_device pointer 1888 * 1889 * init the gfx constants such as the 3D engine, tiling configuration 1890 * registers, maximum number of quad pipes, render backends... 1891 */ 1892 static void gfx_v7_0_constants_init(struct amdgpu_device *adev) 1893 { 1894 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1895 u32 tmp; 1896 int i; 1897 1898 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1899 1900 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1901 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1902 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1903 1904 gfx_v7_0_tiling_mode_table_init(adev); 1905 1906 gfx_v7_0_setup_rb(adev); 1907 gfx_v7_0_get_cu_info(adev); 1908 gfx_v7_0_config_init(adev); 1909 1910 /* set HW defaults for 3D engine */ 1911 WREG32(mmCP_MEQ_THRESHOLDS, 1912 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1913 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1914 1915 mutex_lock(&adev->grbm_idx_mutex); 1916 /* 1917 * making sure that the following register writes will be broadcasted 1918 * to all the shaders 1919 */ 1920 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1921 1922 /* XXX SH_MEM regs */ 1923 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1924 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1925 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1926 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1927 MTYPE_NC); 1928 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1929 MTYPE_UC); 1930 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1931 1932 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1933 SWIZZLE_ENABLE, 1); 1934 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1935 ELEMENT_SIZE, 1); 1936 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1937 INDEX_STRIDE, 3); 1938 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1939 1940 mutex_lock(&adev->srbm_mutex); 1941 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1942 if (i == 0) 1943 sh_mem_base = 0; 1944 else 1945 sh_mem_base = adev->gmc.shared_aperture_start >> 48; 1946 cik_srbm_select(adev, 0, 0, 0, i); 1947 /* CP and shaders */ 1948 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1949 WREG32(mmSH_MEM_APE1_BASE, 1); 1950 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1951 WREG32(mmSH_MEM_BASES, sh_mem_base); 1952 } 1953 cik_srbm_select(adev, 0, 0, 0, 0); 1954 mutex_unlock(&adev->srbm_mutex); 1955 1956 gfx_v7_0_init_compute_vmid(adev); 1957 gfx_v7_0_init_gds_vmid(adev); 1958 1959 WREG32(mmSX_DEBUG_1, 0x20); 1960 1961 WREG32(mmTA_CNTL_AUX, 0x00010000); 1962 1963 tmp = RREG32(mmSPI_CONFIG_CNTL); 1964 tmp |= 0x03000000; 1965 WREG32(mmSPI_CONFIG_CNTL, tmp); 1966 1967 WREG32(mmSQ_CONFIG, 1); 1968 1969 WREG32(mmDB_DEBUG, 0); 1970 1971 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1972 tmp |= 0x00000400; 1973 WREG32(mmDB_DEBUG2, tmp); 1974 1975 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1976 tmp |= 0x00020200; 1977 WREG32(mmDB_DEBUG3, tmp); 1978 1979 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1980 tmp |= 0x00018208; 1981 WREG32(mmCB_HW_CONTROL, tmp); 1982 1983 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1984 1985 WREG32(mmPA_SC_FIFO_SIZE, 1986 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1987 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1988 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1989 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1990 1991 WREG32(mmVGT_NUM_INSTANCES, 1); 1992 1993 WREG32(mmCP_PERFMON_CNTL, 0); 1994 1995 WREG32(mmSQ_CONFIG, 0); 1996 1997 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1998 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1999 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 2000 2001 WREG32(mmVGT_CACHE_INVALIDATION, 2002 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 2003 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 2004 2005 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2006 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2007 2008 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2009 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2010 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2011 2012 tmp = RREG32(mmSPI_ARB_PRIORITY); 2013 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2014 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2015 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2016 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2017 WREG32(mmSPI_ARB_PRIORITY, tmp); 2018 2019 mutex_unlock(&adev->grbm_idx_mutex); 2020 2021 udelay(50); 2022 } 2023 2024 /** 2025 * gfx_v7_0_ring_test_ring - basic gfx ring test 2026 * 2027 * @ring: amdgpu_ring structure holding ring information 2028 * 2029 * Allocate a scratch register and write to it using the gfx ring (CIK). 2030 * Provides a basic gfx ring test to verify that the ring is working. 2031 * Used by gfx_v7_0_cp_gfx_resume(); 2032 * Returns 0 on success, error on failure. 2033 */ 2034 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2035 { 2036 struct amdgpu_device *adev = ring->adev; 2037 uint32_t tmp = 0; 2038 unsigned i; 2039 int r; 2040 2041 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2042 r = amdgpu_ring_alloc(ring, 3); 2043 if (r) 2044 return r; 2045 2046 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2047 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); 2048 amdgpu_ring_write(ring, 0xDEADBEEF); 2049 amdgpu_ring_commit(ring); 2050 2051 for (i = 0; i < adev->usec_timeout; i++) { 2052 tmp = RREG32(mmSCRATCH_REG0); 2053 if (tmp == 0xDEADBEEF) 2054 break; 2055 udelay(1); 2056 } 2057 if (i >= adev->usec_timeout) 2058 r = -ETIMEDOUT; 2059 return r; 2060 } 2061 2062 /** 2063 * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp 2064 * 2065 * @ring: amdgpu_ring structure holding ring information 2066 * 2067 * Emits an hdp flush on the cp. 2068 */ 2069 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2070 { 2071 u32 ref_and_mask; 2072 int usepfp; 2073 struct amdgpu_device *adev = ring->adev; 2074 2075 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2076 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2077 return; 2078 } 2079 2080 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &usepfp); 2081 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2082 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2083 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2084 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2085 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2086 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2087 amdgpu_ring_write(ring, ref_and_mask); 2088 amdgpu_ring_write(ring, ref_and_mask); 2089 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2090 } 2091 2092 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2093 { 2094 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2095 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2096 EVENT_INDEX(4)); 2097 2098 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2099 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2100 EVENT_INDEX(0)); 2101 } 2102 2103 /** 2104 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2105 * 2106 * @ring: amdgpu_ring structure holding ring information 2107 * @addr: address 2108 * @seq: sequence number 2109 * @flags: fence related flags 2110 * 2111 * Emits a fence sequence number on the gfx ring and flushes 2112 * GPU caches. 2113 */ 2114 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2115 u64 seq, unsigned flags) 2116 { 2117 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2118 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2119 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 2120 2121 /* Workaround for cache flush problems. First send a dummy EOP 2122 * event down the pipe with seq one below. 2123 */ 2124 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2125 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2126 EOP_TC_ACTION_EN | 2127 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2128 EVENT_INDEX(5))); 2129 amdgpu_ring_write(ring, addr & 0xfffffffc); 2130 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2131 DATA_SEL(1) | INT_SEL(0)); 2132 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2133 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2134 2135 /* Then send the real EOP event down the pipe. */ 2136 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2137 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2138 EOP_TC_ACTION_EN | 2139 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2140 EVENT_INDEX(5) | 2141 (exec ? EOP_EXEC : 0))); 2142 amdgpu_ring_write(ring, addr & 0xfffffffc); 2143 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2144 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2145 amdgpu_ring_write(ring, lower_32_bits(seq)); 2146 amdgpu_ring_write(ring, upper_32_bits(seq)); 2147 } 2148 2149 /** 2150 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2151 * 2152 * @ring: amdgpu_ring structure holding ring information 2153 * @addr: address 2154 * @seq: sequence number 2155 * @flags: fence related flags 2156 * 2157 * Emits a fence sequence number on the compute ring and flushes 2158 * GPU caches. 2159 */ 2160 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2161 u64 addr, u64 seq, 2162 unsigned flags) 2163 { 2164 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2165 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2166 2167 /* RELEASE_MEM - flush caches, send int */ 2168 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2169 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2170 EOP_TC_ACTION_EN | 2171 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2172 EVENT_INDEX(5))); 2173 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2174 amdgpu_ring_write(ring, addr & 0xfffffffc); 2175 amdgpu_ring_write(ring, upper_32_bits(addr)); 2176 amdgpu_ring_write(ring, lower_32_bits(seq)); 2177 amdgpu_ring_write(ring, upper_32_bits(seq)); 2178 } 2179 2180 /* 2181 * IB stuff 2182 */ 2183 /** 2184 * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring 2185 * 2186 * @ring: amdgpu_ring structure holding ring information 2187 * @job: job to retrieve vmid from 2188 * @ib: amdgpu indirect buffer object 2189 * @flags: options (AMDGPU_HAVE_CTX_SWITCH) 2190 * 2191 * Emits an DE (drawing engine) or CE (constant engine) IB 2192 * on the gfx ring. IBs are usually generated by userspace 2193 * acceleration drivers and submitted to the kernel for 2194 * scheduling on the ring. This function schedules the IB 2195 * on the gfx ring for execution by the GPU. 2196 */ 2197 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2198 struct amdgpu_job *job, 2199 struct amdgpu_ib *ib, 2200 uint32_t flags) 2201 { 2202 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2203 u32 header, control = 0; 2204 2205 if (ib->flags & AMDGPU_IB_FLAG_CE) 2206 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2207 else 2208 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2209 2210 control |= ib->length_dw | (vmid << 24); 2211 2212 amdgpu_ring_write(ring, header); 2213 amdgpu_ring_write(ring, 2214 #ifdef __BIG_ENDIAN 2215 (2 << 0) | 2216 #endif 2217 (ib->gpu_addr & 0xFFFFFFFC)); 2218 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2219 amdgpu_ring_write(ring, control); 2220 } 2221 2222 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2223 struct amdgpu_job *job, 2224 struct amdgpu_ib *ib, 2225 uint32_t flags) 2226 { 2227 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2228 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2229 2230 /* Currently, there is a high possibility to get wave ID mismatch 2231 * between ME and GDS, leading to a hw deadlock, because ME generates 2232 * different wave IDs than the GDS expects. This situation happens 2233 * randomly when at least 5 compute pipes use GDS ordered append. 2234 * The wave IDs generated by ME are also wrong after suspend/resume. 2235 * Those are probably bugs somewhere else in the kernel driver. 2236 * 2237 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2238 * GDS to 0 for this ring (me/pipe). 2239 */ 2240 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2241 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2242 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 2243 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2244 } 2245 2246 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2247 amdgpu_ring_write(ring, 2248 #ifdef __BIG_ENDIAN 2249 (2 << 0) | 2250 #endif 2251 (ib->gpu_addr & 0xFFFFFFFC)); 2252 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2253 amdgpu_ring_write(ring, control); 2254 } 2255 2256 static void gfx_v7_0_ring_emit_sb(struct amdgpu_ring *ring) 2257 { 2258 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2259 amdgpu_ring_write(ring, 0); 2260 } 2261 2262 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2263 { 2264 uint32_t dw2 = 0; 2265 2266 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2267 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2268 gfx_v7_0_ring_emit_vgt_flush(ring); 2269 /* set load_global_config & load_global_uconfig */ 2270 dw2 |= 0x8001; 2271 /* set load_cs_sh_regs */ 2272 dw2 |= 0x01000000; 2273 /* set load_per_context_state & load_gfx_sh_regs */ 2274 dw2 |= 0x10002; 2275 } 2276 2277 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2278 amdgpu_ring_write(ring, dw2); 2279 amdgpu_ring_write(ring, 0); 2280 } 2281 2282 /** 2283 * gfx_v7_0_ring_test_ib - basic ring IB test 2284 * 2285 * @ring: amdgpu_ring structure holding ring information 2286 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 2287 * 2288 * Allocate an IB and execute it on the gfx ring (CIK). 2289 * Provides a basic gfx ring test to verify that IBs are working. 2290 * Returns 0 on success, error on failure. 2291 */ 2292 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2293 { 2294 struct amdgpu_device *adev = ring->adev; 2295 struct amdgpu_ib ib; 2296 struct dma_fence *f = NULL; 2297 uint32_t tmp = 0; 2298 long r; 2299 2300 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2301 memset(&ib, 0, sizeof(ib)); 2302 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 2303 if (r) 2304 return r; 2305 2306 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2307 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; 2308 ib.ptr[2] = 0xDEADBEEF; 2309 ib.length_dw = 3; 2310 2311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2312 if (r) 2313 goto error; 2314 2315 r = dma_fence_wait_timeout(f, false, timeout); 2316 if (r == 0) { 2317 r = -ETIMEDOUT; 2318 goto error; 2319 } else if (r < 0) { 2320 goto error; 2321 } 2322 tmp = RREG32(mmSCRATCH_REG0); 2323 if (tmp == 0xDEADBEEF) 2324 r = 0; 2325 else 2326 r = -EINVAL; 2327 2328 error: 2329 amdgpu_ib_free(&ib, NULL); 2330 dma_fence_put(f); 2331 return r; 2332 } 2333 2334 /* 2335 * CP. 2336 * On CIK, gfx and compute now have independent command processors. 2337 * 2338 * GFX 2339 * Gfx consists of a single ring and can process both gfx jobs and 2340 * compute jobs. The gfx CP consists of three microengines (ME): 2341 * PFP - Pre-Fetch Parser 2342 * ME - Micro Engine 2343 * CE - Constant Engine 2344 * The PFP and ME make up what is considered the Drawing Engine (DE). 2345 * The CE is an asynchronous engine used for updating buffer desciptors 2346 * used by the DE so that they can be loaded into cache in parallel 2347 * while the DE is processing state update packets. 2348 * 2349 * Compute 2350 * The compute CP consists of two microengines (ME): 2351 * MEC1 - Compute MicroEngine 1 2352 * MEC2 - Compute MicroEngine 2 2353 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2354 * The queues are exposed to userspace and are programmed directly 2355 * by the compute runtime. 2356 */ 2357 /** 2358 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2359 * 2360 * @adev: amdgpu_device pointer 2361 * @enable: enable or disable the MEs 2362 * 2363 * Halts or unhalts the gfx MEs. 2364 */ 2365 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2366 { 2367 if (enable) 2368 WREG32(mmCP_ME_CNTL, 0); 2369 else 2370 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2371 CP_ME_CNTL__PFP_HALT_MASK | 2372 CP_ME_CNTL__CE_HALT_MASK)); 2373 udelay(50); 2374 } 2375 2376 /** 2377 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2378 * 2379 * @adev: amdgpu_device pointer 2380 * 2381 * Loads the gfx PFP, ME, and CE ucode. 2382 * Returns 0 for success, -EINVAL if the ucode is not available. 2383 */ 2384 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2385 { 2386 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2387 const struct gfx_firmware_header_v1_0 *ce_hdr; 2388 const struct gfx_firmware_header_v1_0 *me_hdr; 2389 const __le32 *fw_data; 2390 unsigned i, fw_size; 2391 2392 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2393 return -EINVAL; 2394 2395 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2396 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2397 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2398 2399 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2400 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2401 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2402 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2403 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2404 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2405 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2406 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2407 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2408 2409 gfx_v7_0_cp_gfx_enable(adev, false); 2410 2411 /* PFP */ 2412 fw_data = (const __le32 *) 2413 (adev->gfx.pfp_fw->data + 2414 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2415 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2416 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2417 for (i = 0; i < fw_size; i++) 2418 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2419 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2420 2421 /* CE */ 2422 fw_data = (const __le32 *) 2423 (adev->gfx.ce_fw->data + 2424 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2425 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2426 WREG32(mmCP_CE_UCODE_ADDR, 0); 2427 for (i = 0; i < fw_size; i++) 2428 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2429 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2430 2431 /* ME */ 2432 fw_data = (const __le32 *) 2433 (adev->gfx.me_fw->data + 2434 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2435 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2436 WREG32(mmCP_ME_RAM_WADDR, 0); 2437 for (i = 0; i < fw_size; i++) 2438 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2439 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2440 2441 return 0; 2442 } 2443 2444 /** 2445 * gfx_v7_0_cp_gfx_start - start the gfx ring 2446 * 2447 * @adev: amdgpu_device pointer 2448 * 2449 * Enables the ring and loads the clear state context and other 2450 * packets required to init the ring. 2451 * Returns 0 for success, error for failure. 2452 */ 2453 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2454 { 2455 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2456 const struct cs_section_def *sect = NULL; 2457 const struct cs_extent_def *ext = NULL; 2458 int r, i; 2459 2460 /* init the CP */ 2461 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2462 WREG32(mmCP_ENDIAN_SWAP, 0); 2463 WREG32(mmCP_DEVICE_ID, 1); 2464 2465 gfx_v7_0_cp_gfx_enable(adev, true); 2466 2467 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2468 if (r) { 2469 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2470 return r; 2471 } 2472 2473 /* init the CE partitions. CE only used for gfx on CIK */ 2474 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2475 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2476 amdgpu_ring_write(ring, 0x8000); 2477 amdgpu_ring_write(ring, 0x8000); 2478 2479 /* clear state buffer */ 2480 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2481 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2482 2483 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2484 amdgpu_ring_write(ring, 0x80000000); 2485 amdgpu_ring_write(ring, 0x80000000); 2486 2487 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2488 for (ext = sect->section; ext->extent != NULL; ++ext) { 2489 if (sect->id == SECT_CONTEXT) { 2490 amdgpu_ring_write(ring, 2491 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2492 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2493 for (i = 0; i < ext->reg_count; i++) 2494 amdgpu_ring_write(ring, ext->extent[i]); 2495 } 2496 } 2497 } 2498 2499 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2500 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2501 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2502 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2503 2504 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2505 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2506 2507 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2508 amdgpu_ring_write(ring, 0); 2509 2510 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2511 amdgpu_ring_write(ring, 0x00000316); 2512 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2513 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2514 2515 amdgpu_ring_commit(ring); 2516 2517 return 0; 2518 } 2519 2520 /** 2521 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2522 * 2523 * @adev: amdgpu_device pointer 2524 * 2525 * Program the location and size of the gfx ring buffer 2526 * and test it to make sure it's working. 2527 * Returns 0 for success, error for failure. 2528 */ 2529 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2530 { 2531 struct amdgpu_ring *ring; 2532 u32 tmp; 2533 u32 rb_bufsz; 2534 u64 rb_addr, rptr_addr; 2535 int r; 2536 2537 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2538 if (adev->asic_type != CHIP_HAWAII) 2539 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2540 2541 /* Set the write pointer delay */ 2542 WREG32(mmCP_RB_WPTR_DELAY, 0); 2543 2544 /* set the RB to use vmid 0 */ 2545 WREG32(mmCP_RB_VMID, 0); 2546 2547 WREG32(mmSCRATCH_ADDR, 0); 2548 2549 /* ring 0 - compute and gfx */ 2550 ring = &adev->gfx.gfx_ring[0]; 2551 *ring->wptr_cpu_addr = 0; 2552 *ring->rptr_cpu_addr = 0; 2553 amdgpu_ring_clear_ring(ring); 2554 2555 /* Set ring buffer size */ 2556 rb_bufsz = order_base_2(ring->ring_size / 8); 2557 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2558 #ifdef __BIG_ENDIAN 2559 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2560 #endif 2561 WREG32(mmCP_RB0_CNTL, tmp); 2562 2563 /* Initialize the ring buffer's read and write pointers */ 2564 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2565 ring->wptr = 0; 2566 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2567 WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); 2568 2569 /* set the wb address whether it's enabled or not */ 2570 rptr_addr = ring->rptr_gpu_addr; 2571 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2572 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2573 2574 /* scratch register shadowing is no longer supported */ 2575 WREG32(mmSCRATCH_UMSK, 0); 2576 2577 mdelay(1); 2578 WREG32(mmCP_RB0_CNTL, tmp); 2579 2580 rb_addr = ring->gpu_addr >> 8; 2581 WREG32(mmCP_RB0_BASE, rb_addr); 2582 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2583 2584 /* start the ring */ 2585 r = gfx_v7_0_cp_gfx_start(adev); 2586 if (r) 2587 return r; 2588 2589 r = amdgpu_ring_test_helper(ring); 2590 if (r) 2591 return r; 2592 2593 return 0; 2594 } 2595 2596 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2597 { 2598 return *ring->rptr_cpu_addr; 2599 } 2600 2601 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2602 { 2603 struct amdgpu_device *adev = ring->adev; 2604 2605 return RREG32(mmCP_RB0_WPTR); 2606 } 2607 2608 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2609 { 2610 struct amdgpu_device *adev = ring->adev; 2611 2612 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2613 (void)RREG32(mmCP_RB0_WPTR); 2614 } 2615 2616 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2617 { 2618 /* XXX check if swapping is necessary on BE */ 2619 return *ring->wptr_cpu_addr; 2620 } 2621 2622 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2623 { 2624 struct amdgpu_device *adev = ring->adev; 2625 2626 /* XXX check if swapping is necessary on BE */ 2627 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2628 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2629 } 2630 2631 /** 2632 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2633 * 2634 * @adev: amdgpu_device pointer 2635 * @enable: enable or disable the MEs 2636 * 2637 * Halts or unhalts the compute MEs. 2638 */ 2639 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2640 { 2641 if (enable) 2642 WREG32(mmCP_MEC_CNTL, 0); 2643 else 2644 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2645 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2646 udelay(50); 2647 } 2648 2649 /** 2650 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2651 * 2652 * @adev: amdgpu_device pointer 2653 * 2654 * Loads the compute MEC1&2 ucode. 2655 * Returns 0 for success, -EINVAL if the ucode is not available. 2656 */ 2657 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2658 { 2659 const struct gfx_firmware_header_v1_0 *mec_hdr; 2660 const __le32 *fw_data; 2661 unsigned i, fw_size; 2662 2663 if (!adev->gfx.mec_fw) 2664 return -EINVAL; 2665 2666 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2667 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2668 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2669 adev->gfx.mec_feature_version = le32_to_cpu( 2670 mec_hdr->ucode_feature_version); 2671 2672 gfx_v7_0_cp_compute_enable(adev, false); 2673 2674 /* MEC1 */ 2675 fw_data = (const __le32 *) 2676 (adev->gfx.mec_fw->data + 2677 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2678 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2679 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2680 for (i = 0; i < fw_size; i++) 2681 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2682 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2683 2684 if (adev->asic_type == CHIP_KAVERI) { 2685 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2686 2687 if (!adev->gfx.mec2_fw) 2688 return -EINVAL; 2689 2690 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2691 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2692 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2693 adev->gfx.mec2_feature_version = le32_to_cpu( 2694 mec2_hdr->ucode_feature_version); 2695 2696 /* MEC2 */ 2697 fw_data = (const __le32 *) 2698 (adev->gfx.mec2_fw->data + 2699 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2700 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2701 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2702 for (i = 0; i < fw_size; i++) 2703 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2704 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2705 } 2706 2707 return 0; 2708 } 2709 2710 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2711 { 2712 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2713 } 2714 2715 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2716 { 2717 int r; 2718 u32 *hpd; 2719 size_t mec_hpd_size; 2720 2721 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2722 2723 /* take ownership of the relevant compute queues */ 2724 amdgpu_gfx_compute_queue_acquire(adev); 2725 2726 /* allocate space for ALL pipes (even the ones we don't own) */ 2727 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2728 * GFX7_MEC_HPD_SIZE * 2; 2729 2730 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2731 AMDGPU_GEM_DOMAIN_VRAM | 2732 AMDGPU_GEM_DOMAIN_GTT, 2733 &adev->gfx.mec.hpd_eop_obj, 2734 &adev->gfx.mec.hpd_eop_gpu_addr, 2735 (void **)&hpd); 2736 if (r) { 2737 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2738 gfx_v7_0_mec_fini(adev); 2739 return r; 2740 } 2741 2742 /* clear memory. Not sure if this is required or not */ 2743 memset(hpd, 0, mec_hpd_size); 2744 2745 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2746 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2747 2748 return 0; 2749 } 2750 2751 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2752 int mec, int pipe) 2753 { 2754 u64 eop_gpu_addr; 2755 u32 tmp; 2756 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2757 * GFX7_MEC_HPD_SIZE * 2; 2758 2759 mutex_lock(&adev->srbm_mutex); 2760 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2761 2762 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2763 2764 /* write the EOP addr */ 2765 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2766 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2767 2768 /* set the VMID assigned */ 2769 WREG32(mmCP_HPD_EOP_VMID, 0); 2770 2771 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2772 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2773 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2774 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2775 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2776 2777 cik_srbm_select(adev, 0, 0, 0, 0); 2778 mutex_unlock(&adev->srbm_mutex); 2779 } 2780 2781 static int gfx_v7_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) 2782 { 2783 int i, r = 0; 2784 2785 /* disable the queue if it's active */ 2786 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { 2787 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req); 2788 for (i = 0; i < adev->usec_timeout; i++) { 2789 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) 2790 break; 2791 udelay(1); 2792 } 2793 2794 if (i == adev->usec_timeout) 2795 r = -ETIMEDOUT; 2796 2797 } 2798 2799 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2800 WREG32(mmCP_HQD_PQ_RPTR, 0); 2801 WREG32(mmCP_HQD_PQ_WPTR, 0); 2802 2803 return r; 2804 } 2805 2806 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2807 struct cik_mqd *mqd, 2808 uint64_t mqd_gpu_addr, 2809 struct amdgpu_ring *ring) 2810 { 2811 u64 hqd_gpu_addr; 2812 u64 wb_gpu_addr; 2813 u32 tmp; 2814 2815 /* init the mqd struct */ 2816 memset(mqd, 0, sizeof(struct cik_mqd)); 2817 2818 mqd->header = 0xC0310800; 2819 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2820 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2821 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2822 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2823 2824 /* enable doorbell? */ 2825 mqd->cp_hqd_pq_doorbell_control = 2826 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2827 if (ring->use_doorbell) 2828 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2829 else 2830 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2831 2832 /* set the pointer to the MQD */ 2833 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2834 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2835 2836 /* set MQD vmid to 0 */ 2837 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2838 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2839 2840 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2841 hqd_gpu_addr = ring->gpu_addr >> 8; 2842 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2843 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2844 2845 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2846 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2847 mqd->cp_hqd_pq_control &= 2848 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2849 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2850 2851 mqd->cp_hqd_pq_control |= 2852 order_base_2(ring->ring_size / 8); 2853 mqd->cp_hqd_pq_control |= 2854 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2855 #ifdef __BIG_ENDIAN 2856 mqd->cp_hqd_pq_control |= 2857 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2858 #endif 2859 mqd->cp_hqd_pq_control &= 2860 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2861 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2862 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2863 mqd->cp_hqd_pq_control |= 2864 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2865 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2866 2867 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2868 wb_gpu_addr = ring->wptr_gpu_addr; 2869 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2870 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2871 2872 /* set the wb address whether it's enabled or not */ 2873 wb_gpu_addr = ring->rptr_gpu_addr; 2874 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2875 mqd->cp_hqd_pq_rptr_report_addr_hi = 2876 upper_32_bits(wb_gpu_addr) & 0xffff; 2877 2878 /* enable the doorbell if requested */ 2879 if (ring->use_doorbell) { 2880 mqd->cp_hqd_pq_doorbell_control = 2881 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2882 mqd->cp_hqd_pq_doorbell_control &= 2883 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2884 mqd->cp_hqd_pq_doorbell_control |= 2885 (ring->doorbell_index << 2886 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2887 mqd->cp_hqd_pq_doorbell_control |= 2888 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2889 mqd->cp_hqd_pq_doorbell_control &= 2890 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 2891 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 2892 2893 } else { 2894 mqd->cp_hqd_pq_doorbell_control = 0; 2895 } 2896 2897 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2898 ring->wptr = 0; 2899 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 2900 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2901 2902 /* set the vmid for the queue */ 2903 mqd->cp_hqd_vmid = 0; 2904 2905 /* defaults */ 2906 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 2907 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 2908 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 2909 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 2910 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 2911 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 2912 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 2913 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 2914 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 2915 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 2916 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 2917 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2918 tmp = RREG32(mmCP_HQD_QUANTUM); 2919 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 2920 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 2921 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); 2922 mqd->cp_hqd_quantum = tmp; 2923 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 2924 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 2925 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 2926 2927 /* activate the queue */ 2928 mqd->cp_hqd_active = 1; 2929 } 2930 2931 static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 2932 { 2933 uint32_t tmp; 2934 uint32_t mqd_reg; 2935 uint32_t *mqd_data; 2936 2937 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 2938 mqd_data = &mqd->cp_mqd_base_addr_lo; 2939 2940 /* disable wptr polling */ 2941 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 2942 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2943 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 2944 2945 /* program all HQD registers */ 2946 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 2947 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2948 2949 /* activate the HQD */ 2950 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 2951 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2952 2953 return 0; 2954 } 2955 2956 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 2957 { 2958 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2959 struct cik_mqd *mqd = ring->mqd_ptr; 2960 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2961 2962 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2963 memset((void *)mqd, 0, ring->mqd_size); 2964 mutex_lock(&adev->srbm_mutex); 2965 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2966 gfx_v7_0_mqd_init(adev, mqd, ring->mqd_gpu_addr, ring); 2967 gfx_v7_0_deactivate_hqd(adev, 1); 2968 gfx_v7_0_mqd_commit(adev, mqd); 2969 cik_srbm_select(adev, 0, 0, 0, 0); 2970 mutex_unlock(&adev->srbm_mutex); 2971 2972 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2973 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, ring->mqd_size); 2974 } else { 2975 /* restore MQD to a clean status */ 2976 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2977 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], ring->mqd_size); 2978 2979 /* Re-commit the restored backup */ 2980 mutex_lock(&adev->srbm_mutex); 2981 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2982 gfx_v7_0_deactivate_hqd(adev, 2); 2983 gfx_v7_0_mqd_commit(adev, mqd); 2984 cik_srbm_select(adev, 0, 0, 0, 0); 2985 mutex_unlock(&adev->srbm_mutex); 2986 2987 /* reset ring buffer */ 2988 ring->wptr = 0; 2989 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 2990 atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0); 2991 amdgpu_ring_clear_ring(ring); 2992 } 2993 2994 return 0; 2995 } 2996 2997 /** 2998 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 2999 * 3000 * @adev: amdgpu_device pointer 3001 * 3002 * Program the compute queues and test them to make sure they 3003 * are working. 3004 * Returns 0 for success, error for failure. 3005 */ 3006 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3007 { 3008 int r, i, j; 3009 u32 tmp; 3010 struct amdgpu_ring *ring; 3011 3012 /* fix up chicken bits */ 3013 tmp = RREG32(mmCP_CPF_DEBUG); 3014 tmp |= (1 << 23); 3015 WREG32(mmCP_CPF_DEBUG, tmp); 3016 3017 /* init all pipes (even the ones we don't own) */ 3018 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3019 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3020 gfx_v7_0_compute_pipe_init(adev, i, j); 3021 3022 /* init the queues */ 3023 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3024 r = gfx_v7_0_compute_queue_init(adev, i); 3025 if (r) 3026 return r; 3027 } 3028 3029 gfx_v7_0_cp_compute_enable(adev, true); 3030 3031 r = 0; 3032 3033 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3034 ring = &adev->gfx.compute_ring[i]; 3035 r |= amdgpu_ring_test_helper(ring); 3036 } 3037 3038 return r; 3039 } 3040 3041 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3042 { 3043 gfx_v7_0_cp_gfx_enable(adev, enable); 3044 gfx_v7_0_cp_compute_enable(adev, enable); 3045 } 3046 3047 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3048 { 3049 int r; 3050 3051 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3052 if (r) 3053 return r; 3054 r = gfx_v7_0_cp_compute_load_microcode(adev); 3055 if (r) 3056 return r; 3057 3058 return 0; 3059 } 3060 3061 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3062 bool enable) 3063 { 3064 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3065 3066 if (enable) 3067 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3068 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3069 else 3070 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3071 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3072 WREG32(mmCP_INT_CNTL_RING0, tmp); 3073 } 3074 3075 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3076 { 3077 int r; 3078 3079 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3080 3081 r = gfx_v7_0_cp_load_microcode(adev); 3082 if (r) 3083 return r; 3084 3085 r = gfx_v7_0_cp_gfx_resume(adev); 3086 if (r) 3087 return r; 3088 r = gfx_v7_0_cp_compute_resume(adev); 3089 if (r) 3090 return r; 3091 3092 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3093 3094 return 0; 3095 } 3096 3097 /** 3098 * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP 3099 * 3100 * @ring: the ring to emit the commands to 3101 * 3102 * Sync the command pipeline with the PFP. E.g. wait for everything 3103 * to be completed. 3104 */ 3105 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3106 { 3107 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3108 uint32_t seq = ring->fence_drv.sync_seq; 3109 uint64_t addr = ring->fence_drv.gpu_addr; 3110 3111 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3112 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3113 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3114 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3115 amdgpu_ring_write(ring, addr & 0xfffffffc); 3116 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3117 amdgpu_ring_write(ring, seq); 3118 amdgpu_ring_write(ring, 0xffffffff); 3119 amdgpu_ring_write(ring, 4); /* poll interval */ 3120 } 3121 3122 /* 3123 * vm 3124 * VMID 0 is the physical GPU addresses as used by the kernel. 3125 * VMIDs 1-15 are used for userspace clients and are handled 3126 * by the amdgpu vm/hsa code. 3127 */ 3128 /** 3129 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3130 * 3131 * @ring: amdgpu_ring pointer 3132 * @vmid: vmid number to use 3133 * @pd_addr: address 3134 * 3135 * Update the page table base and flush the VM TLB 3136 * using the CP (CIK). 3137 */ 3138 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3139 unsigned vmid, uint64_t pd_addr) 3140 { 3141 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3142 3143 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3144 3145 /* wait for the invalidate to complete */ 3146 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3147 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3148 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3149 WAIT_REG_MEM_ENGINE(0))); /* me */ 3150 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3151 amdgpu_ring_write(ring, 0); 3152 amdgpu_ring_write(ring, 0); /* ref */ 3153 amdgpu_ring_write(ring, 0); /* mask */ 3154 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3155 3156 /* compute doesn't have PFP */ 3157 if (usepfp) { 3158 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3159 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3160 amdgpu_ring_write(ring, 0x0); 3161 } 3162 } 3163 3164 static unsigned int gfx_v7_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 3165 uint64_t gpu_addr) 3166 { 3167 unsigned int ret; 3168 3169 /* Discard following DWs after this packet when gpu_addr==0 */ 3170 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 3171 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 3172 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 3173 amdgpu_ring_write(ring, 0); 3174 ret = ring->wptr & ring->buf_mask; 3175 /* patch dummy value later */ 3176 amdgpu_ring_write(ring, 0); 3177 return ret; 3178 } 3179 3180 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 3181 uint32_t reg, uint32_t val) 3182 { 3183 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3184 3185 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3186 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3187 WRITE_DATA_DST_SEL(0))); 3188 amdgpu_ring_write(ring, reg); 3189 amdgpu_ring_write(ring, 0); 3190 amdgpu_ring_write(ring, val); 3191 } 3192 3193 /* 3194 * RLC 3195 * The RLC is a multi-purpose microengine that handles a 3196 * variety of functions. 3197 */ 3198 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3199 { 3200 const u32 *src_ptr; 3201 u32 dws; 3202 const struct cs_section_def *cs_data; 3203 int r; 3204 3205 /* allocate rlc buffers */ 3206 if (adev->flags & AMD_IS_APU) { 3207 if (adev->asic_type == CHIP_KAVERI) { 3208 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3209 adev->gfx.rlc.reg_list_size = 3210 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3211 } else { 3212 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3213 adev->gfx.rlc.reg_list_size = 3214 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3215 } 3216 } 3217 adev->gfx.rlc.cs_data = ci_cs_data; 3218 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3219 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3220 3221 src_ptr = adev->gfx.rlc.reg_list; 3222 dws = adev->gfx.rlc.reg_list_size; 3223 dws += (5 * 16) + 48 + 48 + 64; 3224 3225 cs_data = adev->gfx.rlc.cs_data; 3226 3227 if (src_ptr) { 3228 /* init save restore block */ 3229 r = amdgpu_gfx_rlc_init_sr(adev, dws); 3230 if (r) 3231 return r; 3232 } 3233 3234 if (cs_data) { 3235 /* init clear state block */ 3236 r = amdgpu_gfx_rlc_init_csb(adev); 3237 if (r) 3238 return r; 3239 } 3240 3241 if (adev->gfx.rlc.cp_table_size) { 3242 r = amdgpu_gfx_rlc_init_cpt(adev); 3243 if (r) 3244 return r; 3245 } 3246 3247 /* init spm vmid with 0xf */ 3248 if (adev->gfx.rlc.funcs->update_spm_vmid) 3249 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 3250 3251 return 0; 3252 } 3253 3254 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3255 { 3256 u32 tmp; 3257 3258 tmp = RREG32(mmRLC_LB_CNTL); 3259 if (enable) 3260 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3261 else 3262 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3263 WREG32(mmRLC_LB_CNTL, tmp); 3264 } 3265 3266 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3267 { 3268 u32 i, j, k; 3269 u32 mask; 3270 3271 mutex_lock(&adev->grbm_idx_mutex); 3272 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3273 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3274 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3275 for (k = 0; k < adev->usec_timeout; k++) { 3276 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3277 break; 3278 udelay(1); 3279 } 3280 } 3281 } 3282 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3283 mutex_unlock(&adev->grbm_idx_mutex); 3284 3285 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3286 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3287 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3288 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3289 for (k = 0; k < adev->usec_timeout; k++) { 3290 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3291 break; 3292 udelay(1); 3293 } 3294 } 3295 3296 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3297 { 3298 u32 tmp; 3299 3300 tmp = RREG32(mmRLC_CNTL); 3301 if (tmp != rlc) 3302 WREG32(mmRLC_CNTL, rlc); 3303 } 3304 3305 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3306 { 3307 u32 data, orig; 3308 3309 orig = data = RREG32(mmRLC_CNTL); 3310 3311 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3312 u32 i; 3313 3314 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3315 WREG32(mmRLC_CNTL, data); 3316 3317 for (i = 0; i < adev->usec_timeout; i++) { 3318 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3319 break; 3320 udelay(1); 3321 } 3322 3323 gfx_v7_0_wait_for_rlc_serdes(adev); 3324 } 3325 3326 return orig; 3327 } 3328 3329 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 3330 { 3331 return true; 3332 } 3333 3334 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 3335 { 3336 u32 tmp, i, mask; 3337 3338 tmp = 0x1 | (1 << 1); 3339 WREG32(mmRLC_GPR_REG2, tmp); 3340 3341 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3342 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3343 for (i = 0; i < adev->usec_timeout; i++) { 3344 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3345 break; 3346 udelay(1); 3347 } 3348 3349 for (i = 0; i < adev->usec_timeout; i++) { 3350 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3351 break; 3352 udelay(1); 3353 } 3354 } 3355 3356 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 3357 { 3358 u32 tmp; 3359 3360 tmp = 0x1 | (0 << 1); 3361 WREG32(mmRLC_GPR_REG2, tmp); 3362 } 3363 3364 /** 3365 * gfx_v7_0_rlc_stop - stop the RLC ME 3366 * 3367 * @adev: amdgpu_device pointer 3368 * 3369 * Halt the RLC ME (MicroEngine) (CIK). 3370 */ 3371 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3372 { 3373 WREG32(mmRLC_CNTL, 0); 3374 3375 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3376 3377 gfx_v7_0_wait_for_rlc_serdes(adev); 3378 } 3379 3380 /** 3381 * gfx_v7_0_rlc_start - start the RLC ME 3382 * 3383 * @adev: amdgpu_device pointer 3384 * 3385 * Unhalt the RLC ME (MicroEngine) (CIK). 3386 */ 3387 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3388 { 3389 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3390 3391 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3392 3393 udelay(50); 3394 } 3395 3396 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3397 { 3398 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3399 3400 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3401 WREG32(mmGRBM_SOFT_RESET, tmp); 3402 udelay(50); 3403 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3404 WREG32(mmGRBM_SOFT_RESET, tmp); 3405 udelay(50); 3406 } 3407 3408 /** 3409 * gfx_v7_0_rlc_resume - setup the RLC hw 3410 * 3411 * @adev: amdgpu_device pointer 3412 * 3413 * Initialize the RLC registers, load the ucode, 3414 * and start the RLC (CIK). 3415 * Returns 0 for success, -EINVAL if the ucode is not available. 3416 */ 3417 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3418 { 3419 const struct rlc_firmware_header_v1_0 *hdr; 3420 const __le32 *fw_data; 3421 unsigned i, fw_size; 3422 u32 tmp; 3423 3424 if (!adev->gfx.rlc_fw) 3425 return -EINVAL; 3426 3427 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3428 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3429 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3430 adev->gfx.rlc_feature_version = le32_to_cpu( 3431 hdr->ucode_feature_version); 3432 3433 adev->gfx.rlc.funcs->stop(adev); 3434 3435 /* disable CG */ 3436 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3437 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3438 3439 adev->gfx.rlc.funcs->reset(adev); 3440 3441 gfx_v7_0_init_pg(adev); 3442 3443 WREG32(mmRLC_LB_CNTR_INIT, 0); 3444 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3445 3446 mutex_lock(&adev->grbm_idx_mutex); 3447 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3448 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3449 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3450 WREG32(mmRLC_LB_CNTL, 0x80000004); 3451 mutex_unlock(&adev->grbm_idx_mutex); 3452 3453 WREG32(mmRLC_MC_CNTL, 0); 3454 WREG32(mmRLC_UCODE_CNTL, 0); 3455 3456 fw_data = (const __le32 *) 3457 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3458 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3459 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3460 for (i = 0; i < fw_size; i++) 3461 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3462 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3463 3464 /* XXX - find out what chips support lbpw */ 3465 gfx_v7_0_enable_lbpw(adev, false); 3466 3467 if (adev->asic_type == CHIP_BONAIRE) 3468 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3469 3470 adev->gfx.rlc.funcs->start(adev); 3471 3472 return 0; 3473 } 3474 3475 static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 3476 struct amdgpu_ring *ring, unsigned vmid) 3477 { 3478 u32 data; 3479 3480 amdgpu_gfx_off_ctrl(adev, false); 3481 3482 data = RREG32(mmRLC_SPM_VMID); 3483 3484 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK; 3485 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT; 3486 3487 WREG32(mmRLC_SPM_VMID, data); 3488 3489 amdgpu_gfx_off_ctrl(adev, true); 3490 } 3491 3492 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3493 { 3494 u32 data, orig, tmp, tmp2; 3495 3496 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3497 3498 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3499 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3500 3501 tmp = gfx_v7_0_halt_rlc(adev); 3502 3503 mutex_lock(&adev->grbm_idx_mutex); 3504 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3505 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3506 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3507 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3508 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3509 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3510 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3511 mutex_unlock(&adev->grbm_idx_mutex); 3512 3513 gfx_v7_0_update_rlc(adev, tmp); 3514 3515 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3516 if (orig != data) 3517 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3518 3519 } else { 3520 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3521 3522 RREG32(mmCB_CGTT_SCLK_CTRL); 3523 RREG32(mmCB_CGTT_SCLK_CTRL); 3524 RREG32(mmCB_CGTT_SCLK_CTRL); 3525 RREG32(mmCB_CGTT_SCLK_CTRL); 3526 3527 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3528 if (orig != data) 3529 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3530 3531 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3532 } 3533 } 3534 3535 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3536 { 3537 u32 data, orig, tmp = 0; 3538 3539 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3540 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3541 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3542 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3543 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3544 if (orig != data) 3545 WREG32(mmCP_MEM_SLP_CNTL, data); 3546 } 3547 } 3548 3549 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3550 data |= 0x00000001; 3551 data &= 0xfffffffd; 3552 if (orig != data) 3553 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3554 3555 tmp = gfx_v7_0_halt_rlc(adev); 3556 3557 mutex_lock(&adev->grbm_idx_mutex); 3558 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3559 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3560 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3561 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3562 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3563 WREG32(mmRLC_SERDES_WR_CTRL, data); 3564 mutex_unlock(&adev->grbm_idx_mutex); 3565 3566 gfx_v7_0_update_rlc(adev, tmp); 3567 3568 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3569 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3570 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3571 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3572 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3573 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3574 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3575 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3576 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3577 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3578 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3579 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3580 if (orig != data) 3581 WREG32(mmCGTS_SM_CTRL_REG, data); 3582 } 3583 } else { 3584 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3585 data |= 0x00000003; 3586 if (orig != data) 3587 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3588 3589 data = RREG32(mmRLC_MEM_SLP_CNTL); 3590 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3591 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3592 WREG32(mmRLC_MEM_SLP_CNTL, data); 3593 } 3594 3595 data = RREG32(mmCP_MEM_SLP_CNTL); 3596 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3597 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3598 WREG32(mmCP_MEM_SLP_CNTL, data); 3599 } 3600 3601 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3602 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3603 if (orig != data) 3604 WREG32(mmCGTS_SM_CTRL_REG, data); 3605 3606 tmp = gfx_v7_0_halt_rlc(adev); 3607 3608 mutex_lock(&adev->grbm_idx_mutex); 3609 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3610 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3611 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3612 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3613 WREG32(mmRLC_SERDES_WR_CTRL, data); 3614 mutex_unlock(&adev->grbm_idx_mutex); 3615 3616 gfx_v7_0_update_rlc(adev, tmp); 3617 } 3618 } 3619 3620 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3621 bool enable) 3622 { 3623 u32 data, orig; 3624 3625 orig = data = RREG32(mmRLC_PG_CNTL); 3626 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3627 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3628 else 3629 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3630 if (orig != data) 3631 WREG32(mmRLC_PG_CNTL, data); 3632 } 3633 3634 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3635 bool enable) 3636 { 3637 u32 data, orig; 3638 3639 orig = data = RREG32(mmRLC_PG_CNTL); 3640 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3641 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3642 else 3643 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3644 if (orig != data) 3645 WREG32(mmRLC_PG_CNTL, data); 3646 } 3647 3648 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3649 { 3650 u32 data, orig; 3651 3652 orig = data = RREG32(mmRLC_PG_CNTL); 3653 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3654 data &= ~0x8000; 3655 else 3656 data |= 0x8000; 3657 if (orig != data) 3658 WREG32(mmRLC_PG_CNTL, data); 3659 } 3660 3661 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3662 { 3663 u32 data, orig; 3664 3665 orig = data = RREG32(mmRLC_PG_CNTL); 3666 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3667 data &= ~0x2000; 3668 else 3669 data |= 0x2000; 3670 if (orig != data) 3671 WREG32(mmRLC_PG_CNTL, data); 3672 } 3673 3674 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) 3675 { 3676 if (adev->asic_type == CHIP_KAVERI) 3677 return 5; 3678 else 3679 return 4; 3680 } 3681 3682 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3683 bool enable) 3684 { 3685 u32 data, orig; 3686 3687 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3688 orig = data = RREG32(mmRLC_PG_CNTL); 3689 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3690 if (orig != data) 3691 WREG32(mmRLC_PG_CNTL, data); 3692 3693 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3694 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3695 if (orig != data) 3696 WREG32(mmRLC_AUTO_PG_CTRL, data); 3697 } else { 3698 orig = data = RREG32(mmRLC_PG_CNTL); 3699 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3700 if (orig != data) 3701 WREG32(mmRLC_PG_CNTL, data); 3702 3703 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3704 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3705 if (orig != data) 3706 WREG32(mmRLC_AUTO_PG_CTRL, data); 3707 3708 data = RREG32(mmDB_RENDER_CONTROL); 3709 } 3710 } 3711 3712 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3713 u32 bitmap) 3714 { 3715 u32 data; 3716 3717 if (!bitmap) 3718 return; 3719 3720 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3721 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3722 3723 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3724 } 3725 3726 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3727 { 3728 u32 data, mask; 3729 3730 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3731 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3732 3733 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3734 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3735 3736 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3737 3738 return (~data) & mask; 3739 } 3740 3741 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3742 { 3743 u32 tmp; 3744 3745 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3746 3747 tmp = RREG32(mmRLC_MAX_PG_CU); 3748 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3749 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3750 WREG32(mmRLC_MAX_PG_CU, tmp); 3751 } 3752 3753 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3754 bool enable) 3755 { 3756 u32 data, orig; 3757 3758 orig = data = RREG32(mmRLC_PG_CNTL); 3759 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3760 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3761 else 3762 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3763 if (orig != data) 3764 WREG32(mmRLC_PG_CNTL, data); 3765 } 3766 3767 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3768 bool enable) 3769 { 3770 u32 data, orig; 3771 3772 orig = data = RREG32(mmRLC_PG_CNTL); 3773 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3774 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3775 else 3776 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3777 if (orig != data) 3778 WREG32(mmRLC_PG_CNTL, data); 3779 } 3780 3781 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3782 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3783 3784 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3785 { 3786 u32 data, orig; 3787 u32 i; 3788 3789 if (adev->gfx.rlc.cs_data) { 3790 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3791 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3792 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3793 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3794 } else { 3795 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3796 for (i = 0; i < 3; i++) 3797 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3798 } 3799 if (adev->gfx.rlc.reg_list) { 3800 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3801 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3802 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3803 } 3804 3805 orig = data = RREG32(mmRLC_PG_CNTL); 3806 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3807 if (orig != data) 3808 WREG32(mmRLC_PG_CNTL, data); 3809 3810 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3811 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3812 3813 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3814 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3815 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3816 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3817 3818 data = 0x10101010; 3819 WREG32(mmRLC_PG_DELAY, data); 3820 3821 data = RREG32(mmRLC_PG_DELAY_2); 3822 data &= ~0xff; 3823 data |= 0x3; 3824 WREG32(mmRLC_PG_DELAY_2, data); 3825 3826 data = RREG32(mmRLC_AUTO_PG_CTRL); 3827 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3828 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3829 WREG32(mmRLC_AUTO_PG_CTRL, data); 3830 3831 } 3832 3833 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3834 { 3835 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3836 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3837 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3838 } 3839 3840 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3841 { 3842 u32 count = 0; 3843 const struct cs_section_def *sect = NULL; 3844 const struct cs_extent_def *ext = NULL; 3845 3846 if (adev->gfx.rlc.cs_data == NULL) 3847 return 0; 3848 3849 /* begin clear state */ 3850 count += 2; 3851 /* context control state */ 3852 count += 3; 3853 3854 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3855 for (ext = sect->section; ext->extent != NULL; ++ext) { 3856 if (sect->id == SECT_CONTEXT) 3857 count += 2 + ext->reg_count; 3858 else 3859 return 0; 3860 } 3861 } 3862 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3863 count += 4; 3864 /* end clear state */ 3865 count += 2; 3866 /* clear state */ 3867 count += 2; 3868 3869 return count; 3870 } 3871 3872 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 3873 { 3874 u32 count = 0; 3875 3876 if (adev->gfx.rlc.cs_data == NULL) 3877 return; 3878 if (buffer == NULL) 3879 return; 3880 3881 count = amdgpu_gfx_csb_preamble_start(buffer); 3882 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 3883 3884 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 3885 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3886 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 3887 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); 3888 3889 amdgpu_gfx_csb_preamble_end(buffer, count); 3890 } 3891 3892 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 3893 { 3894 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3895 AMD_PG_SUPPORT_GFX_SMG | 3896 AMD_PG_SUPPORT_GFX_DMG | 3897 AMD_PG_SUPPORT_CP | 3898 AMD_PG_SUPPORT_GDS | 3899 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3900 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 3901 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 3902 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3903 gfx_v7_0_init_gfx_cgpg(adev); 3904 gfx_v7_0_enable_cp_pg(adev, true); 3905 gfx_v7_0_enable_gds_pg(adev, true); 3906 } 3907 gfx_v7_0_init_ao_cu_mask(adev); 3908 gfx_v7_0_update_gfx_pg(adev, true); 3909 } 3910 } 3911 3912 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 3913 { 3914 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3915 AMD_PG_SUPPORT_GFX_SMG | 3916 AMD_PG_SUPPORT_GFX_DMG | 3917 AMD_PG_SUPPORT_CP | 3918 AMD_PG_SUPPORT_GDS | 3919 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3920 gfx_v7_0_update_gfx_pg(adev, false); 3921 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3922 gfx_v7_0_enable_cp_pg(adev, false); 3923 gfx_v7_0_enable_gds_pg(adev, false); 3924 } 3925 } 3926 } 3927 3928 /** 3929 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 3930 * 3931 * @adev: amdgpu_device pointer 3932 * 3933 * Fetches a GPU clock counter snapshot (SI). 3934 * Returns the 64 bit clock counter snapshot. 3935 */ 3936 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3937 { 3938 uint64_t clock; 3939 3940 mutex_lock(&adev->gfx.gpu_clock_mutex); 3941 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3942 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3943 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3944 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3945 return clock; 3946 } 3947 3948 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3949 uint32_t vmid, 3950 uint32_t gds_base, uint32_t gds_size, 3951 uint32_t gws_base, uint32_t gws_size, 3952 uint32_t oa_base, uint32_t oa_size) 3953 { 3954 /* GDS Base */ 3955 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3956 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3957 WRITE_DATA_DST_SEL(0))); 3958 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 3959 amdgpu_ring_write(ring, 0); 3960 amdgpu_ring_write(ring, gds_base); 3961 3962 /* GDS Size */ 3963 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3964 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3965 WRITE_DATA_DST_SEL(0))); 3966 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 3967 amdgpu_ring_write(ring, 0); 3968 amdgpu_ring_write(ring, gds_size); 3969 3970 /* GWS */ 3971 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3972 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3973 WRITE_DATA_DST_SEL(0))); 3974 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 3975 amdgpu_ring_write(ring, 0); 3976 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3977 3978 /* OA */ 3979 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3980 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3981 WRITE_DATA_DST_SEL(0))); 3982 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 3983 amdgpu_ring_write(ring, 0); 3984 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 3985 } 3986 3987 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 3988 { 3989 struct amdgpu_device *adev = ring->adev; 3990 uint32_t value = 0; 3991 3992 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3993 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3994 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3995 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3996 WREG32(mmSQ_CMD, value); 3997 } 3998 3999 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4000 { 4001 WREG32(mmSQ_IND_INDEX, 4002 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4003 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4004 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4005 (SQ_IND_INDEX__FORCE_READ_MASK)); 4006 return RREG32(mmSQ_IND_DATA); 4007 } 4008 4009 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4010 uint32_t wave, uint32_t thread, 4011 uint32_t regno, uint32_t num, uint32_t *out) 4012 { 4013 WREG32(mmSQ_IND_INDEX, 4014 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4015 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4016 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4017 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4018 (SQ_IND_INDEX__FORCE_READ_MASK) | 4019 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4020 while (num--) 4021 *(out++) = RREG32(mmSQ_IND_DATA); 4022 } 4023 4024 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4025 { 4026 /* type 0 wave data */ 4027 dst[(*no_fields)++] = 0; 4028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4031 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4032 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4033 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4034 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 4047 } 4048 4049 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4050 uint32_t wave, uint32_t start, 4051 uint32_t size, uint32_t *dst) 4052 { 4053 wave_read_regs( 4054 adev, simd, wave, 0, 4055 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4056 } 4057 4058 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, 4059 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4060 { 4061 cik_srbm_select(adev, me, pipe, q, vm); 4062 } 4063 4064 /** 4065 * gfx_v7_0_get_hdp_flush_mask - get the reference and mask for HDP flush 4066 * 4067 * @ring: amdgpu_ring structure holding ring information 4068 * @ref_and_mask: pointer to store the reference and mask 4069 * @reg_mem_engine: pointer to store the register memory engine 4070 * 4071 * Calculates the reference and mask for HDP flush based on the ring type and me. 4072 */ 4073 static void gfx_v7_0_get_hdp_flush_mask(struct amdgpu_ring *ring, 4074 uint32_t *ref_and_mask, uint32_t *reg_mem_engine) 4075 { 4076 if (!ring || !ref_and_mask || !reg_mem_engine) { 4077 DRM_INFO("%s:invalid params\n", __func__); 4078 return; 4079 } 4080 4081 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE || 4082 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 4083 switch (ring->me) { 4084 case 1: 4085 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 4086 break; 4087 case 2: 4088 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 4089 break; 4090 default: 4091 return; 4092 } 4093 *reg_mem_engine = 0; 4094 } else { 4095 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 4096 *reg_mem_engine = 1; 4097 } 4098 } 4099 4100 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4101 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4102 .select_se_sh = &gfx_v7_0_select_se_sh, 4103 .read_wave_data = &gfx_v7_0_read_wave_data, 4104 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4105 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q, 4106 .get_hdp_flush_mask = &gfx_v7_0_get_hdp_flush_mask, 4107 }; 4108 4109 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4110 .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, 4111 .set_safe_mode = gfx_v7_0_set_safe_mode, 4112 .unset_safe_mode = gfx_v7_0_unset_safe_mode, 4113 .init = gfx_v7_0_rlc_init, 4114 .get_csb_size = gfx_v7_0_get_csb_size, 4115 .get_csb_buffer = gfx_v7_0_get_csb_buffer, 4116 .get_cp_table_num = gfx_v7_0_cp_pg_table_num, 4117 .resume = gfx_v7_0_rlc_resume, 4118 .stop = gfx_v7_0_rlc_stop, 4119 .reset = gfx_v7_0_rlc_reset, 4120 .start = gfx_v7_0_rlc_start, 4121 .update_spm_vmid = gfx_v7_0_update_spm_vmid 4122 }; 4123 4124 static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block) 4125 { 4126 struct amdgpu_device *adev = ip_block->adev; 4127 4128 adev->gfx.xcc_mask = 1; 4129 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4130 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4131 AMDGPU_MAX_COMPUTE_RINGS); 4132 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4133 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4134 gfx_v7_0_set_ring_funcs(adev); 4135 gfx_v7_0_set_irq_funcs(adev); 4136 gfx_v7_0_set_gds_init(adev); 4137 4138 return 0; 4139 } 4140 4141 static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block) 4142 { 4143 struct amdgpu_device *adev = ip_block->adev; 4144 int r; 4145 4146 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4147 if (r) 4148 return r; 4149 4150 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4151 if (r) 4152 return r; 4153 4154 return 0; 4155 } 4156 4157 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4158 { 4159 u32 gb_addr_config; 4160 u32 mc_arb_ramcfg; 4161 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4162 u32 tmp; 4163 4164 switch (adev->asic_type) { 4165 case CHIP_BONAIRE: 4166 adev->gfx.config.max_shader_engines = 2; 4167 adev->gfx.config.max_tile_pipes = 4; 4168 adev->gfx.config.max_cu_per_sh = 7; 4169 adev->gfx.config.max_sh_per_se = 1; 4170 adev->gfx.config.max_backends_per_se = 2; 4171 adev->gfx.config.max_texture_channel_caches = 4; 4172 adev->gfx.config.max_gprs = 256; 4173 adev->gfx.config.max_gs_threads = 32; 4174 adev->gfx.config.max_hw_contexts = 8; 4175 4176 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4177 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4178 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4179 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4180 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4181 break; 4182 case CHIP_HAWAII: 4183 adev->gfx.config.max_shader_engines = 4; 4184 adev->gfx.config.max_tile_pipes = 16; 4185 adev->gfx.config.max_cu_per_sh = 11; 4186 adev->gfx.config.max_sh_per_se = 1; 4187 adev->gfx.config.max_backends_per_se = 4; 4188 adev->gfx.config.max_texture_channel_caches = 16; 4189 adev->gfx.config.max_gprs = 256; 4190 adev->gfx.config.max_gs_threads = 32; 4191 adev->gfx.config.max_hw_contexts = 8; 4192 4193 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4194 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4195 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4196 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4197 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4198 break; 4199 case CHIP_KAVERI: 4200 adev->gfx.config.max_shader_engines = 1; 4201 adev->gfx.config.max_tile_pipes = 4; 4202 adev->gfx.config.max_cu_per_sh = 8; 4203 adev->gfx.config.max_backends_per_se = 2; 4204 adev->gfx.config.max_sh_per_se = 1; 4205 adev->gfx.config.max_texture_channel_caches = 4; 4206 adev->gfx.config.max_gprs = 256; 4207 adev->gfx.config.max_gs_threads = 16; 4208 adev->gfx.config.max_hw_contexts = 8; 4209 4210 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4211 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4212 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4213 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4214 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4215 break; 4216 case CHIP_KABINI: 4217 case CHIP_MULLINS: 4218 default: 4219 adev->gfx.config.max_shader_engines = 1; 4220 adev->gfx.config.max_tile_pipes = 2; 4221 adev->gfx.config.max_cu_per_sh = 2; 4222 adev->gfx.config.max_sh_per_se = 1; 4223 adev->gfx.config.max_backends_per_se = 1; 4224 adev->gfx.config.max_texture_channel_caches = 2; 4225 adev->gfx.config.max_gprs = 256; 4226 adev->gfx.config.max_gs_threads = 16; 4227 adev->gfx.config.max_hw_contexts = 8; 4228 4229 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4230 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4231 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4232 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4233 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4234 break; 4235 } 4236 4237 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4238 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4239 4240 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, 4241 MC_ARB_RAMCFG, NOOFBANK); 4242 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, 4243 MC_ARB_RAMCFG, NOOFRANKS); 4244 4245 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4246 adev->gfx.config.mem_max_burst_length_bytes = 256; 4247 if (adev->flags & AMD_IS_APU) { 4248 /* Get memory bank mapping mode. */ 4249 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4250 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4251 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4252 4253 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4254 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4255 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4256 4257 /* Validate settings in case only one DIMM installed. */ 4258 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4259 dimm00_addr_map = 0; 4260 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4261 dimm01_addr_map = 0; 4262 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4263 dimm10_addr_map = 0; 4264 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4265 dimm11_addr_map = 0; 4266 4267 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4268 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4269 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4270 adev->gfx.config.mem_row_size_in_kb = 2; 4271 else 4272 adev->gfx.config.mem_row_size_in_kb = 1; 4273 } else { 4274 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4275 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4276 if (adev->gfx.config.mem_row_size_in_kb > 4) 4277 adev->gfx.config.mem_row_size_in_kb = 4; 4278 } 4279 /* XXX use MC settings? */ 4280 adev->gfx.config.shader_engine_tile_size = 32; 4281 adev->gfx.config.num_gpus = 1; 4282 adev->gfx.config.multi_gpu_tile_size = 64; 4283 4284 /* fix up row size */ 4285 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4286 switch (adev->gfx.config.mem_row_size_in_kb) { 4287 case 1: 4288 default: 4289 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4290 break; 4291 case 2: 4292 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4293 break; 4294 case 4: 4295 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4296 break; 4297 } 4298 adev->gfx.config.gb_addr_config = gb_addr_config; 4299 } 4300 4301 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4302 int mec, int pipe, int queue) 4303 { 4304 int r; 4305 unsigned irq_type; 4306 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4307 4308 /* mec0 is me1 */ 4309 ring->me = mec + 1; 4310 ring->pipe = pipe; 4311 ring->queue = queue; 4312 4313 ring->ring_obj = NULL; 4314 ring->use_doorbell = true; 4315 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 4316 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4317 4318 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4319 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4320 + ring->pipe; 4321 4322 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4323 r = amdgpu_ring_init(adev, ring, 1024, 4324 &adev->gfx.eop_irq, irq_type, 4325 AMDGPU_RING_PRIO_DEFAULT, NULL); 4326 if (r) 4327 return r; 4328 4329 4330 return 0; 4331 } 4332 4333 static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 4334 { 4335 struct amdgpu_ring *ring; 4336 struct amdgpu_device *adev = ip_block->adev; 4337 int i, j, k, r, ring_id; 4338 4339 switch (adev->asic_type) { 4340 case CHIP_KAVERI: 4341 adev->gfx.mec.num_mec = 2; 4342 break; 4343 case CHIP_BONAIRE: 4344 case CHIP_HAWAII: 4345 case CHIP_KABINI: 4346 case CHIP_MULLINS: 4347 default: 4348 adev->gfx.mec.num_mec = 1; 4349 break; 4350 } 4351 adev->gfx.mec.num_pipe_per_mec = 4; 4352 adev->gfx.mec.num_queue_per_pipe = 8; 4353 4354 /* EOP Event */ 4355 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4356 if (r) 4357 return r; 4358 4359 /* Privileged reg */ 4360 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, 4361 &adev->gfx.priv_reg_irq); 4362 if (r) 4363 return r; 4364 4365 /* Privileged inst */ 4366 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, 4367 &adev->gfx.priv_inst_irq); 4368 if (r) 4369 return r; 4370 4371 r = gfx_v7_0_init_microcode(adev); 4372 if (r) { 4373 DRM_ERROR("Failed to load gfx firmware!\n"); 4374 return r; 4375 } 4376 4377 r = adev->gfx.rlc.funcs->init(adev); 4378 if (r) { 4379 DRM_ERROR("Failed to init rlc BOs!\n"); 4380 return r; 4381 } 4382 4383 /* allocate mec buffers */ 4384 r = gfx_v7_0_mec_init(adev); 4385 if (r) { 4386 DRM_ERROR("Failed to init MEC BOs!\n"); 4387 return r; 4388 } 4389 4390 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4391 ring = &adev->gfx.gfx_ring[i]; 4392 ring->ring_obj = NULL; 4393 sprintf(ring->name, "gfx"); 4394 r = amdgpu_ring_init(adev, ring, 1024, 4395 &adev->gfx.eop_irq, 4396 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 4397 AMDGPU_RING_PRIO_DEFAULT, NULL); 4398 if (r) 4399 return r; 4400 } 4401 4402 /* set up the compute queues - allocate horizontally across pipes */ 4403 ring_id = 0; 4404 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4405 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4406 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4407 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4408 k, j)) 4409 continue; 4410 4411 r = gfx_v7_0_compute_ring_init(adev, 4412 ring_id, 4413 i, k, j); 4414 if (r) 4415 return r; 4416 4417 ring_id++; 4418 } 4419 } 4420 } 4421 4422 /* create MQD for all compute queues */ 4423 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct cik_mqd), 0); 4424 if (r) 4425 return r; 4426 4427 adev->gfx.ce_ram_size = 0x8000; 4428 4429 gfx_v7_0_gpu_early_init(adev); 4430 4431 adev->gfx.gfx_supported_reset = 4432 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4433 adev->gfx.compute_supported_reset = 4434 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4435 4436 if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_ip_block_soft_reset) { 4437 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 4438 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 4439 } 4440 4441 return r; 4442 } 4443 4444 static int gfx_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 4445 { 4446 struct amdgpu_device *adev = ip_block->adev; 4447 int i; 4448 4449 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4450 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4451 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4452 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4453 4454 amdgpu_gfx_mqd_sw_fini(adev, 0); 4455 amdgpu_gfx_rlc_fini(adev); 4456 gfx_v7_0_mec_fini(adev); 4457 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4458 &adev->gfx.rlc.clear_state_gpu_addr, 4459 (void **)&adev->gfx.rlc.cs_ptr); 4460 if (adev->gfx.rlc.cp_table_size) { 4461 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4462 &adev->gfx.rlc.cp_table_gpu_addr, 4463 (void **)&adev->gfx.rlc.cp_table_ptr); 4464 } 4465 gfx_v7_0_free_microcode(adev); 4466 4467 return 0; 4468 } 4469 4470 static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 4471 { 4472 int r; 4473 struct amdgpu_device *adev = ip_block->adev; 4474 4475 gfx_v7_0_constants_init(adev); 4476 4477 /* init CSB */ 4478 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4479 /* init rlc */ 4480 r = adev->gfx.rlc.funcs->resume(adev); 4481 if (r) 4482 return r; 4483 4484 r = gfx_v7_0_cp_resume(adev); 4485 if (r) 4486 return r; 4487 4488 return r; 4489 } 4490 4491 static int gfx_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 4492 { 4493 struct amdgpu_device *adev = ip_block->adev; 4494 4495 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4496 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4497 gfx_v7_0_cp_enable(adev, false); 4498 adev->gfx.rlc.funcs->stop(adev); 4499 gfx_v7_0_fini_pg(adev); 4500 4501 return 0; 4502 } 4503 4504 static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block) 4505 { 4506 return gfx_v7_0_hw_fini(ip_block); 4507 } 4508 4509 static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block) 4510 { 4511 return gfx_v7_0_hw_init(ip_block); 4512 } 4513 4514 static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 4515 { 4516 struct amdgpu_device *adev = ip_block->adev; 4517 4518 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4519 return false; 4520 else 4521 return true; 4522 } 4523 4524 static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4525 { 4526 unsigned i; 4527 u32 tmp; 4528 struct amdgpu_device *adev = ip_block->adev; 4529 4530 for (i = 0; i < adev->usec_timeout; i++) { 4531 /* read MC_STATUS */ 4532 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4533 4534 if (!tmp) 4535 return 0; 4536 udelay(1); 4537 } 4538 return -ETIMEDOUT; 4539 } 4540 4541 static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 4542 { 4543 struct amdgpu_device *adev = ip_block->adev; 4544 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4545 u32 tmp; 4546 int i; 4547 int r; 4548 4549 grbm_soft_reset = 4550 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1) | 4551 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1) | 4552 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CP, 1) | 4553 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPF, 1) | 4554 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPC, 1) | 4555 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPG, 1); 4556 4557 srbm_soft_reset = 4558 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1) | 4559 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 4560 4561 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4562 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 4563 4564 mutex_lock(&adev->srbm_mutex); 4565 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4566 gfx_v7_0_deactivate_hqd(adev, 2); 4567 cik_srbm_select(adev, 0, 0, 0, 0); 4568 mutex_unlock(&adev->srbm_mutex); 4569 4570 udelay(50); 4571 } 4572 4573 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 4574 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 4575 ip_block->version->funcs->suspend(ip_block); 4576 4577 if (grbm_soft_reset || srbm_soft_reset) { 4578 tmp = RREG32(mmGMCON_DEBUG); 4579 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1); 4580 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1); 4581 WREG32(mmGMCON_DEBUG, tmp); 4582 4583 udelay(100); 4584 } 4585 4586 if (grbm_soft_reset) { 4587 tmp = RREG32(mmGRBM_SOFT_RESET); 4588 tmp |= grbm_soft_reset; 4589 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4590 WREG32(mmGRBM_SOFT_RESET, tmp); 4591 tmp = RREG32(mmGRBM_SOFT_RESET); 4592 4593 udelay(100); 4594 4595 tmp &= ~grbm_soft_reset; 4596 WREG32(mmGRBM_SOFT_RESET, tmp); 4597 tmp = RREG32(mmGRBM_SOFT_RESET); 4598 4599 udelay(100); 4600 } 4601 4602 if (srbm_soft_reset) { 4603 tmp = RREG32(mmSRBM_SOFT_RESET); 4604 tmp |= srbm_soft_reset; 4605 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4606 WREG32(mmSRBM_SOFT_RESET, tmp); 4607 tmp = RREG32(mmSRBM_SOFT_RESET); 4608 4609 udelay(100); 4610 4611 tmp &= ~srbm_soft_reset; 4612 WREG32(mmSRBM_SOFT_RESET, tmp); 4613 tmp = RREG32(mmSRBM_SOFT_RESET); 4614 4615 udelay(100); 4616 } 4617 4618 if (grbm_soft_reset || srbm_soft_reset) { 4619 tmp = RREG32(mmGMCON_DEBUG); 4620 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); 4621 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); 4622 WREG32(mmGMCON_DEBUG, tmp); 4623 } 4624 4625 /* Wait a little for things to settle down */ 4626 udelay(100); 4627 4628 r = ip_block->version->funcs->resume(ip_block); 4629 r |= ip_block->version->funcs->late_init(ip_block); 4630 if (r) 4631 return r; 4632 4633 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_GATE); 4634 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_GATE); 4635 4636 return 0; 4637 } 4638 4639 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4640 enum amdgpu_interrupt_state state) 4641 { 4642 u32 cp_int_cntl; 4643 4644 switch (state) { 4645 case AMDGPU_IRQ_STATE_DISABLE: 4646 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4647 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4648 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4649 break; 4650 case AMDGPU_IRQ_STATE_ENABLE: 4651 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4652 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4653 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4654 break; 4655 default: 4656 break; 4657 } 4658 } 4659 4660 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4661 int me, int pipe, 4662 enum amdgpu_interrupt_state state) 4663 { 4664 u32 mec_int_cntl, mec_int_cntl_reg; 4665 4666 /* 4667 * amdgpu controls only the first MEC. That's why this function only 4668 * handles the setting of interrupts for this specific MEC. All other 4669 * pipes' interrupts are set by amdkfd. 4670 */ 4671 4672 if (me == 1) { 4673 switch (pipe) { 4674 case 0: 4675 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4676 break; 4677 case 1: 4678 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4679 break; 4680 case 2: 4681 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4682 break; 4683 case 3: 4684 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4685 break; 4686 default: 4687 DRM_DEBUG("invalid pipe %d\n", pipe); 4688 return; 4689 } 4690 } else { 4691 DRM_DEBUG("invalid me %d\n", me); 4692 return; 4693 } 4694 4695 switch (state) { 4696 case AMDGPU_IRQ_STATE_DISABLE: 4697 mec_int_cntl = RREG32(mec_int_cntl_reg); 4698 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4699 WREG32(mec_int_cntl_reg, mec_int_cntl); 4700 break; 4701 case AMDGPU_IRQ_STATE_ENABLE: 4702 mec_int_cntl = RREG32(mec_int_cntl_reg); 4703 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4704 WREG32(mec_int_cntl_reg, mec_int_cntl); 4705 break; 4706 default: 4707 break; 4708 } 4709 } 4710 4711 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4712 struct amdgpu_irq_src *src, 4713 unsigned type, 4714 enum amdgpu_interrupt_state state) 4715 { 4716 u32 cp_int_cntl; 4717 4718 switch (state) { 4719 case AMDGPU_IRQ_STATE_DISABLE: 4720 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4721 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4722 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4723 break; 4724 case AMDGPU_IRQ_STATE_ENABLE: 4725 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4726 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4727 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4728 break; 4729 default: 4730 break; 4731 } 4732 4733 return 0; 4734 } 4735 4736 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4737 struct amdgpu_irq_src *src, 4738 unsigned type, 4739 enum amdgpu_interrupt_state state) 4740 { 4741 u32 cp_int_cntl; 4742 4743 switch (state) { 4744 case AMDGPU_IRQ_STATE_DISABLE: 4745 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4746 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4747 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4748 break; 4749 case AMDGPU_IRQ_STATE_ENABLE: 4750 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4751 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4752 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4753 break; 4754 default: 4755 break; 4756 } 4757 4758 return 0; 4759 } 4760 4761 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4762 struct amdgpu_irq_src *src, 4763 unsigned type, 4764 enum amdgpu_interrupt_state state) 4765 { 4766 switch (type) { 4767 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4768 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4769 break; 4770 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4771 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4772 break; 4773 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4774 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4775 break; 4776 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4777 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4778 break; 4779 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4780 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4781 break; 4782 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4783 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4784 break; 4785 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4786 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4787 break; 4788 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4789 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4790 break; 4791 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4792 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4793 break; 4794 default: 4795 break; 4796 } 4797 return 0; 4798 } 4799 4800 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4801 struct amdgpu_irq_src *source, 4802 struct amdgpu_iv_entry *entry) 4803 { 4804 u8 me_id, pipe_id; 4805 struct amdgpu_ring *ring; 4806 int i; 4807 4808 DRM_DEBUG("IH: CP EOP\n"); 4809 me_id = (entry->ring_id & 0x0c) >> 2; 4810 pipe_id = (entry->ring_id & 0x03) >> 0; 4811 switch (me_id) { 4812 case 0: 4813 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4814 break; 4815 case 1: 4816 case 2: 4817 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4818 ring = &adev->gfx.compute_ring[i]; 4819 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4820 amdgpu_fence_process(ring); 4821 } 4822 break; 4823 } 4824 return 0; 4825 } 4826 4827 static void gfx_v7_0_fault(struct amdgpu_device *adev, 4828 struct amdgpu_iv_entry *entry) 4829 { 4830 struct amdgpu_ring *ring; 4831 u8 me_id, pipe_id; 4832 int i; 4833 4834 me_id = (entry->ring_id & 0x0c) >> 2; 4835 pipe_id = (entry->ring_id & 0x03) >> 0; 4836 switch (me_id) { 4837 case 0: 4838 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4839 break; 4840 case 1: 4841 case 2: 4842 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4843 ring = &adev->gfx.compute_ring[i]; 4844 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4845 drm_sched_fault(&ring->sched); 4846 } 4847 break; 4848 } 4849 } 4850 4851 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 4852 struct amdgpu_irq_src *source, 4853 struct amdgpu_iv_entry *entry) 4854 { 4855 DRM_ERROR("Illegal register access in command stream\n"); 4856 gfx_v7_0_fault(adev, entry); 4857 return 0; 4858 } 4859 4860 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 4861 struct amdgpu_irq_src *source, 4862 struct amdgpu_iv_entry *entry) 4863 { 4864 DRM_ERROR("Illegal instruction in command stream\n"); 4865 // XXX soft reset the gfx block only 4866 gfx_v7_0_fault(adev, entry); 4867 return 0; 4868 } 4869 4870 static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4871 enum amd_clockgating_state state) 4872 { 4873 bool gate = false; 4874 struct amdgpu_device *adev = ip_block->adev; 4875 4876 if (state == AMD_CG_STATE_GATE) 4877 gate = true; 4878 4879 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 4880 /* order matters! */ 4881 if (gate) { 4882 gfx_v7_0_enable_mgcg(adev, true); 4883 gfx_v7_0_enable_cgcg(adev, true); 4884 } else { 4885 gfx_v7_0_enable_cgcg(adev, false); 4886 gfx_v7_0_enable_mgcg(adev, false); 4887 } 4888 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4889 4890 return 0; 4891 } 4892 4893 static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4894 enum amd_powergating_state state) 4895 { 4896 bool gate = false; 4897 struct amdgpu_device *adev = ip_block->adev; 4898 4899 if (state == AMD_PG_STATE_GATE) 4900 gate = true; 4901 4902 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4903 AMD_PG_SUPPORT_GFX_SMG | 4904 AMD_PG_SUPPORT_GFX_DMG | 4905 AMD_PG_SUPPORT_CP | 4906 AMD_PG_SUPPORT_GDS | 4907 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4908 gfx_v7_0_update_gfx_pg(adev, gate); 4909 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4910 gfx_v7_0_enable_cp_pg(adev, gate); 4911 gfx_v7_0_enable_gds_pg(adev, gate); 4912 } 4913 } 4914 4915 return 0; 4916 } 4917 4918 static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring) 4919 { 4920 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 4921 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4922 PACKET3_TC_ACTION_ENA | 4923 PACKET3_SH_KCACHE_ACTION_ENA | 4924 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4925 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4926 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4927 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4928 } 4929 4930 static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring) 4931 { 4932 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 4933 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4934 PACKET3_TC_ACTION_ENA | 4935 PACKET3_SH_KCACHE_ACTION_ENA | 4936 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4937 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4938 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ 4939 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4940 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 4941 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4942 } 4943 4944 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 4945 .name = "gfx_v7_0", 4946 .early_init = gfx_v7_0_early_init, 4947 .late_init = gfx_v7_0_late_init, 4948 .sw_init = gfx_v7_0_sw_init, 4949 .sw_fini = gfx_v7_0_sw_fini, 4950 .hw_init = gfx_v7_0_hw_init, 4951 .hw_fini = gfx_v7_0_hw_fini, 4952 .suspend = gfx_v7_0_suspend, 4953 .resume = gfx_v7_0_resume, 4954 .is_idle = gfx_v7_0_is_idle, 4955 .wait_for_idle = gfx_v7_0_wait_for_idle, 4956 .soft_reset = gfx_v7_0_soft_reset, 4957 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 4958 .set_powergating_state = gfx_v7_0_set_powergating_state, 4959 }; 4960 4961 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 4962 .type = AMDGPU_RING_TYPE_GFX, 4963 .align_mask = 0xff, 4964 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4965 .support_64bit_ptrs = false, 4966 .get_rptr = gfx_v7_0_ring_get_rptr, 4967 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 4968 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 4969 .emit_frame_size = 4970 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 4971 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 4972 20 + /* gfx_v7_0_ring_emit_gds_switch */ 4973 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 4974 5 + /* hdp invalidate */ 4975 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 4976 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 4977 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 2 + /* gfx_v7_0_ring_emit_vm_flush */ 4978 3 * 2 + /* gfx_v7_0_ring_emit_sb x3 (from amdgpu_vm_flush, amdgpu_ib_schedule) */ 4979 3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 4980 5, /* SURFACE_SYNC */ 4981 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 4982 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 4983 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 4984 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 4985 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 4986 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 4987 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 4988 .test_ring = gfx_v7_0_ring_test_ring, 4989 .test_ib = gfx_v7_0_ring_test_ib, 4990 .insert_nop = amdgpu_ring_insert_nop, 4991 .pad_ib = amdgpu_ring_generic_pad_ib, 4992 .emit_switch_buffer = gfx_v7_0_ring_emit_sb, 4993 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 4994 .init_cond_exec = gfx_v7_0_ring_emit_init_cond_exec, 4995 .emit_wreg = gfx_v7_0_ring_emit_wreg, 4996 .soft_recovery = gfx_v7_0_ring_soft_recovery, 4997 .emit_mem_sync = gfx_v7_0_emit_mem_sync, 4998 }; 4999 5000 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5001 .type = AMDGPU_RING_TYPE_COMPUTE, 5002 .align_mask = 0xff, 5003 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5004 .support_64bit_ptrs = false, 5005 .get_rptr = gfx_v7_0_ring_get_rptr, 5006 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5007 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5008 .emit_frame_size = 5009 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 5010 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 5011 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5012 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5013 5 + /* hdp invalidate */ 5014 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5015 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ 5016 7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5017 7, /* gfx_v7_0_emit_mem_sync_compute */ 5018 .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */ 5019 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5020 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5021 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5022 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5023 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5024 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5025 .test_ring = gfx_v7_0_ring_test_ring, 5026 .test_ib = gfx_v7_0_ring_test_ib, 5027 .insert_nop = amdgpu_ring_insert_nop, 5028 .pad_ib = amdgpu_ring_generic_pad_ib, 5029 .init_cond_exec = gfx_v7_0_ring_emit_init_cond_exec, 5030 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5031 .soft_recovery = gfx_v7_0_ring_soft_recovery, 5032 .emit_mem_sync = gfx_v7_0_emit_mem_sync_compute, 5033 }; 5034 5035 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5036 { 5037 int i; 5038 5039 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5040 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5041 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5042 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5043 } 5044 5045 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5046 .set = gfx_v7_0_set_eop_interrupt_state, 5047 .process = gfx_v7_0_eop_irq, 5048 }; 5049 5050 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5051 .set = gfx_v7_0_set_priv_reg_fault_state, 5052 .process = gfx_v7_0_priv_reg_irq, 5053 }; 5054 5055 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5056 .set = gfx_v7_0_set_priv_inst_fault_state, 5057 .process = gfx_v7_0_priv_inst_irq, 5058 }; 5059 5060 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5061 { 5062 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5063 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5064 5065 adev->gfx.priv_reg_irq.num_types = 1; 5066 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5067 5068 adev->gfx.priv_inst_irq.num_types = 1; 5069 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5070 } 5071 5072 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5073 { 5074 /* init asci gds info */ 5075 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 5076 adev->gds.gws_size = 64; 5077 adev->gds.oa_size = 16; 5078 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 5079 } 5080 5081 5082 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5083 { 5084 int i, j, k, counter, active_cu_number = 0; 5085 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5086 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5087 unsigned disable_masks[4 * 2]; 5088 u32 ao_cu_num; 5089 5090 if (adev->flags & AMD_IS_APU) 5091 ao_cu_num = 2; 5092 else 5093 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5094 5095 memset(cu_info, 0, sizeof(*cu_info)); 5096 5097 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 5098 5099 mutex_lock(&adev->grbm_idx_mutex); 5100 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5101 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5102 mask = 1; 5103 ao_bitmap = 0; 5104 counter = 0; 5105 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5106 if (i < 4 && j < 2) 5107 gfx_v7_0_set_user_cu_inactive_bitmap( 5108 adev, disable_masks[i * 2 + j]); 5109 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5110 cu_info->bitmap[0][i][j] = bitmap; 5111 5112 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5113 if (bitmap & mask) { 5114 if (counter < ao_cu_num) 5115 ao_bitmap |= mask; 5116 counter++; 5117 } 5118 mask <<= 1; 5119 } 5120 active_cu_number += counter; 5121 if (i < 2 && j < 2) 5122 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5123 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5124 } 5125 } 5126 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5127 mutex_unlock(&adev->grbm_idx_mutex); 5128 5129 cu_info->number = active_cu_number; 5130 cu_info->ao_cu_mask = ao_cu_mask; 5131 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5132 cu_info->max_waves_per_simd = 10; 5133 cu_info->max_scratch_slots_per_cu = 32; 5134 cu_info->wave_front_size = 64; 5135 cu_info->lds_size = 64; 5136 } 5137 5138 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = { 5139 .type = AMD_IP_BLOCK_TYPE_GFX, 5140 .major = 7, 5141 .minor = 1, 5142 .rev = 0, 5143 .funcs = &gfx_v7_0_ip_funcs, 5144 }; 5145 5146 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = { 5147 .type = AMD_IP_BLOCK_TYPE_GFX, 5148 .major = 7, 5149 .minor = 2, 5150 .rev = 0, 5151 .funcs = &gfx_v7_0_ip_funcs, 5152 }; 5153 5154 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = { 5155 .type = AMD_IP_BLOCK_TYPE_GFX, 5156 .major = 7, 5157 .minor = 3, 5158 .rev = 0, 5159 .funcs = &gfx_v7_0_ip_funcs, 5160 }; 5161