1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "bif/bif_3_0_d.h" 32 #include "bif/bif_3_0_sh_mask.h" 33 #include "oss/oss_1_0_d.h" 34 #include "oss/oss_1_0_sh_mask.h" 35 #include "gca/gfx_6_0_d.h" 36 #include "gca/gfx_6_0_sh_mask.h" 37 #include "gmc/gmc_6_0_d.h" 38 #include "gmc/gmc_6_0_sh_mask.h" 39 #include "dce/dce_6_0_d.h" 40 #include "dce/dce_6_0_sh_mask.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "si_enums.h" 43 #include "si.h" 44 45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 48 49 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 50 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 51 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 52 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 53 54 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 56 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 57 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 58 59 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 60 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 61 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 63 64 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 66 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 71 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 72 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 73 74 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 75 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 76 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 77 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 78 79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 80 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 82 #define MICRO_TILE_MODE(x) ((x) << 0) 83 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 84 #define BANK_WIDTH(x) ((x) << 14) 85 #define BANK_HEIGHT(x) ((x) << 16) 86 #define MACRO_TILE_ASPECT(x) ((x) << 18) 87 #define NUM_BANKS(x) ((x) << 20) 88 89 static const u32 verde_rlc_save_restore_register_list[] = 90 { 91 (0x8000 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8040 << 16) | (0x98f4 >> 2), 94 0x00000000, 95 (0x8000 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8040 << 16) | (0xe80 >> 2), 98 0x00000000, 99 (0x8000 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8040 << 16) | (0x89bc >> 2), 102 0x00000000, 103 (0x8000 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x8040 << 16) | (0x8c1c >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0x98f0 >> 2), 108 0x00000000, 109 (0x9c00 << 16) | (0xe7c >> 2), 110 0x00000000, 111 (0x8000 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x8040 << 16) | (0x9148 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x9150 >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x897c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0x8d8c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0xac54 >> 2), 122 0X00000000, 123 0x3, 124 (0x9c00 << 16) | (0x98f8 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9910 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9914 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x9918 >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x991c >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9920 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9924 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x9928 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x992c >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9930 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9934 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x9938 >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x993c >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9940 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9944 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x9948 >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x994c >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9950 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9954 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x9958 >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x995c >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9960 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9964 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x9968 >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x996c >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9970 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9974 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x9978 >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x997c >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9980 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9984 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x9988 >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x998c >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c00 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c14 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c04 >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x8c08 >> 2), 197 0x00000000, 198 (0x8000 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8040 << 16) | (0x9b7c >> 2), 201 0x00000000, 202 (0x8000 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8040 << 16) | (0xe84 >> 2), 205 0x00000000, 206 (0x8000 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8040 << 16) | (0x89c0 >> 2), 209 0x00000000, 210 (0x8000 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8040 << 16) | (0x914c >> 2), 213 0x00000000, 214 (0x8000 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8040 << 16) | (0x8c20 >> 2), 217 0x00000000, 218 (0x8000 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x8040 << 16) | (0x9354 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9060 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9364 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x9100 >> 2), 227 0x00000000, 228 (0x9c00 << 16) | (0x913c >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e0 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e4 >> 2), 233 0x00000000, 234 (0x8000 << 16) | (0x90e8 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e0 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e4 >> 2), 239 0x00000000, 240 (0x8040 << 16) | (0x90e8 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8bcc >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x8b24 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x88c4 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8e50 >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8c0c >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e58 >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x8e5c >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x9508 >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x950c >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x9494 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac0c >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac10 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xac14 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xae00 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0xac08 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88d4 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88c8 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x88cc >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x89b0 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8b10 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x8a14 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9830 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9834 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9838 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x9a10 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9870 >> 2), 293 0x00000000, 294 (0x8000 << 16) | (0x9874 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9870 >> 2), 297 0x00000000, 298 (0x8001 << 16) | (0x9874 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9870 >> 2), 301 0x00000000, 302 (0x8040 << 16) | (0x9874 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9870 >> 2), 305 0x00000000, 306 (0x8041 << 16) | (0x9874 >> 2), 307 0x00000000, 308 0x00000000 309 }; 310 311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 312 { 313 const char *chip_name; 314 int err; 315 const struct gfx_firmware_header_v1_0 *cp_hdr; 316 const struct rlc_firmware_header_v1_0 *rlc_hdr; 317 318 DRM_DEBUG("\n"); 319 320 switch (adev->asic_type) { 321 case CHIP_TAHITI: 322 chip_name = "tahiti"; 323 break; 324 case CHIP_PITCAIRN: 325 chip_name = "pitcairn"; 326 break; 327 case CHIP_VERDE: 328 chip_name = "verde"; 329 break; 330 case CHIP_OLAND: 331 chip_name = "oland"; 332 break; 333 case CHIP_HAINAN: 334 chip_name = "hainan"; 335 break; 336 default: BUG(); 337 } 338 339 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 340 AMDGPU_UCODE_REQUIRED, 341 "amdgpu/%s_pfp.bin", chip_name); 342 if (err) 343 goto out; 344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 347 348 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 349 AMDGPU_UCODE_REQUIRED, 350 "amdgpu/%s_me.bin", chip_name); 351 if (err) 352 goto out; 353 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 354 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 355 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 356 357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 358 AMDGPU_UCODE_REQUIRED, 359 "amdgpu/%s_ce.bin", chip_name); 360 if (err) 361 goto out; 362 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 363 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 364 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 365 366 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 367 AMDGPU_UCODE_REQUIRED, 368 "amdgpu/%s_rlc.bin", chip_name); 369 if (err) 370 goto out; 371 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 372 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 373 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 374 375 out: 376 if (err) { 377 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); 378 amdgpu_ucode_release(&adev->gfx.pfp_fw); 379 amdgpu_ucode_release(&adev->gfx.me_fw); 380 amdgpu_ucode_release(&adev->gfx.ce_fw); 381 amdgpu_ucode_release(&adev->gfx.rlc_fw); 382 } 383 return err; 384 } 385 386 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 387 { 388 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 389 u32 reg_offset, split_equal_to_row_size, *tilemode; 390 391 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 392 tilemode = adev->gfx.config.tile_mode_array; 393 394 switch (adev->gfx.config.mem_row_size_in_kb) { 395 case 1: 396 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 397 break; 398 case 2: 399 default: 400 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 401 break; 402 case 4: 403 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 404 break; 405 } 406 407 if (adev->asic_type == CHIP_VERDE) { 408 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 409 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 410 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 412 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 413 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 414 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 415 NUM_BANKS(ADDR_SURF_16_BANK); 416 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 418 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 423 NUM_BANKS(ADDR_SURF_16_BANK); 424 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 426 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 431 NUM_BANKS(ADDR_SURF_16_BANK); 432 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 434 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 438 NUM_BANKS(ADDR_SURF_8_BANK) | 439 TILE_SPLIT(split_equal_to_row_size); 440 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 441 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 442 PIPE_CONFIG(ADDR_SURF_P4_8x16); 443 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 444 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 445 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 446 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 447 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 448 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 449 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 450 NUM_BANKS(ADDR_SURF_4_BANK); 451 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 453 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 458 NUM_BANKS(ADDR_SURF_4_BANK); 459 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 461 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 466 NUM_BANKS(ADDR_SURF_2_BANK); 467 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 468 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 469 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 470 PIPE_CONFIG(ADDR_SURF_P4_8x16); 471 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 472 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 473 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 474 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 475 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 478 NUM_BANKS(ADDR_SURF_16_BANK); 479 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 481 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 486 NUM_BANKS(ADDR_SURF_16_BANK); 487 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 489 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 494 NUM_BANKS(ADDR_SURF_16_BANK); 495 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 496 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 497 PIPE_CONFIG(ADDR_SURF_P4_8x16); 498 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 499 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 500 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 502 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 505 NUM_BANKS(ADDR_SURF_16_BANK); 506 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 507 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 508 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 513 NUM_BANKS(ADDR_SURF_16_BANK); 514 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 516 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 521 NUM_BANKS(ADDR_SURF_16_BANK); 522 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 524 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 528 NUM_BANKS(ADDR_SURF_16_BANK) | 529 TILE_SPLIT(split_equal_to_row_size); 530 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 531 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16); 533 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 534 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 535 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 536 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 539 NUM_BANKS(ADDR_SURF_16_BANK) | 540 TILE_SPLIT(split_equal_to_row_size); 541 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 542 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 543 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 544 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 547 NUM_BANKS(ADDR_SURF_16_BANK) | 548 TILE_SPLIT(split_equal_to_row_size); 549 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 550 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 551 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 552 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 556 NUM_BANKS(ADDR_SURF_8_BANK); 557 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 558 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 559 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 560 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 564 NUM_BANKS(ADDR_SURF_8_BANK); 565 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 567 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 572 NUM_BANKS(ADDR_SURF_4_BANK); 573 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 575 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 580 NUM_BANKS(ADDR_SURF_4_BANK); 581 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 583 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 588 NUM_BANKS(ADDR_SURF_2_BANK); 589 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 591 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 596 NUM_BANKS(ADDR_SURF_2_BANK); 597 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 599 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 604 NUM_BANKS(ADDR_SURF_2_BANK); 605 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 607 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 612 NUM_BANKS(ADDR_SURF_2_BANK); 613 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 615 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 620 NUM_BANKS(ADDR_SURF_2_BANK); 621 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 623 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 628 NUM_BANKS(ADDR_SURF_2_BANK); 629 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 630 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 631 } else if (adev->asic_type == CHIP_OLAND) { 632 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 633 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 634 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 635 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 636 NUM_BANKS(ADDR_SURF_16_BANK) | 637 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 638 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 639 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 640 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 641 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 642 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 644 NUM_BANKS(ADDR_SURF_16_BANK) | 645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 648 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 650 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 652 NUM_BANKS(ADDR_SURF_16_BANK) | 653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 656 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 658 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 660 NUM_BANKS(ADDR_SURF_16_BANK) | 661 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 662 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 663 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 664 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 665 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 666 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 667 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 668 NUM_BANKS(ADDR_SURF_16_BANK) | 669 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 672 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 673 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 674 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 675 TILE_SPLIT(split_equal_to_row_size) | 676 NUM_BANKS(ADDR_SURF_16_BANK) | 677 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 678 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 680 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 681 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 682 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 683 TILE_SPLIT(split_equal_to_row_size) | 684 NUM_BANKS(ADDR_SURF_16_BANK) | 685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 688 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 689 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 690 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 691 TILE_SPLIT(split_equal_to_row_size) | 692 NUM_BANKS(ADDR_SURF_16_BANK) | 693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 696 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 697 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 698 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 699 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 700 NUM_BANKS(ADDR_SURF_16_BANK) | 701 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 702 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 703 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 704 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 705 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 706 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 708 NUM_BANKS(ADDR_SURF_16_BANK) | 709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 712 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 713 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 714 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 716 NUM_BANKS(ADDR_SURF_16_BANK) | 717 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 718 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 719 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 720 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 721 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 722 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 724 NUM_BANKS(ADDR_SURF_16_BANK) | 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 728 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 729 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 730 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 732 NUM_BANKS(ADDR_SURF_16_BANK) | 733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 736 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 737 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 738 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 739 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 740 NUM_BANKS(ADDR_SURF_16_BANK) | 741 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 742 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 743 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 744 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 745 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 746 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 747 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 748 NUM_BANKS(ADDR_SURF_16_BANK) | 749 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 750 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 751 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 752 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 753 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 754 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 755 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 756 NUM_BANKS(ADDR_SURF_16_BANK) | 757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 760 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 761 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 762 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 764 NUM_BANKS(ADDR_SURF_16_BANK) | 765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 768 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 769 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 770 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 771 TILE_SPLIT(split_equal_to_row_size) | 772 NUM_BANKS(ADDR_SURF_16_BANK) | 773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 776 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 777 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 778 PIPE_CONFIG(ADDR_SURF_P4_8x16); 779 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 780 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 781 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 785 NUM_BANKS(ADDR_SURF_16_BANK) | 786 TILE_SPLIT(split_equal_to_row_size); 787 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 788 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 789 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 793 NUM_BANKS(ADDR_SURF_16_BANK) | 794 TILE_SPLIT(split_equal_to_row_size); 795 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 796 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 797 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 798 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 799 NUM_BANKS(ADDR_SURF_16_BANK) | 800 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 801 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 802 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 803 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 804 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 805 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 806 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 807 NUM_BANKS(ADDR_SURF_16_BANK) | 808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 811 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 812 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 813 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 814 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 815 NUM_BANKS(ADDR_SURF_16_BANK) | 816 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 819 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 820 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 821 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 822 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 823 NUM_BANKS(ADDR_SURF_16_BANK) | 824 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 825 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 826 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 827 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 828 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 829 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 831 NUM_BANKS(ADDR_SURF_8_BANK) | 832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 835 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 836 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 837 } else if (adev->asic_type == CHIP_HAINAN) { 838 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 839 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 840 PIPE_CONFIG(ADDR_SURF_P2) | 841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 842 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 843 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 844 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 845 NUM_BANKS(ADDR_SURF_16_BANK); 846 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 847 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 848 PIPE_CONFIG(ADDR_SURF_P2) | 849 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 850 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 851 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 852 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 853 NUM_BANKS(ADDR_SURF_16_BANK); 854 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 855 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 856 PIPE_CONFIG(ADDR_SURF_P2) | 857 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 858 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 859 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 860 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 861 NUM_BANKS(ADDR_SURF_16_BANK); 862 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 863 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 864 PIPE_CONFIG(ADDR_SURF_P2) | 865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 868 NUM_BANKS(ADDR_SURF_8_BANK) | 869 TILE_SPLIT(split_equal_to_row_size); 870 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 871 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 872 PIPE_CONFIG(ADDR_SURF_P2); 873 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 874 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 875 PIPE_CONFIG(ADDR_SURF_P2) | 876 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 877 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 880 NUM_BANKS(ADDR_SURF_8_BANK); 881 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 882 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 883 PIPE_CONFIG(ADDR_SURF_P2) | 884 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 885 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 888 NUM_BANKS(ADDR_SURF_8_BANK); 889 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 890 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 891 PIPE_CONFIG(ADDR_SURF_P2) | 892 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 893 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 895 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 896 NUM_BANKS(ADDR_SURF_4_BANK); 897 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 898 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 899 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 900 PIPE_CONFIG(ADDR_SURF_P2); 901 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 902 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 903 PIPE_CONFIG(ADDR_SURF_P2) | 904 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 905 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 906 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 907 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 908 NUM_BANKS(ADDR_SURF_16_BANK); 909 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 910 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 911 PIPE_CONFIG(ADDR_SURF_P2) | 912 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 913 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 914 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 915 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 916 NUM_BANKS(ADDR_SURF_16_BANK); 917 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 918 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 919 PIPE_CONFIG(ADDR_SURF_P2) | 920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 921 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 922 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 923 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 924 NUM_BANKS(ADDR_SURF_16_BANK); 925 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 926 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 927 PIPE_CONFIG(ADDR_SURF_P2); 928 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 929 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 930 PIPE_CONFIG(ADDR_SURF_P2) | 931 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 932 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 933 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 934 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 935 NUM_BANKS(ADDR_SURF_16_BANK); 936 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 937 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 938 PIPE_CONFIG(ADDR_SURF_P2) | 939 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 940 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 943 NUM_BANKS(ADDR_SURF_16_BANK); 944 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 945 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 946 PIPE_CONFIG(ADDR_SURF_P2) | 947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 951 NUM_BANKS(ADDR_SURF_16_BANK); 952 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 953 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 954 PIPE_CONFIG(ADDR_SURF_P2) | 955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 958 NUM_BANKS(ADDR_SURF_16_BANK) | 959 TILE_SPLIT(split_equal_to_row_size); 960 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 961 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 962 PIPE_CONFIG(ADDR_SURF_P2); 963 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 964 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 965 PIPE_CONFIG(ADDR_SURF_P2) | 966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 969 NUM_BANKS(ADDR_SURF_16_BANK) | 970 TILE_SPLIT(split_equal_to_row_size); 971 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 972 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 973 PIPE_CONFIG(ADDR_SURF_P2) | 974 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 977 NUM_BANKS(ADDR_SURF_16_BANK) | 978 TILE_SPLIT(split_equal_to_row_size); 979 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 980 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 981 PIPE_CONFIG(ADDR_SURF_P2) | 982 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 983 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 984 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 985 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 986 NUM_BANKS(ADDR_SURF_8_BANK); 987 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 988 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 989 PIPE_CONFIG(ADDR_SURF_P2) | 990 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 991 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 992 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 993 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 994 NUM_BANKS(ADDR_SURF_8_BANK); 995 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 996 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 997 PIPE_CONFIG(ADDR_SURF_P2) | 998 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 999 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1002 NUM_BANKS(ADDR_SURF_8_BANK); 1003 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1004 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1005 PIPE_CONFIG(ADDR_SURF_P2) | 1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1007 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1009 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1010 NUM_BANKS(ADDR_SURF_8_BANK); 1011 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1012 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1013 PIPE_CONFIG(ADDR_SURF_P2) | 1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1015 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1016 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1017 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1018 NUM_BANKS(ADDR_SURF_4_BANK); 1019 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1020 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1021 PIPE_CONFIG(ADDR_SURF_P2) | 1022 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1023 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1024 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1025 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1026 NUM_BANKS(ADDR_SURF_4_BANK); 1027 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1028 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1029 PIPE_CONFIG(ADDR_SURF_P2) | 1030 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1031 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1032 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1033 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1034 NUM_BANKS(ADDR_SURF_4_BANK); 1035 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1036 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1037 PIPE_CONFIG(ADDR_SURF_P2) | 1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1039 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1042 NUM_BANKS(ADDR_SURF_4_BANK); 1043 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1044 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1045 PIPE_CONFIG(ADDR_SURF_P2) | 1046 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1047 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1048 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1049 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1050 NUM_BANKS(ADDR_SURF_4_BANK); 1051 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1052 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1053 PIPE_CONFIG(ADDR_SURF_P2) | 1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1055 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1058 NUM_BANKS(ADDR_SURF_4_BANK); 1059 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1060 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1061 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1062 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1063 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1069 NUM_BANKS(ADDR_SURF_16_BANK); 1070 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1071 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1072 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1073 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1074 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1075 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1076 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1077 NUM_BANKS(ADDR_SURF_16_BANK); 1078 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1079 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1080 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1081 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1082 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1083 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1084 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1085 NUM_BANKS(ADDR_SURF_16_BANK); 1086 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1092 NUM_BANKS(ADDR_SURF_4_BANK) | 1093 TILE_SPLIT(split_equal_to_row_size); 1094 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1095 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1097 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1098 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1099 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1100 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1101 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1102 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1103 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1104 NUM_BANKS(ADDR_SURF_2_BANK); 1105 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1106 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1109 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1110 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1111 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1112 NUM_BANKS(ADDR_SURF_2_BANK); 1113 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1114 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1115 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1117 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1120 NUM_BANKS(ADDR_SURF_2_BANK); 1121 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1122 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1123 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1125 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1126 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1127 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1128 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1129 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1130 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1132 NUM_BANKS(ADDR_SURF_16_BANK); 1133 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1134 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1135 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1137 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1140 NUM_BANKS(ADDR_SURF_16_BANK); 1141 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1148 NUM_BANKS(ADDR_SURF_16_BANK); 1149 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1150 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1152 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1153 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1154 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1159 NUM_BANKS(ADDR_SURF_16_BANK); 1160 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1161 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1162 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1163 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1164 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1167 NUM_BANKS(ADDR_SURF_16_BANK); 1168 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1169 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1170 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1171 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1172 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1175 NUM_BANKS(ADDR_SURF_16_BANK); 1176 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1177 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1182 NUM_BANKS(ADDR_SURF_16_BANK) | 1183 TILE_SPLIT(split_equal_to_row_size); 1184 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1185 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1187 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1188 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1189 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1193 NUM_BANKS(ADDR_SURF_16_BANK) | 1194 TILE_SPLIT(split_equal_to_row_size); 1195 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1196 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1197 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1198 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1201 NUM_BANKS(ADDR_SURF_16_BANK) | 1202 TILE_SPLIT(split_equal_to_row_size); 1203 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1204 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1205 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1210 NUM_BANKS(ADDR_SURF_4_BANK); 1211 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1212 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1213 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1215 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1218 NUM_BANKS(ADDR_SURF_4_BANK); 1219 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1220 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1221 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1223 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1226 NUM_BANKS(ADDR_SURF_2_BANK); 1227 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1228 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1229 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1231 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1234 NUM_BANKS(ADDR_SURF_2_BANK); 1235 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1236 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1237 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1238 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1242 NUM_BANKS(ADDR_SURF_2_BANK); 1243 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1244 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1250 NUM_BANKS(ADDR_SURF_2_BANK); 1251 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1252 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1253 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1254 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1255 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1256 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1257 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1258 NUM_BANKS(ADDR_SURF_2_BANK); 1259 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1260 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1261 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1263 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1264 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1265 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1266 NUM_BANKS(ADDR_SURF_2_BANK); 1267 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1268 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1269 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1271 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1274 NUM_BANKS(ADDR_SURF_2_BANK); 1275 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1276 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1277 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1282 NUM_BANKS(ADDR_SURF_2_BANK); 1283 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1284 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1285 } else { 1286 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1287 } 1288 } 1289 1290 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1291 u32 sh_num, u32 instance, int xcc_id) 1292 { 1293 u32 data; 1294 1295 if (instance == 0xffffffff) 1296 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1297 else 1298 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1299 1300 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1301 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1302 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1303 else if (se_num == 0xffffffff) 1304 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1305 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1306 else if (sh_num == 0xffffffff) 1307 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1308 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1309 else 1310 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1311 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1312 WREG32(mmGRBM_GFX_INDEX, data); 1313 } 1314 1315 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1316 { 1317 u32 data, mask; 1318 1319 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1320 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1321 1322 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1323 1324 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1325 adev->gfx.config.max_sh_per_se); 1326 1327 return ~data & mask; 1328 } 1329 1330 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1331 { 1332 switch (adev->asic_type) { 1333 case CHIP_TAHITI: 1334 case CHIP_PITCAIRN: 1335 *rconf |= 1336 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1337 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1338 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1339 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1340 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1341 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1342 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1343 break; 1344 case CHIP_VERDE: 1345 *rconf |= 1346 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1347 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1348 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1349 break; 1350 case CHIP_OLAND: 1351 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1352 break; 1353 case CHIP_HAINAN: 1354 *rconf |= 0x0; 1355 break; 1356 default: 1357 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1358 break; 1359 } 1360 } 1361 1362 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1363 u32 raster_config, unsigned rb_mask, 1364 unsigned num_rb) 1365 { 1366 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1367 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1368 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1369 unsigned rb_per_se = num_rb / num_se; 1370 unsigned se_mask[4]; 1371 unsigned se; 1372 1373 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1374 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1375 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1376 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1377 1378 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1379 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1380 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1381 1382 for (se = 0; se < num_se; se++) { 1383 unsigned raster_config_se = raster_config; 1384 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1385 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1386 int idx = (se / 2) * 2; 1387 1388 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1389 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1390 1391 if (!se_mask[idx]) 1392 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1393 else 1394 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1395 } 1396 1397 pkr0_mask &= rb_mask; 1398 pkr1_mask &= rb_mask; 1399 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1400 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1401 1402 if (!pkr0_mask) 1403 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1404 else 1405 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1406 } 1407 1408 if (rb_per_se >= 2) { 1409 unsigned rb0_mask = 1 << (se * rb_per_se); 1410 unsigned rb1_mask = rb0_mask << 1; 1411 1412 rb0_mask &= rb_mask; 1413 rb1_mask &= rb_mask; 1414 if (!rb0_mask || !rb1_mask) { 1415 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1416 1417 if (!rb0_mask) 1418 raster_config_se |= 1419 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1420 else 1421 raster_config_se |= 1422 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1423 } 1424 1425 if (rb_per_se > 2) { 1426 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1427 rb1_mask = rb0_mask << 1; 1428 rb0_mask &= rb_mask; 1429 rb1_mask &= rb_mask; 1430 if (!rb0_mask || !rb1_mask) { 1431 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1432 1433 if (!rb0_mask) 1434 raster_config_se |= 1435 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1436 else 1437 raster_config_se |= 1438 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1439 } 1440 } 1441 } 1442 1443 /* GRBM_GFX_INDEX has a different offset on SI */ 1444 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1445 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1446 } 1447 1448 /* GRBM_GFX_INDEX has a different offset on SI */ 1449 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1450 } 1451 1452 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1453 { 1454 int i, j; 1455 u32 data; 1456 u32 raster_config = 0; 1457 u32 active_rbs = 0; 1458 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1459 adev->gfx.config.max_sh_per_se; 1460 unsigned num_rb_pipes; 1461 1462 mutex_lock(&adev->grbm_idx_mutex); 1463 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1464 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1465 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1466 data = gfx_v6_0_get_rb_active_bitmap(adev); 1467 active_rbs |= data << 1468 ((i * adev->gfx.config.max_sh_per_se + j) * 1469 rb_bitmap_width_per_sh); 1470 } 1471 } 1472 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1473 1474 adev->gfx.config.backend_enable_mask = active_rbs; 1475 adev->gfx.config.num_rbs = hweight32(active_rbs); 1476 1477 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1478 adev->gfx.config.max_shader_engines, 16); 1479 1480 gfx_v6_0_raster_config(adev, &raster_config); 1481 1482 if (!adev->gfx.config.backend_enable_mask || 1483 adev->gfx.config.num_rbs >= num_rb_pipes) 1484 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1485 else 1486 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1487 adev->gfx.config.backend_enable_mask, 1488 num_rb_pipes); 1489 1490 /* cache the values for userspace */ 1491 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1493 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1494 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1495 RREG32(mmCC_RB_BACKEND_DISABLE); 1496 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1497 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1498 adev->gfx.config.rb_config[i][j].raster_config = 1499 RREG32(mmPA_SC_RASTER_CONFIG); 1500 } 1501 } 1502 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1503 mutex_unlock(&adev->grbm_idx_mutex); 1504 } 1505 1506 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1507 u32 bitmap) 1508 { 1509 u32 data; 1510 1511 if (!bitmap) 1512 return; 1513 1514 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1515 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1516 1517 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1518 } 1519 1520 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1521 { 1522 u32 data, mask; 1523 1524 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1525 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1526 1527 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1528 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1529 } 1530 1531 1532 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1533 { 1534 int i, j, k; 1535 u32 data, mask; 1536 u32 active_cu = 0; 1537 1538 mutex_lock(&adev->grbm_idx_mutex); 1539 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1540 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1541 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1542 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1543 active_cu = gfx_v6_0_get_cu_enabled(adev); 1544 1545 mask = 1; 1546 for (k = 0; k < 16; k++) { 1547 mask <<= k; 1548 if (active_cu & mask) { 1549 data &= ~mask; 1550 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1551 break; 1552 } 1553 } 1554 } 1555 } 1556 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1557 mutex_unlock(&adev->grbm_idx_mutex); 1558 } 1559 1560 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1561 { 1562 adev->gfx.config.double_offchip_lds_buf = 0; 1563 } 1564 1565 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1566 { 1567 u32 gb_addr_config = 0; 1568 u32 mc_arb_ramcfg; 1569 u32 sx_debug_1; 1570 u32 hdp_host_path_cntl; 1571 u32 tmp; 1572 1573 switch (adev->asic_type) { 1574 case CHIP_TAHITI: 1575 adev->gfx.config.max_shader_engines = 2; 1576 adev->gfx.config.max_tile_pipes = 12; 1577 adev->gfx.config.max_cu_per_sh = 8; 1578 adev->gfx.config.max_sh_per_se = 2; 1579 adev->gfx.config.max_backends_per_se = 4; 1580 adev->gfx.config.max_texture_channel_caches = 12; 1581 adev->gfx.config.max_gprs = 256; 1582 adev->gfx.config.max_gs_threads = 32; 1583 adev->gfx.config.max_hw_contexts = 8; 1584 1585 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1586 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1587 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1588 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1589 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1590 break; 1591 case CHIP_PITCAIRN: 1592 adev->gfx.config.max_shader_engines = 2; 1593 adev->gfx.config.max_tile_pipes = 8; 1594 adev->gfx.config.max_cu_per_sh = 5; 1595 adev->gfx.config.max_sh_per_se = 2; 1596 adev->gfx.config.max_backends_per_se = 4; 1597 adev->gfx.config.max_texture_channel_caches = 8; 1598 adev->gfx.config.max_gprs = 256; 1599 adev->gfx.config.max_gs_threads = 32; 1600 adev->gfx.config.max_hw_contexts = 8; 1601 1602 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1603 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1604 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1605 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1606 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1607 break; 1608 case CHIP_VERDE: 1609 adev->gfx.config.max_shader_engines = 1; 1610 adev->gfx.config.max_tile_pipes = 4; 1611 adev->gfx.config.max_cu_per_sh = 5; 1612 adev->gfx.config.max_sh_per_se = 2; 1613 adev->gfx.config.max_backends_per_se = 4; 1614 adev->gfx.config.max_texture_channel_caches = 4; 1615 adev->gfx.config.max_gprs = 256; 1616 adev->gfx.config.max_gs_threads = 32; 1617 adev->gfx.config.max_hw_contexts = 8; 1618 1619 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1620 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1621 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1622 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1623 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1624 break; 1625 case CHIP_OLAND: 1626 adev->gfx.config.max_shader_engines = 1; 1627 adev->gfx.config.max_tile_pipes = 4; 1628 adev->gfx.config.max_cu_per_sh = 6; 1629 adev->gfx.config.max_sh_per_se = 1; 1630 adev->gfx.config.max_backends_per_se = 2; 1631 adev->gfx.config.max_texture_channel_caches = 4; 1632 adev->gfx.config.max_gprs = 256; 1633 adev->gfx.config.max_gs_threads = 16; 1634 adev->gfx.config.max_hw_contexts = 8; 1635 1636 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1637 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1638 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1639 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1640 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1641 break; 1642 case CHIP_HAINAN: 1643 adev->gfx.config.max_shader_engines = 1; 1644 adev->gfx.config.max_tile_pipes = 4; 1645 adev->gfx.config.max_cu_per_sh = 5; 1646 adev->gfx.config.max_sh_per_se = 1; 1647 adev->gfx.config.max_backends_per_se = 1; 1648 adev->gfx.config.max_texture_channel_caches = 2; 1649 adev->gfx.config.max_gprs = 256; 1650 adev->gfx.config.max_gs_threads = 16; 1651 adev->gfx.config.max_hw_contexts = 8; 1652 1653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1654 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1655 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1656 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1657 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1658 break; 1659 default: 1660 BUG(); 1661 break; 1662 } 1663 1664 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1665 WREG32(mmSRBM_INT_CNTL, 1); 1666 WREG32(mmSRBM_INT_ACK, 1); 1667 1668 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1669 1670 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1671 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1672 1673 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1674 adev->gfx.config.mem_max_burst_length_bytes = 256; 1675 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1676 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1677 if (adev->gfx.config.mem_row_size_in_kb > 4) 1678 adev->gfx.config.mem_row_size_in_kb = 4; 1679 adev->gfx.config.shader_engine_tile_size = 32; 1680 adev->gfx.config.num_gpus = 1; 1681 adev->gfx.config.multi_gpu_tile_size = 64; 1682 1683 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1684 switch (adev->gfx.config.mem_row_size_in_kb) { 1685 case 1: 1686 default: 1687 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1688 break; 1689 case 2: 1690 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1691 break; 1692 case 4: 1693 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1694 break; 1695 } 1696 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1697 if (adev->gfx.config.max_shader_engines == 2) 1698 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1699 adev->gfx.config.gb_addr_config = gb_addr_config; 1700 1701 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1702 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1703 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1704 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1705 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1706 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1707 1708 #if 0 1709 if (adev->has_uvd) { 1710 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1711 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1712 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1713 } 1714 #endif 1715 gfx_v6_0_tiling_mode_table_init(adev); 1716 1717 gfx_v6_0_setup_rb(adev); 1718 1719 gfx_v6_0_setup_spi(adev); 1720 1721 gfx_v6_0_get_cu_info(adev); 1722 gfx_v6_0_config_init(adev); 1723 1724 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1725 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1726 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1727 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1728 1729 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1730 WREG32(mmSX_DEBUG_1, sx_debug_1); 1731 1732 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1733 1734 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1735 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1736 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1737 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1738 1739 WREG32(mmVGT_NUM_INSTANCES, 1); 1740 WREG32(mmCP_PERFMON_CNTL, 0); 1741 WREG32(mmSQ_CONFIG, 0); 1742 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1743 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1744 1745 WREG32(mmVGT_CACHE_INVALIDATION, 1746 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1747 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1748 1749 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1750 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1751 1752 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1753 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1754 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1755 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1756 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1757 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1758 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1759 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1760 1761 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1762 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1763 1764 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1765 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1766 1767 udelay(50); 1768 } 1769 1770 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1771 { 1772 struct amdgpu_device *adev = ring->adev; 1773 uint32_t tmp = 0; 1774 unsigned i; 1775 int r; 1776 1777 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1778 1779 r = amdgpu_ring_alloc(ring, 3); 1780 if (r) 1781 return r; 1782 1783 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1784 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); 1785 amdgpu_ring_write(ring, 0xDEADBEEF); 1786 amdgpu_ring_commit(ring); 1787 1788 for (i = 0; i < adev->usec_timeout; i++) { 1789 tmp = RREG32(mmSCRATCH_REG0); 1790 if (tmp == 0xDEADBEEF) 1791 break; 1792 udelay(1); 1793 } 1794 1795 if (i >= adev->usec_timeout) 1796 r = -ETIMEDOUT; 1797 return r; 1798 } 1799 1800 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1801 { 1802 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1803 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1804 EVENT_INDEX(0)); 1805 } 1806 1807 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1808 u64 seq, unsigned flags) 1809 { 1810 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1811 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1812 /* flush read cache over gart */ 1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1814 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1815 amdgpu_ring_write(ring, 0); 1816 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1817 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1818 PACKET3_TC_ACTION_ENA | 1819 PACKET3_SH_KCACHE_ACTION_ENA | 1820 PACKET3_SH_ICACHE_ACTION_ENA); 1821 amdgpu_ring_write(ring, 0xFFFFFFFF); 1822 amdgpu_ring_write(ring, 0); 1823 amdgpu_ring_write(ring, 10); /* poll interval */ 1824 /* EVENT_WRITE_EOP - flush caches, send int */ 1825 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1826 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1827 amdgpu_ring_write(ring, addr & 0xfffffffc); 1828 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1829 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1830 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1831 amdgpu_ring_write(ring, lower_32_bits(seq)); 1832 amdgpu_ring_write(ring, upper_32_bits(seq)); 1833 } 1834 1835 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1836 struct amdgpu_job *job, 1837 struct amdgpu_ib *ib, 1838 uint32_t flags) 1839 { 1840 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1841 u32 header, control = 0; 1842 1843 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1844 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1846 amdgpu_ring_write(ring, 0); 1847 } 1848 1849 if (ib->flags & AMDGPU_IB_FLAG_CE) 1850 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1851 else 1852 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1853 1854 control |= ib->length_dw | (vmid << 24); 1855 1856 amdgpu_ring_write(ring, header); 1857 amdgpu_ring_write(ring, 1858 #ifdef __BIG_ENDIAN 1859 (2 << 0) | 1860 #endif 1861 (ib->gpu_addr & 0xFFFFFFFC)); 1862 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1863 amdgpu_ring_write(ring, control); 1864 } 1865 1866 /** 1867 * gfx_v6_0_ring_test_ib - basic ring IB test 1868 * 1869 * @ring: amdgpu_ring structure holding ring information 1870 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1871 * 1872 * Allocate an IB and execute it on the gfx ring (SI). 1873 * Provides a basic gfx ring test to verify that IBs are working. 1874 * Returns 0 on success, error on failure. 1875 */ 1876 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1877 { 1878 struct amdgpu_device *adev = ring->adev; 1879 struct dma_fence *f = NULL; 1880 struct amdgpu_ib ib; 1881 uint32_t tmp = 0; 1882 long r; 1883 1884 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1885 memset(&ib, 0, sizeof(ib)); 1886 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1887 if (r) 1888 return r; 1889 1890 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1891 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; 1892 ib.ptr[2] = 0xDEADBEEF; 1893 ib.length_dw = 3; 1894 1895 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1896 if (r) 1897 goto error; 1898 1899 r = dma_fence_wait_timeout(f, false, timeout); 1900 if (r == 0) { 1901 r = -ETIMEDOUT; 1902 goto error; 1903 } else if (r < 0) { 1904 goto error; 1905 } 1906 tmp = RREG32(mmSCRATCH_REG0); 1907 if (tmp == 0xDEADBEEF) 1908 r = 0; 1909 else 1910 r = -EINVAL; 1911 1912 error: 1913 amdgpu_ib_free(&ib, NULL); 1914 dma_fence_put(f); 1915 return r; 1916 } 1917 1918 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1919 { 1920 if (enable) { 1921 WREG32(mmCP_ME_CNTL, 0); 1922 } else { 1923 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1924 CP_ME_CNTL__PFP_HALT_MASK | 1925 CP_ME_CNTL__CE_HALT_MASK)); 1926 WREG32(mmSCRATCH_UMSK, 0); 1927 } 1928 udelay(50); 1929 } 1930 1931 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1932 { 1933 unsigned i; 1934 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1935 const struct gfx_firmware_header_v1_0 *ce_hdr; 1936 const struct gfx_firmware_header_v1_0 *me_hdr; 1937 const __le32 *fw_data; 1938 u32 fw_size; 1939 1940 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1941 return -EINVAL; 1942 1943 gfx_v6_0_cp_gfx_enable(adev, false); 1944 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1945 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1946 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1947 1948 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1949 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1950 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1951 1952 /* PFP */ 1953 fw_data = (const __le32 *) 1954 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1955 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1956 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1957 for (i = 0; i < fw_size; i++) 1958 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1959 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1960 1961 /* CE */ 1962 fw_data = (const __le32 *) 1963 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1964 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1965 WREG32(mmCP_CE_UCODE_ADDR, 0); 1966 for (i = 0; i < fw_size; i++) 1967 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1968 WREG32(mmCP_CE_UCODE_ADDR, 0); 1969 1970 /* ME */ 1971 fw_data = (const __be32 *) 1972 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1973 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1974 WREG32(mmCP_ME_RAM_WADDR, 0); 1975 for (i = 0; i < fw_size; i++) 1976 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1977 WREG32(mmCP_ME_RAM_WADDR, 0); 1978 1979 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1980 WREG32(mmCP_CE_UCODE_ADDR, 0); 1981 WREG32(mmCP_ME_RAM_WADDR, 0); 1982 WREG32(mmCP_ME_RAM_RADDR, 0); 1983 return 0; 1984 } 1985 1986 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 1987 { 1988 const struct cs_section_def *sect = NULL; 1989 const struct cs_extent_def *ext = NULL; 1990 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1991 int r, i; 1992 1993 r = amdgpu_ring_alloc(ring, 7 + 4); 1994 if (r) { 1995 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1996 return r; 1997 } 1998 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1999 amdgpu_ring_write(ring, 0x1); 2000 amdgpu_ring_write(ring, 0x0); 2001 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2002 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2003 amdgpu_ring_write(ring, 0); 2004 amdgpu_ring_write(ring, 0); 2005 2006 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2007 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2008 amdgpu_ring_write(ring, 0xc000); 2009 amdgpu_ring_write(ring, 0xe000); 2010 amdgpu_ring_commit(ring); 2011 2012 gfx_v6_0_cp_gfx_enable(adev, true); 2013 2014 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2015 if (r) { 2016 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2017 return r; 2018 } 2019 2020 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2021 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2022 2023 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2024 for (ext = sect->section; ext->extent != NULL; ++ext) { 2025 if (sect->id == SECT_CONTEXT) { 2026 amdgpu_ring_write(ring, 2027 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2028 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2029 for (i = 0; i < ext->reg_count; i++) 2030 amdgpu_ring_write(ring, ext->extent[i]); 2031 } 2032 } 2033 } 2034 2035 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2036 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2037 2038 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2039 amdgpu_ring_write(ring, 0); 2040 2041 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2042 amdgpu_ring_write(ring, 0x00000316); 2043 amdgpu_ring_write(ring, 0x0000000e); 2044 amdgpu_ring_write(ring, 0x00000010); 2045 2046 amdgpu_ring_commit(ring); 2047 2048 return 0; 2049 } 2050 2051 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2052 { 2053 struct amdgpu_ring *ring; 2054 u32 tmp; 2055 u32 rb_bufsz; 2056 int r; 2057 u64 rptr_addr; 2058 2059 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2060 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2061 2062 /* Set the write pointer delay */ 2063 WREG32(mmCP_RB_WPTR_DELAY, 0); 2064 2065 WREG32(mmCP_DEBUG, 0); 2066 WREG32(mmSCRATCH_ADDR, 0); 2067 2068 /* ring 0 - compute and gfx */ 2069 /* Set ring buffer size */ 2070 ring = &adev->gfx.gfx_ring[0]; 2071 rb_bufsz = order_base_2(ring->ring_size / 8); 2072 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2073 2074 #ifdef __BIG_ENDIAN 2075 tmp |= BUF_SWAP_32BIT; 2076 #endif 2077 WREG32(mmCP_RB0_CNTL, tmp); 2078 2079 /* Initialize the ring buffer's read and write pointers */ 2080 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2081 ring->wptr = 0; 2082 WREG32(mmCP_RB0_WPTR, ring->wptr); 2083 2084 /* set the wb address whether it's enabled or not */ 2085 rptr_addr = ring->rptr_gpu_addr; 2086 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2087 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2088 2089 WREG32(mmSCRATCH_UMSK, 0); 2090 2091 mdelay(1); 2092 WREG32(mmCP_RB0_CNTL, tmp); 2093 2094 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2095 2096 /* start the rings */ 2097 gfx_v6_0_cp_gfx_start(adev); 2098 r = amdgpu_ring_test_helper(ring); 2099 if (r) 2100 return r; 2101 2102 return 0; 2103 } 2104 2105 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2106 { 2107 return *ring->rptr_cpu_addr; 2108 } 2109 2110 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2111 { 2112 struct amdgpu_device *adev = ring->adev; 2113 2114 if (ring == &adev->gfx.gfx_ring[0]) 2115 return RREG32(mmCP_RB0_WPTR); 2116 else if (ring == &adev->gfx.compute_ring[0]) 2117 return RREG32(mmCP_RB1_WPTR); 2118 else if (ring == &adev->gfx.compute_ring[1]) 2119 return RREG32(mmCP_RB2_WPTR); 2120 else 2121 BUG(); 2122 } 2123 2124 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2125 { 2126 struct amdgpu_device *adev = ring->adev; 2127 2128 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2129 (void)RREG32(mmCP_RB0_WPTR); 2130 } 2131 2132 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2133 { 2134 struct amdgpu_device *adev = ring->adev; 2135 2136 if (ring == &adev->gfx.compute_ring[0]) { 2137 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2138 (void)RREG32(mmCP_RB1_WPTR); 2139 } else if (ring == &adev->gfx.compute_ring[1]) { 2140 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2141 (void)RREG32(mmCP_RB2_WPTR); 2142 } else { 2143 BUG(); 2144 } 2145 2146 } 2147 2148 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2149 { 2150 struct amdgpu_ring *ring; 2151 u32 tmp; 2152 u32 rb_bufsz; 2153 int i, r; 2154 u64 rptr_addr; 2155 2156 /* ring1 - compute only */ 2157 /* Set ring buffer size */ 2158 2159 ring = &adev->gfx.compute_ring[0]; 2160 rb_bufsz = order_base_2(ring->ring_size / 8); 2161 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2162 #ifdef __BIG_ENDIAN 2163 tmp |= BUF_SWAP_32BIT; 2164 #endif 2165 WREG32(mmCP_RB1_CNTL, tmp); 2166 2167 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2168 ring->wptr = 0; 2169 WREG32(mmCP_RB1_WPTR, ring->wptr); 2170 2171 rptr_addr = ring->rptr_gpu_addr; 2172 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2173 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2174 2175 mdelay(1); 2176 WREG32(mmCP_RB1_CNTL, tmp); 2177 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2178 2179 ring = &adev->gfx.compute_ring[1]; 2180 rb_bufsz = order_base_2(ring->ring_size / 8); 2181 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2182 #ifdef __BIG_ENDIAN 2183 tmp |= BUF_SWAP_32BIT; 2184 #endif 2185 WREG32(mmCP_RB2_CNTL, tmp); 2186 2187 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2188 ring->wptr = 0; 2189 WREG32(mmCP_RB2_WPTR, ring->wptr); 2190 rptr_addr = ring->rptr_gpu_addr; 2191 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2192 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2193 2194 mdelay(1); 2195 WREG32(mmCP_RB2_CNTL, tmp); 2196 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2197 2198 2199 for (i = 0; i < 2; i++) { 2200 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2201 if (r) 2202 return r; 2203 } 2204 2205 return 0; 2206 } 2207 2208 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2209 { 2210 gfx_v6_0_cp_gfx_enable(adev, enable); 2211 } 2212 2213 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2214 { 2215 return gfx_v6_0_cp_gfx_load_microcode(adev); 2216 } 2217 2218 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2219 bool enable) 2220 { 2221 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2222 u32 mask; 2223 int i; 2224 2225 if (enable) 2226 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2227 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2228 else 2229 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2230 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2231 WREG32(mmCP_INT_CNTL_RING0, tmp); 2232 2233 if (!enable) { 2234 /* read a gfx register */ 2235 tmp = RREG32(mmDB_DEPTH_INFO); 2236 2237 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2238 for (i = 0; i < adev->usec_timeout; i++) { 2239 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2240 break; 2241 udelay(1); 2242 } 2243 } 2244 } 2245 2246 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2247 { 2248 int r; 2249 2250 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2251 2252 r = gfx_v6_0_cp_load_microcode(adev); 2253 if (r) 2254 return r; 2255 2256 r = gfx_v6_0_cp_gfx_resume(adev); 2257 if (r) 2258 return r; 2259 r = gfx_v6_0_cp_compute_resume(adev); 2260 if (r) 2261 return r; 2262 2263 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2264 2265 return 0; 2266 } 2267 2268 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2269 { 2270 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2271 uint32_t seq = ring->fence_drv.sync_seq; 2272 uint64_t addr = ring->fence_drv.gpu_addr; 2273 2274 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2275 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2276 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2277 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2278 amdgpu_ring_write(ring, addr & 0xfffffffc); 2279 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2280 amdgpu_ring_write(ring, seq); 2281 amdgpu_ring_write(ring, 0xffffffff); 2282 amdgpu_ring_write(ring, 4); /* poll interval */ 2283 2284 if (usepfp) { 2285 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2286 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2287 amdgpu_ring_write(ring, 0); 2288 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2289 amdgpu_ring_write(ring, 0); 2290 } 2291 } 2292 2293 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2294 unsigned vmid, uint64_t pd_addr) 2295 { 2296 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2297 2298 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2299 2300 /* wait for the invalidate to complete */ 2301 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2302 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2303 WAIT_REG_MEM_ENGINE(0))); /* me */ 2304 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2305 amdgpu_ring_write(ring, 0); 2306 amdgpu_ring_write(ring, 0); /* ref */ 2307 amdgpu_ring_write(ring, 0); /* mask */ 2308 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2309 2310 if (usepfp) { 2311 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2312 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2313 amdgpu_ring_write(ring, 0x0); 2314 2315 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2316 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2317 amdgpu_ring_write(ring, 0); 2318 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2319 amdgpu_ring_write(ring, 0); 2320 } 2321 } 2322 2323 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2324 uint32_t reg, uint32_t val) 2325 { 2326 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2327 2328 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2329 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2330 WRITE_DATA_DST_SEL(0))); 2331 amdgpu_ring_write(ring, reg); 2332 amdgpu_ring_write(ring, 0); 2333 amdgpu_ring_write(ring, val); 2334 } 2335 2336 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2337 { 2338 const u32 *src_ptr; 2339 volatile u32 *dst_ptr; 2340 u32 dws; 2341 u64 reg_list_mc_addr; 2342 const struct cs_section_def *cs_data; 2343 int r; 2344 2345 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2346 adev->gfx.rlc.reg_list_size = 2347 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2348 2349 adev->gfx.rlc.cs_data = si_cs_data; 2350 src_ptr = adev->gfx.rlc.reg_list; 2351 dws = adev->gfx.rlc.reg_list_size; 2352 cs_data = adev->gfx.rlc.cs_data; 2353 2354 if (src_ptr) { 2355 /* init save restore block */ 2356 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2357 if (r) 2358 return r; 2359 } 2360 2361 if (cs_data) { 2362 /* clear state block */ 2363 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2364 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2365 2366 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2367 AMDGPU_GEM_DOMAIN_VRAM | 2368 AMDGPU_GEM_DOMAIN_GTT, 2369 &adev->gfx.rlc.clear_state_obj, 2370 &adev->gfx.rlc.clear_state_gpu_addr, 2371 (void **)&adev->gfx.rlc.cs_ptr); 2372 if (r) { 2373 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2374 amdgpu_gfx_rlc_fini(adev); 2375 return r; 2376 } 2377 2378 /* set up the cs buffer */ 2379 dst_ptr = adev->gfx.rlc.cs_ptr; 2380 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2381 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2382 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2383 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2384 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2385 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2386 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2387 } 2388 2389 return 0; 2390 } 2391 2392 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2393 { 2394 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2395 2396 if (!enable) { 2397 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2398 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2399 } 2400 } 2401 2402 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2403 { 2404 int i; 2405 2406 for (i = 0; i < adev->usec_timeout; i++) { 2407 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2408 break; 2409 udelay(1); 2410 } 2411 2412 for (i = 0; i < adev->usec_timeout; i++) { 2413 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2414 break; 2415 udelay(1); 2416 } 2417 } 2418 2419 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2420 { 2421 u32 tmp; 2422 2423 tmp = RREG32(mmRLC_CNTL); 2424 if (tmp != rlc) 2425 WREG32(mmRLC_CNTL, rlc); 2426 } 2427 2428 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2429 { 2430 u32 data, orig; 2431 2432 orig = data = RREG32(mmRLC_CNTL); 2433 2434 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2435 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2436 WREG32(mmRLC_CNTL, data); 2437 2438 gfx_v6_0_wait_for_rlc_serdes(adev); 2439 } 2440 2441 return orig; 2442 } 2443 2444 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2445 { 2446 WREG32(mmRLC_CNTL, 0); 2447 2448 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2449 gfx_v6_0_wait_for_rlc_serdes(adev); 2450 } 2451 2452 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2453 { 2454 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2455 2456 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2457 2458 udelay(50); 2459 } 2460 2461 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2462 { 2463 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2464 udelay(50); 2465 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2466 udelay(50); 2467 } 2468 2469 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2470 { 2471 u32 tmp; 2472 2473 /* Enable LBPW only for DDR3 */ 2474 tmp = RREG32(mmMC_SEQ_MISC0); 2475 if ((tmp & 0xF0000000) == 0xB0000000) 2476 return true; 2477 return false; 2478 } 2479 2480 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2481 { 2482 } 2483 2484 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2485 { 2486 u32 i; 2487 const struct rlc_firmware_header_v1_0 *hdr; 2488 const __le32 *fw_data; 2489 u32 fw_size; 2490 2491 2492 if (!adev->gfx.rlc_fw) 2493 return -EINVAL; 2494 2495 adev->gfx.rlc.funcs->stop(adev); 2496 adev->gfx.rlc.funcs->reset(adev); 2497 gfx_v6_0_init_pg(adev); 2498 gfx_v6_0_init_cg(adev); 2499 2500 WREG32(mmRLC_RL_BASE, 0); 2501 WREG32(mmRLC_RL_SIZE, 0); 2502 WREG32(mmRLC_LB_CNTL, 0); 2503 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2504 WREG32(mmRLC_LB_CNTR_INIT, 0); 2505 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2506 2507 WREG32(mmRLC_MC_CNTL, 0); 2508 WREG32(mmRLC_UCODE_CNTL, 0); 2509 2510 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2511 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2512 fw_data = (const __le32 *) 2513 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2514 2515 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2516 2517 for (i = 0; i < fw_size; i++) { 2518 WREG32(mmRLC_UCODE_ADDR, i); 2519 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2520 } 2521 WREG32(mmRLC_UCODE_ADDR, 0); 2522 2523 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2524 adev->gfx.rlc.funcs->start(adev); 2525 2526 return 0; 2527 } 2528 2529 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2530 { 2531 u32 data, orig, tmp; 2532 2533 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2534 2535 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2536 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2537 2538 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2539 2540 tmp = gfx_v6_0_halt_rlc(adev); 2541 2542 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2543 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2544 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2545 2546 gfx_v6_0_wait_for_rlc_serdes(adev); 2547 gfx_v6_0_update_rlc(adev, tmp); 2548 2549 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2550 2551 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2552 } else { 2553 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2554 2555 RREG32(mmCB_CGTT_SCLK_CTRL); 2556 RREG32(mmCB_CGTT_SCLK_CTRL); 2557 RREG32(mmCB_CGTT_SCLK_CTRL); 2558 RREG32(mmCB_CGTT_SCLK_CTRL); 2559 2560 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2561 } 2562 2563 if (orig != data) 2564 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2565 2566 } 2567 2568 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2569 { 2570 2571 u32 data, orig, tmp = 0; 2572 2573 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2574 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2575 data = 0x96940200; 2576 if (orig != data) 2577 WREG32(mmCGTS_SM_CTRL_REG, data); 2578 2579 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2580 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2581 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2582 if (orig != data) 2583 WREG32(mmCP_MEM_SLP_CNTL, data); 2584 } 2585 2586 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2587 data &= 0xffffffc0; 2588 if (orig != data) 2589 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2590 2591 tmp = gfx_v6_0_halt_rlc(adev); 2592 2593 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2594 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2595 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2596 2597 gfx_v6_0_update_rlc(adev, tmp); 2598 } else { 2599 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2600 data |= 0x00000003; 2601 if (orig != data) 2602 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2603 2604 data = RREG32(mmCP_MEM_SLP_CNTL); 2605 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2606 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2607 WREG32(mmCP_MEM_SLP_CNTL, data); 2608 } 2609 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2610 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2611 if (orig != data) 2612 WREG32(mmCGTS_SM_CTRL_REG, data); 2613 2614 tmp = gfx_v6_0_halt_rlc(adev); 2615 2616 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2617 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2618 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2619 2620 gfx_v6_0_update_rlc(adev, tmp); 2621 } 2622 } 2623 /* 2624 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2625 bool enable) 2626 { 2627 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2628 if (enable) { 2629 gfx_v6_0_enable_mgcg(adev, true); 2630 gfx_v6_0_enable_cgcg(adev, true); 2631 } else { 2632 gfx_v6_0_enable_cgcg(adev, false); 2633 gfx_v6_0_enable_mgcg(adev, false); 2634 } 2635 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2636 } 2637 */ 2638 2639 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2640 bool enable) 2641 { 2642 } 2643 2644 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2645 bool enable) 2646 { 2647 } 2648 2649 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2650 { 2651 u32 data, orig; 2652 2653 orig = data = RREG32(mmRLC_PG_CNTL); 2654 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2655 data &= ~0x8000; 2656 else 2657 data |= 0x8000; 2658 if (orig != data) 2659 WREG32(mmRLC_PG_CNTL, data); 2660 } 2661 2662 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2663 { 2664 } 2665 /* 2666 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2667 { 2668 const __le32 *fw_data; 2669 volatile u32 *dst_ptr; 2670 int me, i, max_me = 4; 2671 u32 bo_offset = 0; 2672 u32 table_offset, table_size; 2673 2674 if (adev->asic_type == CHIP_KAVERI) 2675 max_me = 5; 2676 2677 if (adev->gfx.rlc.cp_table_ptr == NULL) 2678 return; 2679 2680 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2681 for (me = 0; me < max_me; me++) { 2682 if (me == 0) { 2683 const struct gfx_firmware_header_v1_0 *hdr = 2684 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2685 fw_data = (const __le32 *) 2686 (adev->gfx.ce_fw->data + 2687 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2688 table_offset = le32_to_cpu(hdr->jt_offset); 2689 table_size = le32_to_cpu(hdr->jt_size); 2690 } else if (me == 1) { 2691 const struct gfx_firmware_header_v1_0 *hdr = 2692 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2693 fw_data = (const __le32 *) 2694 (adev->gfx.pfp_fw->data + 2695 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2696 table_offset = le32_to_cpu(hdr->jt_offset); 2697 table_size = le32_to_cpu(hdr->jt_size); 2698 } else if (me == 2) { 2699 const struct gfx_firmware_header_v1_0 *hdr = 2700 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2701 fw_data = (const __le32 *) 2702 (adev->gfx.me_fw->data + 2703 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2704 table_offset = le32_to_cpu(hdr->jt_offset); 2705 table_size = le32_to_cpu(hdr->jt_size); 2706 } else if (me == 3) { 2707 const struct gfx_firmware_header_v1_0 *hdr = 2708 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2709 fw_data = (const __le32 *) 2710 (adev->gfx.mec_fw->data + 2711 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2712 table_offset = le32_to_cpu(hdr->jt_offset); 2713 table_size = le32_to_cpu(hdr->jt_size); 2714 } else { 2715 const struct gfx_firmware_header_v1_0 *hdr = 2716 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2717 fw_data = (const __le32 *) 2718 (adev->gfx.mec2_fw->data + 2719 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2720 table_offset = le32_to_cpu(hdr->jt_offset); 2721 table_size = le32_to_cpu(hdr->jt_size); 2722 } 2723 2724 for (i = 0; i < table_size; i ++) { 2725 dst_ptr[bo_offset + i] = 2726 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2727 } 2728 2729 bo_offset += table_size; 2730 } 2731 } 2732 */ 2733 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2734 bool enable) 2735 { 2736 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2737 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2738 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2739 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2740 } else { 2741 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2742 (void)RREG32(mmDB_RENDER_CONTROL); 2743 } 2744 } 2745 2746 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2747 { 2748 u32 tmp; 2749 2750 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2751 2752 tmp = RREG32(mmRLC_MAX_PG_CU); 2753 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2754 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2755 WREG32(mmRLC_MAX_PG_CU, tmp); 2756 } 2757 2758 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2759 bool enable) 2760 { 2761 u32 data, orig; 2762 2763 orig = data = RREG32(mmRLC_PG_CNTL); 2764 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2765 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2766 else 2767 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2768 if (orig != data) 2769 WREG32(mmRLC_PG_CNTL, data); 2770 } 2771 2772 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2773 bool enable) 2774 { 2775 u32 data, orig; 2776 2777 orig = data = RREG32(mmRLC_PG_CNTL); 2778 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2779 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2780 else 2781 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2782 if (orig != data) 2783 WREG32(mmRLC_PG_CNTL, data); 2784 } 2785 2786 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2787 { 2788 u32 tmp; 2789 2790 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2791 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2792 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2793 2794 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2795 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2796 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2797 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2798 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2799 } 2800 2801 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2802 { 2803 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2804 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2805 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2806 } 2807 2808 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2809 { 2810 u32 count = 0; 2811 const struct cs_section_def *sect = NULL; 2812 const struct cs_extent_def *ext = NULL; 2813 2814 if (adev->gfx.rlc.cs_data == NULL) 2815 return 0; 2816 2817 /* begin clear state */ 2818 count += 2; 2819 /* context control state */ 2820 count += 3; 2821 2822 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2823 for (ext = sect->section; ext->extent != NULL; ++ext) { 2824 if (sect->id == SECT_CONTEXT) 2825 count += 2 + ext->reg_count; 2826 else 2827 return 0; 2828 } 2829 } 2830 /* pa_sc_raster_config */ 2831 count += 3; 2832 /* end clear state */ 2833 count += 2; 2834 /* clear state */ 2835 count += 2; 2836 2837 return count; 2838 } 2839 2840 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2841 volatile u32 *buffer) 2842 { 2843 u32 count = 0, i; 2844 const struct cs_section_def *sect = NULL; 2845 const struct cs_extent_def *ext = NULL; 2846 2847 if (adev->gfx.rlc.cs_data == NULL) 2848 return; 2849 if (buffer == NULL) 2850 return; 2851 2852 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2853 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2854 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2855 buffer[count++] = cpu_to_le32(0x80000000); 2856 buffer[count++] = cpu_to_le32(0x80000000); 2857 2858 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2859 for (ext = sect->section; ext->extent != NULL; ++ext) { 2860 if (sect->id == SECT_CONTEXT) { 2861 buffer[count++] = 2862 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2863 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2864 for (i = 0; i < ext->reg_count; i++) 2865 buffer[count++] = cpu_to_le32(ext->extent[i]); 2866 } else { 2867 return; 2868 } 2869 } 2870 } 2871 2872 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2873 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2874 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2875 2876 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2877 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2878 2879 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2880 buffer[count++] = cpu_to_le32(0); 2881 } 2882 2883 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2884 { 2885 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2886 AMD_PG_SUPPORT_GFX_SMG | 2887 AMD_PG_SUPPORT_GFX_DMG | 2888 AMD_PG_SUPPORT_CP | 2889 AMD_PG_SUPPORT_GDS | 2890 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2891 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2892 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2893 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2894 gfx_v6_0_init_gfx_cgpg(adev); 2895 gfx_v6_0_enable_cp_pg(adev, true); 2896 gfx_v6_0_enable_gds_pg(adev, true); 2897 } else { 2898 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2899 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2900 2901 } 2902 gfx_v6_0_init_ao_cu_mask(adev); 2903 gfx_v6_0_update_gfx_pg(adev, true); 2904 } else { 2905 2906 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2907 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2908 } 2909 } 2910 2911 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2912 { 2913 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2914 AMD_PG_SUPPORT_GFX_SMG | 2915 AMD_PG_SUPPORT_GFX_DMG | 2916 AMD_PG_SUPPORT_CP | 2917 AMD_PG_SUPPORT_GDS | 2918 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2919 gfx_v6_0_update_gfx_pg(adev, false); 2920 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2921 gfx_v6_0_enable_cp_pg(adev, false); 2922 gfx_v6_0_enable_gds_pg(adev, false); 2923 } 2924 } 2925 } 2926 2927 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2928 { 2929 uint64_t clock; 2930 2931 mutex_lock(&adev->gfx.gpu_clock_mutex); 2932 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2933 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2934 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2935 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2936 return clock; 2937 } 2938 2939 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2940 { 2941 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2942 gfx_v6_0_ring_emit_vgt_flush(ring); 2943 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2944 amdgpu_ring_write(ring, 0x80000000); 2945 amdgpu_ring_write(ring, 0); 2946 } 2947 2948 2949 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2950 { 2951 WREG32(mmSQ_IND_INDEX, 2952 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2953 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2954 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2955 (SQ_IND_INDEX__FORCE_READ_MASK)); 2956 return RREG32(mmSQ_IND_DATA); 2957 } 2958 2959 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2960 uint32_t wave, uint32_t thread, 2961 uint32_t regno, uint32_t num, uint32_t *out) 2962 { 2963 WREG32(mmSQ_IND_INDEX, 2964 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2965 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2966 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2967 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2968 (SQ_IND_INDEX__FORCE_READ_MASK) | 2969 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2970 while (num--) 2971 *(out++) = RREG32(mmSQ_IND_DATA); 2972 } 2973 2974 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2975 { 2976 /* type 0 wave data */ 2977 dst[(*no_fields)++] = 0; 2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 2993 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 2994 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2995 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2996 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 2997 } 2998 2999 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 3000 uint32_t wave, uint32_t start, 3001 uint32_t size, uint32_t *dst) 3002 { 3003 wave_read_regs( 3004 adev, simd, wave, 0, 3005 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3006 } 3007 3008 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3009 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3010 { 3011 DRM_INFO("Not implemented\n"); 3012 } 3013 3014 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3015 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3016 .select_se_sh = &gfx_v6_0_select_se_sh, 3017 .read_wave_data = &gfx_v6_0_read_wave_data, 3018 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3019 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3020 }; 3021 3022 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3023 .init = gfx_v6_0_rlc_init, 3024 .resume = gfx_v6_0_rlc_resume, 3025 .stop = gfx_v6_0_rlc_stop, 3026 .reset = gfx_v6_0_rlc_reset, 3027 .start = gfx_v6_0_rlc_start 3028 }; 3029 3030 static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) 3031 { 3032 struct amdgpu_device *adev = ip_block->adev; 3033 3034 adev->gfx.xcc_mask = 1; 3035 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3036 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3037 GFX6_NUM_COMPUTE_RINGS); 3038 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3039 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3040 gfx_v6_0_set_ring_funcs(adev); 3041 gfx_v6_0_set_irq_funcs(adev); 3042 3043 return 0; 3044 } 3045 3046 static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 3047 { 3048 struct amdgpu_ring *ring; 3049 struct amdgpu_device *adev = ip_block->adev; 3050 int i, r; 3051 3052 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3053 if (r) 3054 return r; 3055 3056 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3057 if (r) 3058 return r; 3059 3060 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3061 if (r) 3062 return r; 3063 3064 r = gfx_v6_0_init_microcode(adev); 3065 if (r) { 3066 DRM_ERROR("Failed to load gfx firmware!\n"); 3067 return r; 3068 } 3069 3070 r = adev->gfx.rlc.funcs->init(adev); 3071 if (r) { 3072 DRM_ERROR("Failed to init rlc BOs!\n"); 3073 return r; 3074 } 3075 3076 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3077 ring = &adev->gfx.gfx_ring[i]; 3078 ring->ring_obj = NULL; 3079 sprintf(ring->name, "gfx"); 3080 r = amdgpu_ring_init(adev, ring, 2048, 3081 &adev->gfx.eop_irq, 3082 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3083 AMDGPU_RING_PRIO_DEFAULT, NULL); 3084 if (r) 3085 return r; 3086 } 3087 3088 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3089 unsigned irq_type; 3090 3091 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3092 DRM_ERROR("Too many (%d) compute rings!\n", i); 3093 break; 3094 } 3095 ring = &adev->gfx.compute_ring[i]; 3096 ring->ring_obj = NULL; 3097 ring->use_doorbell = false; 3098 ring->doorbell_index = 0; 3099 ring->me = 1; 3100 ring->pipe = i; 3101 ring->queue = i; 3102 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3103 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3104 r = amdgpu_ring_init(adev, ring, 1024, 3105 &adev->gfx.eop_irq, irq_type, 3106 AMDGPU_RING_PRIO_DEFAULT, NULL); 3107 if (r) 3108 return r; 3109 } 3110 3111 return r; 3112 } 3113 3114 static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 3115 { 3116 int i; 3117 struct amdgpu_device *adev = ip_block->adev; 3118 3119 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3120 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3121 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3122 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3123 3124 amdgpu_gfx_rlc_fini(adev); 3125 3126 return 0; 3127 } 3128 3129 static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 3130 { 3131 int r; 3132 struct amdgpu_device *adev = ip_block->adev; 3133 3134 gfx_v6_0_constants_init(adev); 3135 3136 r = adev->gfx.rlc.funcs->resume(adev); 3137 if (r) 3138 return r; 3139 3140 r = gfx_v6_0_cp_resume(adev); 3141 if (r) 3142 return r; 3143 3144 adev->gfx.ce_ram_size = 0x8000; 3145 3146 return r; 3147 } 3148 3149 static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 3150 { 3151 struct amdgpu_device *adev = ip_block->adev; 3152 3153 gfx_v6_0_cp_enable(adev, false); 3154 adev->gfx.rlc.funcs->stop(adev); 3155 gfx_v6_0_fini_pg(adev); 3156 3157 return 0; 3158 } 3159 3160 static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) 3161 { 3162 return gfx_v6_0_hw_fini(ip_block); 3163 } 3164 3165 static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) 3166 { 3167 return gfx_v6_0_hw_init(ip_block); 3168 } 3169 3170 static bool gfx_v6_0_is_idle(void *handle) 3171 { 3172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3173 3174 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3175 return false; 3176 else 3177 return true; 3178 } 3179 3180 static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3181 { 3182 unsigned i; 3183 struct amdgpu_device *adev = ip_block->adev; 3184 3185 for (i = 0; i < adev->usec_timeout; i++) { 3186 if (gfx_v6_0_is_idle(adev)) 3187 return 0; 3188 udelay(1); 3189 } 3190 return -ETIMEDOUT; 3191 } 3192 3193 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3194 enum amdgpu_interrupt_state state) 3195 { 3196 u32 cp_int_cntl; 3197 3198 switch (state) { 3199 case AMDGPU_IRQ_STATE_DISABLE: 3200 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3201 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3202 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3203 break; 3204 case AMDGPU_IRQ_STATE_ENABLE: 3205 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3206 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3207 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3208 break; 3209 default: 3210 break; 3211 } 3212 } 3213 3214 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3215 int ring, 3216 enum amdgpu_interrupt_state state) 3217 { 3218 u32 cp_int_cntl; 3219 switch (state){ 3220 case AMDGPU_IRQ_STATE_DISABLE: 3221 if (ring == 0) { 3222 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3223 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3224 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3225 break; 3226 } else { 3227 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3228 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3229 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3230 break; 3231 3232 } 3233 case AMDGPU_IRQ_STATE_ENABLE: 3234 if (ring == 0) { 3235 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3236 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3237 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3238 break; 3239 } else { 3240 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3241 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3242 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3243 break; 3244 3245 } 3246 3247 default: 3248 BUG(); 3249 break; 3250 3251 } 3252 } 3253 3254 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3255 struct amdgpu_irq_src *src, 3256 unsigned type, 3257 enum amdgpu_interrupt_state state) 3258 { 3259 u32 cp_int_cntl; 3260 3261 switch (state) { 3262 case AMDGPU_IRQ_STATE_DISABLE: 3263 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3264 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3265 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3266 break; 3267 case AMDGPU_IRQ_STATE_ENABLE: 3268 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3269 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3270 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3271 break; 3272 default: 3273 break; 3274 } 3275 3276 return 0; 3277 } 3278 3279 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3280 struct amdgpu_irq_src *src, 3281 unsigned type, 3282 enum amdgpu_interrupt_state state) 3283 { 3284 u32 cp_int_cntl; 3285 3286 switch (state) { 3287 case AMDGPU_IRQ_STATE_DISABLE: 3288 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3289 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3290 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3291 break; 3292 case AMDGPU_IRQ_STATE_ENABLE: 3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3294 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3295 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3296 break; 3297 default: 3298 break; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3305 struct amdgpu_irq_src *src, 3306 unsigned type, 3307 enum amdgpu_interrupt_state state) 3308 { 3309 switch (type) { 3310 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3311 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3312 break; 3313 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3314 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3315 break; 3316 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3317 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3318 break; 3319 default: 3320 break; 3321 } 3322 return 0; 3323 } 3324 3325 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3326 struct amdgpu_irq_src *source, 3327 struct amdgpu_iv_entry *entry) 3328 { 3329 switch (entry->ring_id) { 3330 case 0: 3331 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3332 break; 3333 case 1: 3334 case 2: 3335 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3336 break; 3337 default: 3338 break; 3339 } 3340 return 0; 3341 } 3342 3343 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3344 struct amdgpu_iv_entry *entry) 3345 { 3346 struct amdgpu_ring *ring; 3347 3348 switch (entry->ring_id) { 3349 case 0: 3350 ring = &adev->gfx.gfx_ring[0]; 3351 break; 3352 case 1: 3353 case 2: 3354 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3355 break; 3356 default: 3357 return; 3358 } 3359 drm_sched_fault(&ring->sched); 3360 } 3361 3362 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3363 struct amdgpu_irq_src *source, 3364 struct amdgpu_iv_entry *entry) 3365 { 3366 DRM_ERROR("Illegal register access in command stream\n"); 3367 gfx_v6_0_fault(adev, entry); 3368 return 0; 3369 } 3370 3371 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3372 struct amdgpu_irq_src *source, 3373 struct amdgpu_iv_entry *entry) 3374 { 3375 DRM_ERROR("Illegal instruction in command stream\n"); 3376 gfx_v6_0_fault(adev, entry); 3377 return 0; 3378 } 3379 3380 static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3381 enum amd_clockgating_state state) 3382 { 3383 bool gate = false; 3384 struct amdgpu_device *adev = ip_block->adev; 3385 3386 if (state == AMD_CG_STATE_GATE) 3387 gate = true; 3388 3389 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3390 if (gate) { 3391 gfx_v6_0_enable_mgcg(adev, true); 3392 gfx_v6_0_enable_cgcg(adev, true); 3393 } else { 3394 gfx_v6_0_enable_cgcg(adev, false); 3395 gfx_v6_0_enable_mgcg(adev, false); 3396 } 3397 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3398 3399 return 0; 3400 } 3401 3402 static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3403 enum amd_powergating_state state) 3404 { 3405 bool gate = false; 3406 struct amdgpu_device *adev = ip_block->adev; 3407 3408 if (state == AMD_PG_STATE_GATE) 3409 gate = true; 3410 3411 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3412 AMD_PG_SUPPORT_GFX_SMG | 3413 AMD_PG_SUPPORT_GFX_DMG | 3414 AMD_PG_SUPPORT_CP | 3415 AMD_PG_SUPPORT_GDS | 3416 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3417 gfx_v6_0_update_gfx_pg(adev, gate); 3418 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3419 gfx_v6_0_enable_cp_pg(adev, gate); 3420 gfx_v6_0_enable_gds_pg(adev, gate); 3421 } 3422 } 3423 3424 return 0; 3425 } 3426 3427 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3428 { 3429 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3430 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3431 PACKET3_TC_ACTION_ENA | 3432 PACKET3_SH_KCACHE_ACTION_ENA | 3433 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3434 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3435 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3436 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3437 } 3438 3439 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3440 .name = "gfx_v6_0", 3441 .early_init = gfx_v6_0_early_init, 3442 .sw_init = gfx_v6_0_sw_init, 3443 .sw_fini = gfx_v6_0_sw_fini, 3444 .hw_init = gfx_v6_0_hw_init, 3445 .hw_fini = gfx_v6_0_hw_fini, 3446 .suspend = gfx_v6_0_suspend, 3447 .resume = gfx_v6_0_resume, 3448 .is_idle = gfx_v6_0_is_idle, 3449 .wait_for_idle = gfx_v6_0_wait_for_idle, 3450 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3451 .set_powergating_state = gfx_v6_0_set_powergating_state, 3452 }; 3453 3454 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3455 .type = AMDGPU_RING_TYPE_GFX, 3456 .align_mask = 0xff, 3457 .nop = 0x80000000, 3458 .support_64bit_ptrs = false, 3459 .get_rptr = gfx_v6_0_ring_get_rptr, 3460 .get_wptr = gfx_v6_0_ring_get_wptr, 3461 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3462 .emit_frame_size = 3463 5 + 5 + /* hdp flush / invalidate */ 3464 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3465 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3466 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3467 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3468 5, /* SURFACE_SYNC */ 3469 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3470 .emit_ib = gfx_v6_0_ring_emit_ib, 3471 .emit_fence = gfx_v6_0_ring_emit_fence, 3472 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3473 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3474 .test_ring = gfx_v6_0_ring_test_ring, 3475 .test_ib = gfx_v6_0_ring_test_ib, 3476 .insert_nop = amdgpu_ring_insert_nop, 3477 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3478 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3479 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3480 }; 3481 3482 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3483 .type = AMDGPU_RING_TYPE_COMPUTE, 3484 .align_mask = 0xff, 3485 .nop = 0x80000000, 3486 .get_rptr = gfx_v6_0_ring_get_rptr, 3487 .get_wptr = gfx_v6_0_ring_get_wptr, 3488 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3489 .emit_frame_size = 3490 5 + 5 + /* hdp flush / invalidate */ 3491 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3492 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3493 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3494 5, /* SURFACE_SYNC */ 3495 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3496 .emit_ib = gfx_v6_0_ring_emit_ib, 3497 .emit_fence = gfx_v6_0_ring_emit_fence, 3498 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3499 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3500 .test_ring = gfx_v6_0_ring_test_ring, 3501 .test_ib = gfx_v6_0_ring_test_ib, 3502 .insert_nop = amdgpu_ring_insert_nop, 3503 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3504 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3505 }; 3506 3507 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3508 { 3509 int i; 3510 3511 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3512 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3513 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3514 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3515 } 3516 3517 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3518 .set = gfx_v6_0_set_eop_interrupt_state, 3519 .process = gfx_v6_0_eop_irq, 3520 }; 3521 3522 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3523 .set = gfx_v6_0_set_priv_reg_fault_state, 3524 .process = gfx_v6_0_priv_reg_irq, 3525 }; 3526 3527 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3528 .set = gfx_v6_0_set_priv_inst_fault_state, 3529 .process = gfx_v6_0_priv_inst_irq, 3530 }; 3531 3532 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3533 { 3534 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3535 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3536 3537 adev->gfx.priv_reg_irq.num_types = 1; 3538 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3539 3540 adev->gfx.priv_inst_irq.num_types = 1; 3541 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3542 } 3543 3544 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3545 { 3546 int i, j, k, counter, active_cu_number = 0; 3547 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3548 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3549 unsigned disable_masks[4 * 2]; 3550 u32 ao_cu_num; 3551 3552 if (adev->flags & AMD_IS_APU) 3553 ao_cu_num = 2; 3554 else 3555 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3556 3557 memset(cu_info, 0, sizeof(*cu_info)); 3558 3559 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3560 3561 mutex_lock(&adev->grbm_idx_mutex); 3562 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3563 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3564 mask = 1; 3565 ao_bitmap = 0; 3566 counter = 0; 3567 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3568 if (i < 4 && j < 2) 3569 gfx_v6_0_set_user_cu_inactive_bitmap( 3570 adev, disable_masks[i * 2 + j]); 3571 bitmap = gfx_v6_0_get_cu_enabled(adev); 3572 cu_info->bitmap[0][i][j] = bitmap; 3573 3574 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3575 if (bitmap & mask) { 3576 if (counter < ao_cu_num) 3577 ao_bitmap |= mask; 3578 counter ++; 3579 } 3580 mask <<= 1; 3581 } 3582 active_cu_number += counter; 3583 if (i < 2 && j < 2) 3584 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3585 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3586 } 3587 } 3588 3589 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3590 mutex_unlock(&adev->grbm_idx_mutex); 3591 3592 cu_info->number = active_cu_number; 3593 cu_info->ao_cu_mask = ao_cu_mask; 3594 } 3595 3596 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3597 { 3598 .type = AMD_IP_BLOCK_TYPE_GFX, 3599 .major = 6, 3600 .minor = 0, 3601 .rev = 0, 3602 .funcs = &gfx_v6_0_ip_funcs, 3603 }; 3604