1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "bif/bif_3_0_d.h" 32 #include "bif/bif_3_0_sh_mask.h" 33 #include "oss/oss_1_0_d.h" 34 #include "oss/oss_1_0_sh_mask.h" 35 #include "gca/gfx_6_0_d.h" 36 #include "gca/gfx_6_0_sh_mask.h" 37 #include "gmc/gmc_6_0_d.h" 38 #include "gmc/gmc_6_0_sh_mask.h" 39 #include "dce/dce_6_0_d.h" 40 #include "dce/dce_6_0_sh_mask.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "si_enums.h" 43 #include "si.h" 44 45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 48 49 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 50 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 51 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 52 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 53 54 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 56 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 57 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 58 59 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 60 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 61 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 63 64 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 66 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 71 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 72 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 73 74 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 75 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 76 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 77 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 78 79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 80 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 82 #define MICRO_TILE_MODE(x) ((x) << 0) 83 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 84 #define BANK_WIDTH(x) ((x) << 14) 85 #define BANK_HEIGHT(x) ((x) << 16) 86 #define MACRO_TILE_ASPECT(x) ((x) << 18) 87 #define NUM_BANKS(x) ((x) << 20) 88 89 static const u32 verde_rlc_save_restore_register_list[] = 90 { 91 (0x8000 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8040 << 16) | (0x98f4 >> 2), 94 0x00000000, 95 (0x8000 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8040 << 16) | (0xe80 >> 2), 98 0x00000000, 99 (0x8000 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8040 << 16) | (0x89bc >> 2), 102 0x00000000, 103 (0x8000 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x8040 << 16) | (0x8c1c >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0x98f0 >> 2), 108 0x00000000, 109 (0x9c00 << 16) | (0xe7c >> 2), 110 0x00000000, 111 (0x8000 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x8040 << 16) | (0x9148 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x9150 >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x897c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0x8d8c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0xac54 >> 2), 122 0X00000000, 123 0x3, 124 (0x9c00 << 16) | (0x98f8 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9910 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9914 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x9918 >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x991c >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9920 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9924 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x9928 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x992c >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9930 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9934 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x9938 >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x993c >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9940 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9944 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x9948 >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x994c >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9950 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9954 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x9958 >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x995c >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9960 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9964 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x9968 >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x996c >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9970 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9974 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x9978 >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x997c >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9980 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9984 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x9988 >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x998c >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c00 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c14 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c04 >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x8c08 >> 2), 197 0x00000000, 198 (0x8000 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8040 << 16) | (0x9b7c >> 2), 201 0x00000000, 202 (0x8000 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8040 << 16) | (0xe84 >> 2), 205 0x00000000, 206 (0x8000 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8040 << 16) | (0x89c0 >> 2), 209 0x00000000, 210 (0x8000 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8040 << 16) | (0x914c >> 2), 213 0x00000000, 214 (0x8000 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8040 << 16) | (0x8c20 >> 2), 217 0x00000000, 218 (0x8000 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x8040 << 16) | (0x9354 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9060 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9364 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x9100 >> 2), 227 0x00000000, 228 (0x9c00 << 16) | (0x913c >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e0 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e4 >> 2), 233 0x00000000, 234 (0x8000 << 16) | (0x90e8 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e0 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e4 >> 2), 239 0x00000000, 240 (0x8040 << 16) | (0x90e8 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8bcc >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x8b24 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x88c4 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8e50 >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8c0c >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e58 >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x8e5c >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x9508 >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x950c >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x9494 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac0c >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac10 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xac14 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xae00 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0xac08 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88d4 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88c8 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x88cc >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x89b0 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8b10 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x8a14 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9830 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9834 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9838 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x9a10 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9870 >> 2), 293 0x00000000, 294 (0x8000 << 16) | (0x9874 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9870 >> 2), 297 0x00000000, 298 (0x8001 << 16) | (0x9874 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9870 >> 2), 301 0x00000000, 302 (0x8040 << 16) | (0x9874 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9870 >> 2), 305 0x00000000, 306 (0x8041 << 16) | (0x9874 >> 2), 307 0x00000000, 308 0x00000000 309 }; 310 311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 312 { 313 const char *chip_name; 314 char fw_name[30]; 315 int err; 316 const struct gfx_firmware_header_v1_0 *cp_hdr; 317 const struct rlc_firmware_header_v1_0 *rlc_hdr; 318 319 DRM_DEBUG("\n"); 320 321 switch (adev->asic_type) { 322 case CHIP_TAHITI: 323 chip_name = "tahiti"; 324 break; 325 case CHIP_PITCAIRN: 326 chip_name = "pitcairn"; 327 break; 328 case CHIP_VERDE: 329 chip_name = "verde"; 330 break; 331 case CHIP_OLAND: 332 chip_name = "oland"; 333 break; 334 case CHIP_HAINAN: 335 chip_name = "hainan"; 336 break; 337 default: BUG(); 338 } 339 340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 342 if (err) 343 goto out; 344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 345 if (err) 346 goto out; 347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 350 351 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 353 if (err) 354 goto out; 355 err = amdgpu_ucode_validate(adev->gfx.me_fw); 356 if (err) 357 goto out; 358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 361 362 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 363 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 364 if (err) 365 goto out; 366 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 367 if (err) 368 goto out; 369 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 370 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 371 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 372 373 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 374 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 375 if (err) 376 goto out; 377 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 378 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 379 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 380 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 381 382 out: 383 if (err) { 384 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 385 release_firmware(adev->gfx.pfp_fw); 386 adev->gfx.pfp_fw = NULL; 387 release_firmware(adev->gfx.me_fw); 388 adev->gfx.me_fw = NULL; 389 release_firmware(adev->gfx.ce_fw); 390 adev->gfx.ce_fw = NULL; 391 release_firmware(adev->gfx.rlc_fw); 392 adev->gfx.rlc_fw = NULL; 393 } 394 return err; 395 } 396 397 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 398 { 399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 400 u32 reg_offset, split_equal_to_row_size, *tilemode; 401 402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 403 tilemode = adev->gfx.config.tile_mode_array; 404 405 switch (adev->gfx.config.mem_row_size_in_kb) { 406 case 1: 407 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 408 break; 409 case 2: 410 default: 411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 412 break; 413 case 4: 414 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 415 break; 416 } 417 418 if (adev->asic_type == CHIP_VERDE) { 419 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 420 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 421 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 426 NUM_BANKS(ADDR_SURF_16_BANK); 427 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 428 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 429 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 430 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 434 NUM_BANKS(ADDR_SURF_16_BANK); 435 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 436 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 437 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 438 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 439 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 440 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 441 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 442 NUM_BANKS(ADDR_SURF_16_BANK); 443 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 444 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 445 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 449 NUM_BANKS(ADDR_SURF_8_BANK) | 450 TILE_SPLIT(split_equal_to_row_size); 451 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 452 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 453 PIPE_CONFIG(ADDR_SURF_P4_8x16); 454 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 455 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 456 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 457 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 460 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 461 NUM_BANKS(ADDR_SURF_4_BANK); 462 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 463 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 464 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 465 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 469 NUM_BANKS(ADDR_SURF_4_BANK); 470 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 471 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 472 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 473 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 474 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 477 NUM_BANKS(ADDR_SURF_2_BANK); 478 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 479 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 480 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 481 PIPE_CONFIG(ADDR_SURF_P4_8x16); 482 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 483 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 484 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 485 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 489 NUM_BANKS(ADDR_SURF_16_BANK); 490 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 491 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 492 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 493 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 494 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 495 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 496 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 497 NUM_BANKS(ADDR_SURF_16_BANK); 498 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 499 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 500 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 502 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 505 NUM_BANKS(ADDR_SURF_16_BANK); 506 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 507 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 508 PIPE_CONFIG(ADDR_SURF_P4_8x16); 509 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 510 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 511 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 516 NUM_BANKS(ADDR_SURF_16_BANK); 517 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 518 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 519 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 524 NUM_BANKS(ADDR_SURF_16_BANK); 525 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 526 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 527 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 528 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 532 NUM_BANKS(ADDR_SURF_16_BANK); 533 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 534 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 535 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 536 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 539 NUM_BANKS(ADDR_SURF_16_BANK) | 540 TILE_SPLIT(split_equal_to_row_size); 541 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 542 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 543 PIPE_CONFIG(ADDR_SURF_P4_8x16); 544 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 545 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 546 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 550 NUM_BANKS(ADDR_SURF_16_BANK) | 551 TILE_SPLIT(split_equal_to_row_size); 552 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 553 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 554 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 558 NUM_BANKS(ADDR_SURF_16_BANK) | 559 TILE_SPLIT(split_equal_to_row_size); 560 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 561 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 562 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 563 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 564 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 565 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 566 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 567 NUM_BANKS(ADDR_SURF_8_BANK); 568 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 569 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 570 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 572 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 573 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 574 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 575 NUM_BANKS(ADDR_SURF_8_BANK); 576 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 577 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 578 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 579 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 580 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 583 NUM_BANKS(ADDR_SURF_4_BANK); 584 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 585 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 586 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 587 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 591 NUM_BANKS(ADDR_SURF_4_BANK); 592 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 593 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 594 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 595 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 596 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 599 NUM_BANKS(ADDR_SURF_2_BANK); 600 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 601 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 602 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 603 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 604 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 607 NUM_BANKS(ADDR_SURF_2_BANK); 608 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 609 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 610 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 611 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 612 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 615 NUM_BANKS(ADDR_SURF_2_BANK); 616 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 617 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 618 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 619 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 620 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 623 NUM_BANKS(ADDR_SURF_2_BANK); 624 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 625 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 626 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 627 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 628 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 631 NUM_BANKS(ADDR_SURF_2_BANK); 632 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 633 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 634 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 635 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 636 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 637 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 638 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 639 NUM_BANKS(ADDR_SURF_2_BANK); 640 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 641 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 642 } else if (adev->asic_type == CHIP_OLAND) { 643 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 644 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 645 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 646 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 647 NUM_BANKS(ADDR_SURF_16_BANK) | 648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 649 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 651 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 653 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 655 NUM_BANKS(ADDR_SURF_16_BANK) | 656 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 657 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 658 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 659 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 660 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 661 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 662 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 663 NUM_BANKS(ADDR_SURF_16_BANK) | 664 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 665 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 666 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 667 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 668 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 669 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 670 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 671 NUM_BANKS(ADDR_SURF_16_BANK) | 672 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 673 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 674 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 675 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 676 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 677 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 679 NUM_BANKS(ADDR_SURF_16_BANK) | 680 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 681 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 683 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 684 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 685 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 686 TILE_SPLIT(split_equal_to_row_size) | 687 NUM_BANKS(ADDR_SURF_16_BANK) | 688 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 691 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 693 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 694 TILE_SPLIT(split_equal_to_row_size) | 695 NUM_BANKS(ADDR_SURF_16_BANK) | 696 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 698 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 699 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 700 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 701 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 702 TILE_SPLIT(split_equal_to_row_size) | 703 NUM_BANKS(ADDR_SURF_16_BANK) | 704 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 705 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 706 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 707 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 708 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 709 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 710 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 711 NUM_BANKS(ADDR_SURF_16_BANK) | 712 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 715 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 716 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 717 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 719 NUM_BANKS(ADDR_SURF_16_BANK) | 720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 723 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 724 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 725 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 726 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 727 NUM_BANKS(ADDR_SURF_16_BANK) | 728 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 729 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 730 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 731 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 732 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 733 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 735 NUM_BANKS(ADDR_SURF_16_BANK) | 736 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 739 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 740 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 741 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 742 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 743 NUM_BANKS(ADDR_SURF_16_BANK) | 744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 747 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 748 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 749 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 750 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 751 NUM_BANKS(ADDR_SURF_16_BANK) | 752 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 753 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 754 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 755 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 756 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 757 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 758 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 759 NUM_BANKS(ADDR_SURF_16_BANK) | 760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 763 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 764 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 765 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 766 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 767 NUM_BANKS(ADDR_SURF_16_BANK) | 768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 771 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 772 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 773 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 774 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 775 NUM_BANKS(ADDR_SURF_16_BANK) | 776 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 779 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 780 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 781 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 782 TILE_SPLIT(split_equal_to_row_size) | 783 NUM_BANKS(ADDR_SURF_16_BANK) | 784 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 785 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 786 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 787 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 788 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 789 PIPE_CONFIG(ADDR_SURF_P4_8x16); 790 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 791 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 792 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 796 NUM_BANKS(ADDR_SURF_16_BANK) | 797 TILE_SPLIT(split_equal_to_row_size); 798 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 799 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 800 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 801 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 804 NUM_BANKS(ADDR_SURF_16_BANK) | 805 TILE_SPLIT(split_equal_to_row_size); 806 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 807 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 808 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 809 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 810 NUM_BANKS(ADDR_SURF_16_BANK) | 811 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 812 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 813 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 814 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 815 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 816 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 818 NUM_BANKS(ADDR_SURF_16_BANK) | 819 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 820 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 821 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 822 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 823 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 824 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 825 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 826 NUM_BANKS(ADDR_SURF_16_BANK) | 827 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 830 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 831 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 832 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 833 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 834 NUM_BANKS(ADDR_SURF_16_BANK) | 835 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 836 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 837 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 838 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 839 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 840 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 842 NUM_BANKS(ADDR_SURF_8_BANK) | 843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 846 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 847 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 848 } else if (adev->asic_type == CHIP_HAINAN) { 849 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 850 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 851 PIPE_CONFIG(ADDR_SURF_P2) | 852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 856 NUM_BANKS(ADDR_SURF_16_BANK); 857 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 858 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 859 PIPE_CONFIG(ADDR_SURF_P2) | 860 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 864 NUM_BANKS(ADDR_SURF_16_BANK); 865 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 866 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 867 PIPE_CONFIG(ADDR_SURF_P2) | 868 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 869 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 870 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 871 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 872 NUM_BANKS(ADDR_SURF_16_BANK); 873 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 874 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 875 PIPE_CONFIG(ADDR_SURF_P2) | 876 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 877 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 878 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 879 NUM_BANKS(ADDR_SURF_8_BANK) | 880 TILE_SPLIT(split_equal_to_row_size); 881 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 882 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 883 PIPE_CONFIG(ADDR_SURF_P2); 884 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 885 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 886 PIPE_CONFIG(ADDR_SURF_P2) | 887 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 891 NUM_BANKS(ADDR_SURF_8_BANK); 892 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 893 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 894 PIPE_CONFIG(ADDR_SURF_P2) | 895 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 896 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 897 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 898 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 899 NUM_BANKS(ADDR_SURF_8_BANK); 900 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 901 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 902 PIPE_CONFIG(ADDR_SURF_P2) | 903 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 904 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 905 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 906 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 907 NUM_BANKS(ADDR_SURF_4_BANK); 908 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 909 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 910 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 911 PIPE_CONFIG(ADDR_SURF_P2); 912 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 913 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 914 PIPE_CONFIG(ADDR_SURF_P2) | 915 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 916 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 919 NUM_BANKS(ADDR_SURF_16_BANK); 920 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 921 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 922 PIPE_CONFIG(ADDR_SURF_P2) | 923 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 924 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 925 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 926 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 927 NUM_BANKS(ADDR_SURF_16_BANK); 928 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 929 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 930 PIPE_CONFIG(ADDR_SURF_P2) | 931 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 932 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 933 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 934 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 935 NUM_BANKS(ADDR_SURF_16_BANK); 936 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 937 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 938 PIPE_CONFIG(ADDR_SURF_P2); 939 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 940 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 941 PIPE_CONFIG(ADDR_SURF_P2) | 942 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 943 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 944 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 945 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 946 NUM_BANKS(ADDR_SURF_16_BANK); 947 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 948 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 949 PIPE_CONFIG(ADDR_SURF_P2) | 950 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 951 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 952 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 953 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 954 NUM_BANKS(ADDR_SURF_16_BANK); 955 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 956 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 957 PIPE_CONFIG(ADDR_SURF_P2) | 958 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 959 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 960 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 961 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 962 NUM_BANKS(ADDR_SURF_16_BANK); 963 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 964 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 965 PIPE_CONFIG(ADDR_SURF_P2) | 966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 969 NUM_BANKS(ADDR_SURF_16_BANK) | 970 TILE_SPLIT(split_equal_to_row_size); 971 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 972 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 973 PIPE_CONFIG(ADDR_SURF_P2); 974 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 975 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 976 PIPE_CONFIG(ADDR_SURF_P2) | 977 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 978 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 979 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 980 NUM_BANKS(ADDR_SURF_16_BANK) | 981 TILE_SPLIT(split_equal_to_row_size); 982 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 983 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 984 PIPE_CONFIG(ADDR_SURF_P2) | 985 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 986 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 987 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 988 NUM_BANKS(ADDR_SURF_16_BANK) | 989 TILE_SPLIT(split_equal_to_row_size); 990 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 991 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 992 PIPE_CONFIG(ADDR_SURF_P2) | 993 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 994 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 995 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 996 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 997 NUM_BANKS(ADDR_SURF_8_BANK); 998 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 999 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1000 PIPE_CONFIG(ADDR_SURF_P2) | 1001 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1002 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1003 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1004 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1005 NUM_BANKS(ADDR_SURF_8_BANK); 1006 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1007 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1008 PIPE_CONFIG(ADDR_SURF_P2) | 1009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1013 NUM_BANKS(ADDR_SURF_8_BANK); 1014 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1015 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1016 PIPE_CONFIG(ADDR_SURF_P2) | 1017 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1018 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1021 NUM_BANKS(ADDR_SURF_8_BANK); 1022 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1023 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1024 PIPE_CONFIG(ADDR_SURF_P2) | 1025 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1026 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1029 NUM_BANKS(ADDR_SURF_4_BANK); 1030 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1031 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1032 PIPE_CONFIG(ADDR_SURF_P2) | 1033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1034 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1037 NUM_BANKS(ADDR_SURF_4_BANK); 1038 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1039 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1040 PIPE_CONFIG(ADDR_SURF_P2) | 1041 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1042 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1043 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1044 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1045 NUM_BANKS(ADDR_SURF_4_BANK); 1046 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1047 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1048 PIPE_CONFIG(ADDR_SURF_P2) | 1049 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1053 NUM_BANKS(ADDR_SURF_4_BANK); 1054 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1055 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1056 PIPE_CONFIG(ADDR_SURF_P2) | 1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1058 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1061 NUM_BANKS(ADDR_SURF_4_BANK); 1062 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1063 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P2) | 1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1069 NUM_BANKS(ADDR_SURF_4_BANK); 1070 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1071 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1072 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1073 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1074 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1075 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1076 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1077 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1078 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1079 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1080 NUM_BANKS(ADDR_SURF_16_BANK); 1081 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1082 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1084 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1085 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1086 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1087 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1088 NUM_BANKS(ADDR_SURF_16_BANK); 1089 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1090 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1091 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1092 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1093 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1094 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1095 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1096 NUM_BANKS(ADDR_SURF_16_BANK); 1097 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1098 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1099 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1103 NUM_BANKS(ADDR_SURF_4_BANK) | 1104 TILE_SPLIT(split_equal_to_row_size); 1105 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1106 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1108 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1109 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1110 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1115 NUM_BANKS(ADDR_SURF_2_BANK); 1116 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1117 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1119 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1123 NUM_BANKS(ADDR_SURF_2_BANK); 1124 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1125 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1126 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1127 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1128 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1131 NUM_BANKS(ADDR_SURF_2_BANK); 1132 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1133 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1134 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1135 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1136 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1137 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1138 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1139 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1140 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1143 NUM_BANKS(ADDR_SURF_16_BANK); 1144 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1145 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1146 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1147 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1148 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1151 NUM_BANKS(ADDR_SURF_16_BANK); 1152 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1153 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1154 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1159 NUM_BANKS(ADDR_SURF_16_BANK); 1160 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1161 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1162 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1163 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1164 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1165 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1166 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1170 NUM_BANKS(ADDR_SURF_16_BANK); 1171 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1172 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1173 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1174 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1175 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1178 NUM_BANKS(ADDR_SURF_16_BANK); 1179 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1180 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1181 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1182 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1183 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1184 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1185 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1186 NUM_BANKS(ADDR_SURF_16_BANK); 1187 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1188 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1189 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1193 NUM_BANKS(ADDR_SURF_16_BANK) | 1194 TILE_SPLIT(split_equal_to_row_size); 1195 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1196 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1197 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1198 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1199 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1200 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1201 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1204 NUM_BANKS(ADDR_SURF_16_BANK) | 1205 TILE_SPLIT(split_equal_to_row_size); 1206 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1207 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1208 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1212 NUM_BANKS(ADDR_SURF_16_BANK) | 1213 TILE_SPLIT(split_equal_to_row_size); 1214 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1215 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1216 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1218 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1221 NUM_BANKS(ADDR_SURF_4_BANK); 1222 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1223 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1224 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1226 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1227 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1228 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1229 NUM_BANKS(ADDR_SURF_4_BANK); 1230 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1231 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1232 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1234 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1235 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1236 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1237 NUM_BANKS(ADDR_SURF_2_BANK); 1238 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1239 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1240 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1242 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1243 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1244 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1245 NUM_BANKS(ADDR_SURF_2_BANK); 1246 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1247 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1250 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1253 NUM_BANKS(ADDR_SURF_2_BANK); 1254 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1255 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1258 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1261 NUM_BANKS(ADDR_SURF_2_BANK); 1262 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1263 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1264 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1266 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1269 NUM_BANKS(ADDR_SURF_2_BANK); 1270 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1271 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1272 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1273 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1274 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1277 NUM_BANKS(ADDR_SURF_2_BANK); 1278 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1279 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1280 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1281 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1282 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1285 NUM_BANKS(ADDR_SURF_2_BANK); 1286 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1287 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1288 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1289 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1290 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1293 NUM_BANKS(ADDR_SURF_2_BANK); 1294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1295 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1296 } else { 1297 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1298 } 1299 } 1300 1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1302 u32 sh_num, u32 instance) 1303 { 1304 u32 data; 1305 1306 if (instance == 0xffffffff) 1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1308 else 1309 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1310 1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1312 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1313 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1314 else if (se_num == 0xffffffff) 1315 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1316 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1317 else if (sh_num == 0xffffffff) 1318 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1320 else 1321 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1323 WREG32(mmGRBM_GFX_INDEX, data); 1324 } 1325 1326 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1327 { 1328 u32 data, mask; 1329 1330 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1331 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1332 1333 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1334 1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1336 adev->gfx.config.max_sh_per_se); 1337 1338 return ~data & mask; 1339 } 1340 1341 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1342 { 1343 switch (adev->asic_type) { 1344 case CHIP_TAHITI: 1345 case CHIP_PITCAIRN: 1346 *rconf |= 1347 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1348 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1349 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1350 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1351 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1352 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1353 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1354 break; 1355 case CHIP_VERDE: 1356 *rconf |= 1357 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1358 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1359 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1360 break; 1361 case CHIP_OLAND: 1362 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1363 break; 1364 case CHIP_HAINAN: 1365 *rconf |= 0x0; 1366 break; 1367 default: 1368 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1369 break; 1370 } 1371 } 1372 1373 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1374 u32 raster_config, unsigned rb_mask, 1375 unsigned num_rb) 1376 { 1377 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1378 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1379 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1380 unsigned rb_per_se = num_rb / num_se; 1381 unsigned se_mask[4]; 1382 unsigned se; 1383 1384 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1385 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1386 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1387 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1388 1389 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1390 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1391 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1392 1393 for (se = 0; se < num_se; se++) { 1394 unsigned raster_config_se = raster_config; 1395 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1396 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1397 int idx = (se / 2) * 2; 1398 1399 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1400 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1401 1402 if (!se_mask[idx]) 1403 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1404 else 1405 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1406 } 1407 1408 pkr0_mask &= rb_mask; 1409 pkr1_mask &= rb_mask; 1410 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1411 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1412 1413 if (!pkr0_mask) 1414 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1415 else 1416 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1417 } 1418 1419 if (rb_per_se >= 2) { 1420 unsigned rb0_mask = 1 << (se * rb_per_se); 1421 unsigned rb1_mask = rb0_mask << 1; 1422 1423 rb0_mask &= rb_mask; 1424 rb1_mask &= rb_mask; 1425 if (!rb0_mask || !rb1_mask) { 1426 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1427 1428 if (!rb0_mask) 1429 raster_config_se |= 1430 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1431 else 1432 raster_config_se |= 1433 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1434 } 1435 1436 if (rb_per_se > 2) { 1437 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1438 rb1_mask = rb0_mask << 1; 1439 rb0_mask &= rb_mask; 1440 rb1_mask &= rb_mask; 1441 if (!rb0_mask || !rb1_mask) { 1442 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1443 1444 if (!rb0_mask) 1445 raster_config_se |= 1446 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1447 else 1448 raster_config_se |= 1449 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1450 } 1451 } 1452 } 1453 1454 /* GRBM_GFX_INDEX has a different offset on SI */ 1455 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1456 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1457 } 1458 1459 /* GRBM_GFX_INDEX has a different offset on SI */ 1460 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1461 } 1462 1463 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1464 { 1465 int i, j; 1466 u32 data; 1467 u32 raster_config = 0; 1468 u32 active_rbs = 0; 1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1470 adev->gfx.config.max_sh_per_se; 1471 unsigned num_rb_pipes; 1472 1473 mutex_lock(&adev->grbm_idx_mutex); 1474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1476 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1477 data = gfx_v6_0_get_rb_active_bitmap(adev); 1478 active_rbs |= data << 1479 ((i * adev->gfx.config.max_sh_per_se + j) * 1480 rb_bitmap_width_per_sh); 1481 } 1482 } 1483 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1484 1485 adev->gfx.config.backend_enable_mask = active_rbs; 1486 adev->gfx.config.num_rbs = hweight32(active_rbs); 1487 1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1489 adev->gfx.config.max_shader_engines, 16); 1490 1491 gfx_v6_0_raster_config(adev, &raster_config); 1492 1493 if (!adev->gfx.config.backend_enable_mask || 1494 adev->gfx.config.num_rbs >= num_rb_pipes) 1495 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1496 else 1497 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1498 adev->gfx.config.backend_enable_mask, 1499 num_rb_pipes); 1500 1501 /* cache the values for userspace */ 1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1504 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1505 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1506 RREG32(mmCC_RB_BACKEND_DISABLE); 1507 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1508 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1509 adev->gfx.config.rb_config[i][j].raster_config = 1510 RREG32(mmPA_SC_RASTER_CONFIG); 1511 } 1512 } 1513 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1514 mutex_unlock(&adev->grbm_idx_mutex); 1515 } 1516 1517 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1518 u32 bitmap) 1519 { 1520 u32 data; 1521 1522 if (!bitmap) 1523 return; 1524 1525 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1526 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1527 1528 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1529 } 1530 1531 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1532 { 1533 u32 data, mask; 1534 1535 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1536 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1537 1538 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1539 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1540 } 1541 1542 1543 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1544 { 1545 int i, j, k; 1546 u32 data, mask; 1547 u32 active_cu = 0; 1548 1549 mutex_lock(&adev->grbm_idx_mutex); 1550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1552 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1553 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1554 active_cu = gfx_v6_0_get_cu_enabled(adev); 1555 1556 mask = 1; 1557 for (k = 0; k < 16; k++) { 1558 mask <<= k; 1559 if (active_cu & mask) { 1560 data &= ~mask; 1561 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1562 break; 1563 } 1564 } 1565 } 1566 } 1567 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1568 mutex_unlock(&adev->grbm_idx_mutex); 1569 } 1570 1571 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1572 { 1573 adev->gfx.config.double_offchip_lds_buf = 0; 1574 } 1575 1576 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1577 { 1578 u32 gb_addr_config = 0; 1579 u32 mc_arb_ramcfg; 1580 u32 sx_debug_1; 1581 u32 hdp_host_path_cntl; 1582 u32 tmp; 1583 1584 switch (adev->asic_type) { 1585 case CHIP_TAHITI: 1586 adev->gfx.config.max_shader_engines = 2; 1587 adev->gfx.config.max_tile_pipes = 12; 1588 adev->gfx.config.max_cu_per_sh = 8; 1589 adev->gfx.config.max_sh_per_se = 2; 1590 adev->gfx.config.max_backends_per_se = 4; 1591 adev->gfx.config.max_texture_channel_caches = 12; 1592 adev->gfx.config.max_gprs = 256; 1593 adev->gfx.config.max_gs_threads = 32; 1594 adev->gfx.config.max_hw_contexts = 8; 1595 1596 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1597 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1598 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1599 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1600 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1601 break; 1602 case CHIP_PITCAIRN: 1603 adev->gfx.config.max_shader_engines = 2; 1604 adev->gfx.config.max_tile_pipes = 8; 1605 adev->gfx.config.max_cu_per_sh = 5; 1606 adev->gfx.config.max_sh_per_se = 2; 1607 adev->gfx.config.max_backends_per_se = 4; 1608 adev->gfx.config.max_texture_channel_caches = 8; 1609 adev->gfx.config.max_gprs = 256; 1610 adev->gfx.config.max_gs_threads = 32; 1611 adev->gfx.config.max_hw_contexts = 8; 1612 1613 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1614 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1615 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1616 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1617 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1618 break; 1619 case CHIP_VERDE: 1620 adev->gfx.config.max_shader_engines = 1; 1621 adev->gfx.config.max_tile_pipes = 4; 1622 adev->gfx.config.max_cu_per_sh = 5; 1623 adev->gfx.config.max_sh_per_se = 2; 1624 adev->gfx.config.max_backends_per_se = 4; 1625 adev->gfx.config.max_texture_channel_caches = 4; 1626 adev->gfx.config.max_gprs = 256; 1627 adev->gfx.config.max_gs_threads = 32; 1628 adev->gfx.config.max_hw_contexts = 8; 1629 1630 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1631 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1632 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1633 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1634 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1635 break; 1636 case CHIP_OLAND: 1637 adev->gfx.config.max_shader_engines = 1; 1638 adev->gfx.config.max_tile_pipes = 4; 1639 adev->gfx.config.max_cu_per_sh = 6; 1640 adev->gfx.config.max_sh_per_se = 1; 1641 adev->gfx.config.max_backends_per_se = 2; 1642 adev->gfx.config.max_texture_channel_caches = 4; 1643 adev->gfx.config.max_gprs = 256; 1644 adev->gfx.config.max_gs_threads = 16; 1645 adev->gfx.config.max_hw_contexts = 8; 1646 1647 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1648 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1649 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1650 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1651 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1652 break; 1653 case CHIP_HAINAN: 1654 adev->gfx.config.max_shader_engines = 1; 1655 adev->gfx.config.max_tile_pipes = 4; 1656 adev->gfx.config.max_cu_per_sh = 5; 1657 adev->gfx.config.max_sh_per_se = 1; 1658 adev->gfx.config.max_backends_per_se = 1; 1659 adev->gfx.config.max_texture_channel_caches = 2; 1660 adev->gfx.config.max_gprs = 256; 1661 adev->gfx.config.max_gs_threads = 16; 1662 adev->gfx.config.max_hw_contexts = 8; 1663 1664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1665 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1666 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1667 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1668 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1669 break; 1670 default: 1671 BUG(); 1672 break; 1673 } 1674 1675 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1676 WREG32(mmSRBM_INT_CNTL, 1); 1677 WREG32(mmSRBM_INT_ACK, 1); 1678 1679 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1680 1681 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1682 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1683 1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1685 adev->gfx.config.mem_max_burst_length_bytes = 256; 1686 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1687 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1688 if (adev->gfx.config.mem_row_size_in_kb > 4) 1689 adev->gfx.config.mem_row_size_in_kb = 4; 1690 adev->gfx.config.shader_engine_tile_size = 32; 1691 adev->gfx.config.num_gpus = 1; 1692 adev->gfx.config.multi_gpu_tile_size = 64; 1693 1694 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1695 switch (adev->gfx.config.mem_row_size_in_kb) { 1696 case 1: 1697 default: 1698 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1699 break; 1700 case 2: 1701 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1702 break; 1703 case 4: 1704 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1705 break; 1706 } 1707 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1708 if (adev->gfx.config.max_shader_engines == 2) 1709 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1710 adev->gfx.config.gb_addr_config = gb_addr_config; 1711 1712 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1713 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1714 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1715 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1716 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1717 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1718 1719 #if 0 1720 if (adev->has_uvd) { 1721 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1722 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1723 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1724 } 1725 #endif 1726 gfx_v6_0_tiling_mode_table_init(adev); 1727 1728 gfx_v6_0_setup_rb(adev); 1729 1730 gfx_v6_0_setup_spi(adev); 1731 1732 gfx_v6_0_get_cu_info(adev); 1733 gfx_v6_0_config_init(adev); 1734 1735 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1736 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1737 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1738 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1739 1740 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1741 WREG32(mmSX_DEBUG_1, sx_debug_1); 1742 1743 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1744 1745 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1746 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1747 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1748 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1749 1750 WREG32(mmVGT_NUM_INSTANCES, 1); 1751 WREG32(mmCP_PERFMON_CNTL, 0); 1752 WREG32(mmSQ_CONFIG, 0); 1753 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1754 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1755 1756 WREG32(mmVGT_CACHE_INVALIDATION, 1757 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1758 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1759 1760 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1761 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1762 1763 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1764 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1765 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1766 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1767 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1768 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1769 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1770 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1771 1772 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1773 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1774 1775 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1776 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1777 1778 udelay(50); 1779 } 1780 1781 1782 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1783 { 1784 adev->gfx.scratch.num_reg = 8; 1785 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1786 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1787 } 1788 1789 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1790 { 1791 struct amdgpu_device *adev = ring->adev; 1792 uint32_t scratch; 1793 uint32_t tmp = 0; 1794 unsigned i; 1795 int r; 1796 1797 r = amdgpu_gfx_scratch_get(adev, &scratch); 1798 if (r) 1799 return r; 1800 1801 WREG32(scratch, 0xCAFEDEAD); 1802 1803 r = amdgpu_ring_alloc(ring, 3); 1804 if (r) 1805 goto error_free_scratch; 1806 1807 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1808 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1809 amdgpu_ring_write(ring, 0xDEADBEEF); 1810 amdgpu_ring_commit(ring); 1811 1812 for (i = 0; i < adev->usec_timeout; i++) { 1813 tmp = RREG32(scratch); 1814 if (tmp == 0xDEADBEEF) 1815 break; 1816 udelay(1); 1817 } 1818 1819 if (i >= adev->usec_timeout) 1820 r = -ETIMEDOUT; 1821 1822 error_free_scratch: 1823 amdgpu_gfx_scratch_free(adev, scratch); 1824 return r; 1825 } 1826 1827 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1828 { 1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1830 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1831 EVENT_INDEX(0)); 1832 } 1833 1834 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1835 u64 seq, unsigned flags) 1836 { 1837 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1838 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1839 /* flush read cache over gart */ 1840 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1841 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1842 amdgpu_ring_write(ring, 0); 1843 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1844 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1845 PACKET3_TC_ACTION_ENA | 1846 PACKET3_SH_KCACHE_ACTION_ENA | 1847 PACKET3_SH_ICACHE_ACTION_ENA); 1848 amdgpu_ring_write(ring, 0xFFFFFFFF); 1849 amdgpu_ring_write(ring, 0); 1850 amdgpu_ring_write(ring, 10); /* poll interval */ 1851 /* EVENT_WRITE_EOP - flush caches, send int */ 1852 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1853 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1854 amdgpu_ring_write(ring, addr & 0xfffffffc); 1855 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1856 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1857 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1858 amdgpu_ring_write(ring, lower_32_bits(seq)); 1859 amdgpu_ring_write(ring, upper_32_bits(seq)); 1860 } 1861 1862 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1863 struct amdgpu_job *job, 1864 struct amdgpu_ib *ib, 1865 uint32_t flags) 1866 { 1867 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1868 u32 header, control = 0; 1869 1870 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1871 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1872 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1873 amdgpu_ring_write(ring, 0); 1874 } 1875 1876 if (ib->flags & AMDGPU_IB_FLAG_CE) 1877 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1878 else 1879 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1880 1881 control |= ib->length_dw | (vmid << 24); 1882 1883 amdgpu_ring_write(ring, header); 1884 amdgpu_ring_write(ring, 1885 #ifdef __BIG_ENDIAN 1886 (2 << 0) | 1887 #endif 1888 (ib->gpu_addr & 0xFFFFFFFC)); 1889 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1890 amdgpu_ring_write(ring, control); 1891 } 1892 1893 /** 1894 * gfx_v6_0_ring_test_ib - basic ring IB test 1895 * 1896 * @ring: amdgpu_ring structure holding ring information 1897 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1898 * 1899 * Allocate an IB and execute it on the gfx ring (SI). 1900 * Provides a basic gfx ring test to verify that IBs are working. 1901 * Returns 0 on success, error on failure. 1902 */ 1903 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1904 { 1905 struct amdgpu_device *adev = ring->adev; 1906 struct amdgpu_ib ib; 1907 struct dma_fence *f = NULL; 1908 uint32_t scratch; 1909 uint32_t tmp = 0; 1910 long r; 1911 1912 r = amdgpu_gfx_scratch_get(adev, &scratch); 1913 if (r) 1914 return r; 1915 1916 WREG32(scratch, 0xCAFEDEAD); 1917 memset(&ib, 0, sizeof(ib)); 1918 r = amdgpu_ib_get(adev, NULL, 256, 1919 AMDGPU_IB_POOL_DIRECT, &ib); 1920 if (r) 1921 goto err1; 1922 1923 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1924 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1925 ib.ptr[2] = 0xDEADBEEF; 1926 ib.length_dw = 3; 1927 1928 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1929 if (r) 1930 goto err2; 1931 1932 r = dma_fence_wait_timeout(f, false, timeout); 1933 if (r == 0) { 1934 r = -ETIMEDOUT; 1935 goto err2; 1936 } else if (r < 0) { 1937 goto err2; 1938 } 1939 tmp = RREG32(scratch); 1940 if (tmp == 0xDEADBEEF) 1941 r = 0; 1942 else 1943 r = -EINVAL; 1944 1945 err2: 1946 amdgpu_ib_free(adev, &ib, NULL); 1947 dma_fence_put(f); 1948 err1: 1949 amdgpu_gfx_scratch_free(adev, scratch); 1950 return r; 1951 } 1952 1953 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1954 { 1955 if (enable) { 1956 WREG32(mmCP_ME_CNTL, 0); 1957 } else { 1958 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1959 CP_ME_CNTL__PFP_HALT_MASK | 1960 CP_ME_CNTL__CE_HALT_MASK)); 1961 WREG32(mmSCRATCH_UMSK, 0); 1962 } 1963 udelay(50); 1964 } 1965 1966 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1967 { 1968 unsigned i; 1969 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1970 const struct gfx_firmware_header_v1_0 *ce_hdr; 1971 const struct gfx_firmware_header_v1_0 *me_hdr; 1972 const __le32 *fw_data; 1973 u32 fw_size; 1974 1975 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1976 return -EINVAL; 1977 1978 gfx_v6_0_cp_gfx_enable(adev, false); 1979 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1980 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1981 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1982 1983 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1984 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1985 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1986 1987 /* PFP */ 1988 fw_data = (const __le32 *) 1989 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1990 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1991 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1992 for (i = 0; i < fw_size; i++) 1993 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1994 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1995 1996 /* CE */ 1997 fw_data = (const __le32 *) 1998 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1999 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2000 WREG32(mmCP_CE_UCODE_ADDR, 0); 2001 for (i = 0; i < fw_size; i++) 2002 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2003 WREG32(mmCP_CE_UCODE_ADDR, 0); 2004 2005 /* ME */ 2006 fw_data = (const __be32 *) 2007 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2008 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2009 WREG32(mmCP_ME_RAM_WADDR, 0); 2010 for (i = 0; i < fw_size; i++) 2011 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2012 WREG32(mmCP_ME_RAM_WADDR, 0); 2013 2014 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2015 WREG32(mmCP_CE_UCODE_ADDR, 0); 2016 WREG32(mmCP_ME_RAM_WADDR, 0); 2017 WREG32(mmCP_ME_RAM_RADDR, 0); 2018 return 0; 2019 } 2020 2021 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2022 { 2023 const struct cs_section_def *sect = NULL; 2024 const struct cs_extent_def *ext = NULL; 2025 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2026 int r, i; 2027 2028 r = amdgpu_ring_alloc(ring, 7 + 4); 2029 if (r) { 2030 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2031 return r; 2032 } 2033 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2034 amdgpu_ring_write(ring, 0x1); 2035 amdgpu_ring_write(ring, 0x0); 2036 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2037 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2038 amdgpu_ring_write(ring, 0); 2039 amdgpu_ring_write(ring, 0); 2040 2041 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2042 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2043 amdgpu_ring_write(ring, 0xc000); 2044 amdgpu_ring_write(ring, 0xe000); 2045 amdgpu_ring_commit(ring); 2046 2047 gfx_v6_0_cp_gfx_enable(adev, true); 2048 2049 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2050 if (r) { 2051 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2052 return r; 2053 } 2054 2055 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2056 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2057 2058 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2059 for (ext = sect->section; ext->extent != NULL; ++ext) { 2060 if (sect->id == SECT_CONTEXT) { 2061 amdgpu_ring_write(ring, 2062 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2063 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2064 for (i = 0; i < ext->reg_count; i++) 2065 amdgpu_ring_write(ring, ext->extent[i]); 2066 } 2067 } 2068 } 2069 2070 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2071 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2072 2073 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2074 amdgpu_ring_write(ring, 0); 2075 2076 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2077 amdgpu_ring_write(ring, 0x00000316); 2078 amdgpu_ring_write(ring, 0x0000000e); 2079 amdgpu_ring_write(ring, 0x00000010); 2080 2081 amdgpu_ring_commit(ring); 2082 2083 return 0; 2084 } 2085 2086 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2087 { 2088 struct amdgpu_ring *ring; 2089 u32 tmp; 2090 u32 rb_bufsz; 2091 int r; 2092 u64 rptr_addr; 2093 2094 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2095 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2096 2097 /* Set the write pointer delay */ 2098 WREG32(mmCP_RB_WPTR_DELAY, 0); 2099 2100 WREG32(mmCP_DEBUG, 0); 2101 WREG32(mmSCRATCH_ADDR, 0); 2102 2103 /* ring 0 - compute and gfx */ 2104 /* Set ring buffer size */ 2105 ring = &adev->gfx.gfx_ring[0]; 2106 rb_bufsz = order_base_2(ring->ring_size / 8); 2107 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2108 2109 #ifdef __BIG_ENDIAN 2110 tmp |= BUF_SWAP_32BIT; 2111 #endif 2112 WREG32(mmCP_RB0_CNTL, tmp); 2113 2114 /* Initialize the ring buffer's read and write pointers */ 2115 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2116 ring->wptr = 0; 2117 WREG32(mmCP_RB0_WPTR, ring->wptr); 2118 2119 /* set the wb address whether it's enabled or not */ 2120 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2121 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2122 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2123 2124 WREG32(mmSCRATCH_UMSK, 0); 2125 2126 mdelay(1); 2127 WREG32(mmCP_RB0_CNTL, tmp); 2128 2129 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2130 2131 /* start the rings */ 2132 gfx_v6_0_cp_gfx_start(adev); 2133 r = amdgpu_ring_test_helper(ring); 2134 if (r) 2135 return r; 2136 2137 return 0; 2138 } 2139 2140 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2141 { 2142 return ring->adev->wb.wb[ring->rptr_offs]; 2143 } 2144 2145 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2146 { 2147 struct amdgpu_device *adev = ring->adev; 2148 2149 if (ring == &adev->gfx.gfx_ring[0]) 2150 return RREG32(mmCP_RB0_WPTR); 2151 else if (ring == &adev->gfx.compute_ring[0]) 2152 return RREG32(mmCP_RB1_WPTR); 2153 else if (ring == &adev->gfx.compute_ring[1]) 2154 return RREG32(mmCP_RB2_WPTR); 2155 else 2156 BUG(); 2157 } 2158 2159 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2160 { 2161 struct amdgpu_device *adev = ring->adev; 2162 2163 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2164 (void)RREG32(mmCP_RB0_WPTR); 2165 } 2166 2167 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2168 { 2169 struct amdgpu_device *adev = ring->adev; 2170 2171 if (ring == &adev->gfx.compute_ring[0]) { 2172 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2173 (void)RREG32(mmCP_RB1_WPTR); 2174 } else if (ring == &adev->gfx.compute_ring[1]) { 2175 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2176 (void)RREG32(mmCP_RB2_WPTR); 2177 } else { 2178 BUG(); 2179 } 2180 2181 } 2182 2183 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2184 { 2185 struct amdgpu_ring *ring; 2186 u32 tmp; 2187 u32 rb_bufsz; 2188 int i, r; 2189 u64 rptr_addr; 2190 2191 /* ring1 - compute only */ 2192 /* Set ring buffer size */ 2193 2194 ring = &adev->gfx.compute_ring[0]; 2195 rb_bufsz = order_base_2(ring->ring_size / 8); 2196 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2197 #ifdef __BIG_ENDIAN 2198 tmp |= BUF_SWAP_32BIT; 2199 #endif 2200 WREG32(mmCP_RB1_CNTL, tmp); 2201 2202 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2203 ring->wptr = 0; 2204 WREG32(mmCP_RB1_WPTR, ring->wptr); 2205 2206 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2207 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2208 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2209 2210 mdelay(1); 2211 WREG32(mmCP_RB1_CNTL, tmp); 2212 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2213 2214 ring = &adev->gfx.compute_ring[1]; 2215 rb_bufsz = order_base_2(ring->ring_size / 8); 2216 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2217 #ifdef __BIG_ENDIAN 2218 tmp |= BUF_SWAP_32BIT; 2219 #endif 2220 WREG32(mmCP_RB2_CNTL, tmp); 2221 2222 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2223 ring->wptr = 0; 2224 WREG32(mmCP_RB2_WPTR, ring->wptr); 2225 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2226 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2227 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2228 2229 mdelay(1); 2230 WREG32(mmCP_RB2_CNTL, tmp); 2231 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2232 2233 2234 for (i = 0; i < 2; i++) { 2235 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2236 if (r) 2237 return r; 2238 } 2239 2240 return 0; 2241 } 2242 2243 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2244 { 2245 gfx_v6_0_cp_gfx_enable(adev, enable); 2246 } 2247 2248 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2249 { 2250 return gfx_v6_0_cp_gfx_load_microcode(adev); 2251 } 2252 2253 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2254 bool enable) 2255 { 2256 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2257 u32 mask; 2258 int i; 2259 2260 if (enable) 2261 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2262 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2263 else 2264 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2265 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2266 WREG32(mmCP_INT_CNTL_RING0, tmp); 2267 2268 if (!enable) { 2269 /* read a gfx register */ 2270 tmp = RREG32(mmDB_DEPTH_INFO); 2271 2272 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2273 for (i = 0; i < adev->usec_timeout; i++) { 2274 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2275 break; 2276 udelay(1); 2277 } 2278 } 2279 } 2280 2281 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2282 { 2283 int r; 2284 2285 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2286 2287 r = gfx_v6_0_cp_load_microcode(adev); 2288 if (r) 2289 return r; 2290 2291 r = gfx_v6_0_cp_gfx_resume(adev); 2292 if (r) 2293 return r; 2294 r = gfx_v6_0_cp_compute_resume(adev); 2295 if (r) 2296 return r; 2297 2298 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2299 2300 return 0; 2301 } 2302 2303 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2304 { 2305 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2306 uint32_t seq = ring->fence_drv.sync_seq; 2307 uint64_t addr = ring->fence_drv.gpu_addr; 2308 2309 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2310 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2311 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2312 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2313 amdgpu_ring_write(ring, addr & 0xfffffffc); 2314 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2315 amdgpu_ring_write(ring, seq); 2316 amdgpu_ring_write(ring, 0xffffffff); 2317 amdgpu_ring_write(ring, 4); /* poll interval */ 2318 2319 if (usepfp) { 2320 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2321 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2322 amdgpu_ring_write(ring, 0); 2323 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2324 amdgpu_ring_write(ring, 0); 2325 } 2326 } 2327 2328 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2329 unsigned vmid, uint64_t pd_addr) 2330 { 2331 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2332 2333 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2334 2335 /* wait for the invalidate to complete */ 2336 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2337 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2338 WAIT_REG_MEM_ENGINE(0))); /* me */ 2339 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2340 amdgpu_ring_write(ring, 0); 2341 amdgpu_ring_write(ring, 0); /* ref */ 2342 amdgpu_ring_write(ring, 0); /* mask */ 2343 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2344 2345 if (usepfp) { 2346 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2347 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2348 amdgpu_ring_write(ring, 0x0); 2349 2350 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2352 amdgpu_ring_write(ring, 0); 2353 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2354 amdgpu_ring_write(ring, 0); 2355 } 2356 } 2357 2358 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2359 uint32_t reg, uint32_t val) 2360 { 2361 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2362 2363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2364 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2365 WRITE_DATA_DST_SEL(0))); 2366 amdgpu_ring_write(ring, reg); 2367 amdgpu_ring_write(ring, 0); 2368 amdgpu_ring_write(ring, val); 2369 } 2370 2371 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2372 { 2373 const u32 *src_ptr; 2374 volatile u32 *dst_ptr; 2375 u32 dws; 2376 u64 reg_list_mc_addr; 2377 const struct cs_section_def *cs_data; 2378 int r; 2379 2380 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2381 adev->gfx.rlc.reg_list_size = 2382 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2383 2384 adev->gfx.rlc.cs_data = si_cs_data; 2385 src_ptr = adev->gfx.rlc.reg_list; 2386 dws = adev->gfx.rlc.reg_list_size; 2387 cs_data = adev->gfx.rlc.cs_data; 2388 2389 if (src_ptr) { 2390 /* init save restore block */ 2391 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2392 if (r) 2393 return r; 2394 } 2395 2396 if (cs_data) { 2397 /* clear state block */ 2398 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2399 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2400 2401 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2402 AMDGPU_GEM_DOMAIN_VRAM, 2403 &adev->gfx.rlc.clear_state_obj, 2404 &adev->gfx.rlc.clear_state_gpu_addr, 2405 (void **)&adev->gfx.rlc.cs_ptr); 2406 if (r) { 2407 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2408 amdgpu_gfx_rlc_fini(adev); 2409 return r; 2410 } 2411 2412 /* set up the cs buffer */ 2413 dst_ptr = adev->gfx.rlc.cs_ptr; 2414 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2415 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2416 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2417 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2418 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2419 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2420 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2421 } 2422 2423 return 0; 2424 } 2425 2426 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2427 { 2428 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2429 2430 if (!enable) { 2431 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2432 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2433 } 2434 } 2435 2436 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2437 { 2438 int i; 2439 2440 for (i = 0; i < adev->usec_timeout; i++) { 2441 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2442 break; 2443 udelay(1); 2444 } 2445 2446 for (i = 0; i < adev->usec_timeout; i++) { 2447 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2448 break; 2449 udelay(1); 2450 } 2451 } 2452 2453 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2454 { 2455 u32 tmp; 2456 2457 tmp = RREG32(mmRLC_CNTL); 2458 if (tmp != rlc) 2459 WREG32(mmRLC_CNTL, rlc); 2460 } 2461 2462 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2463 { 2464 u32 data, orig; 2465 2466 orig = data = RREG32(mmRLC_CNTL); 2467 2468 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2469 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2470 WREG32(mmRLC_CNTL, data); 2471 2472 gfx_v6_0_wait_for_rlc_serdes(adev); 2473 } 2474 2475 return orig; 2476 } 2477 2478 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2479 { 2480 WREG32(mmRLC_CNTL, 0); 2481 2482 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2483 gfx_v6_0_wait_for_rlc_serdes(adev); 2484 } 2485 2486 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2487 { 2488 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2489 2490 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2491 2492 udelay(50); 2493 } 2494 2495 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2496 { 2497 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2498 udelay(50); 2499 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2500 udelay(50); 2501 } 2502 2503 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2504 { 2505 u32 tmp; 2506 2507 /* Enable LBPW only for DDR3 */ 2508 tmp = RREG32(mmMC_SEQ_MISC0); 2509 if ((tmp & 0xF0000000) == 0xB0000000) 2510 return true; 2511 return false; 2512 } 2513 2514 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2515 { 2516 } 2517 2518 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2519 { 2520 u32 i; 2521 const struct rlc_firmware_header_v1_0 *hdr; 2522 const __le32 *fw_data; 2523 u32 fw_size; 2524 2525 2526 if (!adev->gfx.rlc_fw) 2527 return -EINVAL; 2528 2529 adev->gfx.rlc.funcs->stop(adev); 2530 adev->gfx.rlc.funcs->reset(adev); 2531 gfx_v6_0_init_pg(adev); 2532 gfx_v6_0_init_cg(adev); 2533 2534 WREG32(mmRLC_RL_BASE, 0); 2535 WREG32(mmRLC_RL_SIZE, 0); 2536 WREG32(mmRLC_LB_CNTL, 0); 2537 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2538 WREG32(mmRLC_LB_CNTR_INIT, 0); 2539 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2540 2541 WREG32(mmRLC_MC_CNTL, 0); 2542 WREG32(mmRLC_UCODE_CNTL, 0); 2543 2544 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2545 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2546 fw_data = (const __le32 *) 2547 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2548 2549 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2550 2551 for (i = 0; i < fw_size; i++) { 2552 WREG32(mmRLC_UCODE_ADDR, i); 2553 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2554 } 2555 WREG32(mmRLC_UCODE_ADDR, 0); 2556 2557 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2558 adev->gfx.rlc.funcs->start(adev); 2559 2560 return 0; 2561 } 2562 2563 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2564 { 2565 u32 data, orig, tmp; 2566 2567 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2568 2569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2570 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2571 2572 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2573 2574 tmp = gfx_v6_0_halt_rlc(adev); 2575 2576 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2577 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2578 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2579 2580 gfx_v6_0_wait_for_rlc_serdes(adev); 2581 gfx_v6_0_update_rlc(adev, tmp); 2582 2583 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2584 2585 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2586 } else { 2587 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2588 2589 RREG32(mmCB_CGTT_SCLK_CTRL); 2590 RREG32(mmCB_CGTT_SCLK_CTRL); 2591 RREG32(mmCB_CGTT_SCLK_CTRL); 2592 RREG32(mmCB_CGTT_SCLK_CTRL); 2593 2594 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2595 } 2596 2597 if (orig != data) 2598 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2599 2600 } 2601 2602 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2603 { 2604 2605 u32 data, orig, tmp = 0; 2606 2607 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2608 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2609 data = 0x96940200; 2610 if (orig != data) 2611 WREG32(mmCGTS_SM_CTRL_REG, data); 2612 2613 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2614 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2615 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2616 if (orig != data) 2617 WREG32(mmCP_MEM_SLP_CNTL, data); 2618 } 2619 2620 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2621 data &= 0xffffffc0; 2622 if (orig != data) 2623 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2624 2625 tmp = gfx_v6_0_halt_rlc(adev); 2626 2627 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2628 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2629 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2630 2631 gfx_v6_0_update_rlc(adev, tmp); 2632 } else { 2633 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2634 data |= 0x00000003; 2635 if (orig != data) 2636 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2637 2638 data = RREG32(mmCP_MEM_SLP_CNTL); 2639 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2640 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2641 WREG32(mmCP_MEM_SLP_CNTL, data); 2642 } 2643 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2644 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2645 if (orig != data) 2646 WREG32(mmCGTS_SM_CTRL_REG, data); 2647 2648 tmp = gfx_v6_0_halt_rlc(adev); 2649 2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2651 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2652 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2653 2654 gfx_v6_0_update_rlc(adev, tmp); 2655 } 2656 } 2657 /* 2658 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2659 bool enable) 2660 { 2661 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2662 if (enable) { 2663 gfx_v6_0_enable_mgcg(adev, true); 2664 gfx_v6_0_enable_cgcg(adev, true); 2665 } else { 2666 gfx_v6_0_enable_cgcg(adev, false); 2667 gfx_v6_0_enable_mgcg(adev, false); 2668 } 2669 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2670 } 2671 */ 2672 2673 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2674 bool enable) 2675 { 2676 } 2677 2678 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2679 bool enable) 2680 { 2681 } 2682 2683 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2684 { 2685 u32 data, orig; 2686 2687 orig = data = RREG32(mmRLC_PG_CNTL); 2688 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2689 data &= ~0x8000; 2690 else 2691 data |= 0x8000; 2692 if (orig != data) 2693 WREG32(mmRLC_PG_CNTL, data); 2694 } 2695 2696 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2697 { 2698 } 2699 /* 2700 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2701 { 2702 const __le32 *fw_data; 2703 volatile u32 *dst_ptr; 2704 int me, i, max_me = 4; 2705 u32 bo_offset = 0; 2706 u32 table_offset, table_size; 2707 2708 if (adev->asic_type == CHIP_KAVERI) 2709 max_me = 5; 2710 2711 if (adev->gfx.rlc.cp_table_ptr == NULL) 2712 return; 2713 2714 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2715 for (me = 0; me < max_me; me++) { 2716 if (me == 0) { 2717 const struct gfx_firmware_header_v1_0 *hdr = 2718 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2719 fw_data = (const __le32 *) 2720 (adev->gfx.ce_fw->data + 2721 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2722 table_offset = le32_to_cpu(hdr->jt_offset); 2723 table_size = le32_to_cpu(hdr->jt_size); 2724 } else if (me == 1) { 2725 const struct gfx_firmware_header_v1_0 *hdr = 2726 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2727 fw_data = (const __le32 *) 2728 (adev->gfx.pfp_fw->data + 2729 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2730 table_offset = le32_to_cpu(hdr->jt_offset); 2731 table_size = le32_to_cpu(hdr->jt_size); 2732 } else if (me == 2) { 2733 const struct gfx_firmware_header_v1_0 *hdr = 2734 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2735 fw_data = (const __le32 *) 2736 (adev->gfx.me_fw->data + 2737 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2738 table_offset = le32_to_cpu(hdr->jt_offset); 2739 table_size = le32_to_cpu(hdr->jt_size); 2740 } else if (me == 3) { 2741 const struct gfx_firmware_header_v1_0 *hdr = 2742 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2743 fw_data = (const __le32 *) 2744 (adev->gfx.mec_fw->data + 2745 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2746 table_offset = le32_to_cpu(hdr->jt_offset); 2747 table_size = le32_to_cpu(hdr->jt_size); 2748 } else { 2749 const struct gfx_firmware_header_v1_0 *hdr = 2750 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2751 fw_data = (const __le32 *) 2752 (adev->gfx.mec2_fw->data + 2753 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2754 table_offset = le32_to_cpu(hdr->jt_offset); 2755 table_size = le32_to_cpu(hdr->jt_size); 2756 } 2757 2758 for (i = 0; i < table_size; i ++) { 2759 dst_ptr[bo_offset + i] = 2760 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2761 } 2762 2763 bo_offset += table_size; 2764 } 2765 } 2766 */ 2767 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2768 bool enable) 2769 { 2770 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2771 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2772 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2773 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2774 } else { 2775 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2776 (void)RREG32(mmDB_RENDER_CONTROL); 2777 } 2778 } 2779 2780 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2781 { 2782 u32 tmp; 2783 2784 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2785 2786 tmp = RREG32(mmRLC_MAX_PG_CU); 2787 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2788 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2789 WREG32(mmRLC_MAX_PG_CU, tmp); 2790 } 2791 2792 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2793 bool enable) 2794 { 2795 u32 data, orig; 2796 2797 orig = data = RREG32(mmRLC_PG_CNTL); 2798 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2799 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2800 else 2801 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2802 if (orig != data) 2803 WREG32(mmRLC_PG_CNTL, data); 2804 } 2805 2806 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2807 bool enable) 2808 { 2809 u32 data, orig; 2810 2811 orig = data = RREG32(mmRLC_PG_CNTL); 2812 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2813 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2814 else 2815 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2816 if (orig != data) 2817 WREG32(mmRLC_PG_CNTL, data); 2818 } 2819 2820 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2821 { 2822 u32 tmp; 2823 2824 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2825 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2826 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2827 2828 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2829 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2830 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2831 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2832 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2833 } 2834 2835 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2836 { 2837 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2838 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2839 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2840 } 2841 2842 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2843 { 2844 u32 count = 0; 2845 const struct cs_section_def *sect = NULL; 2846 const struct cs_extent_def *ext = NULL; 2847 2848 if (adev->gfx.rlc.cs_data == NULL) 2849 return 0; 2850 2851 /* begin clear state */ 2852 count += 2; 2853 /* context control state */ 2854 count += 3; 2855 2856 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2857 for (ext = sect->section; ext->extent != NULL; ++ext) { 2858 if (sect->id == SECT_CONTEXT) 2859 count += 2 + ext->reg_count; 2860 else 2861 return 0; 2862 } 2863 } 2864 /* pa_sc_raster_config */ 2865 count += 3; 2866 /* end clear state */ 2867 count += 2; 2868 /* clear state */ 2869 count += 2; 2870 2871 return count; 2872 } 2873 2874 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2875 volatile u32 *buffer) 2876 { 2877 u32 count = 0, i; 2878 const struct cs_section_def *sect = NULL; 2879 const struct cs_extent_def *ext = NULL; 2880 2881 if (adev->gfx.rlc.cs_data == NULL) 2882 return; 2883 if (buffer == NULL) 2884 return; 2885 2886 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2887 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2888 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2889 buffer[count++] = cpu_to_le32(0x80000000); 2890 buffer[count++] = cpu_to_le32(0x80000000); 2891 2892 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2893 for (ext = sect->section; ext->extent != NULL; ++ext) { 2894 if (sect->id == SECT_CONTEXT) { 2895 buffer[count++] = 2896 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2897 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2898 for (i = 0; i < ext->reg_count; i++) 2899 buffer[count++] = cpu_to_le32(ext->extent[i]); 2900 } else { 2901 return; 2902 } 2903 } 2904 } 2905 2906 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2907 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2908 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2909 2910 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2911 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2912 2913 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2914 buffer[count++] = cpu_to_le32(0); 2915 } 2916 2917 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2918 { 2919 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2920 AMD_PG_SUPPORT_GFX_SMG | 2921 AMD_PG_SUPPORT_GFX_DMG | 2922 AMD_PG_SUPPORT_CP | 2923 AMD_PG_SUPPORT_GDS | 2924 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2925 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2926 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2927 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2928 gfx_v6_0_init_gfx_cgpg(adev); 2929 gfx_v6_0_enable_cp_pg(adev, true); 2930 gfx_v6_0_enable_gds_pg(adev, true); 2931 } else { 2932 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2933 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2934 2935 } 2936 gfx_v6_0_init_ao_cu_mask(adev); 2937 gfx_v6_0_update_gfx_pg(adev, true); 2938 } else { 2939 2940 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2941 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2942 } 2943 } 2944 2945 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2946 { 2947 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2948 AMD_PG_SUPPORT_GFX_SMG | 2949 AMD_PG_SUPPORT_GFX_DMG | 2950 AMD_PG_SUPPORT_CP | 2951 AMD_PG_SUPPORT_GDS | 2952 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2953 gfx_v6_0_update_gfx_pg(adev, false); 2954 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2955 gfx_v6_0_enable_cp_pg(adev, false); 2956 gfx_v6_0_enable_gds_pg(adev, false); 2957 } 2958 } 2959 } 2960 2961 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2962 { 2963 uint64_t clock; 2964 2965 mutex_lock(&adev->gfx.gpu_clock_mutex); 2966 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2967 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2968 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2969 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2970 return clock; 2971 } 2972 2973 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2974 { 2975 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2976 gfx_v6_0_ring_emit_vgt_flush(ring); 2977 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2978 amdgpu_ring_write(ring, 0x80000000); 2979 amdgpu_ring_write(ring, 0); 2980 } 2981 2982 2983 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2984 { 2985 WREG32(mmSQ_IND_INDEX, 2986 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2987 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2988 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2989 (SQ_IND_INDEX__FORCE_READ_MASK)); 2990 return RREG32(mmSQ_IND_DATA); 2991 } 2992 2993 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2994 uint32_t wave, uint32_t thread, 2995 uint32_t regno, uint32_t num, uint32_t *out) 2996 { 2997 WREG32(mmSQ_IND_INDEX, 2998 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2999 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3000 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3001 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3002 (SQ_IND_INDEX__FORCE_READ_MASK) | 3003 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3004 while (num--) 3005 *(out++) = RREG32(mmSQ_IND_DATA); 3006 } 3007 3008 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3009 { 3010 /* type 0 wave data */ 3011 dst[(*no_fields)++] = 0; 3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3030 } 3031 3032 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3033 uint32_t wave, uint32_t start, 3034 uint32_t size, uint32_t *dst) 3035 { 3036 wave_read_regs( 3037 adev, simd, wave, 0, 3038 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3039 } 3040 3041 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3042 u32 me, u32 pipe, u32 q, u32 vm) 3043 { 3044 DRM_INFO("Not implemented\n"); 3045 } 3046 3047 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3048 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3049 .select_se_sh = &gfx_v6_0_select_se_sh, 3050 .read_wave_data = &gfx_v6_0_read_wave_data, 3051 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3052 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3053 }; 3054 3055 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3056 .init = gfx_v6_0_rlc_init, 3057 .resume = gfx_v6_0_rlc_resume, 3058 .stop = gfx_v6_0_rlc_stop, 3059 .reset = gfx_v6_0_rlc_reset, 3060 .start = gfx_v6_0_rlc_start 3061 }; 3062 3063 static int gfx_v6_0_early_init(void *handle) 3064 { 3065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3066 3067 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3068 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3069 GFX6_NUM_COMPUTE_RINGS); 3070 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3071 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3072 gfx_v6_0_set_ring_funcs(adev); 3073 gfx_v6_0_set_irq_funcs(adev); 3074 3075 return 0; 3076 } 3077 3078 static int gfx_v6_0_sw_init(void *handle) 3079 { 3080 struct amdgpu_ring *ring; 3081 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3082 int i, r; 3083 3084 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3085 if (r) 3086 return r; 3087 3088 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3089 if (r) 3090 return r; 3091 3092 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3093 if (r) 3094 return r; 3095 3096 gfx_v6_0_scratch_init(adev); 3097 3098 r = gfx_v6_0_init_microcode(adev); 3099 if (r) { 3100 DRM_ERROR("Failed to load gfx firmware!\n"); 3101 return r; 3102 } 3103 3104 r = adev->gfx.rlc.funcs->init(adev); 3105 if (r) { 3106 DRM_ERROR("Failed to init rlc BOs!\n"); 3107 return r; 3108 } 3109 3110 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3111 ring = &adev->gfx.gfx_ring[i]; 3112 ring->ring_obj = NULL; 3113 sprintf(ring->name, "gfx"); 3114 r = amdgpu_ring_init(adev, ring, 1024, 3115 &adev->gfx.eop_irq, 3116 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3117 AMDGPU_RING_PRIO_DEFAULT); 3118 if (r) 3119 return r; 3120 } 3121 3122 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3123 unsigned irq_type; 3124 3125 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3126 DRM_ERROR("Too many (%d) compute rings!\n", i); 3127 break; 3128 } 3129 ring = &adev->gfx.compute_ring[i]; 3130 ring->ring_obj = NULL; 3131 ring->use_doorbell = false; 3132 ring->doorbell_index = 0; 3133 ring->me = 1; 3134 ring->pipe = i; 3135 ring->queue = i; 3136 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3137 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3138 r = amdgpu_ring_init(adev, ring, 1024, 3139 &adev->gfx.eop_irq, irq_type, 3140 AMDGPU_RING_PRIO_DEFAULT); 3141 if (r) 3142 return r; 3143 } 3144 3145 return r; 3146 } 3147 3148 static int gfx_v6_0_sw_fini(void *handle) 3149 { 3150 int i; 3151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3152 3153 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3154 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3155 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3156 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3157 3158 amdgpu_gfx_rlc_fini(adev); 3159 3160 return 0; 3161 } 3162 3163 static int gfx_v6_0_hw_init(void *handle) 3164 { 3165 int r; 3166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3167 3168 gfx_v6_0_constants_init(adev); 3169 3170 r = adev->gfx.rlc.funcs->resume(adev); 3171 if (r) 3172 return r; 3173 3174 r = gfx_v6_0_cp_resume(adev); 3175 if (r) 3176 return r; 3177 3178 adev->gfx.ce_ram_size = 0x8000; 3179 3180 return r; 3181 } 3182 3183 static int gfx_v6_0_hw_fini(void *handle) 3184 { 3185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3186 3187 gfx_v6_0_cp_enable(adev, false); 3188 adev->gfx.rlc.funcs->stop(adev); 3189 gfx_v6_0_fini_pg(adev); 3190 3191 return 0; 3192 } 3193 3194 static int gfx_v6_0_suspend(void *handle) 3195 { 3196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3197 3198 return gfx_v6_0_hw_fini(adev); 3199 } 3200 3201 static int gfx_v6_0_resume(void *handle) 3202 { 3203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3204 3205 return gfx_v6_0_hw_init(adev); 3206 } 3207 3208 static bool gfx_v6_0_is_idle(void *handle) 3209 { 3210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3211 3212 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3213 return false; 3214 else 3215 return true; 3216 } 3217 3218 static int gfx_v6_0_wait_for_idle(void *handle) 3219 { 3220 unsigned i; 3221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3222 3223 for (i = 0; i < adev->usec_timeout; i++) { 3224 if (gfx_v6_0_is_idle(handle)) 3225 return 0; 3226 udelay(1); 3227 } 3228 return -ETIMEDOUT; 3229 } 3230 3231 static int gfx_v6_0_soft_reset(void *handle) 3232 { 3233 return 0; 3234 } 3235 3236 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3237 enum amdgpu_interrupt_state state) 3238 { 3239 u32 cp_int_cntl; 3240 3241 switch (state) { 3242 case AMDGPU_IRQ_STATE_DISABLE: 3243 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3244 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3245 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3246 break; 3247 case AMDGPU_IRQ_STATE_ENABLE: 3248 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3249 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3250 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3251 break; 3252 default: 3253 break; 3254 } 3255 } 3256 3257 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3258 int ring, 3259 enum amdgpu_interrupt_state state) 3260 { 3261 u32 cp_int_cntl; 3262 switch (state){ 3263 case AMDGPU_IRQ_STATE_DISABLE: 3264 if (ring == 0) { 3265 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3266 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3267 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3268 break; 3269 } else { 3270 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3271 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3272 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3273 break; 3274 3275 } 3276 case AMDGPU_IRQ_STATE_ENABLE: 3277 if (ring == 0) { 3278 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3279 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3280 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3281 break; 3282 } else { 3283 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3284 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3285 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3286 break; 3287 3288 } 3289 3290 default: 3291 BUG(); 3292 break; 3293 3294 } 3295 } 3296 3297 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3298 struct amdgpu_irq_src *src, 3299 unsigned type, 3300 enum amdgpu_interrupt_state state) 3301 { 3302 u32 cp_int_cntl; 3303 3304 switch (state) { 3305 case AMDGPU_IRQ_STATE_DISABLE: 3306 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3307 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3308 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3309 break; 3310 case AMDGPU_IRQ_STATE_ENABLE: 3311 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3312 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3313 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3314 break; 3315 default: 3316 break; 3317 } 3318 3319 return 0; 3320 } 3321 3322 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3323 struct amdgpu_irq_src *src, 3324 unsigned type, 3325 enum amdgpu_interrupt_state state) 3326 { 3327 u32 cp_int_cntl; 3328 3329 switch (state) { 3330 case AMDGPU_IRQ_STATE_DISABLE: 3331 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3332 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3333 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3334 break; 3335 case AMDGPU_IRQ_STATE_ENABLE: 3336 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3337 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3338 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3339 break; 3340 default: 3341 break; 3342 } 3343 3344 return 0; 3345 } 3346 3347 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3348 struct amdgpu_irq_src *src, 3349 unsigned type, 3350 enum amdgpu_interrupt_state state) 3351 { 3352 switch (type) { 3353 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3354 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3355 break; 3356 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3357 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3358 break; 3359 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3360 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3361 break; 3362 default: 3363 break; 3364 } 3365 return 0; 3366 } 3367 3368 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3369 struct amdgpu_irq_src *source, 3370 struct amdgpu_iv_entry *entry) 3371 { 3372 switch (entry->ring_id) { 3373 case 0: 3374 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3375 break; 3376 case 1: 3377 case 2: 3378 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3379 break; 3380 default: 3381 break; 3382 } 3383 return 0; 3384 } 3385 3386 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3387 struct amdgpu_iv_entry *entry) 3388 { 3389 struct amdgpu_ring *ring; 3390 3391 switch (entry->ring_id) { 3392 case 0: 3393 ring = &adev->gfx.gfx_ring[0]; 3394 break; 3395 case 1: 3396 case 2: 3397 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3398 break; 3399 default: 3400 return; 3401 } 3402 drm_sched_fault(&ring->sched); 3403 } 3404 3405 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3406 struct amdgpu_irq_src *source, 3407 struct amdgpu_iv_entry *entry) 3408 { 3409 DRM_ERROR("Illegal register access in command stream\n"); 3410 gfx_v6_0_fault(adev, entry); 3411 return 0; 3412 } 3413 3414 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3415 struct amdgpu_irq_src *source, 3416 struct amdgpu_iv_entry *entry) 3417 { 3418 DRM_ERROR("Illegal instruction in command stream\n"); 3419 gfx_v6_0_fault(adev, entry); 3420 return 0; 3421 } 3422 3423 static int gfx_v6_0_set_clockgating_state(void *handle, 3424 enum amd_clockgating_state state) 3425 { 3426 bool gate = false; 3427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3428 3429 if (state == AMD_CG_STATE_GATE) 3430 gate = true; 3431 3432 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3433 if (gate) { 3434 gfx_v6_0_enable_mgcg(adev, true); 3435 gfx_v6_0_enable_cgcg(adev, true); 3436 } else { 3437 gfx_v6_0_enable_cgcg(adev, false); 3438 gfx_v6_0_enable_mgcg(adev, false); 3439 } 3440 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3441 3442 return 0; 3443 } 3444 3445 static int gfx_v6_0_set_powergating_state(void *handle, 3446 enum amd_powergating_state state) 3447 { 3448 bool gate = false; 3449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3450 3451 if (state == AMD_PG_STATE_GATE) 3452 gate = true; 3453 3454 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3455 AMD_PG_SUPPORT_GFX_SMG | 3456 AMD_PG_SUPPORT_GFX_DMG | 3457 AMD_PG_SUPPORT_CP | 3458 AMD_PG_SUPPORT_GDS | 3459 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3460 gfx_v6_0_update_gfx_pg(adev, gate); 3461 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3462 gfx_v6_0_enable_cp_pg(adev, gate); 3463 gfx_v6_0_enable_gds_pg(adev, gate); 3464 } 3465 } 3466 3467 return 0; 3468 } 3469 3470 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3471 { 3472 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3473 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3474 PACKET3_TC_ACTION_ENA | 3475 PACKET3_SH_KCACHE_ACTION_ENA | 3476 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3477 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3478 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3479 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3480 } 3481 3482 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3483 .name = "gfx_v6_0", 3484 .early_init = gfx_v6_0_early_init, 3485 .late_init = NULL, 3486 .sw_init = gfx_v6_0_sw_init, 3487 .sw_fini = gfx_v6_0_sw_fini, 3488 .hw_init = gfx_v6_0_hw_init, 3489 .hw_fini = gfx_v6_0_hw_fini, 3490 .suspend = gfx_v6_0_suspend, 3491 .resume = gfx_v6_0_resume, 3492 .is_idle = gfx_v6_0_is_idle, 3493 .wait_for_idle = gfx_v6_0_wait_for_idle, 3494 .soft_reset = gfx_v6_0_soft_reset, 3495 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3496 .set_powergating_state = gfx_v6_0_set_powergating_state, 3497 }; 3498 3499 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3500 .type = AMDGPU_RING_TYPE_GFX, 3501 .align_mask = 0xff, 3502 .nop = 0x80000000, 3503 .support_64bit_ptrs = false, 3504 .get_rptr = gfx_v6_0_ring_get_rptr, 3505 .get_wptr = gfx_v6_0_ring_get_wptr, 3506 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3507 .emit_frame_size = 3508 5 + 5 + /* hdp flush / invalidate */ 3509 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3510 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3511 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3512 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3513 5, /* SURFACE_SYNC */ 3514 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3515 .emit_ib = gfx_v6_0_ring_emit_ib, 3516 .emit_fence = gfx_v6_0_ring_emit_fence, 3517 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3518 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3519 .test_ring = gfx_v6_0_ring_test_ring, 3520 .test_ib = gfx_v6_0_ring_test_ib, 3521 .insert_nop = amdgpu_ring_insert_nop, 3522 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3523 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3524 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3525 }; 3526 3527 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3528 .type = AMDGPU_RING_TYPE_COMPUTE, 3529 .align_mask = 0xff, 3530 .nop = 0x80000000, 3531 .get_rptr = gfx_v6_0_ring_get_rptr, 3532 .get_wptr = gfx_v6_0_ring_get_wptr, 3533 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3534 .emit_frame_size = 3535 5 + 5 + /* hdp flush / invalidate */ 3536 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3537 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3538 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3539 5, /* SURFACE_SYNC */ 3540 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3541 .emit_ib = gfx_v6_0_ring_emit_ib, 3542 .emit_fence = gfx_v6_0_ring_emit_fence, 3543 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3544 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3545 .test_ring = gfx_v6_0_ring_test_ring, 3546 .test_ib = gfx_v6_0_ring_test_ib, 3547 .insert_nop = amdgpu_ring_insert_nop, 3548 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3549 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3550 }; 3551 3552 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3553 { 3554 int i; 3555 3556 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3557 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3558 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3559 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3560 } 3561 3562 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3563 .set = gfx_v6_0_set_eop_interrupt_state, 3564 .process = gfx_v6_0_eop_irq, 3565 }; 3566 3567 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3568 .set = gfx_v6_0_set_priv_reg_fault_state, 3569 .process = gfx_v6_0_priv_reg_irq, 3570 }; 3571 3572 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3573 .set = gfx_v6_0_set_priv_inst_fault_state, 3574 .process = gfx_v6_0_priv_inst_irq, 3575 }; 3576 3577 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3578 { 3579 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3580 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3581 3582 adev->gfx.priv_reg_irq.num_types = 1; 3583 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3584 3585 adev->gfx.priv_inst_irq.num_types = 1; 3586 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3587 } 3588 3589 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3590 { 3591 int i, j, k, counter, active_cu_number = 0; 3592 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3593 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3594 unsigned disable_masks[4 * 2]; 3595 u32 ao_cu_num; 3596 3597 if (adev->flags & AMD_IS_APU) 3598 ao_cu_num = 2; 3599 else 3600 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3601 3602 memset(cu_info, 0, sizeof(*cu_info)); 3603 3604 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3605 3606 mutex_lock(&adev->grbm_idx_mutex); 3607 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3608 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3609 mask = 1; 3610 ao_bitmap = 0; 3611 counter = 0; 3612 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3613 if (i < 4 && j < 2) 3614 gfx_v6_0_set_user_cu_inactive_bitmap( 3615 adev, disable_masks[i * 2 + j]); 3616 bitmap = gfx_v6_0_get_cu_enabled(adev); 3617 cu_info->bitmap[i][j] = bitmap; 3618 3619 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3620 if (bitmap & mask) { 3621 if (counter < ao_cu_num) 3622 ao_bitmap |= mask; 3623 counter ++; 3624 } 3625 mask <<= 1; 3626 } 3627 active_cu_number += counter; 3628 if (i < 2 && j < 2) 3629 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3630 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3631 } 3632 } 3633 3634 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3635 mutex_unlock(&adev->grbm_idx_mutex); 3636 3637 cu_info->number = active_cu_number; 3638 cu_info->ao_cu_mask = ao_cu_mask; 3639 } 3640 3641 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3642 { 3643 .type = AMD_IP_BLOCK_TYPE_GFX, 3644 .major = 6, 3645 .minor = 0, 3646 .rev = 0, 3647 .funcs = &gfx_v6_0_ip_funcs, 3648 }; 3649