1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "si.h" 32 #include "sid.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 37 #include "oss/oss_1_0_d.h" 38 #include "oss/oss_1_0_sh_mask.h" 39 40 #include "gca/gfx_6_0_d.h" 41 #include "gca/gfx_6_0_sh_mask.h" 42 #include "gca/gfx_7_2_enum.h" 43 44 #include "gmc/gmc_6_0_d.h" 45 #include "gmc/gmc_6_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "si_enums.h" 51 52 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 53 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 54 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 55 56 #define GFX6_NUM_GFX_RINGS 1 57 #define GFX6_NUM_COMPUTE_RINGS 2 58 59 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 61 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 62 63 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 65 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 66 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 67 68 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 70 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 75 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 77 78 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 80 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 81 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 85 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 87 88 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 89 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 90 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 91 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 92 93 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 94 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 95 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 96 #define MICRO_TILE_MODE(x) ((x) << 0) 97 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 98 #define BANK_WIDTH(x) ((x) << 14) 99 #define BANK_HEIGHT(x) ((x) << 16) 100 #define MACRO_TILE_ASPECT(x) ((x) << 18) 101 #define NUM_BANKS(x) ((x) << 20) 102 103 static const u32 verde_rlc_save_restore_register_list[] = 104 { 105 (0x8000 << 16) | (0x98f4 >> 2), 106 0x00000000, 107 (0x8040 << 16) | (0x98f4 >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0xe80 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0xe80 >> 2), 112 0x00000000, 113 (0x8000 << 16) | (0x89bc >> 2), 114 0x00000000, 115 (0x8040 << 16) | (0x89bc >> 2), 116 0x00000000, 117 (0x8000 << 16) | (0x8c1c >> 2), 118 0x00000000, 119 (0x8040 << 16) | (0x8c1c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0x98f0 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0xe7c >> 2), 124 0x00000000, 125 (0x8000 << 16) | (0x9148 >> 2), 126 0x00000000, 127 (0x8040 << 16) | (0x9148 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x9150 >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x897c >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x8d8c >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0xac54 >> 2), 136 0X00000000, 137 0x3, 138 (0x9c00 << 16) | (0x98f8 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9910 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9914 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9918 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x991c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9920 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9924 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9928 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x992c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9930 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9934 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9938 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x993c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9940 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9944 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9948 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x994c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9950 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9954 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9958 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x995c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9960 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9964 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9968 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x996c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x9970 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x9974 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x9978 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x997c >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x9980 >> 2), 197 0x00000000, 198 (0x9c00 << 16) | (0x9984 >> 2), 199 0x00000000, 200 (0x9c00 << 16) | (0x9988 >> 2), 201 0x00000000, 202 (0x9c00 << 16) | (0x998c >> 2), 203 0x00000000, 204 (0x9c00 << 16) | (0x8c00 >> 2), 205 0x00000000, 206 (0x9c00 << 16) | (0x8c14 >> 2), 207 0x00000000, 208 (0x9c00 << 16) | (0x8c04 >> 2), 209 0x00000000, 210 (0x9c00 << 16) | (0x8c08 >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x9b7c >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x9b7c >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0xe84 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0xe84 >> 2), 219 0x00000000, 220 (0x8000 << 16) | (0x89c0 >> 2), 221 0x00000000, 222 (0x8040 << 16) | (0x89c0 >> 2), 223 0x00000000, 224 (0x8000 << 16) | (0x914c >> 2), 225 0x00000000, 226 (0x8040 << 16) | (0x914c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x8c20 >> 2), 229 0x00000000, 230 (0x8040 << 16) | (0x8c20 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x9354 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x9354 >> 2), 235 0x00000000, 236 (0x9c00 << 16) | (0x9060 >> 2), 237 0x00000000, 238 (0x9c00 << 16) | (0x9364 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x9100 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x913c >> 2), 243 0x00000000, 244 (0x8000 << 16) | (0x90e0 >> 2), 245 0x00000000, 246 (0x8000 << 16) | (0x90e4 >> 2), 247 0x00000000, 248 (0x8000 << 16) | (0x90e8 >> 2), 249 0x00000000, 250 (0x8040 << 16) | (0x90e0 >> 2), 251 0x00000000, 252 (0x8040 << 16) | (0x90e4 >> 2), 253 0x00000000, 254 (0x8040 << 16) | (0x90e8 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x8bcc >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x8b24 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x88c4 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0x8e50 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0x8c0c >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0x8e58 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0x8e5c >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x9508 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x950c >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x9494 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0xac0c >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0xac10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0xac14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0xae00 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0xac08 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x88d4 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x88c8 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x88cc >> 2), 291 0x00000000, 292 (0x9c00 << 16) | (0x89b0 >> 2), 293 0x00000000, 294 (0x9c00 << 16) | (0x8b10 >> 2), 295 0x00000000, 296 (0x9c00 << 16) | (0x8a14 >> 2), 297 0x00000000, 298 (0x9c00 << 16) | (0x9830 >> 2), 299 0x00000000, 300 (0x9c00 << 16) | (0x9834 >> 2), 301 0x00000000, 302 (0x9c00 << 16) | (0x9838 >> 2), 303 0x00000000, 304 (0x9c00 << 16) | (0x9a10 >> 2), 305 0x00000000, 306 (0x8000 << 16) | (0x9870 >> 2), 307 0x00000000, 308 (0x8000 << 16) | (0x9874 >> 2), 309 0x00000000, 310 (0x8001 << 16) | (0x9870 >> 2), 311 0x00000000, 312 (0x8001 << 16) | (0x9874 >> 2), 313 0x00000000, 314 (0x8040 << 16) | (0x9870 >> 2), 315 0x00000000, 316 (0x8040 << 16) | (0x9874 >> 2), 317 0x00000000, 318 (0x8041 << 16) | (0x9870 >> 2), 319 0x00000000, 320 (0x8041 << 16) | (0x9874 >> 2), 321 0x00000000, 322 0x00000000 323 }; 324 325 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 326 { 327 const char *chip_name; 328 int err; 329 const struct gfx_firmware_header_v1_0 *cp_hdr; 330 const struct rlc_firmware_header_v1_0 *rlc_hdr; 331 332 DRM_DEBUG("\n"); 333 334 switch (adev->asic_type) { 335 case CHIP_TAHITI: 336 chip_name = "tahiti"; 337 break; 338 case CHIP_PITCAIRN: 339 chip_name = "pitcairn"; 340 break; 341 case CHIP_VERDE: 342 chip_name = "verde"; 343 break; 344 case CHIP_OLAND: 345 chip_name = "oland"; 346 break; 347 case CHIP_HAINAN: 348 chip_name = "hainan"; 349 break; 350 default: 351 return -EINVAL; 352 } 353 354 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 355 AMDGPU_UCODE_REQUIRED, 356 "amdgpu/%s_pfp.bin", chip_name); 357 if (err) 358 goto out; 359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 360 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 361 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 362 363 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 364 AMDGPU_UCODE_REQUIRED, 365 "amdgpu/%s_me.bin", chip_name); 366 if (err) 367 goto out; 368 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 369 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 370 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 371 372 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 373 AMDGPU_UCODE_REQUIRED, 374 "amdgpu/%s_ce.bin", chip_name); 375 if (err) 376 goto out; 377 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 378 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 379 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 380 381 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 382 AMDGPU_UCODE_REQUIRED, 383 "amdgpu/%s_rlc.bin", chip_name); 384 if (err) 385 goto out; 386 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 387 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 388 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 389 390 out: 391 if (err) { 392 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); 393 amdgpu_ucode_release(&adev->gfx.pfp_fw); 394 amdgpu_ucode_release(&adev->gfx.me_fw); 395 amdgpu_ucode_release(&adev->gfx.ce_fw); 396 amdgpu_ucode_release(&adev->gfx.rlc_fw); 397 } 398 return err; 399 } 400 401 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 402 { 403 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 404 u32 reg_offset, split_equal_to_row_size, *tilemode; 405 406 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 407 tilemode = adev->gfx.config.tile_mode_array; 408 409 switch (adev->gfx.config.mem_row_size_in_kb) { 410 case 1: 411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 412 break; 413 case 2: 414 default: 415 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 416 break; 417 case 4: 418 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 419 break; 420 } 421 422 if (adev->asic_type == CHIP_VERDE) { 423 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 424 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 425 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 426 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 427 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 430 NUM_BANKS(ADDR_SURF_16_BANK); 431 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 432 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 433 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 438 NUM_BANKS(ADDR_SURF_16_BANK); 439 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 446 NUM_BANKS(ADDR_SURF_16_BANK); 447 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 449 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 450 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 453 NUM_BANKS(ADDR_SURF_8_BANK) | 454 TILE_SPLIT(split_equal_to_row_size); 455 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 456 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 457 PIPE_CONFIG(ADDR_SURF_P4_8x16); 458 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 459 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 460 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 461 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 462 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 465 NUM_BANKS(ADDR_SURF_4_BANK); 466 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 467 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 468 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 469 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 470 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 471 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 472 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 473 NUM_BANKS(ADDR_SURF_4_BANK); 474 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 475 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 476 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 477 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 478 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 481 NUM_BANKS(ADDR_SURF_2_BANK); 482 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 483 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 484 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 485 PIPE_CONFIG(ADDR_SURF_P4_8x16); 486 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 487 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 488 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 490 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 493 NUM_BANKS(ADDR_SURF_16_BANK); 494 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 496 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 501 NUM_BANKS(ADDR_SURF_16_BANK); 502 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 504 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 509 NUM_BANKS(ADDR_SURF_16_BANK); 510 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 511 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16); 513 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 514 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 515 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 517 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 520 NUM_BANKS(ADDR_SURF_16_BANK); 521 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 523 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 528 NUM_BANKS(ADDR_SURF_16_BANK); 529 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 530 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 531 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 536 NUM_BANKS(ADDR_SURF_16_BANK); 537 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 538 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 539 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 543 NUM_BANKS(ADDR_SURF_16_BANK) | 544 TILE_SPLIT(split_equal_to_row_size); 545 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 546 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 547 PIPE_CONFIG(ADDR_SURF_P4_8x16); 548 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 549 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 550 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 551 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 554 NUM_BANKS(ADDR_SURF_16_BANK) | 555 TILE_SPLIT(split_equal_to_row_size); 556 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 557 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 558 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 559 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 562 NUM_BANKS(ADDR_SURF_16_BANK) | 563 TILE_SPLIT(split_equal_to_row_size); 564 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 565 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 566 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 567 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 571 NUM_BANKS(ADDR_SURF_8_BANK); 572 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 573 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 574 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 575 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 576 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 579 NUM_BANKS(ADDR_SURF_8_BANK); 580 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 581 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 583 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 587 NUM_BANKS(ADDR_SURF_4_BANK); 588 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 589 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 590 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 595 NUM_BANKS(ADDR_SURF_4_BANK); 596 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 597 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 598 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 599 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 600 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 603 NUM_BANKS(ADDR_SURF_2_BANK); 604 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 605 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 606 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 607 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 611 NUM_BANKS(ADDR_SURF_2_BANK); 612 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 613 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 614 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 615 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 616 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 619 NUM_BANKS(ADDR_SURF_2_BANK); 620 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 621 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 622 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 624 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 627 NUM_BANKS(ADDR_SURF_2_BANK); 628 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 632 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 633 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 634 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 635 NUM_BANKS(ADDR_SURF_2_BANK); 636 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 638 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 640 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 643 NUM_BANKS(ADDR_SURF_2_BANK); 644 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 645 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 646 } else if (adev->asic_type == CHIP_OLAND) { 647 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 648 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 649 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 650 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 651 NUM_BANKS(ADDR_SURF_16_BANK) | 652 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 653 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 654 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 655 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 656 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 657 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 659 NUM_BANKS(ADDR_SURF_16_BANK) | 660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 663 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 664 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 665 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 666 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 667 NUM_BANKS(ADDR_SURF_16_BANK) | 668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 669 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 670 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 671 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 673 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 675 NUM_BANKS(ADDR_SURF_16_BANK) | 676 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 677 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 678 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 679 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 680 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 681 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 682 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 683 NUM_BANKS(ADDR_SURF_16_BANK) | 684 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 687 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 688 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 689 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 690 TILE_SPLIT(split_equal_to_row_size) | 691 NUM_BANKS(ADDR_SURF_16_BANK) | 692 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 693 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 694 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 695 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 696 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 697 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 698 TILE_SPLIT(split_equal_to_row_size) | 699 NUM_BANKS(ADDR_SURF_16_BANK) | 700 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 703 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 704 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 705 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 706 TILE_SPLIT(split_equal_to_row_size) | 707 NUM_BANKS(ADDR_SURF_16_BANK) | 708 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 711 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 712 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 713 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 715 NUM_BANKS(ADDR_SURF_16_BANK) | 716 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 717 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 718 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 719 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 720 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 721 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 723 NUM_BANKS(ADDR_SURF_16_BANK) | 724 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 727 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 728 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 729 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 730 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 731 NUM_BANKS(ADDR_SURF_16_BANK) | 732 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 734 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 735 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 736 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 737 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 738 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 739 NUM_BANKS(ADDR_SURF_16_BANK) | 740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 743 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 744 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 745 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 746 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 747 NUM_BANKS(ADDR_SURF_16_BANK) | 748 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 751 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 752 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 753 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 754 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 755 NUM_BANKS(ADDR_SURF_16_BANK) | 756 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 757 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 758 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 759 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 760 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 761 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 762 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 763 NUM_BANKS(ADDR_SURF_16_BANK) | 764 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 765 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 766 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 767 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 768 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 769 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 770 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 771 NUM_BANKS(ADDR_SURF_16_BANK) | 772 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 773 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 774 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 775 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 776 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 777 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 779 NUM_BANKS(ADDR_SURF_16_BANK) | 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 783 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 784 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 785 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 786 TILE_SPLIT(split_equal_to_row_size) | 787 NUM_BANKS(ADDR_SURF_16_BANK) | 788 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 789 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 790 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 791 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 792 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 793 PIPE_CONFIG(ADDR_SURF_P4_8x16); 794 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 795 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 796 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 800 NUM_BANKS(ADDR_SURF_16_BANK) | 801 TILE_SPLIT(split_equal_to_row_size); 802 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 803 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 804 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 808 NUM_BANKS(ADDR_SURF_16_BANK) | 809 TILE_SPLIT(split_equal_to_row_size); 810 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 811 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 812 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 813 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 814 NUM_BANKS(ADDR_SURF_16_BANK) | 815 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 818 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 819 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 821 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 822 NUM_BANKS(ADDR_SURF_16_BANK) | 823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 826 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 827 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 828 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 829 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 830 NUM_BANKS(ADDR_SURF_16_BANK) | 831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 834 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 836 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 838 NUM_BANKS(ADDR_SURF_16_BANK) | 839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 842 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 844 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 846 NUM_BANKS(ADDR_SURF_8_BANK) | 847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 850 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 851 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 852 } else if (adev->asic_type == CHIP_HAINAN) { 853 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 854 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 855 PIPE_CONFIG(ADDR_SURF_P2) | 856 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 857 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 860 NUM_BANKS(ADDR_SURF_16_BANK); 861 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 862 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 863 PIPE_CONFIG(ADDR_SURF_P2) | 864 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 868 NUM_BANKS(ADDR_SURF_16_BANK); 869 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 871 PIPE_CONFIG(ADDR_SURF_P2) | 872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 876 NUM_BANKS(ADDR_SURF_16_BANK); 877 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 879 PIPE_CONFIG(ADDR_SURF_P2) | 880 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 883 NUM_BANKS(ADDR_SURF_8_BANK) | 884 TILE_SPLIT(split_equal_to_row_size); 885 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 886 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 887 PIPE_CONFIG(ADDR_SURF_P2); 888 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 889 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 890 PIPE_CONFIG(ADDR_SURF_P2) | 891 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 892 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 893 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 894 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 895 NUM_BANKS(ADDR_SURF_8_BANK); 896 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 897 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 898 PIPE_CONFIG(ADDR_SURF_P2) | 899 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 903 NUM_BANKS(ADDR_SURF_8_BANK); 904 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 906 PIPE_CONFIG(ADDR_SURF_P2) | 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 911 NUM_BANKS(ADDR_SURF_4_BANK); 912 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 913 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 914 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 915 PIPE_CONFIG(ADDR_SURF_P2); 916 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 917 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 918 PIPE_CONFIG(ADDR_SURF_P2) | 919 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 923 NUM_BANKS(ADDR_SURF_16_BANK); 924 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 926 PIPE_CONFIG(ADDR_SURF_P2) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 931 NUM_BANKS(ADDR_SURF_16_BANK); 932 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 PIPE_CONFIG(ADDR_SURF_P2) | 935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 939 NUM_BANKS(ADDR_SURF_16_BANK); 940 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 941 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 942 PIPE_CONFIG(ADDR_SURF_P2); 943 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 944 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 945 PIPE_CONFIG(ADDR_SURF_P2) | 946 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 947 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 948 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 949 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 950 NUM_BANKS(ADDR_SURF_16_BANK); 951 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 952 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 953 PIPE_CONFIG(ADDR_SURF_P2) | 954 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 958 NUM_BANKS(ADDR_SURF_16_BANK); 959 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 960 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 961 PIPE_CONFIG(ADDR_SURF_P2) | 962 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 966 NUM_BANKS(ADDR_SURF_16_BANK); 967 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 968 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 969 PIPE_CONFIG(ADDR_SURF_P2) | 970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 973 NUM_BANKS(ADDR_SURF_16_BANK) | 974 TILE_SPLIT(split_equal_to_row_size); 975 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 976 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 977 PIPE_CONFIG(ADDR_SURF_P2); 978 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 979 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 980 PIPE_CONFIG(ADDR_SURF_P2) | 981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 984 NUM_BANKS(ADDR_SURF_16_BANK) | 985 TILE_SPLIT(split_equal_to_row_size); 986 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 987 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 988 PIPE_CONFIG(ADDR_SURF_P2) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 992 NUM_BANKS(ADDR_SURF_16_BANK) | 993 TILE_SPLIT(split_equal_to_row_size); 994 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 995 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 996 PIPE_CONFIG(ADDR_SURF_P2) | 997 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1001 NUM_BANKS(ADDR_SURF_8_BANK); 1002 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1003 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1004 PIPE_CONFIG(ADDR_SURF_P2) | 1005 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1009 NUM_BANKS(ADDR_SURF_8_BANK); 1010 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1011 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1012 PIPE_CONFIG(ADDR_SURF_P2) | 1013 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1014 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1017 NUM_BANKS(ADDR_SURF_8_BANK); 1018 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1019 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1020 PIPE_CONFIG(ADDR_SURF_P2) | 1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1022 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1023 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1024 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1025 NUM_BANKS(ADDR_SURF_8_BANK); 1026 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1027 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1028 PIPE_CONFIG(ADDR_SURF_P2) | 1029 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1033 NUM_BANKS(ADDR_SURF_4_BANK); 1034 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1035 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1036 PIPE_CONFIG(ADDR_SURF_P2) | 1037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1041 NUM_BANKS(ADDR_SURF_4_BANK); 1042 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1043 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1044 PIPE_CONFIG(ADDR_SURF_P2) | 1045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1049 NUM_BANKS(ADDR_SURF_4_BANK); 1050 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1051 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1052 PIPE_CONFIG(ADDR_SURF_P2) | 1053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1054 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1057 NUM_BANKS(ADDR_SURF_4_BANK); 1058 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P2) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1065 NUM_BANKS(ADDR_SURF_4_BANK); 1066 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P2) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1073 NUM_BANKS(ADDR_SURF_4_BANK); 1074 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1075 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1076 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1077 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1078 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1079 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1080 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1081 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1084 NUM_BANKS(ADDR_SURF_16_BANK); 1085 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1086 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1092 NUM_BANKS(ADDR_SURF_16_BANK); 1093 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1100 NUM_BANKS(ADDR_SURF_16_BANK); 1101 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1104 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1105 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1106 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1107 NUM_BANKS(ADDR_SURF_4_BANK) | 1108 TILE_SPLIT(split_equal_to_row_size); 1109 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1110 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1111 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1112 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1113 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1116 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1119 NUM_BANKS(ADDR_SURF_2_BANK); 1120 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1121 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1122 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1123 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1124 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1127 NUM_BANKS(ADDR_SURF_2_BANK); 1128 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1129 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1130 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1131 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1132 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1135 NUM_BANKS(ADDR_SURF_2_BANK); 1136 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1137 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1138 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1140 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1141 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1142 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1143 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1144 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1147 NUM_BANKS(ADDR_SURF_16_BANK); 1148 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1155 NUM_BANKS(ADDR_SURF_16_BANK); 1156 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1163 NUM_BANKS(ADDR_SURF_16_BANK); 1164 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1165 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1167 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1168 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1169 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1170 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1171 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1174 NUM_BANKS(ADDR_SURF_16_BANK); 1175 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1176 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1177 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1178 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1182 NUM_BANKS(ADDR_SURF_16_BANK); 1183 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1184 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1186 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1190 NUM_BANKS(ADDR_SURF_16_BANK); 1191 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1192 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1194 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1197 NUM_BANKS(ADDR_SURF_16_BANK) | 1198 TILE_SPLIT(split_equal_to_row_size); 1199 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1200 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1202 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1203 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1204 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1208 NUM_BANKS(ADDR_SURF_16_BANK) | 1209 TILE_SPLIT(split_equal_to_row_size); 1210 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1211 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1212 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1216 NUM_BANKS(ADDR_SURF_16_BANK) | 1217 TILE_SPLIT(split_equal_to_row_size); 1218 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1219 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1220 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1222 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1223 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1224 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1225 NUM_BANKS(ADDR_SURF_4_BANK); 1226 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1233 NUM_BANKS(ADDR_SURF_4_BANK); 1234 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1235 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1236 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1241 NUM_BANKS(ADDR_SURF_2_BANK); 1242 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1243 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1244 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1249 NUM_BANKS(ADDR_SURF_2_BANK); 1250 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1251 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1252 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1254 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1257 NUM_BANKS(ADDR_SURF_2_BANK); 1258 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1259 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1260 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1261 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1262 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1265 NUM_BANKS(ADDR_SURF_2_BANK); 1266 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1273 NUM_BANKS(ADDR_SURF_2_BANK); 1274 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1275 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1278 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1281 NUM_BANKS(ADDR_SURF_2_BANK); 1282 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1283 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1286 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1289 NUM_BANKS(ADDR_SURF_2_BANK); 1290 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1291 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1293 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1294 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1297 NUM_BANKS(ADDR_SURF_2_BANK); 1298 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1299 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1300 } else { 1301 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1302 } 1303 } 1304 1305 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1306 u32 sh_num, u32 instance, int xcc_id) 1307 { 1308 u32 data; 1309 1310 if (instance == 0xffffffff) 1311 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1312 else 1313 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1314 1315 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1316 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1317 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1318 else if (se_num == 0xffffffff) 1319 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1320 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1321 else if (sh_num == 0xffffffff) 1322 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1323 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1324 else 1325 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1326 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1327 WREG32(mmGRBM_GFX_INDEX, data); 1328 } 1329 1330 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1331 { 1332 u32 data, mask; 1333 1334 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1335 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1336 1337 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1338 1339 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1340 adev->gfx.config.max_sh_per_se); 1341 1342 return ~data & mask; 1343 } 1344 1345 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1346 { 1347 switch (adev->asic_type) { 1348 case CHIP_TAHITI: 1349 case CHIP_PITCAIRN: 1350 *rconf |= 1351 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1352 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1353 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1354 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1355 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1356 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1357 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1358 break; 1359 case CHIP_VERDE: 1360 *rconf |= 1361 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1362 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1363 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1364 break; 1365 case CHIP_OLAND: 1366 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1367 break; 1368 case CHIP_HAINAN: 1369 *rconf |= 0x0; 1370 break; 1371 default: 1372 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1373 break; 1374 } 1375 } 1376 1377 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1378 u32 raster_config, unsigned rb_mask, 1379 unsigned num_rb) 1380 { 1381 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1382 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1383 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1384 unsigned rb_per_se = num_rb / num_se; 1385 unsigned se_mask[4]; 1386 unsigned se; 1387 1388 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1389 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1390 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1391 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1392 1393 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1394 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1395 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1396 1397 for (se = 0; se < num_se; se++) { 1398 unsigned raster_config_se = raster_config; 1399 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1400 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1401 int idx = (se / 2) * 2; 1402 1403 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1404 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1405 1406 if (!se_mask[idx]) 1407 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1408 else 1409 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1410 } 1411 1412 pkr0_mask &= rb_mask; 1413 pkr1_mask &= rb_mask; 1414 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1415 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1416 1417 if (!pkr0_mask) 1418 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1419 else 1420 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1421 } 1422 1423 if (rb_per_se >= 2) { 1424 unsigned rb0_mask = 1 << (se * rb_per_se); 1425 unsigned rb1_mask = rb0_mask << 1; 1426 1427 rb0_mask &= rb_mask; 1428 rb1_mask &= rb_mask; 1429 if (!rb0_mask || !rb1_mask) { 1430 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1431 1432 if (!rb0_mask) 1433 raster_config_se |= 1434 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1435 else 1436 raster_config_se |= 1437 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1438 } 1439 1440 if (rb_per_se > 2) { 1441 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1442 rb1_mask = rb0_mask << 1; 1443 rb0_mask &= rb_mask; 1444 rb1_mask &= rb_mask; 1445 if (!rb0_mask || !rb1_mask) { 1446 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1447 1448 if (!rb0_mask) 1449 raster_config_se |= 1450 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1451 else 1452 raster_config_se |= 1453 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1454 } 1455 } 1456 } 1457 1458 /* GRBM_GFX_INDEX has a different offset on SI */ 1459 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1460 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1461 } 1462 1463 /* GRBM_GFX_INDEX has a different offset on SI */ 1464 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1465 } 1466 1467 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1468 { 1469 int i, j; 1470 u32 data; 1471 u32 raster_config = 0; 1472 u32 active_rbs = 0; 1473 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1474 adev->gfx.config.max_sh_per_se; 1475 unsigned num_rb_pipes; 1476 1477 mutex_lock(&adev->grbm_idx_mutex); 1478 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1479 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1480 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1481 data = gfx_v6_0_get_rb_active_bitmap(adev); 1482 active_rbs |= data << 1483 ((i * adev->gfx.config.max_sh_per_se + j) * 1484 rb_bitmap_width_per_sh); 1485 } 1486 } 1487 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1488 1489 adev->gfx.config.backend_enable_mask = active_rbs; 1490 adev->gfx.config.num_rbs = hweight32(active_rbs); 1491 1492 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1493 adev->gfx.config.max_shader_engines, 16); 1494 1495 gfx_v6_0_raster_config(adev, &raster_config); 1496 1497 if (!adev->gfx.config.backend_enable_mask || 1498 adev->gfx.config.num_rbs >= num_rb_pipes) 1499 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1500 else 1501 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1502 adev->gfx.config.backend_enable_mask, 1503 num_rb_pipes); 1504 1505 /* cache the values for userspace */ 1506 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1507 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1508 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1509 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1510 RREG32(mmCC_RB_BACKEND_DISABLE); 1511 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1512 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1513 adev->gfx.config.rb_config[i][j].raster_config = 1514 RREG32(mmPA_SC_RASTER_CONFIG); 1515 } 1516 } 1517 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1518 mutex_unlock(&adev->grbm_idx_mutex); 1519 } 1520 1521 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1522 u32 bitmap) 1523 { 1524 u32 data; 1525 1526 if (!bitmap) 1527 return; 1528 1529 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1530 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1531 1532 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1533 } 1534 1535 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1536 { 1537 u32 data, mask; 1538 1539 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1540 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1541 1542 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1543 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1544 } 1545 1546 1547 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1548 { 1549 int i, j, k; 1550 u32 data, mask; 1551 u32 active_cu = 0; 1552 1553 mutex_lock(&adev->grbm_idx_mutex); 1554 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1555 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1556 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1557 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1558 active_cu = gfx_v6_0_get_cu_enabled(adev); 1559 1560 mask = 1; 1561 for (k = 0; k < 16; k++) { 1562 mask <<= k; 1563 if (active_cu & mask) { 1564 data &= ~mask; 1565 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1566 break; 1567 } 1568 } 1569 } 1570 } 1571 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1572 mutex_unlock(&adev->grbm_idx_mutex); 1573 } 1574 1575 /** 1576 * gfx_v6_0_setup_tcc() - setup which TCCs are used 1577 * 1578 * @adev: amdgpu_device pointer 1579 * 1580 * Verify whether the current GPU has any TCCs disabled, 1581 * which can happen when the GPU is harvested and some 1582 * memory channels are disabled, reducing the memory bus width. 1583 * For example, on the Radeon HD 7870 XT (Tahiti LE). 1584 * 1585 * If some TCCs are disabled, we need to make sure that 1586 * the disabled TCCs are not used, and the remaining TCCs 1587 * are used optimally. 1588 * 1589 * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels. 1590 * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used. 1591 * 1592 * For optimal performance: 1593 * - Rely on the CHAN_STEER from the golden registers table, 1594 * only skip disabled TCCs but keep the mapping order. 1595 * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing, 1596 * which performs better than using the same TCC twice. 1597 */ 1598 static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) 1599 { 1600 u32 i, tcc, tcp_addr_config, num_active_tcc = 0; 1601 u64 chan_steer, patched_chan_steer = 0; 1602 const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; 1603 const u32 dis_tcc_mask = 1604 amdgpu_gfx_create_bitmask(num_max_tcc) & 1605 (REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE), 1606 CGTS_TCC_DISABLE, TCC_DISABLE) | 1607 REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE), 1608 CGTS_USER_TCC_DISABLE, TCC_DISABLE)); 1609 1610 /* When no TCC is disabled, the golden registers table already has optimal TCC setup */ 1611 if (!dis_tcc_mask) 1612 return; 1613 1614 /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ 1615 chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); 1616 1617 /* Patch the TCP to TCC mapping to skip disabled TCCs */ 1618 for (i = 0; i < num_max_tcc; ++i) { 1619 tcc = (chan_steer >> (u64)(4 * i)) & 0xf; 1620 1621 if (!((1 << tcc) & dis_tcc_mask)) { 1622 /* Copy enabled TCC indices to the patched register value. */ 1623 patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); 1624 ++num_active_tcc; 1625 } 1626 } 1627 1628 WARN_ON(num_active_tcc != num_max_tcc - hweight32(dis_tcc_mask)); 1629 1630 /* Patch number of TCCs used by TCPs */ 1631 tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), 1632 TCP_ADDR_CONFIG, NUM_TCC_BANKS, 1633 num_active_tcc - 1); 1634 1635 WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); 1636 WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); 1637 WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); 1638 } 1639 1640 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1641 { 1642 adev->gfx.config.double_offchip_lds_buf = 0; 1643 } 1644 1645 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1646 { 1647 u32 gb_addr_config = 0; 1648 u32 mc_arb_ramcfg; 1649 u32 sx_debug_1; 1650 u32 hdp_host_path_cntl; 1651 u32 tmp; 1652 1653 switch (adev->asic_type) { 1654 case CHIP_TAHITI: 1655 adev->gfx.config.max_shader_engines = 2; 1656 adev->gfx.config.max_tile_pipes = 12; 1657 adev->gfx.config.max_cu_per_sh = 8; 1658 adev->gfx.config.max_sh_per_se = 2; 1659 adev->gfx.config.max_backends_per_se = 4; 1660 adev->gfx.config.max_texture_channel_caches = 12; 1661 adev->gfx.config.max_gprs = 256; 1662 adev->gfx.config.max_gs_threads = 32; 1663 adev->gfx.config.max_hw_contexts = 8; 1664 1665 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1666 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1667 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1668 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1669 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1670 break; 1671 case CHIP_PITCAIRN: 1672 adev->gfx.config.max_shader_engines = 2; 1673 adev->gfx.config.max_tile_pipes = 8; 1674 adev->gfx.config.max_cu_per_sh = 5; 1675 adev->gfx.config.max_sh_per_se = 2; 1676 adev->gfx.config.max_backends_per_se = 4; 1677 adev->gfx.config.max_texture_channel_caches = 8; 1678 adev->gfx.config.max_gprs = 256; 1679 adev->gfx.config.max_gs_threads = 32; 1680 adev->gfx.config.max_hw_contexts = 8; 1681 1682 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1683 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1684 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1685 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1686 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1687 break; 1688 case CHIP_VERDE: 1689 adev->gfx.config.max_shader_engines = 1; 1690 adev->gfx.config.max_tile_pipes = 4; 1691 adev->gfx.config.max_cu_per_sh = 5; 1692 adev->gfx.config.max_sh_per_se = 2; 1693 adev->gfx.config.max_backends_per_se = 4; 1694 adev->gfx.config.max_texture_channel_caches = 4; 1695 adev->gfx.config.max_gprs = 256; 1696 adev->gfx.config.max_gs_threads = 32; 1697 adev->gfx.config.max_hw_contexts = 8; 1698 1699 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1700 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1701 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1702 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1703 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1704 break; 1705 case CHIP_OLAND: 1706 adev->gfx.config.max_shader_engines = 1; 1707 adev->gfx.config.max_tile_pipes = 4; 1708 adev->gfx.config.max_cu_per_sh = 6; 1709 adev->gfx.config.max_sh_per_se = 1; 1710 adev->gfx.config.max_backends_per_se = 2; 1711 adev->gfx.config.max_texture_channel_caches = 4; 1712 adev->gfx.config.max_gprs = 256; 1713 adev->gfx.config.max_gs_threads = 16; 1714 adev->gfx.config.max_hw_contexts = 8; 1715 1716 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1717 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1718 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1719 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1720 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1721 break; 1722 case CHIP_HAINAN: 1723 adev->gfx.config.max_shader_engines = 1; 1724 adev->gfx.config.max_tile_pipes = 4; 1725 adev->gfx.config.max_cu_per_sh = 5; 1726 adev->gfx.config.max_sh_per_se = 1; 1727 adev->gfx.config.max_backends_per_se = 1; 1728 adev->gfx.config.max_texture_channel_caches = 2; 1729 adev->gfx.config.max_gprs = 256; 1730 adev->gfx.config.max_gs_threads = 16; 1731 adev->gfx.config.max_hw_contexts = 8; 1732 1733 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1734 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1735 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1736 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1737 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1738 break; 1739 default: 1740 dev_warn(adev->dev, "Unsupported asic_type 0x%08x\n", adev->asic_type); 1741 return; 1742 } 1743 1744 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1745 WREG32(mmSRBM_INT_CNTL, 1); 1746 WREG32(mmSRBM_INT_ACK, 1); 1747 1748 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1749 1750 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1751 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1752 1753 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1754 adev->gfx.config.mem_max_burst_length_bytes = 256; 1755 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1756 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1757 if (adev->gfx.config.mem_row_size_in_kb > 4) 1758 adev->gfx.config.mem_row_size_in_kb = 4; 1759 adev->gfx.config.shader_engine_tile_size = 32; 1760 adev->gfx.config.num_gpus = 1; 1761 adev->gfx.config.multi_gpu_tile_size = 64; 1762 1763 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1764 switch (adev->gfx.config.mem_row_size_in_kb) { 1765 case 1: 1766 default: 1767 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1768 break; 1769 case 2: 1770 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1771 break; 1772 case 4: 1773 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1774 break; 1775 } 1776 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1777 if (adev->gfx.config.max_shader_engines == 2) 1778 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1779 adev->gfx.config.gb_addr_config = gb_addr_config; 1780 1781 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1782 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1783 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1784 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1785 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1786 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1787 1788 #if 0 1789 if (adev->has_uvd) { 1790 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1791 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1792 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1793 } 1794 #endif 1795 gfx_v6_0_tiling_mode_table_init(adev); 1796 1797 gfx_v6_0_setup_rb(adev); 1798 gfx_v6_0_setup_tcc(adev); 1799 1800 gfx_v6_0_setup_spi(adev); 1801 1802 gfx_v6_0_get_cu_info(adev); 1803 gfx_v6_0_config_init(adev); 1804 1805 WREG32(mmCP_QUEUE_THRESHOLDS, 1806 ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1807 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1808 1809 /* set HW defaults for 3D engine */ 1810 WREG32(mmCP_MEQ_THRESHOLDS, 1811 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1812 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1813 1814 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1815 WREG32(mmSX_DEBUG_1, sx_debug_1); 1816 1817 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1818 1819 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1820 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1821 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1822 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1823 1824 WREG32(mmVGT_NUM_INSTANCES, 1); 1825 WREG32(mmCP_PERFMON_CNTL, 0); 1826 WREG32(mmSQ_CONFIG, 0); 1827 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1828 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1829 1830 WREG32(mmVGT_CACHE_INVALIDATION, 1831 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1832 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1833 1834 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1835 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1836 1837 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1838 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1839 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1840 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1841 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1842 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1843 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1844 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1845 1846 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1847 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1848 1849 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1850 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1851 1852 udelay(50); 1853 } 1854 1855 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1856 { 1857 struct amdgpu_device *adev = ring->adev; 1858 uint32_t tmp = 0; 1859 unsigned i; 1860 int r; 1861 1862 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1863 1864 r = amdgpu_ring_alloc(ring, 3); 1865 if (r) 1866 return r; 1867 1868 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1869 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); 1870 amdgpu_ring_write(ring, 0xDEADBEEF); 1871 amdgpu_ring_commit(ring); 1872 1873 for (i = 0; i < adev->usec_timeout; i++) { 1874 tmp = RREG32(mmSCRATCH_REG0); 1875 if (tmp == 0xDEADBEEF) 1876 break; 1877 udelay(1); 1878 } 1879 1880 if (i >= adev->usec_timeout) 1881 r = -ETIMEDOUT; 1882 return r; 1883 } 1884 1885 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1886 { 1887 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1888 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1889 EVENT_INDEX(0)); 1890 } 1891 1892 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1893 u64 seq, unsigned flags) 1894 { 1895 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1896 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1897 /* flush read cache over gart */ 1898 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1899 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1900 amdgpu_ring_write(ring, 0); 1901 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1902 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1903 PACKET3_TC_ACTION_ENA | 1904 PACKET3_SH_KCACHE_ACTION_ENA | 1905 PACKET3_SH_ICACHE_ACTION_ENA); 1906 amdgpu_ring_write(ring, 0xFFFFFFFF); 1907 amdgpu_ring_write(ring, 0); 1908 amdgpu_ring_write(ring, 10); /* poll interval */ 1909 /* EVENT_WRITE_EOP - flush caches, send int */ 1910 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1911 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1912 amdgpu_ring_write(ring, addr & 0xfffffffc); 1913 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1914 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1915 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1916 amdgpu_ring_write(ring, lower_32_bits(seq)); 1917 amdgpu_ring_write(ring, upper_32_bits(seq)); 1918 } 1919 1920 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1921 struct amdgpu_job *job, 1922 struct amdgpu_ib *ib, 1923 uint32_t flags) 1924 { 1925 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1926 u32 header, control = 0; 1927 1928 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1929 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1930 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1931 amdgpu_ring_write(ring, 0); 1932 } 1933 1934 if (ib->flags & AMDGPU_IB_FLAG_CE) 1935 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1936 else 1937 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1938 1939 control |= ib->length_dw | (vmid << 24); 1940 1941 amdgpu_ring_write(ring, header); 1942 amdgpu_ring_write(ring, 1943 #ifdef __BIG_ENDIAN 1944 (2 << 0) | 1945 #endif 1946 (ib->gpu_addr & 0xFFFFFFFC)); 1947 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1948 amdgpu_ring_write(ring, control); 1949 } 1950 1951 /** 1952 * gfx_v6_0_ring_test_ib - basic ring IB test 1953 * 1954 * @ring: amdgpu_ring structure holding ring information 1955 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1956 * 1957 * Allocate an IB and execute it on the gfx ring (SI). 1958 * Provides a basic gfx ring test to verify that IBs are working. 1959 * Returns 0 on success, error on failure. 1960 */ 1961 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1962 { 1963 struct amdgpu_device *adev = ring->adev; 1964 struct dma_fence *f = NULL; 1965 struct amdgpu_ib ib; 1966 uint32_t tmp = 0; 1967 long r; 1968 1969 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1970 memset(&ib, 0, sizeof(ib)); 1971 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1972 if (r) 1973 return r; 1974 1975 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1976 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; 1977 ib.ptr[2] = 0xDEADBEEF; 1978 ib.length_dw = 3; 1979 1980 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1981 if (r) 1982 goto error; 1983 1984 r = dma_fence_wait_timeout(f, false, timeout); 1985 if (r == 0) { 1986 r = -ETIMEDOUT; 1987 goto error; 1988 } else if (r < 0) { 1989 goto error; 1990 } 1991 tmp = RREG32(mmSCRATCH_REG0); 1992 if (tmp == 0xDEADBEEF) 1993 r = 0; 1994 else 1995 r = -EINVAL; 1996 1997 error: 1998 amdgpu_ib_free(&ib, NULL); 1999 dma_fence_put(f); 2000 return r; 2001 } 2002 2003 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2004 { 2005 if (enable) { 2006 WREG32(mmCP_ME_CNTL, 0); 2007 } else { 2008 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2009 CP_ME_CNTL__PFP_HALT_MASK | 2010 CP_ME_CNTL__CE_HALT_MASK)); 2011 WREG32(mmSCRATCH_UMSK, 0); 2012 } 2013 udelay(50); 2014 } 2015 2016 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2017 { 2018 unsigned i; 2019 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2020 const struct gfx_firmware_header_v1_0 *ce_hdr; 2021 const struct gfx_firmware_header_v1_0 *me_hdr; 2022 const __le32 *fw_data; 2023 u32 fw_size; 2024 2025 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2026 return -EINVAL; 2027 2028 gfx_v6_0_cp_gfx_enable(adev, false); 2029 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2030 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2031 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2032 2033 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2034 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2035 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2036 2037 /* PFP */ 2038 fw_data = (const __le32 *) 2039 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2040 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2041 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2042 for (i = 0; i < fw_size; i++) 2043 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2044 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2045 2046 /* CE */ 2047 fw_data = (const __le32 *) 2048 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2049 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2050 WREG32(mmCP_CE_UCODE_ADDR, 0); 2051 for (i = 0; i < fw_size; i++) 2052 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2053 WREG32(mmCP_CE_UCODE_ADDR, 0); 2054 2055 /* ME */ 2056 fw_data = (const __be32 *) 2057 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2058 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2059 WREG32(mmCP_ME_RAM_WADDR, 0); 2060 for (i = 0; i < fw_size; i++) 2061 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2062 WREG32(mmCP_ME_RAM_WADDR, 0); 2063 2064 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2065 WREG32(mmCP_CE_UCODE_ADDR, 0); 2066 WREG32(mmCP_ME_RAM_WADDR, 0); 2067 WREG32(mmCP_ME_RAM_RADDR, 0); 2068 return 0; 2069 } 2070 2071 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2072 { 2073 const struct cs_section_def *sect = NULL; 2074 const struct cs_extent_def *ext = NULL; 2075 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2076 int r, i; 2077 2078 r = amdgpu_ring_alloc(ring, 7 + 4); 2079 if (r) { 2080 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2081 return r; 2082 } 2083 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2084 amdgpu_ring_write(ring, 0x1); 2085 amdgpu_ring_write(ring, 0x0); 2086 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2087 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2088 amdgpu_ring_write(ring, 0); 2089 amdgpu_ring_write(ring, 0); 2090 2091 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2092 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2093 amdgpu_ring_write(ring, 0xc000); 2094 amdgpu_ring_write(ring, 0xe000); 2095 amdgpu_ring_commit(ring); 2096 2097 gfx_v6_0_cp_gfx_enable(adev, true); 2098 2099 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2100 if (r) { 2101 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2102 return r; 2103 } 2104 2105 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2106 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2107 2108 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2109 for (ext = sect->section; ext->extent != NULL; ++ext) { 2110 if (sect->id == SECT_CONTEXT) { 2111 amdgpu_ring_write(ring, 2112 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2113 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2114 for (i = 0; i < ext->reg_count; i++) 2115 amdgpu_ring_write(ring, ext->extent[i]); 2116 } 2117 } 2118 } 2119 2120 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2121 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2122 2123 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2124 amdgpu_ring_write(ring, 0); 2125 2126 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2127 amdgpu_ring_write(ring, 0x00000316); 2128 amdgpu_ring_write(ring, 0x0000000e); 2129 amdgpu_ring_write(ring, 0x00000010); 2130 2131 amdgpu_ring_commit(ring); 2132 2133 return 0; 2134 } 2135 2136 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2137 { 2138 struct amdgpu_ring *ring; 2139 u32 tmp; 2140 u32 rb_bufsz; 2141 int r; 2142 u64 rptr_addr; 2143 2144 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2145 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2146 2147 /* Set the write pointer delay */ 2148 WREG32(mmCP_RB_WPTR_DELAY, 0); 2149 2150 WREG32(mmCP_DEBUG, 0); 2151 WREG32(mmSCRATCH_ADDR, 0); 2152 2153 /* ring 0 - compute and gfx */ 2154 /* Set ring buffer size */ 2155 ring = &adev->gfx.gfx_ring[0]; 2156 rb_bufsz = order_base_2(ring->ring_size / 8); 2157 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2158 2159 #ifdef __BIG_ENDIAN 2160 tmp |= BUF_SWAP_32BIT; 2161 #endif 2162 WREG32(mmCP_RB0_CNTL, tmp); 2163 2164 /* Initialize the ring buffer's read and write pointers */ 2165 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2166 ring->wptr = 0; 2167 WREG32(mmCP_RB0_WPTR, ring->wptr); 2168 2169 /* set the wb address whether it's enabled or not */ 2170 rptr_addr = ring->rptr_gpu_addr; 2171 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2172 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2173 2174 WREG32(mmSCRATCH_UMSK, 0); 2175 2176 mdelay(1); 2177 WREG32(mmCP_RB0_CNTL, tmp); 2178 2179 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2180 2181 /* start the rings */ 2182 gfx_v6_0_cp_gfx_start(adev); 2183 r = amdgpu_ring_test_helper(ring); 2184 if (r) 2185 return r; 2186 2187 return 0; 2188 } 2189 2190 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2191 { 2192 return *ring->rptr_cpu_addr; 2193 } 2194 2195 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2196 { 2197 struct amdgpu_device *adev = ring->adev; 2198 2199 if (ring == &adev->gfx.gfx_ring[0]) 2200 return RREG32(mmCP_RB0_WPTR); 2201 else if (ring == &adev->gfx.compute_ring[0]) 2202 return RREG32(mmCP_RB1_WPTR); 2203 else if (ring == &adev->gfx.compute_ring[1]) 2204 return RREG32(mmCP_RB2_WPTR); 2205 else 2206 return 0; 2207 } 2208 2209 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2210 { 2211 struct amdgpu_device *adev = ring->adev; 2212 2213 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2214 (void)RREG32(mmCP_RB0_WPTR); 2215 } 2216 2217 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2218 { 2219 struct amdgpu_device *adev = ring->adev; 2220 2221 if (ring == &adev->gfx.compute_ring[0]) { 2222 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2223 (void)RREG32(mmCP_RB1_WPTR); 2224 } else if (ring == &adev->gfx.compute_ring[1]) { 2225 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2226 (void)RREG32(mmCP_RB2_WPTR); 2227 } 2228 2229 } 2230 2231 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2232 { 2233 struct amdgpu_ring *ring; 2234 u32 tmp; 2235 u32 rb_bufsz; 2236 int i, r; 2237 u64 rptr_addr; 2238 2239 /* ring1 - compute only */ 2240 /* Set ring buffer size */ 2241 2242 ring = &adev->gfx.compute_ring[0]; 2243 rb_bufsz = order_base_2(ring->ring_size / 8); 2244 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2245 #ifdef __BIG_ENDIAN 2246 tmp |= BUF_SWAP_32BIT; 2247 #endif 2248 WREG32(mmCP_RB1_CNTL, tmp); 2249 2250 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2251 ring->wptr = 0; 2252 WREG32(mmCP_RB1_WPTR, ring->wptr); 2253 2254 rptr_addr = ring->rptr_gpu_addr; 2255 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2256 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2257 2258 mdelay(1); 2259 WREG32(mmCP_RB1_CNTL, tmp); 2260 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2261 2262 ring = &adev->gfx.compute_ring[1]; 2263 rb_bufsz = order_base_2(ring->ring_size / 8); 2264 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2265 #ifdef __BIG_ENDIAN 2266 tmp |= BUF_SWAP_32BIT; 2267 #endif 2268 WREG32(mmCP_RB2_CNTL, tmp); 2269 2270 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2271 ring->wptr = 0; 2272 WREG32(mmCP_RB2_WPTR, ring->wptr); 2273 rptr_addr = ring->rptr_gpu_addr; 2274 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2275 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2276 2277 mdelay(1); 2278 WREG32(mmCP_RB2_CNTL, tmp); 2279 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2280 2281 2282 for (i = 0; i < 2; i++) { 2283 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2284 if (r) 2285 return r; 2286 } 2287 2288 return 0; 2289 } 2290 2291 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2292 { 2293 gfx_v6_0_cp_gfx_enable(adev, enable); 2294 } 2295 2296 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2297 { 2298 return gfx_v6_0_cp_gfx_load_microcode(adev); 2299 } 2300 2301 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2302 bool enable) 2303 { 2304 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2305 u32 mask; 2306 int i; 2307 2308 if (enable) 2309 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2310 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2311 else 2312 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2313 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2314 WREG32(mmCP_INT_CNTL_RING0, tmp); 2315 2316 if (!enable) { 2317 /* read a gfx register */ 2318 tmp = RREG32(mmDB_DEPTH_INFO); 2319 2320 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2321 for (i = 0; i < adev->usec_timeout; i++) { 2322 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2323 break; 2324 udelay(1); 2325 } 2326 } 2327 } 2328 2329 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2330 { 2331 int r; 2332 2333 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2334 2335 r = gfx_v6_0_cp_load_microcode(adev); 2336 if (r) 2337 return r; 2338 2339 r = gfx_v6_0_cp_gfx_resume(adev); 2340 if (r) 2341 return r; 2342 r = gfx_v6_0_cp_compute_resume(adev); 2343 if (r) 2344 return r; 2345 2346 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2347 2348 return 0; 2349 } 2350 2351 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2352 { 2353 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2354 uint32_t seq = ring->fence_drv.sync_seq; 2355 uint64_t addr = ring->fence_drv.gpu_addr; 2356 2357 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2358 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2359 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2360 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2361 amdgpu_ring_write(ring, addr & 0xfffffffc); 2362 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2363 amdgpu_ring_write(ring, seq); 2364 amdgpu_ring_write(ring, 0xffffffff); 2365 amdgpu_ring_write(ring, 4); /* poll interval */ 2366 2367 if (usepfp) { 2368 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2369 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2370 amdgpu_ring_write(ring, 0); 2371 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2372 amdgpu_ring_write(ring, 0); 2373 } 2374 } 2375 2376 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2377 unsigned vmid, uint64_t pd_addr) 2378 { 2379 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2380 2381 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2382 2383 /* wait for the invalidate to complete */ 2384 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2385 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2386 WAIT_REG_MEM_ENGINE(0))); /* me */ 2387 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2388 amdgpu_ring_write(ring, 0); 2389 amdgpu_ring_write(ring, 0); /* ref */ 2390 amdgpu_ring_write(ring, 0); /* mask */ 2391 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2392 2393 if (usepfp) { 2394 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2395 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2396 amdgpu_ring_write(ring, 0x0); 2397 2398 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2399 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2400 amdgpu_ring_write(ring, 0); 2401 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2402 amdgpu_ring_write(ring, 0); 2403 } 2404 } 2405 2406 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2407 uint32_t reg, uint32_t val) 2408 { 2409 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2410 2411 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2412 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2413 WRITE_DATA_DST_SEL(0))); 2414 amdgpu_ring_write(ring, reg); 2415 amdgpu_ring_write(ring, 0); 2416 amdgpu_ring_write(ring, val); 2417 } 2418 2419 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2420 { 2421 const u32 *src_ptr; 2422 u32 *dst_ptr; 2423 u32 dws; 2424 u64 reg_list_mc_addr; 2425 const struct cs_section_def *cs_data; 2426 int r; 2427 2428 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2429 adev->gfx.rlc.reg_list_size = 2430 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2431 2432 adev->gfx.rlc.cs_data = si_cs_data; 2433 src_ptr = adev->gfx.rlc.reg_list; 2434 dws = adev->gfx.rlc.reg_list_size; 2435 cs_data = adev->gfx.rlc.cs_data; 2436 2437 if (src_ptr) { 2438 /* init save restore block */ 2439 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2440 if (r) 2441 return r; 2442 } 2443 2444 if (cs_data) { 2445 /* clear state block */ 2446 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2447 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2448 2449 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2450 AMDGPU_GEM_DOMAIN_VRAM | 2451 AMDGPU_GEM_DOMAIN_GTT, 2452 &adev->gfx.rlc.clear_state_obj, 2453 &adev->gfx.rlc.clear_state_gpu_addr, 2454 (void **)&adev->gfx.rlc.cs_ptr); 2455 if (r) { 2456 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2457 amdgpu_gfx_rlc_fini(adev); 2458 return r; 2459 } 2460 2461 /* set up the cs buffer */ 2462 dst_ptr = adev->gfx.rlc.cs_ptr; 2463 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2464 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2465 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2466 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2467 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2468 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2469 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2476 { 2477 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2478 2479 if (!enable) { 2480 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2481 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2482 } 2483 } 2484 2485 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2486 { 2487 int i; 2488 2489 for (i = 0; i < adev->usec_timeout; i++) { 2490 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2491 break; 2492 udelay(1); 2493 } 2494 2495 for (i = 0; i < adev->usec_timeout; i++) { 2496 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2497 break; 2498 udelay(1); 2499 } 2500 } 2501 2502 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2503 { 2504 u32 tmp; 2505 2506 tmp = RREG32(mmRLC_CNTL); 2507 if (tmp != rlc) 2508 WREG32(mmRLC_CNTL, rlc); 2509 } 2510 2511 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2512 { 2513 u32 data, orig; 2514 2515 orig = data = RREG32(mmRLC_CNTL); 2516 2517 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2518 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2519 WREG32(mmRLC_CNTL, data); 2520 2521 gfx_v6_0_wait_for_rlc_serdes(adev); 2522 } 2523 2524 return orig; 2525 } 2526 2527 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2528 { 2529 WREG32(mmRLC_CNTL, 0); 2530 2531 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2532 gfx_v6_0_wait_for_rlc_serdes(adev); 2533 } 2534 2535 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2536 { 2537 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2538 2539 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2540 2541 udelay(50); 2542 } 2543 2544 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2545 { 2546 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2547 udelay(50); 2548 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2549 udelay(50); 2550 } 2551 2552 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2553 { 2554 u32 tmp; 2555 2556 /* Enable LBPW only for DDR3 */ 2557 tmp = RREG32(mmMC_SEQ_MISC0); 2558 if ((tmp & 0xF0000000) == 0xB0000000) 2559 return true; 2560 return false; 2561 } 2562 2563 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2564 { 2565 } 2566 2567 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2568 { 2569 u32 i; 2570 const struct rlc_firmware_header_v1_0 *hdr; 2571 const __le32 *fw_data; 2572 u32 fw_size; 2573 2574 2575 if (!adev->gfx.rlc_fw) 2576 return -EINVAL; 2577 2578 adev->gfx.rlc.funcs->stop(adev); 2579 adev->gfx.rlc.funcs->reset(adev); 2580 gfx_v6_0_init_pg(adev); 2581 gfx_v6_0_init_cg(adev); 2582 2583 WREG32(mmRLC_RL_BASE, 0); 2584 WREG32(mmRLC_RL_SIZE, 0); 2585 WREG32(mmRLC_LB_CNTL, 0); 2586 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2587 WREG32(mmRLC_LB_CNTR_INIT, 0); 2588 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2589 2590 WREG32(mmRLC_MC_CNTL, 0); 2591 WREG32(mmRLC_UCODE_CNTL, 0); 2592 2593 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2594 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2595 fw_data = (const __le32 *) 2596 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2597 2598 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2599 2600 for (i = 0; i < fw_size; i++) { 2601 WREG32(mmRLC_UCODE_ADDR, i); 2602 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2603 } 2604 WREG32(mmRLC_UCODE_ADDR, 0); 2605 2606 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2607 adev->gfx.rlc.funcs->start(adev); 2608 2609 return 0; 2610 } 2611 2612 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2613 { 2614 u32 data, orig, tmp; 2615 2616 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2617 2618 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2619 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2620 2621 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2622 2623 tmp = gfx_v6_0_halt_rlc(adev); 2624 2625 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2626 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2627 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2628 2629 gfx_v6_0_wait_for_rlc_serdes(adev); 2630 gfx_v6_0_update_rlc(adev, tmp); 2631 2632 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2633 2634 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2635 } else { 2636 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2637 2638 RREG32(mmCB_CGTT_SCLK_CTRL); 2639 RREG32(mmCB_CGTT_SCLK_CTRL); 2640 RREG32(mmCB_CGTT_SCLK_CTRL); 2641 RREG32(mmCB_CGTT_SCLK_CTRL); 2642 2643 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2644 } 2645 2646 if (orig != data) 2647 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2648 2649 } 2650 2651 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2652 { 2653 2654 u32 data, orig, tmp = 0; 2655 2656 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2657 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2658 data = 0x96940200; 2659 if (orig != data) 2660 WREG32(mmCGTS_SM_CTRL_REG, data); 2661 2662 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2663 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2664 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2665 if (orig != data) 2666 WREG32(mmCP_MEM_SLP_CNTL, data); 2667 } 2668 2669 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2670 data &= 0xffffffc0; 2671 if (orig != data) 2672 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2673 2674 tmp = gfx_v6_0_halt_rlc(adev); 2675 2676 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2677 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2678 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2679 2680 gfx_v6_0_update_rlc(adev, tmp); 2681 } else { 2682 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2683 data |= 0x00000003; 2684 if (orig != data) 2685 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2686 2687 data = RREG32(mmCP_MEM_SLP_CNTL); 2688 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2689 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2690 WREG32(mmCP_MEM_SLP_CNTL, data); 2691 } 2692 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2693 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2694 if (orig != data) 2695 WREG32(mmCGTS_SM_CTRL_REG, data); 2696 2697 tmp = gfx_v6_0_halt_rlc(adev); 2698 2699 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2700 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2701 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2702 2703 gfx_v6_0_update_rlc(adev, tmp); 2704 } 2705 } 2706 /* 2707 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2708 bool enable) 2709 { 2710 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2711 if (enable) { 2712 gfx_v6_0_enable_mgcg(adev, true); 2713 gfx_v6_0_enable_cgcg(adev, true); 2714 } else { 2715 gfx_v6_0_enable_cgcg(adev, false); 2716 gfx_v6_0_enable_mgcg(adev, false); 2717 } 2718 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2719 } 2720 */ 2721 2722 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2723 bool enable) 2724 { 2725 } 2726 2727 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2728 bool enable) 2729 { 2730 } 2731 2732 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2733 { 2734 u32 data, orig; 2735 2736 orig = data = RREG32(mmRLC_PG_CNTL); 2737 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2738 data &= ~0x8000; 2739 else 2740 data |= 0x8000; 2741 if (orig != data) 2742 WREG32(mmRLC_PG_CNTL, data); 2743 } 2744 2745 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2746 { 2747 } 2748 /* 2749 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2750 { 2751 const __le32 *fw_data; 2752 volatile u32 *dst_ptr; 2753 int me, i, max_me = 4; 2754 u32 bo_offset = 0; 2755 u32 table_offset, table_size; 2756 2757 if (adev->asic_type == CHIP_KAVERI) 2758 max_me = 5; 2759 2760 if (adev->gfx.rlc.cp_table_ptr == NULL) 2761 return; 2762 2763 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2764 for (me = 0; me < max_me; me++) { 2765 if (me == 0) { 2766 const struct gfx_firmware_header_v1_0 *hdr = 2767 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2768 fw_data = (const __le32 *) 2769 (adev->gfx.ce_fw->data + 2770 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2771 table_offset = le32_to_cpu(hdr->jt_offset); 2772 table_size = le32_to_cpu(hdr->jt_size); 2773 } else if (me == 1) { 2774 const struct gfx_firmware_header_v1_0 *hdr = 2775 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2776 fw_data = (const __le32 *) 2777 (adev->gfx.pfp_fw->data + 2778 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2779 table_offset = le32_to_cpu(hdr->jt_offset); 2780 table_size = le32_to_cpu(hdr->jt_size); 2781 } else if (me == 2) { 2782 const struct gfx_firmware_header_v1_0 *hdr = 2783 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2784 fw_data = (const __le32 *) 2785 (adev->gfx.me_fw->data + 2786 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2787 table_offset = le32_to_cpu(hdr->jt_offset); 2788 table_size = le32_to_cpu(hdr->jt_size); 2789 } else if (me == 3) { 2790 const struct gfx_firmware_header_v1_0 *hdr = 2791 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2792 fw_data = (const __le32 *) 2793 (adev->gfx.mec_fw->data + 2794 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2795 table_offset = le32_to_cpu(hdr->jt_offset); 2796 table_size = le32_to_cpu(hdr->jt_size); 2797 } else { 2798 const struct gfx_firmware_header_v1_0 *hdr = 2799 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2800 fw_data = (const __le32 *) 2801 (adev->gfx.mec2_fw->data + 2802 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2803 table_offset = le32_to_cpu(hdr->jt_offset); 2804 table_size = le32_to_cpu(hdr->jt_size); 2805 } 2806 2807 for (i = 0; i < table_size; i ++) { 2808 dst_ptr[bo_offset + i] = 2809 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2810 } 2811 2812 bo_offset += table_size; 2813 } 2814 } 2815 */ 2816 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2817 bool enable) 2818 { 2819 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2820 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2821 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2822 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2823 } else { 2824 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2825 (void)RREG32(mmDB_RENDER_CONTROL); 2826 } 2827 } 2828 2829 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2830 { 2831 u32 tmp; 2832 2833 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2834 2835 tmp = RREG32(mmRLC_MAX_PG_CU); 2836 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2837 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2838 WREG32(mmRLC_MAX_PG_CU, tmp); 2839 } 2840 2841 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2842 bool enable) 2843 { 2844 u32 data, orig; 2845 2846 orig = data = RREG32(mmRLC_PG_CNTL); 2847 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2848 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2849 else 2850 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2851 if (orig != data) 2852 WREG32(mmRLC_PG_CNTL, data); 2853 } 2854 2855 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2856 bool enable) 2857 { 2858 u32 data, orig; 2859 2860 orig = data = RREG32(mmRLC_PG_CNTL); 2861 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2862 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2863 else 2864 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2865 if (orig != data) 2866 WREG32(mmRLC_PG_CNTL, data); 2867 } 2868 2869 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2870 { 2871 u32 tmp; 2872 2873 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2874 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2875 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2876 2877 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2878 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2879 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2880 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2881 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2882 } 2883 2884 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2885 { 2886 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2887 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2888 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2889 } 2890 2891 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2892 { 2893 u32 count = 0; 2894 const struct cs_section_def *sect = NULL; 2895 const struct cs_extent_def *ext = NULL; 2896 2897 if (adev->gfx.rlc.cs_data == NULL) 2898 return 0; 2899 2900 /* begin clear state */ 2901 count += 2; 2902 /* context control state */ 2903 count += 3; 2904 2905 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2906 for (ext = sect->section; ext->extent != NULL; ++ext) { 2907 if (sect->id == SECT_CONTEXT) 2908 count += 2 + ext->reg_count; 2909 else 2910 return 0; 2911 } 2912 } 2913 /* pa_sc_raster_config */ 2914 count += 3; 2915 /* end clear state */ 2916 count += 2; 2917 /* clear state */ 2918 count += 2; 2919 2920 return count; 2921 } 2922 2923 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 2924 { 2925 u32 count = 0; 2926 2927 if (adev->gfx.rlc.cs_data == NULL) 2928 return; 2929 if (buffer == NULL) 2930 return; 2931 2932 count = amdgpu_gfx_csb_preamble_start(buffer); 2933 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 2934 2935 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2936 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2937 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2938 2939 amdgpu_gfx_csb_preamble_end(buffer, count); 2940 } 2941 2942 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2943 { 2944 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2945 AMD_PG_SUPPORT_GFX_SMG | 2946 AMD_PG_SUPPORT_GFX_DMG | 2947 AMD_PG_SUPPORT_CP | 2948 AMD_PG_SUPPORT_GDS | 2949 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2950 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2951 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2952 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2953 gfx_v6_0_init_gfx_cgpg(adev); 2954 gfx_v6_0_enable_cp_pg(adev, true); 2955 gfx_v6_0_enable_gds_pg(adev, true); 2956 } else { 2957 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2958 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2959 2960 } 2961 gfx_v6_0_init_ao_cu_mask(adev); 2962 gfx_v6_0_update_gfx_pg(adev, true); 2963 } else { 2964 2965 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2966 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2967 } 2968 } 2969 2970 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2971 { 2972 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2973 AMD_PG_SUPPORT_GFX_SMG | 2974 AMD_PG_SUPPORT_GFX_DMG | 2975 AMD_PG_SUPPORT_CP | 2976 AMD_PG_SUPPORT_GDS | 2977 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2978 gfx_v6_0_update_gfx_pg(adev, false); 2979 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2980 gfx_v6_0_enable_cp_pg(adev, false); 2981 gfx_v6_0_enable_gds_pg(adev, false); 2982 } 2983 } 2984 } 2985 2986 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2987 { 2988 uint64_t clock; 2989 2990 mutex_lock(&adev->gfx.gpu_clock_mutex); 2991 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2992 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2993 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2994 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2995 return clock; 2996 } 2997 2998 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2999 { 3000 if (flags & AMDGPU_HAVE_CTX_SWITCH) 3001 gfx_v6_0_ring_emit_vgt_flush(ring); 3002 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3003 amdgpu_ring_write(ring, 0x80000000); 3004 amdgpu_ring_write(ring, 0); 3005 } 3006 3007 3008 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 3009 { 3010 WREG32(mmSQ_IND_INDEX, 3011 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3012 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3013 (address << SQ_IND_INDEX__INDEX__SHIFT) | 3014 (SQ_IND_INDEX__FORCE_READ_MASK)); 3015 return RREG32(mmSQ_IND_DATA); 3016 } 3017 3018 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3019 uint32_t wave, uint32_t thread, 3020 uint32_t regno, uint32_t num, uint32_t *out) 3021 { 3022 WREG32(mmSQ_IND_INDEX, 3023 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3024 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3025 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3026 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3027 (SQ_IND_INDEX__FORCE_READ_MASK) | 3028 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3029 while (num--) 3030 *(out++) = RREG32(mmSQ_IND_DATA); 3031 } 3032 3033 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3034 { 3035 /* type 0 wave data */ 3036 dst[(*no_fields)++] = 0; 3037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3053 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3054 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3055 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 3056 } 3057 3058 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 3059 uint32_t wave, uint32_t start, 3060 uint32_t size, uint32_t *dst) 3061 { 3062 wave_read_regs( 3063 adev, simd, wave, 0, 3064 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3065 } 3066 3067 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3068 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3069 { 3070 drm_info(adev_to_drm(adev), "Not implemented\n"); 3071 } 3072 3073 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3074 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3075 .select_se_sh = &gfx_v6_0_select_se_sh, 3076 .read_wave_data = &gfx_v6_0_read_wave_data, 3077 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3078 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3079 }; 3080 3081 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3082 .init = gfx_v6_0_rlc_init, 3083 .resume = gfx_v6_0_rlc_resume, 3084 .stop = gfx_v6_0_rlc_stop, 3085 .reset = gfx_v6_0_rlc_reset, 3086 .start = gfx_v6_0_rlc_start 3087 }; 3088 3089 static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) 3090 { 3091 struct amdgpu_device *adev = ip_block->adev; 3092 3093 adev->gfx.xcc_mask = 1; 3094 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3095 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3096 GFX6_NUM_COMPUTE_RINGS); 3097 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3098 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3099 gfx_v6_0_set_ring_funcs(adev); 3100 gfx_v6_0_set_irq_funcs(adev); 3101 3102 return 0; 3103 } 3104 3105 static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 3106 { 3107 struct amdgpu_ring *ring; 3108 struct amdgpu_device *adev = ip_block->adev; 3109 int i, r; 3110 3111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3112 if (r) 3113 return r; 3114 3115 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3116 if (r) 3117 return r; 3118 3119 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3120 if (r) 3121 return r; 3122 3123 r = gfx_v6_0_init_microcode(adev); 3124 if (r) { 3125 DRM_ERROR("Failed to load gfx firmware!\n"); 3126 return r; 3127 } 3128 3129 r = adev->gfx.rlc.funcs->init(adev); 3130 if (r) { 3131 DRM_ERROR("Failed to init rlc BOs!\n"); 3132 return r; 3133 } 3134 3135 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3136 ring = &adev->gfx.gfx_ring[i]; 3137 ring->ring_obj = NULL; 3138 sprintf(ring->name, "gfx"); 3139 r = amdgpu_ring_init(adev, ring, 2048, 3140 &adev->gfx.eop_irq, 3141 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3142 AMDGPU_RING_PRIO_DEFAULT, NULL); 3143 if (r) 3144 return r; 3145 } 3146 3147 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3148 unsigned irq_type; 3149 3150 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3151 DRM_ERROR("Too many (%d) compute rings!\n", i); 3152 break; 3153 } 3154 ring = &adev->gfx.compute_ring[i]; 3155 ring->ring_obj = NULL; 3156 ring->use_doorbell = false; 3157 ring->doorbell_index = 0; 3158 ring->me = 1; 3159 ring->pipe = i; 3160 ring->queue = i; 3161 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3162 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3163 r = amdgpu_ring_init(adev, ring, 1024, 3164 &adev->gfx.eop_irq, irq_type, 3165 AMDGPU_RING_PRIO_DEFAULT, NULL); 3166 if (r) 3167 return r; 3168 } 3169 3170 adev->gfx.gfx_supported_reset = 3171 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 3172 adev->gfx.compute_supported_reset = 3173 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 3174 3175 return r; 3176 } 3177 3178 static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 3179 { 3180 int i; 3181 struct amdgpu_device *adev = ip_block->adev; 3182 3183 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3184 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3185 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3186 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3187 3188 amdgpu_gfx_rlc_fini(adev); 3189 3190 return 0; 3191 } 3192 3193 static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 3194 { 3195 int r; 3196 struct amdgpu_device *adev = ip_block->adev; 3197 3198 gfx_v6_0_constants_init(adev); 3199 3200 r = adev->gfx.rlc.funcs->resume(adev); 3201 if (r) 3202 return r; 3203 3204 r = gfx_v6_0_cp_resume(adev); 3205 if (r) 3206 return r; 3207 3208 adev->gfx.ce_ram_size = 0x8000; 3209 3210 return r; 3211 } 3212 3213 static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 3214 { 3215 struct amdgpu_device *adev = ip_block->adev; 3216 3217 gfx_v6_0_cp_enable(adev, false); 3218 adev->gfx.rlc.funcs->stop(adev); 3219 gfx_v6_0_fini_pg(adev); 3220 3221 return 0; 3222 } 3223 3224 static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) 3225 { 3226 return gfx_v6_0_hw_fini(ip_block); 3227 } 3228 3229 static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) 3230 { 3231 return gfx_v6_0_hw_init(ip_block); 3232 } 3233 3234 static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 3235 { 3236 struct amdgpu_device *adev = ip_block->adev; 3237 3238 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3239 return false; 3240 else 3241 return true; 3242 } 3243 3244 static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3245 { 3246 unsigned i; 3247 struct amdgpu_device *adev = ip_block->adev; 3248 3249 for (i = 0; i < adev->usec_timeout; i++) { 3250 if (gfx_v6_0_is_idle(ip_block)) 3251 return 0; 3252 udelay(1); 3253 } 3254 return -ETIMEDOUT; 3255 } 3256 3257 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3258 enum amdgpu_interrupt_state state) 3259 { 3260 u32 cp_int_cntl; 3261 3262 switch (state) { 3263 case AMDGPU_IRQ_STATE_DISABLE: 3264 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3265 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3266 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3267 break; 3268 case AMDGPU_IRQ_STATE_ENABLE: 3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3270 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3271 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3272 break; 3273 default: 3274 break; 3275 } 3276 } 3277 3278 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3279 int ring, 3280 enum amdgpu_interrupt_state state) 3281 { 3282 u32 cp_int_cntl; 3283 switch (state){ 3284 case AMDGPU_IRQ_STATE_DISABLE: 3285 if (ring == 0) { 3286 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3287 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3288 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3289 break; 3290 } else { 3291 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3292 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3293 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3294 break; 3295 3296 } 3297 case AMDGPU_IRQ_STATE_ENABLE: 3298 if (ring == 0) { 3299 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3300 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3301 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3302 break; 3303 } else { 3304 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3305 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3306 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3307 break; 3308 3309 } 3310 3311 default: 3312 break; 3313 3314 } 3315 } 3316 3317 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3318 struct amdgpu_irq_src *src, 3319 unsigned type, 3320 enum amdgpu_interrupt_state state) 3321 { 3322 u32 cp_int_cntl; 3323 3324 switch (state) { 3325 case AMDGPU_IRQ_STATE_DISABLE: 3326 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3327 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3328 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3329 break; 3330 case AMDGPU_IRQ_STATE_ENABLE: 3331 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3332 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3333 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3334 break; 3335 default: 3336 break; 3337 } 3338 3339 return 0; 3340 } 3341 3342 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3343 struct amdgpu_irq_src *src, 3344 unsigned type, 3345 enum amdgpu_interrupt_state state) 3346 { 3347 u32 cp_int_cntl; 3348 3349 switch (state) { 3350 case AMDGPU_IRQ_STATE_DISABLE: 3351 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3352 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3353 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3354 break; 3355 case AMDGPU_IRQ_STATE_ENABLE: 3356 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3357 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3358 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3359 break; 3360 default: 3361 break; 3362 } 3363 3364 return 0; 3365 } 3366 3367 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3368 struct amdgpu_irq_src *src, 3369 unsigned type, 3370 enum amdgpu_interrupt_state state) 3371 { 3372 switch (type) { 3373 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3374 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3375 break; 3376 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3377 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3378 break; 3379 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3380 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3381 break; 3382 default: 3383 break; 3384 } 3385 return 0; 3386 } 3387 3388 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3389 struct amdgpu_irq_src *source, 3390 struct amdgpu_iv_entry *entry) 3391 { 3392 switch (entry->ring_id) { 3393 case 0: 3394 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3395 break; 3396 case 1: 3397 case 2: 3398 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3399 break; 3400 default: 3401 break; 3402 } 3403 return 0; 3404 } 3405 3406 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3407 struct amdgpu_iv_entry *entry) 3408 { 3409 struct amdgpu_ring *ring; 3410 3411 switch (entry->ring_id) { 3412 case 0: 3413 ring = &adev->gfx.gfx_ring[0]; 3414 break; 3415 case 1: 3416 case 2: 3417 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3418 break; 3419 default: 3420 return; 3421 } 3422 drm_sched_fault(&ring->sched); 3423 } 3424 3425 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3426 struct amdgpu_irq_src *source, 3427 struct amdgpu_iv_entry *entry) 3428 { 3429 DRM_ERROR("Illegal register access in command stream\n"); 3430 gfx_v6_0_fault(adev, entry); 3431 return 0; 3432 } 3433 3434 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3435 struct amdgpu_irq_src *source, 3436 struct amdgpu_iv_entry *entry) 3437 { 3438 DRM_ERROR("Illegal instruction in command stream\n"); 3439 gfx_v6_0_fault(adev, entry); 3440 return 0; 3441 } 3442 3443 static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3444 enum amd_clockgating_state state) 3445 { 3446 bool gate = false; 3447 struct amdgpu_device *adev = ip_block->adev; 3448 3449 if (state == AMD_CG_STATE_GATE) 3450 gate = true; 3451 3452 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3453 if (gate) { 3454 gfx_v6_0_enable_mgcg(adev, true); 3455 gfx_v6_0_enable_cgcg(adev, true); 3456 } else { 3457 gfx_v6_0_enable_cgcg(adev, false); 3458 gfx_v6_0_enable_mgcg(adev, false); 3459 } 3460 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3461 3462 return 0; 3463 } 3464 3465 static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3466 enum amd_powergating_state state) 3467 { 3468 bool gate = false; 3469 struct amdgpu_device *adev = ip_block->adev; 3470 3471 if (state == AMD_PG_STATE_GATE) 3472 gate = true; 3473 3474 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3475 AMD_PG_SUPPORT_GFX_SMG | 3476 AMD_PG_SUPPORT_GFX_DMG | 3477 AMD_PG_SUPPORT_CP | 3478 AMD_PG_SUPPORT_GDS | 3479 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3480 gfx_v6_0_update_gfx_pg(adev, gate); 3481 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3482 gfx_v6_0_enable_cp_pg(adev, gate); 3483 gfx_v6_0_enable_gds_pg(adev, gate); 3484 } 3485 } 3486 3487 return 0; 3488 } 3489 3490 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3491 { 3492 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3493 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3494 PACKET3_TC_ACTION_ENA | 3495 PACKET3_SH_KCACHE_ACTION_ENA | 3496 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3497 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3498 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3499 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3500 } 3501 3502 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3503 .name = "gfx_v6_0", 3504 .early_init = gfx_v6_0_early_init, 3505 .sw_init = gfx_v6_0_sw_init, 3506 .sw_fini = gfx_v6_0_sw_fini, 3507 .hw_init = gfx_v6_0_hw_init, 3508 .hw_fini = gfx_v6_0_hw_fini, 3509 .suspend = gfx_v6_0_suspend, 3510 .resume = gfx_v6_0_resume, 3511 .is_idle = gfx_v6_0_is_idle, 3512 .wait_for_idle = gfx_v6_0_wait_for_idle, 3513 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3514 .set_powergating_state = gfx_v6_0_set_powergating_state, 3515 }; 3516 3517 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3518 .type = AMDGPU_RING_TYPE_GFX, 3519 .align_mask = 0xff, 3520 .nop = 0x80000000, 3521 .support_64bit_ptrs = false, 3522 .get_rptr = gfx_v6_0_ring_get_rptr, 3523 .get_wptr = gfx_v6_0_ring_get_wptr, 3524 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3525 .emit_frame_size = 3526 5 + 5 + /* hdp flush / invalidate */ 3527 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3528 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3529 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3530 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3531 5, /* SURFACE_SYNC */ 3532 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3533 .emit_ib = gfx_v6_0_ring_emit_ib, 3534 .emit_fence = gfx_v6_0_ring_emit_fence, 3535 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3536 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3537 .test_ring = gfx_v6_0_ring_test_ring, 3538 .test_ib = gfx_v6_0_ring_test_ib, 3539 .insert_nop = amdgpu_ring_insert_nop, 3540 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3541 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3542 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3543 }; 3544 3545 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3546 .type = AMDGPU_RING_TYPE_COMPUTE, 3547 .align_mask = 0xff, 3548 .nop = 0x80000000, 3549 .get_rptr = gfx_v6_0_ring_get_rptr, 3550 .get_wptr = gfx_v6_0_ring_get_wptr, 3551 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3552 .emit_frame_size = 3553 5 + 5 + /* hdp flush / invalidate */ 3554 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3555 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3556 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3557 5, /* SURFACE_SYNC */ 3558 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3559 .emit_ib = gfx_v6_0_ring_emit_ib, 3560 .emit_fence = gfx_v6_0_ring_emit_fence, 3561 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3562 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3563 .test_ring = gfx_v6_0_ring_test_ring, 3564 .test_ib = gfx_v6_0_ring_test_ib, 3565 .insert_nop = amdgpu_ring_insert_nop, 3566 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3567 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3568 }; 3569 3570 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3571 { 3572 int i; 3573 3574 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3575 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3576 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3577 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3578 } 3579 3580 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3581 .set = gfx_v6_0_set_eop_interrupt_state, 3582 .process = gfx_v6_0_eop_irq, 3583 }; 3584 3585 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3586 .set = gfx_v6_0_set_priv_reg_fault_state, 3587 .process = gfx_v6_0_priv_reg_irq, 3588 }; 3589 3590 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3591 .set = gfx_v6_0_set_priv_inst_fault_state, 3592 .process = gfx_v6_0_priv_inst_irq, 3593 }; 3594 3595 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3596 { 3597 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3598 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3599 3600 adev->gfx.priv_reg_irq.num_types = 1; 3601 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3602 3603 adev->gfx.priv_inst_irq.num_types = 1; 3604 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3605 } 3606 3607 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3608 { 3609 int i, j, k, counter, active_cu_number = 0; 3610 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3611 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3612 unsigned disable_masks[4 * 2]; 3613 u32 ao_cu_num; 3614 3615 if (adev->flags & AMD_IS_APU) 3616 ao_cu_num = 2; 3617 else 3618 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3619 3620 memset(cu_info, 0, sizeof(*cu_info)); 3621 3622 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 3623 3624 mutex_lock(&adev->grbm_idx_mutex); 3625 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3626 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3627 mask = 1; 3628 ao_bitmap = 0; 3629 counter = 0; 3630 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3631 if (i < 4 && j < 2) 3632 gfx_v6_0_set_user_cu_inactive_bitmap( 3633 adev, disable_masks[i * 2 + j]); 3634 bitmap = gfx_v6_0_get_cu_enabled(adev); 3635 cu_info->bitmap[0][i][j] = bitmap; 3636 3637 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3638 if (bitmap & mask) { 3639 if (counter < ao_cu_num) 3640 ao_bitmap |= mask; 3641 counter ++; 3642 } 3643 mask <<= 1; 3644 } 3645 active_cu_number += counter; 3646 if (i < 2 && j < 2) 3647 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3648 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3649 } 3650 } 3651 3652 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3653 mutex_unlock(&adev->grbm_idx_mutex); 3654 3655 cu_info->number = active_cu_number; 3656 cu_info->ao_cu_mask = ao_cu_mask; 3657 } 3658 3659 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3660 { 3661 .type = AMD_IP_BLOCK_TYPE_GFX, 3662 .major = 6, 3663 .minor = 0, 3664 .rev = 0, 3665 .funcs = &gfx_v6_0_ip_funcs, 3666 }; 3667