1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "bif/bif_3_0_d.h" 32 #include "bif/bif_3_0_sh_mask.h" 33 #include "oss/oss_1_0_d.h" 34 #include "oss/oss_1_0_sh_mask.h" 35 #include "gca/gfx_6_0_d.h" 36 #include "gca/gfx_6_0_sh_mask.h" 37 #include "gmc/gmc_6_0_d.h" 38 #include "gmc/gmc_6_0_sh_mask.h" 39 #include "dce/dce_6_0_d.h" 40 #include "dce/dce_6_0_sh_mask.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "si_enums.h" 43 #include "si.h" 44 45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 48 49 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 50 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 51 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 52 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 53 54 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 56 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 57 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 58 59 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 60 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 61 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 63 64 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 66 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 71 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 72 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 73 74 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 75 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 76 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 77 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 78 79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 80 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 82 #define MICRO_TILE_MODE(x) ((x) << 0) 83 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 84 #define BANK_WIDTH(x) ((x) << 14) 85 #define BANK_HEIGHT(x) ((x) << 16) 86 #define MACRO_TILE_ASPECT(x) ((x) << 18) 87 #define NUM_BANKS(x) ((x) << 20) 88 89 static const u32 verde_rlc_save_restore_register_list[] = 90 { 91 (0x8000 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8040 << 16) | (0x98f4 >> 2), 94 0x00000000, 95 (0x8000 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8040 << 16) | (0xe80 >> 2), 98 0x00000000, 99 (0x8000 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8040 << 16) | (0x89bc >> 2), 102 0x00000000, 103 (0x8000 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x8040 << 16) | (0x8c1c >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0x98f0 >> 2), 108 0x00000000, 109 (0x9c00 << 16) | (0xe7c >> 2), 110 0x00000000, 111 (0x8000 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x8040 << 16) | (0x9148 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x9150 >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x897c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0x8d8c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0xac54 >> 2), 122 0X00000000, 123 0x3, 124 (0x9c00 << 16) | (0x98f8 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9910 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9914 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x9918 >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x991c >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9920 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9924 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x9928 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x992c >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9930 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9934 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x9938 >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x993c >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9940 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9944 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x9948 >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x994c >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9950 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9954 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x9958 >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x995c >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9960 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9964 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x9968 >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x996c >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9970 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9974 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x9978 >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x997c >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9980 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9984 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x9988 >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x998c >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c00 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c14 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c04 >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x8c08 >> 2), 197 0x00000000, 198 (0x8000 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8040 << 16) | (0x9b7c >> 2), 201 0x00000000, 202 (0x8000 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8040 << 16) | (0xe84 >> 2), 205 0x00000000, 206 (0x8000 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8040 << 16) | (0x89c0 >> 2), 209 0x00000000, 210 (0x8000 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8040 << 16) | (0x914c >> 2), 213 0x00000000, 214 (0x8000 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8040 << 16) | (0x8c20 >> 2), 217 0x00000000, 218 (0x8000 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x8040 << 16) | (0x9354 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9060 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9364 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x9100 >> 2), 227 0x00000000, 228 (0x9c00 << 16) | (0x913c >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e0 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e4 >> 2), 233 0x00000000, 234 (0x8000 << 16) | (0x90e8 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e0 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e4 >> 2), 239 0x00000000, 240 (0x8040 << 16) | (0x90e8 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8bcc >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x8b24 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x88c4 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8e50 >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8c0c >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e58 >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x8e5c >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x9508 >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x950c >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x9494 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac0c >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac10 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xac14 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xae00 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0xac08 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88d4 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88c8 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x88cc >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x89b0 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8b10 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x8a14 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9830 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9834 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9838 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x9a10 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9870 >> 2), 293 0x00000000, 294 (0x8000 << 16) | (0x9874 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9870 >> 2), 297 0x00000000, 298 (0x8001 << 16) | (0x9874 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9870 >> 2), 301 0x00000000, 302 (0x8040 << 16) | (0x9874 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9870 >> 2), 305 0x00000000, 306 (0x8041 << 16) | (0x9874 >> 2), 307 0x00000000, 308 0x00000000 309 }; 310 311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 312 { 313 const char *chip_name; 314 int err; 315 const struct gfx_firmware_header_v1_0 *cp_hdr; 316 const struct rlc_firmware_header_v1_0 *rlc_hdr; 317 318 DRM_DEBUG("\n"); 319 320 switch (adev->asic_type) { 321 case CHIP_TAHITI: 322 chip_name = "tahiti"; 323 break; 324 case CHIP_PITCAIRN: 325 chip_name = "pitcairn"; 326 break; 327 case CHIP_VERDE: 328 chip_name = "verde"; 329 break; 330 case CHIP_OLAND: 331 chip_name = "oland"; 332 break; 333 case CHIP_HAINAN: 334 chip_name = "hainan"; 335 break; 336 default: BUG(); 337 } 338 339 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 340 "amdgpu/%s_pfp.bin", chip_name); 341 if (err) 342 goto out; 343 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 344 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 345 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 346 347 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 348 "amdgpu/%s_me.bin", chip_name); 349 if (err) 350 goto out; 351 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 352 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 353 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 354 355 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 356 "amdgpu/%s_ce.bin", chip_name); 357 if (err) 358 goto out; 359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 360 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 361 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 362 363 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 364 "amdgpu/%s_rlc.bin", chip_name); 365 if (err) 366 goto out; 367 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 368 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 369 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 370 371 out: 372 if (err) { 373 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); 374 amdgpu_ucode_release(&adev->gfx.pfp_fw); 375 amdgpu_ucode_release(&adev->gfx.me_fw); 376 amdgpu_ucode_release(&adev->gfx.ce_fw); 377 amdgpu_ucode_release(&adev->gfx.rlc_fw); 378 } 379 return err; 380 } 381 382 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 383 { 384 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 385 u32 reg_offset, split_equal_to_row_size, *tilemode; 386 387 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 388 tilemode = adev->gfx.config.tile_mode_array; 389 390 switch (adev->gfx.config.mem_row_size_in_kb) { 391 case 1: 392 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 393 break; 394 case 2: 395 default: 396 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 397 break; 398 case 4: 399 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 400 break; 401 } 402 403 if (adev->asic_type == CHIP_VERDE) { 404 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 405 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 406 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 408 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 411 NUM_BANKS(ADDR_SURF_16_BANK); 412 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 413 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 414 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 419 NUM_BANKS(ADDR_SURF_16_BANK); 420 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 421 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 422 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 424 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 425 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 426 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 427 NUM_BANKS(ADDR_SURF_16_BANK); 428 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 430 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 434 NUM_BANKS(ADDR_SURF_8_BANK) | 435 TILE_SPLIT(split_equal_to_row_size); 436 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 437 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 438 PIPE_CONFIG(ADDR_SURF_P4_8x16); 439 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 446 NUM_BANKS(ADDR_SURF_4_BANK); 447 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 449 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 450 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 454 NUM_BANKS(ADDR_SURF_4_BANK); 455 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 456 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 457 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 458 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 459 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 460 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 461 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 462 NUM_BANKS(ADDR_SURF_2_BANK); 463 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 464 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 465 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 466 PIPE_CONFIG(ADDR_SURF_P4_8x16); 467 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 469 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 474 NUM_BANKS(ADDR_SURF_16_BANK); 475 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 477 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 481 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 482 NUM_BANKS(ADDR_SURF_16_BANK); 483 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 485 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 490 NUM_BANKS(ADDR_SURF_16_BANK); 491 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 492 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 493 PIPE_CONFIG(ADDR_SURF_P4_8x16); 494 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 496 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 501 NUM_BANKS(ADDR_SURF_16_BANK); 502 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 504 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 509 NUM_BANKS(ADDR_SURF_16_BANK); 510 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 511 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 514 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 517 NUM_BANKS(ADDR_SURF_16_BANK); 518 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 519 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 520 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 524 NUM_BANKS(ADDR_SURF_16_BANK) | 525 TILE_SPLIT(split_equal_to_row_size); 526 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 527 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 528 PIPE_CONFIG(ADDR_SURF_P4_8x16); 529 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 530 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 531 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 535 NUM_BANKS(ADDR_SURF_16_BANK) | 536 TILE_SPLIT(split_equal_to_row_size); 537 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 538 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 539 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 543 NUM_BANKS(ADDR_SURF_16_BANK) | 544 TILE_SPLIT(split_equal_to_row_size); 545 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 546 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 547 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 548 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 549 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 552 NUM_BANKS(ADDR_SURF_8_BANK); 553 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 554 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 555 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 557 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 560 NUM_BANKS(ADDR_SURF_8_BANK); 561 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 562 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 563 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 564 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 568 NUM_BANKS(ADDR_SURF_4_BANK); 569 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 570 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 571 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 572 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 576 NUM_BANKS(ADDR_SURF_4_BANK); 577 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 578 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 579 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 580 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 581 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 582 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 583 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 584 NUM_BANKS(ADDR_SURF_2_BANK); 585 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 586 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 587 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 588 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 589 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 592 NUM_BANKS(ADDR_SURF_2_BANK); 593 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 594 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 595 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 596 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 598 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 599 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 600 NUM_BANKS(ADDR_SURF_2_BANK); 601 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 603 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 608 NUM_BANKS(ADDR_SURF_2_BANK); 609 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 610 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 611 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 616 NUM_BANKS(ADDR_SURF_2_BANK); 617 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 618 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 619 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 620 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 621 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 622 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 623 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 624 NUM_BANKS(ADDR_SURF_2_BANK); 625 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 626 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 627 } else if (adev->asic_type == CHIP_OLAND) { 628 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 632 NUM_BANKS(ADDR_SURF_16_BANK) | 633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 636 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 638 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 640 NUM_BANKS(ADDR_SURF_16_BANK) | 641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 642 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 644 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 645 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 646 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 648 NUM_BANKS(ADDR_SURF_16_BANK) | 649 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 650 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 651 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 652 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 653 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 654 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 655 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 656 NUM_BANKS(ADDR_SURF_16_BANK) | 657 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 658 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 659 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 660 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 661 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 662 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 664 NUM_BANKS(ADDR_SURF_16_BANK) | 665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 668 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 669 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 670 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 671 TILE_SPLIT(split_equal_to_row_size) | 672 NUM_BANKS(ADDR_SURF_16_BANK) | 673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 676 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 677 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 678 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 679 TILE_SPLIT(split_equal_to_row_size) | 680 NUM_BANKS(ADDR_SURF_16_BANK) | 681 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 682 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 683 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 684 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 685 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 686 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 687 TILE_SPLIT(split_equal_to_row_size) | 688 NUM_BANKS(ADDR_SURF_16_BANK) | 689 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 690 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 691 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 692 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 693 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 694 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 696 NUM_BANKS(ADDR_SURF_16_BANK) | 697 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 698 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 699 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 700 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 701 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 702 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 704 NUM_BANKS(ADDR_SURF_16_BANK) | 705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 708 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 709 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 710 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 712 NUM_BANKS(ADDR_SURF_16_BANK) | 713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 716 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 717 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 718 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 720 NUM_BANKS(ADDR_SURF_16_BANK) | 721 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 722 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 723 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 724 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 725 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 726 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 727 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 728 NUM_BANKS(ADDR_SURF_16_BANK) | 729 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 730 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 731 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 732 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 733 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 734 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 736 NUM_BANKS(ADDR_SURF_16_BANK) | 737 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 738 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 739 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 740 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 741 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 742 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 744 NUM_BANKS(ADDR_SURF_16_BANK) | 745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 748 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 749 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 750 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 752 NUM_BANKS(ADDR_SURF_16_BANK) | 753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 756 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 758 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 760 NUM_BANKS(ADDR_SURF_16_BANK) | 761 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 762 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 763 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 764 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 765 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 766 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 767 TILE_SPLIT(split_equal_to_row_size) | 768 NUM_BANKS(ADDR_SURF_16_BANK) | 769 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 770 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 771 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 772 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 773 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 774 PIPE_CONFIG(ADDR_SURF_P4_8x16); 775 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 776 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 777 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 779 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 780 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 781 NUM_BANKS(ADDR_SURF_16_BANK) | 782 TILE_SPLIT(split_equal_to_row_size); 783 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 784 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 785 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 786 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 787 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 788 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 789 NUM_BANKS(ADDR_SURF_16_BANK) | 790 TILE_SPLIT(split_equal_to_row_size); 791 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 792 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 793 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 794 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 795 NUM_BANKS(ADDR_SURF_16_BANK) | 796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 799 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 800 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 801 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 802 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 803 NUM_BANKS(ADDR_SURF_16_BANK) | 804 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 805 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 806 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 807 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 808 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 809 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 810 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 811 NUM_BANKS(ADDR_SURF_16_BANK) | 812 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 815 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 816 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 817 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 819 NUM_BANKS(ADDR_SURF_16_BANK) | 820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 823 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 824 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 825 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 826 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 827 NUM_BANKS(ADDR_SURF_8_BANK) | 828 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 831 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 832 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 833 } else if (adev->asic_type == CHIP_HAINAN) { 834 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 836 PIPE_CONFIG(ADDR_SURF_P2) | 837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 838 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 841 NUM_BANKS(ADDR_SURF_16_BANK); 842 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 844 PIPE_CONFIG(ADDR_SURF_P2) | 845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 846 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 847 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 848 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 849 NUM_BANKS(ADDR_SURF_16_BANK); 850 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 851 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 852 PIPE_CONFIG(ADDR_SURF_P2) | 853 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 857 NUM_BANKS(ADDR_SURF_16_BANK); 858 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 859 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 860 PIPE_CONFIG(ADDR_SURF_P2) | 861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 864 NUM_BANKS(ADDR_SURF_8_BANK) | 865 TILE_SPLIT(split_equal_to_row_size); 866 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 867 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 868 PIPE_CONFIG(ADDR_SURF_P2); 869 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 871 PIPE_CONFIG(ADDR_SURF_P2) | 872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 876 NUM_BANKS(ADDR_SURF_8_BANK); 877 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 879 PIPE_CONFIG(ADDR_SURF_P2) | 880 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 884 NUM_BANKS(ADDR_SURF_8_BANK); 885 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 886 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 887 PIPE_CONFIG(ADDR_SURF_P2) | 888 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 889 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 890 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 891 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 892 NUM_BANKS(ADDR_SURF_4_BANK); 893 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 894 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 895 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 896 PIPE_CONFIG(ADDR_SURF_P2); 897 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 898 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 899 PIPE_CONFIG(ADDR_SURF_P2) | 900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 904 NUM_BANKS(ADDR_SURF_16_BANK); 905 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 906 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 907 PIPE_CONFIG(ADDR_SURF_P2) | 908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 909 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 910 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 911 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 912 NUM_BANKS(ADDR_SURF_16_BANK); 913 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 914 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 915 PIPE_CONFIG(ADDR_SURF_P2) | 916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 917 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 918 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 919 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 920 NUM_BANKS(ADDR_SURF_16_BANK); 921 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 922 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 923 PIPE_CONFIG(ADDR_SURF_P2); 924 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 926 PIPE_CONFIG(ADDR_SURF_P2) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 931 NUM_BANKS(ADDR_SURF_16_BANK); 932 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 PIPE_CONFIG(ADDR_SURF_P2) | 935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 939 NUM_BANKS(ADDR_SURF_16_BANK); 940 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 941 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 942 PIPE_CONFIG(ADDR_SURF_P2) | 943 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 947 NUM_BANKS(ADDR_SURF_16_BANK); 948 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 949 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 950 PIPE_CONFIG(ADDR_SURF_P2) | 951 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 952 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 953 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 954 NUM_BANKS(ADDR_SURF_16_BANK) | 955 TILE_SPLIT(split_equal_to_row_size); 956 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 957 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 958 PIPE_CONFIG(ADDR_SURF_P2); 959 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 960 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 961 PIPE_CONFIG(ADDR_SURF_P2) | 962 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 963 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 964 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 965 NUM_BANKS(ADDR_SURF_16_BANK) | 966 TILE_SPLIT(split_equal_to_row_size); 967 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 968 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 969 PIPE_CONFIG(ADDR_SURF_P2) | 970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 973 NUM_BANKS(ADDR_SURF_16_BANK) | 974 TILE_SPLIT(split_equal_to_row_size); 975 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 976 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 977 PIPE_CONFIG(ADDR_SURF_P2) | 978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 979 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 982 NUM_BANKS(ADDR_SURF_8_BANK); 983 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 984 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 985 PIPE_CONFIG(ADDR_SURF_P2) | 986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 987 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 988 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 989 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 990 NUM_BANKS(ADDR_SURF_8_BANK); 991 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 992 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 993 PIPE_CONFIG(ADDR_SURF_P2) | 994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 995 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 996 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 997 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 998 NUM_BANKS(ADDR_SURF_8_BANK); 999 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1000 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1001 PIPE_CONFIG(ADDR_SURF_P2) | 1002 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1003 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1004 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1005 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1006 NUM_BANKS(ADDR_SURF_8_BANK); 1007 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1008 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1009 PIPE_CONFIG(ADDR_SURF_P2) | 1010 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1011 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1012 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1013 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1014 NUM_BANKS(ADDR_SURF_4_BANK); 1015 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1016 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1017 PIPE_CONFIG(ADDR_SURF_P2) | 1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1019 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1022 NUM_BANKS(ADDR_SURF_4_BANK); 1023 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1025 PIPE_CONFIG(ADDR_SURF_P2) | 1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1030 NUM_BANKS(ADDR_SURF_4_BANK); 1031 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1032 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1033 PIPE_CONFIG(ADDR_SURF_P2) | 1034 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1035 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1038 NUM_BANKS(ADDR_SURF_4_BANK); 1039 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1040 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1041 PIPE_CONFIG(ADDR_SURF_P2) | 1042 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1043 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1044 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1045 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1046 NUM_BANKS(ADDR_SURF_4_BANK); 1047 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1048 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1049 PIPE_CONFIG(ADDR_SURF_P2) | 1050 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1051 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1052 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1053 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1054 NUM_BANKS(ADDR_SURF_4_BANK); 1055 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1056 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1057 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1058 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1065 NUM_BANKS(ADDR_SURF_16_BANK); 1066 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1073 NUM_BANKS(ADDR_SURF_16_BANK); 1074 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1075 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1081 NUM_BANKS(ADDR_SURF_16_BANK); 1082 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1083 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1084 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1085 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1086 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1087 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1088 NUM_BANKS(ADDR_SURF_4_BANK) | 1089 TILE_SPLIT(split_equal_to_row_size); 1090 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1091 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1092 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1093 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1100 NUM_BANKS(ADDR_SURF_2_BANK); 1101 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1108 NUM_BANKS(ADDR_SURF_2_BANK); 1109 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1110 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1111 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1112 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1113 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1114 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1115 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1116 NUM_BANKS(ADDR_SURF_2_BANK); 1117 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1118 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1119 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1120 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1121 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1128 NUM_BANKS(ADDR_SURF_16_BANK); 1129 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1130 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1131 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1136 NUM_BANKS(ADDR_SURF_16_BANK); 1137 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1138 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1141 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1142 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1144 NUM_BANKS(ADDR_SURF_16_BANK); 1145 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1146 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1147 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1148 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1155 NUM_BANKS(ADDR_SURF_16_BANK); 1156 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1163 NUM_BANKS(ADDR_SURF_16_BANK); 1164 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1165 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1171 NUM_BANKS(ADDR_SURF_16_BANK); 1172 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1173 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1174 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1175 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1178 NUM_BANKS(ADDR_SURF_16_BANK) | 1179 TILE_SPLIT(split_equal_to_row_size); 1180 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1181 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1182 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1183 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1184 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1189 NUM_BANKS(ADDR_SURF_16_BANK) | 1190 TILE_SPLIT(split_equal_to_row_size); 1191 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1192 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1194 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1197 NUM_BANKS(ADDR_SURF_16_BANK) | 1198 TILE_SPLIT(split_equal_to_row_size); 1199 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1200 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1203 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1206 NUM_BANKS(ADDR_SURF_4_BANK); 1207 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1208 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1209 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1211 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1214 NUM_BANKS(ADDR_SURF_4_BANK); 1215 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1216 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1217 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1222 NUM_BANKS(ADDR_SURF_2_BANK); 1223 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1224 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1225 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1230 NUM_BANKS(ADDR_SURF_2_BANK); 1231 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1232 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1233 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1235 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1238 NUM_BANKS(ADDR_SURF_2_BANK); 1239 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1240 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1241 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1242 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1243 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1246 NUM_BANKS(ADDR_SURF_2_BANK); 1247 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1248 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1249 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1251 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1254 NUM_BANKS(ADDR_SURF_2_BANK); 1255 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1256 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1257 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1258 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1262 NUM_BANKS(ADDR_SURF_2_BANK); 1263 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1264 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1265 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1270 NUM_BANKS(ADDR_SURF_2_BANK); 1271 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1272 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1273 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1274 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1275 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1276 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1277 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1278 NUM_BANKS(ADDR_SURF_2_BANK); 1279 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1280 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1281 } else { 1282 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1283 } 1284 } 1285 1286 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1287 u32 sh_num, u32 instance, int xcc_id) 1288 { 1289 u32 data; 1290 1291 if (instance == 0xffffffff) 1292 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1293 else 1294 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1295 1296 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1298 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1299 else if (se_num == 0xffffffff) 1300 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1301 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1302 else if (sh_num == 0xffffffff) 1303 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1304 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1305 else 1306 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1307 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1308 WREG32(mmGRBM_GFX_INDEX, data); 1309 } 1310 1311 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1312 { 1313 u32 data, mask; 1314 1315 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1316 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1317 1318 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1319 1320 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1321 adev->gfx.config.max_sh_per_se); 1322 1323 return ~data & mask; 1324 } 1325 1326 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1327 { 1328 switch (adev->asic_type) { 1329 case CHIP_TAHITI: 1330 case CHIP_PITCAIRN: 1331 *rconf |= 1332 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1333 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1334 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1335 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1336 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1337 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1338 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1339 break; 1340 case CHIP_VERDE: 1341 *rconf |= 1342 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1343 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1344 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1345 break; 1346 case CHIP_OLAND: 1347 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1348 break; 1349 case CHIP_HAINAN: 1350 *rconf |= 0x0; 1351 break; 1352 default: 1353 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1354 break; 1355 } 1356 } 1357 1358 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1359 u32 raster_config, unsigned rb_mask, 1360 unsigned num_rb) 1361 { 1362 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1363 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1364 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1365 unsigned rb_per_se = num_rb / num_se; 1366 unsigned se_mask[4]; 1367 unsigned se; 1368 1369 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1370 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1371 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1372 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1373 1374 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1375 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1376 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1377 1378 for (se = 0; se < num_se; se++) { 1379 unsigned raster_config_se = raster_config; 1380 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1381 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1382 int idx = (se / 2) * 2; 1383 1384 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1385 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1386 1387 if (!se_mask[idx]) 1388 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1389 else 1390 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1391 } 1392 1393 pkr0_mask &= rb_mask; 1394 pkr1_mask &= rb_mask; 1395 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1396 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1397 1398 if (!pkr0_mask) 1399 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1400 else 1401 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1402 } 1403 1404 if (rb_per_se >= 2) { 1405 unsigned rb0_mask = 1 << (se * rb_per_se); 1406 unsigned rb1_mask = rb0_mask << 1; 1407 1408 rb0_mask &= rb_mask; 1409 rb1_mask &= rb_mask; 1410 if (!rb0_mask || !rb1_mask) { 1411 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1412 1413 if (!rb0_mask) 1414 raster_config_se |= 1415 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1416 else 1417 raster_config_se |= 1418 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1419 } 1420 1421 if (rb_per_se > 2) { 1422 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1423 rb1_mask = rb0_mask << 1; 1424 rb0_mask &= rb_mask; 1425 rb1_mask &= rb_mask; 1426 if (!rb0_mask || !rb1_mask) { 1427 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1428 1429 if (!rb0_mask) 1430 raster_config_se |= 1431 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1432 else 1433 raster_config_se |= 1434 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1435 } 1436 } 1437 } 1438 1439 /* GRBM_GFX_INDEX has a different offset on SI */ 1440 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1441 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1442 } 1443 1444 /* GRBM_GFX_INDEX has a different offset on SI */ 1445 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1446 } 1447 1448 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1449 { 1450 int i, j; 1451 u32 data; 1452 u32 raster_config = 0; 1453 u32 active_rbs = 0; 1454 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1455 adev->gfx.config.max_sh_per_se; 1456 unsigned num_rb_pipes; 1457 1458 mutex_lock(&adev->grbm_idx_mutex); 1459 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1460 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1461 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1462 data = gfx_v6_0_get_rb_active_bitmap(adev); 1463 active_rbs |= data << 1464 ((i * adev->gfx.config.max_sh_per_se + j) * 1465 rb_bitmap_width_per_sh); 1466 } 1467 } 1468 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1469 1470 adev->gfx.config.backend_enable_mask = active_rbs; 1471 adev->gfx.config.num_rbs = hweight32(active_rbs); 1472 1473 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1474 adev->gfx.config.max_shader_engines, 16); 1475 1476 gfx_v6_0_raster_config(adev, &raster_config); 1477 1478 if (!adev->gfx.config.backend_enable_mask || 1479 adev->gfx.config.num_rbs >= num_rb_pipes) 1480 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1481 else 1482 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1483 adev->gfx.config.backend_enable_mask, 1484 num_rb_pipes); 1485 1486 /* cache the values for userspace */ 1487 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1488 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1489 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1490 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1491 RREG32(mmCC_RB_BACKEND_DISABLE); 1492 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1493 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1494 adev->gfx.config.rb_config[i][j].raster_config = 1495 RREG32(mmPA_SC_RASTER_CONFIG); 1496 } 1497 } 1498 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1499 mutex_unlock(&adev->grbm_idx_mutex); 1500 } 1501 1502 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1503 u32 bitmap) 1504 { 1505 u32 data; 1506 1507 if (!bitmap) 1508 return; 1509 1510 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1511 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1512 1513 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1514 } 1515 1516 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1517 { 1518 u32 data, mask; 1519 1520 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1521 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1522 1523 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1524 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1525 } 1526 1527 1528 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1529 { 1530 int i, j, k; 1531 u32 data, mask; 1532 u32 active_cu = 0; 1533 1534 mutex_lock(&adev->grbm_idx_mutex); 1535 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1536 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1537 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1538 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1539 active_cu = gfx_v6_0_get_cu_enabled(adev); 1540 1541 mask = 1; 1542 for (k = 0; k < 16; k++) { 1543 mask <<= k; 1544 if (active_cu & mask) { 1545 data &= ~mask; 1546 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1547 break; 1548 } 1549 } 1550 } 1551 } 1552 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1553 mutex_unlock(&adev->grbm_idx_mutex); 1554 } 1555 1556 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1557 { 1558 adev->gfx.config.double_offchip_lds_buf = 0; 1559 } 1560 1561 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1562 { 1563 u32 gb_addr_config = 0; 1564 u32 mc_arb_ramcfg; 1565 u32 sx_debug_1; 1566 u32 hdp_host_path_cntl; 1567 u32 tmp; 1568 1569 switch (adev->asic_type) { 1570 case CHIP_TAHITI: 1571 adev->gfx.config.max_shader_engines = 2; 1572 adev->gfx.config.max_tile_pipes = 12; 1573 adev->gfx.config.max_cu_per_sh = 8; 1574 adev->gfx.config.max_sh_per_se = 2; 1575 adev->gfx.config.max_backends_per_se = 4; 1576 adev->gfx.config.max_texture_channel_caches = 12; 1577 adev->gfx.config.max_gprs = 256; 1578 adev->gfx.config.max_gs_threads = 32; 1579 adev->gfx.config.max_hw_contexts = 8; 1580 1581 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1582 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1583 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1584 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1585 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1586 break; 1587 case CHIP_PITCAIRN: 1588 adev->gfx.config.max_shader_engines = 2; 1589 adev->gfx.config.max_tile_pipes = 8; 1590 adev->gfx.config.max_cu_per_sh = 5; 1591 adev->gfx.config.max_sh_per_se = 2; 1592 adev->gfx.config.max_backends_per_se = 4; 1593 adev->gfx.config.max_texture_channel_caches = 8; 1594 adev->gfx.config.max_gprs = 256; 1595 adev->gfx.config.max_gs_threads = 32; 1596 adev->gfx.config.max_hw_contexts = 8; 1597 1598 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1599 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1600 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1601 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1602 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1603 break; 1604 case CHIP_VERDE: 1605 adev->gfx.config.max_shader_engines = 1; 1606 adev->gfx.config.max_tile_pipes = 4; 1607 adev->gfx.config.max_cu_per_sh = 5; 1608 adev->gfx.config.max_sh_per_se = 2; 1609 adev->gfx.config.max_backends_per_se = 4; 1610 adev->gfx.config.max_texture_channel_caches = 4; 1611 adev->gfx.config.max_gprs = 256; 1612 adev->gfx.config.max_gs_threads = 32; 1613 adev->gfx.config.max_hw_contexts = 8; 1614 1615 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1616 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1617 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1618 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1619 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1620 break; 1621 case CHIP_OLAND: 1622 adev->gfx.config.max_shader_engines = 1; 1623 adev->gfx.config.max_tile_pipes = 4; 1624 adev->gfx.config.max_cu_per_sh = 6; 1625 adev->gfx.config.max_sh_per_se = 1; 1626 adev->gfx.config.max_backends_per_se = 2; 1627 adev->gfx.config.max_texture_channel_caches = 4; 1628 adev->gfx.config.max_gprs = 256; 1629 adev->gfx.config.max_gs_threads = 16; 1630 adev->gfx.config.max_hw_contexts = 8; 1631 1632 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1633 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1634 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1635 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1636 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1637 break; 1638 case CHIP_HAINAN: 1639 adev->gfx.config.max_shader_engines = 1; 1640 adev->gfx.config.max_tile_pipes = 4; 1641 adev->gfx.config.max_cu_per_sh = 5; 1642 adev->gfx.config.max_sh_per_se = 1; 1643 adev->gfx.config.max_backends_per_se = 1; 1644 adev->gfx.config.max_texture_channel_caches = 2; 1645 adev->gfx.config.max_gprs = 256; 1646 adev->gfx.config.max_gs_threads = 16; 1647 adev->gfx.config.max_hw_contexts = 8; 1648 1649 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1650 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1651 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1652 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1653 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1654 break; 1655 default: 1656 BUG(); 1657 break; 1658 } 1659 1660 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1661 WREG32(mmSRBM_INT_CNTL, 1); 1662 WREG32(mmSRBM_INT_ACK, 1); 1663 1664 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1665 1666 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1667 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1668 1669 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1670 adev->gfx.config.mem_max_burst_length_bytes = 256; 1671 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1672 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1673 if (adev->gfx.config.mem_row_size_in_kb > 4) 1674 adev->gfx.config.mem_row_size_in_kb = 4; 1675 adev->gfx.config.shader_engine_tile_size = 32; 1676 adev->gfx.config.num_gpus = 1; 1677 adev->gfx.config.multi_gpu_tile_size = 64; 1678 1679 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1680 switch (adev->gfx.config.mem_row_size_in_kb) { 1681 case 1: 1682 default: 1683 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1684 break; 1685 case 2: 1686 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1687 break; 1688 case 4: 1689 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1690 break; 1691 } 1692 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1693 if (adev->gfx.config.max_shader_engines == 2) 1694 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1695 adev->gfx.config.gb_addr_config = gb_addr_config; 1696 1697 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1698 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1699 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1700 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1701 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1702 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1703 1704 #if 0 1705 if (adev->has_uvd) { 1706 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1707 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1708 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1709 } 1710 #endif 1711 gfx_v6_0_tiling_mode_table_init(adev); 1712 1713 gfx_v6_0_setup_rb(adev); 1714 1715 gfx_v6_0_setup_spi(adev); 1716 1717 gfx_v6_0_get_cu_info(adev); 1718 gfx_v6_0_config_init(adev); 1719 1720 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1721 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1722 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1723 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1724 1725 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1726 WREG32(mmSX_DEBUG_1, sx_debug_1); 1727 1728 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1729 1730 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1731 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1732 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1733 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1734 1735 WREG32(mmVGT_NUM_INSTANCES, 1); 1736 WREG32(mmCP_PERFMON_CNTL, 0); 1737 WREG32(mmSQ_CONFIG, 0); 1738 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1739 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1740 1741 WREG32(mmVGT_CACHE_INVALIDATION, 1742 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1743 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1744 1745 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1746 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1747 1748 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1749 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1750 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1751 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1752 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1753 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1754 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1755 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1756 1757 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1758 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1759 1760 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1761 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1762 1763 udelay(50); 1764 } 1765 1766 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1767 { 1768 struct amdgpu_device *adev = ring->adev; 1769 uint32_t tmp = 0; 1770 unsigned i; 1771 int r; 1772 1773 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1774 1775 r = amdgpu_ring_alloc(ring, 3); 1776 if (r) 1777 return r; 1778 1779 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1780 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); 1781 amdgpu_ring_write(ring, 0xDEADBEEF); 1782 amdgpu_ring_commit(ring); 1783 1784 for (i = 0; i < adev->usec_timeout; i++) { 1785 tmp = RREG32(mmSCRATCH_REG0); 1786 if (tmp == 0xDEADBEEF) 1787 break; 1788 udelay(1); 1789 } 1790 1791 if (i >= adev->usec_timeout) 1792 r = -ETIMEDOUT; 1793 return r; 1794 } 1795 1796 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1797 { 1798 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1799 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1800 EVENT_INDEX(0)); 1801 } 1802 1803 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1804 u64 seq, unsigned flags) 1805 { 1806 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1807 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1808 /* flush read cache over gart */ 1809 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1810 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1811 amdgpu_ring_write(ring, 0); 1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1813 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1814 PACKET3_TC_ACTION_ENA | 1815 PACKET3_SH_KCACHE_ACTION_ENA | 1816 PACKET3_SH_ICACHE_ACTION_ENA); 1817 amdgpu_ring_write(ring, 0xFFFFFFFF); 1818 amdgpu_ring_write(ring, 0); 1819 amdgpu_ring_write(ring, 10); /* poll interval */ 1820 /* EVENT_WRITE_EOP - flush caches, send int */ 1821 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1822 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1823 amdgpu_ring_write(ring, addr & 0xfffffffc); 1824 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1825 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1826 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1827 amdgpu_ring_write(ring, lower_32_bits(seq)); 1828 amdgpu_ring_write(ring, upper_32_bits(seq)); 1829 } 1830 1831 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1832 struct amdgpu_job *job, 1833 struct amdgpu_ib *ib, 1834 uint32_t flags) 1835 { 1836 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1837 u32 header, control = 0; 1838 1839 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1840 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1841 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1842 amdgpu_ring_write(ring, 0); 1843 } 1844 1845 if (ib->flags & AMDGPU_IB_FLAG_CE) 1846 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1847 else 1848 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1849 1850 control |= ib->length_dw | (vmid << 24); 1851 1852 amdgpu_ring_write(ring, header); 1853 amdgpu_ring_write(ring, 1854 #ifdef __BIG_ENDIAN 1855 (2 << 0) | 1856 #endif 1857 (ib->gpu_addr & 0xFFFFFFFC)); 1858 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1859 amdgpu_ring_write(ring, control); 1860 } 1861 1862 /** 1863 * gfx_v6_0_ring_test_ib - basic ring IB test 1864 * 1865 * @ring: amdgpu_ring structure holding ring information 1866 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1867 * 1868 * Allocate an IB and execute it on the gfx ring (SI). 1869 * Provides a basic gfx ring test to verify that IBs are working. 1870 * Returns 0 on success, error on failure. 1871 */ 1872 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1873 { 1874 struct amdgpu_device *adev = ring->adev; 1875 struct dma_fence *f = NULL; 1876 struct amdgpu_ib ib; 1877 uint32_t tmp = 0; 1878 long r; 1879 1880 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1881 memset(&ib, 0, sizeof(ib)); 1882 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1883 if (r) 1884 return r; 1885 1886 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1887 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; 1888 ib.ptr[2] = 0xDEADBEEF; 1889 ib.length_dw = 3; 1890 1891 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1892 if (r) 1893 goto error; 1894 1895 r = dma_fence_wait_timeout(f, false, timeout); 1896 if (r == 0) { 1897 r = -ETIMEDOUT; 1898 goto error; 1899 } else if (r < 0) { 1900 goto error; 1901 } 1902 tmp = RREG32(mmSCRATCH_REG0); 1903 if (tmp == 0xDEADBEEF) 1904 r = 0; 1905 else 1906 r = -EINVAL; 1907 1908 error: 1909 amdgpu_ib_free(adev, &ib, NULL); 1910 dma_fence_put(f); 1911 return r; 1912 } 1913 1914 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1915 { 1916 if (enable) { 1917 WREG32(mmCP_ME_CNTL, 0); 1918 } else { 1919 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1920 CP_ME_CNTL__PFP_HALT_MASK | 1921 CP_ME_CNTL__CE_HALT_MASK)); 1922 WREG32(mmSCRATCH_UMSK, 0); 1923 } 1924 udelay(50); 1925 } 1926 1927 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1928 { 1929 unsigned i; 1930 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1931 const struct gfx_firmware_header_v1_0 *ce_hdr; 1932 const struct gfx_firmware_header_v1_0 *me_hdr; 1933 const __le32 *fw_data; 1934 u32 fw_size; 1935 1936 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1937 return -EINVAL; 1938 1939 gfx_v6_0_cp_gfx_enable(adev, false); 1940 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1941 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1942 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1943 1944 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1945 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1946 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1947 1948 /* PFP */ 1949 fw_data = (const __le32 *) 1950 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1951 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1952 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1953 for (i = 0; i < fw_size; i++) 1954 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1955 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1956 1957 /* CE */ 1958 fw_data = (const __le32 *) 1959 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1960 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1961 WREG32(mmCP_CE_UCODE_ADDR, 0); 1962 for (i = 0; i < fw_size; i++) 1963 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1964 WREG32(mmCP_CE_UCODE_ADDR, 0); 1965 1966 /* ME */ 1967 fw_data = (const __be32 *) 1968 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1969 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1970 WREG32(mmCP_ME_RAM_WADDR, 0); 1971 for (i = 0; i < fw_size; i++) 1972 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1973 WREG32(mmCP_ME_RAM_WADDR, 0); 1974 1975 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1976 WREG32(mmCP_CE_UCODE_ADDR, 0); 1977 WREG32(mmCP_ME_RAM_WADDR, 0); 1978 WREG32(mmCP_ME_RAM_RADDR, 0); 1979 return 0; 1980 } 1981 1982 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 1983 { 1984 const struct cs_section_def *sect = NULL; 1985 const struct cs_extent_def *ext = NULL; 1986 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1987 int r, i; 1988 1989 r = amdgpu_ring_alloc(ring, 7 + 4); 1990 if (r) { 1991 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1992 return r; 1993 } 1994 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1995 amdgpu_ring_write(ring, 0x1); 1996 amdgpu_ring_write(ring, 0x0); 1997 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 1998 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1999 amdgpu_ring_write(ring, 0); 2000 amdgpu_ring_write(ring, 0); 2001 2002 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2003 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2004 amdgpu_ring_write(ring, 0xc000); 2005 amdgpu_ring_write(ring, 0xe000); 2006 amdgpu_ring_commit(ring); 2007 2008 gfx_v6_0_cp_gfx_enable(adev, true); 2009 2010 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2011 if (r) { 2012 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2013 return r; 2014 } 2015 2016 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2017 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2018 2019 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2020 for (ext = sect->section; ext->extent != NULL; ++ext) { 2021 if (sect->id == SECT_CONTEXT) { 2022 amdgpu_ring_write(ring, 2023 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2024 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2025 for (i = 0; i < ext->reg_count; i++) 2026 amdgpu_ring_write(ring, ext->extent[i]); 2027 } 2028 } 2029 } 2030 2031 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2032 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2033 2034 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2035 amdgpu_ring_write(ring, 0); 2036 2037 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2038 amdgpu_ring_write(ring, 0x00000316); 2039 amdgpu_ring_write(ring, 0x0000000e); 2040 amdgpu_ring_write(ring, 0x00000010); 2041 2042 amdgpu_ring_commit(ring); 2043 2044 return 0; 2045 } 2046 2047 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2048 { 2049 struct amdgpu_ring *ring; 2050 u32 tmp; 2051 u32 rb_bufsz; 2052 int r; 2053 u64 rptr_addr; 2054 2055 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2056 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2057 2058 /* Set the write pointer delay */ 2059 WREG32(mmCP_RB_WPTR_DELAY, 0); 2060 2061 WREG32(mmCP_DEBUG, 0); 2062 WREG32(mmSCRATCH_ADDR, 0); 2063 2064 /* ring 0 - compute and gfx */ 2065 /* Set ring buffer size */ 2066 ring = &adev->gfx.gfx_ring[0]; 2067 rb_bufsz = order_base_2(ring->ring_size / 8); 2068 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2069 2070 #ifdef __BIG_ENDIAN 2071 tmp |= BUF_SWAP_32BIT; 2072 #endif 2073 WREG32(mmCP_RB0_CNTL, tmp); 2074 2075 /* Initialize the ring buffer's read and write pointers */ 2076 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2077 ring->wptr = 0; 2078 WREG32(mmCP_RB0_WPTR, ring->wptr); 2079 2080 /* set the wb address whether it's enabled or not */ 2081 rptr_addr = ring->rptr_gpu_addr; 2082 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2083 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2084 2085 WREG32(mmSCRATCH_UMSK, 0); 2086 2087 mdelay(1); 2088 WREG32(mmCP_RB0_CNTL, tmp); 2089 2090 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2091 2092 /* start the rings */ 2093 gfx_v6_0_cp_gfx_start(adev); 2094 r = amdgpu_ring_test_helper(ring); 2095 if (r) 2096 return r; 2097 2098 return 0; 2099 } 2100 2101 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2102 { 2103 return *ring->rptr_cpu_addr; 2104 } 2105 2106 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2107 { 2108 struct amdgpu_device *adev = ring->adev; 2109 2110 if (ring == &adev->gfx.gfx_ring[0]) 2111 return RREG32(mmCP_RB0_WPTR); 2112 else if (ring == &adev->gfx.compute_ring[0]) 2113 return RREG32(mmCP_RB1_WPTR); 2114 else if (ring == &adev->gfx.compute_ring[1]) 2115 return RREG32(mmCP_RB2_WPTR); 2116 else 2117 BUG(); 2118 } 2119 2120 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2121 { 2122 struct amdgpu_device *adev = ring->adev; 2123 2124 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2125 (void)RREG32(mmCP_RB0_WPTR); 2126 } 2127 2128 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2129 { 2130 struct amdgpu_device *adev = ring->adev; 2131 2132 if (ring == &adev->gfx.compute_ring[0]) { 2133 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2134 (void)RREG32(mmCP_RB1_WPTR); 2135 } else if (ring == &adev->gfx.compute_ring[1]) { 2136 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2137 (void)RREG32(mmCP_RB2_WPTR); 2138 } else { 2139 BUG(); 2140 } 2141 2142 } 2143 2144 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2145 { 2146 struct amdgpu_ring *ring; 2147 u32 tmp; 2148 u32 rb_bufsz; 2149 int i, r; 2150 u64 rptr_addr; 2151 2152 /* ring1 - compute only */ 2153 /* Set ring buffer size */ 2154 2155 ring = &adev->gfx.compute_ring[0]; 2156 rb_bufsz = order_base_2(ring->ring_size / 8); 2157 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2158 #ifdef __BIG_ENDIAN 2159 tmp |= BUF_SWAP_32BIT; 2160 #endif 2161 WREG32(mmCP_RB1_CNTL, tmp); 2162 2163 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2164 ring->wptr = 0; 2165 WREG32(mmCP_RB1_WPTR, ring->wptr); 2166 2167 rptr_addr = ring->rptr_gpu_addr; 2168 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2169 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2170 2171 mdelay(1); 2172 WREG32(mmCP_RB1_CNTL, tmp); 2173 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2174 2175 ring = &adev->gfx.compute_ring[1]; 2176 rb_bufsz = order_base_2(ring->ring_size / 8); 2177 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2178 #ifdef __BIG_ENDIAN 2179 tmp |= BUF_SWAP_32BIT; 2180 #endif 2181 WREG32(mmCP_RB2_CNTL, tmp); 2182 2183 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2184 ring->wptr = 0; 2185 WREG32(mmCP_RB2_WPTR, ring->wptr); 2186 rptr_addr = ring->rptr_gpu_addr; 2187 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2188 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2189 2190 mdelay(1); 2191 WREG32(mmCP_RB2_CNTL, tmp); 2192 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2193 2194 2195 for (i = 0; i < 2; i++) { 2196 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2197 if (r) 2198 return r; 2199 } 2200 2201 return 0; 2202 } 2203 2204 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2205 { 2206 gfx_v6_0_cp_gfx_enable(adev, enable); 2207 } 2208 2209 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2210 { 2211 return gfx_v6_0_cp_gfx_load_microcode(adev); 2212 } 2213 2214 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2215 bool enable) 2216 { 2217 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2218 u32 mask; 2219 int i; 2220 2221 if (enable) 2222 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2223 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2224 else 2225 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2226 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2227 WREG32(mmCP_INT_CNTL_RING0, tmp); 2228 2229 if (!enable) { 2230 /* read a gfx register */ 2231 tmp = RREG32(mmDB_DEPTH_INFO); 2232 2233 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2234 for (i = 0; i < adev->usec_timeout; i++) { 2235 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2236 break; 2237 udelay(1); 2238 } 2239 } 2240 } 2241 2242 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2243 { 2244 int r; 2245 2246 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2247 2248 r = gfx_v6_0_cp_load_microcode(adev); 2249 if (r) 2250 return r; 2251 2252 r = gfx_v6_0_cp_gfx_resume(adev); 2253 if (r) 2254 return r; 2255 r = gfx_v6_0_cp_compute_resume(adev); 2256 if (r) 2257 return r; 2258 2259 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2260 2261 return 0; 2262 } 2263 2264 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2265 { 2266 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2267 uint32_t seq = ring->fence_drv.sync_seq; 2268 uint64_t addr = ring->fence_drv.gpu_addr; 2269 2270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2271 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2272 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2273 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2274 amdgpu_ring_write(ring, addr & 0xfffffffc); 2275 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2276 amdgpu_ring_write(ring, seq); 2277 amdgpu_ring_write(ring, 0xffffffff); 2278 amdgpu_ring_write(ring, 4); /* poll interval */ 2279 2280 if (usepfp) { 2281 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2282 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2283 amdgpu_ring_write(ring, 0); 2284 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2285 amdgpu_ring_write(ring, 0); 2286 } 2287 } 2288 2289 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2290 unsigned vmid, uint64_t pd_addr) 2291 { 2292 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2293 2294 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2295 2296 /* wait for the invalidate to complete */ 2297 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2298 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2299 WAIT_REG_MEM_ENGINE(0))); /* me */ 2300 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2301 amdgpu_ring_write(ring, 0); 2302 amdgpu_ring_write(ring, 0); /* ref */ 2303 amdgpu_ring_write(ring, 0); /* mask */ 2304 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2305 2306 if (usepfp) { 2307 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2308 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2309 amdgpu_ring_write(ring, 0x0); 2310 2311 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2312 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2313 amdgpu_ring_write(ring, 0); 2314 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2315 amdgpu_ring_write(ring, 0); 2316 } 2317 } 2318 2319 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2320 uint32_t reg, uint32_t val) 2321 { 2322 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2323 2324 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2325 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2326 WRITE_DATA_DST_SEL(0))); 2327 amdgpu_ring_write(ring, reg); 2328 amdgpu_ring_write(ring, 0); 2329 amdgpu_ring_write(ring, val); 2330 } 2331 2332 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2333 { 2334 const u32 *src_ptr; 2335 volatile u32 *dst_ptr; 2336 u32 dws; 2337 u64 reg_list_mc_addr; 2338 const struct cs_section_def *cs_data; 2339 int r; 2340 2341 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2342 adev->gfx.rlc.reg_list_size = 2343 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2344 2345 adev->gfx.rlc.cs_data = si_cs_data; 2346 src_ptr = adev->gfx.rlc.reg_list; 2347 dws = adev->gfx.rlc.reg_list_size; 2348 cs_data = adev->gfx.rlc.cs_data; 2349 2350 if (src_ptr) { 2351 /* init save restore block */ 2352 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2353 if (r) 2354 return r; 2355 } 2356 2357 if (cs_data) { 2358 /* clear state block */ 2359 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2360 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2361 2362 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2363 AMDGPU_GEM_DOMAIN_VRAM | 2364 AMDGPU_GEM_DOMAIN_GTT, 2365 &adev->gfx.rlc.clear_state_obj, 2366 &adev->gfx.rlc.clear_state_gpu_addr, 2367 (void **)&adev->gfx.rlc.cs_ptr); 2368 if (r) { 2369 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2370 amdgpu_gfx_rlc_fini(adev); 2371 return r; 2372 } 2373 2374 /* set up the cs buffer */ 2375 dst_ptr = adev->gfx.rlc.cs_ptr; 2376 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2377 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2378 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2379 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2380 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2381 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2382 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2383 } 2384 2385 return 0; 2386 } 2387 2388 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2389 { 2390 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2391 2392 if (!enable) { 2393 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2394 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2395 } 2396 } 2397 2398 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2399 { 2400 int i; 2401 2402 for (i = 0; i < adev->usec_timeout; i++) { 2403 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2404 break; 2405 udelay(1); 2406 } 2407 2408 for (i = 0; i < adev->usec_timeout; i++) { 2409 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2410 break; 2411 udelay(1); 2412 } 2413 } 2414 2415 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2416 { 2417 u32 tmp; 2418 2419 tmp = RREG32(mmRLC_CNTL); 2420 if (tmp != rlc) 2421 WREG32(mmRLC_CNTL, rlc); 2422 } 2423 2424 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2425 { 2426 u32 data, orig; 2427 2428 orig = data = RREG32(mmRLC_CNTL); 2429 2430 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2431 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2432 WREG32(mmRLC_CNTL, data); 2433 2434 gfx_v6_0_wait_for_rlc_serdes(adev); 2435 } 2436 2437 return orig; 2438 } 2439 2440 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2441 { 2442 WREG32(mmRLC_CNTL, 0); 2443 2444 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2445 gfx_v6_0_wait_for_rlc_serdes(adev); 2446 } 2447 2448 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2449 { 2450 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2451 2452 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2453 2454 udelay(50); 2455 } 2456 2457 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2458 { 2459 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2460 udelay(50); 2461 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2462 udelay(50); 2463 } 2464 2465 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2466 { 2467 u32 tmp; 2468 2469 /* Enable LBPW only for DDR3 */ 2470 tmp = RREG32(mmMC_SEQ_MISC0); 2471 if ((tmp & 0xF0000000) == 0xB0000000) 2472 return true; 2473 return false; 2474 } 2475 2476 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2477 { 2478 } 2479 2480 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2481 { 2482 u32 i; 2483 const struct rlc_firmware_header_v1_0 *hdr; 2484 const __le32 *fw_data; 2485 u32 fw_size; 2486 2487 2488 if (!adev->gfx.rlc_fw) 2489 return -EINVAL; 2490 2491 adev->gfx.rlc.funcs->stop(adev); 2492 adev->gfx.rlc.funcs->reset(adev); 2493 gfx_v6_0_init_pg(adev); 2494 gfx_v6_0_init_cg(adev); 2495 2496 WREG32(mmRLC_RL_BASE, 0); 2497 WREG32(mmRLC_RL_SIZE, 0); 2498 WREG32(mmRLC_LB_CNTL, 0); 2499 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2500 WREG32(mmRLC_LB_CNTR_INIT, 0); 2501 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2502 2503 WREG32(mmRLC_MC_CNTL, 0); 2504 WREG32(mmRLC_UCODE_CNTL, 0); 2505 2506 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2507 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2508 fw_data = (const __le32 *) 2509 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2510 2511 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2512 2513 for (i = 0; i < fw_size; i++) { 2514 WREG32(mmRLC_UCODE_ADDR, i); 2515 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2516 } 2517 WREG32(mmRLC_UCODE_ADDR, 0); 2518 2519 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2520 adev->gfx.rlc.funcs->start(adev); 2521 2522 return 0; 2523 } 2524 2525 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2526 { 2527 u32 data, orig, tmp; 2528 2529 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2530 2531 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2532 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2533 2534 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2535 2536 tmp = gfx_v6_0_halt_rlc(adev); 2537 2538 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2539 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2540 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2541 2542 gfx_v6_0_wait_for_rlc_serdes(adev); 2543 gfx_v6_0_update_rlc(adev, tmp); 2544 2545 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2546 2547 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2548 } else { 2549 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2550 2551 RREG32(mmCB_CGTT_SCLK_CTRL); 2552 RREG32(mmCB_CGTT_SCLK_CTRL); 2553 RREG32(mmCB_CGTT_SCLK_CTRL); 2554 RREG32(mmCB_CGTT_SCLK_CTRL); 2555 2556 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2557 } 2558 2559 if (orig != data) 2560 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2561 2562 } 2563 2564 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2565 { 2566 2567 u32 data, orig, tmp = 0; 2568 2569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2570 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2571 data = 0x96940200; 2572 if (orig != data) 2573 WREG32(mmCGTS_SM_CTRL_REG, data); 2574 2575 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2576 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2577 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2578 if (orig != data) 2579 WREG32(mmCP_MEM_SLP_CNTL, data); 2580 } 2581 2582 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2583 data &= 0xffffffc0; 2584 if (orig != data) 2585 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2586 2587 tmp = gfx_v6_0_halt_rlc(adev); 2588 2589 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2590 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2591 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2592 2593 gfx_v6_0_update_rlc(adev, tmp); 2594 } else { 2595 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2596 data |= 0x00000003; 2597 if (orig != data) 2598 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2599 2600 data = RREG32(mmCP_MEM_SLP_CNTL); 2601 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2602 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2603 WREG32(mmCP_MEM_SLP_CNTL, data); 2604 } 2605 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2606 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2607 if (orig != data) 2608 WREG32(mmCGTS_SM_CTRL_REG, data); 2609 2610 tmp = gfx_v6_0_halt_rlc(adev); 2611 2612 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2613 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2614 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2615 2616 gfx_v6_0_update_rlc(adev, tmp); 2617 } 2618 } 2619 /* 2620 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2621 bool enable) 2622 { 2623 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2624 if (enable) { 2625 gfx_v6_0_enable_mgcg(adev, true); 2626 gfx_v6_0_enable_cgcg(adev, true); 2627 } else { 2628 gfx_v6_0_enable_cgcg(adev, false); 2629 gfx_v6_0_enable_mgcg(adev, false); 2630 } 2631 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2632 } 2633 */ 2634 2635 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2636 bool enable) 2637 { 2638 } 2639 2640 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2641 bool enable) 2642 { 2643 } 2644 2645 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2646 { 2647 u32 data, orig; 2648 2649 orig = data = RREG32(mmRLC_PG_CNTL); 2650 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2651 data &= ~0x8000; 2652 else 2653 data |= 0x8000; 2654 if (orig != data) 2655 WREG32(mmRLC_PG_CNTL, data); 2656 } 2657 2658 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2659 { 2660 } 2661 /* 2662 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2663 { 2664 const __le32 *fw_data; 2665 volatile u32 *dst_ptr; 2666 int me, i, max_me = 4; 2667 u32 bo_offset = 0; 2668 u32 table_offset, table_size; 2669 2670 if (adev->asic_type == CHIP_KAVERI) 2671 max_me = 5; 2672 2673 if (adev->gfx.rlc.cp_table_ptr == NULL) 2674 return; 2675 2676 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2677 for (me = 0; me < max_me; me++) { 2678 if (me == 0) { 2679 const struct gfx_firmware_header_v1_0 *hdr = 2680 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2681 fw_data = (const __le32 *) 2682 (adev->gfx.ce_fw->data + 2683 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2684 table_offset = le32_to_cpu(hdr->jt_offset); 2685 table_size = le32_to_cpu(hdr->jt_size); 2686 } else if (me == 1) { 2687 const struct gfx_firmware_header_v1_0 *hdr = 2688 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2689 fw_data = (const __le32 *) 2690 (adev->gfx.pfp_fw->data + 2691 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2692 table_offset = le32_to_cpu(hdr->jt_offset); 2693 table_size = le32_to_cpu(hdr->jt_size); 2694 } else if (me == 2) { 2695 const struct gfx_firmware_header_v1_0 *hdr = 2696 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2697 fw_data = (const __le32 *) 2698 (adev->gfx.me_fw->data + 2699 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2700 table_offset = le32_to_cpu(hdr->jt_offset); 2701 table_size = le32_to_cpu(hdr->jt_size); 2702 } else if (me == 3) { 2703 const struct gfx_firmware_header_v1_0 *hdr = 2704 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2705 fw_data = (const __le32 *) 2706 (adev->gfx.mec_fw->data + 2707 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2708 table_offset = le32_to_cpu(hdr->jt_offset); 2709 table_size = le32_to_cpu(hdr->jt_size); 2710 } else { 2711 const struct gfx_firmware_header_v1_0 *hdr = 2712 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2713 fw_data = (const __le32 *) 2714 (adev->gfx.mec2_fw->data + 2715 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2716 table_offset = le32_to_cpu(hdr->jt_offset); 2717 table_size = le32_to_cpu(hdr->jt_size); 2718 } 2719 2720 for (i = 0; i < table_size; i ++) { 2721 dst_ptr[bo_offset + i] = 2722 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2723 } 2724 2725 bo_offset += table_size; 2726 } 2727 } 2728 */ 2729 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2730 bool enable) 2731 { 2732 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2733 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2734 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2735 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2736 } else { 2737 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2738 (void)RREG32(mmDB_RENDER_CONTROL); 2739 } 2740 } 2741 2742 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2743 { 2744 u32 tmp; 2745 2746 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2747 2748 tmp = RREG32(mmRLC_MAX_PG_CU); 2749 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2750 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2751 WREG32(mmRLC_MAX_PG_CU, tmp); 2752 } 2753 2754 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2755 bool enable) 2756 { 2757 u32 data, orig; 2758 2759 orig = data = RREG32(mmRLC_PG_CNTL); 2760 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2761 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2762 else 2763 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2764 if (orig != data) 2765 WREG32(mmRLC_PG_CNTL, data); 2766 } 2767 2768 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2769 bool enable) 2770 { 2771 u32 data, orig; 2772 2773 orig = data = RREG32(mmRLC_PG_CNTL); 2774 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2775 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2776 else 2777 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2778 if (orig != data) 2779 WREG32(mmRLC_PG_CNTL, data); 2780 } 2781 2782 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2783 { 2784 u32 tmp; 2785 2786 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2787 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2788 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2789 2790 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2791 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2792 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2793 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2794 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2795 } 2796 2797 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2798 { 2799 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2800 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2801 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2802 } 2803 2804 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2805 { 2806 u32 count = 0; 2807 const struct cs_section_def *sect = NULL; 2808 const struct cs_extent_def *ext = NULL; 2809 2810 if (adev->gfx.rlc.cs_data == NULL) 2811 return 0; 2812 2813 /* begin clear state */ 2814 count += 2; 2815 /* context control state */ 2816 count += 3; 2817 2818 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2819 for (ext = sect->section; ext->extent != NULL; ++ext) { 2820 if (sect->id == SECT_CONTEXT) 2821 count += 2 + ext->reg_count; 2822 else 2823 return 0; 2824 } 2825 } 2826 /* pa_sc_raster_config */ 2827 count += 3; 2828 /* end clear state */ 2829 count += 2; 2830 /* clear state */ 2831 count += 2; 2832 2833 return count; 2834 } 2835 2836 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2837 volatile u32 *buffer) 2838 { 2839 u32 count = 0, i; 2840 const struct cs_section_def *sect = NULL; 2841 const struct cs_extent_def *ext = NULL; 2842 2843 if (adev->gfx.rlc.cs_data == NULL) 2844 return; 2845 if (buffer == NULL) 2846 return; 2847 2848 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2849 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2850 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2851 buffer[count++] = cpu_to_le32(0x80000000); 2852 buffer[count++] = cpu_to_le32(0x80000000); 2853 2854 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2855 for (ext = sect->section; ext->extent != NULL; ++ext) { 2856 if (sect->id == SECT_CONTEXT) { 2857 buffer[count++] = 2858 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2859 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2860 for (i = 0; i < ext->reg_count; i++) 2861 buffer[count++] = cpu_to_le32(ext->extent[i]); 2862 } else { 2863 return; 2864 } 2865 } 2866 } 2867 2868 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2869 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2870 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2871 2872 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2873 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2874 2875 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2876 buffer[count++] = cpu_to_le32(0); 2877 } 2878 2879 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2880 { 2881 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2882 AMD_PG_SUPPORT_GFX_SMG | 2883 AMD_PG_SUPPORT_GFX_DMG | 2884 AMD_PG_SUPPORT_CP | 2885 AMD_PG_SUPPORT_GDS | 2886 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2887 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2888 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2889 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2890 gfx_v6_0_init_gfx_cgpg(adev); 2891 gfx_v6_0_enable_cp_pg(adev, true); 2892 gfx_v6_0_enable_gds_pg(adev, true); 2893 } else { 2894 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2895 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2896 2897 } 2898 gfx_v6_0_init_ao_cu_mask(adev); 2899 gfx_v6_0_update_gfx_pg(adev, true); 2900 } else { 2901 2902 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2903 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2904 } 2905 } 2906 2907 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2908 { 2909 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2910 AMD_PG_SUPPORT_GFX_SMG | 2911 AMD_PG_SUPPORT_GFX_DMG | 2912 AMD_PG_SUPPORT_CP | 2913 AMD_PG_SUPPORT_GDS | 2914 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2915 gfx_v6_0_update_gfx_pg(adev, false); 2916 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2917 gfx_v6_0_enable_cp_pg(adev, false); 2918 gfx_v6_0_enable_gds_pg(adev, false); 2919 } 2920 } 2921 } 2922 2923 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2924 { 2925 uint64_t clock; 2926 2927 mutex_lock(&adev->gfx.gpu_clock_mutex); 2928 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2929 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2930 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2931 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2932 return clock; 2933 } 2934 2935 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2936 { 2937 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2938 gfx_v6_0_ring_emit_vgt_flush(ring); 2939 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2940 amdgpu_ring_write(ring, 0x80000000); 2941 amdgpu_ring_write(ring, 0); 2942 } 2943 2944 2945 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2946 { 2947 WREG32(mmSQ_IND_INDEX, 2948 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2949 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2950 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2951 (SQ_IND_INDEX__FORCE_READ_MASK)); 2952 return RREG32(mmSQ_IND_DATA); 2953 } 2954 2955 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2956 uint32_t wave, uint32_t thread, 2957 uint32_t regno, uint32_t num, uint32_t *out) 2958 { 2959 WREG32(mmSQ_IND_INDEX, 2960 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2961 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2962 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2963 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2964 (SQ_IND_INDEX__FORCE_READ_MASK) | 2965 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2966 while (num--) 2967 *(out++) = RREG32(mmSQ_IND_DATA); 2968 } 2969 2970 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2971 { 2972 /* type 0 wave data */ 2973 dst[(*no_fields)++] = 0; 2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 2993 } 2994 2995 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 2996 uint32_t wave, uint32_t start, 2997 uint32_t size, uint32_t *dst) 2998 { 2999 wave_read_regs( 3000 adev, simd, wave, 0, 3001 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3002 } 3003 3004 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3005 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3006 { 3007 DRM_INFO("Not implemented\n"); 3008 } 3009 3010 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3011 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3012 .select_se_sh = &gfx_v6_0_select_se_sh, 3013 .read_wave_data = &gfx_v6_0_read_wave_data, 3014 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3015 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3016 }; 3017 3018 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3019 .init = gfx_v6_0_rlc_init, 3020 .resume = gfx_v6_0_rlc_resume, 3021 .stop = gfx_v6_0_rlc_stop, 3022 .reset = gfx_v6_0_rlc_reset, 3023 .start = gfx_v6_0_rlc_start 3024 }; 3025 3026 static int gfx_v6_0_early_init(void *handle) 3027 { 3028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3029 3030 adev->gfx.xcc_mask = 1; 3031 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3032 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3033 GFX6_NUM_COMPUTE_RINGS); 3034 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3035 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3036 gfx_v6_0_set_ring_funcs(adev); 3037 gfx_v6_0_set_irq_funcs(adev); 3038 3039 return 0; 3040 } 3041 3042 static int gfx_v6_0_sw_init(void *handle) 3043 { 3044 struct amdgpu_ring *ring; 3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3046 int i, r; 3047 3048 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3049 if (r) 3050 return r; 3051 3052 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3053 if (r) 3054 return r; 3055 3056 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3057 if (r) 3058 return r; 3059 3060 r = gfx_v6_0_init_microcode(adev); 3061 if (r) { 3062 DRM_ERROR("Failed to load gfx firmware!\n"); 3063 return r; 3064 } 3065 3066 r = adev->gfx.rlc.funcs->init(adev); 3067 if (r) { 3068 DRM_ERROR("Failed to init rlc BOs!\n"); 3069 return r; 3070 } 3071 3072 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3073 ring = &adev->gfx.gfx_ring[i]; 3074 ring->ring_obj = NULL; 3075 sprintf(ring->name, "gfx"); 3076 r = amdgpu_ring_init(adev, ring, 2048, 3077 &adev->gfx.eop_irq, 3078 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3079 AMDGPU_RING_PRIO_DEFAULT, NULL); 3080 if (r) 3081 return r; 3082 } 3083 3084 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3085 unsigned irq_type; 3086 3087 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3088 DRM_ERROR("Too many (%d) compute rings!\n", i); 3089 break; 3090 } 3091 ring = &adev->gfx.compute_ring[i]; 3092 ring->ring_obj = NULL; 3093 ring->use_doorbell = false; 3094 ring->doorbell_index = 0; 3095 ring->me = 1; 3096 ring->pipe = i; 3097 ring->queue = i; 3098 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3099 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3100 r = amdgpu_ring_init(adev, ring, 1024, 3101 &adev->gfx.eop_irq, irq_type, 3102 AMDGPU_RING_PRIO_DEFAULT, NULL); 3103 if (r) 3104 return r; 3105 } 3106 3107 return r; 3108 } 3109 3110 static int gfx_v6_0_sw_fini(void *handle) 3111 { 3112 int i; 3113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3114 3115 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3116 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3117 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3118 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3119 3120 amdgpu_gfx_rlc_fini(adev); 3121 3122 return 0; 3123 } 3124 3125 static int gfx_v6_0_hw_init(void *handle) 3126 { 3127 int r; 3128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3129 3130 gfx_v6_0_constants_init(adev); 3131 3132 r = adev->gfx.rlc.funcs->resume(adev); 3133 if (r) 3134 return r; 3135 3136 r = gfx_v6_0_cp_resume(adev); 3137 if (r) 3138 return r; 3139 3140 adev->gfx.ce_ram_size = 0x8000; 3141 3142 return r; 3143 } 3144 3145 static int gfx_v6_0_hw_fini(void *handle) 3146 { 3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3148 3149 gfx_v6_0_cp_enable(adev, false); 3150 adev->gfx.rlc.funcs->stop(adev); 3151 gfx_v6_0_fini_pg(adev); 3152 3153 return 0; 3154 } 3155 3156 static int gfx_v6_0_suspend(void *handle) 3157 { 3158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3159 3160 return gfx_v6_0_hw_fini(adev); 3161 } 3162 3163 static int gfx_v6_0_resume(void *handle) 3164 { 3165 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3166 3167 return gfx_v6_0_hw_init(adev); 3168 } 3169 3170 static bool gfx_v6_0_is_idle(void *handle) 3171 { 3172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3173 3174 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3175 return false; 3176 else 3177 return true; 3178 } 3179 3180 static int gfx_v6_0_wait_for_idle(void *handle) 3181 { 3182 unsigned i; 3183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3184 3185 for (i = 0; i < adev->usec_timeout; i++) { 3186 if (gfx_v6_0_is_idle(handle)) 3187 return 0; 3188 udelay(1); 3189 } 3190 return -ETIMEDOUT; 3191 } 3192 3193 static int gfx_v6_0_soft_reset(void *handle) 3194 { 3195 return 0; 3196 } 3197 3198 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3199 enum amdgpu_interrupt_state state) 3200 { 3201 u32 cp_int_cntl; 3202 3203 switch (state) { 3204 case AMDGPU_IRQ_STATE_DISABLE: 3205 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3206 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3207 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3208 break; 3209 case AMDGPU_IRQ_STATE_ENABLE: 3210 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3211 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3212 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3213 break; 3214 default: 3215 break; 3216 } 3217 } 3218 3219 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3220 int ring, 3221 enum amdgpu_interrupt_state state) 3222 { 3223 u32 cp_int_cntl; 3224 switch (state){ 3225 case AMDGPU_IRQ_STATE_DISABLE: 3226 if (ring == 0) { 3227 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3228 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3229 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3230 break; 3231 } else { 3232 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3233 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3234 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3235 break; 3236 3237 } 3238 case AMDGPU_IRQ_STATE_ENABLE: 3239 if (ring == 0) { 3240 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3241 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3242 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3243 break; 3244 } else { 3245 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3246 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3247 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3248 break; 3249 3250 } 3251 3252 default: 3253 BUG(); 3254 break; 3255 3256 } 3257 } 3258 3259 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3260 struct amdgpu_irq_src *src, 3261 unsigned type, 3262 enum amdgpu_interrupt_state state) 3263 { 3264 u32 cp_int_cntl; 3265 3266 switch (state) { 3267 case AMDGPU_IRQ_STATE_DISABLE: 3268 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3269 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3270 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3271 break; 3272 case AMDGPU_IRQ_STATE_ENABLE: 3273 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3274 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3275 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3276 break; 3277 default: 3278 break; 3279 } 3280 3281 return 0; 3282 } 3283 3284 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3285 struct amdgpu_irq_src *src, 3286 unsigned type, 3287 enum amdgpu_interrupt_state state) 3288 { 3289 u32 cp_int_cntl; 3290 3291 switch (state) { 3292 case AMDGPU_IRQ_STATE_DISABLE: 3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3294 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3295 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3296 break; 3297 case AMDGPU_IRQ_STATE_ENABLE: 3298 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3299 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3300 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3301 break; 3302 default: 3303 break; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3310 struct amdgpu_irq_src *src, 3311 unsigned type, 3312 enum amdgpu_interrupt_state state) 3313 { 3314 switch (type) { 3315 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3316 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3317 break; 3318 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3319 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3320 break; 3321 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3322 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3323 break; 3324 default: 3325 break; 3326 } 3327 return 0; 3328 } 3329 3330 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3331 struct amdgpu_irq_src *source, 3332 struct amdgpu_iv_entry *entry) 3333 { 3334 switch (entry->ring_id) { 3335 case 0: 3336 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3337 break; 3338 case 1: 3339 case 2: 3340 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3341 break; 3342 default: 3343 break; 3344 } 3345 return 0; 3346 } 3347 3348 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3349 struct amdgpu_iv_entry *entry) 3350 { 3351 struct amdgpu_ring *ring; 3352 3353 switch (entry->ring_id) { 3354 case 0: 3355 ring = &adev->gfx.gfx_ring[0]; 3356 break; 3357 case 1: 3358 case 2: 3359 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3360 break; 3361 default: 3362 return; 3363 } 3364 drm_sched_fault(&ring->sched); 3365 } 3366 3367 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3368 struct amdgpu_irq_src *source, 3369 struct amdgpu_iv_entry *entry) 3370 { 3371 DRM_ERROR("Illegal register access in command stream\n"); 3372 gfx_v6_0_fault(adev, entry); 3373 return 0; 3374 } 3375 3376 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3377 struct amdgpu_irq_src *source, 3378 struct amdgpu_iv_entry *entry) 3379 { 3380 DRM_ERROR("Illegal instruction in command stream\n"); 3381 gfx_v6_0_fault(adev, entry); 3382 return 0; 3383 } 3384 3385 static int gfx_v6_0_set_clockgating_state(void *handle, 3386 enum amd_clockgating_state state) 3387 { 3388 bool gate = false; 3389 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3390 3391 if (state == AMD_CG_STATE_GATE) 3392 gate = true; 3393 3394 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3395 if (gate) { 3396 gfx_v6_0_enable_mgcg(adev, true); 3397 gfx_v6_0_enable_cgcg(adev, true); 3398 } else { 3399 gfx_v6_0_enable_cgcg(adev, false); 3400 gfx_v6_0_enable_mgcg(adev, false); 3401 } 3402 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3403 3404 return 0; 3405 } 3406 3407 static int gfx_v6_0_set_powergating_state(void *handle, 3408 enum amd_powergating_state state) 3409 { 3410 bool gate = false; 3411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3412 3413 if (state == AMD_PG_STATE_GATE) 3414 gate = true; 3415 3416 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3417 AMD_PG_SUPPORT_GFX_SMG | 3418 AMD_PG_SUPPORT_GFX_DMG | 3419 AMD_PG_SUPPORT_CP | 3420 AMD_PG_SUPPORT_GDS | 3421 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3422 gfx_v6_0_update_gfx_pg(adev, gate); 3423 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3424 gfx_v6_0_enable_cp_pg(adev, gate); 3425 gfx_v6_0_enable_gds_pg(adev, gate); 3426 } 3427 } 3428 3429 return 0; 3430 } 3431 3432 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3433 { 3434 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3435 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3436 PACKET3_TC_ACTION_ENA | 3437 PACKET3_SH_KCACHE_ACTION_ENA | 3438 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3439 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3440 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3441 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3442 } 3443 3444 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3445 .name = "gfx_v6_0", 3446 .early_init = gfx_v6_0_early_init, 3447 .late_init = NULL, 3448 .sw_init = gfx_v6_0_sw_init, 3449 .sw_fini = gfx_v6_0_sw_fini, 3450 .hw_init = gfx_v6_0_hw_init, 3451 .hw_fini = gfx_v6_0_hw_fini, 3452 .suspend = gfx_v6_0_suspend, 3453 .resume = gfx_v6_0_resume, 3454 .is_idle = gfx_v6_0_is_idle, 3455 .wait_for_idle = gfx_v6_0_wait_for_idle, 3456 .soft_reset = gfx_v6_0_soft_reset, 3457 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3458 .set_powergating_state = gfx_v6_0_set_powergating_state, 3459 .dump_ip_state = NULL, 3460 .print_ip_state = NULL, 3461 }; 3462 3463 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3464 .type = AMDGPU_RING_TYPE_GFX, 3465 .align_mask = 0xff, 3466 .nop = 0x80000000, 3467 .support_64bit_ptrs = false, 3468 .get_rptr = gfx_v6_0_ring_get_rptr, 3469 .get_wptr = gfx_v6_0_ring_get_wptr, 3470 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3471 .emit_frame_size = 3472 5 + 5 + /* hdp flush / invalidate */ 3473 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3474 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3475 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3476 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3477 5, /* SURFACE_SYNC */ 3478 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3479 .emit_ib = gfx_v6_0_ring_emit_ib, 3480 .emit_fence = gfx_v6_0_ring_emit_fence, 3481 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3482 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3483 .test_ring = gfx_v6_0_ring_test_ring, 3484 .test_ib = gfx_v6_0_ring_test_ib, 3485 .insert_nop = amdgpu_ring_insert_nop, 3486 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3487 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3488 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3489 }; 3490 3491 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3492 .type = AMDGPU_RING_TYPE_COMPUTE, 3493 .align_mask = 0xff, 3494 .nop = 0x80000000, 3495 .get_rptr = gfx_v6_0_ring_get_rptr, 3496 .get_wptr = gfx_v6_0_ring_get_wptr, 3497 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3498 .emit_frame_size = 3499 5 + 5 + /* hdp flush / invalidate */ 3500 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3501 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3502 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3503 5, /* SURFACE_SYNC */ 3504 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3505 .emit_ib = gfx_v6_0_ring_emit_ib, 3506 .emit_fence = gfx_v6_0_ring_emit_fence, 3507 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3508 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3509 .test_ring = gfx_v6_0_ring_test_ring, 3510 .test_ib = gfx_v6_0_ring_test_ib, 3511 .insert_nop = amdgpu_ring_insert_nop, 3512 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3513 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3514 }; 3515 3516 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3517 { 3518 int i; 3519 3520 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3521 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3522 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3523 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3524 } 3525 3526 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3527 .set = gfx_v6_0_set_eop_interrupt_state, 3528 .process = gfx_v6_0_eop_irq, 3529 }; 3530 3531 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3532 .set = gfx_v6_0_set_priv_reg_fault_state, 3533 .process = gfx_v6_0_priv_reg_irq, 3534 }; 3535 3536 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3537 .set = gfx_v6_0_set_priv_inst_fault_state, 3538 .process = gfx_v6_0_priv_inst_irq, 3539 }; 3540 3541 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3542 { 3543 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3544 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3545 3546 adev->gfx.priv_reg_irq.num_types = 1; 3547 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3548 3549 adev->gfx.priv_inst_irq.num_types = 1; 3550 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3551 } 3552 3553 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3554 { 3555 int i, j, k, counter, active_cu_number = 0; 3556 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3557 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3558 unsigned disable_masks[4 * 2]; 3559 u32 ao_cu_num; 3560 3561 if (adev->flags & AMD_IS_APU) 3562 ao_cu_num = 2; 3563 else 3564 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3565 3566 memset(cu_info, 0, sizeof(*cu_info)); 3567 3568 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3569 3570 mutex_lock(&adev->grbm_idx_mutex); 3571 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3572 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3573 mask = 1; 3574 ao_bitmap = 0; 3575 counter = 0; 3576 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3577 if (i < 4 && j < 2) 3578 gfx_v6_0_set_user_cu_inactive_bitmap( 3579 adev, disable_masks[i * 2 + j]); 3580 bitmap = gfx_v6_0_get_cu_enabled(adev); 3581 cu_info->bitmap[0][i][j] = bitmap; 3582 3583 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3584 if (bitmap & mask) { 3585 if (counter < ao_cu_num) 3586 ao_bitmap |= mask; 3587 counter ++; 3588 } 3589 mask <<= 1; 3590 } 3591 active_cu_number += counter; 3592 if (i < 2 && j < 2) 3593 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3594 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3595 } 3596 } 3597 3598 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3599 mutex_unlock(&adev->grbm_idx_mutex); 3600 3601 cu_info->number = active_cu_number; 3602 cu_info->ao_cu_mask = ao_cu_mask; 3603 } 3604 3605 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3606 { 3607 .type = AMD_IP_BLOCK_TYPE_GFX, 3608 .major = 6, 3609 .minor = 0, 3610 .rev = 0, 3611 .funcs = &gfx_v6_0_ip_funcs, 3612 }; 3613