1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "si.h" 32 #include "sid.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 37 #include "oss/oss_1_0_d.h" 38 #include "oss/oss_1_0_sh_mask.h" 39 40 #include "gca/gfx_6_0_d.h" 41 #include "gca/gfx_6_0_sh_mask.h" 42 #include "gca/gfx_7_2_enum.h" 43 44 #include "gmc/gmc_6_0_d.h" 45 #include "gmc/gmc_6_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "si_enums.h" 51 52 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 53 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 54 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 55 56 #define GFX6_NUM_GFX_RINGS 1 57 #define GFX6_NUM_COMPUTE_RINGS 2 58 59 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 61 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 62 63 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 65 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 66 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 67 68 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 70 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 75 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 77 78 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 80 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 81 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 85 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 87 88 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 89 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 90 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 91 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 92 93 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 94 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 95 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 96 #define MICRO_TILE_MODE(x) ((x) << 0) 97 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 98 #define BANK_WIDTH(x) ((x) << 14) 99 #define BANK_HEIGHT(x) ((x) << 16) 100 #define MACRO_TILE_ASPECT(x) ((x) << 18) 101 #define NUM_BANKS(x) ((x) << 20) 102 103 static const u32 verde_rlc_save_restore_register_list[] = 104 { 105 (0x8000 << 16) | (0x98f4 >> 2), 106 0x00000000, 107 (0x8040 << 16) | (0x98f4 >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0xe80 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0xe80 >> 2), 112 0x00000000, 113 (0x8000 << 16) | (0x89bc >> 2), 114 0x00000000, 115 (0x8040 << 16) | (0x89bc >> 2), 116 0x00000000, 117 (0x8000 << 16) | (0x8c1c >> 2), 118 0x00000000, 119 (0x8040 << 16) | (0x8c1c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0x98f0 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0xe7c >> 2), 124 0x00000000, 125 (0x8000 << 16) | (0x9148 >> 2), 126 0x00000000, 127 (0x8040 << 16) | (0x9148 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x9150 >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x897c >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x8d8c >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0xac54 >> 2), 136 0X00000000, 137 0x3, 138 (0x9c00 << 16) | (0x98f8 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9910 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9914 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9918 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x991c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9920 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9924 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9928 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x992c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9930 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9934 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9938 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x993c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9940 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9944 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9948 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x994c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9950 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9954 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9958 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x995c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9960 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9964 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9968 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x996c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x9970 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x9974 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x9978 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x997c >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x9980 >> 2), 197 0x00000000, 198 (0x9c00 << 16) | (0x9984 >> 2), 199 0x00000000, 200 (0x9c00 << 16) | (0x9988 >> 2), 201 0x00000000, 202 (0x9c00 << 16) | (0x998c >> 2), 203 0x00000000, 204 (0x9c00 << 16) | (0x8c00 >> 2), 205 0x00000000, 206 (0x9c00 << 16) | (0x8c14 >> 2), 207 0x00000000, 208 (0x9c00 << 16) | (0x8c04 >> 2), 209 0x00000000, 210 (0x9c00 << 16) | (0x8c08 >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x9b7c >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x9b7c >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0xe84 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0xe84 >> 2), 219 0x00000000, 220 (0x8000 << 16) | (0x89c0 >> 2), 221 0x00000000, 222 (0x8040 << 16) | (0x89c0 >> 2), 223 0x00000000, 224 (0x8000 << 16) | (0x914c >> 2), 225 0x00000000, 226 (0x8040 << 16) | (0x914c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x8c20 >> 2), 229 0x00000000, 230 (0x8040 << 16) | (0x8c20 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x9354 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x9354 >> 2), 235 0x00000000, 236 (0x9c00 << 16) | (0x9060 >> 2), 237 0x00000000, 238 (0x9c00 << 16) | (0x9364 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x9100 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x913c >> 2), 243 0x00000000, 244 (0x8000 << 16) | (0x90e0 >> 2), 245 0x00000000, 246 (0x8000 << 16) | (0x90e4 >> 2), 247 0x00000000, 248 (0x8000 << 16) | (0x90e8 >> 2), 249 0x00000000, 250 (0x8040 << 16) | (0x90e0 >> 2), 251 0x00000000, 252 (0x8040 << 16) | (0x90e4 >> 2), 253 0x00000000, 254 (0x8040 << 16) | (0x90e8 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x8bcc >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x8b24 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x88c4 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0x8e50 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0x8c0c >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0x8e58 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0x8e5c >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x9508 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x950c >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x9494 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0xac0c >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0xac10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0xac14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0xae00 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0xac08 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x88d4 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x88c8 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x88cc >> 2), 291 0x00000000, 292 (0x9c00 << 16) | (0x89b0 >> 2), 293 0x00000000, 294 (0x9c00 << 16) | (0x8b10 >> 2), 295 0x00000000, 296 (0x9c00 << 16) | (0x8a14 >> 2), 297 0x00000000, 298 (0x9c00 << 16) | (0x9830 >> 2), 299 0x00000000, 300 (0x9c00 << 16) | (0x9834 >> 2), 301 0x00000000, 302 (0x9c00 << 16) | (0x9838 >> 2), 303 0x00000000, 304 (0x9c00 << 16) | (0x9a10 >> 2), 305 0x00000000, 306 (0x8000 << 16) | (0x9870 >> 2), 307 0x00000000, 308 (0x8000 << 16) | (0x9874 >> 2), 309 0x00000000, 310 (0x8001 << 16) | (0x9870 >> 2), 311 0x00000000, 312 (0x8001 << 16) | (0x9874 >> 2), 313 0x00000000, 314 (0x8040 << 16) | (0x9870 >> 2), 315 0x00000000, 316 (0x8040 << 16) | (0x9874 >> 2), 317 0x00000000, 318 (0x8041 << 16) | (0x9870 >> 2), 319 0x00000000, 320 (0x8041 << 16) | (0x9874 >> 2), 321 0x00000000, 322 0x00000000 323 }; 324 325 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 326 { 327 const char *chip_name; 328 int err; 329 const struct gfx_firmware_header_v1_0 *cp_hdr; 330 const struct rlc_firmware_header_v1_0 *rlc_hdr; 331 332 DRM_DEBUG("\n"); 333 334 switch (adev->asic_type) { 335 case CHIP_TAHITI: 336 chip_name = "tahiti"; 337 break; 338 case CHIP_PITCAIRN: 339 chip_name = "pitcairn"; 340 break; 341 case CHIP_VERDE: 342 chip_name = "verde"; 343 break; 344 case CHIP_OLAND: 345 chip_name = "oland"; 346 break; 347 case CHIP_HAINAN: 348 chip_name = "hainan"; 349 break; 350 default: 351 return -EINVAL; 352 } 353 354 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 355 AMDGPU_UCODE_REQUIRED, 356 "amdgpu/%s_pfp.bin", chip_name); 357 if (err) 358 goto out; 359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 360 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 361 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 362 363 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 364 AMDGPU_UCODE_REQUIRED, 365 "amdgpu/%s_me.bin", chip_name); 366 if (err) 367 goto out; 368 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 369 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 370 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 371 372 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 373 AMDGPU_UCODE_REQUIRED, 374 "amdgpu/%s_ce.bin", chip_name); 375 if (err) 376 goto out; 377 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 378 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 379 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 380 381 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 382 AMDGPU_UCODE_REQUIRED, 383 "amdgpu/%s_rlc.bin", chip_name); 384 if (err) 385 goto out; 386 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 387 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 388 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 389 390 out: 391 if (err) { 392 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); 393 amdgpu_ucode_release(&adev->gfx.pfp_fw); 394 amdgpu_ucode_release(&adev->gfx.me_fw); 395 amdgpu_ucode_release(&adev->gfx.ce_fw); 396 amdgpu_ucode_release(&adev->gfx.rlc_fw); 397 } 398 return err; 399 } 400 401 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 402 { 403 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 404 u32 reg_offset, split_equal_to_row_size, *tilemode; 405 406 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 407 tilemode = adev->gfx.config.tile_mode_array; 408 409 switch (adev->gfx.config.mem_row_size_in_kb) { 410 case 1: 411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 412 break; 413 case 2: 414 default: 415 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 416 break; 417 case 4: 418 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 419 break; 420 } 421 422 if (adev->asic_type == CHIP_VERDE) { 423 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 424 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 425 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 426 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 427 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 430 NUM_BANKS(ADDR_SURF_16_BANK); 431 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 432 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 433 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 438 NUM_BANKS(ADDR_SURF_16_BANK); 439 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 446 NUM_BANKS(ADDR_SURF_16_BANK); 447 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 449 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 450 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 453 NUM_BANKS(ADDR_SURF_8_BANK) | 454 TILE_SPLIT(split_equal_to_row_size); 455 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 456 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 457 PIPE_CONFIG(ADDR_SURF_P4_8x16); 458 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 459 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 460 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 461 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 462 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 465 NUM_BANKS(ADDR_SURF_4_BANK); 466 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 467 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 468 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 469 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 470 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 471 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 472 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 473 NUM_BANKS(ADDR_SURF_4_BANK); 474 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 475 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 476 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 477 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 478 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 481 NUM_BANKS(ADDR_SURF_2_BANK); 482 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 483 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 484 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 485 PIPE_CONFIG(ADDR_SURF_P4_8x16); 486 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 487 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 488 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 490 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 493 NUM_BANKS(ADDR_SURF_16_BANK); 494 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 496 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 501 NUM_BANKS(ADDR_SURF_16_BANK); 502 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 504 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 509 NUM_BANKS(ADDR_SURF_16_BANK); 510 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 511 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16); 513 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 514 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 515 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 517 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 520 NUM_BANKS(ADDR_SURF_16_BANK); 521 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 523 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 528 NUM_BANKS(ADDR_SURF_16_BANK); 529 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 530 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 531 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 536 NUM_BANKS(ADDR_SURF_16_BANK); 537 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 538 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 539 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 543 NUM_BANKS(ADDR_SURF_16_BANK) | 544 TILE_SPLIT(split_equal_to_row_size); 545 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 546 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 547 PIPE_CONFIG(ADDR_SURF_P4_8x16); 548 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 549 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 550 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 551 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 554 NUM_BANKS(ADDR_SURF_16_BANK) | 555 TILE_SPLIT(split_equal_to_row_size); 556 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 557 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 558 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 559 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 562 NUM_BANKS(ADDR_SURF_16_BANK) | 563 TILE_SPLIT(split_equal_to_row_size); 564 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 565 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 566 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 567 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 571 NUM_BANKS(ADDR_SURF_8_BANK); 572 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 573 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 574 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 575 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 576 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 579 NUM_BANKS(ADDR_SURF_8_BANK); 580 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 581 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 583 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 587 NUM_BANKS(ADDR_SURF_4_BANK); 588 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 589 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 590 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 595 NUM_BANKS(ADDR_SURF_4_BANK); 596 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 597 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 598 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 599 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 600 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 603 NUM_BANKS(ADDR_SURF_2_BANK); 604 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 605 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 606 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 607 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 611 NUM_BANKS(ADDR_SURF_2_BANK); 612 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 613 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 614 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 615 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 616 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 619 NUM_BANKS(ADDR_SURF_2_BANK); 620 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 621 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 622 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 624 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 627 NUM_BANKS(ADDR_SURF_2_BANK); 628 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 632 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 633 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 634 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 635 NUM_BANKS(ADDR_SURF_2_BANK); 636 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 638 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 640 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 643 NUM_BANKS(ADDR_SURF_2_BANK); 644 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 645 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 646 } else if (adev->asic_type == CHIP_OLAND) { 647 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 648 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 649 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 650 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 651 NUM_BANKS(ADDR_SURF_16_BANK) | 652 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 653 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 654 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 655 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 656 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 657 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 659 NUM_BANKS(ADDR_SURF_16_BANK) | 660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 663 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 664 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 665 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 666 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 667 NUM_BANKS(ADDR_SURF_16_BANK) | 668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 669 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 670 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 671 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 673 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 675 NUM_BANKS(ADDR_SURF_16_BANK) | 676 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 677 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 678 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 679 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 680 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 681 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 682 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 683 NUM_BANKS(ADDR_SURF_16_BANK) | 684 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 687 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 688 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 689 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 690 TILE_SPLIT(split_equal_to_row_size) | 691 NUM_BANKS(ADDR_SURF_16_BANK) | 692 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 693 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 694 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 695 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 696 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 697 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 698 TILE_SPLIT(split_equal_to_row_size) | 699 NUM_BANKS(ADDR_SURF_16_BANK) | 700 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 703 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 704 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 705 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 706 TILE_SPLIT(split_equal_to_row_size) | 707 NUM_BANKS(ADDR_SURF_16_BANK) | 708 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 711 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 712 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 713 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 715 NUM_BANKS(ADDR_SURF_16_BANK) | 716 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 717 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 718 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 719 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 720 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 721 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 723 NUM_BANKS(ADDR_SURF_16_BANK) | 724 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 727 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 728 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 729 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 730 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 731 NUM_BANKS(ADDR_SURF_16_BANK) | 732 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 734 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 735 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 736 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 737 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 738 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 739 NUM_BANKS(ADDR_SURF_16_BANK) | 740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 743 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 744 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 745 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 746 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 747 NUM_BANKS(ADDR_SURF_16_BANK) | 748 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 751 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 752 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 753 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 754 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 755 NUM_BANKS(ADDR_SURF_16_BANK) | 756 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 757 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 758 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 759 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 760 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 761 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 762 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 763 NUM_BANKS(ADDR_SURF_16_BANK) | 764 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 765 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 766 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 767 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 768 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 769 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 770 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 771 NUM_BANKS(ADDR_SURF_16_BANK) | 772 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 773 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 774 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 775 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 776 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 777 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 779 NUM_BANKS(ADDR_SURF_16_BANK) | 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 783 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 784 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 785 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 786 TILE_SPLIT(split_equal_to_row_size) | 787 NUM_BANKS(ADDR_SURF_16_BANK) | 788 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 789 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 790 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 791 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 792 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 793 PIPE_CONFIG(ADDR_SURF_P4_8x16); 794 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 795 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 796 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 800 NUM_BANKS(ADDR_SURF_16_BANK) | 801 TILE_SPLIT(split_equal_to_row_size); 802 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 803 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 804 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 808 NUM_BANKS(ADDR_SURF_16_BANK) | 809 TILE_SPLIT(split_equal_to_row_size); 810 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 811 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 812 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 813 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 814 NUM_BANKS(ADDR_SURF_16_BANK) | 815 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 818 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 819 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 821 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 822 NUM_BANKS(ADDR_SURF_16_BANK) | 823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 826 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 827 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 828 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 829 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 830 NUM_BANKS(ADDR_SURF_16_BANK) | 831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 834 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 836 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 838 NUM_BANKS(ADDR_SURF_16_BANK) | 839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 842 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 844 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 846 NUM_BANKS(ADDR_SURF_8_BANK) | 847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 850 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 851 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 852 } else if (adev->asic_type == CHIP_HAINAN) { 853 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 854 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 855 PIPE_CONFIG(ADDR_SURF_P2) | 856 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 857 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 860 NUM_BANKS(ADDR_SURF_16_BANK); 861 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 862 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 863 PIPE_CONFIG(ADDR_SURF_P2) | 864 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 868 NUM_BANKS(ADDR_SURF_16_BANK); 869 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 871 PIPE_CONFIG(ADDR_SURF_P2) | 872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 876 NUM_BANKS(ADDR_SURF_16_BANK); 877 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 879 PIPE_CONFIG(ADDR_SURF_P2) | 880 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 883 NUM_BANKS(ADDR_SURF_8_BANK) | 884 TILE_SPLIT(split_equal_to_row_size); 885 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 886 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 887 PIPE_CONFIG(ADDR_SURF_P2); 888 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 889 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 890 PIPE_CONFIG(ADDR_SURF_P2) | 891 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 892 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 893 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 894 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 895 NUM_BANKS(ADDR_SURF_8_BANK); 896 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 897 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 898 PIPE_CONFIG(ADDR_SURF_P2) | 899 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 903 NUM_BANKS(ADDR_SURF_8_BANK); 904 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 906 PIPE_CONFIG(ADDR_SURF_P2) | 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 911 NUM_BANKS(ADDR_SURF_4_BANK); 912 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 913 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 914 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 915 PIPE_CONFIG(ADDR_SURF_P2); 916 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 917 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 918 PIPE_CONFIG(ADDR_SURF_P2) | 919 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 923 NUM_BANKS(ADDR_SURF_16_BANK); 924 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 926 PIPE_CONFIG(ADDR_SURF_P2) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 931 NUM_BANKS(ADDR_SURF_16_BANK); 932 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 PIPE_CONFIG(ADDR_SURF_P2) | 935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 939 NUM_BANKS(ADDR_SURF_16_BANK); 940 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 941 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 942 PIPE_CONFIG(ADDR_SURF_P2); 943 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 944 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 945 PIPE_CONFIG(ADDR_SURF_P2) | 946 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 947 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 948 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 949 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 950 NUM_BANKS(ADDR_SURF_16_BANK); 951 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 952 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 953 PIPE_CONFIG(ADDR_SURF_P2) | 954 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 958 NUM_BANKS(ADDR_SURF_16_BANK); 959 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 960 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 961 PIPE_CONFIG(ADDR_SURF_P2) | 962 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 966 NUM_BANKS(ADDR_SURF_16_BANK); 967 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 968 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 969 PIPE_CONFIG(ADDR_SURF_P2) | 970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 973 NUM_BANKS(ADDR_SURF_16_BANK) | 974 TILE_SPLIT(split_equal_to_row_size); 975 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 976 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 977 PIPE_CONFIG(ADDR_SURF_P2); 978 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 979 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 980 PIPE_CONFIG(ADDR_SURF_P2) | 981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 984 NUM_BANKS(ADDR_SURF_16_BANK) | 985 TILE_SPLIT(split_equal_to_row_size); 986 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 987 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 988 PIPE_CONFIG(ADDR_SURF_P2) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 992 NUM_BANKS(ADDR_SURF_16_BANK) | 993 TILE_SPLIT(split_equal_to_row_size); 994 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 995 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 996 PIPE_CONFIG(ADDR_SURF_P2) | 997 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1001 NUM_BANKS(ADDR_SURF_8_BANK); 1002 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1003 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1004 PIPE_CONFIG(ADDR_SURF_P2) | 1005 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1009 NUM_BANKS(ADDR_SURF_8_BANK); 1010 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1011 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1012 PIPE_CONFIG(ADDR_SURF_P2) | 1013 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1014 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1017 NUM_BANKS(ADDR_SURF_8_BANK); 1018 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1019 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1020 PIPE_CONFIG(ADDR_SURF_P2) | 1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1022 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1023 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1024 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1025 NUM_BANKS(ADDR_SURF_8_BANK); 1026 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1027 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1028 PIPE_CONFIG(ADDR_SURF_P2) | 1029 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1033 NUM_BANKS(ADDR_SURF_4_BANK); 1034 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1035 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1036 PIPE_CONFIG(ADDR_SURF_P2) | 1037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1041 NUM_BANKS(ADDR_SURF_4_BANK); 1042 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1043 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1044 PIPE_CONFIG(ADDR_SURF_P2) | 1045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1049 NUM_BANKS(ADDR_SURF_4_BANK); 1050 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1051 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1052 PIPE_CONFIG(ADDR_SURF_P2) | 1053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1054 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1057 NUM_BANKS(ADDR_SURF_4_BANK); 1058 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P2) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1065 NUM_BANKS(ADDR_SURF_4_BANK); 1066 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P2) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1073 NUM_BANKS(ADDR_SURF_4_BANK); 1074 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1075 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1076 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1077 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1078 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1079 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1080 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1081 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1084 NUM_BANKS(ADDR_SURF_16_BANK); 1085 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1086 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1092 NUM_BANKS(ADDR_SURF_16_BANK); 1093 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1100 NUM_BANKS(ADDR_SURF_16_BANK); 1101 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1104 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1105 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1106 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1107 NUM_BANKS(ADDR_SURF_4_BANK) | 1108 TILE_SPLIT(split_equal_to_row_size); 1109 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1110 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1111 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1112 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1113 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1116 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1119 NUM_BANKS(ADDR_SURF_2_BANK); 1120 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1121 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1122 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1123 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1124 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1127 NUM_BANKS(ADDR_SURF_2_BANK); 1128 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1129 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1130 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1131 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1132 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1135 NUM_BANKS(ADDR_SURF_2_BANK); 1136 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1137 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1138 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1140 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1141 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1142 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1143 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1144 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1147 NUM_BANKS(ADDR_SURF_16_BANK); 1148 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1155 NUM_BANKS(ADDR_SURF_16_BANK); 1156 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1163 NUM_BANKS(ADDR_SURF_16_BANK); 1164 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1165 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1167 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1168 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1169 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1170 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1171 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1174 NUM_BANKS(ADDR_SURF_16_BANK); 1175 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1176 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1177 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1178 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1182 NUM_BANKS(ADDR_SURF_16_BANK); 1183 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1184 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1186 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1190 NUM_BANKS(ADDR_SURF_16_BANK); 1191 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1192 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1194 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1197 NUM_BANKS(ADDR_SURF_16_BANK) | 1198 TILE_SPLIT(split_equal_to_row_size); 1199 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1200 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1202 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1203 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1204 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1208 NUM_BANKS(ADDR_SURF_16_BANK) | 1209 TILE_SPLIT(split_equal_to_row_size); 1210 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1211 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1212 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1216 NUM_BANKS(ADDR_SURF_16_BANK) | 1217 TILE_SPLIT(split_equal_to_row_size); 1218 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1219 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1220 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1222 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1223 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1224 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1225 NUM_BANKS(ADDR_SURF_4_BANK); 1226 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1233 NUM_BANKS(ADDR_SURF_4_BANK); 1234 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1235 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1236 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1241 NUM_BANKS(ADDR_SURF_2_BANK); 1242 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1243 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1244 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1249 NUM_BANKS(ADDR_SURF_2_BANK); 1250 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1251 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1252 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1254 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1257 NUM_BANKS(ADDR_SURF_2_BANK); 1258 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1259 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1260 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1261 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1262 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1265 NUM_BANKS(ADDR_SURF_2_BANK); 1266 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1273 NUM_BANKS(ADDR_SURF_2_BANK); 1274 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1275 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1278 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1281 NUM_BANKS(ADDR_SURF_2_BANK); 1282 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1283 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1286 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1289 NUM_BANKS(ADDR_SURF_2_BANK); 1290 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1291 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1293 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1294 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1297 NUM_BANKS(ADDR_SURF_2_BANK); 1298 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1299 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1300 } else { 1301 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1302 } 1303 } 1304 1305 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1306 u32 sh_num, u32 instance, int xcc_id) 1307 { 1308 u32 data; 1309 1310 if (instance == 0xffffffff) 1311 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1312 else 1313 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1314 1315 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1316 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1317 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1318 else if (se_num == 0xffffffff) 1319 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1320 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1321 else if (sh_num == 0xffffffff) 1322 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1323 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1324 else 1325 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1326 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1327 WREG32(mmGRBM_GFX_INDEX, data); 1328 } 1329 1330 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1331 { 1332 u32 data, mask; 1333 1334 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1335 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1336 1337 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1338 1339 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1340 adev->gfx.config.max_sh_per_se); 1341 1342 return ~data & mask; 1343 } 1344 1345 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1346 { 1347 switch (adev->asic_type) { 1348 case CHIP_TAHITI: 1349 case CHIP_PITCAIRN: 1350 *rconf |= 1351 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1352 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1353 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1354 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1355 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1356 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1357 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1358 break; 1359 case CHIP_VERDE: 1360 *rconf |= 1361 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1362 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1363 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1364 break; 1365 case CHIP_OLAND: 1366 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1367 break; 1368 case CHIP_HAINAN: 1369 *rconf |= 0x0; 1370 break; 1371 default: 1372 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1373 break; 1374 } 1375 } 1376 1377 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1378 u32 raster_config, unsigned rb_mask, 1379 unsigned num_rb) 1380 { 1381 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1382 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1383 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1384 unsigned rb_per_se = num_rb / num_se; 1385 unsigned se_mask[4]; 1386 unsigned se; 1387 1388 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1389 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1390 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1391 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1392 1393 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1394 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1395 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1396 1397 for (se = 0; se < num_se; se++) { 1398 unsigned raster_config_se = raster_config; 1399 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1400 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1401 int idx = (se / 2) * 2; 1402 1403 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1404 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1405 1406 if (!se_mask[idx]) 1407 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1408 else 1409 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1410 } 1411 1412 pkr0_mask &= rb_mask; 1413 pkr1_mask &= rb_mask; 1414 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1415 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1416 1417 if (!pkr0_mask) 1418 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1419 else 1420 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1421 } 1422 1423 if (rb_per_se >= 2) { 1424 unsigned rb0_mask = 1 << (se * rb_per_se); 1425 unsigned rb1_mask = rb0_mask << 1; 1426 1427 rb0_mask &= rb_mask; 1428 rb1_mask &= rb_mask; 1429 if (!rb0_mask || !rb1_mask) { 1430 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1431 1432 if (!rb0_mask) 1433 raster_config_se |= 1434 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1435 else 1436 raster_config_se |= 1437 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1438 } 1439 1440 if (rb_per_se > 2) { 1441 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1442 rb1_mask = rb0_mask << 1; 1443 rb0_mask &= rb_mask; 1444 rb1_mask &= rb_mask; 1445 if (!rb0_mask || !rb1_mask) { 1446 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1447 1448 if (!rb0_mask) 1449 raster_config_se |= 1450 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1451 else 1452 raster_config_se |= 1453 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1454 } 1455 } 1456 } 1457 1458 /* GRBM_GFX_INDEX has a different offset on SI */ 1459 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1460 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1461 } 1462 1463 /* GRBM_GFX_INDEX has a different offset on SI */ 1464 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1465 } 1466 1467 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1468 { 1469 int i, j; 1470 u32 data; 1471 u32 raster_config = 0; 1472 u32 active_rbs = 0; 1473 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1474 adev->gfx.config.max_sh_per_se; 1475 unsigned num_rb_pipes; 1476 1477 mutex_lock(&adev->grbm_idx_mutex); 1478 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1479 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1480 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1481 data = gfx_v6_0_get_rb_active_bitmap(adev); 1482 active_rbs |= data << 1483 ((i * adev->gfx.config.max_sh_per_se + j) * 1484 rb_bitmap_width_per_sh); 1485 } 1486 } 1487 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1488 1489 adev->gfx.config.backend_enable_mask = active_rbs; 1490 adev->gfx.config.num_rbs = hweight32(active_rbs); 1491 1492 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1493 adev->gfx.config.max_shader_engines, 16); 1494 1495 gfx_v6_0_raster_config(adev, &raster_config); 1496 1497 if (!adev->gfx.config.backend_enable_mask || 1498 adev->gfx.config.num_rbs >= num_rb_pipes) 1499 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1500 else 1501 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1502 adev->gfx.config.backend_enable_mask, 1503 num_rb_pipes); 1504 1505 /* cache the values for userspace */ 1506 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1507 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1508 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1509 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1510 RREG32(mmCC_RB_BACKEND_DISABLE); 1511 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1512 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1513 adev->gfx.config.rb_config[i][j].raster_config = 1514 RREG32(mmPA_SC_RASTER_CONFIG); 1515 } 1516 } 1517 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1518 mutex_unlock(&adev->grbm_idx_mutex); 1519 } 1520 1521 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1522 u32 bitmap) 1523 { 1524 u32 data; 1525 1526 if (!bitmap) 1527 return; 1528 1529 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1530 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1531 1532 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1533 } 1534 1535 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1536 { 1537 u32 data, mask; 1538 1539 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1540 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1541 1542 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1543 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1544 } 1545 1546 1547 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1548 { 1549 int i, j, k; 1550 u32 data, mask; 1551 u32 active_cu = 0; 1552 1553 mutex_lock(&adev->grbm_idx_mutex); 1554 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1555 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1556 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1557 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1558 active_cu = gfx_v6_0_get_cu_enabled(adev); 1559 1560 mask = 1; 1561 for (k = 0; k < 16; k++) { 1562 mask <<= k; 1563 if (active_cu & mask) { 1564 data &= ~mask; 1565 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1566 break; 1567 } 1568 } 1569 } 1570 } 1571 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1572 mutex_unlock(&adev->grbm_idx_mutex); 1573 } 1574 1575 /** 1576 * gfx_v6_0_setup_tcc() - setup which TCCs are used 1577 * 1578 * @adev: amdgpu_device pointer 1579 * 1580 * Verify whether the current GPU has any TCCs disabled, 1581 * which can happen when the GPU is harvested and some 1582 * memory channels are disabled, reducing the memory bus width. 1583 * For example, on the Radeon HD 7870 XT (Tahiti LE). 1584 * 1585 * If some TCCs are disabled, we need to make sure that 1586 * the disabled TCCs are not used, and the remaining TCCs 1587 * are used optimally. 1588 * 1589 * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels. 1590 * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used. 1591 * 1592 * For optimal performance: 1593 * - Rely on the CHAN_STEER from the golden registers table, 1594 * only skip disabled TCCs but keep the mapping order. 1595 * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing, 1596 * which performs better than using the same TCC twice. 1597 */ 1598 static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) 1599 { 1600 u32 i, tcc, tcp_addr_config, num_active_tcc = 0, num_max_active_tcc; 1601 u64 chan_steer, patched_chan_steer = 0; 1602 const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; 1603 const u32 dis_tcc_mask = 1604 amdgpu_gfx_create_bitmask(num_max_tcc) & 1605 (REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE), 1606 CGTS_TCC_DISABLE, TCC_DISABLE) | 1607 REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE), 1608 CGTS_USER_TCC_DISABLE, TCC_DISABLE)); 1609 1610 /* When no TCC is disabled, the golden registers table already has optimal TCC setup */ 1611 if (!dis_tcc_mask) 1612 return; 1613 1614 num_max_active_tcc = num_max_tcc - hweight32(dis_tcc_mask); 1615 1616 /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ 1617 chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); 1618 1619 /* Patch the TCP to TCC mapping to skip disabled TCCs */ 1620 for (i = 0; i < num_max_tcc; ++i) { 1621 tcc = (chan_steer >> (u64)(4 * i)) & 0xf; 1622 1623 if (!((1 << tcc) & dis_tcc_mask)) { 1624 /* Copy enabled TCC indices to the patched register value. */ 1625 patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); 1626 ++num_active_tcc; 1627 } 1628 1629 if (num_active_tcc == num_max_active_tcc) 1630 break; 1631 } 1632 1633 WARN_ON(num_active_tcc != num_max_active_tcc); 1634 1635 /* Patch number of TCCs used by TCPs */ 1636 tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), 1637 TCP_ADDR_CONFIG, NUM_TCC_BANKS, 1638 num_active_tcc - 1); 1639 1640 WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); 1641 WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); 1642 WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); 1643 1644 adev->gfx.config.tcc_disabled_mask = dis_tcc_mask; 1645 } 1646 1647 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1648 { 1649 adev->gfx.config.double_offchip_lds_buf = 0; 1650 } 1651 1652 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1653 { 1654 u32 gb_addr_config = 0; 1655 u32 mc_arb_ramcfg; 1656 u32 sx_debug_1; 1657 u32 hdp_host_path_cntl; 1658 u32 tmp; 1659 1660 switch (adev->asic_type) { 1661 case CHIP_TAHITI: 1662 adev->gfx.config.max_shader_engines = 2; 1663 adev->gfx.config.max_tile_pipes = 12; 1664 adev->gfx.config.max_cu_per_sh = 8; 1665 adev->gfx.config.max_sh_per_se = 2; 1666 adev->gfx.config.max_backends_per_se = 4; 1667 adev->gfx.config.max_texture_channel_caches = 12; 1668 adev->gfx.config.max_gprs = 256; 1669 adev->gfx.config.max_gs_threads = 32; 1670 adev->gfx.config.max_hw_contexts = 8; 1671 1672 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1673 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1674 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1675 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1676 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1677 break; 1678 case CHIP_PITCAIRN: 1679 adev->gfx.config.max_shader_engines = 2; 1680 adev->gfx.config.max_tile_pipes = 8; 1681 adev->gfx.config.max_cu_per_sh = 5; 1682 adev->gfx.config.max_sh_per_se = 2; 1683 adev->gfx.config.max_backends_per_se = 4; 1684 adev->gfx.config.max_texture_channel_caches = 8; 1685 adev->gfx.config.max_gprs = 256; 1686 adev->gfx.config.max_gs_threads = 32; 1687 adev->gfx.config.max_hw_contexts = 8; 1688 1689 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1690 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1691 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1692 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1693 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1694 break; 1695 case CHIP_VERDE: 1696 adev->gfx.config.max_shader_engines = 1; 1697 adev->gfx.config.max_tile_pipes = 4; 1698 adev->gfx.config.max_cu_per_sh = 5; 1699 adev->gfx.config.max_sh_per_se = 2; 1700 adev->gfx.config.max_backends_per_se = 4; 1701 adev->gfx.config.max_texture_channel_caches = 4; 1702 adev->gfx.config.max_gprs = 256; 1703 adev->gfx.config.max_gs_threads = 32; 1704 adev->gfx.config.max_hw_contexts = 8; 1705 1706 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1707 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1708 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1709 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1710 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1711 break; 1712 case CHIP_OLAND: 1713 adev->gfx.config.max_shader_engines = 1; 1714 adev->gfx.config.max_tile_pipes = 4; 1715 adev->gfx.config.max_cu_per_sh = 6; 1716 adev->gfx.config.max_sh_per_se = 1; 1717 adev->gfx.config.max_backends_per_se = 2; 1718 adev->gfx.config.max_texture_channel_caches = 4; 1719 adev->gfx.config.max_gprs = 256; 1720 adev->gfx.config.max_gs_threads = 16; 1721 adev->gfx.config.max_hw_contexts = 8; 1722 1723 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1724 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1725 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1726 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1727 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1728 break; 1729 case CHIP_HAINAN: 1730 adev->gfx.config.max_shader_engines = 1; 1731 adev->gfx.config.max_tile_pipes = 4; 1732 adev->gfx.config.max_cu_per_sh = 5; 1733 adev->gfx.config.max_sh_per_se = 1; 1734 adev->gfx.config.max_backends_per_se = 1; 1735 adev->gfx.config.max_texture_channel_caches = 2; 1736 adev->gfx.config.max_gprs = 256; 1737 adev->gfx.config.max_gs_threads = 16; 1738 adev->gfx.config.max_hw_contexts = 8; 1739 1740 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1741 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1742 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1743 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1744 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1745 break; 1746 default: 1747 dev_warn(adev->dev, "Unsupported asic_type 0x%08x\n", adev->asic_type); 1748 return; 1749 } 1750 1751 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1752 WREG32(mmSRBM_INT_CNTL, 1); 1753 WREG32(mmSRBM_INT_ACK, 1); 1754 1755 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1756 1757 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1758 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1759 1760 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1761 adev->gfx.config.mem_max_burst_length_bytes = 256; 1762 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1763 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1764 if (adev->gfx.config.mem_row_size_in_kb > 4) 1765 adev->gfx.config.mem_row_size_in_kb = 4; 1766 adev->gfx.config.shader_engine_tile_size = 32; 1767 adev->gfx.config.num_gpus = 1; 1768 adev->gfx.config.multi_gpu_tile_size = 64; 1769 1770 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1771 switch (adev->gfx.config.mem_row_size_in_kb) { 1772 case 1: 1773 default: 1774 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1775 break; 1776 case 2: 1777 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1778 break; 1779 case 4: 1780 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1781 break; 1782 } 1783 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1784 if (adev->gfx.config.max_shader_engines == 2) 1785 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1786 adev->gfx.config.gb_addr_config = gb_addr_config; 1787 1788 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1789 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1790 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1791 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1792 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1793 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1794 1795 #if 0 1796 if (adev->has_uvd) { 1797 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1798 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1799 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1800 } 1801 #endif 1802 gfx_v6_0_tiling_mode_table_init(adev); 1803 1804 gfx_v6_0_setup_rb(adev); 1805 gfx_v6_0_setup_tcc(adev); 1806 1807 gfx_v6_0_setup_spi(adev); 1808 1809 gfx_v6_0_get_cu_info(adev); 1810 gfx_v6_0_config_init(adev); 1811 1812 WREG32(mmCP_QUEUE_THRESHOLDS, 1813 ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1814 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1815 1816 /* set HW defaults for 3D engine */ 1817 WREG32(mmCP_MEQ_THRESHOLDS, 1818 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1819 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1820 1821 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1822 WREG32(mmSX_DEBUG_1, sx_debug_1); 1823 1824 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1825 1826 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1827 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1828 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1829 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1830 1831 WREG32(mmVGT_NUM_INSTANCES, 1); 1832 WREG32(mmCP_PERFMON_CNTL, 0); 1833 WREG32(mmSQ_CONFIG, 0); 1834 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1835 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1836 1837 WREG32(mmVGT_CACHE_INVALIDATION, 1838 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1839 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1840 1841 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1842 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1843 1844 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1845 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1846 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1847 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1848 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1849 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1850 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1851 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1852 1853 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1854 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1855 1856 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1857 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1858 1859 udelay(50); 1860 } 1861 1862 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1863 { 1864 struct amdgpu_device *adev = ring->adev; 1865 uint32_t tmp = 0; 1866 unsigned i; 1867 int r; 1868 1869 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1870 1871 r = amdgpu_ring_alloc(ring, 3); 1872 if (r) 1873 return r; 1874 1875 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1876 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); 1877 amdgpu_ring_write(ring, 0xDEADBEEF); 1878 amdgpu_ring_commit(ring); 1879 1880 for (i = 0; i < adev->usec_timeout; i++) { 1881 tmp = RREG32(mmSCRATCH_REG0); 1882 if (tmp == 0xDEADBEEF) 1883 break; 1884 udelay(1); 1885 } 1886 1887 if (i >= adev->usec_timeout) 1888 r = -ETIMEDOUT; 1889 return r; 1890 } 1891 1892 static void gfx_v6_0_ring_emit_event_write(struct amdgpu_ring *ring, 1893 uint32_t event_type, 1894 uint32_t event_index) 1895 { 1896 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1897 amdgpu_ring_write(ring, EVENT_TYPE(event_type) | 1898 EVENT_INDEX(event_index)); 1899 } 1900 1901 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1902 u64 seq, unsigned flags) 1903 { 1904 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1905 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1906 /* flush read cache over gart */ 1907 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1908 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1909 amdgpu_ring_write(ring, 0); 1910 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1911 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1912 PACKET3_TC_ACTION_ENA | 1913 PACKET3_SH_KCACHE_ACTION_ENA | 1914 PACKET3_SH_ICACHE_ACTION_ENA); 1915 amdgpu_ring_write(ring, 0xFFFFFFFF); 1916 amdgpu_ring_write(ring, 0); 1917 amdgpu_ring_write(ring, 10); /* poll interval */ 1918 /* EVENT_WRITE_EOP - flush caches, send int */ 1919 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1920 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1921 amdgpu_ring_write(ring, addr & 0xfffffffc); 1922 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1923 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1924 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1925 amdgpu_ring_write(ring, lower_32_bits(seq)); 1926 amdgpu_ring_write(ring, upper_32_bits(seq)); 1927 } 1928 1929 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1930 struct amdgpu_job *job, 1931 struct amdgpu_ib *ib, 1932 uint32_t flags) 1933 { 1934 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1935 u32 header, control = 0; 1936 1937 if (ib->flags & AMDGPU_IB_FLAG_CE) 1938 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1939 else 1940 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1941 1942 control |= ib->length_dw | (vmid << 24); 1943 1944 amdgpu_ring_write(ring, header); 1945 amdgpu_ring_write(ring, 1946 #ifdef __BIG_ENDIAN 1947 (2 << 0) | 1948 #endif 1949 (ib->gpu_addr & 0xFFFFFFFC)); 1950 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1951 amdgpu_ring_write(ring, control); 1952 } 1953 1954 /** 1955 * gfx_v6_0_ring_test_ib - basic ring IB test 1956 * 1957 * @ring: amdgpu_ring structure holding ring information 1958 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1959 * 1960 * Allocate an IB and execute it on the gfx ring (SI). 1961 * Provides a basic gfx ring test to verify that IBs are working. 1962 * Returns 0 on success, error on failure. 1963 */ 1964 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1965 { 1966 struct amdgpu_device *adev = ring->adev; 1967 struct dma_fence *f = NULL; 1968 struct amdgpu_ib ib; 1969 uint32_t tmp = 0; 1970 long r; 1971 1972 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1973 memset(&ib, 0, sizeof(ib)); 1974 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1975 if (r) 1976 return r; 1977 1978 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1979 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; 1980 ib.ptr[2] = 0xDEADBEEF; 1981 ib.length_dw = 3; 1982 1983 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1984 if (r) 1985 goto error; 1986 1987 r = dma_fence_wait_timeout(f, false, timeout); 1988 if (r == 0) { 1989 r = -ETIMEDOUT; 1990 goto error; 1991 } else if (r < 0) { 1992 goto error; 1993 } 1994 tmp = RREG32(mmSCRATCH_REG0); 1995 if (tmp == 0xDEADBEEF) 1996 r = 0; 1997 else 1998 r = -EINVAL; 1999 2000 error: 2001 amdgpu_ib_free(&ib, NULL); 2002 dma_fence_put(f); 2003 return r; 2004 } 2005 2006 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2007 { 2008 if (enable) { 2009 WREG32(mmCP_ME_CNTL, 0); 2010 } else { 2011 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2012 CP_ME_CNTL__PFP_HALT_MASK | 2013 CP_ME_CNTL__CE_HALT_MASK)); 2014 WREG32(mmSCRATCH_UMSK, 0); 2015 } 2016 udelay(50); 2017 } 2018 2019 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2020 { 2021 unsigned i; 2022 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2023 const struct gfx_firmware_header_v1_0 *ce_hdr; 2024 const struct gfx_firmware_header_v1_0 *me_hdr; 2025 const __le32 *fw_data; 2026 u32 fw_size; 2027 2028 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2029 return -EINVAL; 2030 2031 gfx_v6_0_cp_gfx_enable(adev, false); 2032 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2033 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2034 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2035 2036 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2037 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2038 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2039 2040 /* PFP */ 2041 fw_data = (const __le32 *) 2042 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2043 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2044 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2045 for (i = 0; i < fw_size; i++) 2046 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2047 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2048 2049 /* CE */ 2050 fw_data = (const __le32 *) 2051 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2052 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2053 WREG32(mmCP_CE_UCODE_ADDR, 0); 2054 for (i = 0; i < fw_size; i++) 2055 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2056 WREG32(mmCP_CE_UCODE_ADDR, 0); 2057 2058 /* ME */ 2059 fw_data = (const __be32 *) 2060 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2061 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2062 WREG32(mmCP_ME_RAM_WADDR, 0); 2063 for (i = 0; i < fw_size; i++) 2064 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2065 WREG32(mmCP_ME_RAM_WADDR, 0); 2066 2067 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2068 WREG32(mmCP_CE_UCODE_ADDR, 0); 2069 WREG32(mmCP_ME_RAM_WADDR, 0); 2070 WREG32(mmCP_ME_RAM_RADDR, 0); 2071 return 0; 2072 } 2073 2074 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2075 { 2076 const struct cs_section_def *sect = NULL; 2077 const struct cs_extent_def *ext = NULL; 2078 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2079 int r, i; 2080 2081 r = amdgpu_ring_alloc(ring, 7 + 4); 2082 if (r) { 2083 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2084 return r; 2085 } 2086 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2087 amdgpu_ring_write(ring, 0x1); 2088 amdgpu_ring_write(ring, 0x0); 2089 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2090 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2091 amdgpu_ring_write(ring, 0); 2092 amdgpu_ring_write(ring, 0); 2093 2094 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2095 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2096 amdgpu_ring_write(ring, 0xc000); 2097 amdgpu_ring_write(ring, 0xe000); 2098 amdgpu_ring_commit(ring); 2099 2100 gfx_v6_0_cp_gfx_enable(adev, true); 2101 2102 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2103 if (r) { 2104 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2105 return r; 2106 } 2107 2108 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2109 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2110 2111 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2112 for (ext = sect->section; ext->extent != NULL; ++ext) { 2113 if (sect->id == SECT_CONTEXT) { 2114 amdgpu_ring_write(ring, 2115 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2116 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2117 for (i = 0; i < ext->reg_count; i++) 2118 amdgpu_ring_write(ring, ext->extent[i]); 2119 } 2120 } 2121 } 2122 2123 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2124 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2125 2126 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2127 amdgpu_ring_write(ring, 0); 2128 2129 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2130 amdgpu_ring_write(ring, 0x00000316); 2131 amdgpu_ring_write(ring, 0x0000000e); 2132 amdgpu_ring_write(ring, 0x00000010); 2133 2134 amdgpu_ring_commit(ring); 2135 2136 return 0; 2137 } 2138 2139 /** 2140 * gfx_v6_0_cp_gfx_resume() - Initialize CP rings 2141 * 2142 * @adev: amdgpu_device pointer 2143 * 2144 * In GFX6 GPUs, compute takes the same CP path as graphics. 2145 * CP ME command parser executes packets for each ring buffer: 2146 * RB0 supports graphics, RB1 and RB2 are compute only. 2147 * Initialize all three rings before calling gfx_v6_0_cp_gfx_start() 2148 * to make sure they are all in a sane state before execution starts. 2149 */ 2150 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2151 { 2152 struct amdgpu_ring *ring; 2153 u32 tmp; 2154 u32 rb_bufsz; 2155 int r; 2156 int i; 2157 u64 rptr_addr; 2158 2159 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2160 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2161 2162 /* Set the write pointer delay */ 2163 WREG32(mmCP_RB_WPTR_DELAY, 0); 2164 2165 WREG32(mmCP_DEBUG, 0); 2166 WREG32(mmSCRATCH_ADDR, 0); 2167 2168 /* ring 0 - compute and gfx */ 2169 ring = &adev->gfx.gfx_ring[0]; 2170 *ring->wptr_cpu_addr = 0; 2171 *ring->rptr_cpu_addr = 0; 2172 amdgpu_ring_clear_ring(ring); 2173 2174 /* Set ring buffer size */ 2175 rb_bufsz = order_base_2(ring->ring_size / 8); 2176 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2177 2178 #ifdef __BIG_ENDIAN 2179 tmp |= BUF_SWAP_32BIT; 2180 #endif 2181 WREG32(mmCP_RB0_CNTL, tmp); 2182 2183 /* Initialize the ring buffer's read and write pointers */ 2184 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2185 ring->wptr = 0; 2186 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2187 WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); 2188 2189 /* set the wb address whether it's enabled or not */ 2190 rptr_addr = ring->rptr_gpu_addr; 2191 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2192 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2193 2194 WREG32(mmSCRATCH_UMSK, 0); 2195 2196 mdelay(1); 2197 WREG32(mmCP_RB0_CNTL, tmp); 2198 2199 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2200 2201 /* ring 1 - compute only */ 2202 if (adev->gfx.num_compute_rings >= 1) { 2203 ring = &adev->gfx.compute_ring[0]; 2204 *ring->wptr_cpu_addr = 0; 2205 *ring->rptr_cpu_addr = 0; 2206 amdgpu_ring_clear_ring(ring); 2207 2208 rb_bufsz = order_base_2(ring->ring_size / 8); 2209 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; 2210 #ifdef __BIG_ENDIAN 2211 tmp |= BUF_SWAP_32BIT; 2212 #endif 2213 WREG32(mmCP_RB1_CNTL, tmp); 2214 2215 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2216 ring->wptr = 0; 2217 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2218 WREG32(mmCP_RB1_RPTR, lower_32_bits(ring->wptr)); 2219 2220 rptr_addr = ring->rptr_gpu_addr; 2221 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2222 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2223 2224 mdelay(1); 2225 WREG32(mmCP_RB1_CNTL, tmp); 2226 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2227 } 2228 2229 /* ring 2 - compute only */ 2230 if (adev->gfx.num_compute_rings >= 2) { 2231 ring = &adev->gfx.compute_ring[1]; 2232 *ring->wptr_cpu_addr = 0; 2233 *ring->rptr_cpu_addr = 0; 2234 amdgpu_ring_clear_ring(ring); 2235 2236 rb_bufsz = order_base_2(ring->ring_size / 8); 2237 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; 2238 #ifdef __BIG_ENDIAN 2239 tmp |= BUF_SWAP_32BIT; 2240 #endif 2241 WREG32(mmCP_RB2_CNTL, tmp); 2242 2243 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2244 ring->wptr = 0; 2245 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2246 WREG32(mmCP_RB2_RPTR, lower_32_bits(ring->wptr)); 2247 2248 rptr_addr = ring->rptr_gpu_addr; 2249 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2250 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2251 2252 mdelay(1); 2253 WREG32(mmCP_RB2_CNTL, tmp); 2254 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2255 } 2256 2257 /* start the rings */ 2258 gfx_v6_0_cp_gfx_start(adev); 2259 2260 /* Wait for the initial packets to finish, run gfx ring test */ 2261 r = amdgpu_ring_test_helper(&adev->gfx.gfx_ring[0]); 2262 if (r) 2263 return r; 2264 2265 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2266 ring = &adev->gfx.compute_ring[i]; 2267 2268 r = amdgpu_ring_alloc(ring, 2); 2269 if (r) 2270 return r; 2271 2272 amdgpu_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 2273 amdgpu_ring_write(ring, 0); 2274 amdgpu_ring_commit(ring); 2275 2276 r = amdgpu_ring_test_helper(ring); 2277 if (r) 2278 return r; 2279 } 2280 2281 return 0; 2282 } 2283 2284 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2285 { 2286 return *ring->rptr_cpu_addr; 2287 } 2288 2289 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2290 { 2291 struct amdgpu_device *adev = ring->adev; 2292 2293 if (ring == &adev->gfx.gfx_ring[0]) 2294 return RREG32(mmCP_RB0_WPTR); 2295 else if (ring == &adev->gfx.compute_ring[0]) 2296 return RREG32(mmCP_RB1_WPTR); 2297 else if (ring == &adev->gfx.compute_ring[1]) 2298 return RREG32(mmCP_RB2_WPTR); 2299 else 2300 return 0; 2301 } 2302 2303 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2304 { 2305 struct amdgpu_device *adev = ring->adev; 2306 2307 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2308 (void)RREG32(mmCP_RB0_WPTR); 2309 } 2310 2311 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2312 { 2313 struct amdgpu_device *adev = ring->adev; 2314 2315 if (ring == &adev->gfx.compute_ring[0]) { 2316 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2317 (void)RREG32(mmCP_RB1_WPTR); 2318 } else if (ring == &adev->gfx.compute_ring[1]) { 2319 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2320 (void)RREG32(mmCP_RB2_WPTR); 2321 } 2322 2323 } 2324 2325 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2326 { 2327 gfx_v6_0_cp_gfx_enable(adev, enable); 2328 } 2329 2330 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2331 { 2332 return gfx_v6_0_cp_gfx_load_microcode(adev); 2333 } 2334 2335 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2336 bool enable) 2337 { 2338 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2339 u32 mask; 2340 int i; 2341 2342 if (enable) 2343 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2344 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2345 else 2346 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2347 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2348 WREG32(mmCP_INT_CNTL_RING0, tmp); 2349 2350 if (!enable) { 2351 /* read a gfx register */ 2352 tmp = RREG32(mmDB_DEPTH_INFO); 2353 2354 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2355 for (i = 0; i < adev->usec_timeout; i++) { 2356 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2357 break; 2358 udelay(1); 2359 } 2360 } 2361 } 2362 2363 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2364 { 2365 int r; 2366 2367 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2368 2369 r = gfx_v6_0_cp_load_microcode(adev); 2370 if (r) 2371 return r; 2372 2373 r = gfx_v6_0_cp_gfx_resume(adev); 2374 if (r) 2375 return r; 2376 2377 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2378 2379 return 0; 2380 } 2381 2382 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2383 { 2384 int usepfp = 1; 2385 uint32_t seq = ring->fence_drv.sync_seq; 2386 uint64_t addr = ring->fence_drv.gpu_addr; 2387 2388 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2389 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2390 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2391 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2392 amdgpu_ring_write(ring, addr & 0xfffffffc); 2393 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2394 amdgpu_ring_write(ring, seq); 2395 amdgpu_ring_write(ring, 0xffffffff); 2396 amdgpu_ring_write(ring, 4); /* poll interval */ 2397 } 2398 2399 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2400 unsigned vmid, uint64_t pd_addr) 2401 { 2402 int usepfp = 1; 2403 2404 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2405 2406 /* wait for the invalidate to complete */ 2407 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2408 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2409 WAIT_REG_MEM_ENGINE(0))); /* me */ 2410 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2411 amdgpu_ring_write(ring, 0); 2412 amdgpu_ring_write(ring, 0); /* ref */ 2413 amdgpu_ring_write(ring, 0); /* mask */ 2414 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2415 2416 if (usepfp) { 2417 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2418 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2419 amdgpu_ring_write(ring, 0x0); 2420 } 2421 } 2422 2423 static unsigned int gfx_v6_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 2424 uint64_t gpu_addr) 2425 { 2426 unsigned int ret; 2427 2428 /* 2429 * Discard following DWs after this packet when gpu_addr==0 2430 * The packet is only 4 DW on GFX6 (as opposed to GFX7+). 2431 */ 2432 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 2)); 2433 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 2434 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 2435 ret = ring->wptr & ring->buf_mask; 2436 /* patch dummy value later */ 2437 amdgpu_ring_write(ring, 0); 2438 return ret; 2439 } 2440 2441 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2442 uint32_t reg, uint32_t val) 2443 { 2444 int usepfp = 1; 2445 2446 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2447 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2448 WRITE_DATA_DST_SEL(0))); 2449 amdgpu_ring_write(ring, reg); 2450 amdgpu_ring_write(ring, 0); 2451 amdgpu_ring_write(ring, val); 2452 } 2453 2454 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2455 { 2456 const u32 *src_ptr; 2457 u32 *dst_ptr; 2458 u32 dws; 2459 u64 reg_list_mc_addr; 2460 const struct cs_section_def *cs_data; 2461 int r; 2462 2463 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2464 adev->gfx.rlc.reg_list_size = 2465 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2466 2467 adev->gfx.rlc.cs_data = si_cs_data; 2468 src_ptr = adev->gfx.rlc.reg_list; 2469 dws = adev->gfx.rlc.reg_list_size; 2470 cs_data = adev->gfx.rlc.cs_data; 2471 2472 if (src_ptr) { 2473 /* init save restore block */ 2474 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2475 if (r) 2476 return r; 2477 } 2478 2479 if (cs_data) { 2480 /* clear state block */ 2481 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2482 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2483 2484 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2485 AMDGPU_GEM_DOMAIN_VRAM | 2486 AMDGPU_GEM_DOMAIN_GTT, 2487 &adev->gfx.rlc.clear_state_obj, 2488 &adev->gfx.rlc.clear_state_gpu_addr, 2489 (void **)&adev->gfx.rlc.cs_ptr); 2490 if (r) { 2491 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2492 amdgpu_gfx_rlc_fini(adev); 2493 return r; 2494 } 2495 2496 /* set up the cs buffer */ 2497 dst_ptr = adev->gfx.rlc.cs_ptr; 2498 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2499 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2500 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2501 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2502 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2503 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2504 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2505 } 2506 2507 return 0; 2508 } 2509 2510 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2511 { 2512 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2513 2514 if (!enable) { 2515 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2516 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2517 } 2518 } 2519 2520 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2521 { 2522 int i; 2523 2524 for (i = 0; i < adev->usec_timeout; i++) { 2525 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2526 break; 2527 udelay(1); 2528 } 2529 2530 for (i = 0; i < adev->usec_timeout; i++) { 2531 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2532 break; 2533 udelay(1); 2534 } 2535 } 2536 2537 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2538 { 2539 u32 tmp; 2540 2541 tmp = RREG32(mmRLC_CNTL); 2542 if (tmp != rlc) 2543 WREG32(mmRLC_CNTL, rlc); 2544 } 2545 2546 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2547 { 2548 u32 data, orig; 2549 2550 orig = data = RREG32(mmRLC_CNTL); 2551 2552 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2553 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2554 WREG32(mmRLC_CNTL, data); 2555 2556 gfx_v6_0_wait_for_rlc_serdes(adev); 2557 } 2558 2559 return orig; 2560 } 2561 2562 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2563 { 2564 WREG32(mmRLC_CNTL, 0); 2565 2566 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2567 gfx_v6_0_wait_for_rlc_serdes(adev); 2568 } 2569 2570 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2571 { 2572 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2573 2574 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2575 2576 udelay(50); 2577 } 2578 2579 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2580 { 2581 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2582 udelay(50); 2583 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2584 udelay(50); 2585 } 2586 2587 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2588 { 2589 u32 tmp; 2590 2591 /* Enable LBPW only for DDR3 */ 2592 tmp = RREG32(mmMC_SEQ_MISC0); 2593 if ((tmp & 0xF0000000) == 0xB0000000) 2594 return true; 2595 return false; 2596 } 2597 2598 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2599 { 2600 } 2601 2602 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2603 { 2604 u32 i; 2605 const struct rlc_firmware_header_v1_0 *hdr; 2606 const __le32 *fw_data; 2607 u32 fw_size; 2608 2609 2610 if (!adev->gfx.rlc_fw) 2611 return -EINVAL; 2612 2613 adev->gfx.rlc.funcs->stop(adev); 2614 adev->gfx.rlc.funcs->reset(adev); 2615 gfx_v6_0_init_pg(adev); 2616 gfx_v6_0_init_cg(adev); 2617 2618 WREG32(mmRLC_RL_BASE, 0); 2619 WREG32(mmRLC_RL_SIZE, 0); 2620 WREG32(mmRLC_LB_CNTL, 0); 2621 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2622 WREG32(mmRLC_LB_CNTR_INIT, 0); 2623 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2624 2625 WREG32(mmRLC_MC_CNTL, 0); 2626 WREG32(mmRLC_UCODE_CNTL, 0); 2627 2628 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2629 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2630 fw_data = (const __le32 *) 2631 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2632 2633 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2634 2635 for (i = 0; i < fw_size; i++) { 2636 WREG32(mmRLC_UCODE_ADDR, i); 2637 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2638 } 2639 WREG32(mmRLC_UCODE_ADDR, 0); 2640 2641 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2642 adev->gfx.rlc.funcs->start(adev); 2643 2644 return 0; 2645 } 2646 2647 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2648 { 2649 u32 data, orig, tmp; 2650 2651 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2652 2653 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2654 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2655 2656 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2657 2658 tmp = gfx_v6_0_halt_rlc(adev); 2659 2660 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2661 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2662 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2663 2664 gfx_v6_0_wait_for_rlc_serdes(adev); 2665 gfx_v6_0_update_rlc(adev, tmp); 2666 2667 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2668 2669 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2670 } else { 2671 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2672 2673 RREG32(mmCB_CGTT_SCLK_CTRL); 2674 RREG32(mmCB_CGTT_SCLK_CTRL); 2675 RREG32(mmCB_CGTT_SCLK_CTRL); 2676 RREG32(mmCB_CGTT_SCLK_CTRL); 2677 2678 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2679 } 2680 2681 if (orig != data) 2682 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2683 2684 } 2685 2686 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2687 { 2688 2689 u32 data, orig, tmp = 0; 2690 2691 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2692 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2693 data = 0x96940200; 2694 if (orig != data) 2695 WREG32(mmCGTS_SM_CTRL_REG, data); 2696 2697 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2698 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2699 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2700 if (orig != data) 2701 WREG32(mmCP_MEM_SLP_CNTL, data); 2702 } 2703 2704 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2705 data &= 0xffffffc0; 2706 if (orig != data) 2707 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2708 2709 tmp = gfx_v6_0_halt_rlc(adev); 2710 2711 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2712 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2713 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2714 2715 gfx_v6_0_update_rlc(adev, tmp); 2716 } else { 2717 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2718 data |= 0x00000003; 2719 if (orig != data) 2720 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2721 2722 data = RREG32(mmCP_MEM_SLP_CNTL); 2723 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2724 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2725 WREG32(mmCP_MEM_SLP_CNTL, data); 2726 } 2727 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2728 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2729 if (orig != data) 2730 WREG32(mmCGTS_SM_CTRL_REG, data); 2731 2732 tmp = gfx_v6_0_halt_rlc(adev); 2733 2734 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2735 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2736 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2737 2738 gfx_v6_0_update_rlc(adev, tmp); 2739 } 2740 } 2741 /* 2742 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2743 bool enable) 2744 { 2745 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2746 if (enable) { 2747 gfx_v6_0_enable_mgcg(adev, true); 2748 gfx_v6_0_enable_cgcg(adev, true); 2749 } else { 2750 gfx_v6_0_enable_cgcg(adev, false); 2751 gfx_v6_0_enable_mgcg(adev, false); 2752 } 2753 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2754 } 2755 */ 2756 2757 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2758 bool enable) 2759 { 2760 } 2761 2762 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2763 bool enable) 2764 { 2765 } 2766 2767 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2768 { 2769 u32 data, orig; 2770 2771 orig = data = RREG32(mmRLC_PG_CNTL); 2772 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2773 data &= ~0x8000; 2774 else 2775 data |= 0x8000; 2776 if (orig != data) 2777 WREG32(mmRLC_PG_CNTL, data); 2778 } 2779 2780 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2781 { 2782 } 2783 /* 2784 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2785 { 2786 const __le32 *fw_data; 2787 volatile u32 *dst_ptr; 2788 int me, i, max_me = 4; 2789 u32 bo_offset = 0; 2790 u32 table_offset, table_size; 2791 2792 if (adev->asic_type == CHIP_KAVERI) 2793 max_me = 5; 2794 2795 if (adev->gfx.rlc.cp_table_ptr == NULL) 2796 return; 2797 2798 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2799 for (me = 0; me < max_me; me++) { 2800 if (me == 0) { 2801 const struct gfx_firmware_header_v1_0 *hdr = 2802 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2803 fw_data = (const __le32 *) 2804 (adev->gfx.ce_fw->data + 2805 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2806 table_offset = le32_to_cpu(hdr->jt_offset); 2807 table_size = le32_to_cpu(hdr->jt_size); 2808 } else if (me == 1) { 2809 const struct gfx_firmware_header_v1_0 *hdr = 2810 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2811 fw_data = (const __le32 *) 2812 (adev->gfx.pfp_fw->data + 2813 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2814 table_offset = le32_to_cpu(hdr->jt_offset); 2815 table_size = le32_to_cpu(hdr->jt_size); 2816 } else if (me == 2) { 2817 const struct gfx_firmware_header_v1_0 *hdr = 2818 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2819 fw_data = (const __le32 *) 2820 (adev->gfx.me_fw->data + 2821 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2822 table_offset = le32_to_cpu(hdr->jt_offset); 2823 table_size = le32_to_cpu(hdr->jt_size); 2824 } else if (me == 3) { 2825 const struct gfx_firmware_header_v1_0 *hdr = 2826 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2827 fw_data = (const __le32 *) 2828 (adev->gfx.mec_fw->data + 2829 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2830 table_offset = le32_to_cpu(hdr->jt_offset); 2831 table_size = le32_to_cpu(hdr->jt_size); 2832 } else { 2833 const struct gfx_firmware_header_v1_0 *hdr = 2834 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2835 fw_data = (const __le32 *) 2836 (adev->gfx.mec2_fw->data + 2837 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2838 table_offset = le32_to_cpu(hdr->jt_offset); 2839 table_size = le32_to_cpu(hdr->jt_size); 2840 } 2841 2842 for (i = 0; i < table_size; i ++) { 2843 dst_ptr[bo_offset + i] = 2844 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2845 } 2846 2847 bo_offset += table_size; 2848 } 2849 } 2850 */ 2851 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2852 bool enable) 2853 { 2854 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2855 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2856 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2857 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2858 } else { 2859 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2860 (void)RREG32(mmDB_RENDER_CONTROL); 2861 } 2862 } 2863 2864 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2865 { 2866 u32 tmp; 2867 2868 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2869 2870 tmp = RREG32(mmRLC_MAX_PG_CU); 2871 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2872 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2873 WREG32(mmRLC_MAX_PG_CU, tmp); 2874 } 2875 2876 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2877 bool enable) 2878 { 2879 u32 data, orig; 2880 2881 orig = data = RREG32(mmRLC_PG_CNTL); 2882 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2883 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2884 else 2885 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2886 if (orig != data) 2887 WREG32(mmRLC_PG_CNTL, data); 2888 } 2889 2890 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2891 bool enable) 2892 { 2893 u32 data, orig; 2894 2895 orig = data = RREG32(mmRLC_PG_CNTL); 2896 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2897 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2898 else 2899 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2900 if (orig != data) 2901 WREG32(mmRLC_PG_CNTL, data); 2902 } 2903 2904 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2905 { 2906 u32 tmp; 2907 2908 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2909 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2910 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2911 2912 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2913 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2914 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2915 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2916 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2917 } 2918 2919 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2920 { 2921 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2922 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2923 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2924 } 2925 2926 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2927 { 2928 u32 count = 0; 2929 const struct cs_section_def *sect = NULL; 2930 const struct cs_extent_def *ext = NULL; 2931 2932 if (adev->gfx.rlc.cs_data == NULL) 2933 return 0; 2934 2935 /* begin clear state */ 2936 count += 2; 2937 /* context control state */ 2938 count += 3; 2939 2940 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2941 for (ext = sect->section; ext->extent != NULL; ++ext) { 2942 if (sect->id == SECT_CONTEXT) 2943 count += 2 + ext->reg_count; 2944 else 2945 return 0; 2946 } 2947 } 2948 /* pa_sc_raster_config */ 2949 count += 3; 2950 /* end clear state */ 2951 count += 2; 2952 /* clear state */ 2953 count += 2; 2954 2955 return count; 2956 } 2957 2958 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 2959 { 2960 u32 count = 0; 2961 2962 if (adev->gfx.rlc.cs_data == NULL) 2963 return; 2964 if (buffer == NULL) 2965 return; 2966 2967 count = amdgpu_gfx_csb_preamble_start(buffer); 2968 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 2969 2970 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2971 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2972 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2973 2974 amdgpu_gfx_csb_preamble_end(buffer, count); 2975 } 2976 2977 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2978 { 2979 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2980 AMD_PG_SUPPORT_GFX_SMG | 2981 AMD_PG_SUPPORT_GFX_DMG | 2982 AMD_PG_SUPPORT_CP | 2983 AMD_PG_SUPPORT_GDS | 2984 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2985 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2986 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2987 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2988 gfx_v6_0_init_gfx_cgpg(adev); 2989 gfx_v6_0_enable_cp_pg(adev, true); 2990 gfx_v6_0_enable_gds_pg(adev, true); 2991 } else { 2992 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2993 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2994 2995 } 2996 gfx_v6_0_init_ao_cu_mask(adev); 2997 gfx_v6_0_update_gfx_pg(adev, true); 2998 } else { 2999 3000 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3001 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 3002 } 3003 } 3004 3005 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 3006 { 3007 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3008 AMD_PG_SUPPORT_GFX_SMG | 3009 AMD_PG_SUPPORT_GFX_DMG | 3010 AMD_PG_SUPPORT_CP | 3011 AMD_PG_SUPPORT_GDS | 3012 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3013 gfx_v6_0_update_gfx_pg(adev, false); 3014 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3015 gfx_v6_0_enable_cp_pg(adev, false); 3016 gfx_v6_0_enable_gds_pg(adev, false); 3017 } 3018 } 3019 } 3020 3021 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3022 { 3023 uint64_t clock; 3024 3025 mutex_lock(&adev->gfx.gpu_clock_mutex); 3026 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3027 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3028 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3029 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3030 return clock; 3031 } 3032 3033 static void gfx_v6_0_ring_emit_sb(struct amdgpu_ring *ring) 3034 { 3035 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3036 amdgpu_ring_write(ring, 0); 3037 } 3038 3039 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3040 { 3041 u32 dw2 = 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3042 3043 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3044 gfx_v6_0_ring_emit_event_write(ring, VS_PARTIAL_FLUSH, 4); 3045 gfx_v6_0_ring_emit_event_write(ring, VGT_FLUSH, 0); 3046 3047 /* set load_global_config (load_global_uconfig doesn't exist on GFX6) */ 3048 dw2 |= 0x1; 3049 /* set load_cs_sh_regs */ 3050 dw2 |= 0x01000000; 3051 /* set load_per_context_state & load_gfx_sh_regs */ 3052 dw2 |= 0x10002; 3053 } 3054 3055 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3056 amdgpu_ring_write(ring, dw2); 3057 amdgpu_ring_write(ring, 0); 3058 } 3059 3060 3061 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 3062 { 3063 WREG32(mmSQ_IND_INDEX, 3064 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3065 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3066 (address << SQ_IND_INDEX__INDEX__SHIFT) | 3067 (SQ_IND_INDEX__FORCE_READ_MASK)); 3068 return RREG32(mmSQ_IND_DATA); 3069 } 3070 3071 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3072 uint32_t wave, uint32_t thread, 3073 uint32_t regno, uint32_t num, uint32_t *out) 3074 { 3075 WREG32(mmSQ_IND_INDEX, 3076 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3077 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3078 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3079 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3080 (SQ_IND_INDEX__FORCE_READ_MASK) | 3081 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3082 while (num--) 3083 *(out++) = RREG32(mmSQ_IND_DATA); 3084 } 3085 3086 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3087 { 3088 /* type 0 wave data */ 3089 dst[(*no_fields)++] = 0; 3090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3091 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3092 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3093 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3094 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3096 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3097 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3100 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3101 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3104 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3105 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3106 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3107 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3108 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 3109 } 3110 3111 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 3112 uint32_t wave, uint32_t start, 3113 uint32_t size, uint32_t *dst) 3114 { 3115 wave_read_regs( 3116 adev, simd, wave, 0, 3117 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3118 } 3119 3120 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3121 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3122 { 3123 drm_info(adev_to_drm(adev), "Not implemented\n"); 3124 } 3125 3126 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3127 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3128 .select_se_sh = &gfx_v6_0_select_se_sh, 3129 .read_wave_data = &gfx_v6_0_read_wave_data, 3130 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3131 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3132 }; 3133 3134 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3135 .init = gfx_v6_0_rlc_init, 3136 .resume = gfx_v6_0_rlc_resume, 3137 .stop = gfx_v6_0_rlc_stop, 3138 .reset = gfx_v6_0_rlc_reset, 3139 .start = gfx_v6_0_rlc_start 3140 }; 3141 3142 static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) 3143 { 3144 struct amdgpu_device *adev = ip_block->adev; 3145 3146 adev->gfx.xcc_mask = 1; 3147 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3148 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3149 GFX6_NUM_COMPUTE_RINGS); 3150 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3151 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3152 gfx_v6_0_set_ring_funcs(adev); 3153 gfx_v6_0_set_irq_funcs(adev); 3154 3155 return 0; 3156 } 3157 3158 static int gfx_v6_0_late_init(struct amdgpu_ip_block *ip_block) 3159 { 3160 return 0; 3161 } 3162 3163 static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 3164 { 3165 struct amdgpu_ring *ring; 3166 struct amdgpu_device *adev = ip_block->adev; 3167 int i, r; 3168 3169 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3170 if (r) 3171 return r; 3172 3173 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3174 if (r) 3175 return r; 3176 3177 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3178 if (r) 3179 return r; 3180 3181 r = gfx_v6_0_init_microcode(adev); 3182 if (r) { 3183 DRM_ERROR("Failed to load gfx firmware!\n"); 3184 return r; 3185 } 3186 3187 r = adev->gfx.rlc.funcs->init(adev); 3188 if (r) { 3189 DRM_ERROR("Failed to init rlc BOs!\n"); 3190 return r; 3191 } 3192 3193 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3194 ring = &adev->gfx.gfx_ring[i]; 3195 ring->ring_obj = NULL; 3196 sprintf(ring->name, "gfx"); 3197 r = amdgpu_ring_init(adev, ring, 2048, 3198 &adev->gfx.eop_irq, 3199 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3200 AMDGPU_RING_PRIO_DEFAULT, NULL); 3201 if (r) 3202 return r; 3203 } 3204 3205 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3206 unsigned irq_type; 3207 3208 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3209 DRM_ERROR("Too many (%d) compute rings!\n", i); 3210 break; 3211 } 3212 ring = &adev->gfx.compute_ring[i]; 3213 ring->ring_obj = NULL; 3214 ring->use_doorbell = false; 3215 ring->doorbell_index = 0; 3216 ring->me = 1; 3217 ring->pipe = i; 3218 ring->queue = i; 3219 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3220 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3221 r = amdgpu_ring_init(adev, ring, 1024, 3222 &adev->gfx.eop_irq, irq_type, 3223 AMDGPU_RING_PRIO_DEFAULT, NULL); 3224 if (r) 3225 return r; 3226 } 3227 3228 adev->gfx.gfx_supported_reset = 3229 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 3230 adev->gfx.compute_supported_reset = 3231 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 3232 3233 if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_ip_block_soft_reset) { 3234 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 3235 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 3236 } 3237 3238 return r; 3239 } 3240 3241 static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 3242 { 3243 int i; 3244 struct amdgpu_device *adev = ip_block->adev; 3245 3246 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3247 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3248 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3249 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3250 3251 amdgpu_gfx_rlc_fini(adev); 3252 3253 return 0; 3254 } 3255 3256 static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 3257 { 3258 int r; 3259 struct amdgpu_device *adev = ip_block->adev; 3260 3261 gfx_v6_0_constants_init(adev); 3262 3263 r = adev->gfx.rlc.funcs->resume(adev); 3264 if (r) 3265 return r; 3266 3267 r = gfx_v6_0_cp_resume(adev); 3268 if (r) 3269 return r; 3270 3271 adev->gfx.ce_ram_size = 0x8000; 3272 3273 return r; 3274 } 3275 3276 static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 3277 { 3278 struct amdgpu_device *adev = ip_block->adev; 3279 3280 gfx_v6_0_cp_enable(adev, false); 3281 adev->gfx.rlc.funcs->stop(adev); 3282 gfx_v6_0_fini_pg(adev); 3283 3284 return 0; 3285 } 3286 3287 static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) 3288 { 3289 return gfx_v6_0_hw_fini(ip_block); 3290 } 3291 3292 static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) 3293 { 3294 return gfx_v6_0_hw_init(ip_block); 3295 } 3296 3297 static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 3298 { 3299 struct amdgpu_device *adev = ip_block->adev; 3300 3301 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3302 return false; 3303 else 3304 return true; 3305 } 3306 3307 static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3308 { 3309 unsigned i; 3310 struct amdgpu_device *adev = ip_block->adev; 3311 3312 for (i = 0; i < adev->usec_timeout; i++) { 3313 if (gfx_v6_0_is_idle(ip_block)) 3314 return 0; 3315 udelay(1); 3316 } 3317 return -ETIMEDOUT; 3318 } 3319 3320 static int gfx_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 3321 { 3322 struct amdgpu_device *adev = ip_block->adev; 3323 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 3324 u32 tmp; 3325 int r; 3326 3327 grbm_soft_reset = 3328 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CP, 1) | 3329 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CB, 1) | 3330 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1) | 3331 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_DB, 1) | 3332 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_GDS, 1) | 3333 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_PA, 1) | 3334 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SC, 1) | 3335 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_BCI, 1) | 3336 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SPI, 1) | 3337 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SX, 1) | 3338 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_TC, 1) | 3339 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_TA, 1) | 3340 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_VGT, 1) | 3341 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_IA, 1); 3342 3343 srbm_soft_reset = 3344 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1) | 3345 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 3346 3347 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 3348 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 3349 ip_block->version->funcs->suspend(ip_block); 3350 3351 if (grbm_soft_reset || srbm_soft_reset) { 3352 tmp = RREG32(mmGMCON_DEBUG); 3353 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1); 3354 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1); 3355 WREG32(mmGMCON_DEBUG, tmp); 3356 3357 udelay(100); 3358 } 3359 3360 if (grbm_soft_reset) { 3361 tmp = RREG32(mmGRBM_SOFT_RESET); 3362 tmp |= grbm_soft_reset; 3363 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3364 WREG32(mmGRBM_SOFT_RESET, tmp); 3365 tmp = RREG32(mmGRBM_SOFT_RESET); 3366 3367 udelay(100); 3368 3369 tmp &= ~grbm_soft_reset; 3370 WREG32(mmGRBM_SOFT_RESET, tmp); 3371 tmp = RREG32(mmGRBM_SOFT_RESET); 3372 3373 udelay(100); 3374 } 3375 3376 if (srbm_soft_reset) { 3377 tmp = RREG32(mmSRBM_SOFT_RESET); 3378 tmp |= srbm_soft_reset; 3379 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3380 WREG32(mmSRBM_SOFT_RESET, tmp); 3381 tmp = RREG32(mmSRBM_SOFT_RESET); 3382 3383 udelay(100); 3384 3385 tmp &= ~srbm_soft_reset; 3386 WREG32(mmSRBM_SOFT_RESET, tmp); 3387 tmp = RREG32(mmSRBM_SOFT_RESET); 3388 3389 udelay(100); 3390 } 3391 3392 if (grbm_soft_reset || srbm_soft_reset) { 3393 tmp = RREG32(mmGMCON_DEBUG); 3394 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); 3395 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); 3396 WREG32(mmGMCON_DEBUG, tmp); 3397 } 3398 3399 /* Wait a little for things to settle down */ 3400 udelay(100); 3401 3402 r = ip_block->version->funcs->resume(ip_block); 3403 r |= ip_block->version->funcs->late_init(ip_block); 3404 if (r) 3405 return r; 3406 3407 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_GATE); 3408 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_GATE); 3409 3410 return 0; 3411 } 3412 3413 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3414 enum amdgpu_interrupt_state state) 3415 { 3416 u32 cp_int_cntl; 3417 3418 switch (state) { 3419 case AMDGPU_IRQ_STATE_DISABLE: 3420 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3421 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3422 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3423 break; 3424 case AMDGPU_IRQ_STATE_ENABLE: 3425 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3426 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3427 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3428 break; 3429 default: 3430 break; 3431 } 3432 } 3433 3434 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3435 int ring, 3436 enum amdgpu_interrupt_state state) 3437 { 3438 u32 cp_int_cntl; 3439 switch (state){ 3440 case AMDGPU_IRQ_STATE_DISABLE: 3441 if (ring == 0) { 3442 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3443 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3444 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3445 break; 3446 } else { 3447 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3448 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3449 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3450 break; 3451 3452 } 3453 case AMDGPU_IRQ_STATE_ENABLE: 3454 if (ring == 0) { 3455 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3456 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3457 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3458 break; 3459 } else { 3460 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3461 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3462 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3463 break; 3464 3465 } 3466 3467 default: 3468 break; 3469 3470 } 3471 } 3472 3473 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3474 struct amdgpu_irq_src *src, 3475 unsigned type, 3476 enum amdgpu_interrupt_state state) 3477 { 3478 u32 cp_int_cntl; 3479 3480 switch (state) { 3481 case AMDGPU_IRQ_STATE_DISABLE: 3482 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3483 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3484 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3485 break; 3486 case AMDGPU_IRQ_STATE_ENABLE: 3487 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3488 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3489 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3490 break; 3491 default: 3492 break; 3493 } 3494 3495 return 0; 3496 } 3497 3498 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3499 struct amdgpu_irq_src *src, 3500 unsigned type, 3501 enum amdgpu_interrupt_state state) 3502 { 3503 u32 cp_int_cntl; 3504 3505 switch (state) { 3506 case AMDGPU_IRQ_STATE_DISABLE: 3507 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3508 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3509 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3510 break; 3511 case AMDGPU_IRQ_STATE_ENABLE: 3512 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3513 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3514 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3515 break; 3516 default: 3517 break; 3518 } 3519 3520 return 0; 3521 } 3522 3523 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3524 struct amdgpu_irq_src *src, 3525 unsigned type, 3526 enum amdgpu_interrupt_state state) 3527 { 3528 switch (type) { 3529 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3530 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3531 break; 3532 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3533 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3534 break; 3535 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3536 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3537 break; 3538 default: 3539 break; 3540 } 3541 return 0; 3542 } 3543 3544 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3545 struct amdgpu_irq_src *source, 3546 struct amdgpu_iv_entry *entry) 3547 { 3548 switch (entry->ring_id) { 3549 case 0: 3550 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3551 break; 3552 case 1: 3553 case 2: 3554 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3555 break; 3556 default: 3557 break; 3558 } 3559 return 0; 3560 } 3561 3562 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3563 struct amdgpu_iv_entry *entry) 3564 { 3565 struct amdgpu_ring *ring; 3566 3567 switch (entry->ring_id) { 3568 case 0: 3569 ring = &adev->gfx.gfx_ring[0]; 3570 break; 3571 case 1: 3572 case 2: 3573 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3574 break; 3575 default: 3576 return; 3577 } 3578 drm_sched_fault(&ring->sched); 3579 } 3580 3581 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3582 struct amdgpu_irq_src *source, 3583 struct amdgpu_iv_entry *entry) 3584 { 3585 DRM_ERROR("Illegal register access in command stream\n"); 3586 gfx_v6_0_fault(adev, entry); 3587 return 0; 3588 } 3589 3590 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3591 struct amdgpu_irq_src *source, 3592 struct amdgpu_iv_entry *entry) 3593 { 3594 DRM_ERROR("Illegal instruction in command stream\n"); 3595 gfx_v6_0_fault(adev, entry); 3596 return 0; 3597 } 3598 3599 static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3600 enum amd_clockgating_state state) 3601 { 3602 bool gate = false; 3603 struct amdgpu_device *adev = ip_block->adev; 3604 3605 if (state == AMD_CG_STATE_GATE) 3606 gate = true; 3607 3608 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3609 if (gate) { 3610 gfx_v6_0_enable_mgcg(adev, true); 3611 gfx_v6_0_enable_cgcg(adev, true); 3612 } else { 3613 gfx_v6_0_enable_cgcg(adev, false); 3614 gfx_v6_0_enable_mgcg(adev, false); 3615 } 3616 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3617 3618 return 0; 3619 } 3620 3621 static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3622 enum amd_powergating_state state) 3623 { 3624 bool gate = false; 3625 struct amdgpu_device *adev = ip_block->adev; 3626 3627 if (state == AMD_PG_STATE_GATE) 3628 gate = true; 3629 3630 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3631 AMD_PG_SUPPORT_GFX_SMG | 3632 AMD_PG_SUPPORT_GFX_DMG | 3633 AMD_PG_SUPPORT_CP | 3634 AMD_PG_SUPPORT_GDS | 3635 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3636 gfx_v6_0_update_gfx_pg(adev, gate); 3637 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3638 gfx_v6_0_enable_cp_pg(adev, gate); 3639 gfx_v6_0_enable_gds_pg(adev, gate); 3640 } 3641 } 3642 3643 return 0; 3644 } 3645 3646 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3647 { 3648 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3649 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3650 PACKET3_TC_ACTION_ENA | 3651 PACKET3_SH_KCACHE_ACTION_ENA | 3652 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3653 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3654 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3655 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3656 } 3657 3658 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3659 .name = "gfx_v6_0", 3660 .early_init = gfx_v6_0_early_init, 3661 .late_init = gfx_v6_0_late_init, 3662 .sw_init = gfx_v6_0_sw_init, 3663 .sw_fini = gfx_v6_0_sw_fini, 3664 .hw_init = gfx_v6_0_hw_init, 3665 .hw_fini = gfx_v6_0_hw_fini, 3666 .suspend = gfx_v6_0_suspend, 3667 .resume = gfx_v6_0_resume, 3668 .is_idle = gfx_v6_0_is_idle, 3669 .wait_for_idle = gfx_v6_0_wait_for_idle, 3670 .soft_reset = gfx_v6_0_soft_reset, 3671 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3672 .set_powergating_state = gfx_v6_0_set_powergating_state, 3673 }; 3674 3675 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3676 .type = AMDGPU_RING_TYPE_GFX, 3677 .align_mask = 0xff, 3678 .nop = 0x80000000, 3679 .support_64bit_ptrs = false, 3680 .get_rptr = gfx_v6_0_ring_get_rptr, 3681 .get_wptr = gfx_v6_0_ring_get_wptr, 3682 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3683 .emit_frame_size = 3684 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 3685 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 3686 5 + 5 + /* hdp flush / invalidate */ 3687 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3688 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3689 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 2 + /* gfx_v6_0_ring_emit_vm_flush */ 3690 3 * 2 + /* gfx_v6_0_ring_emit_sb x3 (from amdgpu_vm_flush, amdgpu_ib_schedule) */ 3691 3 + 2 + 2 + /* gfx_v6_ring_emit_cntxcntl including VGT flush */ 3692 5, /* SURFACE_SYNC */ 3693 .emit_ib_size = 4, /* gfx_v6_0_ring_emit_ib */ 3694 .emit_ib = gfx_v6_0_ring_emit_ib, 3695 .emit_fence = gfx_v6_0_ring_emit_fence, 3696 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3697 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3698 .test_ring = gfx_v6_0_ring_test_ring, 3699 .test_ib = gfx_v6_0_ring_test_ib, 3700 .insert_nop = amdgpu_ring_insert_nop, 3701 .emit_switch_buffer = gfx_v6_0_ring_emit_sb, 3702 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3703 .init_cond_exec = gfx_v6_0_ring_emit_init_cond_exec, 3704 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3705 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3706 }; 3707 3708 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3709 .type = AMDGPU_RING_TYPE_COMPUTE, 3710 .align_mask = 0xff, 3711 .nop = 0x80000000, 3712 .get_rptr = gfx_v6_0_ring_get_rptr, 3713 .get_wptr = gfx_v6_0_ring_get_wptr, 3714 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3715 .emit_frame_size = 3716 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 3717 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 3718 5 + 5 + /* hdp flush / invalidate */ 3719 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3720 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 2 + /* gfx_v6_0_ring_emit_vm_flush */ 3721 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3722 3 * 2 + /* gfx_v6_0_ring_emit_sb x3 (from amdgpu_vm_flush, amdgpu_ib_schedule) */ 3723 5, /* SURFACE_SYNC */ 3724 .emit_ib_size = 4, /* gfx_v6_0_ring_emit_ib */ 3725 .emit_ib = gfx_v6_0_ring_emit_ib, 3726 .emit_fence = gfx_v6_0_ring_emit_fence, 3727 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3728 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3729 .test_ring = gfx_v6_0_ring_test_ring, 3730 .test_ib = gfx_v6_0_ring_test_ib, 3731 .insert_nop = amdgpu_ring_insert_nop, 3732 .emit_switch_buffer = gfx_v6_0_ring_emit_sb, 3733 .init_cond_exec = gfx_v6_0_ring_emit_init_cond_exec, 3734 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3735 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3736 }; 3737 3738 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3739 { 3740 int i; 3741 3742 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3743 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3744 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3745 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3746 } 3747 3748 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3749 .set = gfx_v6_0_set_eop_interrupt_state, 3750 .process = gfx_v6_0_eop_irq, 3751 }; 3752 3753 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3754 .set = gfx_v6_0_set_priv_reg_fault_state, 3755 .process = gfx_v6_0_priv_reg_irq, 3756 }; 3757 3758 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3759 .set = gfx_v6_0_set_priv_inst_fault_state, 3760 .process = gfx_v6_0_priv_inst_irq, 3761 }; 3762 3763 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3764 { 3765 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3766 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3767 3768 adev->gfx.priv_reg_irq.num_types = 1; 3769 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3770 3771 adev->gfx.priv_inst_irq.num_types = 1; 3772 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3773 } 3774 3775 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3776 { 3777 int i, j, k, counter, active_cu_number = 0; 3778 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3779 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3780 unsigned disable_masks[4 * 2]; 3781 u32 ao_cu_num; 3782 3783 if (adev->flags & AMD_IS_APU) 3784 ao_cu_num = 2; 3785 else 3786 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3787 3788 memset(cu_info, 0, sizeof(*cu_info)); 3789 3790 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 3791 3792 mutex_lock(&adev->grbm_idx_mutex); 3793 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3794 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3795 mask = 1; 3796 ao_bitmap = 0; 3797 counter = 0; 3798 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3799 if (i < 4 && j < 2) 3800 gfx_v6_0_set_user_cu_inactive_bitmap( 3801 adev, disable_masks[i * 2 + j]); 3802 bitmap = gfx_v6_0_get_cu_enabled(adev); 3803 cu_info->bitmap[0][i][j] = bitmap; 3804 3805 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3806 if (bitmap & mask) { 3807 if (counter < ao_cu_num) 3808 ao_bitmap |= mask; 3809 counter ++; 3810 } 3811 mask <<= 1; 3812 } 3813 active_cu_number += counter; 3814 if (i < 2 && j < 2) 3815 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3816 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3817 } 3818 } 3819 3820 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3821 mutex_unlock(&adev->grbm_idx_mutex); 3822 3823 cu_info->number = active_cu_number; 3824 cu_info->ao_cu_mask = ao_cu_mask; 3825 } 3826 3827 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3828 { 3829 .type = AMD_IP_BLOCK_TYPE_GFX, 3830 .major = 6, 3831 .minor = 0, 3832 .rev = 0, 3833 .funcs = &gfx_v6_0_ip_funcs, 3834 }; 3835