1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "si/clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 45 46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin"); 47 MODULE_FIRMWARE("radeon/tahiti_me.bin"); 48 MODULE_FIRMWARE("radeon/tahiti_ce.bin"); 49 MODULE_FIRMWARE("radeon/tahiti_rlc.bin"); 50 51 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin"); 52 MODULE_FIRMWARE("radeon/pitcairn_me.bin"); 53 MODULE_FIRMWARE("radeon/pitcairn_ce.bin"); 54 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin"); 55 56 MODULE_FIRMWARE("radeon/verde_pfp.bin"); 57 MODULE_FIRMWARE("radeon/verde_me.bin"); 58 MODULE_FIRMWARE("radeon/verde_ce.bin"); 59 MODULE_FIRMWARE("radeon/verde_rlc.bin"); 60 61 MODULE_FIRMWARE("radeon/oland_pfp.bin"); 62 MODULE_FIRMWARE("radeon/oland_me.bin"); 63 MODULE_FIRMWARE("radeon/oland_ce.bin"); 64 MODULE_FIRMWARE("radeon/oland_rlc.bin"); 65 66 MODULE_FIRMWARE("radeon/hainan_pfp.bin"); 67 MODULE_FIRMWARE("radeon/hainan_me.bin"); 68 MODULE_FIRMWARE("radeon/hainan_ce.bin"); 69 MODULE_FIRMWARE("radeon/hainan_rlc.bin"); 70 71 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 72 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 73 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 74 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 75 76 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 77 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 78 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 79 #define MICRO_TILE_MODE(x) ((x) << 0) 80 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 81 #define BANK_WIDTH(x) ((x) << 14) 82 #define BANK_HEIGHT(x) ((x) << 16) 83 #define MACRO_TILE_ASPECT(x) ((x) << 18) 84 #define NUM_BANKS(x) ((x) << 20) 85 86 static const u32 verde_rlc_save_restore_register_list[] = 87 { 88 (0x8000 << 16) | (0x98f4 >> 2), 89 0x00000000, 90 (0x8040 << 16) | (0x98f4 >> 2), 91 0x00000000, 92 (0x8000 << 16) | (0xe80 >> 2), 93 0x00000000, 94 (0x8040 << 16) | (0xe80 >> 2), 95 0x00000000, 96 (0x8000 << 16) | (0x89bc >> 2), 97 0x00000000, 98 (0x8040 << 16) | (0x89bc >> 2), 99 0x00000000, 100 (0x8000 << 16) | (0x8c1c >> 2), 101 0x00000000, 102 (0x8040 << 16) | (0x8c1c >> 2), 103 0x00000000, 104 (0x9c00 << 16) | (0x98f0 >> 2), 105 0x00000000, 106 (0x9c00 << 16) | (0xe7c >> 2), 107 0x00000000, 108 (0x8000 << 16) | (0x9148 >> 2), 109 0x00000000, 110 (0x8040 << 16) | (0x9148 >> 2), 111 0x00000000, 112 (0x9c00 << 16) | (0x9150 >> 2), 113 0x00000000, 114 (0x9c00 << 16) | (0x897c >> 2), 115 0x00000000, 116 (0x9c00 << 16) | (0x8d8c >> 2), 117 0x00000000, 118 (0x9c00 << 16) | (0xac54 >> 2), 119 0X00000000, 120 0x3, 121 (0x9c00 << 16) | (0x98f8 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0x9910 >> 2), 124 0x00000000, 125 (0x9c00 << 16) | (0x9914 >> 2), 126 0x00000000, 127 (0x9c00 << 16) | (0x9918 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x991c >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x9920 >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x9924 >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0x9928 >> 2), 136 0x00000000, 137 (0x9c00 << 16) | (0x992c >> 2), 138 0x00000000, 139 (0x9c00 << 16) | (0x9930 >> 2), 140 0x00000000, 141 (0x9c00 << 16) | (0x9934 >> 2), 142 0x00000000, 143 (0x9c00 << 16) | (0x9938 >> 2), 144 0x00000000, 145 (0x9c00 << 16) | (0x993c >> 2), 146 0x00000000, 147 (0x9c00 << 16) | (0x9940 >> 2), 148 0x00000000, 149 (0x9c00 << 16) | (0x9944 >> 2), 150 0x00000000, 151 (0x9c00 << 16) | (0x9948 >> 2), 152 0x00000000, 153 (0x9c00 << 16) | (0x994c >> 2), 154 0x00000000, 155 (0x9c00 << 16) | (0x9950 >> 2), 156 0x00000000, 157 (0x9c00 << 16) | (0x9954 >> 2), 158 0x00000000, 159 (0x9c00 << 16) | (0x9958 >> 2), 160 0x00000000, 161 (0x9c00 << 16) | (0x995c >> 2), 162 0x00000000, 163 (0x9c00 << 16) | (0x9960 >> 2), 164 0x00000000, 165 (0x9c00 << 16) | (0x9964 >> 2), 166 0x00000000, 167 (0x9c00 << 16) | (0x9968 >> 2), 168 0x00000000, 169 (0x9c00 << 16) | (0x996c >> 2), 170 0x00000000, 171 (0x9c00 << 16) | (0x9970 >> 2), 172 0x00000000, 173 (0x9c00 << 16) | (0x9974 >> 2), 174 0x00000000, 175 (0x9c00 << 16) | (0x9978 >> 2), 176 0x00000000, 177 (0x9c00 << 16) | (0x997c >> 2), 178 0x00000000, 179 (0x9c00 << 16) | (0x9980 >> 2), 180 0x00000000, 181 (0x9c00 << 16) | (0x9984 >> 2), 182 0x00000000, 183 (0x9c00 << 16) | (0x9988 >> 2), 184 0x00000000, 185 (0x9c00 << 16) | (0x998c >> 2), 186 0x00000000, 187 (0x9c00 << 16) | (0x8c00 >> 2), 188 0x00000000, 189 (0x9c00 << 16) | (0x8c14 >> 2), 190 0x00000000, 191 (0x9c00 << 16) | (0x8c04 >> 2), 192 0x00000000, 193 (0x9c00 << 16) | (0x8c08 >> 2), 194 0x00000000, 195 (0x8000 << 16) | (0x9b7c >> 2), 196 0x00000000, 197 (0x8040 << 16) | (0x9b7c >> 2), 198 0x00000000, 199 (0x8000 << 16) | (0xe84 >> 2), 200 0x00000000, 201 (0x8040 << 16) | (0xe84 >> 2), 202 0x00000000, 203 (0x8000 << 16) | (0x89c0 >> 2), 204 0x00000000, 205 (0x8040 << 16) | (0x89c0 >> 2), 206 0x00000000, 207 (0x8000 << 16) | (0x914c >> 2), 208 0x00000000, 209 (0x8040 << 16) | (0x914c >> 2), 210 0x00000000, 211 (0x8000 << 16) | (0x8c20 >> 2), 212 0x00000000, 213 (0x8040 << 16) | (0x8c20 >> 2), 214 0x00000000, 215 (0x8000 << 16) | (0x9354 >> 2), 216 0x00000000, 217 (0x8040 << 16) | (0x9354 >> 2), 218 0x00000000, 219 (0x9c00 << 16) | (0x9060 >> 2), 220 0x00000000, 221 (0x9c00 << 16) | (0x9364 >> 2), 222 0x00000000, 223 (0x9c00 << 16) | (0x9100 >> 2), 224 0x00000000, 225 (0x9c00 << 16) | (0x913c >> 2), 226 0x00000000, 227 (0x8000 << 16) | (0x90e0 >> 2), 228 0x00000000, 229 (0x8000 << 16) | (0x90e4 >> 2), 230 0x00000000, 231 (0x8000 << 16) | (0x90e8 >> 2), 232 0x00000000, 233 (0x8040 << 16) | (0x90e0 >> 2), 234 0x00000000, 235 (0x8040 << 16) | (0x90e4 >> 2), 236 0x00000000, 237 (0x8040 << 16) | (0x90e8 >> 2), 238 0x00000000, 239 (0x9c00 << 16) | (0x8bcc >> 2), 240 0x00000000, 241 (0x9c00 << 16) | (0x8b24 >> 2), 242 0x00000000, 243 (0x9c00 << 16) | (0x88c4 >> 2), 244 0x00000000, 245 (0x9c00 << 16) | (0x8e50 >> 2), 246 0x00000000, 247 (0x9c00 << 16) | (0x8c0c >> 2), 248 0x00000000, 249 (0x9c00 << 16) | (0x8e58 >> 2), 250 0x00000000, 251 (0x9c00 << 16) | (0x8e5c >> 2), 252 0x00000000, 253 (0x9c00 << 16) | (0x9508 >> 2), 254 0x00000000, 255 (0x9c00 << 16) | (0x950c >> 2), 256 0x00000000, 257 (0x9c00 << 16) | (0x9494 >> 2), 258 0x00000000, 259 (0x9c00 << 16) | (0xac0c >> 2), 260 0x00000000, 261 (0x9c00 << 16) | (0xac10 >> 2), 262 0x00000000, 263 (0x9c00 << 16) | (0xac14 >> 2), 264 0x00000000, 265 (0x9c00 << 16) | (0xae00 >> 2), 266 0x00000000, 267 (0x9c00 << 16) | (0xac08 >> 2), 268 0x00000000, 269 (0x9c00 << 16) | (0x88d4 >> 2), 270 0x00000000, 271 (0x9c00 << 16) | (0x88c8 >> 2), 272 0x00000000, 273 (0x9c00 << 16) | (0x88cc >> 2), 274 0x00000000, 275 (0x9c00 << 16) | (0x89b0 >> 2), 276 0x00000000, 277 (0x9c00 << 16) | (0x8b10 >> 2), 278 0x00000000, 279 (0x9c00 << 16) | (0x8a14 >> 2), 280 0x00000000, 281 (0x9c00 << 16) | (0x9830 >> 2), 282 0x00000000, 283 (0x9c00 << 16) | (0x9834 >> 2), 284 0x00000000, 285 (0x9c00 << 16) | (0x9838 >> 2), 286 0x00000000, 287 (0x9c00 << 16) | (0x9a10 >> 2), 288 0x00000000, 289 (0x8000 << 16) | (0x9870 >> 2), 290 0x00000000, 291 (0x8000 << 16) | (0x9874 >> 2), 292 0x00000000, 293 (0x8001 << 16) | (0x9870 >> 2), 294 0x00000000, 295 (0x8001 << 16) | (0x9874 >> 2), 296 0x00000000, 297 (0x8040 << 16) | (0x9870 >> 2), 298 0x00000000, 299 (0x8040 << 16) | (0x9874 >> 2), 300 0x00000000, 301 (0x8041 << 16) | (0x9870 >> 2), 302 0x00000000, 303 (0x8041 << 16) | (0x9874 >> 2), 304 0x00000000, 305 0x00000000 306 }; 307 308 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 309 { 310 const char *chip_name; 311 char fw_name[30]; 312 int err; 313 const struct gfx_firmware_header_v1_0 *cp_hdr; 314 const struct rlc_firmware_header_v1_0 *rlc_hdr; 315 316 DRM_DEBUG("\n"); 317 318 switch (adev->asic_type) { 319 case CHIP_TAHITI: 320 chip_name = "tahiti"; 321 break; 322 case CHIP_PITCAIRN: 323 chip_name = "pitcairn"; 324 break; 325 case CHIP_VERDE: 326 chip_name = "verde"; 327 break; 328 case CHIP_OLAND: 329 chip_name = "oland"; 330 break; 331 case CHIP_HAINAN: 332 chip_name = "hainan"; 333 break; 334 default: BUG(); 335 } 336 337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 339 if (err) 340 goto out; 341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 342 if (err) 343 goto out; 344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 347 348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 350 if (err) 351 goto out; 352 err = amdgpu_ucode_validate(adev->gfx.me_fw); 353 if (err) 354 goto out; 355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 358 359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 361 if (err) 362 goto out; 363 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 364 if (err) 365 goto out; 366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 369 370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 372 if (err) 373 goto out; 374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 378 379 out: 380 if (err) { 381 printk(KERN_ERR 382 "gfx6: Failed to load firmware \"%s\"\n", 383 fw_name); 384 release_firmware(adev->gfx.pfp_fw); 385 adev->gfx.pfp_fw = NULL; 386 release_firmware(adev->gfx.me_fw); 387 adev->gfx.me_fw = NULL; 388 release_firmware(adev->gfx.ce_fw); 389 adev->gfx.ce_fw = NULL; 390 release_firmware(adev->gfx.rlc_fw); 391 adev->gfx.rlc_fw = NULL; 392 } 393 return err; 394 } 395 396 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 397 { 398 const u32 num_tile_mode_states = 32; 399 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 400 401 switch (adev->gfx.config.mem_row_size_in_kb) { 402 case 1: 403 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 404 break; 405 case 2: 406 default: 407 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 408 break; 409 case 4: 410 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 411 break; 412 } 413 414 if (adev->asic_type == CHIP_VERDE || 415 adev->asic_type == CHIP_OLAND || 416 adev->asic_type == CHIP_HAINAN) { 417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 418 switch (reg_offset) { 419 case 0: 420 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 421 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 422 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 424 NUM_BANKS(ADDR_SURF_16_BANK) | 425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 428 break; 429 case 1: 430 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 431 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 432 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 433 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 434 NUM_BANKS(ADDR_SURF_16_BANK) | 435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 438 break; 439 case 2: 440 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 442 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 444 NUM_BANKS(ADDR_SURF_16_BANK) | 445 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 448 break; 449 case 3: 450 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 451 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 452 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 453 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 454 NUM_BANKS(ADDR_SURF_16_BANK) | 455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 458 break; 459 case 4: 460 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 461 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 464 NUM_BANKS(ADDR_SURF_16_BANK) | 465 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 468 break; 469 case 5: 470 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 471 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 472 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 473 TILE_SPLIT(split_equal_to_row_size) | 474 NUM_BANKS(ADDR_SURF_16_BANK) | 475 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 478 break; 479 case 6: 480 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 481 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 483 TILE_SPLIT(split_equal_to_row_size) | 484 NUM_BANKS(ADDR_SURF_16_BANK) | 485 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 488 break; 489 case 7: 490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 491 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 492 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 493 TILE_SPLIT(split_equal_to_row_size) | 494 NUM_BANKS(ADDR_SURF_16_BANK) | 495 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 496 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 497 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 498 break; 499 case 8: 500 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 501 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 502 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 504 NUM_BANKS(ADDR_SURF_16_BANK) | 505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 508 break; 509 case 9: 510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 511 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 514 NUM_BANKS(ADDR_SURF_16_BANK) | 515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 518 break; 519 case 10: 520 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 521 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 522 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 523 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 524 NUM_BANKS(ADDR_SURF_16_BANK) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 528 break; 529 case 11: 530 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 531 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 534 NUM_BANKS(ADDR_SURF_16_BANK) | 535 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 538 break; 539 case 12: 540 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 541 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 542 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 543 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 544 NUM_BANKS(ADDR_SURF_16_BANK) | 545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 548 break; 549 case 13: 550 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 551 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 553 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 554 NUM_BANKS(ADDR_SURF_16_BANK) | 555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 558 break; 559 case 14: 560 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 561 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 562 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 563 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 564 NUM_BANKS(ADDR_SURF_16_BANK) | 565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 568 break; 569 case 15: 570 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 571 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 572 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 574 NUM_BANKS(ADDR_SURF_16_BANK) | 575 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 578 break; 579 case 16: 580 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 581 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 583 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 584 NUM_BANKS(ADDR_SURF_16_BANK) | 585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 588 break; 589 case 17: 590 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 591 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 593 TILE_SPLIT(split_equal_to_row_size) | 594 NUM_BANKS(ADDR_SURF_16_BANK) | 595 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 598 break; 599 case 21: 600 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 601 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 602 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 603 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 604 NUM_BANKS(ADDR_SURF_16_BANK) | 605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 608 break; 609 case 22: 610 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 611 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 612 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 613 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 614 NUM_BANKS(ADDR_SURF_16_BANK) | 615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 618 break; 619 case 23: 620 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 621 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 624 NUM_BANKS(ADDR_SURF_16_BANK) | 625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 628 break; 629 case 24: 630 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 631 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 632 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 634 NUM_BANKS(ADDR_SURF_16_BANK) | 635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 638 break; 639 case 25: 640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 641 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 642 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 644 NUM_BANKS(ADDR_SURF_8_BANK) | 645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 648 break; 649 default: 650 gb_tile_moden = 0; 651 break; 652 } 653 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 654 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 655 } 656 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 657 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 658 switch (reg_offset) { 659 case 0: /* non-AA compressed depth or any compressed stencil */ 660 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 661 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 662 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 664 NUM_BANKS(ADDR_SURF_16_BANK) | 665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 668 break; 669 case 1: /* 2xAA/4xAA compressed depth only */ 670 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 671 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 672 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 673 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 674 NUM_BANKS(ADDR_SURF_16_BANK) | 675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 678 break; 679 case 2: /* 8xAA compressed depth only */ 680 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 681 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 682 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 683 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 684 NUM_BANKS(ADDR_SURF_16_BANK) | 685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 688 break; 689 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 690 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 691 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 692 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 693 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 694 NUM_BANKS(ADDR_SURF_16_BANK) | 695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 698 break; 699 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 700 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 701 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 702 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 704 NUM_BANKS(ADDR_SURF_16_BANK) | 705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 708 break; 709 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 710 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 711 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 712 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 713 TILE_SPLIT(split_equal_to_row_size) | 714 NUM_BANKS(ADDR_SURF_16_BANK) | 715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 718 break; 719 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 720 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 721 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 722 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 723 TILE_SPLIT(split_equal_to_row_size) | 724 NUM_BANKS(ADDR_SURF_16_BANK) | 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 728 break; 729 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 730 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 731 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 732 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 733 TILE_SPLIT(split_equal_to_row_size) | 734 NUM_BANKS(ADDR_SURF_16_BANK) | 735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 738 break; 739 case 8: /* 1D and 1D Array Surfaces */ 740 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 741 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 742 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 744 NUM_BANKS(ADDR_SURF_16_BANK) | 745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 748 break; 749 case 9: /* Displayable maps. */ 750 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 751 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 752 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 753 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 754 NUM_BANKS(ADDR_SURF_16_BANK) | 755 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 756 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 757 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 758 break; 759 case 10: /* Display 8bpp. */ 760 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 761 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 762 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 764 NUM_BANKS(ADDR_SURF_16_BANK) | 765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 768 break; 769 case 11: /* Display 16bpp. */ 770 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 771 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 772 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 773 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 774 NUM_BANKS(ADDR_SURF_16_BANK) | 775 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 776 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 777 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 778 break; 779 case 12: /* Display 32bpp. */ 780 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 781 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 782 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 783 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 784 NUM_BANKS(ADDR_SURF_16_BANK) | 785 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 788 break; 789 case 13: /* Thin. */ 790 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 791 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 792 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 793 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 794 NUM_BANKS(ADDR_SURF_16_BANK) | 795 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 796 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 797 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 798 break; 799 case 14: /* Thin 8 bpp. */ 800 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 801 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 804 NUM_BANKS(ADDR_SURF_16_BANK) | 805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 808 break; 809 case 15: /* Thin 16 bpp. */ 810 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 811 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 812 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 813 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 814 NUM_BANKS(ADDR_SURF_16_BANK) | 815 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 818 break; 819 case 16: /* Thin 32 bpp. */ 820 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 821 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 822 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 823 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 824 NUM_BANKS(ADDR_SURF_16_BANK) | 825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 828 break; 829 case 17: /* Thin 64 bpp. */ 830 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 831 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 832 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 833 TILE_SPLIT(split_equal_to_row_size) | 834 NUM_BANKS(ADDR_SURF_16_BANK) | 835 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 836 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 837 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 838 break; 839 case 21: /* 8 bpp PRT. */ 840 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 841 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 842 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 843 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 844 NUM_BANKS(ADDR_SURF_16_BANK) | 845 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 846 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 847 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 848 break; 849 case 22: /* 16 bpp PRT */ 850 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 851 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 852 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 853 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 854 NUM_BANKS(ADDR_SURF_16_BANK) | 855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 858 break; 859 case 23: /* 32 bpp PRT */ 860 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 861 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 862 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 864 NUM_BANKS(ADDR_SURF_16_BANK) | 865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 868 break; 869 case 24: /* 64 bpp PRT */ 870 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 871 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 872 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 874 NUM_BANKS(ADDR_SURF_16_BANK) | 875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 878 break; 879 case 25: /* 128 bpp PRT */ 880 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 881 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 882 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 883 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 884 NUM_BANKS(ADDR_SURF_8_BANK) | 885 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 888 break; 889 default: 890 gb_tile_moden = 0; 891 break; 892 } 893 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 894 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 895 } 896 } else{ 897 898 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 899 } 900 901 } 902 903 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 904 u32 sh_num, u32 instance) 905 { 906 u32 data; 907 908 if (instance == 0xffffffff) 909 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 910 else 911 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 912 913 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 914 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 915 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 916 else if (se_num == 0xffffffff) 917 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 918 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 919 else if (sh_num == 0xffffffff) 920 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 921 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 922 else 923 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 924 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 925 WREG32(mmGRBM_GFX_INDEX, data); 926 } 927 928 static u32 gfx_v6_0_create_bitmask(u32 bit_width) 929 { 930 return (u32)(((u64)1 << bit_width) - 1); 931 } 932 933 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev, 934 u32 max_rb_num_per_se, 935 u32 sh_per_se) 936 { 937 u32 data, mask; 938 939 data = RREG32(mmCC_RB_BACKEND_DISABLE); 940 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 941 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 942 943 data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 944 945 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); 946 947 return data & mask; 948 } 949 950 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 951 { 952 switch (adev->asic_type) { 953 case CHIP_TAHITI: 954 case CHIP_PITCAIRN: 955 *rconf |= 956 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 957 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 958 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 959 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 960 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 961 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 962 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 963 break; 964 case CHIP_VERDE: 965 *rconf |= 966 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 967 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 968 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 969 break; 970 case CHIP_OLAND: 971 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 972 break; 973 case CHIP_HAINAN: 974 *rconf |= 0x0; 975 break; 976 default: 977 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 978 break; 979 } 980 } 981 982 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 983 u32 raster_config, unsigned rb_mask, 984 unsigned num_rb) 985 { 986 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 987 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 988 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 989 unsigned rb_per_se = num_rb / num_se; 990 unsigned se_mask[4]; 991 unsigned se; 992 993 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 994 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 995 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 996 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 997 998 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 999 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1000 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1001 1002 for (se = 0; se < num_se; se++) { 1003 unsigned raster_config_se = raster_config; 1004 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1005 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1006 int idx = (se / 2) * 2; 1007 1008 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1009 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1010 1011 if (!se_mask[idx]) { 1012 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1013 } else { 1014 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1015 } 1016 } 1017 1018 pkr0_mask &= rb_mask; 1019 pkr1_mask &= rb_mask; 1020 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1021 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1022 1023 if (!pkr0_mask) { 1024 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1025 } else { 1026 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1027 } 1028 } 1029 1030 if (rb_per_se >= 2) { 1031 unsigned rb0_mask = 1 << (se * rb_per_se); 1032 unsigned rb1_mask = rb0_mask << 1; 1033 1034 rb0_mask &= rb_mask; 1035 rb1_mask &= rb_mask; 1036 if (!rb0_mask || !rb1_mask) { 1037 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1038 1039 if (!rb0_mask) { 1040 raster_config_se |= 1041 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1042 } else { 1043 raster_config_se |= 1044 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1045 } 1046 } 1047 1048 if (rb_per_se > 2) { 1049 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1050 rb1_mask = rb0_mask << 1; 1051 rb0_mask &= rb_mask; 1052 rb1_mask &= rb_mask; 1053 if (!rb0_mask || !rb1_mask) { 1054 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1055 1056 if (!rb0_mask) { 1057 raster_config_se |= 1058 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1059 } else { 1060 raster_config_se |= 1061 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1062 } 1063 } 1064 } 1065 } 1066 1067 /* GRBM_GFX_INDEX has a different offset on SI */ 1068 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1069 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1070 } 1071 1072 /* GRBM_GFX_INDEX has a different offset on SI */ 1073 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1074 } 1075 1076 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 1077 u32 se_num, u32 sh_per_se, 1078 u32 max_rb_num_per_se) 1079 { 1080 int i, j; 1081 u32 data, mask; 1082 u32 disabled_rbs = 0; 1083 u32 enabled_rbs = 0; 1084 unsigned num_rb_pipes; 1085 1086 mutex_lock(&adev->grbm_idx_mutex); 1087 for (i = 0; i < se_num; i++) { 1088 for (j = 0; j < sh_per_se; j++) { 1089 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1090 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); 1091 disabled_rbs |= data << ((i * sh_per_se + j) * 2); 1092 } 1093 } 1094 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1095 mutex_unlock(&adev->grbm_idx_mutex); 1096 1097 mask = 1; 1098 for (i = 0; i < max_rb_num_per_se * se_num; i++) { 1099 if (!(disabled_rbs & mask)) 1100 enabled_rbs |= mask; 1101 mask <<= 1; 1102 } 1103 1104 adev->gfx.config.backend_enable_mask = enabled_rbs; 1105 adev->gfx.config.num_rbs = hweight32(enabled_rbs); 1106 1107 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1108 adev->gfx.config.max_shader_engines, 16); 1109 1110 mutex_lock(&adev->grbm_idx_mutex); 1111 for (i = 0; i < se_num; i++) { 1112 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff); 1113 data = 0; 1114 for (j = 0; j < sh_per_se; j++) { 1115 switch (enabled_rbs & 3) { 1116 case 1: 1117 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 1118 break; 1119 case 2: 1120 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); 1121 break; 1122 case 3: 1123 default: 1124 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); 1125 break; 1126 } 1127 enabled_rbs >>= 2; 1128 } 1129 gfx_v6_0_raster_config(adev, &data); 1130 1131 if (!adev->gfx.config.backend_enable_mask || 1132 adev->gfx.config.num_rbs >= num_rb_pipes) 1133 WREG32(mmPA_SC_RASTER_CONFIG, data); 1134 else 1135 gfx_v6_0_write_harvested_raster_configs(adev, data, 1136 adev->gfx.config.backend_enable_mask, 1137 num_rb_pipes); 1138 } 1139 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1140 mutex_unlock(&adev->grbm_idx_mutex); 1141 } 1142 /* 1143 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev) 1144 { 1145 } 1146 */ 1147 1148 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh) 1149 { 1150 u32 data, mask; 1151 1152 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 1153 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1154 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1155 1156 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1157 1158 mask = gfx_v6_0_create_bitmask(cu_per_sh); 1159 1160 return ~data & mask; 1161 } 1162 1163 1164 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, 1165 u32 se_num, u32 sh_per_se, 1166 u32 cu_per_sh) 1167 { 1168 int i, j, k; 1169 u32 data, mask; 1170 u32 active_cu = 0; 1171 1172 mutex_lock(&adev->grbm_idx_mutex); 1173 for (i = 0; i < se_num; i++) { 1174 for (j = 0; j < sh_per_se; j++) { 1175 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1176 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1177 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); 1178 1179 mask = 1; 1180 for (k = 0; k < 16; k++) { 1181 mask <<= k; 1182 if (active_cu & mask) { 1183 data &= ~mask; 1184 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1185 break; 1186 } 1187 } 1188 } 1189 } 1190 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1191 mutex_unlock(&adev->grbm_idx_mutex); 1192 } 1193 1194 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) 1195 { 1196 u32 gb_addr_config = 0; 1197 u32 mc_shared_chmap, mc_arb_ramcfg; 1198 u32 sx_debug_1; 1199 u32 hdp_host_path_cntl; 1200 u32 tmp; 1201 1202 switch (adev->asic_type) { 1203 case CHIP_TAHITI: 1204 adev->gfx.config.max_shader_engines = 2; 1205 adev->gfx.config.max_tile_pipes = 12; 1206 adev->gfx.config.max_cu_per_sh = 8; 1207 adev->gfx.config.max_sh_per_se = 2; 1208 adev->gfx.config.max_backends_per_se = 4; 1209 adev->gfx.config.max_texture_channel_caches = 12; 1210 adev->gfx.config.max_gprs = 256; 1211 adev->gfx.config.max_gs_threads = 32; 1212 adev->gfx.config.max_hw_contexts = 8; 1213 1214 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1215 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1216 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1217 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1218 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1219 break; 1220 case CHIP_PITCAIRN: 1221 adev->gfx.config.max_shader_engines = 2; 1222 adev->gfx.config.max_tile_pipes = 8; 1223 adev->gfx.config.max_cu_per_sh = 5; 1224 adev->gfx.config.max_sh_per_se = 2; 1225 adev->gfx.config.max_backends_per_se = 4; 1226 adev->gfx.config.max_texture_channel_caches = 8; 1227 adev->gfx.config.max_gprs = 256; 1228 adev->gfx.config.max_gs_threads = 32; 1229 adev->gfx.config.max_hw_contexts = 8; 1230 1231 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1232 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1233 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1234 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1235 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1236 break; 1237 case CHIP_VERDE: 1238 adev->gfx.config.max_shader_engines = 1; 1239 adev->gfx.config.max_tile_pipes = 4; 1240 adev->gfx.config.max_cu_per_sh = 5; 1241 adev->gfx.config.max_sh_per_se = 2; 1242 adev->gfx.config.max_backends_per_se = 4; 1243 adev->gfx.config.max_texture_channel_caches = 4; 1244 adev->gfx.config.max_gprs = 256; 1245 adev->gfx.config.max_gs_threads = 32; 1246 adev->gfx.config.max_hw_contexts = 8; 1247 1248 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1249 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1250 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1251 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1252 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1253 break; 1254 case CHIP_OLAND: 1255 adev->gfx.config.max_shader_engines = 1; 1256 adev->gfx.config.max_tile_pipes = 4; 1257 adev->gfx.config.max_cu_per_sh = 6; 1258 adev->gfx.config.max_sh_per_se = 1; 1259 adev->gfx.config.max_backends_per_se = 2; 1260 adev->gfx.config.max_texture_channel_caches = 4; 1261 adev->gfx.config.max_gprs = 256; 1262 adev->gfx.config.max_gs_threads = 16; 1263 adev->gfx.config.max_hw_contexts = 8; 1264 1265 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1266 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1267 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1268 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1269 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1270 break; 1271 case CHIP_HAINAN: 1272 adev->gfx.config.max_shader_engines = 1; 1273 adev->gfx.config.max_tile_pipes = 4; 1274 adev->gfx.config.max_cu_per_sh = 5; 1275 adev->gfx.config.max_sh_per_se = 1; 1276 adev->gfx.config.max_backends_per_se = 1; 1277 adev->gfx.config.max_texture_channel_caches = 2; 1278 adev->gfx.config.max_gprs = 256; 1279 adev->gfx.config.max_gs_threads = 16; 1280 adev->gfx.config.max_hw_contexts = 8; 1281 1282 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1283 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1284 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1285 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1286 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1287 break; 1288 default: 1289 BUG(); 1290 break; 1291 } 1292 1293 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1294 WREG32(mmSRBM_INT_CNTL, 1); 1295 WREG32(mmSRBM_INT_ACK, 1); 1296 1297 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1298 1299 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1300 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1301 1302 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1303 adev->gfx.config.mem_max_burst_length_bytes = 256; 1304 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1305 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1306 if (adev->gfx.config.mem_row_size_in_kb > 4) 1307 adev->gfx.config.mem_row_size_in_kb = 4; 1308 adev->gfx.config.shader_engine_tile_size = 32; 1309 adev->gfx.config.num_gpus = 1; 1310 adev->gfx.config.multi_gpu_tile_size = 64; 1311 1312 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1313 switch (adev->gfx.config.mem_row_size_in_kb) { 1314 case 1: 1315 default: 1316 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1317 break; 1318 case 2: 1319 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1320 break; 1321 case 4: 1322 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1323 break; 1324 } 1325 adev->gfx.config.gb_addr_config = gb_addr_config; 1326 1327 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1328 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1329 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1330 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1331 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1332 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1333 1334 #if 0 1335 if (adev->has_uvd) { 1336 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1337 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1338 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1339 } 1340 #endif 1341 gfx_v6_0_tiling_mode_table_init(adev); 1342 1343 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines, 1344 adev->gfx.config.max_sh_per_se, 1345 adev->gfx.config.max_backends_per_se); 1346 1347 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines, 1348 adev->gfx.config.max_sh_per_se, 1349 adev->gfx.config.max_cu_per_sh); 1350 1351 gfx_v6_0_get_cu_info(adev); 1352 1353 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1354 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1355 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1356 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1357 1358 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1359 WREG32(mmSX_DEBUG_1, sx_debug_1); 1360 1361 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1362 1363 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1364 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1365 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1366 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1367 1368 WREG32(mmVGT_NUM_INSTANCES, 1); 1369 WREG32(mmCP_PERFMON_CNTL, 0); 1370 WREG32(mmSQ_CONFIG, 0); 1371 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1372 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1373 1374 WREG32(mmVGT_CACHE_INVALIDATION, 1375 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1376 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1377 1378 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1379 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1380 1381 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1382 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1383 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1384 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1385 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1386 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1387 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1388 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1389 1390 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1391 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1392 1393 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1394 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1395 1396 udelay(50); 1397 } 1398 1399 1400 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1401 { 1402 int i; 1403 1404 adev->gfx.scratch.num_reg = 7; 1405 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1406 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 1407 adev->gfx.scratch.free[i] = true; 1408 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 1409 } 1410 } 1411 1412 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1413 { 1414 struct amdgpu_device *adev = ring->adev; 1415 uint32_t scratch; 1416 uint32_t tmp = 0; 1417 unsigned i; 1418 int r; 1419 1420 r = amdgpu_gfx_scratch_get(adev, &scratch); 1421 if (r) { 1422 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 1423 return r; 1424 } 1425 WREG32(scratch, 0xCAFEDEAD); 1426 1427 r = amdgpu_ring_alloc(ring, 3); 1428 if (r) { 1429 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 1430 amdgpu_gfx_scratch_free(adev, scratch); 1431 return r; 1432 } 1433 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1434 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1435 amdgpu_ring_write(ring, 0xDEADBEEF); 1436 amdgpu_ring_commit(ring); 1437 1438 for (i = 0; i < adev->usec_timeout; i++) { 1439 tmp = RREG32(scratch); 1440 if (tmp == 0xDEADBEEF) 1441 break; 1442 DRM_UDELAY(1); 1443 } 1444 if (i < adev->usec_timeout) { 1445 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1446 } else { 1447 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1448 ring->idx, scratch, tmp); 1449 r = -EINVAL; 1450 } 1451 amdgpu_gfx_scratch_free(adev, scratch); 1452 return r; 1453 } 1454 1455 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1456 { 1457 /* flush hdp cache */ 1458 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1459 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1460 WRITE_DATA_DST_SEL(0))); 1461 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1462 amdgpu_ring_write(ring, 0); 1463 amdgpu_ring_write(ring, 0x1); 1464 } 1465 1466 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1467 { 1468 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1469 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1470 EVENT_INDEX(0)); 1471 } 1472 1473 /** 1474 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1475 * 1476 * @adev: amdgpu_device pointer 1477 * @ridx: amdgpu ring index 1478 * 1479 * Emits an hdp invalidate on the cp. 1480 */ 1481 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 1482 { 1483 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1484 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1485 WRITE_DATA_DST_SEL(0))); 1486 amdgpu_ring_write(ring, mmHDP_DEBUG0); 1487 amdgpu_ring_write(ring, 0); 1488 amdgpu_ring_write(ring, 0x1); 1489 } 1490 1491 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1492 u64 seq, unsigned flags) 1493 { 1494 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1495 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1496 /* flush read cache over gart */ 1497 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1498 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1499 amdgpu_ring_write(ring, 0); 1500 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1501 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1502 PACKET3_TC_ACTION_ENA | 1503 PACKET3_SH_KCACHE_ACTION_ENA | 1504 PACKET3_SH_ICACHE_ACTION_ENA); 1505 amdgpu_ring_write(ring, 0xFFFFFFFF); 1506 amdgpu_ring_write(ring, 0); 1507 amdgpu_ring_write(ring, 10); /* poll interval */ 1508 /* EVENT_WRITE_EOP - flush caches, send int */ 1509 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1510 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1511 amdgpu_ring_write(ring, addr & 0xfffffffc); 1512 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1513 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1514 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1515 amdgpu_ring_write(ring, lower_32_bits(seq)); 1516 amdgpu_ring_write(ring, upper_32_bits(seq)); 1517 } 1518 1519 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1520 struct amdgpu_ib *ib, 1521 unsigned vm_id, bool ctx_switch) 1522 { 1523 u32 header, control = 0; 1524 1525 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1526 if (ctx_switch) { 1527 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1528 amdgpu_ring_write(ring, 0); 1529 } 1530 1531 if (ib->flags & AMDGPU_IB_FLAG_CE) 1532 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1533 else 1534 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1535 1536 control |= ib->length_dw | (vm_id << 24); 1537 1538 amdgpu_ring_write(ring, header); 1539 amdgpu_ring_write(ring, 1540 #ifdef __BIG_ENDIAN 1541 (2 << 0) | 1542 #endif 1543 (ib->gpu_addr & 0xFFFFFFFC)); 1544 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1545 amdgpu_ring_write(ring, control); 1546 } 1547 1548 /** 1549 * gfx_v6_0_ring_test_ib - basic ring IB test 1550 * 1551 * @ring: amdgpu_ring structure holding ring information 1552 * 1553 * Allocate an IB and execute it on the gfx ring (SI). 1554 * Provides a basic gfx ring test to verify that IBs are working. 1555 * Returns 0 on success, error on failure. 1556 */ 1557 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1558 { 1559 struct amdgpu_device *adev = ring->adev; 1560 struct amdgpu_ib ib; 1561 struct dma_fence *f = NULL; 1562 uint32_t scratch; 1563 uint32_t tmp = 0; 1564 long r; 1565 1566 r = amdgpu_gfx_scratch_get(adev, &scratch); 1567 if (r) { 1568 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 1569 return r; 1570 } 1571 WREG32(scratch, 0xCAFEDEAD); 1572 memset(&ib, 0, sizeof(ib)); 1573 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1574 if (r) { 1575 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1576 goto err1; 1577 } 1578 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1579 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1580 ib.ptr[2] = 0xDEADBEEF; 1581 ib.length_dw = 3; 1582 1583 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); 1584 if (r) 1585 goto err2; 1586 1587 r = dma_fence_wait_timeout(f, false, timeout); 1588 if (r == 0) { 1589 DRM_ERROR("amdgpu: IB test timed out\n"); 1590 r = -ETIMEDOUT; 1591 goto err2; 1592 } else if (r < 0) { 1593 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1594 goto err2; 1595 } 1596 tmp = RREG32(scratch); 1597 if (tmp == 0xDEADBEEF) { 1598 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 1599 r = 0; 1600 } else { 1601 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 1602 scratch, tmp); 1603 r = -EINVAL; 1604 } 1605 1606 err2: 1607 amdgpu_ib_free(adev, &ib, NULL); 1608 dma_fence_put(f); 1609 err1: 1610 amdgpu_gfx_scratch_free(adev, scratch); 1611 return r; 1612 } 1613 1614 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1615 { 1616 int i; 1617 if (enable) { 1618 WREG32(mmCP_ME_CNTL, 0); 1619 } else { 1620 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1621 CP_ME_CNTL__PFP_HALT_MASK | 1622 CP_ME_CNTL__CE_HALT_MASK)); 1623 WREG32(mmSCRATCH_UMSK, 0); 1624 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1625 adev->gfx.gfx_ring[i].ready = false; 1626 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1627 adev->gfx.compute_ring[i].ready = false; 1628 } 1629 udelay(50); 1630 } 1631 1632 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1633 { 1634 unsigned i; 1635 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1636 const struct gfx_firmware_header_v1_0 *ce_hdr; 1637 const struct gfx_firmware_header_v1_0 *me_hdr; 1638 const __le32 *fw_data; 1639 u32 fw_size; 1640 1641 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1642 return -EINVAL; 1643 1644 gfx_v6_0_cp_gfx_enable(adev, false); 1645 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1646 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1647 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1648 1649 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1650 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1651 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1652 1653 /* PFP */ 1654 fw_data = (const __le32 *) 1655 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1656 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1657 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1658 for (i = 0; i < fw_size; i++) 1659 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1660 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1661 1662 /* CE */ 1663 fw_data = (const __le32 *) 1664 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1665 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1666 WREG32(mmCP_CE_UCODE_ADDR, 0); 1667 for (i = 0; i < fw_size; i++) 1668 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1669 WREG32(mmCP_CE_UCODE_ADDR, 0); 1670 1671 /* ME */ 1672 fw_data = (const __be32 *) 1673 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1674 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1675 WREG32(mmCP_ME_RAM_WADDR, 0); 1676 for (i = 0; i < fw_size; i++) 1677 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1678 WREG32(mmCP_ME_RAM_WADDR, 0); 1679 1680 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1681 WREG32(mmCP_CE_UCODE_ADDR, 0); 1682 WREG32(mmCP_ME_RAM_WADDR, 0); 1683 WREG32(mmCP_ME_RAM_RADDR, 0); 1684 return 0; 1685 } 1686 1687 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 1688 { 1689 const struct cs_section_def *sect = NULL; 1690 const struct cs_extent_def *ext = NULL; 1691 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1692 int r, i; 1693 1694 r = amdgpu_ring_alloc(ring, 7 + 4); 1695 if (r) { 1696 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1697 return r; 1698 } 1699 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1700 amdgpu_ring_write(ring, 0x1); 1701 amdgpu_ring_write(ring, 0x0); 1702 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 1703 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1704 amdgpu_ring_write(ring, 0); 1705 amdgpu_ring_write(ring, 0); 1706 1707 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1708 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1709 amdgpu_ring_write(ring, 0xc000); 1710 amdgpu_ring_write(ring, 0xe000); 1711 amdgpu_ring_commit(ring); 1712 1713 gfx_v6_0_cp_gfx_enable(adev, true); 1714 1715 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 1716 if (r) { 1717 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1718 return r; 1719 } 1720 1721 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1722 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1723 1724 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1725 for (ext = sect->section; ext->extent != NULL; ++ext) { 1726 if (sect->id == SECT_CONTEXT) { 1727 amdgpu_ring_write(ring, 1728 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1729 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 1730 for (i = 0; i < ext->reg_count; i++) 1731 amdgpu_ring_write(ring, ext->extent[i]); 1732 } 1733 } 1734 } 1735 1736 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1737 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1738 1739 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1740 amdgpu_ring_write(ring, 0); 1741 1742 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1743 amdgpu_ring_write(ring, 0x00000316); 1744 amdgpu_ring_write(ring, 0x0000000e); 1745 amdgpu_ring_write(ring, 0x00000010); 1746 1747 amdgpu_ring_commit(ring); 1748 1749 return 0; 1750 } 1751 1752 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 1753 { 1754 struct amdgpu_ring *ring; 1755 u32 tmp; 1756 u32 rb_bufsz; 1757 int r; 1758 u64 rptr_addr; 1759 1760 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 1761 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1762 1763 /* Set the write pointer delay */ 1764 WREG32(mmCP_RB_WPTR_DELAY, 0); 1765 1766 WREG32(mmCP_DEBUG, 0); 1767 WREG32(mmSCRATCH_ADDR, 0); 1768 1769 /* ring 0 - compute and gfx */ 1770 /* Set ring buffer size */ 1771 ring = &adev->gfx.gfx_ring[0]; 1772 rb_bufsz = order_base_2(ring->ring_size / 8); 1773 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1774 1775 #ifdef __BIG_ENDIAN 1776 tmp |= BUF_SWAP_32BIT; 1777 #endif 1778 WREG32(mmCP_RB0_CNTL, tmp); 1779 1780 /* Initialize the ring buffer's read and write pointers */ 1781 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 1782 ring->wptr = 0; 1783 WREG32(mmCP_RB0_WPTR, ring->wptr); 1784 1785 /* set the wb address whether it's enabled or not */ 1786 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1787 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 1788 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1789 1790 WREG32(mmSCRATCH_UMSK, 0); 1791 1792 mdelay(1); 1793 WREG32(mmCP_RB0_CNTL, tmp); 1794 1795 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 1796 1797 /* start the rings */ 1798 gfx_v6_0_cp_gfx_start(adev); 1799 ring->ready = true; 1800 r = amdgpu_ring_test_ring(ring); 1801 if (r) { 1802 ring->ready = false; 1803 return r; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 1810 { 1811 return ring->adev->wb.wb[ring->rptr_offs]; 1812 } 1813 1814 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 1815 { 1816 struct amdgpu_device *adev = ring->adev; 1817 1818 if (ring == &adev->gfx.gfx_ring[0]) 1819 return RREG32(mmCP_RB0_WPTR); 1820 else if (ring == &adev->gfx.compute_ring[0]) 1821 return RREG32(mmCP_RB1_WPTR); 1822 else if (ring == &adev->gfx.compute_ring[1]) 1823 return RREG32(mmCP_RB2_WPTR); 1824 else 1825 BUG(); 1826 } 1827 1828 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 1829 { 1830 struct amdgpu_device *adev = ring->adev; 1831 1832 WREG32(mmCP_RB0_WPTR, ring->wptr); 1833 (void)RREG32(mmCP_RB0_WPTR); 1834 } 1835 1836 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 1837 { 1838 struct amdgpu_device *adev = ring->adev; 1839 1840 if (ring == &adev->gfx.compute_ring[0]) { 1841 WREG32(mmCP_RB1_WPTR, ring->wptr); 1842 (void)RREG32(mmCP_RB1_WPTR); 1843 } else if (ring == &adev->gfx.compute_ring[1]) { 1844 WREG32(mmCP_RB2_WPTR, ring->wptr); 1845 (void)RREG32(mmCP_RB2_WPTR); 1846 } else { 1847 BUG(); 1848 } 1849 1850 } 1851 1852 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 1853 { 1854 struct amdgpu_ring *ring; 1855 u32 tmp; 1856 u32 rb_bufsz; 1857 int i, r; 1858 u64 rptr_addr; 1859 1860 /* ring1 - compute only */ 1861 /* Set ring buffer size */ 1862 1863 ring = &adev->gfx.compute_ring[0]; 1864 rb_bufsz = order_base_2(ring->ring_size / 8); 1865 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1866 #ifdef __BIG_ENDIAN 1867 tmp |= BUF_SWAP_32BIT; 1868 #endif 1869 WREG32(mmCP_RB1_CNTL, tmp); 1870 1871 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 1872 ring->wptr = 0; 1873 WREG32(mmCP_RB1_WPTR, ring->wptr); 1874 1875 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1876 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 1877 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1878 1879 mdelay(1); 1880 WREG32(mmCP_RB1_CNTL, tmp); 1881 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 1882 1883 ring = &adev->gfx.compute_ring[1]; 1884 rb_bufsz = order_base_2(ring->ring_size / 8); 1885 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1886 #ifdef __BIG_ENDIAN 1887 tmp |= BUF_SWAP_32BIT; 1888 #endif 1889 WREG32(mmCP_RB2_CNTL, tmp); 1890 1891 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 1892 ring->wptr = 0; 1893 WREG32(mmCP_RB2_WPTR, ring->wptr); 1894 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1895 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 1896 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1897 1898 mdelay(1); 1899 WREG32(mmCP_RB2_CNTL, tmp); 1900 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 1901 1902 adev->gfx.compute_ring[0].ready = false; 1903 adev->gfx.compute_ring[1].ready = false; 1904 1905 for (i = 0; i < 2; i++) { 1906 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); 1907 if (r) 1908 return r; 1909 adev->gfx.compute_ring[i].ready = true; 1910 } 1911 1912 return 0; 1913 } 1914 1915 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 1916 { 1917 gfx_v6_0_cp_gfx_enable(adev, enable); 1918 } 1919 1920 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 1921 { 1922 return gfx_v6_0_cp_gfx_load_microcode(adev); 1923 } 1924 1925 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1926 bool enable) 1927 { 1928 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 1929 u32 mask; 1930 int i; 1931 1932 if (enable) 1933 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 1934 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 1935 else 1936 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 1937 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 1938 WREG32(mmCP_INT_CNTL_RING0, tmp); 1939 1940 if (!enable) { 1941 /* read a gfx register */ 1942 tmp = RREG32(mmDB_DEPTH_INFO); 1943 1944 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 1945 for (i = 0; i < adev->usec_timeout; i++) { 1946 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 1947 break; 1948 udelay(1); 1949 } 1950 } 1951 } 1952 1953 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 1954 { 1955 int r; 1956 1957 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 1958 1959 r = gfx_v6_0_cp_load_microcode(adev); 1960 if (r) 1961 return r; 1962 1963 r = gfx_v6_0_cp_gfx_resume(adev); 1964 if (r) 1965 return r; 1966 r = gfx_v6_0_cp_compute_resume(adev); 1967 if (r) 1968 return r; 1969 1970 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 1971 1972 return 0; 1973 } 1974 1975 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1976 { 1977 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 1978 uint32_t seq = ring->fence_drv.sync_seq; 1979 uint64_t addr = ring->fence_drv.gpu_addr; 1980 1981 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1982 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 1983 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 1984 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 1985 amdgpu_ring_write(ring, addr & 0xfffffffc); 1986 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1987 amdgpu_ring_write(ring, seq); 1988 amdgpu_ring_write(ring, 0xffffffff); 1989 amdgpu_ring_write(ring, 4); /* poll interval */ 1990 1991 if (usepfp) { 1992 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 1993 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1994 amdgpu_ring_write(ring, 0); 1995 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1996 amdgpu_ring_write(ring, 0); 1997 } 1998 } 1999 2000 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2001 unsigned vm_id, uint64_t pd_addr) 2002 { 2003 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2004 2005 /* write new base address */ 2006 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2007 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2008 WRITE_DATA_DST_SEL(0))); 2009 if (vm_id < 8) { 2010 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2011 } else { 2012 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2013 } 2014 amdgpu_ring_write(ring, 0); 2015 amdgpu_ring_write(ring, pd_addr >> 12); 2016 2017 /* bits 0-15 are the VM contexts0-15 */ 2018 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2019 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2020 WRITE_DATA_DST_SEL(0))); 2021 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2022 amdgpu_ring_write(ring, 0); 2023 amdgpu_ring_write(ring, 1 << vm_id); 2024 2025 /* wait for the invalidate to complete */ 2026 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2027 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2028 WAIT_REG_MEM_ENGINE(0))); /* me */ 2029 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2030 amdgpu_ring_write(ring, 0); 2031 amdgpu_ring_write(ring, 0); /* ref */ 2032 amdgpu_ring_write(ring, 0); /* mask */ 2033 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2034 2035 if (usepfp) { 2036 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2037 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2038 amdgpu_ring_write(ring, 0x0); 2039 2040 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2041 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2042 amdgpu_ring_write(ring, 0); 2043 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2044 amdgpu_ring_write(ring, 0); 2045 } 2046 } 2047 2048 2049 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) 2050 { 2051 int r; 2052 2053 if (adev->gfx.rlc.save_restore_obj) { 2054 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 2055 if (unlikely(r != 0)) 2056 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); 2057 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); 2058 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2059 2060 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); 2061 adev->gfx.rlc.save_restore_obj = NULL; 2062 } 2063 2064 if (adev->gfx.rlc.clear_state_obj) { 2065 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 2066 if (unlikely(r != 0)) 2067 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); 2068 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 2069 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2070 2071 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 2072 adev->gfx.rlc.clear_state_obj = NULL; 2073 } 2074 2075 if (adev->gfx.rlc.cp_table_obj) { 2076 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 2077 if (unlikely(r != 0)) 2078 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 2079 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); 2080 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 2081 2082 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); 2083 adev->gfx.rlc.cp_table_obj = NULL; 2084 } 2085 } 2086 2087 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2088 { 2089 const u32 *src_ptr; 2090 volatile u32 *dst_ptr; 2091 u32 dws, i; 2092 u64 reg_list_mc_addr; 2093 const struct cs_section_def *cs_data; 2094 int r; 2095 2096 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2097 adev->gfx.rlc.reg_list_size = 2098 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2099 2100 adev->gfx.rlc.cs_data = si_cs_data; 2101 src_ptr = adev->gfx.rlc.reg_list; 2102 dws = adev->gfx.rlc.reg_list_size; 2103 cs_data = adev->gfx.rlc.cs_data; 2104 2105 if (src_ptr) { 2106 /* save restore block */ 2107 if (adev->gfx.rlc.save_restore_obj == NULL) { 2108 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2109 AMDGPU_GEM_DOMAIN_VRAM, 2110 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2111 NULL, NULL, 2112 &adev->gfx.rlc.save_restore_obj); 2113 2114 if (r) { 2115 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); 2116 return r; 2117 } 2118 } 2119 2120 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 2121 if (unlikely(r != 0)) { 2122 gfx_v6_0_rlc_fini(adev); 2123 return r; 2124 } 2125 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, 2126 &adev->gfx.rlc.save_restore_gpu_addr); 2127 if (r) { 2128 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2129 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); 2130 gfx_v6_0_rlc_fini(adev); 2131 return r; 2132 } 2133 2134 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); 2135 if (r) { 2136 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); 2137 gfx_v6_0_rlc_fini(adev); 2138 return r; 2139 } 2140 /* write the sr buffer */ 2141 dst_ptr = adev->gfx.rlc.sr_ptr; 2142 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 2143 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 2144 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 2145 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2146 } 2147 2148 if (cs_data) { 2149 /* clear state block */ 2150 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2151 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2152 2153 if (adev->gfx.rlc.clear_state_obj == NULL) { 2154 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2155 AMDGPU_GEM_DOMAIN_VRAM, 2156 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2157 NULL, NULL, 2158 &adev->gfx.rlc.clear_state_obj); 2159 2160 if (r) { 2161 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2162 gfx_v6_0_rlc_fini(adev); 2163 return r; 2164 } 2165 } 2166 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 2167 if (unlikely(r != 0)) { 2168 gfx_v6_0_rlc_fini(adev); 2169 return r; 2170 } 2171 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, 2172 &adev->gfx.rlc.clear_state_gpu_addr); 2173 if (r) { 2174 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2175 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); 2176 gfx_v6_0_rlc_fini(adev); 2177 return r; 2178 } 2179 2180 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); 2181 if (r) { 2182 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); 2183 gfx_v6_0_rlc_fini(adev); 2184 return r; 2185 } 2186 /* set up the cs buffer */ 2187 dst_ptr = adev->gfx.rlc.cs_ptr; 2188 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2189 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2190 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2191 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2192 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2193 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2194 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2195 } 2196 2197 return 0; 2198 } 2199 2200 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2201 { 2202 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2203 2204 if (!enable) { 2205 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2206 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2207 } 2208 } 2209 2210 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2211 { 2212 int i; 2213 2214 for (i = 0; i < adev->usec_timeout; i++) { 2215 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2216 break; 2217 udelay(1); 2218 } 2219 2220 for (i = 0; i < adev->usec_timeout; i++) { 2221 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2222 break; 2223 udelay(1); 2224 } 2225 } 2226 2227 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2228 { 2229 u32 tmp; 2230 2231 tmp = RREG32(mmRLC_CNTL); 2232 if (tmp != rlc) 2233 WREG32(mmRLC_CNTL, rlc); 2234 } 2235 2236 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2237 { 2238 u32 data, orig; 2239 2240 orig = data = RREG32(mmRLC_CNTL); 2241 2242 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2243 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2244 WREG32(mmRLC_CNTL, data); 2245 2246 gfx_v6_0_wait_for_rlc_serdes(adev); 2247 } 2248 2249 return orig; 2250 } 2251 2252 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2253 { 2254 WREG32(mmRLC_CNTL, 0); 2255 2256 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2257 gfx_v6_0_wait_for_rlc_serdes(adev); 2258 } 2259 2260 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2261 { 2262 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2263 2264 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2265 2266 udelay(50); 2267 } 2268 2269 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2270 { 2271 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2272 udelay(50); 2273 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2274 udelay(50); 2275 } 2276 2277 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2278 { 2279 u32 tmp; 2280 2281 /* Enable LBPW only for DDR3 */ 2282 tmp = RREG32(mmMC_SEQ_MISC0); 2283 if ((tmp & 0xF0000000) == 0xB0000000) 2284 return true; 2285 return false; 2286 } 2287 2288 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2289 { 2290 } 2291 2292 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2293 { 2294 u32 i; 2295 const struct rlc_firmware_header_v1_0 *hdr; 2296 const __le32 *fw_data; 2297 u32 fw_size; 2298 2299 2300 if (!adev->gfx.rlc_fw) 2301 return -EINVAL; 2302 2303 gfx_v6_0_rlc_stop(adev); 2304 gfx_v6_0_rlc_reset(adev); 2305 gfx_v6_0_init_pg(adev); 2306 gfx_v6_0_init_cg(adev); 2307 2308 WREG32(mmRLC_RL_BASE, 0); 2309 WREG32(mmRLC_RL_SIZE, 0); 2310 WREG32(mmRLC_LB_CNTL, 0); 2311 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2312 WREG32(mmRLC_LB_CNTR_INIT, 0); 2313 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2314 2315 WREG32(mmRLC_MC_CNTL, 0); 2316 WREG32(mmRLC_UCODE_CNTL, 0); 2317 2318 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2319 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2320 fw_data = (const __le32 *) 2321 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2322 2323 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2324 2325 for (i = 0; i < fw_size; i++) { 2326 WREG32(mmRLC_UCODE_ADDR, i); 2327 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2328 } 2329 WREG32(mmRLC_UCODE_ADDR, 0); 2330 2331 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2332 gfx_v6_0_rlc_start(adev); 2333 2334 return 0; 2335 } 2336 2337 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2338 { 2339 u32 data, orig, tmp; 2340 2341 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2342 2343 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2344 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2345 2346 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2347 2348 tmp = gfx_v6_0_halt_rlc(adev); 2349 2350 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2351 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2352 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2353 2354 gfx_v6_0_wait_for_rlc_serdes(adev); 2355 gfx_v6_0_update_rlc(adev, tmp); 2356 2357 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2358 2359 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2360 } else { 2361 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2362 2363 RREG32(mmCB_CGTT_SCLK_CTRL); 2364 RREG32(mmCB_CGTT_SCLK_CTRL); 2365 RREG32(mmCB_CGTT_SCLK_CTRL); 2366 RREG32(mmCB_CGTT_SCLK_CTRL); 2367 2368 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2369 } 2370 2371 if (orig != data) 2372 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2373 2374 } 2375 2376 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2377 { 2378 2379 u32 data, orig, tmp = 0; 2380 2381 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2382 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2383 data = 0x96940200; 2384 if (orig != data) 2385 WREG32(mmCGTS_SM_CTRL_REG, data); 2386 2387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2388 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2389 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2390 if (orig != data) 2391 WREG32(mmCP_MEM_SLP_CNTL, data); 2392 } 2393 2394 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2395 data &= 0xffffffc0; 2396 if (orig != data) 2397 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2398 2399 tmp = gfx_v6_0_halt_rlc(adev); 2400 2401 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2402 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2403 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2404 2405 gfx_v6_0_update_rlc(adev, tmp); 2406 } else { 2407 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2408 data |= 0x00000003; 2409 if (orig != data) 2410 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2411 2412 data = RREG32(mmCP_MEM_SLP_CNTL); 2413 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2414 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2415 WREG32(mmCP_MEM_SLP_CNTL, data); 2416 } 2417 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2418 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2419 if (orig != data) 2420 WREG32(mmCGTS_SM_CTRL_REG, data); 2421 2422 tmp = gfx_v6_0_halt_rlc(adev); 2423 2424 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2425 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2426 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2427 2428 gfx_v6_0_update_rlc(adev, tmp); 2429 } 2430 } 2431 /* 2432 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2433 bool enable) 2434 { 2435 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2436 if (enable) { 2437 gfx_v6_0_enable_mgcg(adev, true); 2438 gfx_v6_0_enable_cgcg(adev, true); 2439 } else { 2440 gfx_v6_0_enable_cgcg(adev, false); 2441 gfx_v6_0_enable_mgcg(adev, false); 2442 } 2443 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2444 } 2445 */ 2446 2447 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2448 bool enable) 2449 { 2450 } 2451 2452 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2453 bool enable) 2454 { 2455 } 2456 2457 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2458 { 2459 u32 data, orig; 2460 2461 orig = data = RREG32(mmRLC_PG_CNTL); 2462 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2463 data &= ~0x8000; 2464 else 2465 data |= 0x8000; 2466 if (orig != data) 2467 WREG32(mmRLC_PG_CNTL, data); 2468 } 2469 2470 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2471 { 2472 } 2473 /* 2474 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2475 { 2476 const __le32 *fw_data; 2477 volatile u32 *dst_ptr; 2478 int me, i, max_me = 4; 2479 u32 bo_offset = 0; 2480 u32 table_offset, table_size; 2481 2482 if (adev->asic_type == CHIP_KAVERI) 2483 max_me = 5; 2484 2485 if (adev->gfx.rlc.cp_table_ptr == NULL) 2486 return; 2487 2488 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2489 for (me = 0; me < max_me; me++) { 2490 if (me == 0) { 2491 const struct gfx_firmware_header_v1_0 *hdr = 2492 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2493 fw_data = (const __le32 *) 2494 (adev->gfx.ce_fw->data + 2495 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2496 table_offset = le32_to_cpu(hdr->jt_offset); 2497 table_size = le32_to_cpu(hdr->jt_size); 2498 } else if (me == 1) { 2499 const struct gfx_firmware_header_v1_0 *hdr = 2500 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2501 fw_data = (const __le32 *) 2502 (adev->gfx.pfp_fw->data + 2503 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2504 table_offset = le32_to_cpu(hdr->jt_offset); 2505 table_size = le32_to_cpu(hdr->jt_size); 2506 } else if (me == 2) { 2507 const struct gfx_firmware_header_v1_0 *hdr = 2508 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2509 fw_data = (const __le32 *) 2510 (adev->gfx.me_fw->data + 2511 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2512 table_offset = le32_to_cpu(hdr->jt_offset); 2513 table_size = le32_to_cpu(hdr->jt_size); 2514 } else if (me == 3) { 2515 const struct gfx_firmware_header_v1_0 *hdr = 2516 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2517 fw_data = (const __le32 *) 2518 (adev->gfx.mec_fw->data + 2519 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2520 table_offset = le32_to_cpu(hdr->jt_offset); 2521 table_size = le32_to_cpu(hdr->jt_size); 2522 } else { 2523 const struct gfx_firmware_header_v1_0 *hdr = 2524 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2525 fw_data = (const __le32 *) 2526 (adev->gfx.mec2_fw->data + 2527 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2528 table_offset = le32_to_cpu(hdr->jt_offset); 2529 table_size = le32_to_cpu(hdr->jt_size); 2530 } 2531 2532 for (i = 0; i < table_size; i ++) { 2533 dst_ptr[bo_offset + i] = 2534 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2535 } 2536 2537 bo_offset += table_size; 2538 } 2539 } 2540 */ 2541 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2542 bool enable) 2543 { 2544 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2545 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2546 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2547 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2548 } else { 2549 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2550 (void)RREG32(mmDB_RENDER_CONTROL); 2551 } 2552 } 2553 2554 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev, 2555 u32 se, u32 sh) 2556 { 2557 2558 u32 mask = 0, tmp, tmp1; 2559 int i; 2560 2561 mutex_lock(&adev->grbm_idx_mutex); 2562 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff); 2563 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 2564 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 2565 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2566 mutex_unlock(&adev->grbm_idx_mutex); 2567 2568 tmp &= 0xffff0000; 2569 2570 tmp |= tmp1; 2571 tmp >>= 16; 2572 2573 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { 2574 mask <<= 1; 2575 mask |= 1; 2576 } 2577 2578 return (~tmp) & mask; 2579 } 2580 2581 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2582 { 2583 u32 i, j, k, active_cu_number = 0; 2584 2585 u32 mask, counter, cu_bitmap; 2586 u32 tmp = 0; 2587 2588 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2589 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2590 mask = 1; 2591 cu_bitmap = 0; 2592 counter = 0; 2593 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 2594 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) { 2595 if (counter < 2) 2596 cu_bitmap |= mask; 2597 counter++; 2598 } 2599 mask <<= 1; 2600 } 2601 2602 active_cu_number += counter; 2603 tmp |= (cu_bitmap << (i * 16 + j * 8)); 2604 } 2605 } 2606 2607 WREG32(mmRLC_PG_AO_CU_MASK, tmp); 2608 WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number); 2609 } 2610 2611 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2612 bool enable) 2613 { 2614 u32 data, orig; 2615 2616 orig = data = RREG32(mmRLC_PG_CNTL); 2617 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2618 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2619 else 2620 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2621 if (orig != data) 2622 WREG32(mmRLC_PG_CNTL, data); 2623 } 2624 2625 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2626 bool enable) 2627 { 2628 u32 data, orig; 2629 2630 orig = data = RREG32(mmRLC_PG_CNTL); 2631 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2632 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2633 else 2634 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2635 if (orig != data) 2636 WREG32(mmRLC_PG_CNTL, data); 2637 } 2638 2639 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2640 { 2641 u32 tmp; 2642 2643 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2644 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2645 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2646 2647 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2648 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2649 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2650 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2651 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2652 } 2653 2654 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2655 { 2656 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2657 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2658 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2659 } 2660 2661 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2662 { 2663 u32 count = 0; 2664 const struct cs_section_def *sect = NULL; 2665 const struct cs_extent_def *ext = NULL; 2666 2667 if (adev->gfx.rlc.cs_data == NULL) 2668 return 0; 2669 2670 /* begin clear state */ 2671 count += 2; 2672 /* context control state */ 2673 count += 3; 2674 2675 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2676 for (ext = sect->section; ext->extent != NULL; ++ext) { 2677 if (sect->id == SECT_CONTEXT) 2678 count += 2 + ext->reg_count; 2679 else 2680 return 0; 2681 } 2682 } 2683 /* pa_sc_raster_config */ 2684 count += 3; 2685 /* end clear state */ 2686 count += 2; 2687 /* clear state */ 2688 count += 2; 2689 2690 return count; 2691 } 2692 2693 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2694 volatile u32 *buffer) 2695 { 2696 u32 count = 0, i; 2697 const struct cs_section_def *sect = NULL; 2698 const struct cs_extent_def *ext = NULL; 2699 2700 if (adev->gfx.rlc.cs_data == NULL) 2701 return; 2702 if (buffer == NULL) 2703 return; 2704 2705 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2706 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2708 buffer[count++] = cpu_to_le32(0x80000000); 2709 buffer[count++] = cpu_to_le32(0x80000000); 2710 2711 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2712 for (ext = sect->section; ext->extent != NULL; ++ext) { 2713 if (sect->id == SECT_CONTEXT) { 2714 buffer[count++] = 2715 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2716 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2717 for (i = 0; i < ext->reg_count; i++) 2718 buffer[count++] = cpu_to_le32(ext->extent[i]); 2719 } else { 2720 return; 2721 } 2722 } 2723 } 2724 2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2726 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2727 2728 switch (adev->asic_type) { 2729 case CHIP_TAHITI: 2730 case CHIP_PITCAIRN: 2731 buffer[count++] = cpu_to_le32(0x2a00126a); 2732 break; 2733 case CHIP_VERDE: 2734 buffer[count++] = cpu_to_le32(0x0000124a); 2735 break; 2736 case CHIP_OLAND: 2737 buffer[count++] = cpu_to_le32(0x00000082); 2738 break; 2739 case CHIP_HAINAN: 2740 buffer[count++] = cpu_to_le32(0x00000000); 2741 break; 2742 default: 2743 buffer[count++] = cpu_to_le32(0x00000000); 2744 break; 2745 } 2746 2747 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2748 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2749 2750 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2751 buffer[count++] = cpu_to_le32(0); 2752 } 2753 2754 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2755 { 2756 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2757 AMD_PG_SUPPORT_GFX_SMG | 2758 AMD_PG_SUPPORT_GFX_DMG | 2759 AMD_PG_SUPPORT_CP | 2760 AMD_PG_SUPPORT_GDS | 2761 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2762 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2763 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2764 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2765 gfx_v6_0_init_gfx_cgpg(adev); 2766 gfx_v6_0_enable_cp_pg(adev, true); 2767 gfx_v6_0_enable_gds_pg(adev, true); 2768 } else { 2769 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2770 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2771 2772 } 2773 gfx_v6_0_init_ao_cu_mask(adev); 2774 gfx_v6_0_update_gfx_pg(adev, true); 2775 } else { 2776 2777 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2778 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2779 } 2780 } 2781 2782 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2783 { 2784 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2785 AMD_PG_SUPPORT_GFX_SMG | 2786 AMD_PG_SUPPORT_GFX_DMG | 2787 AMD_PG_SUPPORT_CP | 2788 AMD_PG_SUPPORT_GDS | 2789 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2790 gfx_v6_0_update_gfx_pg(adev, false); 2791 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2792 gfx_v6_0_enable_cp_pg(adev, false); 2793 gfx_v6_0_enable_gds_pg(adev, false); 2794 } 2795 } 2796 } 2797 2798 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2799 { 2800 uint64_t clock; 2801 2802 mutex_lock(&adev->gfx.gpu_clock_mutex); 2803 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2804 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2805 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2806 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2807 return clock; 2808 } 2809 2810 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2811 { 2812 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2813 gfx_v6_0_ring_emit_vgt_flush(ring); 2814 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2815 amdgpu_ring_write(ring, 0x80000000); 2816 amdgpu_ring_write(ring, 0); 2817 } 2818 2819 2820 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2821 { 2822 WREG32(mmSQ_IND_INDEX, 2823 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2824 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2825 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2826 (SQ_IND_INDEX__FORCE_READ_MASK)); 2827 return RREG32(mmSQ_IND_DATA); 2828 } 2829 2830 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2831 uint32_t wave, uint32_t thread, 2832 uint32_t regno, uint32_t num, uint32_t *out) 2833 { 2834 WREG32(mmSQ_IND_INDEX, 2835 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2836 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2837 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2838 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2839 (SQ_IND_INDEX__FORCE_READ_MASK) | 2840 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2841 while (num--) 2842 *(out++) = RREG32(mmSQ_IND_DATA); 2843 } 2844 2845 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2846 { 2847 /* type 0 wave data */ 2848 dst[(*no_fields)++] = 0; 2849 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2850 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2851 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2852 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2853 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2854 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2855 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2856 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2857 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2858 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2859 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2860 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2861 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 2862 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 2863 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 2864 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 2865 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2866 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2867 } 2868 2869 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 2870 uint32_t wave, uint32_t start, 2871 uint32_t size, uint32_t *dst) 2872 { 2873 wave_read_regs( 2874 adev, simd, wave, 0, 2875 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 2876 } 2877 2878 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2879 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2880 .select_se_sh = &gfx_v6_0_select_se_sh, 2881 .read_wave_data = &gfx_v6_0_read_wave_data, 2882 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 2883 }; 2884 2885 static int gfx_v6_0_early_init(void *handle) 2886 { 2887 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2888 2889 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 2890 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 2891 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 2892 gfx_v6_0_set_ring_funcs(adev); 2893 gfx_v6_0_set_irq_funcs(adev); 2894 2895 return 0; 2896 } 2897 2898 static int gfx_v6_0_sw_init(void *handle) 2899 { 2900 struct amdgpu_ring *ring; 2901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2902 int i, r; 2903 2904 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 2905 if (r) 2906 return r; 2907 2908 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 2909 if (r) 2910 return r; 2911 2912 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 2913 if (r) 2914 return r; 2915 2916 gfx_v6_0_scratch_init(adev); 2917 2918 r = gfx_v6_0_init_microcode(adev); 2919 if (r) { 2920 DRM_ERROR("Failed to load gfx firmware!\n"); 2921 return r; 2922 } 2923 2924 r = gfx_v6_0_rlc_init(adev); 2925 if (r) { 2926 DRM_ERROR("Failed to init rlc BOs!\n"); 2927 return r; 2928 } 2929 2930 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2931 ring = &adev->gfx.gfx_ring[i]; 2932 ring->ring_obj = NULL; 2933 sprintf(ring->name, "gfx"); 2934 r = amdgpu_ring_init(adev, ring, 1024, 2935 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 2936 if (r) 2937 return r; 2938 } 2939 2940 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2941 unsigned irq_type; 2942 2943 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 2944 DRM_ERROR("Too many (%d) compute rings!\n", i); 2945 break; 2946 } 2947 ring = &adev->gfx.compute_ring[i]; 2948 ring->ring_obj = NULL; 2949 ring->use_doorbell = false; 2950 ring->doorbell_index = 0; 2951 ring->me = 1; 2952 ring->pipe = i; 2953 ring->queue = i; 2954 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 2955 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 2956 r = amdgpu_ring_init(adev, ring, 1024, 2957 &adev->gfx.eop_irq, irq_type); 2958 if (r) 2959 return r; 2960 } 2961 2962 return r; 2963 } 2964 2965 static int gfx_v6_0_sw_fini(void *handle) 2966 { 2967 int i; 2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2969 2970 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 2971 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 2972 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); 2973 2974 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2975 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2976 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2977 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2978 2979 gfx_v6_0_rlc_fini(adev); 2980 2981 return 0; 2982 } 2983 2984 static int gfx_v6_0_hw_init(void *handle) 2985 { 2986 int r; 2987 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2988 2989 gfx_v6_0_gpu_init(adev); 2990 2991 r = gfx_v6_0_rlc_resume(adev); 2992 if (r) 2993 return r; 2994 2995 r = gfx_v6_0_cp_resume(adev); 2996 if (r) 2997 return r; 2998 2999 adev->gfx.ce_ram_size = 0x8000; 3000 3001 return r; 3002 } 3003 3004 static int gfx_v6_0_hw_fini(void *handle) 3005 { 3006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3007 3008 gfx_v6_0_cp_enable(adev, false); 3009 gfx_v6_0_rlc_stop(adev); 3010 gfx_v6_0_fini_pg(adev); 3011 3012 return 0; 3013 } 3014 3015 static int gfx_v6_0_suspend(void *handle) 3016 { 3017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3018 3019 return gfx_v6_0_hw_fini(adev); 3020 } 3021 3022 static int gfx_v6_0_resume(void *handle) 3023 { 3024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3025 3026 return gfx_v6_0_hw_init(adev); 3027 } 3028 3029 static bool gfx_v6_0_is_idle(void *handle) 3030 { 3031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3032 3033 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3034 return false; 3035 else 3036 return true; 3037 } 3038 3039 static int gfx_v6_0_wait_for_idle(void *handle) 3040 { 3041 unsigned i; 3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3043 3044 for (i = 0; i < adev->usec_timeout; i++) { 3045 if (gfx_v6_0_is_idle(handle)) 3046 return 0; 3047 udelay(1); 3048 } 3049 return -ETIMEDOUT; 3050 } 3051 3052 static int gfx_v6_0_soft_reset(void *handle) 3053 { 3054 return 0; 3055 } 3056 3057 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3058 enum amdgpu_interrupt_state state) 3059 { 3060 u32 cp_int_cntl; 3061 3062 switch (state) { 3063 case AMDGPU_IRQ_STATE_DISABLE: 3064 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3065 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3066 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3067 break; 3068 case AMDGPU_IRQ_STATE_ENABLE: 3069 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3070 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3071 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3072 break; 3073 default: 3074 break; 3075 } 3076 } 3077 3078 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3079 int ring, 3080 enum amdgpu_interrupt_state state) 3081 { 3082 u32 cp_int_cntl; 3083 switch (state){ 3084 case AMDGPU_IRQ_STATE_DISABLE: 3085 if (ring == 0) { 3086 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3087 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3088 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3089 break; 3090 } else { 3091 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3092 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3093 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3094 break; 3095 3096 } 3097 case AMDGPU_IRQ_STATE_ENABLE: 3098 if (ring == 0) { 3099 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3100 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3101 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3102 break; 3103 } else { 3104 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3105 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3106 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3107 break; 3108 3109 } 3110 3111 default: 3112 BUG(); 3113 break; 3114 3115 } 3116 } 3117 3118 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3119 struct amdgpu_irq_src *src, 3120 unsigned type, 3121 enum amdgpu_interrupt_state state) 3122 { 3123 u32 cp_int_cntl; 3124 3125 switch (state) { 3126 case AMDGPU_IRQ_STATE_DISABLE: 3127 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3128 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3129 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3130 break; 3131 case AMDGPU_IRQ_STATE_ENABLE: 3132 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3133 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3134 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3135 break; 3136 default: 3137 break; 3138 } 3139 3140 return 0; 3141 } 3142 3143 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3144 struct amdgpu_irq_src *src, 3145 unsigned type, 3146 enum amdgpu_interrupt_state state) 3147 { 3148 u32 cp_int_cntl; 3149 3150 switch (state) { 3151 case AMDGPU_IRQ_STATE_DISABLE: 3152 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3153 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3154 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3155 break; 3156 case AMDGPU_IRQ_STATE_ENABLE: 3157 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3158 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3159 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 return 0; 3166 } 3167 3168 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3169 struct amdgpu_irq_src *src, 3170 unsigned type, 3171 enum amdgpu_interrupt_state state) 3172 { 3173 switch (type) { 3174 case AMDGPU_CP_IRQ_GFX_EOP: 3175 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3176 break; 3177 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3178 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3179 break; 3180 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3181 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3182 break; 3183 default: 3184 break; 3185 } 3186 return 0; 3187 } 3188 3189 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3190 struct amdgpu_irq_src *source, 3191 struct amdgpu_iv_entry *entry) 3192 { 3193 switch (entry->ring_id) { 3194 case 0: 3195 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3196 break; 3197 case 1: 3198 case 2: 3199 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3200 break; 3201 default: 3202 break; 3203 } 3204 return 0; 3205 } 3206 3207 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3208 struct amdgpu_irq_src *source, 3209 struct amdgpu_iv_entry *entry) 3210 { 3211 DRM_ERROR("Illegal register access in command stream\n"); 3212 schedule_work(&adev->reset_work); 3213 return 0; 3214 } 3215 3216 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3217 struct amdgpu_irq_src *source, 3218 struct amdgpu_iv_entry *entry) 3219 { 3220 DRM_ERROR("Illegal instruction in command stream\n"); 3221 schedule_work(&adev->reset_work); 3222 return 0; 3223 } 3224 3225 static int gfx_v6_0_set_clockgating_state(void *handle, 3226 enum amd_clockgating_state state) 3227 { 3228 bool gate = false; 3229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3230 3231 if (state == AMD_CG_STATE_GATE) 3232 gate = true; 3233 3234 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3235 if (gate) { 3236 gfx_v6_0_enable_mgcg(adev, true); 3237 gfx_v6_0_enable_cgcg(adev, true); 3238 } else { 3239 gfx_v6_0_enable_cgcg(adev, false); 3240 gfx_v6_0_enable_mgcg(adev, false); 3241 } 3242 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3243 3244 return 0; 3245 } 3246 3247 static int gfx_v6_0_set_powergating_state(void *handle, 3248 enum amd_powergating_state state) 3249 { 3250 bool gate = false; 3251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3252 3253 if (state == AMD_PG_STATE_GATE) 3254 gate = true; 3255 3256 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3257 AMD_PG_SUPPORT_GFX_SMG | 3258 AMD_PG_SUPPORT_GFX_DMG | 3259 AMD_PG_SUPPORT_CP | 3260 AMD_PG_SUPPORT_GDS | 3261 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3262 gfx_v6_0_update_gfx_pg(adev, gate); 3263 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3264 gfx_v6_0_enable_cp_pg(adev, gate); 3265 gfx_v6_0_enable_gds_pg(adev, gate); 3266 } 3267 } 3268 3269 return 0; 3270 } 3271 3272 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3273 .name = "gfx_v6_0", 3274 .early_init = gfx_v6_0_early_init, 3275 .late_init = NULL, 3276 .sw_init = gfx_v6_0_sw_init, 3277 .sw_fini = gfx_v6_0_sw_fini, 3278 .hw_init = gfx_v6_0_hw_init, 3279 .hw_fini = gfx_v6_0_hw_fini, 3280 .suspend = gfx_v6_0_suspend, 3281 .resume = gfx_v6_0_resume, 3282 .is_idle = gfx_v6_0_is_idle, 3283 .wait_for_idle = gfx_v6_0_wait_for_idle, 3284 .soft_reset = gfx_v6_0_soft_reset, 3285 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3286 .set_powergating_state = gfx_v6_0_set_powergating_state, 3287 }; 3288 3289 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3290 .type = AMDGPU_RING_TYPE_GFX, 3291 .align_mask = 0xff, 3292 .nop = 0x80000000, 3293 .get_rptr = gfx_v6_0_ring_get_rptr, 3294 .get_wptr = gfx_v6_0_ring_get_wptr, 3295 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3296 .emit_frame_size = 3297 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3298 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3299 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3300 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3301 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3302 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3303 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3304 .emit_ib = gfx_v6_0_ring_emit_ib, 3305 .emit_fence = gfx_v6_0_ring_emit_fence, 3306 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3307 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3308 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3309 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3310 .test_ring = gfx_v6_0_ring_test_ring, 3311 .test_ib = gfx_v6_0_ring_test_ib, 3312 .insert_nop = amdgpu_ring_insert_nop, 3313 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3314 }; 3315 3316 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3317 .type = AMDGPU_RING_TYPE_COMPUTE, 3318 .align_mask = 0xff, 3319 .nop = 0x80000000, 3320 .get_rptr = gfx_v6_0_ring_get_rptr, 3321 .get_wptr = gfx_v6_0_ring_get_wptr, 3322 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3323 .emit_frame_size = 3324 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3325 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3326 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3327 17 + /* gfx_v6_0_ring_emit_vm_flush */ 3328 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3329 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3330 .emit_ib = gfx_v6_0_ring_emit_ib, 3331 .emit_fence = gfx_v6_0_ring_emit_fence, 3332 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3333 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3334 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3335 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3336 .test_ring = gfx_v6_0_ring_test_ring, 3337 .test_ib = gfx_v6_0_ring_test_ib, 3338 .insert_nop = amdgpu_ring_insert_nop, 3339 }; 3340 3341 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3342 { 3343 int i; 3344 3345 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3346 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3347 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3348 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3349 } 3350 3351 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3352 .set = gfx_v6_0_set_eop_interrupt_state, 3353 .process = gfx_v6_0_eop_irq, 3354 }; 3355 3356 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3357 .set = gfx_v6_0_set_priv_reg_fault_state, 3358 .process = gfx_v6_0_priv_reg_irq, 3359 }; 3360 3361 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3362 .set = gfx_v6_0_set_priv_inst_fault_state, 3363 .process = gfx_v6_0_priv_inst_irq, 3364 }; 3365 3366 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3367 { 3368 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3369 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3370 3371 adev->gfx.priv_reg_irq.num_types = 1; 3372 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3373 3374 adev->gfx.priv_inst_irq.num_types = 1; 3375 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3376 } 3377 3378 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3379 { 3380 int i, j, k, counter, active_cu_number = 0; 3381 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3382 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3383 3384 memset(cu_info, 0, sizeof(*cu_info)); 3385 3386 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3387 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3388 mask = 1; 3389 ao_bitmap = 0; 3390 counter = 0; 3391 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j); 3392 cu_info->bitmap[i][j] = bitmap; 3393 3394 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 3395 if (bitmap & mask) { 3396 if (counter < 2) 3397 ao_bitmap |= mask; 3398 counter ++; 3399 } 3400 mask <<= 1; 3401 } 3402 active_cu_number += counter; 3403 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3404 } 3405 } 3406 3407 cu_info->number = active_cu_number; 3408 cu_info->ao_cu_mask = ao_cu_mask; 3409 } 3410 3411 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3412 { 3413 .type = AMD_IP_BLOCK_TYPE_GFX, 3414 .major = 6, 3415 .minor = 0, 3416 .rev = 0, 3417 .funcs = &gfx_v6_0_ip_funcs, 3418 }; 3419