1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_si.h" 31 #include "si.h" 32 #include "sid.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 37 #include "oss/oss_1_0_d.h" 38 #include "oss/oss_1_0_sh_mask.h" 39 40 #include "gca/gfx_6_0_d.h" 41 #include "gca/gfx_6_0_sh_mask.h" 42 #include "gca/gfx_7_2_enum.h" 43 44 #include "gmc/gmc_6_0_d.h" 45 #include "gmc/gmc_6_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "si_enums.h" 51 52 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 53 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 54 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 55 56 #define GFX6_NUM_GFX_RINGS 1 57 #define GFX6_NUM_COMPUTE_RINGS 2 58 59 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 61 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 62 63 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 65 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 66 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 67 68 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 70 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 75 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 77 78 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 80 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 81 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 85 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 87 88 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 89 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); 90 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 91 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 92 93 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 94 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 95 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 96 #define MICRO_TILE_MODE(x) ((x) << 0) 97 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 98 #define BANK_WIDTH(x) ((x) << 14) 99 #define BANK_HEIGHT(x) ((x) << 16) 100 #define MACRO_TILE_ASPECT(x) ((x) << 18) 101 #define NUM_BANKS(x) ((x) << 20) 102 103 static const u32 verde_rlc_save_restore_register_list[] = 104 { 105 (0x8000 << 16) | (0x98f4 >> 2), 106 0x00000000, 107 (0x8040 << 16) | (0x98f4 >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0xe80 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0xe80 >> 2), 112 0x00000000, 113 (0x8000 << 16) | (0x89bc >> 2), 114 0x00000000, 115 (0x8040 << 16) | (0x89bc >> 2), 116 0x00000000, 117 (0x8000 << 16) | (0x8c1c >> 2), 118 0x00000000, 119 (0x8040 << 16) | (0x8c1c >> 2), 120 0x00000000, 121 (0x9c00 << 16) | (0x98f0 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0xe7c >> 2), 124 0x00000000, 125 (0x8000 << 16) | (0x9148 >> 2), 126 0x00000000, 127 (0x8040 << 16) | (0x9148 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x9150 >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x897c >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x8d8c >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0xac54 >> 2), 136 0X00000000, 137 0x3, 138 (0x9c00 << 16) | (0x98f8 >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9910 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9914 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9918 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x991c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9920 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9924 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9928 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x992c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9930 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9934 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9938 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x993c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9940 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9944 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9948 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x994c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9950 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9954 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9958 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x995c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9960 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9964 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9968 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x996c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x9970 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x9974 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x9978 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x997c >> 2), 195 0x00000000, 196 (0x9c00 << 16) | (0x9980 >> 2), 197 0x00000000, 198 (0x9c00 << 16) | (0x9984 >> 2), 199 0x00000000, 200 (0x9c00 << 16) | (0x9988 >> 2), 201 0x00000000, 202 (0x9c00 << 16) | (0x998c >> 2), 203 0x00000000, 204 (0x9c00 << 16) | (0x8c00 >> 2), 205 0x00000000, 206 (0x9c00 << 16) | (0x8c14 >> 2), 207 0x00000000, 208 (0x9c00 << 16) | (0x8c04 >> 2), 209 0x00000000, 210 (0x9c00 << 16) | (0x8c08 >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x9b7c >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x9b7c >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0xe84 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0xe84 >> 2), 219 0x00000000, 220 (0x8000 << 16) | (0x89c0 >> 2), 221 0x00000000, 222 (0x8040 << 16) | (0x89c0 >> 2), 223 0x00000000, 224 (0x8000 << 16) | (0x914c >> 2), 225 0x00000000, 226 (0x8040 << 16) | (0x914c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x8c20 >> 2), 229 0x00000000, 230 (0x8040 << 16) | (0x8c20 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x9354 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x9354 >> 2), 235 0x00000000, 236 (0x9c00 << 16) | (0x9060 >> 2), 237 0x00000000, 238 (0x9c00 << 16) | (0x9364 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x9100 >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x913c >> 2), 243 0x00000000, 244 (0x8000 << 16) | (0x90e0 >> 2), 245 0x00000000, 246 (0x8000 << 16) | (0x90e4 >> 2), 247 0x00000000, 248 (0x8000 << 16) | (0x90e8 >> 2), 249 0x00000000, 250 (0x8040 << 16) | (0x90e0 >> 2), 251 0x00000000, 252 (0x8040 << 16) | (0x90e4 >> 2), 253 0x00000000, 254 (0x8040 << 16) | (0x90e8 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x8bcc >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x8b24 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0x88c4 >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0x8e50 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0x8c0c >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0x8e58 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0x8e5c >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x9508 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x950c >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x9494 >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0xac0c >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0xac10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0xac14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0xae00 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0xac08 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x88d4 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x88c8 >> 2), 289 0x00000000, 290 (0x9c00 << 16) | (0x88cc >> 2), 291 0x00000000, 292 (0x9c00 << 16) | (0x89b0 >> 2), 293 0x00000000, 294 (0x9c00 << 16) | (0x8b10 >> 2), 295 0x00000000, 296 (0x9c00 << 16) | (0x8a14 >> 2), 297 0x00000000, 298 (0x9c00 << 16) | (0x9830 >> 2), 299 0x00000000, 300 (0x9c00 << 16) | (0x9834 >> 2), 301 0x00000000, 302 (0x9c00 << 16) | (0x9838 >> 2), 303 0x00000000, 304 (0x9c00 << 16) | (0x9a10 >> 2), 305 0x00000000, 306 (0x8000 << 16) | (0x9870 >> 2), 307 0x00000000, 308 (0x8000 << 16) | (0x9874 >> 2), 309 0x00000000, 310 (0x8001 << 16) | (0x9870 >> 2), 311 0x00000000, 312 (0x8001 << 16) | (0x9874 >> 2), 313 0x00000000, 314 (0x8040 << 16) | (0x9870 >> 2), 315 0x00000000, 316 (0x8040 << 16) | (0x9874 >> 2), 317 0x00000000, 318 (0x8041 << 16) | (0x9870 >> 2), 319 0x00000000, 320 (0x8041 << 16) | (0x9874 >> 2), 321 0x00000000, 322 0x00000000 323 }; 324 325 static void gfx_v6_0_free_microcode(struct amdgpu_device *adev) 326 { 327 amdgpu_ucode_release(&adev->gfx.pfp_fw); 328 amdgpu_ucode_release(&adev->gfx.me_fw); 329 amdgpu_ucode_release(&adev->gfx.ce_fw); 330 amdgpu_ucode_release(&adev->gfx.rlc_fw); 331 } 332 333 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 334 { 335 const char *chip_name; 336 int err; 337 const struct gfx_firmware_header_v1_0 *cp_hdr; 338 const struct rlc_firmware_header_v1_0 *rlc_hdr; 339 340 DRM_DEBUG("\n"); 341 342 switch (adev->asic_type) { 343 case CHIP_TAHITI: 344 chip_name = "tahiti"; 345 break; 346 case CHIP_PITCAIRN: 347 chip_name = "pitcairn"; 348 break; 349 case CHIP_VERDE: 350 chip_name = "verde"; 351 break; 352 case CHIP_OLAND: 353 chip_name = "oland"; 354 break; 355 case CHIP_HAINAN: 356 chip_name = "hainan"; 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 363 AMDGPU_UCODE_REQUIRED, 364 "amdgpu/%s_pfp.bin", chip_name); 365 if (err) 366 goto out; 367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 368 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 369 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 370 371 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 372 AMDGPU_UCODE_REQUIRED, 373 "amdgpu/%s_me.bin", chip_name); 374 if (err) 375 goto out; 376 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 377 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 378 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 379 380 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 381 AMDGPU_UCODE_REQUIRED, 382 "amdgpu/%s_ce.bin", chip_name); 383 if (err) 384 goto out; 385 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 386 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 387 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 388 389 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 390 AMDGPU_UCODE_REQUIRED, 391 "amdgpu/%s_rlc.bin", chip_name); 392 if (err) 393 goto out; 394 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 395 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 396 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 397 398 out: 399 if (err) { 400 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); 401 amdgpu_ucode_release(&adev->gfx.pfp_fw); 402 amdgpu_ucode_release(&adev->gfx.me_fw); 403 amdgpu_ucode_release(&adev->gfx.ce_fw); 404 amdgpu_ucode_release(&adev->gfx.rlc_fw); 405 } 406 return err; 407 } 408 409 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 410 { 411 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 412 u32 reg_offset, split_equal_to_row_size, *tilemode; 413 414 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 415 tilemode = adev->gfx.config.tile_mode_array; 416 417 switch (adev->gfx.config.mem_row_size_in_kb) { 418 case 1: 419 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 420 break; 421 case 2: 422 default: 423 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 424 break; 425 case 4: 426 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 427 break; 428 } 429 430 if (adev->asic_type == CHIP_VERDE) { 431 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 432 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 433 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 438 NUM_BANKS(ADDR_SURF_16_BANK); 439 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 446 NUM_BANKS(ADDR_SURF_16_BANK); 447 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 449 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 450 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 454 NUM_BANKS(ADDR_SURF_16_BANK); 455 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 456 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 457 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 460 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 461 NUM_BANKS(ADDR_SURF_8_BANK) | 462 TILE_SPLIT(split_equal_to_row_size); 463 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 464 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 465 PIPE_CONFIG(ADDR_SURF_P4_8x16); 466 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 467 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 468 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 469 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 470 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 471 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 472 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 473 NUM_BANKS(ADDR_SURF_4_BANK); 474 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 475 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 476 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 477 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 478 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 481 NUM_BANKS(ADDR_SURF_4_BANK); 482 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 483 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 484 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 485 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 489 NUM_BANKS(ADDR_SURF_2_BANK); 490 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 491 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 492 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 493 PIPE_CONFIG(ADDR_SURF_P4_8x16); 494 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 496 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 501 NUM_BANKS(ADDR_SURF_16_BANK); 502 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 504 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 509 NUM_BANKS(ADDR_SURF_16_BANK); 510 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 511 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 514 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 517 NUM_BANKS(ADDR_SURF_16_BANK); 518 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 519 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 520 PIPE_CONFIG(ADDR_SURF_P4_8x16); 521 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 523 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 528 NUM_BANKS(ADDR_SURF_16_BANK); 529 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 530 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 531 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 536 NUM_BANKS(ADDR_SURF_16_BANK); 537 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 538 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 539 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 540 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 544 NUM_BANKS(ADDR_SURF_16_BANK); 545 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 546 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 547 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 551 NUM_BANKS(ADDR_SURF_16_BANK) | 552 TILE_SPLIT(split_equal_to_row_size); 553 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 554 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 555 PIPE_CONFIG(ADDR_SURF_P4_8x16); 556 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 557 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 558 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 559 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 562 NUM_BANKS(ADDR_SURF_16_BANK) | 563 TILE_SPLIT(split_equal_to_row_size); 564 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 565 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 566 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 567 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 568 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 569 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 570 NUM_BANKS(ADDR_SURF_16_BANK) | 571 TILE_SPLIT(split_equal_to_row_size); 572 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 573 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 574 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 575 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 576 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 579 NUM_BANKS(ADDR_SURF_8_BANK); 580 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 581 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 583 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 587 NUM_BANKS(ADDR_SURF_8_BANK); 588 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 589 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 590 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 595 NUM_BANKS(ADDR_SURF_4_BANK); 596 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 597 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 598 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 599 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 600 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 603 NUM_BANKS(ADDR_SURF_4_BANK); 604 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 605 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 606 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 607 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 611 NUM_BANKS(ADDR_SURF_2_BANK); 612 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 613 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 614 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 615 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 616 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 619 NUM_BANKS(ADDR_SURF_2_BANK); 620 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 621 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 622 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 624 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 627 NUM_BANKS(ADDR_SURF_2_BANK); 628 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 632 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 633 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 634 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 635 NUM_BANKS(ADDR_SURF_2_BANK); 636 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 638 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 640 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 643 NUM_BANKS(ADDR_SURF_2_BANK); 644 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 645 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 646 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 649 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 651 NUM_BANKS(ADDR_SURF_2_BANK); 652 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 653 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 654 } else if (adev->asic_type == CHIP_OLAND) { 655 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 656 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 657 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 659 NUM_BANKS(ADDR_SURF_16_BANK) | 660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 663 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 664 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 665 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 666 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 667 NUM_BANKS(ADDR_SURF_16_BANK) | 668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 669 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 670 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 671 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 673 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 675 NUM_BANKS(ADDR_SURF_16_BANK) | 676 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 677 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 678 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 679 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 680 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 681 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 682 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 683 NUM_BANKS(ADDR_SURF_16_BANK) | 684 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 687 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 688 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 689 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 690 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 691 NUM_BANKS(ADDR_SURF_16_BANK) | 692 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 693 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 694 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 695 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 696 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 697 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 698 TILE_SPLIT(split_equal_to_row_size) | 699 NUM_BANKS(ADDR_SURF_16_BANK) | 700 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 703 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 704 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 705 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 706 TILE_SPLIT(split_equal_to_row_size) | 707 NUM_BANKS(ADDR_SURF_16_BANK) | 708 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 711 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 713 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 714 TILE_SPLIT(split_equal_to_row_size) | 715 NUM_BANKS(ADDR_SURF_16_BANK) | 716 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 717 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 718 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 719 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 720 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 721 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 723 NUM_BANKS(ADDR_SURF_16_BANK) | 724 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 727 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 728 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 729 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 730 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 731 NUM_BANKS(ADDR_SURF_16_BANK) | 732 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 734 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 735 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 736 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 737 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 738 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 739 NUM_BANKS(ADDR_SURF_16_BANK) | 740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 743 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 744 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 745 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 746 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 747 NUM_BANKS(ADDR_SURF_16_BANK) | 748 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 751 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 752 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 753 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 754 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 755 NUM_BANKS(ADDR_SURF_16_BANK) | 756 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 757 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 758 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 759 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 760 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 761 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 762 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 763 NUM_BANKS(ADDR_SURF_16_BANK) | 764 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 765 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 766 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 767 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 768 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 769 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 770 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 771 NUM_BANKS(ADDR_SURF_16_BANK) | 772 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 773 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 774 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 775 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 776 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 777 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 779 NUM_BANKS(ADDR_SURF_16_BANK) | 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 783 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 784 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 785 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 786 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 787 NUM_BANKS(ADDR_SURF_16_BANK) | 788 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 789 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 790 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 791 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 792 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 793 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 794 TILE_SPLIT(split_equal_to_row_size) | 795 NUM_BANKS(ADDR_SURF_16_BANK) | 796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 799 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 800 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 801 PIPE_CONFIG(ADDR_SURF_P4_8x16); 802 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 803 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 804 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 808 NUM_BANKS(ADDR_SURF_16_BANK) | 809 TILE_SPLIT(split_equal_to_row_size); 810 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 811 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 812 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 816 NUM_BANKS(ADDR_SURF_16_BANK) | 817 TILE_SPLIT(split_equal_to_row_size); 818 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 819 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 821 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 822 NUM_BANKS(ADDR_SURF_16_BANK) | 823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 826 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 827 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 828 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 829 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 830 NUM_BANKS(ADDR_SURF_16_BANK) | 831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 834 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 836 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 838 NUM_BANKS(ADDR_SURF_16_BANK) | 839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 842 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 844 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 846 NUM_BANKS(ADDR_SURF_16_BANK) | 847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 850 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 851 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 852 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 853 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 854 NUM_BANKS(ADDR_SURF_8_BANK) | 855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 858 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 859 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 860 } else if (adev->asic_type == CHIP_HAINAN) { 861 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 862 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 863 PIPE_CONFIG(ADDR_SURF_P2) | 864 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 868 NUM_BANKS(ADDR_SURF_16_BANK); 869 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 871 PIPE_CONFIG(ADDR_SURF_P2) | 872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 876 NUM_BANKS(ADDR_SURF_16_BANK); 877 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 879 PIPE_CONFIG(ADDR_SURF_P2) | 880 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 884 NUM_BANKS(ADDR_SURF_16_BANK); 885 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 886 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 887 PIPE_CONFIG(ADDR_SURF_P2) | 888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 891 NUM_BANKS(ADDR_SURF_8_BANK) | 892 TILE_SPLIT(split_equal_to_row_size); 893 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 894 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 895 PIPE_CONFIG(ADDR_SURF_P2); 896 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 897 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 898 PIPE_CONFIG(ADDR_SURF_P2) | 899 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 903 NUM_BANKS(ADDR_SURF_8_BANK); 904 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 906 PIPE_CONFIG(ADDR_SURF_P2) | 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 911 NUM_BANKS(ADDR_SURF_8_BANK); 912 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 913 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 914 PIPE_CONFIG(ADDR_SURF_P2) | 915 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 916 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 919 NUM_BANKS(ADDR_SURF_4_BANK); 920 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 921 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 922 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 923 PIPE_CONFIG(ADDR_SURF_P2); 924 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 926 PIPE_CONFIG(ADDR_SURF_P2) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 931 NUM_BANKS(ADDR_SURF_16_BANK); 932 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 PIPE_CONFIG(ADDR_SURF_P2) | 935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 939 NUM_BANKS(ADDR_SURF_16_BANK); 940 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 941 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 942 PIPE_CONFIG(ADDR_SURF_P2) | 943 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 947 NUM_BANKS(ADDR_SURF_16_BANK); 948 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 949 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 950 PIPE_CONFIG(ADDR_SURF_P2); 951 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 952 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 953 PIPE_CONFIG(ADDR_SURF_P2) | 954 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 958 NUM_BANKS(ADDR_SURF_16_BANK); 959 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 960 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 961 PIPE_CONFIG(ADDR_SURF_P2) | 962 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 966 NUM_BANKS(ADDR_SURF_16_BANK); 967 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 968 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 969 PIPE_CONFIG(ADDR_SURF_P2) | 970 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 971 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 974 NUM_BANKS(ADDR_SURF_16_BANK); 975 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 976 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 977 PIPE_CONFIG(ADDR_SURF_P2) | 978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 981 NUM_BANKS(ADDR_SURF_16_BANK) | 982 TILE_SPLIT(split_equal_to_row_size); 983 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 984 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 985 PIPE_CONFIG(ADDR_SURF_P2); 986 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 987 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 988 PIPE_CONFIG(ADDR_SURF_P2) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 992 NUM_BANKS(ADDR_SURF_16_BANK) | 993 TILE_SPLIT(split_equal_to_row_size); 994 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 995 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 996 PIPE_CONFIG(ADDR_SURF_P2) | 997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1000 NUM_BANKS(ADDR_SURF_16_BANK) | 1001 TILE_SPLIT(split_equal_to_row_size); 1002 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1003 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1004 PIPE_CONFIG(ADDR_SURF_P2) | 1005 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1009 NUM_BANKS(ADDR_SURF_8_BANK); 1010 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1011 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1012 PIPE_CONFIG(ADDR_SURF_P2) | 1013 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1014 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1017 NUM_BANKS(ADDR_SURF_8_BANK); 1018 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1019 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1020 PIPE_CONFIG(ADDR_SURF_P2) | 1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1022 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1023 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1024 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1025 NUM_BANKS(ADDR_SURF_8_BANK); 1026 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1027 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1028 PIPE_CONFIG(ADDR_SURF_P2) | 1029 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1033 NUM_BANKS(ADDR_SURF_8_BANK); 1034 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1035 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1036 PIPE_CONFIG(ADDR_SURF_P2) | 1037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1041 NUM_BANKS(ADDR_SURF_4_BANK); 1042 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1043 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1044 PIPE_CONFIG(ADDR_SURF_P2) | 1045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1049 NUM_BANKS(ADDR_SURF_4_BANK); 1050 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1051 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1052 PIPE_CONFIG(ADDR_SURF_P2) | 1053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1054 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1057 NUM_BANKS(ADDR_SURF_4_BANK); 1058 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P2) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1065 NUM_BANKS(ADDR_SURF_4_BANK); 1066 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P2) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1073 NUM_BANKS(ADDR_SURF_4_BANK); 1074 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1075 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P2) | 1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1081 NUM_BANKS(ADDR_SURF_4_BANK); 1082 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1083 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1084 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1085 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1086 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1092 NUM_BANKS(ADDR_SURF_16_BANK); 1093 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1100 NUM_BANKS(ADDR_SURF_16_BANK); 1101 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1108 NUM_BANKS(ADDR_SURF_16_BANK); 1109 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1110 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1111 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1115 NUM_BANKS(ADDR_SURF_4_BANK) | 1116 TILE_SPLIT(split_equal_to_row_size); 1117 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1118 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1119 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1120 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1121 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1122 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1123 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1124 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1127 NUM_BANKS(ADDR_SURF_2_BANK); 1128 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1129 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1130 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1131 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1132 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1135 NUM_BANKS(ADDR_SURF_2_BANK); 1136 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1137 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1138 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1139 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1140 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1143 NUM_BANKS(ADDR_SURF_2_BANK); 1144 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1145 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1146 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1147 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1148 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1155 NUM_BANKS(ADDR_SURF_16_BANK); 1156 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1163 NUM_BANKS(ADDR_SURF_16_BANK); 1164 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1165 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1171 NUM_BANKS(ADDR_SURF_16_BANK); 1172 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1173 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1174 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1175 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1176 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1177 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1178 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1182 NUM_BANKS(ADDR_SURF_16_BANK); 1183 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1184 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1186 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1190 NUM_BANKS(ADDR_SURF_16_BANK); 1191 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1192 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1195 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1198 NUM_BANKS(ADDR_SURF_16_BANK); 1199 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1200 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1202 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1205 NUM_BANKS(ADDR_SURF_16_BANK) | 1206 TILE_SPLIT(split_equal_to_row_size); 1207 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1208 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1209 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1210 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1211 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1212 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1216 NUM_BANKS(ADDR_SURF_16_BANK) | 1217 TILE_SPLIT(split_equal_to_row_size); 1218 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1219 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1220 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1224 NUM_BANKS(ADDR_SURF_16_BANK) | 1225 TILE_SPLIT(split_equal_to_row_size); 1226 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1233 NUM_BANKS(ADDR_SURF_4_BANK); 1234 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1235 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1236 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1241 NUM_BANKS(ADDR_SURF_4_BANK); 1242 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1243 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1244 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1249 NUM_BANKS(ADDR_SURF_2_BANK); 1250 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1251 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1252 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1254 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1257 NUM_BANKS(ADDR_SURF_2_BANK); 1258 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1259 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1260 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1261 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1262 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1265 NUM_BANKS(ADDR_SURF_2_BANK); 1266 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1273 NUM_BANKS(ADDR_SURF_2_BANK); 1274 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1275 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1278 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1281 NUM_BANKS(ADDR_SURF_2_BANK); 1282 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1283 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1286 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1289 NUM_BANKS(ADDR_SURF_2_BANK); 1290 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1291 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1293 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1294 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1297 NUM_BANKS(ADDR_SURF_2_BANK); 1298 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1299 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1300 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1301 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1302 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1303 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1304 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1305 NUM_BANKS(ADDR_SURF_2_BANK); 1306 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1307 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1308 } else { 1309 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1310 } 1311 } 1312 1313 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1314 u32 sh_num, u32 instance, int xcc_id) 1315 { 1316 u32 data; 1317 1318 if (instance == 0xffffffff) 1319 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1320 else 1321 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1322 1323 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1324 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1325 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1326 else if (se_num == 0xffffffff) 1327 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1328 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1329 else if (sh_num == 0xffffffff) 1330 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1331 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1332 else 1333 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1334 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1335 WREG32(mmGRBM_GFX_INDEX, data); 1336 } 1337 1338 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1339 { 1340 u32 data, mask; 1341 1342 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1343 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1344 1345 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1346 1347 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1348 adev->gfx.config.max_sh_per_se); 1349 1350 return ~data & mask; 1351 } 1352 1353 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1354 { 1355 switch (adev->asic_type) { 1356 case CHIP_TAHITI: 1357 case CHIP_PITCAIRN: 1358 *rconf |= 1359 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1360 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1361 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1362 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1363 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1364 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1365 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1366 break; 1367 case CHIP_VERDE: 1368 *rconf |= 1369 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1370 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1371 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1372 break; 1373 case CHIP_OLAND: 1374 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1375 break; 1376 case CHIP_HAINAN: 1377 *rconf |= 0x0; 1378 break; 1379 default: 1380 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1381 break; 1382 } 1383 } 1384 1385 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1386 u32 raster_config, unsigned rb_mask, 1387 unsigned num_rb) 1388 { 1389 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1390 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1391 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1392 unsigned rb_per_se = num_rb / num_se; 1393 unsigned se_mask[4]; 1394 unsigned se; 1395 1396 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1397 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1398 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1399 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1400 1401 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1402 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1403 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1404 1405 for (se = 0; se < num_se; se++) { 1406 unsigned raster_config_se = raster_config; 1407 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1408 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1409 int idx = (se / 2) * 2; 1410 1411 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1412 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1413 1414 if (!se_mask[idx]) 1415 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1416 else 1417 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1418 } 1419 1420 pkr0_mask &= rb_mask; 1421 pkr1_mask &= rb_mask; 1422 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1423 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1424 1425 if (!pkr0_mask) 1426 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1427 else 1428 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1429 } 1430 1431 if (rb_per_se >= 2) { 1432 unsigned rb0_mask = 1 << (se * rb_per_se); 1433 unsigned rb1_mask = rb0_mask << 1; 1434 1435 rb0_mask &= rb_mask; 1436 rb1_mask &= rb_mask; 1437 if (!rb0_mask || !rb1_mask) { 1438 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1439 1440 if (!rb0_mask) 1441 raster_config_se |= 1442 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1443 else 1444 raster_config_se |= 1445 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1446 } 1447 1448 if (rb_per_se > 2) { 1449 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1450 rb1_mask = rb0_mask << 1; 1451 rb0_mask &= rb_mask; 1452 rb1_mask &= rb_mask; 1453 if (!rb0_mask || !rb1_mask) { 1454 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1455 1456 if (!rb0_mask) 1457 raster_config_se |= 1458 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1459 else 1460 raster_config_se |= 1461 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1462 } 1463 } 1464 } 1465 1466 /* GRBM_GFX_INDEX has a different offset on SI */ 1467 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1468 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1469 } 1470 1471 /* GRBM_GFX_INDEX has a different offset on SI */ 1472 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1473 } 1474 1475 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1476 { 1477 int i, j; 1478 u32 data; 1479 u32 raster_config = 0; 1480 u32 active_rbs = 0; 1481 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1482 adev->gfx.config.max_sh_per_se; 1483 unsigned num_rb_pipes; 1484 1485 mutex_lock(&adev->grbm_idx_mutex); 1486 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1487 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1488 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1489 data = gfx_v6_0_get_rb_active_bitmap(adev); 1490 active_rbs |= data << 1491 ((i * adev->gfx.config.max_sh_per_se + j) * 1492 rb_bitmap_width_per_sh); 1493 } 1494 } 1495 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1496 1497 adev->gfx.config.backend_enable_mask = active_rbs; 1498 adev->gfx.config.num_rbs = hweight32(active_rbs); 1499 1500 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1501 adev->gfx.config.max_shader_engines, 16); 1502 1503 gfx_v6_0_raster_config(adev, &raster_config); 1504 1505 if (!adev->gfx.config.backend_enable_mask || 1506 adev->gfx.config.num_rbs >= num_rb_pipes) 1507 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1508 else 1509 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1510 adev->gfx.config.backend_enable_mask, 1511 num_rb_pipes); 1512 1513 /* cache the values for userspace */ 1514 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1515 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1516 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1517 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1518 RREG32(mmCC_RB_BACKEND_DISABLE); 1519 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1520 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1521 adev->gfx.config.rb_config[i][j].raster_config = 1522 RREG32(mmPA_SC_RASTER_CONFIG); 1523 } 1524 } 1525 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1526 mutex_unlock(&adev->grbm_idx_mutex); 1527 } 1528 1529 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1530 u32 bitmap) 1531 { 1532 u32 data; 1533 1534 if (!bitmap) 1535 return; 1536 1537 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1538 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1539 1540 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1541 } 1542 1543 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1544 { 1545 u32 data, mask; 1546 1547 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1548 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1549 1550 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1551 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1552 } 1553 1554 1555 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1556 { 1557 int i, j, k; 1558 u32 data, mask; 1559 u32 active_cu = 0; 1560 1561 mutex_lock(&adev->grbm_idx_mutex); 1562 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1563 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1564 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1565 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1566 active_cu = gfx_v6_0_get_cu_enabled(adev); 1567 1568 mask = 1; 1569 for (k = 0; k < 16; k++) { 1570 mask <<= k; 1571 if (active_cu & mask) { 1572 data &= ~mask; 1573 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1574 break; 1575 } 1576 } 1577 } 1578 } 1579 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1580 mutex_unlock(&adev->grbm_idx_mutex); 1581 } 1582 1583 /** 1584 * gfx_v6_0_setup_tcc() - setup which TCCs are used 1585 * 1586 * @adev: amdgpu_device pointer 1587 * 1588 * Verify whether the current GPU has any TCCs disabled, 1589 * which can happen when the GPU is harvested and some 1590 * memory channels are disabled, reducing the memory bus width. 1591 * For example, on the Radeon HD 7870 XT (Tahiti LE). 1592 * 1593 * If some TCCs are disabled, we need to make sure that 1594 * the disabled TCCs are not used, and the remaining TCCs 1595 * are used optimally. 1596 * 1597 * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels. 1598 * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used. 1599 * 1600 * For optimal performance: 1601 * - Rely on the CHAN_STEER from the golden registers table, 1602 * only skip disabled TCCs but keep the mapping order. 1603 * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing, 1604 * which performs better than using the same TCC twice. 1605 */ 1606 static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) 1607 { 1608 u32 i, tcc, tcp_addr_config, num_active_tcc = 0, num_max_active_tcc; 1609 u64 chan_steer, patched_chan_steer = 0; 1610 const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; 1611 const u32 dis_tcc_mask = 1612 amdgpu_gfx_create_bitmask(num_max_tcc) & 1613 (REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE), 1614 CGTS_TCC_DISABLE, TCC_DISABLE) | 1615 REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE), 1616 CGTS_USER_TCC_DISABLE, TCC_DISABLE)); 1617 1618 /* When no TCC is disabled, the golden registers table already has optimal TCC setup */ 1619 if (!dis_tcc_mask) 1620 return; 1621 1622 num_max_active_tcc = num_max_tcc - hweight32(dis_tcc_mask); 1623 1624 /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ 1625 chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); 1626 1627 /* Patch the TCP to TCC mapping to skip disabled TCCs */ 1628 for (i = 0; i < num_max_tcc; ++i) { 1629 tcc = (chan_steer >> (u64)(4 * i)) & 0xf; 1630 1631 if (!((1 << tcc) & dis_tcc_mask)) { 1632 /* Copy enabled TCC indices to the patched register value. */ 1633 patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); 1634 ++num_active_tcc; 1635 } 1636 1637 if (num_active_tcc == num_max_active_tcc) 1638 break; 1639 } 1640 1641 WARN_ON(num_active_tcc != num_max_active_tcc); 1642 1643 /* Patch number of TCCs used by TCPs */ 1644 tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), 1645 TCP_ADDR_CONFIG, NUM_TCC_BANKS, 1646 num_active_tcc - 1); 1647 1648 WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); 1649 WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); 1650 WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); 1651 1652 adev->gfx.config.tcc_disabled_mask = dis_tcc_mask; 1653 } 1654 1655 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1656 { 1657 adev->gfx.config.double_offchip_lds_buf = 0; 1658 } 1659 1660 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1661 { 1662 u32 gb_addr_config = 0; 1663 u32 mc_arb_ramcfg; 1664 u32 sx_debug_1; 1665 u32 hdp_host_path_cntl; 1666 u32 tmp; 1667 1668 switch (adev->asic_type) { 1669 case CHIP_TAHITI: 1670 adev->gfx.config.max_shader_engines = 2; 1671 adev->gfx.config.max_tile_pipes = 12; 1672 adev->gfx.config.max_cu_per_sh = 8; 1673 adev->gfx.config.max_sh_per_se = 2; 1674 adev->gfx.config.max_backends_per_se = 4; 1675 adev->gfx.config.max_texture_channel_caches = 12; 1676 adev->gfx.config.max_gprs = 256; 1677 adev->gfx.config.max_gs_threads = 32; 1678 adev->gfx.config.max_hw_contexts = 8; 1679 1680 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1681 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1682 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1683 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1684 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1685 break; 1686 case CHIP_PITCAIRN: 1687 adev->gfx.config.max_shader_engines = 2; 1688 adev->gfx.config.max_tile_pipes = 8; 1689 adev->gfx.config.max_cu_per_sh = 5; 1690 adev->gfx.config.max_sh_per_se = 2; 1691 adev->gfx.config.max_backends_per_se = 4; 1692 adev->gfx.config.max_texture_channel_caches = 8; 1693 adev->gfx.config.max_gprs = 256; 1694 adev->gfx.config.max_gs_threads = 32; 1695 adev->gfx.config.max_hw_contexts = 8; 1696 1697 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1698 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1699 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1700 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1701 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1702 break; 1703 case CHIP_VERDE: 1704 adev->gfx.config.max_shader_engines = 1; 1705 adev->gfx.config.max_tile_pipes = 4; 1706 adev->gfx.config.max_cu_per_sh = 5; 1707 adev->gfx.config.max_sh_per_se = 2; 1708 adev->gfx.config.max_backends_per_se = 4; 1709 adev->gfx.config.max_texture_channel_caches = 4; 1710 adev->gfx.config.max_gprs = 256; 1711 adev->gfx.config.max_gs_threads = 32; 1712 adev->gfx.config.max_hw_contexts = 8; 1713 1714 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1715 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1716 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1717 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1718 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1719 break; 1720 case CHIP_OLAND: 1721 adev->gfx.config.max_shader_engines = 1; 1722 adev->gfx.config.max_tile_pipes = 4; 1723 adev->gfx.config.max_cu_per_sh = 6; 1724 adev->gfx.config.max_sh_per_se = 1; 1725 adev->gfx.config.max_backends_per_se = 2; 1726 adev->gfx.config.max_texture_channel_caches = 4; 1727 adev->gfx.config.max_gprs = 256; 1728 adev->gfx.config.max_gs_threads = 16; 1729 adev->gfx.config.max_hw_contexts = 8; 1730 1731 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1732 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1733 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1734 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1735 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1736 break; 1737 case CHIP_HAINAN: 1738 adev->gfx.config.max_shader_engines = 1; 1739 adev->gfx.config.max_tile_pipes = 4; 1740 adev->gfx.config.max_cu_per_sh = 5; 1741 adev->gfx.config.max_sh_per_se = 1; 1742 adev->gfx.config.max_backends_per_se = 1; 1743 adev->gfx.config.max_texture_channel_caches = 2; 1744 adev->gfx.config.max_gprs = 256; 1745 adev->gfx.config.max_gs_threads = 16; 1746 adev->gfx.config.max_hw_contexts = 8; 1747 1748 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1749 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1750 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1751 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1752 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1753 break; 1754 default: 1755 dev_warn(adev->dev, "Unsupported asic_type 0x%08x\n", adev->asic_type); 1756 return; 1757 } 1758 1759 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1760 WREG32(mmSRBM_INT_CNTL, 1); 1761 WREG32(mmSRBM_INT_ACK, 1); 1762 1763 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1764 1765 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1766 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1767 1768 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1769 adev->gfx.config.mem_max_burst_length_bytes = 256; 1770 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1771 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1772 if (adev->gfx.config.mem_row_size_in_kb > 4) 1773 adev->gfx.config.mem_row_size_in_kb = 4; 1774 adev->gfx.config.shader_engine_tile_size = 32; 1775 adev->gfx.config.num_gpus = 1; 1776 adev->gfx.config.multi_gpu_tile_size = 64; 1777 1778 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1779 switch (adev->gfx.config.mem_row_size_in_kb) { 1780 case 1: 1781 default: 1782 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1783 break; 1784 case 2: 1785 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1786 break; 1787 case 4: 1788 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1789 break; 1790 } 1791 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1792 if (adev->gfx.config.max_shader_engines == 2) 1793 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1794 adev->gfx.config.gb_addr_config = gb_addr_config; 1795 1796 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1797 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1798 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1799 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1800 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1801 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1802 1803 #if 0 1804 if (adev->has_uvd) { 1805 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1806 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1807 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1808 } 1809 #endif 1810 gfx_v6_0_tiling_mode_table_init(adev); 1811 1812 gfx_v6_0_setup_rb(adev); 1813 gfx_v6_0_setup_tcc(adev); 1814 1815 gfx_v6_0_setup_spi(adev); 1816 1817 gfx_v6_0_get_cu_info(adev); 1818 gfx_v6_0_config_init(adev); 1819 1820 WREG32(mmCP_QUEUE_THRESHOLDS, 1821 ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1822 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1823 1824 /* set HW defaults for 3D engine */ 1825 WREG32(mmCP_MEQ_THRESHOLDS, 1826 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1827 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1828 1829 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1830 WREG32(mmSX_DEBUG_1, sx_debug_1); 1831 1832 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1833 1834 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1835 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1836 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1837 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1838 1839 WREG32(mmVGT_NUM_INSTANCES, 1); 1840 WREG32(mmCP_PERFMON_CNTL, 0); 1841 WREG32(mmSQ_CONFIG, 0); 1842 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1843 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1844 1845 WREG32(mmVGT_CACHE_INVALIDATION, 1846 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1847 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1848 1849 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1850 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1851 1852 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1853 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1854 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1855 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1856 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1857 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1858 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1859 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1860 1861 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1862 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1863 1864 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1865 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1866 1867 udelay(50); 1868 } 1869 1870 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1871 { 1872 struct amdgpu_device *adev = ring->adev; 1873 uint32_t tmp = 0; 1874 unsigned i; 1875 int r; 1876 1877 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1878 1879 r = amdgpu_ring_alloc(ring, 3); 1880 if (r) 1881 return r; 1882 1883 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1884 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); 1885 amdgpu_ring_write(ring, 0xDEADBEEF); 1886 amdgpu_ring_commit(ring); 1887 1888 for (i = 0; i < adev->usec_timeout; i++) { 1889 tmp = RREG32(mmSCRATCH_REG0); 1890 if (tmp == 0xDEADBEEF) 1891 break; 1892 udelay(1); 1893 } 1894 1895 if (i >= adev->usec_timeout) 1896 r = -ETIMEDOUT; 1897 return r; 1898 } 1899 1900 static void gfx_v6_0_ring_emit_event_write(struct amdgpu_ring *ring, 1901 uint32_t event_type, 1902 uint32_t event_index) 1903 { 1904 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1905 amdgpu_ring_write(ring, EVENT_TYPE(event_type) | 1906 EVENT_INDEX(event_index)); 1907 } 1908 1909 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1910 u64 seq, unsigned flags) 1911 { 1912 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1913 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1914 /* flush read cache over gart */ 1915 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1916 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1917 amdgpu_ring_write(ring, 0); 1918 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1919 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1920 PACKET3_TC_ACTION_ENA | 1921 PACKET3_SH_KCACHE_ACTION_ENA | 1922 PACKET3_SH_ICACHE_ACTION_ENA); 1923 amdgpu_ring_write(ring, 0xFFFFFFFF); 1924 amdgpu_ring_write(ring, 0); 1925 amdgpu_ring_write(ring, 10); /* poll interval */ 1926 /* EVENT_WRITE_EOP - flush caches, send int */ 1927 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1928 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1929 amdgpu_ring_write(ring, addr & 0xfffffffc); 1930 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1931 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1932 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1933 amdgpu_ring_write(ring, lower_32_bits(seq)); 1934 amdgpu_ring_write(ring, upper_32_bits(seq)); 1935 } 1936 1937 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1938 struct amdgpu_job *job, 1939 struct amdgpu_ib *ib, 1940 uint32_t flags) 1941 { 1942 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1943 u32 header, control = 0; 1944 1945 if (ib->flags & AMDGPU_IB_FLAG_CE) 1946 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1947 else 1948 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1949 1950 control |= ib->length_dw | (vmid << 24); 1951 1952 amdgpu_ring_write(ring, header); 1953 amdgpu_ring_write(ring, 1954 #ifdef __BIG_ENDIAN 1955 (2 << 0) | 1956 #endif 1957 (ib->gpu_addr & 0xFFFFFFFC)); 1958 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1959 amdgpu_ring_write(ring, control); 1960 } 1961 1962 /** 1963 * gfx_v6_0_ring_test_ib - basic ring IB test 1964 * 1965 * @ring: amdgpu_ring structure holding ring information 1966 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1967 * 1968 * Allocate an IB and execute it on the gfx ring (SI). 1969 * Provides a basic gfx ring test to verify that IBs are working. 1970 * Returns 0 on success, error on failure. 1971 */ 1972 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1973 { 1974 struct amdgpu_device *adev = ring->adev; 1975 struct dma_fence *f = NULL; 1976 struct amdgpu_ib ib; 1977 uint32_t tmp = 0; 1978 long r; 1979 1980 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 1981 memset(&ib, 0, sizeof(ib)); 1982 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1983 if (r) 1984 return r; 1985 1986 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1987 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; 1988 ib.ptr[2] = 0xDEADBEEF; 1989 ib.length_dw = 3; 1990 1991 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1992 if (r) 1993 goto error; 1994 1995 r = dma_fence_wait_timeout(f, false, timeout); 1996 if (r == 0) { 1997 r = -ETIMEDOUT; 1998 goto error; 1999 } else if (r < 0) { 2000 goto error; 2001 } 2002 tmp = RREG32(mmSCRATCH_REG0); 2003 if (tmp == 0xDEADBEEF) 2004 r = 0; 2005 else 2006 r = -EINVAL; 2007 2008 error: 2009 amdgpu_ib_free(&ib, NULL); 2010 dma_fence_put(f); 2011 return r; 2012 } 2013 2014 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2015 { 2016 if (enable) { 2017 WREG32(mmCP_ME_CNTL, 0); 2018 } else { 2019 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2020 CP_ME_CNTL__PFP_HALT_MASK | 2021 CP_ME_CNTL__CE_HALT_MASK)); 2022 WREG32(mmSCRATCH_UMSK, 0); 2023 } 2024 udelay(50); 2025 } 2026 2027 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2028 { 2029 unsigned i; 2030 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2031 const struct gfx_firmware_header_v1_0 *ce_hdr; 2032 const struct gfx_firmware_header_v1_0 *me_hdr; 2033 const __le32 *fw_data; 2034 u32 fw_size; 2035 2036 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2037 return -EINVAL; 2038 2039 gfx_v6_0_cp_gfx_enable(adev, false); 2040 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2041 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2042 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2043 2044 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2045 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2046 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2047 2048 /* PFP */ 2049 fw_data = (const __le32 *) 2050 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2051 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2052 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2053 for (i = 0; i < fw_size; i++) 2054 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2055 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2056 2057 /* CE */ 2058 fw_data = (const __le32 *) 2059 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2060 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2061 WREG32(mmCP_CE_UCODE_ADDR, 0); 2062 for (i = 0; i < fw_size; i++) 2063 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2064 WREG32(mmCP_CE_UCODE_ADDR, 0); 2065 2066 /* ME */ 2067 fw_data = (const __be32 *) 2068 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2069 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2070 WREG32(mmCP_ME_RAM_WADDR, 0); 2071 for (i = 0; i < fw_size; i++) 2072 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2073 WREG32(mmCP_ME_RAM_WADDR, 0); 2074 2075 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2076 WREG32(mmCP_CE_UCODE_ADDR, 0); 2077 WREG32(mmCP_ME_RAM_WADDR, 0); 2078 WREG32(mmCP_ME_RAM_RADDR, 0); 2079 return 0; 2080 } 2081 2082 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2083 { 2084 const struct cs_section_def *sect = NULL; 2085 const struct cs_extent_def *ext = NULL; 2086 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2087 int r, i; 2088 2089 r = amdgpu_ring_alloc(ring, 7 + 4); 2090 if (r) { 2091 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2092 return r; 2093 } 2094 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2095 amdgpu_ring_write(ring, 0x1); 2096 amdgpu_ring_write(ring, 0x0); 2097 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2098 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2099 amdgpu_ring_write(ring, 0); 2100 amdgpu_ring_write(ring, 0); 2101 2102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2103 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2104 amdgpu_ring_write(ring, 0xc000); 2105 amdgpu_ring_write(ring, 0xe000); 2106 amdgpu_ring_commit(ring); 2107 2108 gfx_v6_0_cp_gfx_enable(adev, true); 2109 2110 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2111 if (r) { 2112 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 2113 return r; 2114 } 2115 2116 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2117 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2118 2119 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2120 for (ext = sect->section; ext->extent != NULL; ++ext) { 2121 if (sect->id == SECT_CONTEXT) { 2122 amdgpu_ring_write(ring, 2123 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2124 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2125 for (i = 0; i < ext->reg_count; i++) 2126 amdgpu_ring_write(ring, ext->extent[i]); 2127 } 2128 } 2129 } 2130 2131 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2132 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2133 2134 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2135 amdgpu_ring_write(ring, 0); 2136 2137 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2138 amdgpu_ring_write(ring, 0x00000316); 2139 amdgpu_ring_write(ring, 0x0000000e); 2140 amdgpu_ring_write(ring, 0x00000010); 2141 2142 amdgpu_ring_commit(ring); 2143 2144 return 0; 2145 } 2146 2147 /** 2148 * gfx_v6_0_cp_gfx_resume() - Initialize CP rings 2149 * 2150 * @adev: amdgpu_device pointer 2151 * 2152 * In GFX6 GPUs, compute takes the same CP path as graphics. 2153 * CP ME command parser executes packets for each ring buffer: 2154 * RB0 supports graphics, RB1 and RB2 are compute only. 2155 * Initialize all three rings before calling gfx_v6_0_cp_gfx_start() 2156 * to make sure they are all in a sane state before execution starts. 2157 */ 2158 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2159 { 2160 struct amdgpu_ring *ring; 2161 u32 tmp; 2162 u32 rb_bufsz; 2163 int r; 2164 int i; 2165 u64 rptr_addr; 2166 2167 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2168 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2169 2170 /* Set the write pointer delay */ 2171 WREG32(mmCP_RB_WPTR_DELAY, 0); 2172 2173 WREG32(mmCP_DEBUG, 0); 2174 WREG32(mmSCRATCH_ADDR, 0); 2175 2176 /* ring 0 - compute and gfx */ 2177 ring = &adev->gfx.gfx_ring[0]; 2178 *ring->wptr_cpu_addr = 0; 2179 *ring->rptr_cpu_addr = 0; 2180 amdgpu_ring_clear_ring(ring); 2181 2182 /* Set ring buffer size */ 2183 rb_bufsz = order_base_2(ring->ring_size / 8); 2184 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2185 2186 #ifdef __BIG_ENDIAN 2187 tmp |= BUF_SWAP_32BIT; 2188 #endif 2189 WREG32(mmCP_RB0_CNTL, tmp); 2190 2191 /* Initialize the ring buffer's read and write pointers */ 2192 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2193 ring->wptr = 0; 2194 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2195 WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); 2196 2197 /* set the wb address whether it's enabled or not */ 2198 rptr_addr = ring->rptr_gpu_addr; 2199 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2200 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2201 2202 WREG32(mmSCRATCH_UMSK, 0); 2203 2204 mdelay(1); 2205 WREG32(mmCP_RB0_CNTL, tmp); 2206 2207 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2208 2209 /* ring 1 - compute only */ 2210 if (adev->gfx.num_compute_rings >= 1) { 2211 ring = &adev->gfx.compute_ring[0]; 2212 *ring->wptr_cpu_addr = 0; 2213 *ring->rptr_cpu_addr = 0; 2214 amdgpu_ring_clear_ring(ring); 2215 2216 rb_bufsz = order_base_2(ring->ring_size / 8); 2217 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; 2218 #ifdef __BIG_ENDIAN 2219 tmp |= BUF_SWAP_32BIT; 2220 #endif 2221 WREG32(mmCP_RB1_CNTL, tmp); 2222 2223 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2224 ring->wptr = 0; 2225 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2226 WREG32(mmCP_RB1_RPTR, lower_32_bits(ring->wptr)); 2227 2228 rptr_addr = ring->rptr_gpu_addr; 2229 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2230 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2231 2232 mdelay(1); 2233 WREG32(mmCP_RB1_CNTL, tmp); 2234 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2235 } 2236 2237 /* ring 2 - compute only */ 2238 if (adev->gfx.num_compute_rings >= 2) { 2239 ring = &adev->gfx.compute_ring[1]; 2240 *ring->wptr_cpu_addr = 0; 2241 *ring->rptr_cpu_addr = 0; 2242 amdgpu_ring_clear_ring(ring); 2243 2244 rb_bufsz = order_base_2(ring->ring_size / 8); 2245 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; 2246 #ifdef __BIG_ENDIAN 2247 tmp |= BUF_SWAP_32BIT; 2248 #endif 2249 WREG32(mmCP_RB2_CNTL, tmp); 2250 2251 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2252 ring->wptr = 0; 2253 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2254 WREG32(mmCP_RB2_RPTR, lower_32_bits(ring->wptr)); 2255 2256 rptr_addr = ring->rptr_gpu_addr; 2257 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2258 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2259 2260 mdelay(1); 2261 WREG32(mmCP_RB2_CNTL, tmp); 2262 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2263 } 2264 2265 /* start the rings */ 2266 gfx_v6_0_cp_gfx_start(adev); 2267 2268 /* Wait for the initial packets to finish, run gfx ring test */ 2269 r = amdgpu_ring_test_helper(&adev->gfx.gfx_ring[0]); 2270 if (r) 2271 return r; 2272 2273 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2274 ring = &adev->gfx.compute_ring[i]; 2275 2276 r = amdgpu_ring_alloc(ring, 2); 2277 if (r) 2278 return r; 2279 2280 amdgpu_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 2281 amdgpu_ring_write(ring, 0); 2282 amdgpu_ring_commit(ring); 2283 2284 r = amdgpu_ring_test_helper(ring); 2285 if (r) 2286 return r; 2287 } 2288 2289 return 0; 2290 } 2291 2292 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2293 { 2294 return *ring->rptr_cpu_addr; 2295 } 2296 2297 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2298 { 2299 struct amdgpu_device *adev = ring->adev; 2300 2301 if (ring == &adev->gfx.gfx_ring[0]) 2302 return RREG32(mmCP_RB0_WPTR); 2303 else if (ring == &adev->gfx.compute_ring[0]) 2304 return RREG32(mmCP_RB1_WPTR); 2305 else if (ring == &adev->gfx.compute_ring[1]) 2306 return RREG32(mmCP_RB2_WPTR); 2307 else 2308 return 0; 2309 } 2310 2311 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2312 { 2313 struct amdgpu_device *adev = ring->adev; 2314 2315 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2316 (void)RREG32(mmCP_RB0_WPTR); 2317 } 2318 2319 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2320 { 2321 struct amdgpu_device *adev = ring->adev; 2322 2323 if (ring == &adev->gfx.compute_ring[0]) { 2324 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2325 (void)RREG32(mmCP_RB1_WPTR); 2326 } else if (ring == &adev->gfx.compute_ring[1]) { 2327 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2328 (void)RREG32(mmCP_RB2_WPTR); 2329 } 2330 2331 } 2332 2333 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2334 { 2335 gfx_v6_0_cp_gfx_enable(adev, enable); 2336 } 2337 2338 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2339 { 2340 return gfx_v6_0_cp_gfx_load_microcode(adev); 2341 } 2342 2343 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2344 bool enable) 2345 { 2346 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2347 u32 mask; 2348 int i; 2349 2350 if (enable) 2351 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2352 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2353 else 2354 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2355 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2356 WREG32(mmCP_INT_CNTL_RING0, tmp); 2357 2358 if (!enable) { 2359 /* read a gfx register */ 2360 tmp = RREG32(mmDB_DEPTH_INFO); 2361 2362 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2363 for (i = 0; i < adev->usec_timeout; i++) { 2364 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2365 break; 2366 udelay(1); 2367 } 2368 } 2369 } 2370 2371 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2372 { 2373 int r; 2374 2375 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2376 2377 r = gfx_v6_0_cp_load_microcode(adev); 2378 if (r) 2379 return r; 2380 2381 r = gfx_v6_0_cp_gfx_resume(adev); 2382 if (r) 2383 return r; 2384 2385 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2386 2387 return 0; 2388 } 2389 2390 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2391 { 2392 int usepfp = 1; 2393 uint32_t seq = ring->fence_drv.sync_seq; 2394 uint64_t addr = ring->fence_drv.gpu_addr; 2395 2396 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2397 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2398 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2399 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2400 amdgpu_ring_write(ring, addr & 0xfffffffc); 2401 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2402 amdgpu_ring_write(ring, seq); 2403 amdgpu_ring_write(ring, 0xffffffff); 2404 amdgpu_ring_write(ring, 4); /* poll interval */ 2405 } 2406 2407 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2408 unsigned vmid, uint64_t pd_addr) 2409 { 2410 int usepfp = 1; 2411 2412 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2413 2414 /* wait for the invalidate to complete */ 2415 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2416 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2417 WAIT_REG_MEM_ENGINE(0))); /* me */ 2418 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2419 amdgpu_ring_write(ring, 0); 2420 amdgpu_ring_write(ring, 0); /* ref */ 2421 amdgpu_ring_write(ring, 0); /* mask */ 2422 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2423 2424 if (usepfp) { 2425 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2426 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2427 amdgpu_ring_write(ring, 0x0); 2428 } 2429 } 2430 2431 static unsigned int gfx_v6_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 2432 uint64_t gpu_addr) 2433 { 2434 unsigned int ret; 2435 2436 /* 2437 * Discard following DWs after this packet when gpu_addr==0 2438 * The packet is only 4 DW on GFX6 (as opposed to GFX7+). 2439 */ 2440 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 2)); 2441 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 2442 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 2443 ret = ring->wptr & ring->buf_mask; 2444 /* patch dummy value later */ 2445 amdgpu_ring_write(ring, 0); 2446 return ret; 2447 } 2448 2449 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2450 uint32_t reg, uint32_t val) 2451 { 2452 int usepfp = 1; 2453 2454 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2455 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2456 WRITE_DATA_DST_SEL(0))); 2457 amdgpu_ring_write(ring, reg); 2458 amdgpu_ring_write(ring, 0); 2459 amdgpu_ring_write(ring, val); 2460 } 2461 2462 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2463 { 2464 const u32 *src_ptr; 2465 u32 *dst_ptr; 2466 u32 dws; 2467 u64 reg_list_mc_addr; 2468 const struct cs_section_def *cs_data; 2469 int r; 2470 2471 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2472 adev->gfx.rlc.reg_list_size = 2473 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2474 2475 adev->gfx.rlc.cs_data = si_cs_data; 2476 src_ptr = adev->gfx.rlc.reg_list; 2477 dws = adev->gfx.rlc.reg_list_size; 2478 cs_data = adev->gfx.rlc.cs_data; 2479 2480 if (src_ptr) { 2481 /* init save restore block */ 2482 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2483 if (r) 2484 return r; 2485 } 2486 2487 if (cs_data) { 2488 /* clear state block */ 2489 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2490 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2491 2492 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2493 AMDGPU_GEM_DOMAIN_VRAM | 2494 AMDGPU_GEM_DOMAIN_GTT, 2495 &adev->gfx.rlc.clear_state_obj, 2496 &adev->gfx.rlc.clear_state_gpu_addr, 2497 (void **)&adev->gfx.rlc.cs_ptr); 2498 if (r) { 2499 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2500 amdgpu_gfx_rlc_fini(adev); 2501 return r; 2502 } 2503 2504 /* set up the cs buffer */ 2505 dst_ptr = adev->gfx.rlc.cs_ptr; 2506 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2507 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2508 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2509 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2510 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2511 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2512 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2513 } 2514 2515 return 0; 2516 } 2517 2518 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2519 { 2520 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2521 2522 if (!enable) { 2523 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2524 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2525 } 2526 } 2527 2528 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2529 { 2530 int i; 2531 2532 for (i = 0; i < adev->usec_timeout; i++) { 2533 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2534 break; 2535 udelay(1); 2536 } 2537 2538 for (i = 0; i < adev->usec_timeout; i++) { 2539 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2540 break; 2541 udelay(1); 2542 } 2543 } 2544 2545 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2546 { 2547 u32 tmp; 2548 2549 tmp = RREG32(mmRLC_CNTL); 2550 if (tmp != rlc) 2551 WREG32(mmRLC_CNTL, rlc); 2552 } 2553 2554 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2555 { 2556 u32 data, orig; 2557 2558 orig = data = RREG32(mmRLC_CNTL); 2559 2560 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2561 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2562 WREG32(mmRLC_CNTL, data); 2563 2564 gfx_v6_0_wait_for_rlc_serdes(adev); 2565 } 2566 2567 return orig; 2568 } 2569 2570 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2571 { 2572 WREG32(mmRLC_CNTL, 0); 2573 2574 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2575 gfx_v6_0_wait_for_rlc_serdes(adev); 2576 } 2577 2578 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2579 { 2580 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2581 2582 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2583 2584 udelay(50); 2585 } 2586 2587 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2588 { 2589 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2590 udelay(50); 2591 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2592 udelay(50); 2593 } 2594 2595 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2596 { 2597 u32 tmp; 2598 2599 /* Enable LBPW only for DDR3 */ 2600 tmp = RREG32(mmMC_SEQ_MISC0); 2601 if ((tmp & 0xF0000000) == 0xB0000000) 2602 return true; 2603 return false; 2604 } 2605 2606 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2607 { 2608 } 2609 2610 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2611 { 2612 u32 i; 2613 const struct rlc_firmware_header_v1_0 *hdr; 2614 const __le32 *fw_data; 2615 u32 fw_size; 2616 2617 2618 if (!adev->gfx.rlc_fw) 2619 return -EINVAL; 2620 2621 adev->gfx.rlc.funcs->stop(adev); 2622 adev->gfx.rlc.funcs->reset(adev); 2623 gfx_v6_0_init_pg(adev); 2624 gfx_v6_0_init_cg(adev); 2625 2626 WREG32(mmRLC_RL_BASE, 0); 2627 WREG32(mmRLC_RL_SIZE, 0); 2628 WREG32(mmRLC_LB_CNTL, 0); 2629 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2630 WREG32(mmRLC_LB_CNTR_INIT, 0); 2631 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2632 2633 WREG32(mmRLC_MC_CNTL, 0); 2634 WREG32(mmRLC_UCODE_CNTL, 0); 2635 2636 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2637 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2638 fw_data = (const __le32 *) 2639 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2640 2641 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2642 2643 for (i = 0; i < fw_size; i++) { 2644 WREG32(mmRLC_UCODE_ADDR, i); 2645 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2646 } 2647 WREG32(mmRLC_UCODE_ADDR, 0); 2648 2649 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2650 adev->gfx.rlc.funcs->start(adev); 2651 2652 return 0; 2653 } 2654 2655 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2656 { 2657 u32 data, orig, tmp; 2658 2659 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2660 2661 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2662 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2663 2664 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2665 2666 tmp = gfx_v6_0_halt_rlc(adev); 2667 2668 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2669 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2670 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2671 2672 gfx_v6_0_wait_for_rlc_serdes(adev); 2673 gfx_v6_0_update_rlc(adev, tmp); 2674 2675 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2676 2677 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2678 } else { 2679 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2680 2681 RREG32(mmCB_CGTT_SCLK_CTRL); 2682 RREG32(mmCB_CGTT_SCLK_CTRL); 2683 RREG32(mmCB_CGTT_SCLK_CTRL); 2684 RREG32(mmCB_CGTT_SCLK_CTRL); 2685 2686 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2687 } 2688 2689 if (orig != data) 2690 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2691 2692 } 2693 2694 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2695 { 2696 2697 u32 data, orig, tmp = 0; 2698 2699 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2700 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2701 data = 0x96940200; 2702 if (orig != data) 2703 WREG32(mmCGTS_SM_CTRL_REG, data); 2704 2705 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2706 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2707 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2708 if (orig != data) 2709 WREG32(mmCP_MEM_SLP_CNTL, data); 2710 } 2711 2712 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2713 data &= 0xffffffc0; 2714 if (orig != data) 2715 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2716 2717 tmp = gfx_v6_0_halt_rlc(adev); 2718 2719 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2720 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2721 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2722 2723 gfx_v6_0_update_rlc(adev, tmp); 2724 } else { 2725 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2726 data |= 0x00000003; 2727 if (orig != data) 2728 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2729 2730 data = RREG32(mmCP_MEM_SLP_CNTL); 2731 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2732 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2733 WREG32(mmCP_MEM_SLP_CNTL, data); 2734 } 2735 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2736 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2737 if (orig != data) 2738 WREG32(mmCGTS_SM_CTRL_REG, data); 2739 2740 tmp = gfx_v6_0_halt_rlc(adev); 2741 2742 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2743 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2744 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2745 2746 gfx_v6_0_update_rlc(adev, tmp); 2747 } 2748 } 2749 /* 2750 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2751 bool enable) 2752 { 2753 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2754 if (enable) { 2755 gfx_v6_0_enable_mgcg(adev, true); 2756 gfx_v6_0_enable_cgcg(adev, true); 2757 } else { 2758 gfx_v6_0_enable_cgcg(adev, false); 2759 gfx_v6_0_enable_mgcg(adev, false); 2760 } 2761 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2762 } 2763 */ 2764 2765 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2766 bool enable) 2767 { 2768 } 2769 2770 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2771 bool enable) 2772 { 2773 } 2774 2775 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2776 { 2777 u32 data, orig; 2778 2779 orig = data = RREG32(mmRLC_PG_CNTL); 2780 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2781 data &= ~0x8000; 2782 else 2783 data |= 0x8000; 2784 if (orig != data) 2785 WREG32(mmRLC_PG_CNTL, data); 2786 } 2787 2788 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2789 { 2790 } 2791 /* 2792 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2793 { 2794 const __le32 *fw_data; 2795 volatile u32 *dst_ptr; 2796 int me, i, max_me = 4; 2797 u32 bo_offset = 0; 2798 u32 table_offset, table_size; 2799 2800 if (adev->asic_type == CHIP_KAVERI) 2801 max_me = 5; 2802 2803 if (adev->gfx.rlc.cp_table_ptr == NULL) 2804 return; 2805 2806 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2807 for (me = 0; me < max_me; me++) { 2808 if (me == 0) { 2809 const struct gfx_firmware_header_v1_0 *hdr = 2810 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2811 fw_data = (const __le32 *) 2812 (adev->gfx.ce_fw->data + 2813 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2814 table_offset = le32_to_cpu(hdr->jt_offset); 2815 table_size = le32_to_cpu(hdr->jt_size); 2816 } else if (me == 1) { 2817 const struct gfx_firmware_header_v1_0 *hdr = 2818 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2819 fw_data = (const __le32 *) 2820 (adev->gfx.pfp_fw->data + 2821 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2822 table_offset = le32_to_cpu(hdr->jt_offset); 2823 table_size = le32_to_cpu(hdr->jt_size); 2824 } else if (me == 2) { 2825 const struct gfx_firmware_header_v1_0 *hdr = 2826 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2827 fw_data = (const __le32 *) 2828 (adev->gfx.me_fw->data + 2829 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2830 table_offset = le32_to_cpu(hdr->jt_offset); 2831 table_size = le32_to_cpu(hdr->jt_size); 2832 } else if (me == 3) { 2833 const struct gfx_firmware_header_v1_0 *hdr = 2834 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2835 fw_data = (const __le32 *) 2836 (adev->gfx.mec_fw->data + 2837 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2838 table_offset = le32_to_cpu(hdr->jt_offset); 2839 table_size = le32_to_cpu(hdr->jt_size); 2840 } else { 2841 const struct gfx_firmware_header_v1_0 *hdr = 2842 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2843 fw_data = (const __le32 *) 2844 (adev->gfx.mec2_fw->data + 2845 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2846 table_offset = le32_to_cpu(hdr->jt_offset); 2847 table_size = le32_to_cpu(hdr->jt_size); 2848 } 2849 2850 for (i = 0; i < table_size; i ++) { 2851 dst_ptr[bo_offset + i] = 2852 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2853 } 2854 2855 bo_offset += table_size; 2856 } 2857 } 2858 */ 2859 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2860 bool enable) 2861 { 2862 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2863 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2864 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2865 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2866 } else { 2867 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2868 (void)RREG32(mmDB_RENDER_CONTROL); 2869 } 2870 } 2871 2872 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2873 { 2874 u32 tmp; 2875 2876 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2877 2878 tmp = RREG32(mmRLC_MAX_PG_CU); 2879 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2880 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2881 WREG32(mmRLC_MAX_PG_CU, tmp); 2882 } 2883 2884 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2885 bool enable) 2886 { 2887 u32 data, orig; 2888 2889 orig = data = RREG32(mmRLC_PG_CNTL); 2890 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2891 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2892 else 2893 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2894 if (orig != data) 2895 WREG32(mmRLC_PG_CNTL, data); 2896 } 2897 2898 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2899 bool enable) 2900 { 2901 u32 data, orig; 2902 2903 orig = data = RREG32(mmRLC_PG_CNTL); 2904 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2905 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2906 else 2907 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2908 if (orig != data) 2909 WREG32(mmRLC_PG_CNTL, data); 2910 } 2911 2912 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2913 { 2914 u32 tmp; 2915 2916 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2917 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2918 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2919 2920 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2921 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2922 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2923 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2924 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2925 } 2926 2927 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2928 { 2929 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2930 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2931 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2932 } 2933 2934 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2935 { 2936 u32 count = 0; 2937 const struct cs_section_def *sect = NULL; 2938 const struct cs_extent_def *ext = NULL; 2939 2940 if (adev->gfx.rlc.cs_data == NULL) 2941 return 0; 2942 2943 /* begin clear state */ 2944 count += 2; 2945 /* context control state */ 2946 count += 3; 2947 2948 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2949 for (ext = sect->section; ext->extent != NULL; ++ext) { 2950 if (sect->id == SECT_CONTEXT) 2951 count += 2 + ext->reg_count; 2952 else 2953 return 0; 2954 } 2955 } 2956 /* pa_sc_raster_config */ 2957 count += 3; 2958 /* end clear state */ 2959 count += 2; 2960 /* clear state */ 2961 count += 2; 2962 2963 return count; 2964 } 2965 2966 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 2967 { 2968 u32 count = 0; 2969 2970 if (adev->gfx.rlc.cs_data == NULL) 2971 return; 2972 if (buffer == NULL) 2973 return; 2974 2975 count = amdgpu_gfx_csb_preamble_start(buffer); 2976 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 2977 2978 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2979 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2980 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2981 2982 amdgpu_gfx_csb_preamble_end(buffer, count); 2983 } 2984 2985 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2986 { 2987 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2988 AMD_PG_SUPPORT_GFX_SMG | 2989 AMD_PG_SUPPORT_GFX_DMG | 2990 AMD_PG_SUPPORT_CP | 2991 AMD_PG_SUPPORT_GDS | 2992 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2993 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2994 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2995 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2996 gfx_v6_0_init_gfx_cgpg(adev); 2997 gfx_v6_0_enable_cp_pg(adev, true); 2998 gfx_v6_0_enable_gds_pg(adev, true); 2999 } else { 3000 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3001 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 3002 3003 } 3004 gfx_v6_0_init_ao_cu_mask(adev); 3005 gfx_v6_0_update_gfx_pg(adev, true); 3006 } else { 3007 3008 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3009 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 3010 } 3011 } 3012 3013 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 3014 { 3015 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3016 AMD_PG_SUPPORT_GFX_SMG | 3017 AMD_PG_SUPPORT_GFX_DMG | 3018 AMD_PG_SUPPORT_CP | 3019 AMD_PG_SUPPORT_GDS | 3020 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3021 gfx_v6_0_update_gfx_pg(adev, false); 3022 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3023 gfx_v6_0_enable_cp_pg(adev, false); 3024 gfx_v6_0_enable_gds_pg(adev, false); 3025 } 3026 } 3027 } 3028 3029 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3030 { 3031 uint64_t clock; 3032 3033 mutex_lock(&adev->gfx.gpu_clock_mutex); 3034 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3035 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3036 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3037 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3038 return clock; 3039 } 3040 3041 static void gfx_v6_0_ring_emit_sb(struct amdgpu_ring *ring) 3042 { 3043 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3044 amdgpu_ring_write(ring, 0); 3045 } 3046 3047 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3048 { 3049 u32 dw2 = 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3050 3051 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3052 gfx_v6_0_ring_emit_event_write(ring, VS_PARTIAL_FLUSH, 4); 3053 gfx_v6_0_ring_emit_event_write(ring, VGT_FLUSH, 0); 3054 3055 /* set load_global_config (load_global_uconfig doesn't exist on GFX6) */ 3056 dw2 |= 0x1; 3057 /* set load_cs_sh_regs */ 3058 dw2 |= 0x01000000; 3059 /* set load_per_context_state & load_gfx_sh_regs */ 3060 dw2 |= 0x10002; 3061 } 3062 3063 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3064 amdgpu_ring_write(ring, dw2); 3065 amdgpu_ring_write(ring, 0); 3066 } 3067 3068 3069 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 3070 { 3071 WREG32(mmSQ_IND_INDEX, 3072 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3073 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3074 (address << SQ_IND_INDEX__INDEX__SHIFT) | 3075 (SQ_IND_INDEX__FORCE_READ_MASK)); 3076 return RREG32(mmSQ_IND_DATA); 3077 } 3078 3079 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3080 uint32_t wave, uint32_t thread, 3081 uint32_t regno, uint32_t num, uint32_t *out) 3082 { 3083 WREG32(mmSQ_IND_INDEX, 3084 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3085 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3086 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3087 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3088 (SQ_IND_INDEX__FORCE_READ_MASK) | 3089 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3090 while (num--) 3091 *(out++) = RREG32(mmSQ_IND_DATA); 3092 } 3093 3094 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3095 { 3096 /* type 0 wave data */ 3097 dst[(*no_fields)++] = 0; 3098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3100 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3101 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3104 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3105 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3106 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3107 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3108 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3109 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3110 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3111 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3112 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3113 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3114 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3115 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3116 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 3117 } 3118 3119 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 3120 uint32_t wave, uint32_t start, 3121 uint32_t size, uint32_t *dst) 3122 { 3123 wave_read_regs( 3124 adev, simd, wave, 0, 3125 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3126 } 3127 3128 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3129 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 3130 { 3131 drm_info(adev_to_drm(adev), "Not implemented\n"); 3132 } 3133 3134 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3135 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3136 .select_se_sh = &gfx_v6_0_select_se_sh, 3137 .read_wave_data = &gfx_v6_0_read_wave_data, 3138 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3139 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3140 }; 3141 3142 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3143 .init = gfx_v6_0_rlc_init, 3144 .resume = gfx_v6_0_rlc_resume, 3145 .stop = gfx_v6_0_rlc_stop, 3146 .reset = gfx_v6_0_rlc_reset, 3147 .start = gfx_v6_0_rlc_start 3148 }; 3149 3150 static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) 3151 { 3152 struct amdgpu_device *adev = ip_block->adev; 3153 3154 adev->gfx.xcc_mask = 1; 3155 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3156 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3157 GFX6_NUM_COMPUTE_RINGS); 3158 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3159 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3160 gfx_v6_0_set_ring_funcs(adev); 3161 gfx_v6_0_set_irq_funcs(adev); 3162 3163 return 0; 3164 } 3165 3166 static int gfx_v6_0_late_init(struct amdgpu_ip_block *ip_block) 3167 { 3168 return 0; 3169 } 3170 3171 static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 3172 { 3173 struct amdgpu_ring *ring; 3174 struct amdgpu_device *adev = ip_block->adev; 3175 int i, r; 3176 3177 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3178 if (r) 3179 return r; 3180 3181 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3182 if (r) 3183 return r; 3184 3185 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3186 if (r) 3187 return r; 3188 3189 r = gfx_v6_0_init_microcode(adev); 3190 if (r) { 3191 DRM_ERROR("Failed to load gfx firmware!\n"); 3192 return r; 3193 } 3194 3195 r = adev->gfx.rlc.funcs->init(adev); 3196 if (r) { 3197 DRM_ERROR("Failed to init rlc BOs!\n"); 3198 return r; 3199 } 3200 3201 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3202 ring = &adev->gfx.gfx_ring[i]; 3203 ring->ring_obj = NULL; 3204 sprintf(ring->name, "gfx"); 3205 r = amdgpu_ring_init(adev, ring, 2048, 3206 &adev->gfx.eop_irq, 3207 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3208 AMDGPU_RING_PRIO_DEFAULT, NULL); 3209 if (r) 3210 return r; 3211 } 3212 3213 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3214 unsigned irq_type; 3215 3216 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3217 DRM_ERROR("Too many (%d) compute rings!\n", i); 3218 break; 3219 } 3220 ring = &adev->gfx.compute_ring[i]; 3221 ring->ring_obj = NULL; 3222 ring->use_doorbell = false; 3223 ring->doorbell_index = 0; 3224 ring->me = 1; 3225 ring->pipe = i; 3226 ring->queue = i; 3227 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3228 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3229 r = amdgpu_ring_init(adev, ring, 1024, 3230 &adev->gfx.eop_irq, irq_type, 3231 AMDGPU_RING_PRIO_DEFAULT, NULL); 3232 if (r) 3233 return r; 3234 } 3235 3236 adev->gfx.gfx_supported_reset = 3237 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 3238 adev->gfx.compute_supported_reset = 3239 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 3240 3241 if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_ip_block_soft_reset) { 3242 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 3243 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET; 3244 } 3245 3246 return r; 3247 } 3248 3249 static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 3250 { 3251 int i; 3252 struct amdgpu_device *adev = ip_block->adev; 3253 3254 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3255 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3256 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3257 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3258 3259 amdgpu_gfx_rlc_fini(adev); 3260 gfx_v6_0_free_microcode(adev); 3261 3262 return 0; 3263 } 3264 3265 static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 3266 { 3267 int r; 3268 struct amdgpu_device *adev = ip_block->adev; 3269 3270 gfx_v6_0_constants_init(adev); 3271 3272 r = adev->gfx.rlc.funcs->resume(adev); 3273 if (r) 3274 return r; 3275 3276 r = gfx_v6_0_cp_resume(adev); 3277 if (r) 3278 return r; 3279 3280 adev->gfx.ce_ram_size = 0x8000; 3281 3282 return r; 3283 } 3284 3285 static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 3286 { 3287 struct amdgpu_device *adev = ip_block->adev; 3288 3289 gfx_v6_0_cp_enable(adev, false); 3290 adev->gfx.rlc.funcs->stop(adev); 3291 gfx_v6_0_fini_pg(adev); 3292 3293 return 0; 3294 } 3295 3296 static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) 3297 { 3298 return gfx_v6_0_hw_fini(ip_block); 3299 } 3300 3301 static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) 3302 { 3303 return gfx_v6_0_hw_init(ip_block); 3304 } 3305 3306 static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 3307 { 3308 struct amdgpu_device *adev = ip_block->adev; 3309 3310 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3311 return false; 3312 else 3313 return true; 3314 } 3315 3316 static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3317 { 3318 unsigned i; 3319 struct amdgpu_device *adev = ip_block->adev; 3320 3321 for (i = 0; i < adev->usec_timeout; i++) { 3322 if (gfx_v6_0_is_idle(ip_block)) 3323 return 0; 3324 udelay(1); 3325 } 3326 return -ETIMEDOUT; 3327 } 3328 3329 static int gfx_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 3330 { 3331 struct amdgpu_device *adev = ip_block->adev; 3332 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 3333 u32 tmp; 3334 int r; 3335 3336 grbm_soft_reset = 3337 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CP, 1) | 3338 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CB, 1) | 3339 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1) | 3340 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_DB, 1) | 3341 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_GDS, 1) | 3342 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_PA, 1) | 3343 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SC, 1) | 3344 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_BCI, 1) | 3345 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SPI, 1) | 3346 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_SX, 1) | 3347 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_TC, 1) | 3348 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_TA, 1) | 3349 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_VGT, 1) | 3350 REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_IA, 1); 3351 3352 srbm_soft_reset = 3353 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1) | 3354 REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 3355 3356 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 3357 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 3358 ip_block->version->funcs->suspend(ip_block); 3359 3360 if (grbm_soft_reset || srbm_soft_reset) { 3361 tmp = RREG32(mmGMCON_DEBUG); 3362 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1); 3363 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1); 3364 WREG32(mmGMCON_DEBUG, tmp); 3365 3366 udelay(100); 3367 } 3368 3369 if (grbm_soft_reset) { 3370 tmp = RREG32(mmGRBM_SOFT_RESET); 3371 tmp |= grbm_soft_reset; 3372 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3373 WREG32(mmGRBM_SOFT_RESET, tmp); 3374 tmp = RREG32(mmGRBM_SOFT_RESET); 3375 3376 udelay(100); 3377 3378 tmp &= ~grbm_soft_reset; 3379 WREG32(mmGRBM_SOFT_RESET, tmp); 3380 tmp = RREG32(mmGRBM_SOFT_RESET); 3381 3382 udelay(100); 3383 } 3384 3385 if (srbm_soft_reset) { 3386 tmp = RREG32(mmSRBM_SOFT_RESET); 3387 tmp |= srbm_soft_reset; 3388 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3389 WREG32(mmSRBM_SOFT_RESET, tmp); 3390 tmp = RREG32(mmSRBM_SOFT_RESET); 3391 3392 udelay(100); 3393 3394 tmp &= ~srbm_soft_reset; 3395 WREG32(mmSRBM_SOFT_RESET, tmp); 3396 tmp = RREG32(mmSRBM_SOFT_RESET); 3397 3398 udelay(100); 3399 } 3400 3401 if (grbm_soft_reset || srbm_soft_reset) { 3402 tmp = RREG32(mmGMCON_DEBUG); 3403 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); 3404 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); 3405 WREG32(mmGMCON_DEBUG, tmp); 3406 } 3407 3408 /* Wait a little for things to settle down */ 3409 udelay(100); 3410 3411 r = ip_block->version->funcs->resume(ip_block); 3412 r |= ip_block->version->funcs->late_init(ip_block); 3413 if (r) 3414 return r; 3415 3416 ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_GATE); 3417 ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_GATE); 3418 3419 return 0; 3420 } 3421 3422 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3423 enum amdgpu_interrupt_state state) 3424 { 3425 u32 cp_int_cntl; 3426 3427 switch (state) { 3428 case AMDGPU_IRQ_STATE_DISABLE: 3429 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3430 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3431 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3432 break; 3433 case AMDGPU_IRQ_STATE_ENABLE: 3434 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3435 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3436 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3437 break; 3438 default: 3439 break; 3440 } 3441 } 3442 3443 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3444 int ring, 3445 enum amdgpu_interrupt_state state) 3446 { 3447 u32 cp_int_cntl; 3448 switch (state){ 3449 case AMDGPU_IRQ_STATE_DISABLE: 3450 if (ring == 0) { 3451 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3452 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3453 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3454 break; 3455 } else { 3456 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3457 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3458 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3459 break; 3460 3461 } 3462 case AMDGPU_IRQ_STATE_ENABLE: 3463 if (ring == 0) { 3464 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3465 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3466 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3467 break; 3468 } else { 3469 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3470 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3471 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3472 break; 3473 3474 } 3475 3476 default: 3477 break; 3478 3479 } 3480 } 3481 3482 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3483 struct amdgpu_irq_src *src, 3484 unsigned type, 3485 enum amdgpu_interrupt_state state) 3486 { 3487 u32 cp_int_cntl; 3488 3489 switch (state) { 3490 case AMDGPU_IRQ_STATE_DISABLE: 3491 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3492 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3493 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3494 break; 3495 case AMDGPU_IRQ_STATE_ENABLE: 3496 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3497 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3498 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3499 break; 3500 default: 3501 break; 3502 } 3503 3504 return 0; 3505 } 3506 3507 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3508 struct amdgpu_irq_src *src, 3509 unsigned type, 3510 enum amdgpu_interrupt_state state) 3511 { 3512 u32 cp_int_cntl; 3513 3514 switch (state) { 3515 case AMDGPU_IRQ_STATE_DISABLE: 3516 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3517 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3518 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3519 break; 3520 case AMDGPU_IRQ_STATE_ENABLE: 3521 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3522 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3523 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3524 break; 3525 default: 3526 break; 3527 } 3528 3529 return 0; 3530 } 3531 3532 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3533 struct amdgpu_irq_src *src, 3534 unsigned type, 3535 enum amdgpu_interrupt_state state) 3536 { 3537 switch (type) { 3538 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3539 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3540 break; 3541 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3542 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3543 break; 3544 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3545 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3546 break; 3547 default: 3548 break; 3549 } 3550 return 0; 3551 } 3552 3553 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3554 struct amdgpu_irq_src *source, 3555 struct amdgpu_iv_entry *entry) 3556 { 3557 switch (entry->ring_id) { 3558 case 0: 3559 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3560 break; 3561 case 1: 3562 case 2: 3563 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3564 break; 3565 default: 3566 break; 3567 } 3568 return 0; 3569 } 3570 3571 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3572 struct amdgpu_iv_entry *entry) 3573 { 3574 struct amdgpu_ring *ring; 3575 3576 switch (entry->ring_id) { 3577 case 0: 3578 ring = &adev->gfx.gfx_ring[0]; 3579 break; 3580 case 1: 3581 case 2: 3582 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3583 break; 3584 default: 3585 return; 3586 } 3587 drm_sched_fault(&ring->sched); 3588 } 3589 3590 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3591 struct amdgpu_irq_src *source, 3592 struct amdgpu_iv_entry *entry) 3593 { 3594 DRM_ERROR("Illegal register access in command stream\n"); 3595 gfx_v6_0_fault(adev, entry); 3596 return 0; 3597 } 3598 3599 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3600 struct amdgpu_irq_src *source, 3601 struct amdgpu_iv_entry *entry) 3602 { 3603 DRM_ERROR("Illegal instruction in command stream\n"); 3604 gfx_v6_0_fault(adev, entry); 3605 return 0; 3606 } 3607 3608 static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3609 enum amd_clockgating_state state) 3610 { 3611 bool gate = false; 3612 struct amdgpu_device *adev = ip_block->adev; 3613 3614 if (state == AMD_CG_STATE_GATE) 3615 gate = true; 3616 3617 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3618 if (gate) { 3619 gfx_v6_0_enable_mgcg(adev, true); 3620 gfx_v6_0_enable_cgcg(adev, true); 3621 } else { 3622 gfx_v6_0_enable_cgcg(adev, false); 3623 gfx_v6_0_enable_mgcg(adev, false); 3624 } 3625 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3626 3627 return 0; 3628 } 3629 3630 static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3631 enum amd_powergating_state state) 3632 { 3633 bool gate = false; 3634 struct amdgpu_device *adev = ip_block->adev; 3635 3636 if (state == AMD_PG_STATE_GATE) 3637 gate = true; 3638 3639 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3640 AMD_PG_SUPPORT_GFX_SMG | 3641 AMD_PG_SUPPORT_GFX_DMG | 3642 AMD_PG_SUPPORT_CP | 3643 AMD_PG_SUPPORT_GDS | 3644 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3645 gfx_v6_0_update_gfx_pg(adev, gate); 3646 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3647 gfx_v6_0_enable_cp_pg(adev, gate); 3648 gfx_v6_0_enable_gds_pg(adev, gate); 3649 } 3650 } 3651 3652 return 0; 3653 } 3654 3655 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) 3656 { 3657 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 3658 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 3659 PACKET3_TC_ACTION_ENA | 3660 PACKET3_SH_KCACHE_ACTION_ENA | 3661 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 3662 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3663 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3664 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 3665 } 3666 3667 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3668 .name = "gfx_v6_0", 3669 .early_init = gfx_v6_0_early_init, 3670 .late_init = gfx_v6_0_late_init, 3671 .sw_init = gfx_v6_0_sw_init, 3672 .sw_fini = gfx_v6_0_sw_fini, 3673 .hw_init = gfx_v6_0_hw_init, 3674 .hw_fini = gfx_v6_0_hw_fini, 3675 .suspend = gfx_v6_0_suspend, 3676 .resume = gfx_v6_0_resume, 3677 .is_idle = gfx_v6_0_is_idle, 3678 .wait_for_idle = gfx_v6_0_wait_for_idle, 3679 .soft_reset = gfx_v6_0_soft_reset, 3680 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3681 .set_powergating_state = gfx_v6_0_set_powergating_state, 3682 }; 3683 3684 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3685 .type = AMDGPU_RING_TYPE_GFX, 3686 .align_mask = 0xff, 3687 .nop = 0x80000000, 3688 .support_64bit_ptrs = false, 3689 .get_rptr = gfx_v6_0_ring_get_rptr, 3690 .get_wptr = gfx_v6_0_ring_get_wptr, 3691 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3692 .emit_frame_size = 3693 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 3694 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 3695 5 + 5 + /* hdp flush / invalidate */ 3696 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3697 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3698 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 2 + /* gfx_v6_0_ring_emit_vm_flush */ 3699 3 * 2 + /* gfx_v6_0_ring_emit_sb x3 (from amdgpu_vm_flush, amdgpu_ib_schedule) */ 3700 3 + 2 + 2 + /* gfx_v6_ring_emit_cntxcntl including VGT flush */ 3701 5, /* SURFACE_SYNC */ 3702 .emit_ib_size = 4, /* gfx_v6_0_ring_emit_ib */ 3703 .emit_ib = gfx_v6_0_ring_emit_ib, 3704 .emit_fence = gfx_v6_0_ring_emit_fence, 3705 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3706 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3707 .test_ring = gfx_v6_0_ring_test_ring, 3708 .test_ib = gfx_v6_0_ring_test_ib, 3709 .insert_nop = amdgpu_ring_insert_nop, 3710 .emit_switch_buffer = gfx_v6_0_ring_emit_sb, 3711 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3712 .init_cond_exec = gfx_v6_0_ring_emit_init_cond_exec, 3713 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3714 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3715 }; 3716 3717 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3718 .type = AMDGPU_RING_TYPE_COMPUTE, 3719 .align_mask = 0xff, 3720 .nop = 0x80000000, 3721 .get_rptr = gfx_v6_0_ring_get_rptr, 3722 .get_wptr = gfx_v6_0_ring_get_wptr, 3723 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3724 .emit_frame_size = 3725 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_ib_schedule) */ 3726 4 + /* gfx_v6_0_ring_emit_init_cond_exec (from amdgpu_vm_flush) */ 3727 5 + 5 + /* hdp flush / invalidate */ 3728 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3729 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 2 + /* gfx_v6_0_ring_emit_vm_flush */ 3730 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3731 3 * 2 + /* gfx_v6_0_ring_emit_sb x3 (from amdgpu_vm_flush, amdgpu_ib_schedule) */ 3732 5, /* SURFACE_SYNC */ 3733 .emit_ib_size = 4, /* gfx_v6_0_ring_emit_ib */ 3734 .emit_ib = gfx_v6_0_ring_emit_ib, 3735 .emit_fence = gfx_v6_0_ring_emit_fence, 3736 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3737 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3738 .test_ring = gfx_v6_0_ring_test_ring, 3739 .test_ib = gfx_v6_0_ring_test_ib, 3740 .insert_nop = amdgpu_ring_insert_nop, 3741 .emit_switch_buffer = gfx_v6_0_ring_emit_sb, 3742 .init_cond_exec = gfx_v6_0_ring_emit_init_cond_exec, 3743 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3744 .emit_mem_sync = gfx_v6_0_emit_mem_sync, 3745 }; 3746 3747 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3748 { 3749 int i; 3750 3751 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3752 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3753 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3754 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3755 } 3756 3757 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3758 .set = gfx_v6_0_set_eop_interrupt_state, 3759 .process = gfx_v6_0_eop_irq, 3760 }; 3761 3762 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3763 .set = gfx_v6_0_set_priv_reg_fault_state, 3764 .process = gfx_v6_0_priv_reg_irq, 3765 }; 3766 3767 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3768 .set = gfx_v6_0_set_priv_inst_fault_state, 3769 .process = gfx_v6_0_priv_inst_irq, 3770 }; 3771 3772 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3773 { 3774 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3775 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3776 3777 adev->gfx.priv_reg_irq.num_types = 1; 3778 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3779 3780 adev->gfx.priv_inst_irq.num_types = 1; 3781 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3782 } 3783 3784 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3785 { 3786 int i, j, k, counter, active_cu_number = 0; 3787 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3788 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3789 unsigned disable_masks[4 * 2]; 3790 u32 ao_cu_num; 3791 3792 if (adev->flags & AMD_IS_APU) 3793 ao_cu_num = 2; 3794 else 3795 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3796 3797 memset(cu_info, 0, sizeof(*cu_info)); 3798 3799 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 3800 3801 mutex_lock(&adev->grbm_idx_mutex); 3802 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3803 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3804 mask = 1; 3805 ao_bitmap = 0; 3806 counter = 0; 3807 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3808 if (i < 4 && j < 2) 3809 gfx_v6_0_set_user_cu_inactive_bitmap( 3810 adev, disable_masks[i * 2 + j]); 3811 bitmap = gfx_v6_0_get_cu_enabled(adev); 3812 cu_info->bitmap[0][i][j] = bitmap; 3813 3814 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3815 if (bitmap & mask) { 3816 if (counter < ao_cu_num) 3817 ao_bitmap |= mask; 3818 counter ++; 3819 } 3820 mask <<= 1; 3821 } 3822 active_cu_number += counter; 3823 if (i < 2 && j < 2) 3824 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3825 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3826 } 3827 } 3828 3829 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3830 mutex_unlock(&adev->grbm_idx_mutex); 3831 3832 cu_info->number = active_cu_number; 3833 cu_info->ao_cu_mask = ao_cu_mask; 3834 } 3835 3836 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3837 { 3838 .type = AMD_IP_BLOCK_TYPE_GFX, 3839 .major = 6, 3840 .minor = 0, 3841 .rev = 0, 3842 .funcs = &gfx_v6_0_ip_funcs, 3843 }; 3844