1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef GFX_V12_1_PKT_H 25 #define GFX_V12_1_PKT_H 26 27 /** 28 * PM4 definitions 29 */ 30 #define PACKET_TYPE0 0 31 #define PACKET_TYPE1 1 32 #define PACKET_TYPE2 2 33 #define PACKET_TYPE3 3 34 35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 36 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 37 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 38 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 39 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 40 ((reg) & 0xFFFF) | \ 41 ((n) & 0x3FFF) << 16) 42 #define CP_PACKET2 0x80000000 43 #define PACKET2_PAD_SHIFT 0 44 #define PACKET2_PAD_MASK (0x3fffffff << 0) 45 46 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 47 48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 49 (((op) & 0xFF) << 8) | \ 50 ((n) & 0x3FFF) << 16) 51 52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 53 54 /* Packet 3 types */ 55 #define PACKET3_NOP 0x10 56 #define PACKET3_CLEAR_STATE 0x12 57 #define PACKET3_INDEX_BUFFER_SIZE 0x13 58 #define PACKET3_DISPATCH_DIRECT 0x15 59 #define PACKET3_DISPATCH_INDIRECT 0x16 60 #define PACKET3_ATOMIC_MEM 0x1E 61 #define PACKET3_OCCLUSION_QUERY 0x1F 62 #define PACKET3_SET_PREDICATION 0x20 63 #define PACKET3_REG_RMW 0x21 64 #define PACKET3_COND_EXEC 0x22 65 #define PACKET3_PRED_EXEC 0x23 66 #define PACKET3_DRAW_INDIRECT 0x24 67 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 68 #define PACKET3_INDEX_BASE 0x26 69 #define PACKET3_DRAW_INDEX_2 0x27 70 #define PACKET3_CONTEXT_CONTROL 0x28 71 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 72 #define PACKET3_DRAW_INDEX_AUTO 0x2D 73 #define PACKET3_NUM_INSTANCES 0x2F 74 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 75 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 76 #define PACKET3_WRITE_DATA 0x37 77 #define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) 78 /* 0 - register 79 * 1 - reserved 80 * 2 - tc_l2 81 * 3 - reserved 82 * 4 - reserved 83 * 5 - memory (same as tc_l2) 84 * 6 - memory_mapped_adc_persistent_state 85 */ 86 #define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) 87 #define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) 88 /* 0 - local xcd 89 * 1 - remote/local aid 90 * 2 - remote xcd 91 * 3 - remote mid 92 */ 93 #define WRITE_DATA_ADDR_INCR (1 << 16) 94 #define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) 95 #define WR_CONFIRM (1 << 20) 96 #define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) 97 #define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) 98 /* 0 - rt 99 * 1 - nt 100 * 2 - ht 101 * 3 - lu 102 */ 103 #define WRITE_DATA_COOP_DISABLE (1 << 27) 104 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 105 #define PACKET3_WAIT_REG_MEM 0x3C 106 #define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) 107 /* 0 - always 108 * 1 - < 109 * 2 - <= 110 * 3 - == 111 * 4 - != 112 * 5 - >= 113 * 6 - > 114 */ 115 #define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) 116 /* 0 - reg 117 * 1 - mem 118 */ 119 #define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) 120 /* 0 - wait_reg_mem 121 * 1 - wr_wait_wr_reg 122 */ 123 #define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) 124 /* 0 - local xcd 125 * 1 - remote/local aid 126 * 2 - remote xcd 127 * 3 - remote mid 128 */ 129 #define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) 130 #define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) 131 #define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) 132 #define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) 133 #define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) 134 /* 0 - rt 135 * 1 - nt 136 * 2 - ht 137 * 3 - lu 138 */ 139 #define PACKET3_INDIRECT_BUFFER 0x3F 140 #define INDIRECT_BUFFER_VALID (1 << 23) 141 #define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) 142 /* 0 - rt 143 * 1 - nt 144 * 2 - ht 145 * 3 - lu 146 */ 147 #define PACKET3_COND_INDIRECT_BUFFER 0x3F 148 #define PACKET3_COPY_DATA 0x40 149 #define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) 150 #define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) 151 #define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) 152 #define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) 153 #define COPY_DATA_MODE(x) (((x) & 0x3) << 6) 154 /* 0 - local xcd 155 * 1 - remote/local aid 156 * 2 - remote xcd 157 * 3 - remote mid 158 */ 159 #define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) 160 #define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) 161 /* 0 - rt 162 * 1 - nt 163 * 2 - ht 164 * 3 - lu 165 */ 166 #define COPY_DATA_COUNT_SEL (1 << 16) 167 #define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) 168 /* 0 - src remote 169 * 1 - dst remote 170 */ 171 #define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) 172 #define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) 173 #define COPY_DATA_PQ_EXE_STATUS (1 << 27) 174 #define PACKET3_PFP_SYNC_ME 0x42 175 #define PACKET3_COND_WRITE 0x45 176 #define PACKET3_EVENT_WRITE 0x46 177 #define EVENT_TYPE(x) ((x) << 0) 178 #define EVENT_INDEX(x) ((x) << 8) 179 /* 0 - any non-TS event 180 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 181 * 2 - SAMPLE_PIPELINESTAT 182 * 3 - SAMPLE_STREAMOUTSTAT* 183 * 4 - *S_PARTIAL_FLUSH 184 */ 185 #define PACKET3_RELEASE_MEM 0x49 186 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 187 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) 188 #define PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(x) ((x) << 12) 189 #define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) 190 #define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) 191 #define PACKET3_RELEASE_MEM_GCR_GL2_RANGE(x) ((x) << 17) 192 #define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) 193 #define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) 194 #define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) 195 #define PACKET3_RELEASE_MEM_GCR_SEQ(x) ((x) << 22) 196 #define PACKET3_RELEASE_MEM_GCR_GLV_WB (1 << 24) 197 #define PACKET3_RELEASE_MEM_TEMPORAL(x) ((x) << 25) 198 /* 0 - temporal__release_mem__rt 199 * 1 - temporal__release_mem__nt 200 * 2 - temporal__release_mem__ht 201 * 3 - temporal__release_mem__lu 202 */ 203 #define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) 204 #define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) 205 206 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 207 /* 0 - memory controller 208 * 1 - TC/L2 209 * 2 - register 210 */ 211 #define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) 212 #define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) 213 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 214 /* 0 - none 215 * 1 - interrupt only (DATA_SEL = 0) 216 * 2 - interrupt when data write is confirmed 217 */ 218 #define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) 219 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 220 /* 0 - discard 221 * 1 - send low 32bit data 222 * 2 - send 64bit data 223 * 3 - send 64bit GPU counter value 224 * 4 - send 64bit sys counter value 225 */ 226 227 #define PACKET3_PREAMBLE_CNTL 0x4A 228 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 229 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 230 #define PACKET3_DMA_DATA 0x50 231 /* 1. header 232 * 2. CONTROL 233 * 3. SRC_ADDR_LO or DATA [31:0] 234 * 4. SRC_ADDR_HI [31:0] 235 * 5. DST_ADDR_LO [31:0] 236 * 6. DST_ADDR_HI [7:0] 237 * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 238 */ 239 /* CONTROL */ 240 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 241 /* 0 - ME 242 * 1 - PFP 243 */ 244 # define PACKET3_DMA_DATA_SRC_TEMPORAL(x) ((x) << 13) 245 /* 0 - rt 246 * 1 - nt 247 * 2 - ht 248 * 3 - lu 249 */ 250 # define PACKET3_DMA_DATA_SRC_SCOPE(x) ((x) << 15) 251 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 252 /* 0 - DST_ADDR using DAS 253 * 1 - GDS 254 * 3 - DST_ADDR using L2 255 */ 256 # define PACKET3_DMA_DATA_DST_TEMPORAL(x) ((x) << 25) 257 /* 0 - LRU 258 * 1 - Stream 259 */ 260 # define PACKET3_DMA_DATA_DST_SCOPE(x) ((x) << 27) 261 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 262 /* 0 - SRC_ADDR using SAS 263 * 1 - GDS 264 * 2 - DATA 265 * 3 - SRC_ADDR using L2 266 */ 267 /* COMMAND */ 268 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 269 /* 0 - memory 270 * 1 - register 271 */ 272 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 273 /* 0 - memory 274 * 1 - register 275 */ 276 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 277 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 278 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 279 # define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) 280 #define PACKET3_CONTEXT_REG_RMW 0x51 281 #define PACKET3_ACQUIRE_MEM 0x58 282 /* 1. HEADER 283 * 2. COHER_CNTL [30:0] 284 * 2.1 ENGINE_SEL [31:31] 285 * 2. COHER_SIZE [31:0] 286 * 3. COHER_SIZE_HI [7:0] 287 * 4. COHER_BASE_LO [31:0] 288 * 5. COHER_BASE_HI [23:0] 289 * 7. POLL_INTERVAL [15:0] 290 * 8. GCR_CNTL [18:0] 291 */ 292 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) 293 /* 294 * 0:NOP 295 * 1:ALL 296 * 2:RANGE 297 * 3:FIRST_LAST 298 */ 299 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) 300 /* 301 * 0:ALL 302 * 1:reserved 303 * 2:RANGE 304 * 3:FIRST_LAST 305 */ 306 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(x) ((x) << 4) 307 /* 308 * 0:Device scope 309 * 1:System scope 310 * 2:Force INV/WB all 311 * 3:Reserved 312 */ 313 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_WB(x) ((x) << 6) 314 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) 315 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) 316 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) 317 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) 318 /* 319 * 0:ALL 320 * 1:VOL 321 * 2:RANGE 322 * 3:FIRST_LAST 323 */ 324 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) 325 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) 326 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) 327 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) 328 /* 329 * 0: PARALLEL 330 * 1: FORWARD 331 * 2: REVERSE 332 */ 333 #define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) 334 #define PACKET3_GEN_PDEPTE 0x5B 335 #define PACKET3_PRIME_UTCL2 0x5D 336 #define PACKET3_LOAD_UCONFIG_REG 0x5E 337 #define PACKET3_LOAD_SH_REG 0x5F 338 #define PACKET3_LOAD_CONFIG_REG 0x60 339 #define PACKET3_LOAD_CONTEXT_REG 0x61 340 #define PACKET3_LOAD_COMPUTE_STATE 0x62 341 #define PACKET3_LOAD_SH_REG_INDEX 0x63 342 #define PACKET3_SET_CONFIG_REG 0x68 343 #define PACKET3_SET_CONFIG_REG_START 0x00002000 344 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 345 #define PACKET3_SET_CONTEXT_REG 0x69 346 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 347 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 348 #define PACKET3_SET_SH_REG 0x76 349 #define PACKET3_SET_SH_REG_START 0x00002c00 350 #define PACKET3_SET_SH_REG_END 0x00003000 351 #define PACKET3_SET_SH_REG_OFFSET 0x77 352 #define PACKET3_SET_QUEUE_REG 0x78 353 #define PACKET3_SET_UCONFIG_REG 0x79 354 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 355 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 356 #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 357 #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 358 #define PACKET3_DISPATCH_DRAW 0x8D 359 #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 360 #define PACKET3_WAIT_REG_MEM64 0x93 361 #define PACKET3_HDP_FLUSH 0x95 362 #define PACKET3_INVALIDATE_TLBS 0x98 363 #define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 364 #define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 365 #define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 366 #define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 367 368 #define PACKET3_DMA_DATA_FILL_MULTI 0x9A 369 #define PACKET3_SET_SH_REG_INDEX 0x9B 370 #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 371 #define PACKET3_SET_RESOURCES 0xA0 372 /* 1. header 373 * 2. CONTROL 374 * 3. QUEUE_MASK_LO [31:0] 375 * 4. QUEUE_MASK_HI [31:0] 376 * 5. GWS_MASK_LO [31:0] 377 * 6. GWS_MASK_HI [31:0] 378 * 7. OAC_MASK [15:0] 379 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 380 */ 381 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 382 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 383 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 384 #define PACKET3_MAP_QUEUES 0xA2 385 /* 1. header 386 * 2. CONTROL 387 * 3. CONTROL2 388 * 4. MQD_ADDR_LO [31:0] 389 * 5. MQD_ADDR_HI [31:0] 390 * 6. WPTR_ADDR_LO [31:0] 391 * 7. WPTR_ADDR_HI [31:0] 392 */ 393 /* CONTROL */ 394 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 395 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 396 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 397 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 398 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 399 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 400 # define PACKET3_MAP_QUEUES_QUEUE_GROUP(x) ((x) << 24) 401 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 402 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 403 /* CONTROL2 */ 404 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 405 #define PACKET3_UNMAP_QUEUES 0xA3 406 /* 1. header 407 * 2. CONTROL 408 * 3. CONTROL2 409 * 4. CONTROL3 410 * 5. CONTROL4 411 * 6. CONTROL5 412 */ 413 /* CONTROL */ 414 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 415 /* 0 - PREEMPT_QUEUES 416 * 1 - RESET_QUEUES 417 * 2 - DISABLE_PROCESS_QUEUES 418 * 3 - PREEMPT_QUEUES_NO_UNMAP 419 */ 420 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 421 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 422 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 423 /* CONTROL2a */ 424 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 425 /* CONTROL2b */ 426 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 427 /* CONTROL3a */ 428 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 429 /* CONTROL3b */ 430 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 431 /* CONTROL4 */ 432 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 433 /* CONTROL5 */ 434 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 435 #define PACKET3_QUERY_STATUS 0xA4 436 /* 1. header 437 * 2. CONTROL 438 * 3. CONTROL2 439 * 4. ADDR_LO [31:0] 440 * 5. ADDR_HI [31:0] 441 * 6. DATA_LO [31:0] 442 * 7. DATA_HI [31:0] 443 */ 444 /* CONTROL */ 445 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 446 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 447 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 448 /* CONTROL2a */ 449 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 450 /* CONTROL2b */ 451 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 452 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 28) 453 454 #endif 455