1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef GFX_V12_1_PKT_H 25 #define GFX_V12_1_PKT_H 26 27 /** 28 * PM4 definitions 29 */ 30 #define PACKET_TYPE0 0 31 #define PACKET_TYPE1 1 32 #define PACKET_TYPE2 2 33 #define PACKET_TYPE3 3 34 35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 36 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 37 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 38 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 39 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 40 ((reg) & 0xFFFF) | \ 41 ((n) & 0x3FFF) << 16) 42 #define CP_PACKET2 0x80000000 43 #define PACKET2_PAD_SHIFT 0 44 #define PACKET2_PAD_MASK (0x3fffffff << 0) 45 46 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 47 48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 49 (((op) & 0xFF) << 8) | \ 50 ((n) & 0x3FFF) << 16) 51 52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 53 54 /* Packet 3 types */ 55 #define PACKET3_NOP 0x10 56 #define PACKET3_CLEAR_STATE 0x12 57 #define PACKET3_INDEX_BUFFER_SIZE 0x13 58 #define PACKET3_DISPATCH_DIRECT 0x15 59 #define PACKET3_DISPATCH_INDIRECT 0x16 60 #define PACKET3_ATOMIC_MEM 0x1E 61 #define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0) 62 #define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8) 63 #define PACKET3_ATOMIC_MEM__SCOPE(x) ((((unsigned)(x)) & 0x3) << 23) 64 #define PACKET3_ATOMIC_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 65 #define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) 66 #define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) 67 #define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x))) 68 #define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x))) 69 #define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x))) 70 #define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x))) 71 #define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0) 72 #define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0 73 #define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1 74 #define PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2 75 #define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3 76 #define PACKET3_ATOMIC_MEM__SCOPE__CU 0 77 #define PACKET3_ATOMIC_MEM__SCOPE__SE 1 78 #define PACKET3_ATOMIC_MEM__SCOPE__DEVICE 2 79 #define PACKET3_ATOMIC_MEM__SCOPE__SYSTEM 3 80 #define PACKET3_ATOMIC_MEM__TEMPORAL__RT 0 81 #define PACKET3_ATOMIC_MEM__TEMPORAL__NT 1 82 #define PACKET3_ATOMIC_MEM__TEMPORAL__FW 2 83 #define PACKET3_ATOMIC_MEM__TEMPORAL__UC 3 84 #define PACKET3_OCCLUSION_QUERY 0x1F 85 #define PACKET3_SET_PREDICATION 0x20 86 #define PACKET3_REG_RMW 0x21 87 #define PACKET3_COND_EXEC 0x22 88 #define PACKET3_PRED_EXEC 0x23 89 #define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0) 90 #define PACKET3_PRED_EXEC__VIRTUALXCCID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24) 91 #define PACKET3_DRAW_INDIRECT 0x24 92 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 93 #define PACKET3_INDEX_BASE 0x26 94 #define PACKET3_DRAW_INDEX_2 0x27 95 #define PACKET3_CONTEXT_CONTROL 0x28 96 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 97 #define PACKET3_DRAW_INDEX_AUTO 0x2D 98 #define PACKET3_NUM_INSTANCES 0x2F 99 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 100 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 101 #define PACKET3_WRITE_DATA 0x37 102 #define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) 103 #define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 104 #define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2 105 #define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5 106 #define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6 107 /* 0 - register 108 * 1 - reserved 109 * 2 - tc_l2 110 * 3 - reserved 111 * 4 - reserved 112 * 5 - memory (same as tc_l2) 113 * 6 - memory_mapped_adc_persistent_state 114 */ 115 #define PACKET3_WRITE_DATA__SCOPE(x) ((((unsigned)(x)) & 0x3) << 12) 116 #define PACKET3_WRITE_DATA__SCOPE__CU 0 117 #define PACKET3_WRITE_DATA__SCOPE__SE 1 118 #define PACKET3_WRITE_DATA__SCOPE__DEVICE 2 119 #define PACKET3_WRITE_DATA__SCOPE__SYSTEM 3 120 #define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 14) 121 #define PACKET3_WRITE_DATA__MODE__LOCAL_XCD 0 122 #define PACKET3_WRITE_DATA__MODE__REMOTE_OR_LOCAL_AID 1 123 #define PACKET3_WRITE_DATA__MODE__REMOTE_XCD 2 124 #define PACKET3_WRITE_DATA__MODE__REMOTE_MID 3 125 /* 0 - local xcd 126 * 1 - remote/local aid 127 * 2 - remote xcd 128 * 3 - remote mid 129 */ 130 #define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16) 131 #define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0 132 #define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1 133 #define PACKET3_WRITE_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) 134 #define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) 135 #define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0 136 #define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1 137 #define PACKET3_WRITE_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) 138 #define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 139 #define PACKET3_WRITE_DATA__TEMPORAL__RT 0 140 #define PACKET3_WRITE_DATA__TEMPORAL__NT 1 141 #define PACKET3_WRITE_DATA__TEMPORAL__HT 2 142 #define PACKET3_WRITE_DATA__TEMPORAL__LU 3 143 #define PACKET3_WRITE_DATA__COOP_DISABLE(x) ((((unsigned)(x)) & 0x1) << 27) 144 #define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_AND_SLAVE_COOP 0 145 #define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_ONLY 1 146 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x)) 147 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 148 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) 149 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x)) 150 #define PACKET3_WRITE_DATA__DATA(x) ((unsigned)(x)) 151 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 152 #define PACKET3_WAIT_REG_MEM 0x3C 153 #define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0) 154 #define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0 155 #define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1 156 #define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2 157 #define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3 158 #define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4 159 #define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5 160 #define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6 161 /* 0 - always 162 * 1 - < 163 * 2 - <= 164 * 3 - == 165 * 4 - != 166 * 5 - >= 167 * 6 - > 168 */ 169 #define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4) 170 #define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0 171 #define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1 172 /* 0 - reg 173 * 1 - mem 174 */ 175 #define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6) 176 #define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0 177 #define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1 178 #define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3 179 /* 0 - wait_reg_mem 180 * 1 - wr_wait_wr_reg 181 * 2 - reserved 182 * 3 - wait_mem_preemptable 183 */ 184 #define PACKET3_WAIT_REG_MEM__MODE(x) ((((unsigned)(x)) & 0x3) << 10) 185 #define PACKET3_WAIT_REG_MEM__MODE__LOCAL_XCD 0 186 #define PACKET3_WAIT_REG_MEM__MODE__REMOTE_OR_LOCAL_AID 1 187 #define PACKET3_WAIT_REG_MEM__MODE__REMOTE_XCD 2 188 #define PACKET3_WAIT_REG_MEM__MODE__REMOTE_MID 3 189 /* 0 - local xcd 190 * 1 - remote/local aid 191 * 2 - remote xcd 192 * 3 - remote mid 193 */ 194 #define PACKET3_WAIT_REG_MEM__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 12) 195 #define PACKET3_WAIT_REG_MEM__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xf) << 14) 196 #define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22) 197 #define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24) 198 #define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 199 #define PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0 200 #define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1 201 #define PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2 202 #define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3 203 /* 0 - rt 204 * 1 - nt 205 * 2 - ht 206 * 3 - lu 207 */ 208 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 209 #define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((unsigned)(x)) 210 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 211 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x)) 212 #define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) 213 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0) 214 #define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x)) 215 #define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) 216 #define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) 217 #define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31) 218 #define PACKET3_INDIRECT_BUFFER 0x3F 219 #define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 220 #define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x)) 221 #define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0) 222 #define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20) 223 #define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21) 224 #define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23) 225 #define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24) 226 #define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28) 227 #define PACKET3_INDIRECT_BUFFER__INHERIT_VMID(x) ((((unsigned)(x)) & 0x1) << 30) 228 #define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31) 229 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0 230 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1 231 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2 232 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3 233 #define PACKET3_COND_INDIRECT_BUFFER 0x3F 234 #define PACKET3_COPY_DATA 0x40 235 #define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0) 236 #define PACKET3_COPY_DATA__SRC_SCOPE(x) ((((unsigned)(x)) & 0x3) << 4) 237 #define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 6) 238 #define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) 239 #define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13) 240 #define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16) 241 #define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE(x) ((((unsigned)(x)) & 0x1) << 17) 242 #define PACKET3_COPY_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) 243 #define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) 244 #define PACKET3_COPY_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) 245 #define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 246 #define PACKET3_COPY_DATA__DST_SCOPE(x) ((((unsigned)(x)) & 0x3) << 27) 247 #define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29) 248 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x)) 249 #define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 250 #define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 251 #define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) 252 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) 253 #define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x)) 254 #define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x)) 255 #define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x)) 256 #define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 257 #define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 258 #define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) 259 #define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x)) 260 #define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0 261 #define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1 262 #define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2 263 #define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4 264 #define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5 265 #define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6 266 #define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9 267 #define PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10 268 #define PACKET3_COPY_DATA__SRC_SCOPE__CU 0 269 #define PACKET3_COPY_DATA__SRC_SCOPE__SE 1 270 #define PACKET3_COPY_DATA__SRC_SCOPE__DEVICE 2 271 #define PACKET3_COPY_DATA__SRC_SCOPE__SYSTEM 3 272 #define PACKET3_COPY_DATA__MODE__LOCAL_XCD 0 273 #define PACKET3_COPY_DATA__MODE__REMOTE_OR_LOCAL_AID 1 274 #define PACKET3_COPY_DATA__MODE__REMOTE_XCD 2 275 #define PACKET3_COPY_DATA__MODE__REMOTE_MID 3 276 #define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 277 #define PACKET3_COPY_DATA__DST_SEL__TC_L2 2 278 #define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4 279 #define PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5 280 #define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6 281 #define PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0 282 #define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1 283 #define PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2 284 #define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3 285 #define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0 286 #define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1 287 #define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__SRC_IS_REMOTE 0 288 #define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__DST_IS_REMOTE 1 289 #define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0 290 #define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1 291 #define PACKET3_COPY_DATA__DST_TEMPORAL__RT 0 292 #define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1 293 #define PACKET3_COPY_DATA__DST_TEMPORAL__HT 2 294 #define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3 295 #define PACKET3_COPY_DATA__DST_SCOPE__CU 0 296 #define PACKET3_COPY_DATA__DST_SCOPE__SE 1 297 #define PACKET3_COPY_DATA__DST_SCOPE__DEVICE 2 298 #define PACKET3_COPY_DATA__DST_SCOPE__SYSTEM 3 299 #define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0 300 #define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1 301 #define PACKET3_PFP_SYNC_ME 0x42 302 #define PACKET3_COND_WRITE 0x45 303 #define PACKET3_EVENT_WRITE 0x46 304 #define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) 305 #define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) 306 #define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31) 307 #define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 308 #define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x)) 309 #define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0 310 #define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2 311 #define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4 312 #define PACKET3_EVENT_WRITE_EOP 0x47 313 #define PACKET3_EVENT_WRITE_EOS 0x48 314 #define PACKET3_RELEASE_MEM 0x49 315 #define PACKET3_RELEASE_MEM__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) 316 #define PACKET3_RELEASE_MEM__WAIT_SYNC(x) ((((unsigned)(x)) & 0x1) << 7) 317 #define PACKET3_RELEASE_MEM__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) 318 #define PACKET3_RELEASE_MEM__EVENT_INDEX__END_OF_PIPE 5 319 #define PACKET3_RELEASE_MEM__EVENT_INDEX__SHADER_DONE 6 320 #define PACKET3_RELEASE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x1FFF) << 12) 321 #define PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(x) ((x) << 12) 322 #define PACKET3_RELEASE_MEM__GCR_GLV_INV (1 << 14) 323 #define PACKET3_RELEASE_MEM__GCR_GL2_US (1 << 16) 324 #define PACKET3_RELEASE_MEM__GCR_GL2_RANGE(x) ((x) << 17) 325 #define PACKET3_RELEASE_MEM__GCR_GL2_DISCARD (1 << 19) 326 #define PACKET3_RELEASE_MEM__GCR_GL2_INV (1 << 20) 327 #define PACKET3_RELEASE_MEM__GCR_GL2_WB (1 << 21) 328 #define PACKET3_RELEASE_MEM__GCR_SEQ(x) ((x) << 22) 329 #define PACKET3_RELEASE_MEM__GCR_GLV_WB (1 << 24) 330 #define PACKET3_RELEASE_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) 331 #define PACKET3_RELEASE_MEM__TEMPORAL__RT 0 332 #define PACKET3_RELEASE_MEM__TEMPORAL__NT 1 333 #define PACKET3_RELEASE_MEM__TEMPORAL__HT 2 334 #define PACKET3_RELEASE_MEM__TEMPORAL__LU 3 335 /* 0 - temporal__release_mem__rt 336 * 1 - temporal__release_mem__nt 337 * 2 - temporal__release_mem__ht 338 * 3 - temporal__release_mem__lu 339 */ 340 #define PACKET3_RELEASE_MEM__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 28) 341 #define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__DEFAULT 0 342 #define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__PHASE_UPDATE 1 343 #define PACKET3_RELEASE_MEM__GCR_GLK_INV (1 << 30) 344 345 #define PACKET3_RELEASE_MEM__DST_SEL(x) ((((unsigned)(x)) & 0x3) << 16) 346 #define PACKET3_RELEASE_MEM__DST_SEL__MEMORY_CONTROLLER 0 347 #define PACKET3_RELEASE_MEM__DST_SEL__TC_L2 1 348 #define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_REGISTER 2 349 #define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_POLL_MASK_BIT 3 350 #define PACKET3_RELEASE_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 20) 351 #define PACKET3_RELEASE_MEM__MES_ACTION_ID(x) ((((unsigned)(x)) & 0x3) << 22) 352 #define PACKET3_RELEASE_MEM__MES_ACTION_ID__NO_MES_NOTIFICATION 0 353 #define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_FENCE 1 354 #define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_NO_FENCE_THEN_ADDRESS_PAYLOAD 2 355 #define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_ADDRESS_PAYLOAD 3 356 #define PACKET3_RELEASE_MEM__INT_SEL(x) ((((unsigned)(x)) & 0x7) << 24) 357 #define PACKET3_RELEASE_MEM__INT_SEL__NONE 0 358 #define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_ONLY 1 359 #define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_AFTER_WRITE_CONFIRM 2 360 #define PACKET3_RELEASE_MEM__INT_SEL__SEND_DATA_AND_WRITE_CONFIRM 3 361 #define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID 4 362 #define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_32_BIT_COMPARE 5 363 #define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_64_BIT_COMPARE 6 364 #define PACKET3_RELEASE_MEM__ADD_DOOREBLL_OFFSET(x) ((((unsigned)(x)) & 0x1) << 28) 365 #define PACKET3_RELEASE_MEM__DATA_SEL(x) ((((unsigned)(x)) & 0x7) << 29) 366 #define PACKET3_RELEASE_MEM__DATA_SEL__NONE 0 367 #define PACKET3_RELEASE_MEM__DATA_SEL__SEND_32_BIT_LOW 1 368 #define PACKET3_RELEASE_MEM__DATA_SEL__SEND_64_BIT_DATA 2 369 #define PACKET3_RELEASE_MEM__DATA_SEL__SEND_GPU_CLOCK_COUNTER 3 370 #define PACKET3_RELEASE_MEM__DATA_SEL__SEND_SYSTEM_CLOCK_COUNTER 4 371 /* 0 - discard 372 * 1 - send low 32bit data 373 * 2 - send 64bit data 374 * 3 - send 64bit GPU counter value 375 * 4 - send 64bit sys counter value 376 */ 377 #define PACKET3_RELEASE_MEM__ADDRESS_LO_32B(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) 378 #define PACKET3_RELEASE_MEM__ADDRESS_LO_64B(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) 379 #define PACKET3_RELEASE_MEM__ADDRESS_HI(x) ((unsigned)(x)) 380 #define PACKET3_RELEASE_MEM__DATA_LO(x) ((unsigned)(x)) 381 #define PACKET3_RELEASE_MEM__CMP_DATA_LO(x) ((unsigned)(x)) 382 #define PACKET3_RELEASE_MEM__DATA_HI(x) ((unsigned)(x)) 383 #define PACKET3_RELEASE_MEM__CMP_DATA_HI(x) ((unsigned)(x)) 384 #define PACKET3_RELEASE_MEM__INT_CTXID(x) ((unsigned)(x)) 385 386 #define PACKET3_PREAMBLE_CNTL 0x4A 387 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 388 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 389 #define PACKET3_DMA_DATA 0x50 390 /* 1. header 391 * 2. CONTROL 392 * 3. SRC_ADDR_LO or DATA [31:0] 393 * 4. SRC_ADDR_HI [31:0] 394 * 5. DST_ADDR_LO [31:0] 395 * 6. DST_ADDR_HI [7:0] 396 * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 397 */ 398 /* CONTROL */ 399 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 400 /* 0 - ME 401 * 1 - PFP 402 */ 403 # define PACKET3_DMA_DATA_SRC_TEMPORAL(x) ((x) << 13) 404 /* 0 - rt 405 * 1 - nt 406 * 2 - ht 407 * 3 - lu 408 */ 409 # define PACKET3_DMA_DATA_SRC_SCOPE(x) ((x) << 15) 410 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 411 /* 0 - DST_ADDR using DAS 412 * 1 - GDS 413 * 3 - DST_ADDR using L2 414 */ 415 # define PACKET3_DMA_DATA_DST_TEMPORAL(x) ((x) << 25) 416 /* 0 - LRU 417 * 1 - Stream 418 */ 419 # define PACKET3_DMA_DATA_DST_SCOPE(x) ((x) << 27) 420 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 421 /* 0 - SRC_ADDR using SAS 422 * 1 - GDS 423 * 2 - DATA 424 * 3 - SRC_ADDR using L2 425 */ 426 /* COMMAND */ 427 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 428 /* 0 - memory 429 * 1 - register 430 */ 431 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 432 /* 0 - memory 433 * 1 - register 434 */ 435 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 436 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 437 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 438 # define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) 439 #define PACKET3_CONTEXT_REG_RMW 0x51 440 #define PACKET3_ACQUIRE_MEM 0x58 441 /* 1. HEADER */ 442 #define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x)) 443 /* 3. COHER_SIZE [31:0] */ 444 #define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0) 445 /* 4. COHER_SIZE_HI [7:0] */ 446 #define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x)) 447 /* 5. COHER_BASE_LO [31:0] */ 448 #define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0) 449 /* 6. COHER_BASE_HI [23:0] */ 450 #define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) 451 /* 7. POLL_INTERVAL [15:0] */ 452 #define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0) 453 /* 8. GCR_CNTL [18:0] */ 454 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(x) ((x) << 0) 455 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__NOP 0 456 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__ALL 1 457 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__RANGE 2 458 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__FIRST_LAST 3 459 /* 460 * 0:NOP 461 * 1:ALL 462 * 2:RANGE 463 * 3:FIRST_LAST 464 */ 465 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE(x) ((x) << 2) 466 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__ALL 0 467 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__RANGE 2 468 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__FIRST_LAST 3 469 /* 470 * 0:ALL 471 * 1:reserved 472 * 2:RANGE 473 * 3:FIRST_LAST 474 */ 475 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(x) ((x) << 4) 476 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__DEVICE 0 477 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__SYSTEM 1 478 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__FORCE_ALL 2 479 /* 480 * 0:Device scope 481 * 1:System scope 482 * 2:Force INV/WB all 483 * 3:Reserved 484 */ 485 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_WB(x) ((x) << 6) 486 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(x) ((x) << 7) 487 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(x) ((x) << 8) 488 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_US(x) ((x) << 10) 489 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE(x) ((x) << 11) 490 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__ALL 0 491 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__VOL 1 492 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__RANGE 2 493 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__FIRST_LAST 3 494 /* 495 * 0:ALL 496 * 1:VOL 497 * 2:RANGE 498 * 3:FIRST_LAST 499 */ 500 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_DISCARD(x) ((x) << 13) 501 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(x) ((x) << 14) 502 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(x) ((x) << 15) 503 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ(x) ((x) << 16) 504 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__PARALLET 0 505 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__FORWARD 1 506 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__REVERSE 2 507 /* 508 * 0: PARALLEL 509 * 1: FORWARD 510 * 2: REVERSE 511 */ 512 #define PACKET3_ACQUIRE_MEM__GCR_CNTL__GCR_RANGE_IS_PA (1 << 18) 513 #define PACKET3_GEN_PDEPTE 0x5B 514 #define PACKET3_PRIME_UTCL2 0x5D 515 #define PACKET3_LOAD_UCONFIG_REG 0x5E 516 #define PACKET3_LOAD_SH_REG 0x5F 517 #define PACKET3_LOAD_CONFIG_REG 0x60 518 #define PACKET3_LOAD_CONTEXT_REG 0x61 519 #define PACKET3_LOAD_COMPUTE_STATE 0x62 520 #define PACKET3_LOAD_SH_REG_INDEX 0x63 521 #define PACKET3_SET_CONFIG_REG 0x68 522 #define PACKET3_SET_CONFIG_REG_START 0x00002000 523 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 524 #define PACKET3_SET_CONTEXT_REG 0x69 525 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 526 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 527 #define PACKET3_SET_SH_REG 0x76 528 #define PACKET3_SET_SH_REG_START 0x00002c00 529 #define PACKET3_SET_SH_REG_END 0x00003000 530 #define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) 531 #define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23) 532 #define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28) 533 #define PACKET3_SET_SH_REG__REG_DATA(x) (((unsigned)(x))) 534 #define PACKET3_SET_SH_REG__INDEX__DEFAULT 0 535 #define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1 536 #define PACKET3_SET_SH_REG_OFFSET 0x77 537 #define PACKET3_SET_QUEUE_REG 0x78 538 #define PACKET3_SET_UCONFIG_REG 0x79 539 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 540 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 541 #define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) 542 #define PACKET3_SET_UCONFIG_REG__REG_DATA(x) (((unsigned)(x))) 543 #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 544 #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 545 #define PACKET3_DISPATCH_DRAW 0x8D 546 #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 547 #define PACKET3_WAIT_REG_MEM64 0x93 548 #define PACKET3_HDP_FLUSH 0x95 549 #define PACKET3_INVALIDATE_TLBS 0x98 550 #define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 551 #define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 552 #define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 553 #define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 554 555 #define PACKET3_DMA_DATA_FILL_MULTI 0x9A 556 #define PACKET3_SET_SH_REG_INDEX 0x9B 557 #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 558 #define PACKET3_SET_RESOURCES 0xA0 559 /* 1. header 560 * 2. CONTROL 561 * 3. QUEUE_MASK_LO [31:0] 562 * 4. QUEUE_MASK_HI [31:0] 563 * 5. GWS_MASK_LO [31:0] 564 * 6. GWS_MASK_HI [31:0] 565 * 7. OAC_MASK [15:0] 566 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 567 */ 568 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 569 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 570 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 571 #define PACKET3_MAP_QUEUES 0xA2 572 /* 1. header 573 * 2. CONTROL 574 * 3. CONTROL2 575 * 4. MQD_ADDR_LO [31:0] 576 * 5. MQD_ADDR_HI [31:0] 577 * 6. WPTR_ADDR_LO [31:0] 578 * 7. WPTR_ADDR_HI [31:0] 579 */ 580 /* CONTROL */ 581 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 582 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 583 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 584 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 585 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 586 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 587 # define PACKET3_MAP_QUEUES_QUEUE_GROUP(x) ((x) << 24) 588 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 589 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 590 /* CONTROL2 */ 591 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 592 #define PACKET3_UNMAP_QUEUES 0xA3 593 /* 1. header 594 * 2. CONTROL 595 * 3. CONTROL2 596 * 4. CONTROL3 597 * 5. CONTROL4 598 * 6. CONTROL5 599 */ 600 /* CONTROL */ 601 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 602 /* 0 - PREEMPT_QUEUES 603 * 1 - RESET_QUEUES 604 * 2 - DISABLE_PROCESS_QUEUES 605 * 3 - PREEMPT_QUEUES_NO_UNMAP 606 */ 607 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 608 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 609 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 610 /* CONTROL2a */ 611 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 612 /* CONTROL2b */ 613 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 614 /* CONTROL3a */ 615 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 616 /* CONTROL3b */ 617 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 618 /* CONTROL4 */ 619 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 620 /* CONTROL5 */ 621 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 622 #define PACKET3_QUERY_STATUS 0xA4 623 /* 1. header 624 * 2. CONTROL 625 * 3. CONTROL2 626 * 4. ADDR_LO [31:0] 627 * 5. ADDR_HI [31:0] 628 * 6. DATA_LO [31:0] 629 * 7. DATA_HI [31:0] 630 */ 631 /* CONTROL */ 632 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 633 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 634 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 635 /* CONTROL2a */ 636 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 637 /* CONTROL2b */ 638 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 639 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 28) 640 641 #endif 642