1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_userq_fence.h" 34 #include "imu_v12_1.h" 35 #include "soc_v1_0.h" 36 #include "gfx_v12_1_pkt.h" 37 38 #include "gc/gc_12_1_0_offset.h" 39 #include "gc/gc_12_1_0_sh_mask.h" 40 #include "soc24_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_1.h" 47 #include "mes_v12_1.h" 48 #include "amdgpu_ras_mgr.h" 49 50 #define GFX12_MEC_HPD_SIZE 2048 51 #define NUM_SIMD_PER_CU_GFX12_1 4 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000000 56 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 57 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 58 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 59 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 60 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0ae06301 61 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 62 63 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); 65 66 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 67 #define DEFAULT_SH_MEM_CONFIG \ 68 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 69 (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 70 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 71 72 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); 73 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); 74 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); 75 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev); 76 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev); 77 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev); 78 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 79 struct amdgpu_cu_info *cu_info); 80 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev); 81 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 82 u32 sh_num, u32 instance, int xcc_id); 83 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 84 uint32_t val); 85 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 86 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 87 uint16_t pasid, uint32_t flush_type, 88 bool all_hub, uint8_t dst_sel); 89 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 90 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 91 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 92 bool enable); 93 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 94 bool enable, int xcc_id); 95 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); 96 97 static void gfx_v12_1_kiq_set_resources(struct amdgpu_ring *kiq_ring, 98 uint64_t queue_mask) 99 { 100 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 101 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 102 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 103 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 104 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 105 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 106 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 107 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 108 amdgpu_ring_write(kiq_ring, 0); 109 } 110 111 static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, 112 struct amdgpu_ring *ring) 113 { 114 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 115 uint64_t wptr_addr = ring->wptr_gpu_addr; 116 uint32_t me = 0, eng_sel = 0; 117 118 switch (ring->funcs->type) { 119 case AMDGPU_RING_TYPE_COMPUTE: 120 me = 1; 121 eng_sel = 0; 122 break; 123 case AMDGPU_RING_TYPE_MES: 124 me = 2; 125 eng_sel = 5; 126 break; 127 default: 128 WARN_ON(1); 129 } 130 131 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 132 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 133 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 134 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 135 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 136 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 137 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 138 PACKET3_MAP_QUEUES_ME((me)) | 139 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 140 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 141 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 142 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 143 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 144 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 145 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 146 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 147 } 148 149 static void gfx_v12_1_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 150 struct amdgpu_ring *ring, 151 enum amdgpu_unmap_queues_action action, 152 u64 gpu_addr, u64 seq) 153 { 154 struct amdgpu_device *adev = kiq_ring->adev; 155 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 156 157 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 158 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, 159 seq, kiq_ring->xcc_id); 160 return; 161 } 162 163 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 164 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 165 PACKET3_UNMAP_QUEUES_ACTION(action) | 166 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 167 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 168 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 169 amdgpu_ring_write(kiq_ring, 170 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 171 172 if (action == PREEMPT_QUEUES_NO_UNMAP) { 173 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 174 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 175 amdgpu_ring_write(kiq_ring, seq); 176 } else { 177 amdgpu_ring_write(kiq_ring, 0); 178 amdgpu_ring_write(kiq_ring, 0); 179 amdgpu_ring_write(kiq_ring, 0); 180 } 181 } 182 183 static void gfx_v12_1_kiq_query_status(struct amdgpu_ring *kiq_ring, 184 struct amdgpu_ring *ring, 185 u64 addr, u64 seq) 186 { 187 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 188 189 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 190 amdgpu_ring_write(kiq_ring, 191 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 192 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 193 PACKET3_QUERY_STATUS_COMMAND(2)); 194 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 195 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 196 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 197 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 198 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 199 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 200 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 201 } 202 203 static void gfx_v12_1_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 204 uint16_t pasid, 205 uint32_t flush_type, 206 bool all_hub) 207 { 208 gfx_v12_1_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 209 } 210 211 static const struct kiq_pm4_funcs gfx_v12_1_kiq_pm4_funcs = { 212 .kiq_set_resources = gfx_v12_1_kiq_set_resources, 213 .kiq_map_queues = gfx_v12_1_kiq_map_queues, 214 .kiq_unmap_queues = gfx_v12_1_kiq_unmap_queues, 215 .kiq_query_status = gfx_v12_1_kiq_query_status, 216 .kiq_invalidate_tlbs = gfx_v12_1_kiq_invalidate_tlbs, 217 .set_resources_size = 8, 218 .map_queues_size = 7, 219 .unmap_queues_size = 6, 220 .query_status_size = 7, 221 .invalidate_tlbs_size = 2, 222 }; 223 224 static void gfx_v12_1_set_kiq_pm4_funcs(struct amdgpu_device *adev) 225 { 226 int i, num_xcc; 227 228 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 229 for (i =0; i < num_xcc; i++) 230 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; 231 } 232 233 static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 234 int mem_space, int opt, uint32_t addr0, 235 uint32_t addr1, uint32_t ref, 236 uint32_t mask, uint32_t inv) 237 { 238 if (mem_space == 0) { 239 addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0); 240 addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1); 241 } 242 243 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 244 amdgpu_ring_write(ring, 245 /* memory (1) or register (0) */ 246 (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | 247 PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ 248 PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ 249 250 if (mem_space) 251 WARN_ON(addr0 & 0x3); /* Dword align */ 252 amdgpu_ring_write(ring, addr0); 253 amdgpu_ring_write(ring, addr1); 254 amdgpu_ring_write(ring, ref); 255 amdgpu_ring_write(ring, mask); 256 amdgpu_ring_write(ring, inv); /* poll interval */ 257 } 258 259 static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring) 260 { 261 struct amdgpu_device *adev = ring->adev; 262 uint32_t scratch_reg0_offset, xcc_offset; 263 uint32_t tmp = 0; 264 unsigned i; 265 int r; 266 267 /* Use register offset which is local to XCC in the packet */ 268 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 269 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 270 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 271 tmp = RREG32(scratch_reg0_offset); 272 273 r = amdgpu_ring_alloc(ring, 5); 274 if (r) { 275 dev_err(adev->dev, 276 "amdgpu: cp failed to lock ring %d (%d).\n", 277 ring->idx, r); 278 return r; 279 } 280 281 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 282 gfx_v12_1_ring_emit_wreg(ring, xcc_offset, 0xDEADBEEF); 283 } else { 284 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 285 amdgpu_ring_write(ring, xcc_offset - 286 PACKET3_SET_UCONFIG_REG_START); 287 amdgpu_ring_write(ring, 0xDEADBEEF); 288 } 289 amdgpu_ring_commit(ring); 290 291 for (i = 0; i < adev->usec_timeout; i++) { 292 tmp = RREG32(scratch_reg0_offset); 293 if (tmp == 0xDEADBEEF) 294 break; 295 if (amdgpu_emu_mode == 1) 296 msleep(1); 297 else 298 udelay(1); 299 } 300 301 if (i >= adev->usec_timeout) 302 r = -ETIMEDOUT; 303 return r; 304 } 305 306 static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 struct amdgpu_ib ib; 310 struct dma_fence *f = NULL; 311 unsigned index; 312 uint64_t gpu_addr; 313 volatile uint32_t *cpu_ptr; 314 long r; 315 316 /* MES KIQ fw hasn't indirect buffer support for now */ 317 if (adev->enable_mes_kiq && 318 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 319 return 0; 320 321 memset(&ib, 0, sizeof(ib)); 322 323 r = amdgpu_device_wb_get(adev, &index); 324 if (r) 325 return r; 326 327 gpu_addr = adev->wb.gpu_addr + (index * 4); 328 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 329 cpu_ptr = &adev->wb.wb[index]; 330 331 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 332 if (r) { 333 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 334 goto err1; 335 } 336 337 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 338 ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); 339 ib.ptr[2] = lower_32_bits(gpu_addr); 340 ib.ptr[3] = upper_32_bits(gpu_addr); 341 ib.ptr[4] = 0xDEADBEEF; 342 ib.length_dw = 5; 343 344 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 345 if (r) 346 goto err2; 347 348 r = dma_fence_wait_timeout(f, false, timeout); 349 if (r == 0) { 350 r = -ETIMEDOUT; 351 goto err2; 352 } else if (r < 0) { 353 goto err2; 354 } 355 356 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 357 r = 0; 358 else 359 r = -EINVAL; 360 err2: 361 amdgpu_ib_free(&ib, NULL); 362 dma_fence_put(f); 363 err1: 364 amdgpu_device_wb_free(adev, index); 365 return r; 366 } 367 368 static void gfx_v12_1_free_microcode(struct amdgpu_device *adev) 369 { 370 amdgpu_ucode_release(&adev->gfx.rlc_fw); 371 amdgpu_ucode_release(&adev->gfx.mec_fw); 372 373 kfree(adev->gfx.rlc.register_list_format); 374 } 375 376 static int gfx_v12_1_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 377 { 378 const struct psp_firmware_header_v1_0 *toc_hdr; 379 int err = 0; 380 381 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 382 AMDGPU_UCODE_REQUIRED, 383 "amdgpu/%s_toc.bin", ucode_prefix); 384 if (err) 385 goto out; 386 387 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 388 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 389 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 390 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 391 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 392 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 393 return 0; 394 out: 395 amdgpu_ucode_release(&adev->psp.toc_fw); 396 return err; 397 } 398 399 static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) 400 { 401 char ucode_prefix[15]; 402 int err; 403 const struct rlc_firmware_header_v2_0 *rlc_hdr; 404 uint16_t version_major; 405 uint16_t version_minor; 406 407 DRM_DEBUG("\n"); 408 409 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 410 411 if (!amdgpu_sriov_vf(adev)) { 412 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && 413 adev->rev_id == 0) 414 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 415 AMDGPU_UCODE_REQUIRED, 416 "amdgpu/%s_rlc_1.bin", ucode_prefix); 417 else 418 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 419 AMDGPU_UCODE_REQUIRED, 420 "amdgpu/%s_rlc.bin", ucode_prefix); 421 if (err) 422 goto out; 423 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 424 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 425 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 426 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 427 if (err) 428 goto out; 429 } 430 431 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 432 AMDGPU_UCODE_REQUIRED, 433 "amdgpu/%s_mec.bin", ucode_prefix); 434 if (err) 435 goto out; 436 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 437 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 438 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 439 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 440 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 441 442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 443 err = gfx_v12_1_init_toc_microcode(adev, ucode_prefix); 444 445 /* only one MEC for gfx 12 */ 446 adev->gfx.mec2_fw = NULL; 447 448 if (adev->gfx.imu.funcs) { 449 if (adev->gfx.imu.funcs->init_microcode) { 450 err = adev->gfx.imu.funcs->init_microcode(adev); 451 if (err) 452 dev_err(adev->dev, "Failed to load imu firmware!\n"); 453 } 454 } 455 456 out: 457 if (err) { 458 amdgpu_ucode_release(&adev->gfx.rlc_fw); 459 amdgpu_ucode_release(&adev->gfx.mec_fw); 460 } 461 462 return err; 463 } 464 465 static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev) 466 { 467 u32 count = 0; 468 const struct cs_section_def *sect = NULL; 469 const struct cs_extent_def *ext = NULL; 470 471 count += 1; 472 473 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 474 if (sect->id == SECT_CONTEXT) { 475 for (ext = sect->section; ext->extent != NULL; ++ext) 476 count += 2 + ext->reg_count; 477 } else 478 return 0; 479 } 480 481 return count; 482 } 483 484 static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 485 { 486 u32 count = 0, clustercount = 0, i; 487 const struct cs_section_def *sect = NULL; 488 const struct cs_extent_def *ext = NULL; 489 490 if (adev->gfx.rlc.cs_data == NULL) 491 return; 492 if (buffer == NULL) 493 return; 494 495 count += 1; 496 497 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 498 if (sect->id == SECT_CONTEXT) { 499 for (ext = sect->section; ext->extent != NULL; ++ext) { 500 clustercount++; 501 buffer[count++] = ext->reg_count; 502 buffer[count++] = ext->reg_index; 503 504 for (i = 0; i < ext->reg_count; i++) 505 buffer[count++] = cpu_to_le32(ext->extent[i]); 506 } 507 } else 508 return; 509 } 510 511 buffer[0] = clustercount; 512 } 513 514 static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev) 515 { 516 /* clear state block */ 517 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 518 &adev->gfx.rlc.clear_state_gpu_addr, 519 (void **)&adev->gfx.rlc.cs_ptr); 520 521 /* jump table block */ 522 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 523 &adev->gfx.rlc.cp_table_gpu_addr, 524 (void **)&adev->gfx.rlc.cp_table_ptr); 525 } 526 527 static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 528 { 529 int xcc_id, num_xcc; 530 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 531 532 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 533 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 534 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 535 536 reg_access_ctrl->grbm_cntl = 537 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 538 reg_access_ctrl->grbm_idx = 539 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 540 541 reg_access_ctrl->vfi_cmd = 542 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD); 543 reg_access_ctrl->vfi_stat = 544 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT); 545 reg_access_ctrl->vfi_addr = 546 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR); 547 reg_access_ctrl->vfi_data = 548 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA); 549 reg_access_ctrl->vfi_grbm_cntl = 550 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL); 551 reg_access_ctrl->vfi_grbm_idx = 552 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX); 553 reg_access_ctrl->vfi_grbm_cntl_data = 0; 554 reg_access_ctrl->vfi_grbm_idx_data = 0; 555 } 556 adev->gfx.rlc.rlcg_reg_access_supported = true; 557 } 558 559 static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) 560 { 561 const struct cs_section_def *cs_data; 562 int r, i, num_xcc; 563 564 adev->gfx.rlc.cs_data = gfx12_cs_data; 565 566 cs_data = adev->gfx.rlc.cs_data; 567 568 if (cs_data) { 569 /* init clear state block */ 570 r = amdgpu_gfx_rlc_init_csb(adev); 571 if (r) 572 return r; 573 } 574 575 /* init spm vmid with 0xf */ 576 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 577 for (i = 0; i < num_xcc; i++) { 578 if (adev->gfx.rlc.funcs->update_spm_vmid) 579 adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); 580 } 581 582 return 0; 583 } 584 585 static void gfx_v12_1_mec_fini(struct amdgpu_device *adev) 586 { 587 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 588 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 589 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 590 } 591 592 static int gfx_v12_1_mec_init(struct amdgpu_device *adev) 593 { 594 int r, i, num_xcc; 595 u32 *hpd; 596 size_t mec_hpd_size; 597 598 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 599 600 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 601 for (i = 0; i < num_xcc; i++) 602 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 603 AMDGPU_MAX_COMPUTE_QUEUES); 604 605 /* take ownership of the relevant compute queues */ 606 amdgpu_gfx_compute_queue_acquire(adev); 607 mec_hpd_size = adev->gfx.num_compute_rings * 608 GFX12_MEC_HPD_SIZE * num_xcc; 609 610 if (mec_hpd_size) { 611 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 612 AMDGPU_GEM_DOMAIN_GTT, 613 &adev->gfx.mec.hpd_eop_obj, 614 &adev->gfx.mec.hpd_eop_gpu_addr, 615 (void **)&hpd); 616 if (r) { 617 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 618 gfx_v12_1_mec_fini(adev); 619 return r; 620 } 621 622 memset(hpd, 0, mec_hpd_size); 623 624 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 625 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 626 } 627 628 return 0; 629 } 630 631 static uint32_t wave_read_ind(struct amdgpu_device *adev, 632 uint32_t xcc_id, uint32_t wave, 633 uint32_t address) 634 { 635 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 636 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 637 (address << SQ_IND_INDEX__INDEX__SHIFT)); 638 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 639 } 640 641 static void wave_read_regs(struct amdgpu_device *adev, 642 uint32_t xcc_id, uint32_t wave, 643 uint32_t thread, uint32_t regno, 644 uint32_t num, uint32_t *out) 645 { 646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 647 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 648 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 649 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 650 (SQ_IND_INDEX__AUTO_INCR_MASK)); 651 while (num--) 652 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 653 } 654 655 static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, 656 uint32_t xcc_id, 657 uint32_t simd, uint32_t wave, 658 uint32_t *dst, int *no_fields) 659 { 660 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 661 * field when performing a select_se_sh so it should be 662 * zero here */ 663 WARN_ON(simd != 0); 664 665 /* type 4 wave data */ 666 dst[(*no_fields)++] = 4; 667 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); 668 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); 669 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); 670 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); 671 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); 672 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); 673 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); 674 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); 675 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); 676 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); 677 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); 678 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); 679 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); 680 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); 681 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); 682 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 683 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); 684 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); 685 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); 686 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); 687 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 688 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 689 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); 690 } 691 692 static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, 693 uint32_t xcc_id, uint32_t simd, 694 uint32_t wave, uint32_t start, 695 uint32_t size, uint32_t *dst) 696 { 697 WARN_ON(simd != 0); 698 699 wave_read_regs(adev, xcc_id, wave, 0, 700 start + SQIND_WAVE_SGPRS_OFFSET, 701 size, dst); 702 } 703 704 static void gfx_v12_1_read_wave_vgprs(struct amdgpu_device *adev, 705 uint32_t xcc_id, uint32_t simd, 706 uint32_t wave, uint32_t thread, 707 uint32_t start, uint32_t size, 708 uint32_t *dst) 709 { 710 wave_read_regs(adev, xcc_id, wave, thread, 711 start + SQIND_WAVE_VGPRS_OFFSET, 712 size, dst); 713 } 714 715 static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, 716 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 717 { 718 soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 719 } 720 721 #define regGFX_IMU_PARTITION_SWITCH 0x5f8c 722 #define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 723 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 724 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL 725 726 static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) 727 { 728 u32 reg_data; 729 730 /* the register data is expected to be the same on all instances */ 731 reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); 732 733 return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); 734 } 735 736 static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 737 { 738 int logic_xcc; 739 int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; 740 741 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { 742 if (xcc == GET_INST(GC, logic_xcc)) 743 return logic_xcc; 744 } 745 746 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 747 return -EINVAL; 748 } 749 750 static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { 751 .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, 752 .select_se_sh = &gfx_v12_1_xcc_select_se_sh, 753 .read_wave_data = &gfx_v12_1_read_wave_data, 754 .read_wave_sgprs = &gfx_v12_1_read_wave_sgprs, 755 .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, 756 .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, 757 .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, 758 .get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp, 759 .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, 760 }; 761 762 static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) 763 { 764 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 765 case IP_VERSION(12, 1, 0): 766 adev->gfx.config.max_hw_contexts = 8; 767 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 768 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 769 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 770 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 771 break; 772 default: 773 BUG(); 774 break; 775 } 776 777 return 0; 778 } 779 780 static int gfx_v12_1_compute_ring_init(struct amdgpu_device *adev, int ring_id, 781 int xcc_id, int mec, int pipe, int queue) 782 { 783 int r; 784 unsigned irq_type; 785 struct amdgpu_ring *ring; 786 unsigned int hw_prio; 787 uint32_t xcc_doorbell_start; 788 789 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 790 ring_id]; 791 792 /* mec0 is me1 */ 793 ring->xcc_id = xcc_id; 794 ring->me = mec + 1; 795 ring->pipe = pipe; 796 ring->queue = queue; 797 798 ring->ring_obj = NULL; 799 ring->use_doorbell = true; 800 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 801 xcc_id * adev->doorbell_index.xcc_doorbell_range; 802 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 803 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 804 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 805 GFX12_MEC_HPD_SIZE; 806 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 807 sprintf(ring->name, "comp_%d.%d.%d.%d", 808 ring->xcc_id, ring->me, ring->pipe, ring->queue); 809 810 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 811 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 812 + ring->pipe; 813 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 814 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 815 /* type-2 packets are deprecated on MEC, use type-3 instead */ 816 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 817 hw_prio, NULL); 818 if (r) 819 return r; 820 821 return 0; 822 } 823 824 static struct { 825 SOC24_FIRMWARE_ID id; 826 unsigned int offset; 827 unsigned int size; 828 unsigned int size_x16; 829 unsigned int num_inst; 830 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 831 832 #define RLC_TOC_OFFSET_DWUNIT 8 833 #define RLC_SIZE_MULTIPLE 1024 834 #define RLC_TOC_UMF_SIZE_inM 23ULL 835 #define RLC_TOC_FORMAT_API 165ULL 836 837 #define RLC_NUM_INS_CODE0 1 838 #define RLC_NUM_INS_CODE1 8 839 #define RLC_NUM_INS_CODE2 2 840 #define RLC_NUM_INS_CODE3 16 841 842 static void gfx_v12_1_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 843 { 844 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 845 846 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 847 rlc_autoload_info[ucode->id].id = ucode->id; 848 rlc_autoload_info[ucode->id].offset = 849 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 850 rlc_autoload_info[ucode->id].size = 851 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 852 ucode->size * 4; 853 switch (ucode->vfflr_image_code) { 854 case 0: 855 rlc_autoload_info[ucode->id].num_inst = 856 RLC_NUM_INS_CODE0; 857 break; 858 case 1: 859 rlc_autoload_info[ucode->id].num_inst = 860 RLC_NUM_INS_CODE1; 861 break; 862 case 2: 863 rlc_autoload_info[ucode->id].num_inst = 864 RLC_NUM_INS_CODE2; 865 break; 866 case 3: 867 rlc_autoload_info[ucode->id].num_inst = 868 RLC_NUM_INS_CODE3; 869 break; 870 default: 871 dev_err(adev->dev, 872 "Invalid Instance number detected\n"); 873 break; 874 } 875 ucode++; 876 } 877 } 878 879 static uint32_t gfx_v12_1_calc_toc_total_size(struct amdgpu_device *adev) 880 { 881 uint32_t total_size = 0; 882 SOC24_FIRMWARE_ID id; 883 884 gfx_v12_1_parse_rlc_toc(adev, adev->psp.toc.start_addr); 885 886 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 887 total_size += rlc_autoload_info[id].size; 888 889 /* In case the offset in rlc toc ucode is aligned */ 890 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 891 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 892 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 893 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 894 total_size = RLC_TOC_UMF_SIZE_inM << 20; 895 896 return total_size; 897 } 898 899 static int gfx_v12_1_rlc_autoload_buffer_init(struct amdgpu_device *adev) 900 { 901 int r; 902 uint32_t total_size; 903 904 total_size = gfx_v12_1_calc_toc_total_size(adev); 905 906 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 907 AMDGPU_GEM_DOMAIN_VRAM, 908 &adev->gfx.rlc.rlc_autoload_bo, 909 &adev->gfx.rlc.rlc_autoload_gpu_addr, 910 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 911 912 if (r) { 913 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 914 return r; 915 } 916 917 return 0; 918 } 919 920 static void gfx_v12_1_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 921 SOC24_FIRMWARE_ID id, 922 const void *fw_data, 923 uint32_t fw_size) 924 { 925 uint32_t toc_offset; 926 uint32_t toc_fw_size, toc_fw_inst_size; 927 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 928 int i, num_inst; 929 930 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 931 return; 932 933 toc_offset = rlc_autoload_info[id].offset; 934 toc_fw_size = rlc_autoload_info[id].size; 935 num_inst = rlc_autoload_info[id].num_inst; 936 toc_fw_inst_size = toc_fw_size / num_inst; 937 938 if (fw_size == 0) 939 fw_size = toc_fw_inst_size; 940 941 if (fw_size > toc_fw_inst_size) 942 fw_size = toc_fw_inst_size; 943 944 for (i = 0; i < num_inst; i++) { 945 if ((num_inst == RLC_NUM_INS_CODE0) || 946 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { 947 memcpy(ptr + toc_offset + i * toc_fw_inst_size, fw_data, fw_size); 948 949 if (fw_size < toc_fw_inst_size) 950 memset(ptr + toc_offset + fw_size + i * toc_fw_inst_size, 951 0, toc_fw_inst_size - fw_size); 952 } 953 } 954 } 955 956 static void 957 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 958 { 959 void *data; 960 uint32_t size; 961 uint32_t *toc_ptr; 962 963 data = adev->psp.toc.start_addr; 964 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 965 966 toc_ptr = (uint32_t *)data + size / 4 - 2; 967 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 968 969 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 970 data, size); 971 } 972 973 static void 974 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 975 { 976 const __le32 *fw_data; 977 uint32_t fw_size; 978 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 979 const struct rlc_firmware_header_v2_0 *rlc_hdr; 980 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 981 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 982 uint16_t version_major, version_minor; 983 984 /* mec ucode */ 985 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 986 adev->gfx.mec_fw->data; 987 /* instruction */ 988 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 989 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 990 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 991 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 992 fw_data, fw_size); 993 /* data */ 994 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 995 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 996 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 997 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 998 fw_data, fw_size); 999 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1000 fw_data, fw_size); 1001 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1002 fw_data, fw_size); 1003 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1004 fw_data, fw_size); 1005 1006 /* rlc ucode */ 1007 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1008 adev->gfx.rlc_fw->data; 1009 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1010 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1011 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1012 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1013 fw_data, fw_size); 1014 1015 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1016 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1017 if (version_major == 2) { 1018 if (version_minor >= 1) { 1019 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1020 1021 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1022 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1023 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1024 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1025 fw_data, fw_size); 1026 1027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1028 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1029 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1030 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1031 fw_data, fw_size); 1032 } 1033 if (version_minor >= 2) { 1034 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1035 1036 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1037 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1038 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1039 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1040 fw_data, fw_size); 1041 1042 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1043 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1044 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1045 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1046 fw_data, fw_size); 1047 } 1048 } 1049 } 1050 1051 static void 1052 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1053 { 1054 const __le32 *fw_data; 1055 uint32_t fw_size; 1056 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1057 1058 if (adev->sdma.instance[0].fw) { 1059 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1060 adev->sdma.instance[0].fw->data; 1061 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1062 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1063 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1064 1065 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1066 fw_data, fw_size); 1067 } 1068 } 1069 1070 static void 1071 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1072 { 1073 const __le32 *fw_data; 1074 unsigned fw_size; 1075 const struct mes_firmware_header_v1_0 *mes_hdr; 1076 int pipe, ucode_id, data_id; 1077 1078 for (pipe = 0; pipe < 2; pipe++) { 1079 if (pipe == 0) { 1080 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1081 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1082 } else { 1083 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1084 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1085 } 1086 1087 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1088 adev->mes.fw[pipe]->data; 1089 1090 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1091 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1092 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1093 1094 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1095 1096 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1097 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1098 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1099 1100 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1101 } 1102 } 1103 1104 static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1105 { 1106 uint32_t rlc_g_offset, rlc_g_size; 1107 uint64_t gpu_addr; 1108 uint32_t data; 1109 int i, num_xcc; 1110 1111 /* RLC autoload sequence 2: copy ucode */ 1112 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1113 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1114 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(adev); 1115 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(adev); 1116 1117 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1118 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1119 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1120 1121 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1122 for (i = 0; i < num_xcc; i++) { 1123 WREG32_SOC15(GC, GET_INST(GC, i), 1124 regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, 1125 upper_32_bits(gpu_addr)); 1126 WREG32_SOC15(GC, GET_INST(GC, i), 1127 regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, 1128 lower_32_bits(gpu_addr)); 1129 WREG32_SOC15(GC, GET_INST(GC, i), 1130 regGFX_IMU_RLC_BOOTLOADER_SIZE, 1131 rlc_g_size); 1132 } 1133 1134 if (adev->gfx.imu.funcs) { 1135 /* RLC autoload sequence 3: load IMU fw */ 1136 if (adev->gfx.imu.funcs->load_microcode) 1137 adev->gfx.imu.funcs->load_microcode(adev); 1138 } 1139 1140 /* unhalt rlc to start autoload */ 1141 for (i = 0; i < num_xcc; i++) { 1142 data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE); 1143 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1144 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1145 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data); 1146 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1153 { 1154 uint16_t major_ver, minor_ver; 1155 int i, j, k, r, ring_id = 0; 1156 unsigned num_compute_rings; 1157 int xcc_id, num_xcc; 1158 struct amdgpu_device *adev = ip_block->adev; 1159 1160 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1161 case IP_VERSION(12, 1, 0): 1162 adev->gfx.mec.num_mec = 1; 1163 adev->gfx.mec.num_pipe_per_mec = 4; 1164 adev->gfx.mec.num_queue_per_pipe = 8; 1165 1166 if (!amdgpu_discovery_get_gc_major_minor_version( 1167 adev, &major_ver, &minor_ver)) { 1168 if (major_ver == 1 && minor_ver == 3) { 1169 adev->gfx.config.max_cu_per_sh /= 2; 1170 dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", 1171 adev->gfx.config.max_cu_per_sh); 1172 } 1173 } 1174 break; 1175 default: 1176 adev->gfx.mec.num_mec = 2; 1177 adev->gfx.mec.num_pipe_per_mec = 2; 1178 adev->gfx.mec.num_queue_per_pipe = 4; 1179 break; 1180 } 1181 1182 if (adev->gfx.num_compute_rings) { 1183 /* recalculate compute rings to use based on hardware configuration */ 1184 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1185 adev->gfx.mec.num_queue_per_pipe) / 2; 1186 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1187 num_compute_rings); 1188 } 1189 1190 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1191 1192 /* EOP Event */ 1193 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1194 GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, 1195 &adev->gfx.eop_irq); 1196 if (r) 1197 return r; 1198 1199 /* Privileged reg */ 1200 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1201 GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, 1202 &adev->gfx.priv_reg_irq); 1203 if (r) 1204 return r; 1205 1206 /* Privileged inst */ 1207 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1208 GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, 1209 &adev->gfx.priv_inst_irq); 1210 if (r) 1211 return r; 1212 1213 /* RLC POISON Error */ 1214 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, 1215 GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, 1216 &adev->gfx.rlc_poison_irq); 1217 if (r) 1218 return r; 1219 1220 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1221 1222 r = gfx_v12_1_rlc_init(adev); 1223 if (r) { 1224 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1225 return r; 1226 } 1227 1228 r = gfx_v12_1_mec_init(adev); 1229 if (r) { 1230 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1231 return r; 1232 } 1233 1234 /* set up the compute queues - allocate horizontally across pipes */ 1235 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1236 ring_id = 0; 1237 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1238 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1239 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1240 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1241 xcc_id, i, k, j)) 1242 continue; 1243 1244 r = gfx_v12_1_compute_ring_init(adev, ring_id, 1245 xcc_id, i, k, j); 1246 if (r) 1247 return r; 1248 1249 ring_id++; 1250 } 1251 } 1252 } 1253 1254 if (!adev->enable_mes_kiq) { 1255 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, xcc_id); 1256 if (r) { 1257 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1258 return r; 1259 } 1260 1261 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1262 if (r) 1263 return r; 1264 } 1265 1266 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_1_compute_mqd), xcc_id); 1267 if (r) 1268 return r; 1269 } 1270 1271 /* allocate visible FB for rlc auto-loading fw */ 1272 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1273 r = gfx_v12_1_rlc_autoload_buffer_init(adev); 1274 if (r) 1275 return r; 1276 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1277 r = gfx_v12_1_init_cp_compute_microcode_bo(adev); 1278 if (r) 1279 return r; 1280 } 1281 1282 r = gfx_v12_1_gpu_early_init(adev); 1283 if (r) 1284 return r; 1285 1286 r = amdgpu_gfx_sysfs_init(adev); 1287 if (r) 1288 return r; 1289 1290 return 0; 1291 } 1292 1293 static void gfx_v12_1_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1294 { 1295 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1296 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1297 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1298 } 1299 1300 static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1301 { 1302 int i, num_xcc; 1303 struct amdgpu_device *adev = ip_block->adev; 1304 1305 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1306 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1307 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1308 1309 for (i = 0; i < num_xcc; i++) { 1310 amdgpu_gfx_mqd_sw_fini(adev, i); 1311 1312 if (!adev->enable_mes_kiq) { 1313 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1314 amdgpu_gfx_kiq_fini(adev, i); 1315 } 1316 } 1317 1318 gfx_v12_1_rlc_fini(adev); 1319 gfx_v12_1_mec_fini(adev); 1320 1321 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1322 gfx_v12_1_rlc_autoload_buffer_fini(adev); 1323 1324 gfx_v12_1_free_microcode(adev); 1325 amdgpu_gfx_sysfs_fini(adev); 1326 1327 return 0; 1328 } 1329 1330 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1331 u32 sh_num, u32 instance, int xcc_id) 1332 { 1333 u32 data; 1334 1335 if (instance == 0xffffffff) 1336 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1337 INSTANCE_BROADCAST_WRITES, 1); 1338 else 1339 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1340 instance); 1341 1342 if (se_num == 0xffffffff) 1343 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1344 1); 1345 else 1346 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1347 1348 if (sh_num == 0xffffffff) 1349 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1350 1); 1351 else 1352 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1353 1354 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 1355 } 1356 1357 static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, 1358 int xcc_id) 1359 { 1360 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1361 1362 gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE); 1363 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1364 CC_GC_SA_UNIT_DISABLE, 1365 SA_DISABLE); 1366 gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE); 1367 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1368 GC_USER_SA_UNIT_DISABLE, 1369 SA_DISABLE); 1370 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1371 adev->gfx.config.max_shader_engines); 1372 1373 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1374 } 1375 1376 static u32 gfx_v12_1_get_rb_active_bitmap(struct amdgpu_device *adev, 1377 int xcc_id) 1378 { 1379 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1380 u32 rb_mask; 1381 1382 gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1383 regCC_RB_BACKEND_DISABLE); 1384 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1385 CC_RB_BACKEND_DISABLE, 1386 BACKEND_DISABLE); 1387 gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1388 regGC_USER_RB_BACKEND_DISABLE); 1389 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1390 GC_USER_RB_BACKEND_DISABLE, 1391 BACKEND_DISABLE); 1392 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1393 adev->gfx.config.max_shader_engines); 1394 1395 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1396 } 1397 1398 static void gfx_v12_1_setup_rb(struct amdgpu_device *adev) 1399 { 1400 u32 rb_bitmap_width_per_sa; 1401 u32 max_sa; 1402 u32 active_sa_bitmap; 1403 u32 global_active_rb_bitmap; 1404 u32 active_rb_bitmap = 0; 1405 u32 i; 1406 int xcc_id; 1407 1408 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 1409 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1410 active_sa_bitmap = gfx_v12_1_get_sa_active_bitmap(adev, xcc_id); 1411 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1412 global_active_rb_bitmap = gfx_v12_1_get_rb_active_bitmap(adev, xcc_id); 1413 1414 /* generate active rb bitmap according to active sa bitmap */ 1415 max_sa = adev->gfx.config.max_shader_engines * 1416 adev->gfx.config.max_sh_per_se; 1417 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1418 adev->gfx.config.max_sh_per_se; 1419 for (i = 0; i < max_sa; i++) { 1420 if (active_sa_bitmap & (1 << i)) 1421 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1422 } 1423 1424 active_rb_bitmap |= global_active_rb_bitmap; 1425 } 1426 1427 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1428 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1429 } 1430 1431 static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, 1432 int xcc_id) 1433 { 1434 int i; 1435 uint32_t sh_mem_bases; 1436 uint32_t data; 1437 1438 /* 1439 * Configure apertures: 1440 * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) 1441 * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) 1442 */ 1443 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1444 (adev->gmc.private_aperture_start >> 58)); 1445 sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, 1446 (adev->gmc.shared_aperture_start >> 48)); 1447 1448 mutex_lock(&adev->srbm_mutex); 1449 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1450 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1451 /* CP and shaders */ 1452 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1453 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1454 1455 /* Enable trap for each kfd vmid. */ 1456 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1457 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1458 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1459 1460 /* Disable VGPR deallocation instruction for each KFD vmid. */ 1461 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG); 1462 data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1); 1463 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data); 1464 } 1465 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1466 mutex_unlock(&adev->srbm_mutex); 1467 } 1468 1469 static void gfx_v12_1_tcp_harvest(struct amdgpu_device *adev) 1470 { 1471 /* TODO: harvest feature to be added later. */ 1472 } 1473 1474 static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) 1475 { 1476 } 1477 1478 static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) 1479 { 1480 /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ 1481 mutex_lock(&adev->srbm_mutex); 1482 if (!adev->gmc.noretry) { 1483 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1484 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); 1485 } else 1486 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1487 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); 1488 mutex_unlock(&adev->srbm_mutex); 1489 } 1490 1491 static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, 1492 int xcc_id) 1493 { 1494 u32 tmp; 1495 int i; 1496 1497 /* XXX SH_MEM regs */ 1498 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1499 mutex_lock(&adev->srbm_mutex); 1500 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1501 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1502 /* CP and shaders */ 1503 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1504 regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1505 if (i != 0) { 1506 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1507 (adev->gmc.private_aperture_start >> 58)); 1508 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1509 (adev->gmc.shared_aperture_start >> 48)); 1510 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); 1511 } 1512 } 1513 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1514 1515 mutex_unlock(&adev->srbm_mutex); 1516 1517 gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); 1518 gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); 1519 1520 } 1521 1522 static void gfx_v12_1_constants_init(struct amdgpu_device *adev) 1523 { 1524 int i, num_xcc; 1525 1526 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1527 1528 gfx_v12_1_setup_rb(adev); 1529 gfx_v12_1_get_cu_info(adev, &adev->gfx.cu_info); 1530 gfx_v12_1_get_tcc_info(adev); 1531 adev->gfx.config.pa_sc_tile_steering_override = 0; 1532 1533 for (i = 0; i < num_xcc; i++) 1534 gfx_v12_1_xcc_constants_init(adev, i); 1535 } 1536 1537 static void gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1538 bool enable, int xcc_id) 1539 { 1540 u32 tmp; 1541 1542 if (amdgpu_sriov_vf(adev)) 1543 return; 1544 1545 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1546 1547 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1548 enable ? 1 : 0); 1549 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1550 enable ? 1 : 0); 1551 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1552 enable ? 1 : 0); 1553 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1554 enable ? 1 : 0); 1555 1556 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1557 } 1558 1559 static int gfx_v12_1_xcc_init_csb(struct amdgpu_device *adev, 1560 int xcc_id) 1561 { 1562 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1563 1564 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI, 1565 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1566 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO, 1567 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1568 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1569 regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1570 1571 return 0; 1572 } 1573 1574 static void gfx_v12_1_xcc_rlc_stop(struct amdgpu_device *adev, 1575 int xcc_id) 1576 { 1577 u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); 1578 1579 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1580 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); 1581 } 1582 1583 static void gfx_v12_1_rlc_stop(struct amdgpu_device *adev) 1584 { 1585 int i, num_xcc; 1586 1587 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1588 for (i = 0; i < num_xcc; i++) 1589 gfx_v12_1_xcc_rlc_stop(adev, i); 1590 } 1591 1592 static void gfx_v12_1_xcc_rlc_reset(struct amdgpu_device *adev, 1593 int xcc_id) 1594 { 1595 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1596 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1597 udelay(50); 1598 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1599 GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1600 udelay(50); 1601 } 1602 1603 static void gfx_v12_1_rlc_reset(struct amdgpu_device *adev) 1604 { 1605 int i, num_xcc; 1606 1607 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1608 for (i = 0; i < num_xcc; i++) 1609 gfx_v12_1_xcc_rlc_reset(adev, i); 1610 } 1611 1612 static void gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1613 bool enable, int xcc_id) 1614 { 1615 uint32_t rlc_pg_cntl; 1616 1617 rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL); 1618 1619 if (!enable) { 1620 /* RLC_PG_CNTL[23] = 0 (default) 1621 * RLC will wait for handshake acks with SMU 1622 * GFXOFF will be enabled 1623 * RLC_PG_CNTL[23] = 1 1624 * RLC will not issue any message to SMU 1625 * hence no handshake between SMU & RLC 1626 * GFXOFF will be disabled 1627 */ 1628 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1629 } else 1630 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1631 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl); 1632 } 1633 1634 static void gfx_v12_1_xcc_rlc_start(struct amdgpu_device *adev, 1635 int xcc_id) 1636 { 1637 /* TODO: enable rlc & smu handshake until smu 1638 * and gfxoff feature works as expected */ 1639 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1640 gfx_v12_1_xcc_rlc_smu_handshake_cntl(adev, false, xcc_id); 1641 1642 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); 1643 udelay(50); 1644 } 1645 1646 static void gfx_v12_1_rlc_start(struct amdgpu_device *adev) 1647 { 1648 int i, num_xcc; 1649 1650 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1651 for (i = 0; i < num_xcc; i++) { 1652 gfx_v12_1_xcc_rlc_start(adev, i); 1653 } 1654 } 1655 1656 static void gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device *adev, 1657 int xcc_id) 1658 { 1659 uint32_t tmp; 1660 1661 /* enable Save Restore Machine */ 1662 tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL)); 1663 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1664 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1665 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp); 1666 } 1667 1668 static void gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device *adev, 1669 int xcc_id) 1670 { 1671 const struct rlc_firmware_header_v2_0 *hdr; 1672 const __le32 *fw_data; 1673 unsigned i, fw_size; 1674 1675 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1676 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1677 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1678 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1679 1680 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1681 RLCG_UCODE_LOADING_START_ADDRESS); 1682 1683 for (i = 0; i < fw_size; i++) 1684 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1685 regRLC_GPM_UCODE_DATA, 1686 le32_to_cpup(fw_data++)); 1687 1688 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1689 regRLC_GPM_UCODE_ADDR, 1690 adev->gfx.rlc_fw_version); 1691 } 1692 1693 static void gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device *adev, 1694 int xcc_id) 1695 { 1696 const struct rlc_firmware_header_v2_2 *hdr; 1697 const __le32 *fw_data; 1698 unsigned i, fw_size; 1699 u32 tmp; 1700 1701 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1702 1703 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1704 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1705 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1706 1707 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0); 1708 1709 for (i = 0; i < fw_size; i++) { 1710 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1711 msleep(1); 1712 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1713 regRLC_LX6_IRAM_DATA, 1714 le32_to_cpup(fw_data++)); 1715 } 1716 1717 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1718 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1719 1720 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1721 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1722 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1723 1724 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1725 regRLC_LX6_DRAM_ADDR, 0); 1726 for (i = 0; i < fw_size; i++) { 1727 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1728 msleep(1); 1729 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1730 regRLC_LX6_DRAM_DATA, 1731 le32_to_cpup(fw_data++)); 1732 } 1733 1734 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1735 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1736 1737 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL); 1738 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1739 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1740 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp); 1741 } 1742 1743 static int gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1744 int xcc_id) 1745 { 1746 const struct rlc_firmware_header_v2_0 *hdr; 1747 uint16_t version_major; 1748 uint16_t version_minor; 1749 1750 if (!adev->gfx.rlc_fw) 1751 return -EINVAL; 1752 1753 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1754 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1755 1756 version_major = le16_to_cpu(hdr->header.header_version_major); 1757 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1758 1759 if (version_major == 2) { 1760 gfx_v12_1_xcc_load_rlcg_microcode(adev, xcc_id); 1761 if (amdgpu_dpm == 1) { 1762 if (version_minor >= 2) 1763 gfx_v12_1_xcc_load_rlc_iram_dram_microcode(adev, xcc_id); 1764 } 1765 1766 return 0; 1767 } 1768 1769 return -EINVAL; 1770 } 1771 1772 static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, 1773 int xcc_id) 1774 { 1775 int r; 1776 1777 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1778 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1779 1780 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1781 gfx_v12_1_xcc_rlc_enable_srm(adev, xcc_id); 1782 } else { 1783 if (amdgpu_sriov_vf(adev)) { 1784 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1785 return 0; 1786 } 1787 1788 gfx_v12_1_xcc_rlc_stop(adev, xcc_id); 1789 1790 /* disable CG */ 1791 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1792 1793 /* disable PG */ 1794 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0); 1795 1796 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1797 /* legacy rlc firmware loading */ 1798 r = gfx_v12_1_xcc_rlc_load_microcode(adev, xcc_id); 1799 if (r) 1800 return r; 1801 } 1802 1803 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1804 1805 gfx_v12_1_xcc_rlc_start(adev, xcc_id); 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int gfx_v12_1_rlc_resume(struct amdgpu_device *adev) 1812 { 1813 int r, i, num_xcc; 1814 1815 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1816 for (i = 0; i < num_xcc; i++) { 1817 r = gfx_v12_1_xcc_rlc_resume(adev, i); 1818 if (r) 1819 return r; 1820 } 1821 1822 return 0; 1823 } 1824 1825 static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, 1826 int xcc_id) 1827 { 1828 const struct gfx_firmware_header_v2_0 *mec_hdr; 1829 uint32_t pipe_id, tmp; 1830 1831 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1832 adev->gfx.mec_fw->data; 1833 1834 /* config mec program start addr */ 1835 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 1836 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1837 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1838 mec_hdr->ucode_start_addr_lo >> 2 | 1839 mec_hdr->ucode_start_addr_hi << 30); 1840 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1841 mec_hdr->ucode_start_addr_hi >> 2); 1842 } 1843 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1844 1845 /* reset mec pipe */ 1846 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 1847 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 1848 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 1849 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 1850 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 1851 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1852 1853 /* clear mec pipe reset */ 1854 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 1855 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 1856 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 1857 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 1858 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1859 } 1860 1861 static void gfx_v12_1_config_gfx_rs64(struct amdgpu_device *adev) 1862 { 1863 int i, num_xcc; 1864 1865 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1866 1867 for (i = 0; i < num_xcc; i++) 1868 gfx_v12_1_xcc_config_gfx_rs64(adev, i); 1869 } 1870 1871 static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, 1872 int xcc_id) 1873 { 1874 const struct gfx_firmware_header_v2_0 *cp_hdr; 1875 unsigned pipe_id; 1876 1877 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1878 adev->gfx.mec_fw->data; 1879 mutex_lock(&adev->srbm_mutex); 1880 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 1881 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1882 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1883 cp_hdr->ucode_start_addr_lo >> 2 | 1884 cp_hdr->ucode_start_addr_hi << 30); 1885 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1886 cp_hdr->ucode_start_addr_hi >> 2); 1887 } 1888 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1889 mutex_unlock(&adev->srbm_mutex); 1890 } 1891 1892 static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev, 1893 int xcc_id) 1894 { 1895 uint32_t cp_status; 1896 uint32_t bootload_status; 1897 int i; 1898 1899 for (i = 0; i < adev->usec_timeout; i++) { 1900 cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT); 1901 bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1902 regRLC_RLCS_BOOTLOAD_STATUS); 1903 1904 if ((cp_status == 0) && 1905 (REG_GET_FIELD(bootload_status, 1906 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 1907 break; 1908 } 1909 udelay(1); 1910 if (amdgpu_emu_mode) 1911 msleep(10); 1912 } 1913 1914 if (i >= adev->usec_timeout) { 1915 dev_err(adev->dev, 1916 "rlc autoload: xcc%d gc ucode autoload timeout\n", xcc_id); 1917 return -ETIMEDOUT; 1918 } 1919 1920 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1921 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 1928 { 1929 int xcc_id; 1930 1931 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) 1932 gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id); 1933 1934 return 0; 1935 } 1936 1937 static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, 1938 bool enable, int xcc_id) 1939 { 1940 u32 data; 1941 1942 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 1943 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 1944 enable ? 0 : 1); 1945 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1946 enable ? 0 : 1); 1947 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1948 enable ? 0 : 1); 1949 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1950 enable ? 0 : 1); 1951 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1952 enable ? 0 : 1); 1953 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 1954 enable ? 1 : 0); 1955 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 1956 enable ? 1 : 0); 1957 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 1958 enable ? 1 : 0); 1959 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 1960 enable ? 1 : 0); 1961 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 1962 enable ? 0 : 1); 1963 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); 1964 1965 adev->gfx.kiq[xcc_id].ring.sched.ready = enable; 1966 1967 udelay(50); 1968 } 1969 1970 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev) 1971 { 1972 const struct gfx_firmware_header_v2_0 *mec_hdr; 1973 const __le32 *fw_ucode, *fw_data; 1974 u32 fw_ucode_size, fw_data_size; 1975 u32 *fw_ucode_ptr, *fw_data_ptr; 1976 int i, r, xcc_id; 1977 1978 if (!adev->gfx.mec_fw) 1979 return -EINVAL; 1980 1981 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 1982 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1983 1984 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 1985 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 1986 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 1987 1988 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1989 le32_to_cpu(mec_hdr->data_offset_bytes)); 1990 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 1991 1992 if (adev->gfx.mec.mec_fw_obj == NULL) { 1993 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 1994 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 1995 &adev->gfx.mec.mec_fw_obj, 1996 &adev->gfx.mec.mec_fw_gpu_addr, 1997 (void **)&fw_ucode_ptr); 1998 if (r) { 1999 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2000 gfx_v12_1_mec_fini(adev); 2001 return r; 2002 } 2003 2004 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2005 2006 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2007 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2008 } 2009 2010 if (adev->gfx.mec.mec_fw_data_obj == NULL) { 2011 r = amdgpu_bo_create_reserved(adev, 2012 ALIGN(fw_data_size, 64 * 1024) * 2013 adev->gfx.mec.num_pipe_per_mec * NUM_XCC(adev->gfx.xcc_mask), 2014 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2015 &adev->gfx.mec.mec_fw_data_obj, 2016 &adev->gfx.mec.mec_fw_data_gpu_addr, 2017 (void **)&fw_data_ptr); 2018 if (r) { 2019 dev_err(adev->dev, "(%d) failed to create mec fw data bo\n", r); 2020 gfx_v12_1_mec_fini(adev); 2021 return r; 2022 } 2023 2024 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 2025 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2026 u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2027 ALIGN(fw_data_size, 64 * 1024) / 4; 2028 memcpy(fw_data_ptr + offset, fw_data, fw_data_size); 2029 } 2030 } 2031 2032 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2033 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, 2040 int xcc_id) 2041 { 2042 const struct gfx_firmware_header_v2_0 *mec_hdr; 2043 u32 fw_data_size; 2044 u32 tmp, i, usec_timeout = 50000; /* Wait for 50 ms */ 2045 2046 if (!adev->gfx.mec_fw) 2047 return -EINVAL; 2048 2049 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2050 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2051 2052 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2053 2054 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); 2055 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2056 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2057 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2058 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 2059 2060 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); 2061 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2062 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2063 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); 2064 2065 mutex_lock(&adev->srbm_mutex); 2066 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2067 soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); 2068 2069 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, 2070 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2071 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2072 ALIGN(fw_data_size, 64 * 1024))); 2073 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, 2074 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2075 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2076 ALIGN(fw_data_size, 64 * 1024))); 2077 2078 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 2079 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2080 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 2081 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2082 } 2083 mutex_unlock(&adev->srbm_mutex); 2084 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2085 2086 /* Trigger an invalidation of the L1 instruction caches */ 2087 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2088 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2089 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); 2090 2091 /* Wait for invalidation complete */ 2092 for (i = 0; i < usec_timeout; i++) { 2093 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2094 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2095 INVALIDATE_DCACHE_COMPLETE)) 2096 break; 2097 udelay(1); 2098 } 2099 2100 if (i >= usec_timeout) { 2101 dev_err(adev->dev, "failed to invalidate data cache\n"); 2102 return -EINVAL; 2103 } 2104 2105 /* Trigger an invalidation of the L1 instruction caches */ 2106 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2107 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2108 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); 2109 2110 /* Wait for invalidation complete */ 2111 for (i = 0; i < usec_timeout; i++) { 2112 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2113 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2114 INVALIDATE_CACHE_COMPLETE)) 2115 break; 2116 udelay(1); 2117 } 2118 2119 if (i >= usec_timeout) { 2120 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2121 return -EINVAL; 2122 } 2123 2124 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2125 2126 return 0; 2127 } 2128 2129 static void gfx_v12_1_xcc_kiq_setting(struct amdgpu_ring *ring, 2130 int xcc_id) 2131 { 2132 uint32_t tmp; 2133 struct amdgpu_device *adev = ring->adev; 2134 2135 /* tell RLC which is KIQ queue */ 2136 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2137 tmp &= 0xffffff00; 2138 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2139 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2140 tmp |= 0x80; 2141 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2142 } 2143 2144 static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev, 2145 int xcc_id) 2146 { 2147 /* disable gfx engine doorbell range */ 2148 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0); 2149 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0); 2150 2151 /* set compute engine doorbell range */ 2152 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER, 2153 ((adev->doorbell_index.kiq + 2154 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2155 2) << 2); 2156 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER, 2157 ((adev->doorbell_index.userqueue_end + 2158 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2159 2) << 2); 2160 } 2161 2162 static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, 2163 struct amdgpu_mqd_prop *prop) 2164 { 2165 struct v12_1_compute_mqd *mqd = m; 2166 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2167 uint32_t tmp; 2168 2169 mqd->header = 0xC0310800; 2170 mqd->compute_pipelinestat_enable = 0x00000001; 2171 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2172 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2173 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2174 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2175 mqd->compute_misc_reserved = 0x00000007; 2176 2177 eop_base_addr = prop->eop_gpu_addr >> 8; 2178 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2179 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2180 2181 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2182 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 2183 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2184 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 2185 2186 mqd->cp_hqd_eop_control = tmp; 2187 2188 /* enable doorbell? */ 2189 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2190 2191 if (prop->use_doorbell) { 2192 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2193 DOORBELL_OFFSET, prop->doorbell_index); 2194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2195 DOORBELL_EN, 1); 2196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2197 DOORBELL_SOURCE, 0); 2198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2199 DOORBELL_HIT, 0); 2200 } else { 2201 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2202 DOORBELL_EN, 0); 2203 } 2204 2205 mqd->cp_hqd_pq_doorbell_control = tmp; 2206 2207 /* disable the queue if it's active */ 2208 mqd->cp_hqd_dequeue_request = 0; 2209 mqd->cp_hqd_pq_rptr = 0; 2210 mqd->cp_hqd_pq_wptr_lo = 0; 2211 mqd->cp_hqd_pq_wptr_hi = 0; 2212 2213 /* set the pointer to the MQD */ 2214 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 2215 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2216 2217 /* set MQD vmid to 0 */ 2218 tmp = regCP_MQD_CONTROL_DEFAULT; 2219 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2220 mqd->cp_mqd_control = tmp; 2221 2222 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2223 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2224 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2225 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2226 2227 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2228 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 2229 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2230 (order_base_2(prop->queue_size / 4) - 1)); 2231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2232 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 2233 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2234 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 2235 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2236 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2237 mqd->cp_hqd_pq_control = tmp; 2238 2239 /* set the wb address whether it's enabled or not */ 2240 wb_gpu_addr = prop->rptr_gpu_addr; 2241 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2242 mqd->cp_hqd_pq_rptr_report_addr_hi = 2243 upper_32_bits(wb_gpu_addr) & 0xffff; 2244 2245 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2246 wb_gpu_addr = prop->wptr_gpu_addr; 2247 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2248 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2249 2250 tmp = 0; 2251 /* enable the doorbell if requested */ 2252 if (prop->use_doorbell) { 2253 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2254 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2255 DOORBELL_OFFSET, prop->doorbell_index); 2256 2257 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2258 DOORBELL_EN, 1); 2259 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2260 DOORBELL_SOURCE, 0); 2261 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2262 DOORBELL_HIT, 0); 2263 } 2264 2265 mqd->cp_hqd_pq_doorbell_control = tmp; 2266 2267 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2268 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 2269 2270 /* set the vmid for the queue */ 2271 mqd->cp_hqd_vmid = 0; 2272 2273 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 2274 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63); 2275 mqd->cp_hqd_persistent_state = tmp; 2276 2277 /* set MIN_IB_AVAIL_SIZE */ 2278 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 2279 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1); 2280 mqd->cp_hqd_ib_control = tmp; 2281 2282 /* set static priority for a compute queue/ring */ 2283 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 2284 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2285 2286 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : 2287 AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); 2288 2289 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 2290 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 2291 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 2292 mqd->cp_hqd_quantum = tmp; 2293 2294 mqd->cp_hqd_active = prop->hqd_active; 2295 2296 return 0; 2297 } 2298 2299 static int gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring *ring, 2300 int xcc_id) 2301 { 2302 struct amdgpu_device *adev = ring->adev; 2303 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2304 int j; 2305 2306 /* inactivate the queue */ 2307 if (amdgpu_sriov_vf(adev)) 2308 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2309 2310 /* disable wptr polling */ 2311 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2312 2313 /* write the EOP addr */ 2314 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 2315 mqd->cp_hqd_eop_base_addr_lo); 2316 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 2317 mqd->cp_hqd_eop_base_addr_hi); 2318 2319 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2320 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 2321 mqd->cp_hqd_eop_control); 2322 2323 /* enable doorbell? */ 2324 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2325 mqd->cp_hqd_pq_doorbell_control); 2326 2327 /* disable the queue if it's active */ 2328 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2329 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2330 for (j = 0; j < adev->usec_timeout; j++) { 2331 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2332 break; 2333 udelay(1); 2334 } 2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2336 mqd->cp_hqd_dequeue_request); 2337 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 2338 mqd->cp_hqd_pq_rptr); 2339 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2340 mqd->cp_hqd_pq_wptr_lo); 2341 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2342 mqd->cp_hqd_pq_wptr_hi); 2343 } 2344 2345 /* set the pointer to the MQD */ 2346 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2347 mqd->cp_mqd_base_addr_lo); 2348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2349 mqd->cp_mqd_base_addr_hi); 2350 2351 /* set MQD vmid to 0 */ 2352 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2353 mqd->cp_mqd_control); 2354 2355 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2356 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2357 mqd->cp_hqd_pq_base_lo); 2358 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2359 mqd->cp_hqd_pq_base_hi); 2360 2361 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2362 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2363 mqd->cp_hqd_pq_control); 2364 2365 /* set the wb address whether it's enabled or not */ 2366 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2367 mqd->cp_hqd_pq_rptr_report_addr_lo); 2368 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2369 mqd->cp_hqd_pq_rptr_report_addr_hi); 2370 2371 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2372 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2373 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2374 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2375 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2376 2377 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2378 mqd->cp_hqd_pq_doorbell_control); 2379 2380 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2381 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2382 mqd->cp_hqd_pq_wptr_lo); 2383 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2384 mqd->cp_hqd_pq_wptr_hi); 2385 2386 /* set the vmid for the queue */ 2387 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2388 2389 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2390 mqd->cp_hqd_persistent_state); 2391 2392 /* activate the queue */ 2393 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2394 mqd->cp_hqd_active); 2395 2396 if (ring->use_doorbell) 2397 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2398 2399 return 0; 2400 } 2401 2402 static int gfx_v12_1_xcc_kiq_init_queue(struct amdgpu_ring *ring, 2403 int xcc_id) 2404 { 2405 struct amdgpu_device *adev = ring->adev; 2406 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2407 2408 gfx_v12_1_xcc_kiq_setting(ring, xcc_id); 2409 2410 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 2411 /* reset MQD to a clean status */ 2412 if (adev->gfx.kiq[xcc_id].mqd_backup) 2413 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(*mqd)); 2414 2415 /* reset ring buffer */ 2416 ring->wptr = 0; 2417 amdgpu_ring_clear_ring(ring); 2418 2419 mutex_lock(&adev->srbm_mutex); 2420 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2421 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2422 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2423 mutex_unlock(&adev->srbm_mutex); 2424 } else { 2425 memset((void *)mqd, 0, sizeof(*mqd)); 2426 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2427 amdgpu_ring_clear_ring(ring); 2428 mutex_lock(&adev->srbm_mutex); 2429 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2430 amdgpu_ring_init_mqd(ring); 2431 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2432 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2433 mutex_unlock(&adev->srbm_mutex); 2434 2435 if (adev->gfx.kiq[xcc_id].mqd_backup) 2436 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(*mqd)); 2437 } 2438 2439 return 0; 2440 } 2441 2442 static int gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring *ring, 2443 int xcc_id) 2444 { 2445 struct amdgpu_device *adev = ring->adev; 2446 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2447 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2448 2449 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2450 memset((void *)mqd, 0, sizeof(*mqd)); 2451 mutex_lock(&adev->srbm_mutex); 2452 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2453 amdgpu_ring_init_mqd(ring); 2454 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2455 mutex_unlock(&adev->srbm_mutex); 2456 2457 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2458 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2459 } else { 2460 /* restore MQD to a clean status */ 2461 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2462 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2463 /* reset ring buffer */ 2464 ring->wptr = 0; 2465 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 2466 amdgpu_ring_clear_ring(ring); 2467 } 2468 2469 return 0; 2470 } 2471 2472 static int gfx_v12_1_xcc_kiq_resume(struct amdgpu_device *adev, 2473 int xcc_id) 2474 { 2475 struct amdgpu_ring *ring; 2476 int r; 2477 2478 ring = &adev->gfx.kiq[xcc_id].ring; 2479 2480 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2481 if (unlikely(r != 0)) 2482 return r; 2483 2484 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2485 if (unlikely(r != 0)) { 2486 amdgpu_bo_unreserve(ring->mqd_obj); 2487 return r; 2488 } 2489 2490 gfx_v12_1_xcc_kiq_init_queue(ring, xcc_id); 2491 amdgpu_bo_kunmap(ring->mqd_obj); 2492 ring->mqd_ptr = NULL; 2493 amdgpu_bo_unreserve(ring->mqd_obj); 2494 ring->sched.ready = true; 2495 return 0; 2496 } 2497 2498 static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, 2499 int xcc_id) 2500 { 2501 struct amdgpu_ring *ring = NULL; 2502 int r = 0, i; 2503 2504 if (!amdgpu_async_gfx_ring) 2505 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2506 2507 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2508 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2509 2510 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2511 if (unlikely(r != 0)) 2512 goto done; 2513 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2514 if (!r) { 2515 r = gfx_v12_1_xcc_kcq_init_queue(ring, xcc_id); 2516 amdgpu_bo_kunmap(ring->mqd_obj); 2517 ring->mqd_ptr = NULL; 2518 } 2519 amdgpu_bo_unreserve(ring->mqd_obj); 2520 if (r) 2521 goto done; 2522 } 2523 2524 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2525 done: 2526 return r; 2527 } 2528 2529 static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) 2530 { 2531 int r, i, xcc_id; 2532 struct amdgpu_ring *ring; 2533 2534 for_each_inst(xcc_id, xcc_mask) { 2535 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2536 /* legacy firmware loading */ 2537 r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); 2538 if (r) 2539 return r; 2540 } 2541 2542 /* GFX CGCG and LS is set by default */ 2543 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2544 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2545 2546 gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); 2547 2548 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2549 2550 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) { 2551 r = amdgpu_mes_kiq_hw_init(adev, xcc_id); 2552 /* 2553 * With MES, GFX KIQ ring is owned by the MES and is never 2554 * initialized/used directly by the driver, so it must 2555 * not be left flagged as ready. mes_v12_0_hw_init() clears 2556 * but clear here if MES init fails 2557 */ 2558 if (r) 2559 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 2560 } else { 2561 r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); 2562 } 2563 if (r) 2564 return r; 2565 2566 r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); 2567 if (r) 2568 return r; 2569 2570 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2571 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2572 r = amdgpu_ring_test_helper(ring); 2573 if (r) 2574 return r; 2575 } 2576 } 2577 2578 return 0; 2579 } 2580 2581 static int gfx_v12_1_cp_resume(struct amdgpu_device *adev) 2582 { 2583 int num_xcc, num_xcp, num_xcc_per_xcp; 2584 uint16_t xcc_mask; 2585 int r = 0; 2586 2587 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2588 if (amdgpu_sriov_vf(adev)) { 2589 enum amdgpu_gfx_partition mode; 2590 2591 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2592 AMDGPU_XCP_FL_NONE); 2593 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2594 return -EINVAL; 2595 if (adev->gfx.funcs && 2596 adev->gfx.funcs->get_xccs_per_xcp) { 2597 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 2598 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2599 num_xcp = num_xcc / num_xcc_per_xcp; 2600 } else { 2601 return -EINVAL; 2602 } 2603 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2604 2605 } else { 2606 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2607 AMDGPU_XCP_FL_NONE) == 2608 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2609 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2610 amdgpu_user_partt_mode); 2611 } 2612 2613 if (r) 2614 return r; 2615 2616 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 2617 2618 return gfx_v12_1_xcc_cp_resume(adev, xcc_mask); 2619 } 2620 2621 static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev) 2622 { 2623 int r, i; 2624 bool value; 2625 2626 r = adev->gfxhub.funcs->gart_enable(adev); 2627 if (r) 2628 return r; 2629 2630 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 2631 false : true; 2632 2633 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2634 /* TODO investigate why TLB flush is needed, 2635 * are we missing a flush somewhere else? */ 2636 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2637 if (AMDGPU_IS_GFXHUB(i)) 2638 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0); 2639 } 2640 2641 return 0; 2642 } 2643 2644 static int get_gb_addr_config(struct amdgpu_device *adev) 2645 { 2646 u32 gb_addr_config; 2647 2648 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ); 2649 if (gb_addr_config == 0) 2650 return -EINVAL; 2651 2652 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2653 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG_READ, NUM_PKRS); 2654 2655 adev->gfx.config.gb_addr_config = gb_addr_config; 2656 2657 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2658 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2659 GB_ADDR_CONFIG_READ, NUM_PIPES); 2660 2661 adev->gfx.config.max_tile_pipes = 2662 adev->gfx.config.gb_addr_config_fields.num_pipes; 2663 2664 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2665 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2666 GB_ADDR_CONFIG_READ, MAX_COMPRESSED_FRAGS); 2667 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2668 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2669 GB_ADDR_CONFIG_READ, NUM_RB_PER_SE); 2670 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2671 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2672 GB_ADDR_CONFIG_READ, NUM_SHADER_ENGINES); 2673 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2674 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2675 GB_ADDR_CONFIG_READ, PIPE_INTERLEAVE_SIZE)); 2676 2677 return 0; 2678 } 2679 2680 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, 2681 int xcc_id) 2682 { 2683 uint32_t data; 2684 2685 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 2686 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 2687 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 2688 2689 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG); 2690 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 2691 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); 2692 } 2693 2694 static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, 2695 int xcc_id) 2696 { 2697 uint32_t data; 2698 2699 /* Set the TCP UTCL0 register to enable atomics */ 2700 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); 2701 data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); 2702 2703 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); 2704 } 2705 2706 static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, 2707 int xcc_id) 2708 { 2709 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); 2710 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); 2711 } 2712 2713 static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, 2714 int xcc_id) 2715 { 2716 uint32_t data; 2717 2718 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3); 2719 data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1); 2720 2721 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); 2722 } 2723 2724 static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, 2725 int xcc_id) 2726 { 2727 uint32_t data; 2728 2729 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); 2730 data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); 2731 2732 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); 2733 } 2734 2735 static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) 2736 { 2737 int i; 2738 2739 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { 2740 gfx_v12_1_xcc_disable_burst(adev, i); 2741 gfx_v12_1_xcc_enable_atomics(adev, i); 2742 gfx_v12_1_xcc_disable_early_write_ack(adev, i); 2743 gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); 2744 } 2745 } 2746 2747 static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, 2748 bool enable) 2749 { 2750 unsigned int irq_type; 2751 int m, p, r; 2752 2753 if (!adev->gfx.disable_kq) 2754 return 0; 2755 2756 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 2757 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 2758 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2759 + (m * adev->gfx.mec.num_pipe_per_mec) 2760 + p; 2761 if (enable) 2762 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 2763 else 2764 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2765 if (r) { 2766 if (!enable) 2767 return r; 2768 goto err_unwind; 2769 } 2770 } 2771 } 2772 2773 return 0; 2774 2775 err_unwind: 2776 for (p--; p >= 0; p--) { 2777 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2778 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2779 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2780 } 2781 for (m--; m >= 0; m--) { 2782 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2783 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2784 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2785 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2786 } 2787 } 2788 return r; 2789 } 2790 2791 static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 2792 { 2793 int r, i, num_xcc; 2794 struct amdgpu_device *adev = ip_block->adev; 2795 2796 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2797 /* rlc autoload firmware */ 2798 r = gfx_v12_1_rlc_backdoor_autoload_enable(adev); 2799 if (r) 2800 return r; 2801 } else { 2802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2803 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2804 2805 if (adev->gfx.imu.funcs) { 2806 if (adev->gfx.imu.funcs->load_microcode) 2807 adev->gfx.imu.funcs->load_microcode(adev); 2808 } 2809 2810 for (i = 0; i < num_xcc; i++) { 2811 /* disable gpa mode in backdoor loading */ 2812 gfx_v12_1_xcc_disable_gpa_mode(adev, i); 2813 } 2814 } 2815 } 2816 2817 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 2818 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2819 r = gfx_v12_1_wait_for_rlc_autoload_complete(adev); 2820 if (r) { 2821 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 2822 return r; 2823 } 2824 } 2825 2826 adev->gfx.is_poweron = true; 2827 2828 if (get_gb_addr_config(adev)) 2829 DRM_WARN("Invalid gb_addr_config !\n"); 2830 2831 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2832 gfx_v12_1_config_gfx_rs64(adev); 2833 2834 r = gfx_v12_1_gfxhub_enable(adev); 2835 if (r) 2836 return r; 2837 2838 gfx_v12_1_init_golden_registers(adev); 2839 2840 gfx_v12_1_constants_init(adev); 2841 2842 if (adev->nbio.funcs->gc_doorbell_init) 2843 adev->nbio.funcs->gc_doorbell_init(adev); 2844 2845 r = gfx_v12_1_rlc_resume(adev); 2846 if (r) 2847 return r; 2848 2849 /* 2850 * init golden registers and rlc resume may override some registers, 2851 * reconfig them here 2852 */ 2853 gfx_v12_1_tcp_harvest(adev); 2854 2855 r = gfx_v12_1_cp_resume(adev); 2856 if (r) 2857 return r; 2858 2859 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2860 if (r) 2861 return r; 2862 2863 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2864 if (r) 2865 goto err_priv_inst; 2866 2867 r = gfx_v12_1_set_userq_eop_interrupts(adev, true); 2868 if (r) 2869 goto err_userq_eop; 2870 2871 return 0; 2872 2873 err_userq_eop: 2874 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2875 err_priv_inst: 2876 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2877 return r; 2878 } 2879 2880 static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, 2881 int xcc_id) 2882 { 2883 uint32_t tmp; 2884 2885 if (!adev->no_hw_access) { 2886 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2887 DRM_ERROR("KCQ disable failed\n"); 2888 2889 amdgpu_mes_kiq_hw_fini(adev, xcc_id); 2890 } 2891 2892 if (amdgpu_sriov_vf(adev)) { 2893 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 2894 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2895 tmp &= 0xffffff00; 2896 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2897 } 2898 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2899 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2900 } 2901 2902 static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 2903 { 2904 struct amdgpu_device *adev = ip_block->adev; 2905 int i, num_xcc; 2906 2907 gfx_v12_1_set_userq_eop_interrupts(adev, false); 2908 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2909 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2910 2911 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2912 for (i = 0; i < num_xcc; i++) { 2913 gfx_v12_1_xcc_fini(adev, i); 2914 } 2915 2916 adev->gfxhub.funcs->gart_disable(adev); 2917 2918 adev->gfx.is_poweron = false; 2919 2920 return 0; 2921 } 2922 2923 static int gfx_v12_1_suspend(struct amdgpu_ip_block *ip_block) 2924 { 2925 return gfx_v12_1_hw_fini(ip_block); 2926 } 2927 2928 static int gfx_v12_1_resume(struct amdgpu_ip_block *ip_block) 2929 { 2930 return gfx_v12_1_hw_init(ip_block); 2931 } 2932 2933 static bool gfx_v12_1_is_idle(struct amdgpu_ip_block *ip_block) 2934 { 2935 struct amdgpu_device *adev = ip_block->adev; 2936 int i, num_xcc; 2937 2938 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2939 for (i = 0; i < num_xcc; i++) { 2940 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), 2941 regGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 2942 return false; 2943 } 2944 return true; 2945 } 2946 2947 static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 2948 { 2949 unsigned i; 2950 struct amdgpu_device *adev = ip_block->adev; 2951 2952 for (i = 0; i < adev->usec_timeout; i++) { 2953 if (gfx_v12_1_is_idle(ip_block)) 2954 return 0; 2955 udelay(1); 2956 } 2957 return -ETIMEDOUT; 2958 } 2959 2960 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) 2961 { 2962 uint64_t clock = 0; 2963 2964 if (adev->smuio.funcs && 2965 adev->smuio.funcs->get_gpu_clock_counter) 2966 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 2967 else 2968 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 2969 2970 return clock; 2971 } 2972 2973 static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) 2974 { 2975 struct amdgpu_device *adev = ip_block->adev; 2976 2977 2978 switch (amdgpu_user_queue) { 2979 case -1: 2980 default: 2981 adev->gfx.disable_kq = true; 2982 adev->gfx.disable_uq = true; 2983 break; 2984 case 0: 2985 adev->gfx.disable_kq = false; 2986 adev->gfx.disable_uq = true; 2987 break; 2988 } 2989 2990 adev->gfx.funcs = &gfx_v12_1_gfx_funcs; 2991 2992 if (adev->gfx.disable_kq) 2993 adev->gfx.num_compute_rings = 0; 2994 else 2995 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2996 AMDGPU_MAX_COMPUTE_RINGS); 2997 2998 gfx_v12_1_set_kiq_pm4_funcs(adev); 2999 gfx_v12_1_set_ring_funcs(adev); 3000 gfx_v12_1_set_irq_funcs(adev); 3001 gfx_v12_1_set_rlc_funcs(adev); 3002 gfx_v12_1_set_mqd_funcs(adev); 3003 gfx_v12_1_set_imu_funcs(adev); 3004 3005 gfx_v12_1_init_rlcg_reg_access_ctrl(adev); 3006 3007 return gfx_v12_1_init_microcode(adev); 3008 } 3009 3010 static bool gfx_v12_1_is_rlc_enabled(struct amdgpu_device *adev) 3011 { 3012 uint32_t rlc_cntl; 3013 3014 /* if RLC is not enabled, do nothing */ 3015 rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 3016 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3017 } 3018 3019 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, 3020 int xcc_id) 3021 { 3022 uint32_t data; 3023 unsigned i; 3024 3025 data = RLC_SAFE_MODE__CMD_MASK; 3026 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3027 3028 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 3029 3030 /* wait for RLC_SAFE_MODE */ 3031 for (i = 0; i < adev->usec_timeout; i++) { 3032 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3033 regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3034 break; 3035 udelay(1); 3036 } 3037 } 3038 3039 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, 3040 int xcc_id) 3041 { 3042 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3043 regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3044 } 3045 3046 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 3047 bool enable) 3048 { 3049 int i, num_xcc; 3050 3051 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3052 for (i = 0; i < num_xcc; i++) 3053 gfx_v12_1_xcc_update_perf_clk(adev, enable, i); 3054 } 3055 3056 static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, 3057 int xcc_id, 3058 struct amdgpu_ring *ring, 3059 unsigned vmid) 3060 { 3061 u32 reg, data; 3062 3063 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3064 if (amdgpu_sriov_is_pp_one_vf(adev)) 3065 data = RREG32_NO_KIQ(reg); 3066 else 3067 data = RREG32(reg); 3068 3069 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3070 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3071 3072 if (amdgpu_sriov_is_pp_one_vf(adev)) 3073 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3074 else 3075 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3076 3077 if (ring 3078 && amdgpu_sriov_is_pp_one_vf(adev) 3079 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3080 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3081 uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3082 amdgpu_ring_emit_wreg(ring, reg, data); 3083 } 3084 } 3085 3086 static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = { 3087 .is_rlc_enabled = gfx_v12_1_is_rlc_enabled, 3088 .set_safe_mode = gfx_v12_1_xcc_set_safe_mode, 3089 .unset_safe_mode = gfx_v12_1_xcc_unset_safe_mode, 3090 .init = gfx_v12_1_rlc_init, 3091 .get_csb_size = gfx_v12_1_get_csb_size, 3092 .get_csb_buffer = gfx_v12_1_get_csb_buffer, 3093 .resume = gfx_v12_1_rlc_resume, 3094 .stop = gfx_v12_1_rlc_stop, 3095 .reset = gfx_v12_1_rlc_reset, 3096 .start = gfx_v12_1_rlc_start, 3097 .update_spm_vmid = gfx_v12_1_update_spm_vmid, 3098 }; 3099 3100 #if 0 3101 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3102 { 3103 /* TODO */ 3104 } 3105 3106 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3107 { 3108 /* TODO */ 3109 } 3110 #endif 3111 3112 static int gfx_v12_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 3113 enum amd_powergating_state state) 3114 { 3115 struct amdgpu_device *adev = ip_block->adev; 3116 bool enable = (state == AMD_PG_STATE_GATE); 3117 3118 if (amdgpu_sriov_vf(adev)) 3119 return 0; 3120 3121 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3122 case IP_VERSION(12, 1, 0): 3123 amdgpu_gfx_off_ctrl(adev, enable); 3124 break; 3125 default: 3126 break; 3127 } 3128 3129 return 0; 3130 } 3131 3132 static void gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3133 bool enable, int xcc_id) 3134 { 3135 uint32_t def, data; 3136 3137 if (!(adev->cg_flags & 3138 (AMD_CG_SUPPORT_GFX_CGCG | 3139 AMD_CG_SUPPORT_GFX_CGLS | 3140 AMD_CG_SUPPORT_GFX_3D_CGCG | 3141 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3142 return; 3143 3144 if (enable) { 3145 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3146 regRLC_CGTT_MGCG_OVERRIDE); 3147 3148 /* unset CGCG override */ 3149 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3150 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3151 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3152 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3153 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3154 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3155 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3156 3157 /* update CGCG override bits */ 3158 if (def != data) 3159 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3160 regRLC_CGTT_MGCG_OVERRIDE, data); 3161 3162 /* enable cgcg FSM(0x0000363F) */ 3163 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3164 3165 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3166 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3167 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3168 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3169 } 3170 3171 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3172 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3173 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3174 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3175 } 3176 3177 if (def != data) 3178 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3179 regRLC_CGCG_CGLS_CTRL, data); 3180 3181 /* set IDLE_POLL_COUNT(0x00900100) */ 3182 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 3183 3184 data &= ~CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK; 3185 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3186 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3187 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3188 3189 if (def != data) 3190 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 3191 3192 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL); 3193 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3194 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3195 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3196 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3197 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data); 3198 } else { 3199 /* Program RLC_CGCG_CGLS_CTRL */ 3200 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3201 3202 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3203 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3204 3205 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3206 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3207 3208 if (def != data) 3209 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 3210 } 3211 } 3212 3213 static void gfx_v12_1_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3214 bool enable, int xcc_id) 3215 { 3216 uint32_t data, def; 3217 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 3218 return; 3219 3220 /* It is disabled by HW by default */ 3221 if (enable) { 3222 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3223 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3224 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3225 3226 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3227 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3228 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3229 3230 if (def != data) 3231 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3232 } 3233 } else { 3234 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3235 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3236 3237 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3238 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3239 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3240 3241 if (def != data) 3242 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3243 } 3244 } 3245 } 3246 3247 static void gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 3248 bool enable, int xcc_id) 3249 { 3250 uint32_t def, data; 3251 3252 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 3253 return; 3254 3255 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3256 3257 if (enable) 3258 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3259 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 3260 else 3261 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3262 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 3263 3264 if (def != data) 3265 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3266 } 3267 3268 static void gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device *adev, 3269 bool enable, int xcc_id) 3270 { 3271 uint32_t def, data; 3272 3273 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 3274 return; 3275 3276 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3277 3278 if (enable) 3279 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3280 else 3281 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3282 3283 if (def != data) 3284 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3285 } 3286 3287 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 3288 bool enable, int xcc_id) 3289 { 3290 uint32_t def, data; 3291 3292 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3293 return; 3294 3295 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3296 3297 if (enable) 3298 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3299 else 3300 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3301 3302 if (def != data) 3303 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3304 } 3305 3306 static int gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 3307 bool enable, int xcc_id) 3308 { 3309 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3310 3311 gfx_v12_1_xcc_update_coarse_grain_clock_gating(adev, enable, xcc_id); 3312 3313 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, enable, xcc_id); 3314 3315 gfx_v12_1_xcc_update_repeater_fgcg(adev, enable, xcc_id); 3316 3317 gfx_v12_1_xcc_update_sram_fgcg(adev, enable, xcc_id); 3318 3319 gfx_v12_1_xcc_update_perf_clk(adev, enable, xcc_id); 3320 3321 if (adev->cg_flags & 3322 (AMD_CG_SUPPORT_GFX_MGCG | 3323 AMD_CG_SUPPORT_GFX_CGLS | 3324 AMD_CG_SUPPORT_GFX_CGCG | 3325 AMD_CG_SUPPORT_GFX_3D_CGCG | 3326 AMD_CG_SUPPORT_GFX_3D_CGLS)) 3327 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, enable, xcc_id); 3328 3329 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 3330 3331 return 0; 3332 } 3333 3334 static int gfx_v12_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3335 enum amd_clockgating_state state) 3336 { 3337 struct amdgpu_device *adev = ip_block->adev; 3338 int i, num_xcc; 3339 3340 if (amdgpu_sriov_vf(adev)) 3341 return 0; 3342 3343 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3344 switch (adev->ip_versions[GC_HWIP][0]) { 3345 case IP_VERSION(12, 1, 0): 3346 for (i = 0; i < num_xcc; i++) 3347 gfx_v12_1_xcc_update_gfx_clock_gating(adev, 3348 state == AMD_CG_STATE_GATE, i); 3349 break; 3350 default: 3351 break; 3352 } 3353 3354 return 0; 3355 } 3356 3357 static void gfx_v12_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 3358 { 3359 struct amdgpu_device *adev = ip_block->adev; 3360 int data; 3361 3362 /* AMD_CG_SUPPORT_GFX_MGCG */ 3363 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE); 3364 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3365 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3366 3367 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 3368 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 3369 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 3370 3371 /* AMD_CG_SUPPORT_GFX_FGCG */ 3372 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 3373 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 3374 3375 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 3376 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 3377 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 3378 3379 /* AMD_CG_SUPPORT_GFX_CGCG */ 3380 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); 3381 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3382 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3383 3384 /* AMD_CG_SUPPORT_GFX_CGLS */ 3385 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3386 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3387 } 3388 3389 static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring) 3390 { 3391 /* gfx12 hardware is 32bit rptr */ 3392 return *(uint32_t *)ring->rptr_cpu_addr; 3393 } 3394 3395 static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring) 3396 { 3397 u64 wptr; 3398 3399 /* XXX check if swapping is necessary on BE */ 3400 if (ring->use_doorbell) 3401 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3402 else 3403 BUG(); 3404 return wptr; 3405 } 3406 3407 static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring) 3408 { 3409 struct amdgpu_device *adev = ring->adev; 3410 3411 /* XXX check if swapping is necessary on BE */ 3412 if (ring->use_doorbell) { 3413 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 3414 ring->wptr); 3415 WDOORBELL64(ring->doorbell_index, ring->wptr); 3416 } else { 3417 BUG(); /* only DOORBELL method supported on gfx12 now */ 3418 } 3419 } 3420 3421 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, 3422 struct amdgpu_job *job, 3423 struct amdgpu_ib *ib, 3424 uint32_t flags) 3425 { 3426 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3427 u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); 3428 3429 /* Currently, there is a high possibility to get wave ID mismatch 3430 * between ME and GDS, leading to a hw deadlock, because ME generates 3431 * different wave IDs than the GDS expects. This situation happens 3432 * randomly when at least 5 compute pipes use GDS ordered append. 3433 * The wave IDs generated by ME are also wrong after suspend/resume. 3434 * Those are probably bugs somewhere else in the kernel driver. 3435 * 3436 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 3437 * GDS to 0 for this ring (me/pipe). 3438 */ 3439 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 3440 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3441 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 3442 } 3443 3444 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3445 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 3446 amdgpu_ring_write(ring, 3447 #ifdef __BIG_ENDIAN 3448 (2 << 0) | 3449 #endif 3450 lower_32_bits(ib->gpu_addr)); 3451 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3452 amdgpu_ring_write(ring, control); 3453 } 3454 3455 static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3456 u64 seq, unsigned flags) 3457 { 3458 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3459 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3460 3461 /* RELEASE_MEM - flush caches, send int */ 3462 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3463 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | 3464 PACKET3_RELEASE_MEM__GCR_GLV_WB | 3465 PACKET3_RELEASE_MEM__GCR_GL2_WB | 3466 PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | 3467 PACKET3_RELEASE_MEM__TEMPORAL(3) | 3468 PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3469 PACKET3_RELEASE_MEM__EVENT_INDEX(5))); 3470 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | 3471 PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); 3472 3473 /* 3474 * the address should be Qword aligned if 64bit write, Dword 3475 * aligned if only send 32bit data low (discard data high) 3476 */ 3477 if (write64bit) 3478 WARN_ON(addr & 0x7); 3479 else 3480 WARN_ON(addr & 0x3); 3481 amdgpu_ring_write(ring, lower_32_bits(addr)); 3482 amdgpu_ring_write(ring, upper_32_bits(addr)); 3483 amdgpu_ring_write(ring, lower_32_bits(seq)); 3484 amdgpu_ring_write(ring, upper_32_bits(seq)); 3485 amdgpu_ring_write(ring, 0); 3486 } 3487 3488 static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3489 { 3490 uint32_t seq = ring->fence_drv.sync_seq; 3491 uint64_t addr = ring->fence_drv.gpu_addr; 3492 3493 gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), 3494 upper_32_bits(addr), seq, 0xffffffff, 4); 3495 } 3496 3497 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3498 uint16_t pasid, uint32_t flush_type, 3499 bool all_hub, uint8_t dst_sel) 3500 { 3501 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3502 amdgpu_ring_write(ring, 3503 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 3504 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3505 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3506 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3507 } 3508 3509 static void gfx_v12_1_ring_emit_vm_flush(struct amdgpu_ring *ring, 3510 unsigned vmid, uint64_t pd_addr) 3511 { 3512 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3513 3514 /* compute doesn't have PFP */ 3515 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 3516 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3517 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3518 amdgpu_ring_write(ring, 0x0); 3519 } 3520 } 3521 3522 static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3523 u64 seq, unsigned int flags) 3524 { 3525 struct amdgpu_device *adev = ring->adev; 3526 3527 /* write fence seq to the "addr" */ 3528 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3529 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3530 amdgpu_ring_write(ring, lower_32_bits(addr)); 3531 amdgpu_ring_write(ring, upper_32_bits(addr)); 3532 amdgpu_ring_write(ring, lower_32_bits(seq)); 3533 3534 if (flags & AMDGPU_FENCE_FLAG_INT) { 3535 /* set register to trigger INT */ 3536 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3537 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3538 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3539 amdgpu_ring_write(ring, 0); 3540 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3541 } 3542 } 3543 3544 static void gfx_v12_1_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3545 uint32_t reg_val_offs) 3546 { 3547 struct amdgpu_device *adev = ring->adev; 3548 3549 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3550 3551 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3552 amdgpu_ring_write(ring, 0 | /* src: register*/ 3553 (5 << 8) | /* dst: memory */ 3554 (1 << 20)); /* write confirm */ 3555 amdgpu_ring_write(ring, reg); 3556 amdgpu_ring_write(ring, 0); 3557 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3558 reg_val_offs * 4)); 3559 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3560 reg_val_offs * 4)); 3561 } 3562 3563 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, 3564 uint32_t reg, 3565 uint32_t val) 3566 { 3567 uint32_t cmd = 0; 3568 3569 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3570 3571 switch (ring->funcs->type) { 3572 case AMDGPU_RING_TYPE_KIQ: 3573 cmd = (1 << 16); /* no inc addr */ 3574 break; 3575 default: 3576 cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1); 3577 break; 3578 } 3579 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3580 amdgpu_ring_write(ring, cmd); 3581 amdgpu_ring_write(ring, reg); 3582 amdgpu_ring_write(ring, 0); 3583 amdgpu_ring_write(ring, val); 3584 } 3585 3586 static void gfx_v12_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3587 uint32_t val, uint32_t mask) 3588 { 3589 gfx_v12_1_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3590 } 3591 3592 static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3593 uint32_t reg0, uint32_t reg1, 3594 uint32_t ref, uint32_t mask) 3595 { 3596 gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, 3597 ref, mask, 0x20); 3598 } 3599 3600 static void gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3601 int me, int pipe, 3602 enum amdgpu_interrupt_state state, 3603 int xcc_id) 3604 { 3605 u32 mec_int_cntl, mec_int_cntl_reg; 3606 3607 /* 3608 * amdgpu controls only the first MEC. That's why this function only 3609 * handles the setting of interrupts for this specific MEC. All other 3610 * pipes' interrupts are set by amdkfd. 3611 */ 3612 3613 if (me == 1) { 3614 switch (pipe) { 3615 case 0: 3616 mec_int_cntl_reg = SOC15_REG_OFFSET( 3617 GC, GET_INST(GC, xcc_id), 3618 regCP_ME1_PIPE0_INT_CNTL); 3619 break; 3620 case 1: 3621 mec_int_cntl_reg = SOC15_REG_OFFSET( 3622 GC, GET_INST(GC, xcc_id), 3623 regCP_ME1_PIPE1_INT_CNTL); 3624 break; 3625 case 2: 3626 mec_int_cntl_reg = SOC15_REG_OFFSET( 3627 GC, GET_INST(GC, xcc_id), 3628 regCP_ME1_PIPE2_INT_CNTL); 3629 break; 3630 case 3: 3631 mec_int_cntl_reg = SOC15_REG_OFFSET( 3632 GC, GET_INST(GC, xcc_id), 3633 regCP_ME1_PIPE3_INT_CNTL); 3634 break; 3635 default: 3636 DRM_DEBUG("invalid pipe %d\n", pipe); 3637 return; 3638 } 3639 } else { 3640 DRM_DEBUG("invalid me %d\n", me); 3641 return; 3642 } 3643 3644 switch (state) { 3645 case AMDGPU_IRQ_STATE_DISABLE: 3646 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3647 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3648 TIME_STAMP_INT_ENABLE, 0); 3649 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3650 GENERIC0_INT_ENABLE, 0); 3651 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3652 break; 3653 case AMDGPU_IRQ_STATE_ENABLE: 3654 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3655 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3656 TIME_STAMP_INT_ENABLE, 1); 3657 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3658 GENERIC0_INT_ENABLE, 1); 3659 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3660 break; 3661 default: 3662 break; 3663 } 3664 } 3665 3666 static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, 3667 struct amdgpu_irq_src *src, 3668 unsigned type, 3669 enum amdgpu_interrupt_state state) 3670 { 3671 int i, num_xcc; 3672 3673 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3674 for (i = 0; i < num_xcc; i++) { 3675 switch (type) { 3676 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3677 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3678 adev, 1, 0, state, i); 3679 break; 3680 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3681 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3682 adev, 1, 1, state, i); 3683 break; 3684 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3685 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3686 adev, 1, 2, state, i); 3687 break; 3688 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3689 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3690 adev, 1, 3, state, i); 3691 break; 3692 default: 3693 break; 3694 } 3695 } 3696 3697 return 0; 3698 } 3699 3700 static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, 3701 struct amdgpu_irq_src *source, 3702 struct amdgpu_iv_entry *entry) 3703 { 3704 u32 doorbell_offset = entry->src_data[0]; 3705 u8 me_id, pipe_id, queue_id; 3706 struct amdgpu_ring *ring; 3707 int i, xcc_id; 3708 3709 DRM_DEBUG("IH: CP EOP\n"); 3710 3711 if (adev->enable_mes && doorbell_offset) { 3712 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 3713 } else { 3714 me_id = (entry->ring_id & 0x0c) >> 2; 3715 pipe_id = (entry->ring_id & 0x03) >> 0; 3716 queue_id = (entry->ring_id & 0x70) >> 4; 3717 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3718 3719 if (xcc_id == -EINVAL) 3720 return -EINVAL; 3721 3722 switch (me_id) { 3723 case 1: 3724 case 2: 3725 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3726 ring = &adev->gfx.compute_ring 3727 [i + 3728 xcc_id * adev->gfx.num_compute_rings]; 3729 /* Per-queue interrupt is supported for MEC starting from VI. 3730 * The interrupt can only be enabled/disabled per pipe instead 3731 * of per queue. 3732 */ 3733 if ((ring->me == me_id) && 3734 (ring->pipe == pipe_id) && 3735 (ring->queue == queue_id)) 3736 amdgpu_fence_process(ring); 3737 } 3738 break; 3739 default: 3740 dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); 3741 break; 3742 } 3743 } 3744 3745 return 0; 3746 } 3747 3748 static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, 3749 struct amdgpu_irq_src *source, 3750 unsigned type, 3751 enum amdgpu_interrupt_state state) 3752 { 3753 int i, num_xcc; 3754 3755 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3756 switch (state) { 3757 case AMDGPU_IRQ_STATE_DISABLE: 3758 case AMDGPU_IRQ_STATE_ENABLE: 3759 for (i = 0; i < num_xcc; i++) 3760 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3761 PRIV_REG_INT_ENABLE, 3762 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3763 break; 3764 default: 3765 break; 3766 } 3767 3768 return 0; 3769 } 3770 3771 static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, 3772 struct amdgpu_irq_src *source, 3773 unsigned type, 3774 enum amdgpu_interrupt_state state) 3775 { 3776 int i, num_xcc; 3777 3778 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3779 switch (state) { 3780 case AMDGPU_IRQ_STATE_DISABLE: 3781 case AMDGPU_IRQ_STATE_ENABLE: 3782 for (i = 0; i < num_xcc; i++) 3783 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3784 PRIV_INSTR_INT_ENABLE, 3785 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3786 break; 3787 default: 3788 break; 3789 } 3790 3791 return 0; 3792 } 3793 3794 static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 3795 struct amdgpu_iv_entry *entry) 3796 { 3797 u8 me_id, pipe_id, queue_id; 3798 struct amdgpu_ring *ring; 3799 int i, xcc_id; 3800 3801 me_id = (entry->ring_id & 0x0c) >> 2; 3802 pipe_id = (entry->ring_id & 0x03) >> 0; 3803 queue_id = (entry->ring_id & 0x70) >> 4; 3804 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3805 3806 if (xcc_id == -EINVAL) 3807 return; 3808 3809 if (!adev->gfx.disable_kq) { 3810 switch (me_id) { 3811 case 1: 3812 case 2: 3813 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3814 ring = &adev->gfx.compute_ring 3815 [i + 3816 xcc_id * adev->gfx.num_compute_rings]; 3817 if (ring->me == me_id && ring->pipe == pipe_id && 3818 ring->queue == queue_id) 3819 drm_sched_fault(&ring->sched); 3820 } 3821 break; 3822 default: 3823 dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); 3824 break; 3825 } 3826 } 3827 } 3828 3829 static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev, 3830 struct amdgpu_irq_src *source, 3831 struct amdgpu_iv_entry *entry) 3832 { 3833 DRM_ERROR("Illegal register access in command stream\n"); 3834 gfx_v12_1_handle_priv_fault(adev, entry); 3835 return 0; 3836 } 3837 3838 static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, 3839 struct amdgpu_irq_src *source, 3840 struct amdgpu_iv_entry *entry) 3841 { 3842 DRM_ERROR("Illegal instruction in command stream\n"); 3843 gfx_v12_1_handle_priv_fault(adev, entry); 3844 return 0; 3845 } 3846 3847 static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, 3848 struct amdgpu_irq_src *source, 3849 struct amdgpu_iv_entry *entry) 3850 { 3851 uint32_t rlc_fed_status = 0; 3852 uint32_t ras_blk = RAS_BLOCK_ID__GFX; 3853 struct ras_ih_info ih_info = {0}; 3854 int i, num_xcc; 3855 3856 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3857 for (i = 0; i < num_xcc; i++) 3858 rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, 3859 GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); 3860 3861 if (!rlc_fed_status) 3862 return 0; 3863 3864 if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || 3865 REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) 3866 ras_blk = RAS_BLOCK_ID__SDMA; 3867 3868 dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); 3869 3870 ih_info.block = ras_blk; 3871 ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 3872 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 3873 return 0; 3874 } 3875 3876 static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) 3877 { 3878 const unsigned int gcr_cntl = 3879 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | 3880 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | 3881 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | 3882 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | 3883 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | 3884 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); 3885 3886 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 3887 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 3888 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 3889 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3890 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3891 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3892 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3893 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3894 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 3895 } 3896 3897 static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { 3898 .name = "gfx_v12_1", 3899 .early_init = gfx_v12_1_early_init, 3900 .sw_init = gfx_v12_1_sw_init, 3901 .sw_fini = gfx_v12_1_sw_fini, 3902 .hw_init = gfx_v12_1_hw_init, 3903 .hw_fini = gfx_v12_1_hw_fini, 3904 .suspend = gfx_v12_1_suspend, 3905 .resume = gfx_v12_1_resume, 3906 .is_idle = gfx_v12_1_is_idle, 3907 .wait_for_idle = gfx_v12_1_wait_for_idle, 3908 .set_clockgating_state = gfx_v12_1_set_clockgating_state, 3909 .set_powergating_state = gfx_v12_1_set_powergating_state, 3910 .get_clockgating_state = gfx_v12_1_get_clockgating_state, 3911 }; 3912 3913 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { 3914 .type = AMDGPU_RING_TYPE_COMPUTE, 3915 .align_mask = 0xff, 3916 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3917 .support_64bit_ptrs = true, 3918 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 3919 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3920 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3921 .emit_frame_size = 3922 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3923 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3924 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3925 2 + /* gfx_v12_1_ring_emit_vm_flush */ 3926 8 + 8 + 8 + /* gfx_v12_1_ring_emit_fence x3 for user fence, vm fence */ 3927 8, /* gfx_v12_1_emit_mem_sync */ 3928 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 3929 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 3930 .emit_fence = gfx_v12_1_ring_emit_fence, 3931 .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, 3932 .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, 3933 .test_ring = gfx_v12_1_ring_test_ring, 3934 .test_ib = gfx_v12_1_ring_test_ib, 3935 .insert_nop = amdgpu_ring_insert_nop, 3936 .pad_ib = amdgpu_ring_generic_pad_ib, 3937 .emit_wreg = gfx_v12_1_ring_emit_wreg, 3938 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 3939 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 3940 .emit_mem_sync = gfx_v12_1_emit_mem_sync, 3941 }; 3942 3943 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_kiq = { 3944 .type = AMDGPU_RING_TYPE_KIQ, 3945 .align_mask = 0xff, 3946 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3947 .support_64bit_ptrs = true, 3948 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 3949 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3950 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3951 .emit_frame_size = 3952 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3953 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3954 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3955 2 + /* gfx_v12_1_ring_emit_vm_flush */ 3956 8 + 8 + 8, /* gfx_v12_1_ring_emit_fence_kiq x3 for user fence, vm fence */ 3957 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 3958 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 3959 .emit_fence = gfx_v12_1_ring_emit_fence_kiq, 3960 .test_ring = gfx_v12_1_ring_test_ring, 3961 .test_ib = gfx_v12_1_ring_test_ib, 3962 .insert_nop = amdgpu_ring_insert_nop, 3963 .pad_ib = amdgpu_ring_generic_pad_ib, 3964 .emit_rreg = gfx_v12_1_ring_emit_rreg, 3965 .emit_wreg = gfx_v12_1_ring_emit_wreg, 3966 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 3967 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 3968 }; 3969 3970 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev) 3971 { 3972 int i, j, num_xcc; 3973 3974 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3975 for (i = 0; i < num_xcc; i++) { 3976 adev->gfx.kiq[i].ring.funcs = &gfx_v12_1_ring_funcs_kiq; 3977 3978 for (j = 0; j < adev->gfx.num_compute_rings; j++) 3979 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs = 3980 &gfx_v12_1_ring_funcs_compute; 3981 } 3982 } 3983 3984 static const struct amdgpu_irq_src_funcs gfx_v12_1_eop_irq_funcs = { 3985 .set = gfx_v12_1_set_eop_interrupt_state, 3986 .process = gfx_v12_1_eop_irq, 3987 }; 3988 3989 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_reg_irq_funcs = { 3990 .set = gfx_v12_1_set_priv_reg_fault_state, 3991 .process = gfx_v12_1_priv_reg_irq, 3992 }; 3993 3994 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { 3995 .set = gfx_v12_1_set_priv_inst_fault_state, 3996 .process = gfx_v12_1_priv_inst_irq, 3997 }; 3998 3999 static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { 4000 .process = gfx_v12_1_rlc_poison_irq, 4001 }; 4002 4003 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) 4004 { 4005 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4006 adev->gfx.eop_irq.funcs = &gfx_v12_1_eop_irq_funcs; 4007 4008 adev->gfx.priv_reg_irq.num_types = 1; 4009 adev->gfx.priv_reg_irq.funcs = &gfx_v12_1_priv_reg_irq_funcs; 4010 4011 adev->gfx.priv_inst_irq.num_types = 1; 4012 adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; 4013 4014 adev->gfx.rlc_poison_irq.num_types = 1; 4015 adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; 4016 } 4017 4018 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) 4019 { 4020 if (adev->flags & AMD_IS_APU) 4021 adev->gfx.imu.mode = MISSION_MODE; 4022 else 4023 adev->gfx.imu.mode = DEBUG_MODE; 4024 if (!amdgpu_sriov_vf(adev)) 4025 adev->gfx.imu.funcs = &gfx_v12_1_imu_funcs; 4026 } 4027 4028 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev) 4029 { 4030 adev->gfx.rlc.funcs = &gfx_v12_1_rlc_funcs; 4031 } 4032 4033 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev) 4034 { 4035 /* set compute eng mqd */ 4036 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 4037 sizeof(struct v12_1_compute_mqd); 4038 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 4039 gfx_v12_1_compute_mqd_init; 4040 } 4041 4042 static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev, 4043 u32 bitmap, int xcc_id) 4044 { 4045 u32 data; 4046 4047 if (!bitmap) 4048 return; 4049 4050 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4051 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4052 4053 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4054 } 4055 4056 static u32 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev, 4057 int xcc_id) 4058 { 4059 u32 data, mask; 4060 4061 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4062 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4063 4064 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4065 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4066 4067 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4068 4069 return (~data) & mask; 4070 } 4071 4072 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 4073 struct amdgpu_cu_info *cu_info) 4074 { 4075 int i, j, k, counter, xcc_id, active_cu_number = 0; 4076 u32 mask, bitmap; 4077 unsigned int disable_masks[2 * 2]; 4078 4079 if (!adev || !cu_info) 4080 return -EINVAL; 4081 4082 if (adev->gfx.config.max_shader_engines > 2 || 4083 adev->gfx.config.max_sh_per_se > 2) { 4084 dev_err(adev->dev, 4085 "Max SE (%d) and Max SA per SE (%d) is greater than expected\n", 4086 adev->gfx.config.max_shader_engines, 4087 adev->gfx.config.max_sh_per_se); 4088 return -EINVAL; 4089 } 4090 4091 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4092 adev->gfx.config.max_shader_engines, 4093 adev->gfx.config.max_sh_per_se); 4094 4095 mutex_lock(&adev->grbm_idx_mutex); 4096 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4097 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4098 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4099 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4100 if (!((gfx_v12_1_get_sa_active_bitmap(adev, xcc_id) >> bitmap) & 1)) 4101 continue; 4102 mask = 1; 4103 counter = 0; 4104 gfx_v12_1_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4105 gfx_v12_1_set_user_cu_inactive_bitmap_per_sh( 4106 adev, 4107 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4108 xcc_id); 4109 bitmap = gfx_v12_1_get_cu_active_bitmap_per_sh(adev, xcc_id); 4110 4111 cu_info->bitmap[xcc_id][i][j] = bitmap; 4112 4113 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4114 if (bitmap & mask) 4115 counter++; 4116 4117 mask <<= 1; 4118 } 4119 active_cu_number += counter; 4120 } 4121 } 4122 gfx_v12_1_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 4123 } 4124 mutex_unlock(&adev->grbm_idx_mutex); 4125 4126 cu_info->number = active_cu_number; 4127 cu_info->simd_per_cu = NUM_SIMD_PER_CU_GFX12_1; 4128 cu_info->lds_size = 320; 4129 4130 return 0; 4131 } 4132 4133 const struct amdgpu_ip_block_version gfx_v12_1_ip_block = { 4134 .type = AMD_IP_BLOCK_TYPE_GFX, 4135 .major = 12, 4136 .minor = 1, 4137 .rev = 0, 4138 .funcs = &gfx_v12_1_ip_funcs, 4139 }; 4140 4141 static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) 4142 { 4143 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4144 uint32_t tmp_mask; 4145 int i, r; 4146 4147 /* TODO : Initialize golden regs */ 4148 /* gfx_v12_1_init_golden_registers(adev); */ 4149 4150 tmp_mask = inst_mask; 4151 for_each_inst(i, tmp_mask) 4152 gfx_v12_1_xcc_constants_init(adev, i); 4153 4154 if (!amdgpu_sriov_vf(adev)) { 4155 tmp_mask = inst_mask; 4156 for_each_inst(i, tmp_mask) { 4157 r = gfx_v12_1_xcc_rlc_resume(adev, i); 4158 if (r) 4159 return r; 4160 } 4161 } 4162 4163 r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); 4164 4165 return r; 4166 } 4167 4168 static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) 4169 { 4170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4171 int i; 4172 4173 for_each_inst(i, inst_mask) 4174 gfx_v12_1_xcc_fini(adev, i); 4175 4176 return 0; 4177 } 4178 4179 struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs = { 4180 .suspend = &gfx_v12_1_xcp_suspend, 4181 .resume = &gfx_v12_1_xcp_resume 4182 }; 4183