1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_userq_fence.h" 34 #include "imu_v12_1.h" 35 #include "soc_v1_0.h" 36 #include "gfx_v12_1_pkt.h" 37 38 #include "gc/gc_12_1_0_offset.h" 39 #include "gc/gc_12_1_0_sh_mask.h" 40 #include "soc24_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_1.h" 47 #include "mes_v12_1.h" 48 #include "amdgpu_ras_mgr.h" 49 50 #define GFX12_MEC_HPD_SIZE 2048 51 #define NUM_SIMD_PER_CU_GFX12_1 4 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000000 56 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 57 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 58 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 59 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 60 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0ae06301 61 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 62 63 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); 65 66 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 67 #define DEFAULT_SH_MEM_CONFIG \ 68 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 69 (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 70 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 71 72 73 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_1[] = { 74 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 75 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 76 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 104 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 105 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 108 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 109 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 110 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 111 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 112 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 113 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 114 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 116 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 127 /* cp header registers */ 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 136 /* SE status registers */ 137 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 138 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 139 }; 140 141 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12_1[] = { 142 /* compute registers */ 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 182 /* cp header registers */ 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 191 }; 192 193 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); 194 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); 195 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); 196 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev); 197 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev); 198 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev); 199 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 200 struct amdgpu_cu_info *cu_info); 201 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev); 202 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 203 u32 sh_num, u32 instance, int xcc_id); 204 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 205 uint32_t val); 206 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 207 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 208 uint16_t pasid, uint32_t flush_type, 209 bool all_hub, uint8_t dst_sel); 210 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 211 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 212 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 213 bool enable); 214 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 215 bool enable, int xcc_id); 216 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); 217 218 static void gfx_v12_1_kiq_set_resources(struct amdgpu_ring *kiq_ring, 219 uint64_t queue_mask) 220 { 221 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 222 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 223 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 224 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 225 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 226 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 227 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 228 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 229 amdgpu_ring_write(kiq_ring, 0); 230 } 231 232 static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, 233 struct amdgpu_ring *ring) 234 { 235 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 236 uint64_t wptr_addr = ring->wptr_gpu_addr; 237 uint32_t me = 0, eng_sel = 0; 238 239 switch (ring->funcs->type) { 240 case AMDGPU_RING_TYPE_COMPUTE: 241 me = 1; 242 eng_sel = 0; 243 break; 244 case AMDGPU_RING_TYPE_MES: 245 me = 2; 246 eng_sel = 5; 247 break; 248 default: 249 WARN_ON(1); 250 } 251 252 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 253 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 254 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 255 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 256 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 257 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 258 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 259 PACKET3_MAP_QUEUES_ME((me)) | 260 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 261 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 262 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 263 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 264 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 265 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 266 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 267 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 268 } 269 270 static void gfx_v12_1_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 271 struct amdgpu_ring *ring, 272 enum amdgpu_unmap_queues_action action, 273 u64 gpu_addr, u64 seq) 274 { 275 struct amdgpu_device *adev = kiq_ring->adev; 276 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 277 278 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 279 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, 280 seq, kiq_ring->xcc_id); 281 return; 282 } 283 284 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 285 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 286 PACKET3_UNMAP_QUEUES_ACTION(action) | 287 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 288 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 289 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 290 amdgpu_ring_write(kiq_ring, 291 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 292 293 if (action == PREEMPT_QUEUES_NO_UNMAP) { 294 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 295 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 296 amdgpu_ring_write(kiq_ring, seq); 297 } else { 298 amdgpu_ring_write(kiq_ring, 0); 299 amdgpu_ring_write(kiq_ring, 0); 300 amdgpu_ring_write(kiq_ring, 0); 301 } 302 } 303 304 static void gfx_v12_1_kiq_query_status(struct amdgpu_ring *kiq_ring, 305 struct amdgpu_ring *ring, 306 u64 addr, u64 seq) 307 { 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 311 amdgpu_ring_write(kiq_ring, 312 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 313 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 314 PACKET3_QUERY_STATUS_COMMAND(2)); 315 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 316 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 317 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 318 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 319 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 320 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 321 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 322 } 323 324 static void gfx_v12_1_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 325 uint16_t pasid, 326 uint32_t flush_type, 327 bool all_hub) 328 { 329 gfx_v12_1_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 330 } 331 332 static const struct kiq_pm4_funcs gfx_v12_1_kiq_pm4_funcs = { 333 .kiq_set_resources = gfx_v12_1_kiq_set_resources, 334 .kiq_map_queues = gfx_v12_1_kiq_map_queues, 335 .kiq_unmap_queues = gfx_v12_1_kiq_unmap_queues, 336 .kiq_query_status = gfx_v12_1_kiq_query_status, 337 .kiq_invalidate_tlbs = gfx_v12_1_kiq_invalidate_tlbs, 338 .set_resources_size = 8, 339 .map_queues_size = 7, 340 .unmap_queues_size = 6, 341 .query_status_size = 7, 342 .invalidate_tlbs_size = 2, 343 }; 344 345 static void gfx_v12_1_set_kiq_pm4_funcs(struct amdgpu_device *adev) 346 { 347 int i, num_xcc; 348 349 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 350 for (i =0; i < num_xcc; i++) 351 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; 352 } 353 354 static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 355 int mem_space, int opt, uint32_t addr0, 356 uint32_t addr1, uint32_t ref, 357 uint32_t mask, uint32_t inv) 358 { 359 if (mem_space == 0) { 360 addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0); 361 addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1); 362 } 363 364 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 365 amdgpu_ring_write(ring, 366 /* memory (1) or register (0) */ 367 (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | 368 PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ 369 PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ 370 371 if (mem_space) 372 WARN_ON(addr0 & 0x3); /* Dword align */ 373 amdgpu_ring_write(ring, addr0); 374 amdgpu_ring_write(ring, addr1); 375 amdgpu_ring_write(ring, ref); 376 amdgpu_ring_write(ring, mask); 377 amdgpu_ring_write(ring, inv); /* poll interval */ 378 } 379 380 static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring) 381 { 382 struct amdgpu_device *adev = ring->adev; 383 uint32_t scratch_reg0_offset, xcc_offset; 384 uint32_t tmp = 0; 385 unsigned i; 386 int r; 387 388 /* Use register offset which is local to XCC in the packet */ 389 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 390 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 391 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 392 tmp = RREG32(scratch_reg0_offset); 393 394 r = amdgpu_ring_alloc(ring, 5); 395 if (r) { 396 dev_err(adev->dev, 397 "amdgpu: cp failed to lock ring %d (%d).\n", 398 ring->idx, r); 399 return r; 400 } 401 402 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 403 gfx_v12_1_ring_emit_wreg(ring, xcc_offset, 0xDEADBEEF); 404 } else { 405 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 406 amdgpu_ring_write(ring, xcc_offset - 407 PACKET3_SET_UCONFIG_REG_START); 408 amdgpu_ring_write(ring, 0xDEADBEEF); 409 } 410 amdgpu_ring_commit(ring); 411 412 for (i = 0; i < adev->usec_timeout; i++) { 413 tmp = RREG32(scratch_reg0_offset); 414 if (tmp == 0xDEADBEEF) 415 break; 416 if (amdgpu_emu_mode == 1) 417 msleep(1); 418 else 419 udelay(1); 420 } 421 422 if (i >= adev->usec_timeout) 423 r = -ETIMEDOUT; 424 return r; 425 } 426 427 static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) 428 { 429 struct amdgpu_device *adev = ring->adev; 430 struct amdgpu_ib ib; 431 struct dma_fence *f = NULL; 432 unsigned index; 433 uint64_t gpu_addr; 434 volatile uint32_t *cpu_ptr; 435 long r; 436 437 /* MES KIQ fw hasn't indirect buffer support for now */ 438 if (adev->enable_mes_kiq && 439 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 440 return 0; 441 442 memset(&ib, 0, sizeof(ib)); 443 444 r = amdgpu_wb_get(adev, &index); 445 if (r) 446 return r; 447 448 gpu_addr = adev->wb.gpu_addr + (index * 4); 449 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 450 cpu_ptr = &adev->wb.wb[index]; 451 452 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 453 if (r) { 454 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 455 goto err1; 456 } 457 458 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 459 ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); 460 ib.ptr[2] = lower_32_bits(gpu_addr); 461 ib.ptr[3] = upper_32_bits(gpu_addr); 462 ib.ptr[4] = 0xDEADBEEF; 463 ib.length_dw = 5; 464 465 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 466 if (r) 467 goto err2; 468 469 r = dma_fence_wait_timeout(f, false, timeout); 470 if (r == 0) { 471 r = -ETIMEDOUT; 472 goto err2; 473 } else if (r < 0) { 474 goto err2; 475 } 476 477 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 478 r = 0; 479 else 480 r = -EINVAL; 481 err2: 482 amdgpu_ib_free(&ib, NULL); 483 dma_fence_put(f); 484 err1: 485 amdgpu_wb_free(adev, index); 486 return r; 487 } 488 489 static void gfx_v12_1_free_microcode(struct amdgpu_device *adev) 490 { 491 amdgpu_ucode_release(&adev->gfx.rlc_fw); 492 amdgpu_ucode_release(&adev->gfx.mec_fw); 493 494 kfree(adev->gfx.rlc.register_list_format); 495 } 496 497 static int gfx_v12_1_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 498 { 499 const struct psp_firmware_header_v1_0 *toc_hdr; 500 int err = 0; 501 502 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 503 AMDGPU_UCODE_REQUIRED, 504 "amdgpu/%s_toc.bin", ucode_prefix); 505 if (err) 506 goto out; 507 508 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 509 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 510 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 511 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 512 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 513 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 514 return 0; 515 out: 516 amdgpu_ucode_release(&adev->psp.toc_fw); 517 return err; 518 } 519 520 static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) 521 { 522 char ucode_prefix[15]; 523 int err; 524 const struct rlc_firmware_header_v2_0 *rlc_hdr; 525 uint16_t version_major; 526 uint16_t version_minor; 527 528 DRM_DEBUG("\n"); 529 530 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 531 532 if (!amdgpu_sriov_vf(adev)) { 533 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && 534 adev->rev_id == 0) 535 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 536 AMDGPU_UCODE_REQUIRED, 537 "amdgpu/%s_rlc_1.bin", ucode_prefix); 538 else 539 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 540 AMDGPU_UCODE_REQUIRED, 541 "amdgpu/%s_rlc.bin", ucode_prefix); 542 if (err) 543 goto out; 544 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 545 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 546 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 547 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 548 if (err) 549 goto out; 550 } 551 552 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 553 AMDGPU_UCODE_REQUIRED, 554 "amdgpu/%s_mec.bin", ucode_prefix); 555 if (err) 556 goto out; 557 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 558 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 559 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 560 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 561 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 562 563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 564 err = gfx_v12_1_init_toc_microcode(adev, ucode_prefix); 565 566 /* only one MEC for gfx 12 */ 567 adev->gfx.mec2_fw = NULL; 568 569 if (adev->gfx.imu.funcs) { 570 if (adev->gfx.imu.funcs->init_microcode) { 571 err = adev->gfx.imu.funcs->init_microcode(adev); 572 if (err) 573 dev_err(adev->dev, "Failed to load imu firmware!\n"); 574 } 575 } 576 577 out: 578 if (err) { 579 amdgpu_ucode_release(&adev->gfx.rlc_fw); 580 amdgpu_ucode_release(&adev->gfx.mec_fw); 581 } 582 583 return err; 584 } 585 586 static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev) 587 { 588 u32 count = 0; 589 const struct cs_section_def *sect = NULL; 590 const struct cs_extent_def *ext = NULL; 591 592 count += 1; 593 594 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 595 if (sect->id == SECT_CONTEXT) { 596 for (ext = sect->section; ext->extent != NULL; ++ext) 597 count += 2 + ext->reg_count; 598 } else 599 return 0; 600 } 601 602 return count; 603 } 604 605 static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 606 { 607 u32 count = 0, clustercount = 0, i; 608 const struct cs_section_def *sect = NULL; 609 const struct cs_extent_def *ext = NULL; 610 611 if (adev->gfx.rlc.cs_data == NULL) 612 return; 613 if (buffer == NULL) 614 return; 615 616 count += 1; 617 618 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 619 if (sect->id == SECT_CONTEXT) { 620 for (ext = sect->section; ext->extent != NULL; ++ext) { 621 clustercount++; 622 buffer[count++] = ext->reg_count; 623 buffer[count++] = ext->reg_index; 624 625 for (i = 0; i < ext->reg_count; i++) 626 buffer[count++] = cpu_to_le32(ext->extent[i]); 627 } 628 } else 629 return; 630 } 631 632 buffer[0] = clustercount; 633 } 634 635 static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev) 636 { 637 /* clear state block */ 638 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 639 &adev->gfx.rlc.clear_state_gpu_addr, 640 (void **)&adev->gfx.rlc.cs_ptr); 641 642 /* jump table block */ 643 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 644 &adev->gfx.rlc.cp_table_gpu_addr, 645 (void **)&adev->gfx.rlc.cp_table_ptr); 646 } 647 648 static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 649 { 650 int xcc_id, num_xcc; 651 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 652 653 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 654 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 655 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 656 657 reg_access_ctrl->grbm_cntl = 658 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 659 reg_access_ctrl->grbm_idx = 660 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 661 662 reg_access_ctrl->vfi_cmd = 663 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD); 664 reg_access_ctrl->vfi_stat = 665 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT); 666 reg_access_ctrl->vfi_addr = 667 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR); 668 reg_access_ctrl->vfi_data = 669 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA); 670 reg_access_ctrl->vfi_grbm_cntl = 671 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL); 672 reg_access_ctrl->vfi_grbm_idx = 673 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX); 674 reg_access_ctrl->vfi_grbm_cntl_data = 0; 675 reg_access_ctrl->vfi_grbm_idx_data = 0; 676 } 677 adev->gfx.rlc.rlcg_reg_access_supported = true; 678 } 679 680 static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) 681 { 682 const struct cs_section_def *cs_data; 683 int r, i, num_xcc; 684 685 adev->gfx.rlc.cs_data = gfx12_cs_data; 686 687 cs_data = adev->gfx.rlc.cs_data; 688 689 if (cs_data) { 690 /* init clear state block */ 691 r = amdgpu_gfx_rlc_init_csb(adev); 692 if (r) 693 return r; 694 } 695 696 /* init spm vmid with 0xf */ 697 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 698 for (i = 0; i < num_xcc; i++) { 699 if (adev->gfx.rlc.funcs->update_spm_vmid) 700 adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); 701 } 702 703 return 0; 704 } 705 706 static void gfx_v12_1_mec_fini(struct amdgpu_device *adev) 707 { 708 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 709 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 710 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 711 } 712 713 static int gfx_v12_1_mec_init(struct amdgpu_device *adev) 714 { 715 int r, i, num_xcc; 716 u32 *hpd; 717 size_t mec_hpd_size; 718 719 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 720 721 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 722 for (i = 0; i < num_xcc; i++) 723 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 724 AMDGPU_MAX_COMPUTE_QUEUES); 725 726 /* take ownership of the relevant compute queues */ 727 amdgpu_gfx_compute_queue_acquire(adev); 728 mec_hpd_size = adev->gfx.num_compute_rings * 729 GFX12_MEC_HPD_SIZE * num_xcc; 730 731 if (mec_hpd_size) { 732 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 733 AMDGPU_GEM_DOMAIN_GTT, 734 &adev->gfx.mec.hpd_eop_obj, 735 &adev->gfx.mec.hpd_eop_gpu_addr, 736 (void **)&hpd); 737 if (r) { 738 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 739 gfx_v12_1_mec_fini(adev); 740 return r; 741 } 742 743 memset(hpd, 0, mec_hpd_size); 744 745 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 746 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 747 } 748 749 return 0; 750 } 751 752 static uint32_t wave_read_ind(struct amdgpu_device *adev, 753 uint32_t xcc_id, uint32_t wave, 754 uint32_t address) 755 { 756 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 757 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 758 (address << SQ_IND_INDEX__INDEX__SHIFT)); 759 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 760 } 761 762 static void wave_read_regs(struct amdgpu_device *adev, 763 uint32_t xcc_id, uint32_t wave, 764 uint32_t thread, uint32_t regno, 765 uint32_t num, uint32_t *out) 766 { 767 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 768 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 769 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 770 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 771 (SQ_IND_INDEX__AUTO_INCR_MASK)); 772 while (num--) 773 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 774 } 775 776 static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, 777 uint32_t xcc_id, 778 uint32_t simd, uint32_t wave, 779 uint32_t *dst, int *no_fields) 780 { 781 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 782 * field when performing a select_se_sh so it should be 783 * zero here */ 784 WARN_ON(simd != 0); 785 786 /* type 4 wave data */ 787 dst[(*no_fields)++] = 4; 788 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); 789 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); 790 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); 791 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); 792 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); 793 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); 794 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); 795 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); 796 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); 797 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); 798 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); 799 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); 800 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); 801 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); 802 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); 803 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 804 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); 805 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); 806 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); 807 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); 808 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 809 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 810 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); 811 } 812 813 static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, 814 uint32_t xcc_id, uint32_t simd, 815 uint32_t wave, uint32_t start, 816 uint32_t size, uint32_t *dst) 817 { 818 WARN_ON(simd != 0); 819 820 wave_read_regs(adev, xcc_id, wave, 0, 821 start + SQIND_WAVE_SGPRS_OFFSET, 822 size, dst); 823 } 824 825 static void gfx_v12_1_read_wave_vgprs(struct amdgpu_device *adev, 826 uint32_t xcc_id, uint32_t simd, 827 uint32_t wave, uint32_t thread, 828 uint32_t start, uint32_t size, 829 uint32_t *dst) 830 { 831 wave_read_regs(adev, xcc_id, wave, thread, 832 start + SQIND_WAVE_VGPRS_OFFSET, 833 size, dst); 834 } 835 836 static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, 837 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 838 { 839 soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 840 } 841 842 #define regGFX_IMU_PARTITION_SWITCH 0x5f8c 843 #define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 844 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 845 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL 846 847 static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) 848 { 849 u32 reg_data; 850 851 /* the register data is expected to be the same on all instances */ 852 reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); 853 854 return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); 855 } 856 857 static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 858 { 859 int logic_xcc; 860 int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; 861 862 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { 863 if (xcc == GET_INST(GC, logic_xcc)) 864 return logic_xcc; 865 } 866 867 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 868 return -EINVAL; 869 } 870 871 static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { 872 .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, 873 .select_se_sh = &gfx_v12_1_xcc_select_se_sh, 874 .read_wave_data = &gfx_v12_1_read_wave_data, 875 .read_wave_sgprs = &gfx_v12_1_read_wave_sgprs, 876 .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, 877 .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, 878 .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, 879 .get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp, 880 .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, 881 }; 882 883 static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) 884 { 885 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 886 case IP_VERSION(12, 1, 0): 887 adev->gfx.config.max_hw_contexts = 8; 888 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 889 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 890 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 891 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 892 break; 893 default: 894 BUG(); 895 break; 896 } 897 898 return 0; 899 } 900 901 static int gfx_v12_1_compute_ring_init(struct amdgpu_device *adev, int ring_id, 902 int xcc_id, int mec, int pipe, int queue) 903 { 904 int r; 905 unsigned irq_type; 906 struct amdgpu_ring *ring; 907 unsigned int hw_prio; 908 uint32_t xcc_doorbell_start; 909 910 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 911 ring_id]; 912 913 /* mec0 is me1 */ 914 ring->xcc_id = xcc_id; 915 ring->me = mec + 1; 916 ring->pipe = pipe; 917 ring->queue = queue; 918 919 ring->ring_obj = NULL; 920 ring->use_doorbell = true; 921 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 922 xcc_id * adev->doorbell_index.xcc_doorbell_range; 923 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 924 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 925 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 926 GFX12_MEC_HPD_SIZE; 927 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 928 sprintf(ring->name, "comp_%d.%d.%d.%d", 929 ring->xcc_id, ring->me, ring->pipe, ring->queue); 930 931 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 932 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 933 + ring->pipe; 934 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 935 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 936 /* type-2 packets are deprecated on MEC, use type-3 instead */ 937 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 938 hw_prio, NULL); 939 if (r) 940 return r; 941 942 return 0; 943 } 944 945 static struct { 946 SOC24_FIRMWARE_ID id; 947 unsigned int offset; 948 unsigned int size; 949 unsigned int size_x16; 950 unsigned int num_inst; 951 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 952 953 #define RLC_TOC_OFFSET_DWUNIT 8 954 #define RLC_SIZE_MULTIPLE 1024 955 #define RLC_TOC_UMF_SIZE_inM 23ULL 956 #define RLC_TOC_FORMAT_API 165ULL 957 958 #define RLC_NUM_INS_CODE0 1 959 #define RLC_NUM_INS_CODE1 8 960 #define RLC_NUM_INS_CODE2 2 961 #define RLC_NUM_INS_CODE3 16 962 963 static void gfx_v12_1_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 964 { 965 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 966 967 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 968 rlc_autoload_info[ucode->id].id = ucode->id; 969 rlc_autoload_info[ucode->id].offset = 970 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 971 rlc_autoload_info[ucode->id].size = 972 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 973 ucode->size * 4; 974 switch (ucode->vfflr_image_code) { 975 case 0: 976 rlc_autoload_info[ucode->id].num_inst = 977 RLC_NUM_INS_CODE0; 978 break; 979 case 1: 980 rlc_autoload_info[ucode->id].num_inst = 981 RLC_NUM_INS_CODE1; 982 break; 983 case 2: 984 rlc_autoload_info[ucode->id].num_inst = 985 RLC_NUM_INS_CODE2; 986 break; 987 case 3: 988 rlc_autoload_info[ucode->id].num_inst = 989 RLC_NUM_INS_CODE3; 990 break; 991 default: 992 dev_err(adev->dev, 993 "Invalid Instance number detected\n"); 994 break; 995 } 996 ucode++; 997 } 998 } 999 1000 static uint32_t gfx_v12_1_calc_toc_total_size(struct amdgpu_device *adev) 1001 { 1002 uint32_t total_size = 0; 1003 SOC24_FIRMWARE_ID id; 1004 1005 gfx_v12_1_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1006 1007 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1008 total_size += rlc_autoload_info[id].size; 1009 1010 /* In case the offset in rlc toc ucode is aligned */ 1011 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1012 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1013 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1014 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1015 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1016 1017 return total_size; 1018 } 1019 1020 static int gfx_v12_1_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1021 { 1022 int r; 1023 uint32_t total_size; 1024 1025 total_size = gfx_v12_1_calc_toc_total_size(adev); 1026 1027 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1028 AMDGPU_GEM_DOMAIN_VRAM, 1029 &adev->gfx.rlc.rlc_autoload_bo, 1030 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1031 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1032 1033 if (r) { 1034 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1035 return r; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static void gfx_v12_1_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1042 SOC24_FIRMWARE_ID id, 1043 const void *fw_data, 1044 uint32_t fw_size) 1045 { 1046 uint32_t toc_offset; 1047 uint32_t toc_fw_size, toc_fw_inst_size; 1048 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1049 int i, num_inst; 1050 1051 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1052 return; 1053 1054 toc_offset = rlc_autoload_info[id].offset; 1055 toc_fw_size = rlc_autoload_info[id].size; 1056 num_inst = rlc_autoload_info[id].num_inst; 1057 toc_fw_inst_size = toc_fw_size / num_inst; 1058 1059 if (fw_size == 0) 1060 fw_size = toc_fw_inst_size; 1061 1062 if (fw_size > toc_fw_inst_size) 1063 fw_size = toc_fw_inst_size; 1064 1065 for (i = 0; i < num_inst; i++) { 1066 if ((num_inst == RLC_NUM_INS_CODE0) || 1067 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { 1068 memcpy(ptr + toc_offset + i * toc_fw_inst_size, fw_data, fw_size); 1069 1070 if (fw_size < toc_fw_inst_size) 1071 memset(ptr + toc_offset + fw_size + i * toc_fw_inst_size, 1072 0, toc_fw_inst_size - fw_size); 1073 } 1074 } 1075 } 1076 1077 static void 1078 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1079 { 1080 void *data; 1081 uint32_t size; 1082 uint32_t *toc_ptr; 1083 1084 data = adev->psp.toc.start_addr; 1085 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1086 1087 toc_ptr = (uint32_t *)data + size / 4 - 2; 1088 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1089 1090 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1091 data, size); 1092 } 1093 1094 static void 1095 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1096 { 1097 const __le32 *fw_data; 1098 uint32_t fw_size; 1099 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1100 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1101 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1102 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1103 uint16_t version_major, version_minor; 1104 1105 /* mec ucode */ 1106 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1107 adev->gfx.mec_fw->data; 1108 /* instruction */ 1109 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1110 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1111 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1112 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1113 fw_data, fw_size); 1114 /* data */ 1115 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1116 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1117 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1118 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1119 fw_data, fw_size); 1120 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1121 fw_data, fw_size); 1122 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1123 fw_data, fw_size); 1124 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1125 fw_data, fw_size); 1126 1127 /* rlc ucode */ 1128 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1129 adev->gfx.rlc_fw->data; 1130 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1131 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1132 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1133 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1134 fw_data, fw_size); 1135 1136 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1137 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1138 if (version_major == 2) { 1139 if (version_minor >= 1) { 1140 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1141 1142 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1143 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1144 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1145 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1146 fw_data, fw_size); 1147 1148 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1149 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1150 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1151 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1152 fw_data, fw_size); 1153 } 1154 if (version_minor >= 2) { 1155 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1156 1157 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1158 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1159 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1160 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1161 fw_data, fw_size); 1162 1163 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1164 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1165 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1166 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1167 fw_data, fw_size); 1168 } 1169 } 1170 } 1171 1172 static void 1173 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1174 { 1175 const __le32 *fw_data; 1176 uint32_t fw_size; 1177 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1178 1179 if (adev->sdma.instance[0].fw) { 1180 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1181 adev->sdma.instance[0].fw->data; 1182 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1183 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1184 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1185 1186 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1187 fw_data, fw_size); 1188 } 1189 } 1190 1191 static void 1192 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1193 { 1194 const __le32 *fw_data; 1195 unsigned fw_size; 1196 const struct mes_firmware_header_v1_0 *mes_hdr; 1197 int pipe, ucode_id, data_id; 1198 1199 for (pipe = 0; pipe < 2; pipe++) { 1200 if (pipe == 0) { 1201 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1202 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1203 } else { 1204 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1205 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1206 } 1207 1208 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1209 adev->mes.fw[pipe]->data; 1210 1211 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1212 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1213 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1214 1215 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1216 1217 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1218 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1219 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1220 1221 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1222 } 1223 } 1224 1225 static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1226 { 1227 uint32_t rlc_g_offset, rlc_g_size; 1228 uint64_t gpu_addr; 1229 uint32_t data; 1230 int i, num_xcc; 1231 1232 /* RLC autoload sequence 2: copy ucode */ 1233 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1234 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1235 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(adev); 1236 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(adev); 1237 1238 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1239 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1240 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1241 1242 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1243 for (i = 0; i < num_xcc; i++) { 1244 WREG32_SOC15(GC, GET_INST(GC, i), 1245 regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, 1246 upper_32_bits(gpu_addr)); 1247 WREG32_SOC15(GC, GET_INST(GC, i), 1248 regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, 1249 lower_32_bits(gpu_addr)); 1250 WREG32_SOC15(GC, GET_INST(GC, i), 1251 regGFX_IMU_RLC_BOOTLOADER_SIZE, 1252 rlc_g_size); 1253 } 1254 1255 if (adev->gfx.imu.funcs) { 1256 /* RLC autoload sequence 3: load IMU fw */ 1257 if (adev->gfx.imu.funcs->load_microcode) 1258 adev->gfx.imu.funcs->load_microcode(adev); 1259 } 1260 1261 /* unhalt rlc to start autoload */ 1262 for (i = 0; i < num_xcc; i++) { 1263 data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE); 1264 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1265 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1266 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data); 1267 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static void gfx_v12_1_alloc_ip_dump(struct amdgpu_device *adev) 1274 { 1275 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1276 uint32_t *ptr, inst, num_xcc; 1277 1278 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1279 1280 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1281 if (!ptr) { 1282 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1283 adev->gfx.ip_dump_core = NULL; 1284 } else { 1285 adev->gfx.ip_dump_core = ptr; 1286 } 1287 1288 /* Allocate memory for compute queue registers for all the instances */ 1289 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1290 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1291 adev->gfx.mec.num_queue_per_pipe; 1292 1293 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1294 if (!ptr) { 1295 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1296 adev->gfx.ip_dump_compute_queues = NULL; 1297 } else { 1298 adev->gfx.ip_dump_compute_queues = ptr; 1299 } 1300 } 1301 1302 static void gfx_v12_1_ip_print(struct amdgpu_ip_block *ip_block, 1303 struct drm_printer *p) 1304 { 1305 struct amdgpu_device *adev = ip_block->adev; 1306 uint32_t i, j, k; 1307 uint32_t xcc_id, xcc_offset, inst_offset; 1308 uint32_t num_xcc, reg, num_inst; 1309 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1310 1311 if (!adev->gfx.ip_dump_core) 1312 return; 1313 1314 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1315 drm_printf(p, "Number of Instances:%d\n", num_xcc); 1316 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1317 xcc_offset = xcc_id * reg_count; 1318 drm_printf(p, "\nInstance id:%d\n", xcc_id); 1319 for (i = 0; i < reg_count; i++) 1320 drm_printf(p, "%-50s \t 0x%08x\n", 1321 gc_reg_list_12_1[i].reg_name, 1322 adev->gfx.ip_dump_core[xcc_offset + i]); 1323 } 1324 1325 /* print compute queue registers for all instances */ 1326 if (!adev->gfx.ip_dump_compute_queues) 1327 return; 1328 1329 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1330 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 1331 num_xcc, 1332 adev->gfx.mec.num_mec, 1333 adev->gfx.mec.num_pipe_per_mec, 1334 adev->gfx.mec.num_queue_per_pipe); 1335 1336 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1337 adev->gfx.mec.num_queue_per_pipe; 1338 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1339 xcc_offset = xcc_id * reg_count * num_inst; 1340 inst_offset = 0; 1341 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 1342 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 1343 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 1344 drm_printf(p, 1345 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 1346 xcc_id, i, j, k); 1347 for (reg = 0; reg < reg_count; reg++) { 1348 drm_printf(p, 1349 "%-50s \t 0x%08x\n", 1350 gc_cp_reg_list_12_1[reg].reg_name, 1351 adev->gfx.ip_dump_compute_queues 1352 [xcc_offset + inst_offset + 1353 reg]); 1354 } 1355 inst_offset += reg_count; 1356 } 1357 } 1358 } 1359 } 1360 } 1361 1362 static void gfx_v12_1_ip_dump(struct amdgpu_ip_block *ip_block) 1363 { 1364 struct amdgpu_device *adev = ip_block->adev; 1365 uint32_t i, j, k; 1366 uint32_t num_xcc, reg, num_inst; 1367 uint32_t xcc_id, xcc_offset, inst_offset; 1368 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1369 1370 if (!adev->gfx.ip_dump_core) 1371 return; 1372 1373 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1374 1375 amdgpu_gfx_off_ctrl(adev, false); 1376 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1377 xcc_offset = xcc_id * reg_count; 1378 for (i = 0; i < reg_count; i++) 1379 adev->gfx.ip_dump_core[xcc_offset + i] = 1380 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_12_1[i], 1381 GET_INST(GC, xcc_id))); 1382 } 1383 amdgpu_gfx_off_ctrl(adev, true); 1384 1385 /* dump compute queue registers for all instances */ 1386 if (!adev->gfx.ip_dump_compute_queues) 1387 return; 1388 1389 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1390 adev->gfx.mec.num_queue_per_pipe; 1391 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1392 amdgpu_gfx_off_ctrl(adev, false); 1393 mutex_lock(&adev->srbm_mutex); 1394 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1395 xcc_offset = xcc_id * reg_count * num_inst; 1396 inst_offset = 0; 1397 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 1398 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 1399 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 1400 /* ME0 is for GFX so start from 1 for CP */ 1401 soc_v1_0_grbm_select(adev, 1 + i, j, k, 0, 1402 GET_INST(GC, xcc_id)); 1403 1404 for (reg = 0; reg < reg_count; reg++) { 1405 adev->gfx.ip_dump_compute_queues 1406 [xcc_offset + 1407 inst_offset + reg] = 1408 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 1409 gc_cp_reg_list_12_1[reg], 1410 GET_INST(GC, xcc_id))); 1411 } 1412 inst_offset += reg_count; 1413 } 1414 } 1415 } 1416 } 1417 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, 0); 1418 mutex_unlock(&adev->srbm_mutex); 1419 amdgpu_gfx_off_ctrl(adev, true); 1420 } 1421 1422 static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1423 { 1424 uint16_t major_ver, minor_ver; 1425 int i, j, k, r, ring_id = 0; 1426 unsigned num_compute_rings; 1427 int xcc_id, num_xcc; 1428 struct amdgpu_device *adev = ip_block->adev; 1429 1430 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1431 case IP_VERSION(12, 1, 0): 1432 adev->gfx.mec.num_mec = 1; 1433 adev->gfx.mec.num_pipe_per_mec = 4; 1434 adev->gfx.mec.num_queue_per_pipe = 8; 1435 1436 if (!amdgpu_discovery_get_gc_major_minor_version( 1437 adev, &major_ver, &minor_ver)) { 1438 if (major_ver == 1 && minor_ver == 3) { 1439 adev->gfx.config.max_cu_per_sh /= 2; 1440 dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", 1441 adev->gfx.config.max_cu_per_sh); 1442 } 1443 } 1444 break; 1445 default: 1446 adev->gfx.mec.num_mec = 2; 1447 adev->gfx.mec.num_pipe_per_mec = 2; 1448 adev->gfx.mec.num_queue_per_pipe = 4; 1449 break; 1450 } 1451 1452 if (adev->gfx.num_compute_rings) { 1453 /* recalculate compute rings to use based on hardware configuration */ 1454 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1455 adev->gfx.mec.num_queue_per_pipe) / 2; 1456 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1457 num_compute_rings); 1458 } 1459 1460 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1461 1462 /* EOP Event */ 1463 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1464 GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, 1465 &adev->gfx.eop_irq); 1466 if (r) 1467 return r; 1468 1469 /* Privileged reg */ 1470 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1471 GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, 1472 &adev->gfx.priv_reg_irq); 1473 if (r) 1474 return r; 1475 1476 /* Privileged inst */ 1477 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1478 GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, 1479 &adev->gfx.priv_inst_irq); 1480 if (r) 1481 return r; 1482 1483 /* RLC POISON Error */ 1484 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, 1485 GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, 1486 &adev->gfx.rlc_poison_irq); 1487 if (r) 1488 return r; 1489 1490 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1491 1492 r = gfx_v12_1_rlc_init(adev); 1493 if (r) { 1494 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1495 return r; 1496 } 1497 1498 r = gfx_v12_1_mec_init(adev); 1499 if (r) { 1500 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1501 return r; 1502 } 1503 1504 /* set up the compute queues - allocate horizontally across pipes */ 1505 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1506 ring_id = 0; 1507 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1508 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1509 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1510 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1511 xcc_id, i, k, j)) 1512 continue; 1513 1514 r = gfx_v12_1_compute_ring_init(adev, ring_id, 1515 xcc_id, i, k, j); 1516 if (r) 1517 return r; 1518 1519 ring_id++; 1520 } 1521 } 1522 } 1523 1524 if (!adev->enable_mes_kiq) { 1525 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, xcc_id); 1526 if (r) { 1527 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1528 return r; 1529 } 1530 1531 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1532 if (r) 1533 return r; 1534 } 1535 1536 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_1_compute_mqd), xcc_id); 1537 if (r) 1538 return r; 1539 } 1540 1541 /* allocate visible FB for rlc auto-loading fw */ 1542 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1543 r = gfx_v12_1_rlc_autoload_buffer_init(adev); 1544 if (r) 1545 return r; 1546 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1547 r = gfx_v12_1_init_cp_compute_microcode_bo(adev); 1548 if (r) 1549 return r; 1550 } 1551 1552 r = gfx_v12_1_gpu_early_init(adev); 1553 if (r) 1554 return r; 1555 1556 r = amdgpu_gfx_sysfs_init(adev); 1557 if (r) 1558 return r; 1559 1560 gfx_v12_1_alloc_ip_dump(adev); 1561 1562 mutex_init(&adev->gfx.mec.reset_mutex); 1563 1564 return 0; 1565 } 1566 1567 static void gfx_v12_1_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1568 { 1569 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1570 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1571 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1572 } 1573 1574 static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1575 { 1576 int i, num_xcc; 1577 struct amdgpu_device *adev = ip_block->adev; 1578 1579 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1580 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1581 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1582 1583 for (i = 0; i < num_xcc; i++) { 1584 amdgpu_gfx_mqd_sw_fini(adev, i); 1585 1586 if (!adev->enable_mes_kiq) { 1587 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1588 amdgpu_gfx_kiq_fini(adev, i); 1589 } 1590 } 1591 1592 gfx_v12_1_rlc_fini(adev); 1593 gfx_v12_1_mec_fini(adev); 1594 1595 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1596 gfx_v12_1_rlc_autoload_buffer_fini(adev); 1597 1598 gfx_v12_1_free_microcode(adev); 1599 amdgpu_gfx_sysfs_fini(adev); 1600 1601 kfree(adev->gfx.ip_dump_core); 1602 kfree(adev->gfx.ip_dump_compute_queues); 1603 1604 return 0; 1605 } 1606 1607 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1608 u32 sh_num, u32 instance, int xcc_id) 1609 { 1610 u32 data; 1611 1612 if (instance == 0xffffffff) 1613 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1614 INSTANCE_BROADCAST_WRITES, 1); 1615 else 1616 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1617 instance); 1618 1619 if (se_num == 0xffffffff) 1620 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1621 1); 1622 else 1623 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1624 1625 if (sh_num == 0xffffffff) 1626 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1627 1); 1628 else 1629 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1630 1631 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 1632 } 1633 1634 static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, 1635 int xcc_id) 1636 { 1637 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1638 1639 gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE); 1640 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1641 CC_GC_SA_UNIT_DISABLE, 1642 SA_DISABLE); 1643 gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE); 1644 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1645 GC_USER_SA_UNIT_DISABLE, 1646 SA_DISABLE); 1647 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1648 adev->gfx.config.max_shader_engines); 1649 1650 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1651 } 1652 1653 static u32 gfx_v12_1_get_rb_active_bitmap(struct amdgpu_device *adev, 1654 int xcc_id) 1655 { 1656 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1657 u32 rb_mask; 1658 1659 gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1660 regCC_RB_BACKEND_DISABLE); 1661 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1662 CC_RB_BACKEND_DISABLE, 1663 BACKEND_DISABLE); 1664 gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1665 regGC_USER_RB_BACKEND_DISABLE); 1666 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1667 GC_USER_RB_BACKEND_DISABLE, 1668 BACKEND_DISABLE); 1669 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1670 adev->gfx.config.max_shader_engines); 1671 1672 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1673 } 1674 1675 static void gfx_v12_1_setup_rb(struct amdgpu_device *adev) 1676 { 1677 u32 rb_bitmap_width_per_sa; 1678 u32 max_sa; 1679 u32 active_sa_bitmap; 1680 u32 global_active_rb_bitmap; 1681 u32 active_rb_bitmap = 0; 1682 u32 i; 1683 int xcc_id; 1684 1685 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 1686 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1687 active_sa_bitmap = gfx_v12_1_get_sa_active_bitmap(adev, xcc_id); 1688 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1689 global_active_rb_bitmap = gfx_v12_1_get_rb_active_bitmap(adev, xcc_id); 1690 1691 /* generate active rb bitmap according to active sa bitmap */ 1692 max_sa = adev->gfx.config.max_shader_engines * 1693 adev->gfx.config.max_sh_per_se; 1694 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1695 adev->gfx.config.max_sh_per_se; 1696 for (i = 0; i < max_sa; i++) { 1697 if (active_sa_bitmap & (1 << i)) 1698 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1699 } 1700 1701 active_rb_bitmap |= global_active_rb_bitmap; 1702 } 1703 1704 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1705 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1706 } 1707 1708 static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, 1709 int xcc_id) 1710 { 1711 int i; 1712 uint32_t sh_mem_bases; 1713 uint32_t data; 1714 1715 /* 1716 * Configure apertures: 1717 * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) 1718 * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) 1719 */ 1720 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1721 (adev->gmc.private_aperture_start >> 58)); 1722 sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, 1723 (adev->gmc.shared_aperture_start >> 48)); 1724 1725 mutex_lock(&adev->srbm_mutex); 1726 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1727 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1728 /* CP and shaders */ 1729 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1730 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1731 1732 /* Enable trap for each kfd vmid. */ 1733 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1734 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1735 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1736 1737 /* Disable VGPR deallocation instruction for each KFD vmid. */ 1738 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG); 1739 data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1); 1740 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data); 1741 } 1742 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1743 mutex_unlock(&adev->srbm_mutex); 1744 } 1745 1746 static void gfx_v12_1_tcp_harvest(struct amdgpu_device *adev) 1747 { 1748 /* TODO: harvest feature to be added later. */ 1749 } 1750 1751 static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) 1752 { 1753 } 1754 1755 static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) 1756 { 1757 /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ 1758 mutex_lock(&adev->srbm_mutex); 1759 if (!adev->gmc.noretry) { 1760 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1761 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); 1762 } else 1763 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1764 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); 1765 mutex_unlock(&adev->srbm_mutex); 1766 } 1767 1768 static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, 1769 int xcc_id) 1770 { 1771 u32 tmp; 1772 int i; 1773 1774 /* XXX SH_MEM regs */ 1775 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1776 mutex_lock(&adev->srbm_mutex); 1777 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1778 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1779 /* CP and shaders */ 1780 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1781 regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1782 if (i != 0) { 1783 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1784 (adev->gmc.private_aperture_start >> 58)); 1785 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1786 (adev->gmc.shared_aperture_start >> 48)); 1787 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); 1788 } 1789 } 1790 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1791 1792 mutex_unlock(&adev->srbm_mutex); 1793 1794 gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); 1795 gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); 1796 1797 } 1798 1799 static void gfx_v12_1_constants_init(struct amdgpu_device *adev) 1800 { 1801 int i, num_xcc; 1802 1803 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1804 1805 gfx_v12_1_setup_rb(adev); 1806 gfx_v12_1_get_cu_info(adev, &adev->gfx.cu_info); 1807 gfx_v12_1_get_tcc_info(adev); 1808 adev->gfx.config.pa_sc_tile_steering_override = 0; 1809 1810 for (i = 0; i < num_xcc; i++) 1811 gfx_v12_1_xcc_constants_init(adev, i); 1812 } 1813 1814 static void gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1815 bool enable, int xcc_id) 1816 { 1817 u32 tmp; 1818 1819 if (amdgpu_sriov_vf(adev)) 1820 return; 1821 1822 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1823 1824 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1825 enable ? 1 : 0); 1826 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1827 enable ? 1 : 0); 1828 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1829 enable ? 1 : 0); 1830 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1831 enable ? 1 : 0); 1832 1833 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1834 } 1835 1836 static int gfx_v12_1_xcc_init_csb(struct amdgpu_device *adev, 1837 int xcc_id) 1838 { 1839 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1840 1841 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI, 1842 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1843 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO, 1844 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1845 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1846 regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1847 1848 return 0; 1849 } 1850 1851 static void gfx_v12_1_xcc_rlc_stop(struct amdgpu_device *adev, 1852 int xcc_id) 1853 { 1854 u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); 1855 1856 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1857 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); 1858 } 1859 1860 static void gfx_v12_1_rlc_stop(struct amdgpu_device *adev) 1861 { 1862 int i, num_xcc; 1863 1864 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1865 for (i = 0; i < num_xcc; i++) 1866 gfx_v12_1_xcc_rlc_stop(adev, i); 1867 } 1868 1869 static void gfx_v12_1_xcc_rlc_reset(struct amdgpu_device *adev, 1870 int xcc_id) 1871 { 1872 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1873 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1874 udelay(50); 1875 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1876 GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1877 udelay(50); 1878 } 1879 1880 static void gfx_v12_1_rlc_reset(struct amdgpu_device *adev) 1881 { 1882 int i, num_xcc; 1883 1884 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1885 for (i = 0; i < num_xcc; i++) 1886 gfx_v12_1_xcc_rlc_reset(adev, i); 1887 } 1888 1889 static void gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1890 bool enable, int xcc_id) 1891 { 1892 uint32_t rlc_pg_cntl; 1893 1894 rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL); 1895 1896 if (!enable) { 1897 /* RLC_PG_CNTL[23] = 0 (default) 1898 * RLC will wait for handshake acks with SMU 1899 * GFXOFF will be enabled 1900 * RLC_PG_CNTL[23] = 1 1901 * RLC will not issue any message to SMU 1902 * hence no handshake between SMU & RLC 1903 * GFXOFF will be disabled 1904 */ 1905 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1906 } else 1907 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1908 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl); 1909 } 1910 1911 static void gfx_v12_1_xcc_rlc_start(struct amdgpu_device *adev, 1912 int xcc_id) 1913 { 1914 /* TODO: enable rlc & smu handshake until smu 1915 * and gfxoff feature works as expected */ 1916 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1917 gfx_v12_1_xcc_rlc_smu_handshake_cntl(adev, false, xcc_id); 1918 1919 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); 1920 udelay(50); 1921 } 1922 1923 static void gfx_v12_1_rlc_start(struct amdgpu_device *adev) 1924 { 1925 int i, num_xcc; 1926 1927 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1928 for (i = 0; i < num_xcc; i++) { 1929 gfx_v12_1_xcc_rlc_start(adev, i); 1930 } 1931 } 1932 1933 static void gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device *adev, 1934 int xcc_id) 1935 { 1936 uint32_t tmp; 1937 1938 /* enable Save Restore Machine */ 1939 tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL)); 1940 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1941 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1942 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp); 1943 } 1944 1945 static void gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device *adev, 1946 int xcc_id) 1947 { 1948 const struct rlc_firmware_header_v2_0 *hdr; 1949 const __le32 *fw_data; 1950 unsigned i, fw_size; 1951 1952 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1953 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1954 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1955 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1956 1957 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1958 RLCG_UCODE_LOADING_START_ADDRESS); 1959 1960 for (i = 0; i < fw_size; i++) 1961 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1962 regRLC_GPM_UCODE_DATA, 1963 le32_to_cpup(fw_data++)); 1964 1965 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1966 regRLC_GPM_UCODE_ADDR, 1967 adev->gfx.rlc_fw_version); 1968 } 1969 1970 static void gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device *adev, 1971 int xcc_id) 1972 { 1973 const struct rlc_firmware_header_v2_2 *hdr; 1974 const __le32 *fw_data; 1975 unsigned i, fw_size; 1976 u32 tmp; 1977 1978 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1979 1980 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1981 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1982 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1983 1984 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0); 1985 1986 for (i = 0; i < fw_size; i++) { 1987 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1988 msleep(1); 1989 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1990 regRLC_LX6_IRAM_DATA, 1991 le32_to_cpup(fw_data++)); 1992 } 1993 1994 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1995 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1996 1997 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1998 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1999 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2000 2001 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2002 regRLC_LX6_DRAM_ADDR, 0); 2003 for (i = 0; i < fw_size; i++) { 2004 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2005 msleep(1); 2006 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2007 regRLC_LX6_DRAM_DATA, 2008 le32_to_cpup(fw_data++)); 2009 } 2010 2011 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2012 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2013 2014 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL); 2015 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2016 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2017 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp); 2018 } 2019 2020 static int gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device *adev, 2021 int xcc_id) 2022 { 2023 const struct rlc_firmware_header_v2_0 *hdr; 2024 uint16_t version_major; 2025 uint16_t version_minor; 2026 2027 if (!adev->gfx.rlc_fw) 2028 return -EINVAL; 2029 2030 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2031 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2032 2033 version_major = le16_to_cpu(hdr->header.header_version_major); 2034 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2035 2036 if (version_major == 2) { 2037 gfx_v12_1_xcc_load_rlcg_microcode(adev, xcc_id); 2038 if (amdgpu_dpm == 1) { 2039 if (version_minor >= 2) 2040 gfx_v12_1_xcc_load_rlc_iram_dram_microcode(adev, xcc_id); 2041 } 2042 2043 return 0; 2044 } 2045 2046 return -EINVAL; 2047 } 2048 2049 static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, 2050 int xcc_id) 2051 { 2052 int r; 2053 2054 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2055 gfx_v12_1_xcc_init_csb(adev, xcc_id); 2056 2057 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2058 gfx_v12_1_xcc_rlc_enable_srm(adev, xcc_id); 2059 } else { 2060 if (amdgpu_sriov_vf(adev)) { 2061 gfx_v12_1_xcc_init_csb(adev, xcc_id); 2062 return 0; 2063 } 2064 2065 gfx_v12_1_xcc_rlc_stop(adev, xcc_id); 2066 2067 /* disable CG */ 2068 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 2069 2070 /* disable PG */ 2071 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0); 2072 2073 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2074 /* legacy rlc firmware loading */ 2075 r = gfx_v12_1_xcc_rlc_load_microcode(adev, xcc_id); 2076 if (r) 2077 return r; 2078 } 2079 2080 gfx_v12_1_xcc_init_csb(adev, xcc_id); 2081 2082 gfx_v12_1_xcc_rlc_start(adev, xcc_id); 2083 } 2084 2085 return 0; 2086 } 2087 2088 static int gfx_v12_1_rlc_resume(struct amdgpu_device *adev) 2089 { 2090 int r, i, num_xcc; 2091 2092 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2093 for (i = 0; i < num_xcc; i++) { 2094 r = gfx_v12_1_xcc_rlc_resume(adev, i); 2095 if (r) 2096 return r; 2097 } 2098 2099 return 0; 2100 } 2101 2102 static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, 2103 int xcc_id) 2104 { 2105 const struct gfx_firmware_header_v2_0 *mec_hdr; 2106 uint32_t pipe_id, tmp; 2107 2108 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2109 adev->gfx.mec_fw->data; 2110 2111 /* config mec program start addr */ 2112 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2113 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 2114 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 2115 mec_hdr->ucode_start_addr_lo >> 2 | 2116 mec_hdr->ucode_start_addr_hi << 30); 2117 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2118 mec_hdr->ucode_start_addr_hi >> 2); 2119 } 2120 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2121 2122 /* reset mec pipe */ 2123 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 2124 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2125 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2126 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2127 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2128 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 2129 2130 /* clear mec pipe reset */ 2131 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2132 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2133 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2134 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2135 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 2136 } 2137 2138 static void gfx_v12_1_config_gfx_rs64(struct amdgpu_device *adev) 2139 { 2140 int i, num_xcc; 2141 2142 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2143 2144 for (i = 0; i < num_xcc; i++) 2145 gfx_v12_1_xcc_config_gfx_rs64(adev, i); 2146 } 2147 2148 static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, 2149 int xcc_id) 2150 { 2151 const struct gfx_firmware_header_v2_0 *cp_hdr; 2152 unsigned pipe_id; 2153 2154 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2155 adev->gfx.mec_fw->data; 2156 mutex_lock(&adev->srbm_mutex); 2157 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2158 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 2159 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 2160 cp_hdr->ucode_start_addr_lo >> 2 | 2161 cp_hdr->ucode_start_addr_hi << 30); 2162 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2163 cp_hdr->ucode_start_addr_hi >> 2); 2164 } 2165 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2166 mutex_unlock(&adev->srbm_mutex); 2167 } 2168 2169 static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev, 2170 int xcc_id) 2171 { 2172 uint32_t cp_status; 2173 uint32_t bootload_status; 2174 int i; 2175 2176 for (i = 0; i < adev->usec_timeout; i++) { 2177 cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT); 2178 bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2179 regRLC_RLCS_BOOTLOAD_STATUS); 2180 2181 if ((cp_status == 0) && 2182 (REG_GET_FIELD(bootload_status, 2183 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2184 break; 2185 } 2186 udelay(1); 2187 if (amdgpu_emu_mode) 2188 msleep(10); 2189 } 2190 2191 if (i >= adev->usec_timeout) { 2192 dev_err(adev->dev, 2193 "rlc autoload: xcc%d gc ucode autoload timeout\n", xcc_id); 2194 return -ETIMEDOUT; 2195 } 2196 2197 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2198 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2199 } 2200 2201 return 0; 2202 } 2203 2204 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2205 { 2206 int xcc_id; 2207 2208 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) 2209 gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id); 2210 2211 return 0; 2212 } 2213 2214 static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, 2215 bool enable, int xcc_id) 2216 { 2217 u32 data; 2218 2219 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 2220 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2221 enable ? 0 : 1); 2222 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2223 enable ? 0 : 1); 2224 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2225 enable ? 0 : 1); 2226 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2227 enable ? 0 : 1); 2228 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2229 enable ? 0 : 1); 2230 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2231 enable ? 1 : 0); 2232 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2233 enable ? 1 : 0); 2234 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2235 enable ? 1 : 0); 2236 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2237 enable ? 1 : 0); 2238 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2239 enable ? 0 : 1); 2240 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); 2241 2242 adev->gfx.kiq[xcc_id].ring.sched.ready = enable; 2243 2244 udelay(50); 2245 } 2246 2247 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev) 2248 { 2249 const struct gfx_firmware_header_v2_0 *mec_hdr; 2250 const __le32 *fw_ucode, *fw_data; 2251 u32 fw_ucode_size, fw_data_size; 2252 u32 *fw_ucode_ptr, *fw_data_ptr; 2253 int i, r, xcc_id; 2254 2255 if (!adev->gfx.mec_fw) 2256 return -EINVAL; 2257 2258 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2259 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2260 2261 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2262 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2263 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2264 2265 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2266 le32_to_cpu(mec_hdr->data_offset_bytes)); 2267 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2268 2269 if (adev->gfx.mec.mec_fw_obj == NULL) { 2270 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2271 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2272 &adev->gfx.mec.mec_fw_obj, 2273 &adev->gfx.mec.mec_fw_gpu_addr, 2274 (void **)&fw_ucode_ptr); 2275 if (r) { 2276 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2277 gfx_v12_1_mec_fini(adev); 2278 return r; 2279 } 2280 2281 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2282 2283 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2284 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2285 } 2286 2287 if (adev->gfx.mec.mec_fw_data_obj == NULL) { 2288 r = amdgpu_bo_create_reserved(adev, 2289 ALIGN(fw_data_size, 64 * 1024) * 2290 adev->gfx.mec.num_pipe_per_mec * NUM_XCC(adev->gfx.xcc_mask), 2291 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2292 &adev->gfx.mec.mec_fw_data_obj, 2293 &adev->gfx.mec.mec_fw_data_gpu_addr, 2294 (void **)&fw_data_ptr); 2295 if (r) { 2296 dev_err(adev->dev, "(%d) failed to create mec fw data bo\n", r); 2297 gfx_v12_1_mec_fini(adev); 2298 return r; 2299 } 2300 2301 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 2302 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2303 u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2304 ALIGN(fw_data_size, 64 * 1024) / 4; 2305 memcpy(fw_data_ptr + offset, fw_data, fw_data_size); 2306 } 2307 } 2308 2309 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2310 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2311 } 2312 2313 return 0; 2314 } 2315 2316 static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, 2317 int xcc_id) 2318 { 2319 const struct gfx_firmware_header_v2_0 *mec_hdr; 2320 u32 fw_data_size; 2321 u32 tmp, i, usec_timeout = 50000; /* Wait for 50 ms */ 2322 2323 if (!adev->gfx.mec_fw) 2324 return -EINVAL; 2325 2326 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2327 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2328 2329 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2330 2331 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); 2332 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2333 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2334 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 2336 2337 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); 2338 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2339 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2340 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); 2341 2342 mutex_lock(&adev->srbm_mutex); 2343 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2344 soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); 2345 2346 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, 2347 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2348 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2349 ALIGN(fw_data_size, 64 * 1024))); 2350 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, 2351 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2352 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2353 ALIGN(fw_data_size, 64 * 1024))); 2354 2355 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 2356 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2357 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 2358 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2359 } 2360 mutex_unlock(&adev->srbm_mutex); 2361 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2362 2363 /* Trigger an invalidation of the L1 instruction caches */ 2364 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2365 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2366 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); 2367 2368 /* Wait for invalidation complete */ 2369 for (i = 0; i < usec_timeout; i++) { 2370 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2371 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2372 INVALIDATE_DCACHE_COMPLETE)) 2373 break; 2374 udelay(1); 2375 } 2376 2377 if (i >= usec_timeout) { 2378 dev_err(adev->dev, "failed to invalidate data cache\n"); 2379 return -EINVAL; 2380 } 2381 2382 /* Trigger an invalidation of the L1 instruction caches */ 2383 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2384 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2385 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); 2386 2387 /* Wait for invalidation complete */ 2388 for (i = 0; i < usec_timeout; i++) { 2389 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2390 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2391 INVALIDATE_CACHE_COMPLETE)) 2392 break; 2393 udelay(1); 2394 } 2395 2396 if (i >= usec_timeout) { 2397 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2398 return -EINVAL; 2399 } 2400 2401 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2402 2403 return 0; 2404 } 2405 2406 static void gfx_v12_1_xcc_kiq_setting(struct amdgpu_ring *ring, 2407 int xcc_id) 2408 { 2409 uint32_t tmp; 2410 struct amdgpu_device *adev = ring->adev; 2411 2412 /* tell RLC which is KIQ queue */ 2413 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2414 tmp &= 0xffffff00; 2415 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2416 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2417 tmp |= 0x80; 2418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2419 } 2420 2421 static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev, 2422 int xcc_id) 2423 { 2424 /* disable gfx engine doorbell range */ 2425 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0); 2426 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0); 2427 2428 /* set compute engine doorbell range */ 2429 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER, 2430 ((adev->doorbell_index.kiq + 2431 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2432 2) << 2); 2433 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER, 2434 ((adev->doorbell_index.userqueue_end + 2435 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2436 2) << 2); 2437 } 2438 2439 static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, 2440 struct amdgpu_mqd_prop *prop) 2441 { 2442 struct v12_1_compute_mqd *mqd = m; 2443 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2444 uint32_t tmp; 2445 2446 mqd->header = 0xC0310800; 2447 mqd->compute_pipelinestat_enable = 0x00000001; 2448 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2449 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2450 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2451 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2452 mqd->compute_misc_reserved = 0x00000007; 2453 2454 eop_base_addr = prop->eop_gpu_addr >> 8; 2455 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2456 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2457 2458 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2459 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 2460 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2461 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 2462 2463 mqd->cp_hqd_eop_control = tmp; 2464 2465 /* enable doorbell? */ 2466 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2467 2468 if (prop->use_doorbell) { 2469 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2470 DOORBELL_OFFSET, prop->doorbell_index); 2471 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2472 DOORBELL_EN, 1); 2473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2474 DOORBELL_SOURCE, 0); 2475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2476 DOORBELL_HIT, 0); 2477 } else { 2478 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2479 DOORBELL_EN, 0); 2480 } 2481 2482 mqd->cp_hqd_pq_doorbell_control = tmp; 2483 2484 /* disable the queue if it's active */ 2485 mqd->cp_hqd_dequeue_request = 0; 2486 mqd->cp_hqd_pq_rptr = 0; 2487 mqd->cp_hqd_pq_wptr_lo = 0; 2488 mqd->cp_hqd_pq_wptr_hi = 0; 2489 2490 /* set the pointer to the MQD */ 2491 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 2492 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2493 2494 /* set MQD vmid to 0 */ 2495 tmp = regCP_MQD_CONTROL_DEFAULT; 2496 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2497 mqd->cp_mqd_control = tmp; 2498 2499 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2500 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2501 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2502 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2503 2504 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2505 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 2506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2507 (order_base_2(prop->queue_size / 4) - 1)); 2508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2509 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 2510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 2512 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2514 mqd->cp_hqd_pq_control = tmp; 2515 2516 /* set the wb address whether it's enabled or not */ 2517 wb_gpu_addr = prop->rptr_gpu_addr; 2518 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2519 mqd->cp_hqd_pq_rptr_report_addr_hi = 2520 upper_32_bits(wb_gpu_addr) & 0xffff; 2521 2522 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2523 wb_gpu_addr = prop->wptr_gpu_addr; 2524 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2525 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2526 2527 tmp = 0; 2528 /* enable the doorbell if requested */ 2529 if (prop->use_doorbell) { 2530 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2532 DOORBELL_OFFSET, prop->doorbell_index); 2533 2534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2535 DOORBELL_EN, 1); 2536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2537 DOORBELL_SOURCE, 0); 2538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2539 DOORBELL_HIT, 0); 2540 } 2541 2542 mqd->cp_hqd_pq_doorbell_control = tmp; 2543 2544 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2545 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 2546 2547 /* set the vmid for the queue */ 2548 mqd->cp_hqd_vmid = 0; 2549 2550 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 2551 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63); 2552 mqd->cp_hqd_persistent_state = tmp; 2553 2554 /* set MIN_IB_AVAIL_SIZE */ 2555 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 2556 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1); 2557 mqd->cp_hqd_ib_control = tmp; 2558 2559 /* set static priority for a compute queue/ring */ 2560 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 2561 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2562 2563 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : 2564 AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); 2565 2566 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 2567 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 2568 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 2569 mqd->cp_hqd_quantum = tmp; 2570 2571 mqd->cp_hqd_active = prop->hqd_active; 2572 2573 return 0; 2574 } 2575 2576 static int gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring *ring, 2577 int xcc_id) 2578 { 2579 struct amdgpu_device *adev = ring->adev; 2580 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2581 int j; 2582 2583 /* inactivate the queue */ 2584 if (amdgpu_sriov_vf(adev)) 2585 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2586 2587 /* disable wptr polling */ 2588 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2589 2590 /* write the EOP addr */ 2591 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 2592 mqd->cp_hqd_eop_base_addr_lo); 2593 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 2594 mqd->cp_hqd_eop_base_addr_hi); 2595 2596 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2597 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 2598 mqd->cp_hqd_eop_control); 2599 2600 /* enable doorbell? */ 2601 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2602 mqd->cp_hqd_pq_doorbell_control); 2603 2604 /* disable the queue if it's active */ 2605 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2606 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2607 for (j = 0; j < adev->usec_timeout; j++) { 2608 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2609 break; 2610 udelay(1); 2611 } 2612 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2613 mqd->cp_hqd_dequeue_request); 2614 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 2615 mqd->cp_hqd_pq_rptr); 2616 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2617 mqd->cp_hqd_pq_wptr_lo); 2618 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2619 mqd->cp_hqd_pq_wptr_hi); 2620 } 2621 2622 /* set the pointer to the MQD */ 2623 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2624 mqd->cp_mqd_base_addr_lo); 2625 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2626 mqd->cp_mqd_base_addr_hi); 2627 2628 /* set MQD vmid to 0 */ 2629 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2630 mqd->cp_mqd_control); 2631 2632 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2633 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2634 mqd->cp_hqd_pq_base_lo); 2635 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2636 mqd->cp_hqd_pq_base_hi); 2637 2638 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2639 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2640 mqd->cp_hqd_pq_control); 2641 2642 /* set the wb address whether it's enabled or not */ 2643 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2644 mqd->cp_hqd_pq_rptr_report_addr_lo); 2645 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2646 mqd->cp_hqd_pq_rptr_report_addr_hi); 2647 2648 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2649 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2650 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2651 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2652 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2653 2654 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2655 mqd->cp_hqd_pq_doorbell_control); 2656 2657 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2658 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2659 mqd->cp_hqd_pq_wptr_lo); 2660 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2661 mqd->cp_hqd_pq_wptr_hi); 2662 2663 /* set the vmid for the queue */ 2664 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2665 2666 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2667 mqd->cp_hqd_persistent_state); 2668 2669 /* activate the queue */ 2670 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2671 mqd->cp_hqd_active); 2672 2673 if (ring->use_doorbell) 2674 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2675 2676 return 0; 2677 } 2678 2679 static int gfx_v12_1_xcc_kiq_init_queue(struct amdgpu_ring *ring, 2680 int xcc_id) 2681 { 2682 struct amdgpu_device *adev = ring->adev; 2683 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2684 2685 gfx_v12_1_xcc_kiq_setting(ring, xcc_id); 2686 2687 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 2688 /* reset MQD to a clean status */ 2689 if (adev->gfx.kiq[xcc_id].mqd_backup) 2690 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(*mqd)); 2691 2692 /* reset ring buffer */ 2693 ring->wptr = 0; 2694 amdgpu_ring_clear_ring(ring); 2695 2696 mutex_lock(&adev->srbm_mutex); 2697 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2698 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2699 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2700 mutex_unlock(&adev->srbm_mutex); 2701 } else { 2702 memset((void *)mqd, 0, sizeof(*mqd)); 2703 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2704 amdgpu_ring_clear_ring(ring); 2705 mutex_lock(&adev->srbm_mutex); 2706 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2707 amdgpu_ring_init_mqd(ring); 2708 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2709 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2710 mutex_unlock(&adev->srbm_mutex); 2711 2712 if (adev->gfx.kiq[xcc_id].mqd_backup) 2713 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(*mqd)); 2714 } 2715 2716 return 0; 2717 } 2718 2719 static int gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring *ring, 2720 int xcc_id) 2721 { 2722 struct amdgpu_device *adev = ring->adev; 2723 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2724 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2725 2726 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2727 memset((void *)mqd, 0, sizeof(*mqd)); 2728 mutex_lock(&adev->srbm_mutex); 2729 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2730 amdgpu_ring_init_mqd(ring); 2731 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2732 mutex_unlock(&adev->srbm_mutex); 2733 2734 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2735 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2736 } else { 2737 /* restore MQD to a clean status */ 2738 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2739 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2740 /* reset ring buffer */ 2741 ring->wptr = 0; 2742 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 2743 amdgpu_ring_clear_ring(ring); 2744 } 2745 2746 return 0; 2747 } 2748 2749 static int gfx_v12_1_xcc_kiq_resume(struct amdgpu_device *adev, 2750 int xcc_id) 2751 { 2752 struct amdgpu_ring *ring; 2753 int r; 2754 2755 ring = &adev->gfx.kiq[xcc_id].ring; 2756 2757 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2758 if (unlikely(r != 0)) 2759 return r; 2760 2761 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2762 if (unlikely(r != 0)) { 2763 amdgpu_bo_unreserve(ring->mqd_obj); 2764 return r; 2765 } 2766 2767 gfx_v12_1_xcc_kiq_init_queue(ring, xcc_id); 2768 amdgpu_bo_kunmap(ring->mqd_obj); 2769 ring->mqd_ptr = NULL; 2770 amdgpu_bo_unreserve(ring->mqd_obj); 2771 ring->sched.ready = true; 2772 return 0; 2773 } 2774 2775 static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, 2776 int xcc_id) 2777 { 2778 struct amdgpu_ring *ring = NULL; 2779 int r = 0, i; 2780 2781 if (!amdgpu_async_gfx_ring) 2782 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2783 2784 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2785 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2786 2787 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2788 if (unlikely(r != 0)) 2789 goto done; 2790 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2791 if (!r) { 2792 r = gfx_v12_1_xcc_kcq_init_queue(ring, xcc_id); 2793 amdgpu_bo_kunmap(ring->mqd_obj); 2794 ring->mqd_ptr = NULL; 2795 } 2796 amdgpu_bo_unreserve(ring->mqd_obj); 2797 if (r) 2798 goto done; 2799 } 2800 2801 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2802 done: 2803 return r; 2804 } 2805 2806 static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) 2807 { 2808 int r, i, xcc_id; 2809 struct amdgpu_ring *ring; 2810 2811 for_each_inst(xcc_id, xcc_mask) { 2812 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2813 /* legacy firmware loading */ 2814 r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); 2815 if (r) 2816 return r; 2817 } 2818 2819 /* GFX CGCG and LS is set by default */ 2820 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2821 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2822 2823 gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); 2824 2825 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2826 2827 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) { 2828 r = amdgpu_mes_kiq_hw_init(adev, xcc_id); 2829 /* 2830 * With MES, GFX KIQ ring is owned by the MES and is never 2831 * initialized/used directly by the driver, so it must 2832 * not be left flagged as ready. mes_v12_0_hw_init() clears 2833 * but clear here if MES init fails 2834 */ 2835 if (r) 2836 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 2837 } else { 2838 r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); 2839 } 2840 if (r) 2841 return r; 2842 2843 r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); 2844 if (r) 2845 return r; 2846 2847 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2848 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2849 r = amdgpu_ring_test_helper(ring); 2850 if (r) 2851 return r; 2852 } 2853 } 2854 2855 return 0; 2856 } 2857 2858 static int gfx_v12_1_cp_resume(struct amdgpu_device *adev) 2859 { 2860 int num_xcc, num_xcp, num_xcc_per_xcp; 2861 uint16_t xcc_mask; 2862 int r = 0; 2863 2864 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2865 if (amdgpu_sriov_vf(adev)) { 2866 enum amdgpu_gfx_partition mode; 2867 2868 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2869 AMDGPU_XCP_FL_NONE); 2870 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2871 return -EINVAL; 2872 if (adev->gfx.funcs && 2873 adev->gfx.funcs->get_xccs_per_xcp) { 2874 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 2875 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2876 num_xcp = num_xcc / num_xcc_per_xcp; 2877 } else { 2878 return -EINVAL; 2879 } 2880 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2881 2882 } else { 2883 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2884 AMDGPU_XCP_FL_NONE) == 2885 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2886 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2887 amdgpu_user_partt_mode); 2888 } 2889 2890 if (r) 2891 return r; 2892 2893 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 2894 2895 return gfx_v12_1_xcc_cp_resume(adev, xcc_mask); 2896 } 2897 2898 static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev) 2899 { 2900 int r, i; 2901 bool value; 2902 2903 r = adev->gfxhub.funcs->gart_enable(adev); 2904 if (r) 2905 return r; 2906 2907 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 2908 false : true; 2909 2910 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2911 /* TODO investigate why TLB flush is needed, 2912 * are we missing a flush somewhere else? */ 2913 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2914 if (AMDGPU_IS_GFXHUB(i)) 2915 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0); 2916 } 2917 2918 return 0; 2919 } 2920 2921 static int get_gb_addr_config(struct amdgpu_device *adev) 2922 { 2923 u32 gb_addr_config; 2924 2925 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ); 2926 if (gb_addr_config == 0) 2927 return -EINVAL; 2928 2929 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2930 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG_READ, NUM_PKRS); 2931 2932 adev->gfx.config.gb_addr_config = gb_addr_config; 2933 2934 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2935 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2936 GB_ADDR_CONFIG_READ, NUM_PIPES); 2937 2938 adev->gfx.config.max_tile_pipes = 2939 adev->gfx.config.gb_addr_config_fields.num_pipes; 2940 2941 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2942 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2943 GB_ADDR_CONFIG_READ, MAX_COMPRESSED_FRAGS); 2944 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2945 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2946 GB_ADDR_CONFIG_READ, NUM_RB_PER_SE); 2947 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2948 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2949 GB_ADDR_CONFIG_READ, NUM_SHADER_ENGINES); 2950 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2951 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2952 GB_ADDR_CONFIG_READ, PIPE_INTERLEAVE_SIZE)); 2953 2954 return 0; 2955 } 2956 2957 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, 2958 int xcc_id) 2959 { 2960 uint32_t data; 2961 2962 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 2963 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 2964 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 2965 2966 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG); 2967 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 2968 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); 2969 } 2970 2971 static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, 2972 int xcc_id) 2973 { 2974 uint32_t data; 2975 2976 /* Set the TCP UTCL0 register to enable atomics */ 2977 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); 2978 data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); 2979 2980 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); 2981 } 2982 2983 static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, 2984 int xcc_id) 2985 { 2986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); 2987 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); 2988 } 2989 2990 static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, 2991 int xcc_id) 2992 { 2993 uint32_t data; 2994 2995 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3); 2996 data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1); 2997 2998 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); 2999 } 3000 3001 static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, 3002 int xcc_id) 3003 { 3004 uint32_t data; 3005 3006 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); 3007 data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); 3008 3009 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); 3010 } 3011 3012 static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) 3013 { 3014 int i; 3015 3016 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { 3017 gfx_v12_1_xcc_disable_burst(adev, i); 3018 gfx_v12_1_xcc_enable_atomics(adev, i); 3019 gfx_v12_1_xcc_disable_early_write_ack(adev, i); 3020 gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); 3021 } 3022 } 3023 3024 static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, 3025 bool enable) 3026 { 3027 unsigned int irq_type; 3028 int m, p, r; 3029 3030 if (!adev->gfx.disable_kq) 3031 return 0; 3032 3033 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3034 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3035 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3036 + (m * adev->gfx.mec.num_pipe_per_mec) 3037 + p; 3038 if (enable) 3039 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3040 else 3041 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3042 if (r) { 3043 if (!enable) 3044 return r; 3045 goto err_unwind; 3046 } 3047 } 3048 } 3049 3050 return 0; 3051 3052 err_unwind: 3053 for (p--; p >= 0; p--) { 3054 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3055 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3056 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3057 } 3058 for (m--; m >= 0; m--) { 3059 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 3060 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3061 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3062 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3063 } 3064 } 3065 return r; 3066 } 3067 3068 static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 3069 { 3070 int r, i, num_xcc; 3071 struct amdgpu_device *adev = ip_block->adev; 3072 3073 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3074 /* rlc autoload firmware */ 3075 r = gfx_v12_1_rlc_backdoor_autoload_enable(adev); 3076 if (r) 3077 return r; 3078 } else { 3079 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3080 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3081 3082 if (adev->gfx.imu.funcs) { 3083 if (adev->gfx.imu.funcs->load_microcode) 3084 adev->gfx.imu.funcs->load_microcode(adev); 3085 } 3086 3087 for (i = 0; i < num_xcc; i++) { 3088 /* disable gpa mode in backdoor loading */ 3089 gfx_v12_1_xcc_disable_gpa_mode(adev, i); 3090 } 3091 } 3092 } 3093 3094 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3095 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3096 r = gfx_v12_1_wait_for_rlc_autoload_complete(adev); 3097 if (r) { 3098 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3099 return r; 3100 } 3101 } 3102 3103 adev->gfx.is_poweron = true; 3104 3105 if (get_gb_addr_config(adev)) 3106 DRM_WARN("Invalid gb_addr_config !\n"); 3107 3108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3109 gfx_v12_1_config_gfx_rs64(adev); 3110 3111 r = gfx_v12_1_gfxhub_enable(adev); 3112 if (r) 3113 return r; 3114 3115 gfx_v12_1_init_golden_registers(adev); 3116 3117 gfx_v12_1_constants_init(adev); 3118 3119 if (adev->nbio.funcs->gc_doorbell_init) 3120 adev->nbio.funcs->gc_doorbell_init(adev); 3121 3122 r = gfx_v12_1_rlc_resume(adev); 3123 if (r) 3124 return r; 3125 3126 /* 3127 * init golden registers and rlc resume may override some registers, 3128 * reconfig them here 3129 */ 3130 gfx_v12_1_tcp_harvest(adev); 3131 3132 r = gfx_v12_1_cp_resume(adev); 3133 if (r) 3134 return r; 3135 3136 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3137 if (r) 3138 return r; 3139 3140 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3141 if (r) 3142 goto err_priv_inst; 3143 3144 r = gfx_v12_1_set_userq_eop_interrupts(adev, true); 3145 if (r) 3146 goto err_userq_eop; 3147 3148 return 0; 3149 3150 err_userq_eop: 3151 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3152 err_priv_inst: 3153 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3154 return r; 3155 } 3156 3157 static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, 3158 int xcc_id) 3159 { 3160 uint32_t tmp; 3161 3162 if (!adev->no_hw_access) { 3163 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 3164 DRM_ERROR("KCQ disable failed\n"); 3165 3166 amdgpu_mes_kiq_hw_fini(adev, xcc_id); 3167 } 3168 3169 if (amdgpu_sriov_vf(adev)) { 3170 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3171 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 3172 tmp &= 0xffffff00; 3173 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 3174 } 3175 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 3176 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 3177 } 3178 3179 static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 3180 { 3181 struct amdgpu_device *adev = ip_block->adev; 3182 int i, num_xcc; 3183 3184 gfx_v12_1_set_userq_eop_interrupts(adev, false); 3185 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3186 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3187 3188 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3189 for (i = 0; i < num_xcc; i++) { 3190 gfx_v12_1_xcc_fini(adev, i); 3191 } 3192 3193 adev->gfxhub.funcs->gart_disable(adev); 3194 3195 adev->gfx.is_poweron = false; 3196 3197 return 0; 3198 } 3199 3200 static int gfx_v12_1_suspend(struct amdgpu_ip_block *ip_block) 3201 { 3202 return gfx_v12_1_hw_fini(ip_block); 3203 } 3204 3205 static int gfx_v12_1_resume(struct amdgpu_ip_block *ip_block) 3206 { 3207 return gfx_v12_1_hw_init(ip_block); 3208 } 3209 3210 static bool gfx_v12_1_is_idle(struct amdgpu_ip_block *ip_block) 3211 { 3212 struct amdgpu_device *adev = ip_block->adev; 3213 int i, num_xcc; 3214 3215 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3216 for (i = 0; i < num_xcc; i++) { 3217 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), 3218 regGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 3219 return false; 3220 } 3221 return true; 3222 } 3223 3224 static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 3225 { 3226 unsigned i; 3227 struct amdgpu_device *adev = ip_block->adev; 3228 3229 for (i = 0; i < adev->usec_timeout; i++) { 3230 if (gfx_v12_1_is_idle(ip_block)) 3231 return 0; 3232 udelay(1); 3233 } 3234 return -ETIMEDOUT; 3235 } 3236 3237 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) 3238 { 3239 uint64_t clock = 0; 3240 3241 if (adev->smuio.funcs && 3242 adev->smuio.funcs->get_gpu_clock_counter) 3243 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3244 else 3245 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3246 3247 return clock; 3248 } 3249 3250 static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) 3251 { 3252 struct amdgpu_device *adev = ip_block->adev; 3253 3254 3255 switch (amdgpu_user_queue) { 3256 case -1: 3257 default: 3258 adev->gfx.disable_kq = true; 3259 adev->gfx.disable_uq = true; 3260 break; 3261 case 0: 3262 adev->gfx.disable_kq = false; 3263 adev->gfx.disable_uq = true; 3264 break; 3265 } 3266 3267 adev->gfx.funcs = &gfx_v12_1_gfx_funcs; 3268 3269 if (adev->gfx.disable_kq) 3270 adev->gfx.num_compute_rings = 0; 3271 else 3272 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3273 AMDGPU_MAX_COMPUTE_RINGS); 3274 3275 gfx_v12_1_set_kiq_pm4_funcs(adev); 3276 gfx_v12_1_set_ring_funcs(adev); 3277 gfx_v12_1_set_irq_funcs(adev); 3278 gfx_v12_1_set_rlc_funcs(adev); 3279 gfx_v12_1_set_mqd_funcs(adev); 3280 gfx_v12_1_set_imu_funcs(adev); 3281 3282 gfx_v12_1_init_rlcg_reg_access_ctrl(adev); 3283 3284 amdgpu_init_rlc_reg_funcs(adev); 3285 3286 return gfx_v12_1_init_microcode(adev); 3287 } 3288 3289 static bool gfx_v12_1_is_rlc_enabled(struct amdgpu_device *adev) 3290 { 3291 uint32_t rlc_cntl; 3292 3293 /* if RLC is not enabled, do nothing */ 3294 rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 3295 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3296 } 3297 3298 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, 3299 int xcc_id) 3300 { 3301 uint32_t data; 3302 unsigned i; 3303 3304 data = RLC_SAFE_MODE__CMD_MASK; 3305 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3306 3307 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 3308 3309 /* wait for RLC_SAFE_MODE */ 3310 for (i = 0; i < adev->usec_timeout; i++) { 3311 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3312 regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3313 break; 3314 udelay(1); 3315 } 3316 } 3317 3318 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, 3319 int xcc_id) 3320 { 3321 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3322 regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3323 } 3324 3325 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 3326 bool enable) 3327 { 3328 int i, num_xcc; 3329 3330 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3331 for (i = 0; i < num_xcc; i++) 3332 gfx_v12_1_xcc_update_perf_clk(adev, enable, i); 3333 } 3334 3335 static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, 3336 int xcc_id, 3337 struct amdgpu_ring *ring, 3338 unsigned vmid) 3339 { 3340 u32 reg, data; 3341 3342 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3343 if (amdgpu_sriov_is_pp_one_vf(adev)) 3344 data = RREG32_NO_KIQ(reg); 3345 else 3346 data = RREG32(reg); 3347 3348 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3349 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3350 3351 if (amdgpu_sriov_is_pp_one_vf(adev)) 3352 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3353 else 3354 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3355 3356 if (ring 3357 && amdgpu_sriov_is_pp_one_vf(adev) 3358 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3359 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3360 uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3361 amdgpu_ring_emit_wreg(ring, reg, data); 3362 } 3363 } 3364 3365 static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = { 3366 .is_rlc_enabled = gfx_v12_1_is_rlc_enabled, 3367 .set_safe_mode = gfx_v12_1_xcc_set_safe_mode, 3368 .unset_safe_mode = gfx_v12_1_xcc_unset_safe_mode, 3369 .init = gfx_v12_1_rlc_init, 3370 .get_csb_size = gfx_v12_1_get_csb_size, 3371 .get_csb_buffer = gfx_v12_1_get_csb_buffer, 3372 .resume = gfx_v12_1_rlc_resume, 3373 .stop = gfx_v12_1_rlc_stop, 3374 .reset = gfx_v12_1_rlc_reset, 3375 .start = gfx_v12_1_rlc_start, 3376 .update_spm_vmid = gfx_v12_1_update_spm_vmid, 3377 }; 3378 3379 #if 0 3380 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3381 { 3382 /* TODO */ 3383 } 3384 3385 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3386 { 3387 /* TODO */ 3388 } 3389 #endif 3390 3391 static int gfx_v12_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 3392 enum amd_powergating_state state) 3393 { 3394 struct amdgpu_device *adev = ip_block->adev; 3395 bool enable = (state == AMD_PG_STATE_GATE); 3396 3397 if (amdgpu_sriov_vf(adev)) 3398 return 0; 3399 3400 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3401 case IP_VERSION(12, 1, 0): 3402 amdgpu_gfx_off_ctrl(adev, enable); 3403 break; 3404 default: 3405 break; 3406 } 3407 3408 return 0; 3409 } 3410 3411 static void gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3412 bool enable, int xcc_id) 3413 { 3414 uint32_t def, data; 3415 3416 if (!(adev->cg_flags & 3417 (AMD_CG_SUPPORT_GFX_CGCG | 3418 AMD_CG_SUPPORT_GFX_CGLS | 3419 AMD_CG_SUPPORT_GFX_3D_CGCG | 3420 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3421 return; 3422 3423 if (enable) { 3424 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3425 regRLC_CGTT_MGCG_OVERRIDE); 3426 3427 /* unset CGCG override */ 3428 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3429 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3430 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3431 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3432 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3433 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3434 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3435 3436 /* update CGCG override bits */ 3437 if (def != data) 3438 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3439 regRLC_CGTT_MGCG_OVERRIDE, data); 3440 3441 /* enable cgcg FSM(0x0000363F) */ 3442 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3443 3444 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3445 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3446 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3447 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3448 } 3449 3450 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3451 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3452 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3453 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3454 } 3455 3456 if (def != data) 3457 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3458 regRLC_CGCG_CGLS_CTRL, data); 3459 3460 /* set IDLE_POLL_COUNT(0x00900100) */ 3461 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 3462 3463 data &= ~CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK; 3464 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3465 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3466 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3467 3468 if (def != data) 3469 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 3470 3471 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL); 3472 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3473 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3474 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3475 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3476 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data); 3477 } else { 3478 /* Program RLC_CGCG_CGLS_CTRL */ 3479 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3480 3481 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3482 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3483 3484 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3485 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3486 3487 if (def != data) 3488 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 3489 } 3490 } 3491 3492 static void gfx_v12_1_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3493 bool enable, int xcc_id) 3494 { 3495 uint32_t data, def; 3496 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 3497 return; 3498 3499 /* It is disabled by HW by default */ 3500 if (enable) { 3501 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3502 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3503 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3504 3505 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3506 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3507 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3508 3509 if (def != data) 3510 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3511 } 3512 } else { 3513 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3514 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3515 3516 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3517 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3518 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3519 3520 if (def != data) 3521 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3522 } 3523 } 3524 } 3525 3526 static void gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 3527 bool enable, int xcc_id) 3528 { 3529 uint32_t def, data; 3530 3531 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 3532 return; 3533 3534 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3535 3536 if (enable) 3537 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3538 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 3539 else 3540 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3541 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 3542 3543 if (def != data) 3544 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3545 } 3546 3547 static void gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device *adev, 3548 bool enable, int xcc_id) 3549 { 3550 uint32_t def, data; 3551 3552 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 3553 return; 3554 3555 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3556 3557 if (enable) 3558 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3559 else 3560 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3561 3562 if (def != data) 3563 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3564 } 3565 3566 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 3567 bool enable, int xcc_id) 3568 { 3569 uint32_t def, data; 3570 3571 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3572 return; 3573 3574 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3575 3576 if (enable) 3577 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3578 else 3579 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3580 3581 if (def != data) 3582 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3583 } 3584 3585 static int gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 3586 bool enable, int xcc_id) 3587 { 3588 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3589 3590 gfx_v12_1_xcc_update_coarse_grain_clock_gating(adev, enable, xcc_id); 3591 3592 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, enable, xcc_id); 3593 3594 gfx_v12_1_xcc_update_repeater_fgcg(adev, enable, xcc_id); 3595 3596 gfx_v12_1_xcc_update_sram_fgcg(adev, enable, xcc_id); 3597 3598 gfx_v12_1_xcc_update_perf_clk(adev, enable, xcc_id); 3599 3600 if (adev->cg_flags & 3601 (AMD_CG_SUPPORT_GFX_MGCG | 3602 AMD_CG_SUPPORT_GFX_CGLS | 3603 AMD_CG_SUPPORT_GFX_CGCG | 3604 AMD_CG_SUPPORT_GFX_3D_CGCG | 3605 AMD_CG_SUPPORT_GFX_3D_CGLS)) 3606 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, enable, xcc_id); 3607 3608 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 3609 3610 return 0; 3611 } 3612 3613 static int gfx_v12_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3614 enum amd_clockgating_state state) 3615 { 3616 struct amdgpu_device *adev = ip_block->adev; 3617 int i, num_xcc; 3618 3619 if (amdgpu_sriov_vf(adev)) 3620 return 0; 3621 3622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3623 switch (adev->ip_versions[GC_HWIP][0]) { 3624 case IP_VERSION(12, 1, 0): 3625 for (i = 0; i < num_xcc; i++) 3626 gfx_v12_1_xcc_update_gfx_clock_gating(adev, 3627 state == AMD_CG_STATE_GATE, i); 3628 break; 3629 default: 3630 break; 3631 } 3632 3633 return 0; 3634 } 3635 3636 static void gfx_v12_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 3637 { 3638 struct amdgpu_device *adev = ip_block->adev; 3639 int data; 3640 3641 /* AMD_CG_SUPPORT_GFX_MGCG */ 3642 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE); 3643 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3644 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3645 3646 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 3647 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 3648 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 3649 3650 /* AMD_CG_SUPPORT_GFX_FGCG */ 3651 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 3652 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 3653 3654 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 3655 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 3656 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 3657 3658 /* AMD_CG_SUPPORT_GFX_CGCG */ 3659 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); 3660 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3661 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3662 3663 /* AMD_CG_SUPPORT_GFX_CGLS */ 3664 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3665 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3666 } 3667 3668 static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring) 3669 { 3670 /* gfx12 hardware is 32bit rptr */ 3671 return *(uint32_t *)ring->rptr_cpu_addr; 3672 } 3673 3674 static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring) 3675 { 3676 u64 wptr; 3677 3678 /* XXX check if swapping is necessary on BE */ 3679 if (ring->use_doorbell) 3680 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3681 else 3682 BUG(); 3683 return wptr; 3684 } 3685 3686 static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring) 3687 { 3688 struct amdgpu_device *adev = ring->adev; 3689 3690 /* XXX check if swapping is necessary on BE */ 3691 if (ring->use_doorbell) { 3692 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 3693 ring->wptr); 3694 WDOORBELL64(ring->doorbell_index, ring->wptr); 3695 } else { 3696 BUG(); /* only DOORBELL method supported on gfx12 now */ 3697 } 3698 } 3699 3700 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, 3701 struct amdgpu_job *job, 3702 struct amdgpu_ib *ib, 3703 uint32_t flags) 3704 { 3705 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3706 u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); 3707 3708 /* Currently, there is a high possibility to get wave ID mismatch 3709 * between ME and GDS, leading to a hw deadlock, because ME generates 3710 * different wave IDs than the GDS expects. This situation happens 3711 * randomly when at least 5 compute pipes use GDS ordered append. 3712 * The wave IDs generated by ME are also wrong after suspend/resume. 3713 * Those are probably bugs somewhere else in the kernel driver. 3714 * 3715 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 3716 * GDS to 0 for this ring (me/pipe). 3717 */ 3718 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 3719 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3720 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 3721 } 3722 3723 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3724 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 3725 amdgpu_ring_write(ring, 3726 #ifdef __BIG_ENDIAN 3727 (2 << 0) | 3728 #endif 3729 lower_32_bits(ib->gpu_addr)); 3730 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3731 amdgpu_ring_write(ring, control); 3732 } 3733 3734 static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3735 u64 seq, unsigned flags) 3736 { 3737 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3738 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3739 3740 /* RELEASE_MEM - flush caches, send int */ 3741 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3742 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | 3743 PACKET3_RELEASE_MEM__GCR_GLV_WB | 3744 PACKET3_RELEASE_MEM__GCR_GL2_WB | 3745 PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | 3746 PACKET3_RELEASE_MEM__TEMPORAL(3) | 3747 PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3748 PACKET3_RELEASE_MEM__EVENT_INDEX(5))); 3749 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | 3750 PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); 3751 3752 /* 3753 * the address should be Qword aligned if 64bit write, Dword 3754 * aligned if only send 32bit data low (discard data high) 3755 */ 3756 if (write64bit) 3757 WARN_ON(addr & 0x7); 3758 else 3759 WARN_ON(addr & 0x3); 3760 amdgpu_ring_write(ring, lower_32_bits(addr)); 3761 amdgpu_ring_write(ring, upper_32_bits(addr)); 3762 amdgpu_ring_write(ring, lower_32_bits(seq)); 3763 amdgpu_ring_write(ring, upper_32_bits(seq)); 3764 amdgpu_ring_write(ring, 0); 3765 } 3766 3767 static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3768 { 3769 uint32_t seq = ring->fence_drv.sync_seq; 3770 uint64_t addr = ring->fence_drv.gpu_addr; 3771 3772 gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), 3773 upper_32_bits(addr), seq, 0xffffffff, 4); 3774 } 3775 3776 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3777 uint16_t pasid, uint32_t flush_type, 3778 bool all_hub, uint8_t dst_sel) 3779 { 3780 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3781 amdgpu_ring_write(ring, 3782 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 3783 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3784 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3785 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3786 } 3787 3788 static void gfx_v12_1_ring_emit_vm_flush(struct amdgpu_ring *ring, 3789 unsigned vmid, uint64_t pd_addr) 3790 { 3791 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3792 3793 /* compute doesn't have PFP */ 3794 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 3795 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3796 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3797 amdgpu_ring_write(ring, 0x0); 3798 } 3799 } 3800 3801 static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3802 u64 seq, unsigned int flags) 3803 { 3804 struct amdgpu_device *adev = ring->adev; 3805 3806 /* write fence seq to the "addr" */ 3807 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3808 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3809 amdgpu_ring_write(ring, lower_32_bits(addr)); 3810 amdgpu_ring_write(ring, upper_32_bits(addr)); 3811 amdgpu_ring_write(ring, lower_32_bits(seq)); 3812 3813 if (flags & AMDGPU_FENCE_FLAG_INT) { 3814 /* set register to trigger INT */ 3815 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3816 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3817 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3818 amdgpu_ring_write(ring, 0); 3819 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3820 } 3821 } 3822 3823 static void gfx_v12_1_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3824 uint32_t reg_val_offs) 3825 { 3826 struct amdgpu_device *adev = ring->adev; 3827 3828 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3829 3830 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3831 amdgpu_ring_write(ring, 0 | /* src: register*/ 3832 (5 << 8) | /* dst: memory */ 3833 (1 << 20)); /* write confirm */ 3834 amdgpu_ring_write(ring, reg); 3835 amdgpu_ring_write(ring, 0); 3836 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3837 reg_val_offs * 4)); 3838 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3839 reg_val_offs * 4)); 3840 } 3841 3842 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, 3843 uint32_t reg, 3844 uint32_t val) 3845 { 3846 uint32_t cmd = 0; 3847 3848 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3849 3850 switch (ring->funcs->type) { 3851 case AMDGPU_RING_TYPE_KIQ: 3852 cmd = (1 << 16); /* no inc addr */ 3853 break; 3854 default: 3855 cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1); 3856 break; 3857 } 3858 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3859 amdgpu_ring_write(ring, cmd); 3860 amdgpu_ring_write(ring, reg); 3861 amdgpu_ring_write(ring, 0); 3862 amdgpu_ring_write(ring, val); 3863 } 3864 3865 static void gfx_v12_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3866 uint32_t val, uint32_t mask) 3867 { 3868 gfx_v12_1_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3869 } 3870 3871 static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3872 uint32_t reg0, uint32_t reg1, 3873 uint32_t ref, uint32_t mask) 3874 { 3875 gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, 3876 ref, mask, 0x20); 3877 } 3878 3879 static void gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3880 int me, int pipe, 3881 enum amdgpu_interrupt_state state, 3882 int xcc_id) 3883 { 3884 u32 mec_int_cntl, mec_int_cntl_reg; 3885 3886 /* 3887 * amdgpu controls only the first MEC. That's why this function only 3888 * handles the setting of interrupts for this specific MEC. All other 3889 * pipes' interrupts are set by amdkfd. 3890 */ 3891 3892 if (me == 1) { 3893 switch (pipe) { 3894 case 0: 3895 mec_int_cntl_reg = SOC15_REG_OFFSET( 3896 GC, GET_INST(GC, xcc_id), 3897 regCP_ME1_PIPE0_INT_CNTL); 3898 break; 3899 case 1: 3900 mec_int_cntl_reg = SOC15_REG_OFFSET( 3901 GC, GET_INST(GC, xcc_id), 3902 regCP_ME1_PIPE1_INT_CNTL); 3903 break; 3904 case 2: 3905 mec_int_cntl_reg = SOC15_REG_OFFSET( 3906 GC, GET_INST(GC, xcc_id), 3907 regCP_ME1_PIPE2_INT_CNTL); 3908 break; 3909 case 3: 3910 mec_int_cntl_reg = SOC15_REG_OFFSET( 3911 GC, GET_INST(GC, xcc_id), 3912 regCP_ME1_PIPE3_INT_CNTL); 3913 break; 3914 default: 3915 DRM_DEBUG("invalid pipe %d\n", pipe); 3916 return; 3917 } 3918 } else { 3919 DRM_DEBUG("invalid me %d\n", me); 3920 return; 3921 } 3922 3923 switch (state) { 3924 case AMDGPU_IRQ_STATE_DISABLE: 3925 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3926 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3927 TIME_STAMP_INT_ENABLE, 0); 3928 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3929 GENERIC0_INT_ENABLE, 0); 3930 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3931 break; 3932 case AMDGPU_IRQ_STATE_ENABLE: 3933 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3934 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3935 TIME_STAMP_INT_ENABLE, 1); 3936 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3937 GENERIC0_INT_ENABLE, 1); 3938 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3939 break; 3940 default: 3941 break; 3942 } 3943 } 3944 3945 static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, 3946 struct amdgpu_irq_src *src, 3947 unsigned type, 3948 enum amdgpu_interrupt_state state) 3949 { 3950 int i, num_xcc; 3951 3952 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3953 for (i = 0; i < num_xcc; i++) { 3954 switch (type) { 3955 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3956 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3957 adev, 1, 0, state, i); 3958 break; 3959 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3960 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3961 adev, 1, 1, state, i); 3962 break; 3963 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3964 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3965 adev, 1, 2, state, i); 3966 break; 3967 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3968 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3969 adev, 1, 3, state, i); 3970 break; 3971 default: 3972 break; 3973 } 3974 } 3975 3976 return 0; 3977 } 3978 3979 static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, 3980 struct amdgpu_irq_src *source, 3981 struct amdgpu_iv_entry *entry) 3982 { 3983 u32 doorbell_offset = entry->src_data[0]; 3984 u8 me_id, pipe_id, queue_id; 3985 struct amdgpu_ring *ring; 3986 int i, xcc_id; 3987 3988 DRM_DEBUG("IH: CP EOP\n"); 3989 3990 if (adev->enable_mes && doorbell_offset) { 3991 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 3992 } else { 3993 me_id = (entry->ring_id & 0x0c) >> 2; 3994 pipe_id = (entry->ring_id & 0x03) >> 0; 3995 queue_id = (entry->ring_id & 0x70) >> 4; 3996 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3997 3998 if (xcc_id == -EINVAL) 3999 return -EINVAL; 4000 4001 switch (me_id) { 4002 case 1: 4003 case 2: 4004 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4005 ring = &adev->gfx.compute_ring 4006 [i + 4007 xcc_id * adev->gfx.num_compute_rings]; 4008 /* Per-queue interrupt is supported for MEC starting from VI. 4009 * The interrupt can only be enabled/disabled per pipe instead 4010 * of per queue. 4011 */ 4012 if ((ring->me == me_id) && 4013 (ring->pipe == pipe_id) && 4014 (ring->queue == queue_id)) 4015 amdgpu_fence_process(ring); 4016 } 4017 break; 4018 default: 4019 dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); 4020 break; 4021 } 4022 } 4023 4024 return 0; 4025 } 4026 4027 static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, 4028 struct amdgpu_irq_src *source, 4029 unsigned type, 4030 enum amdgpu_interrupt_state state) 4031 { 4032 int i, num_xcc; 4033 4034 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4035 switch (state) { 4036 case AMDGPU_IRQ_STATE_DISABLE: 4037 case AMDGPU_IRQ_STATE_ENABLE: 4038 for (i = 0; i < num_xcc; i++) 4039 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 4040 PRIV_REG_INT_ENABLE, 4041 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4042 break; 4043 default: 4044 break; 4045 } 4046 4047 return 0; 4048 } 4049 4050 static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, 4051 struct amdgpu_irq_src *source, 4052 unsigned type, 4053 enum amdgpu_interrupt_state state) 4054 { 4055 int i, num_xcc; 4056 4057 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4058 switch (state) { 4059 case AMDGPU_IRQ_STATE_DISABLE: 4060 case AMDGPU_IRQ_STATE_ENABLE: 4061 for (i = 0; i < num_xcc; i++) 4062 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 4063 PRIV_INSTR_INT_ENABLE, 4064 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4065 break; 4066 default: 4067 break; 4068 } 4069 4070 return 0; 4071 } 4072 4073 static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 4074 struct amdgpu_iv_entry *entry) 4075 { 4076 u8 me_id, pipe_id, queue_id; 4077 struct amdgpu_ring *ring; 4078 int i, xcc_id; 4079 4080 me_id = (entry->ring_id & 0x0c) >> 2; 4081 pipe_id = (entry->ring_id & 0x03) >> 0; 4082 queue_id = (entry->ring_id & 0x70) >> 4; 4083 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 4084 4085 if (xcc_id == -EINVAL) 4086 return; 4087 4088 if (!adev->gfx.disable_kq) { 4089 switch (me_id) { 4090 case 1: 4091 case 2: 4092 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4093 ring = &adev->gfx.compute_ring 4094 [i + 4095 xcc_id * adev->gfx.num_compute_rings]; 4096 if (ring->me == me_id && ring->pipe == pipe_id && 4097 ring->queue == queue_id) 4098 drm_sched_fault(&ring->sched); 4099 } 4100 break; 4101 default: 4102 dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); 4103 break; 4104 } 4105 } 4106 } 4107 4108 static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev, 4109 struct amdgpu_irq_src *source, 4110 struct amdgpu_iv_entry *entry) 4111 { 4112 DRM_ERROR("Illegal register access in command stream\n"); 4113 gfx_v12_1_handle_priv_fault(adev, entry); 4114 return 0; 4115 } 4116 4117 static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, 4118 struct amdgpu_irq_src *source, 4119 struct amdgpu_iv_entry *entry) 4120 { 4121 DRM_ERROR("Illegal instruction in command stream\n"); 4122 gfx_v12_1_handle_priv_fault(adev, entry); 4123 return 0; 4124 } 4125 4126 static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, 4127 struct amdgpu_irq_src *source, 4128 struct amdgpu_iv_entry *entry) 4129 { 4130 uint32_t rlc_fed_status = 0; 4131 uint32_t ras_blk = RAS_BLOCK_ID__GFX; 4132 struct ras_ih_info ih_info = {0}; 4133 int i, num_xcc; 4134 4135 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4136 for (i = 0; i < num_xcc; i++) 4137 rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, 4138 GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); 4139 4140 if (!rlc_fed_status) 4141 return 0; 4142 4143 if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || 4144 REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) 4145 ras_blk = RAS_BLOCK_ID__SDMA; 4146 4147 dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); 4148 4149 ih_info.block = ras_blk; 4150 ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 4151 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 4152 return 0; 4153 } 4154 4155 static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) 4156 { 4157 const unsigned int gcr_cntl = 4158 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | 4159 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | 4160 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | 4161 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | 4162 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | 4163 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); 4164 4165 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 4166 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 4167 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 4168 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4169 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 4170 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4171 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 4172 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 4173 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 4174 } 4175 4176 static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { 4177 .name = "gfx_v12_1", 4178 .early_init = gfx_v12_1_early_init, 4179 .sw_init = gfx_v12_1_sw_init, 4180 .sw_fini = gfx_v12_1_sw_fini, 4181 .hw_init = gfx_v12_1_hw_init, 4182 .hw_fini = gfx_v12_1_hw_fini, 4183 .suspend = gfx_v12_1_suspend, 4184 .resume = gfx_v12_1_resume, 4185 .is_idle = gfx_v12_1_is_idle, 4186 .wait_for_idle = gfx_v12_1_wait_for_idle, 4187 .set_clockgating_state = gfx_v12_1_set_clockgating_state, 4188 .set_powergating_state = gfx_v12_1_set_powergating_state, 4189 .get_clockgating_state = gfx_v12_1_get_clockgating_state, 4190 .dump_ip_state = gfx_v12_1_ip_dump, 4191 .print_ip_state = gfx_v12_1_ip_print, 4192 }; 4193 4194 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { 4195 .type = AMDGPU_RING_TYPE_COMPUTE, 4196 .align_mask = 0xff, 4197 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4198 .support_64bit_ptrs = true, 4199 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 4200 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 4201 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 4202 .emit_frame_size = 4203 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 4204 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4205 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4206 2 + /* gfx_v12_1_ring_emit_vm_flush */ 4207 8 + 8 + 8 + /* gfx_v12_1_ring_emit_fence x3 for user fence, vm fence */ 4208 8, /* gfx_v12_1_emit_mem_sync */ 4209 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 4210 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 4211 .emit_fence = gfx_v12_1_ring_emit_fence, 4212 .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, 4213 .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, 4214 .test_ring = gfx_v12_1_ring_test_ring, 4215 .test_ib = gfx_v12_1_ring_test_ib, 4216 .insert_nop = amdgpu_ring_insert_nop, 4217 .pad_ib = amdgpu_ring_generic_pad_ib, 4218 .emit_wreg = gfx_v12_1_ring_emit_wreg, 4219 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 4220 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 4221 .emit_mem_sync = gfx_v12_1_emit_mem_sync, 4222 }; 4223 4224 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_kiq = { 4225 .type = AMDGPU_RING_TYPE_KIQ, 4226 .align_mask = 0xff, 4227 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4228 .support_64bit_ptrs = true, 4229 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 4230 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 4231 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 4232 .emit_frame_size = 4233 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 4234 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4235 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4236 2 + /* gfx_v12_1_ring_emit_vm_flush */ 4237 8 + 8 + 8, /* gfx_v12_1_ring_emit_fence_kiq x3 for user fence, vm fence */ 4238 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 4239 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 4240 .emit_fence = gfx_v12_1_ring_emit_fence_kiq, 4241 .test_ring = gfx_v12_1_ring_test_ring, 4242 .test_ib = gfx_v12_1_ring_test_ib, 4243 .insert_nop = amdgpu_ring_insert_nop, 4244 .pad_ib = amdgpu_ring_generic_pad_ib, 4245 .emit_rreg = gfx_v12_1_ring_emit_rreg, 4246 .emit_wreg = gfx_v12_1_ring_emit_wreg, 4247 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 4248 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 4249 }; 4250 4251 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev) 4252 { 4253 int i, j, num_xcc; 4254 4255 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4256 for (i = 0; i < num_xcc; i++) { 4257 adev->gfx.kiq[i].ring.funcs = &gfx_v12_1_ring_funcs_kiq; 4258 4259 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4260 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs = 4261 &gfx_v12_1_ring_funcs_compute; 4262 } 4263 } 4264 4265 static const struct amdgpu_irq_src_funcs gfx_v12_1_eop_irq_funcs = { 4266 .set = gfx_v12_1_set_eop_interrupt_state, 4267 .process = gfx_v12_1_eop_irq, 4268 }; 4269 4270 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_reg_irq_funcs = { 4271 .set = gfx_v12_1_set_priv_reg_fault_state, 4272 .process = gfx_v12_1_priv_reg_irq, 4273 }; 4274 4275 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { 4276 .set = gfx_v12_1_set_priv_inst_fault_state, 4277 .process = gfx_v12_1_priv_inst_irq, 4278 }; 4279 4280 static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { 4281 .process = gfx_v12_1_rlc_poison_irq, 4282 }; 4283 4284 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) 4285 { 4286 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4287 adev->gfx.eop_irq.funcs = &gfx_v12_1_eop_irq_funcs; 4288 4289 adev->gfx.priv_reg_irq.num_types = 1; 4290 adev->gfx.priv_reg_irq.funcs = &gfx_v12_1_priv_reg_irq_funcs; 4291 4292 adev->gfx.priv_inst_irq.num_types = 1; 4293 adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; 4294 4295 adev->gfx.rlc_poison_irq.num_types = 1; 4296 adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; 4297 } 4298 4299 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) 4300 { 4301 if (adev->flags & AMD_IS_APU) 4302 adev->gfx.imu.mode = MISSION_MODE; 4303 else 4304 adev->gfx.imu.mode = DEBUG_MODE; 4305 if (!amdgpu_sriov_vf(adev)) 4306 adev->gfx.imu.funcs = &gfx_v12_1_imu_funcs; 4307 } 4308 4309 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev) 4310 { 4311 adev->gfx.rlc.funcs = &gfx_v12_1_rlc_funcs; 4312 } 4313 4314 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev) 4315 { 4316 /* set compute eng mqd */ 4317 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 4318 sizeof(struct v12_1_compute_mqd); 4319 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 4320 gfx_v12_1_compute_mqd_init; 4321 } 4322 4323 static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev, 4324 u32 bitmap, int xcc_id) 4325 { 4326 u32 data; 4327 4328 if (!bitmap) 4329 return; 4330 4331 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4332 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4333 4334 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4335 } 4336 4337 static u32 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev, 4338 int xcc_id) 4339 { 4340 u32 data, mask; 4341 4342 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4343 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4344 4345 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4346 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4347 4348 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4349 4350 return (~data) & mask; 4351 } 4352 4353 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 4354 struct amdgpu_cu_info *cu_info) 4355 { 4356 int i, j, k, counter, xcc_id, active_cu_number = 0; 4357 u32 mask, bitmap; 4358 unsigned int disable_masks[2 * 2]; 4359 4360 if (!adev || !cu_info) 4361 return -EINVAL; 4362 4363 if (adev->gfx.config.max_shader_engines > 2 || 4364 adev->gfx.config.max_sh_per_se > 2) { 4365 dev_err(adev->dev, 4366 "Max SE (%d) and Max SA per SE (%d) is greater than expected\n", 4367 adev->gfx.config.max_shader_engines, 4368 adev->gfx.config.max_sh_per_se); 4369 return -EINVAL; 4370 } 4371 4372 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4373 adev->gfx.config.max_shader_engines, 4374 adev->gfx.config.max_sh_per_se); 4375 4376 mutex_lock(&adev->grbm_idx_mutex); 4377 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4378 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4379 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4380 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4381 if (!((gfx_v12_1_get_sa_active_bitmap(adev, xcc_id) >> bitmap) & 1)) 4382 continue; 4383 mask = 1; 4384 counter = 0; 4385 gfx_v12_1_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4386 gfx_v12_1_set_user_cu_inactive_bitmap_per_sh( 4387 adev, 4388 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4389 xcc_id); 4390 bitmap = gfx_v12_1_get_cu_active_bitmap_per_sh(adev, xcc_id); 4391 4392 cu_info->bitmap[xcc_id][i][j] = bitmap; 4393 4394 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4395 if (bitmap & mask) 4396 counter++; 4397 4398 mask <<= 1; 4399 } 4400 active_cu_number += counter; 4401 } 4402 } 4403 gfx_v12_1_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 4404 } 4405 mutex_unlock(&adev->grbm_idx_mutex); 4406 4407 cu_info->number = active_cu_number; 4408 cu_info->simd_per_cu = NUM_SIMD_PER_CU_GFX12_1; 4409 cu_info->lds_size = 320; 4410 4411 return 0; 4412 } 4413 4414 const struct amdgpu_ip_block_version gfx_v12_1_ip_block = { 4415 .type = AMD_IP_BLOCK_TYPE_GFX, 4416 .major = 12, 4417 .minor = 1, 4418 .rev = 0, 4419 .funcs = &gfx_v12_1_ip_funcs, 4420 }; 4421 4422 static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) 4423 { 4424 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4425 uint32_t tmp_mask; 4426 int i, r; 4427 4428 /* TODO : Initialize golden regs */ 4429 /* gfx_v12_1_init_golden_registers(adev); */ 4430 4431 tmp_mask = inst_mask; 4432 for_each_inst(i, tmp_mask) 4433 gfx_v12_1_xcc_constants_init(adev, i); 4434 4435 if (!amdgpu_sriov_vf(adev)) { 4436 tmp_mask = inst_mask; 4437 for_each_inst(i, tmp_mask) { 4438 r = gfx_v12_1_xcc_rlc_resume(adev, i); 4439 if (r) 4440 return r; 4441 } 4442 } 4443 4444 r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); 4445 4446 return r; 4447 } 4448 4449 static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) 4450 { 4451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4452 int i; 4453 4454 for_each_inst(i, inst_mask) 4455 gfx_v12_1_xcc_fini(adev, i); 4456 4457 return 0; 4458 } 4459 4460 struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs = { 4461 .suspend = &gfx_v12_1_xcp_suspend, 4462 .resume = &gfx_v12_1_xcp_resume 4463 }; 4464