1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_userq_fence.h" 34 #include "imu_v12_1.h" 35 #include "soc_v1_0.h" 36 #include "gfx_v12_1_pkt.h" 37 38 #include "gc/gc_12_1_0_offset.h" 39 #include "gc/gc_12_1_0_sh_mask.h" 40 #include "soc24_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_1.h" 47 #include "mes_v12_1.h" 48 #include "amdgpu_ras_mgr.h" 49 50 #define GFX12_MEC_HPD_SIZE 2048 51 #define NUM_SIMD_PER_CU_GFX12_1 4 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000000 56 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 57 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 58 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 59 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 60 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0ae06301 61 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 62 63 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); 65 66 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 67 #define DEFAULT_SH_MEM_CONFIG \ 68 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 69 (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 70 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 71 72 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); 73 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); 74 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); 75 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev); 76 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev); 77 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev); 78 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 79 struct amdgpu_cu_info *cu_info); 80 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev); 81 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 82 u32 sh_num, u32 instance, int xcc_id); 83 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 84 uint32_t val); 85 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 86 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 87 uint16_t pasid, uint32_t flush_type, 88 bool all_hub, uint8_t dst_sel); 89 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 90 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 91 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 92 bool enable); 93 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 94 bool enable, int xcc_id); 95 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); 96 97 static void gfx_v12_1_kiq_set_resources(struct amdgpu_ring *kiq_ring, 98 uint64_t queue_mask) 99 { 100 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 101 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 102 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 103 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 104 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 105 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 106 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 107 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 108 amdgpu_ring_write(kiq_ring, 0); 109 } 110 111 static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, 112 struct amdgpu_ring *ring) 113 { 114 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 115 uint64_t wptr_addr = ring->wptr_gpu_addr; 116 uint32_t me = 0, eng_sel = 0; 117 118 switch (ring->funcs->type) { 119 case AMDGPU_RING_TYPE_COMPUTE: 120 me = 1; 121 eng_sel = 0; 122 break; 123 case AMDGPU_RING_TYPE_MES: 124 me = 2; 125 eng_sel = 5; 126 break; 127 default: 128 WARN_ON(1); 129 } 130 131 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 132 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 133 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 134 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 135 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 136 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 137 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 138 PACKET3_MAP_QUEUES_ME((me)) | 139 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 140 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 141 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 142 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 143 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 144 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 145 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 146 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 147 } 148 149 static void gfx_v12_1_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 150 struct amdgpu_ring *ring, 151 enum amdgpu_unmap_queues_action action, 152 u64 gpu_addr, u64 seq) 153 { 154 struct amdgpu_device *adev = kiq_ring->adev; 155 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 156 157 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 158 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, 159 seq, kiq_ring->xcc_id); 160 return; 161 } 162 163 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 164 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 165 PACKET3_UNMAP_QUEUES_ACTION(action) | 166 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 167 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 168 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 169 amdgpu_ring_write(kiq_ring, 170 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 171 172 if (action == PREEMPT_QUEUES_NO_UNMAP) { 173 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 174 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 175 amdgpu_ring_write(kiq_ring, seq); 176 } else { 177 amdgpu_ring_write(kiq_ring, 0); 178 amdgpu_ring_write(kiq_ring, 0); 179 amdgpu_ring_write(kiq_ring, 0); 180 } 181 } 182 183 static void gfx_v12_1_kiq_query_status(struct amdgpu_ring *kiq_ring, 184 struct amdgpu_ring *ring, 185 u64 addr, u64 seq) 186 { 187 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 188 189 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 190 amdgpu_ring_write(kiq_ring, 191 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 192 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 193 PACKET3_QUERY_STATUS_COMMAND(2)); 194 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 195 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 196 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 197 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 198 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 199 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 200 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 201 } 202 203 static void gfx_v12_1_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 204 uint16_t pasid, 205 uint32_t flush_type, 206 bool all_hub) 207 { 208 gfx_v12_1_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 209 } 210 211 static const struct kiq_pm4_funcs gfx_v12_1_kiq_pm4_funcs = { 212 .kiq_set_resources = gfx_v12_1_kiq_set_resources, 213 .kiq_map_queues = gfx_v12_1_kiq_map_queues, 214 .kiq_unmap_queues = gfx_v12_1_kiq_unmap_queues, 215 .kiq_query_status = gfx_v12_1_kiq_query_status, 216 .kiq_invalidate_tlbs = gfx_v12_1_kiq_invalidate_tlbs, 217 .set_resources_size = 8, 218 .map_queues_size = 7, 219 .unmap_queues_size = 6, 220 .query_status_size = 7, 221 .invalidate_tlbs_size = 2, 222 }; 223 224 static void gfx_v12_1_set_kiq_pm4_funcs(struct amdgpu_device *adev) 225 { 226 int i, num_xcc; 227 228 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 229 for (i =0; i < num_xcc; i++) 230 adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; 231 } 232 233 static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 234 int mem_space, int opt, uint32_t addr0, 235 uint32_t addr1, uint32_t ref, 236 uint32_t mask, uint32_t inv) 237 { 238 if (mem_space == 0) { 239 addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0); 240 addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1); 241 } 242 243 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 244 amdgpu_ring_write(ring, 245 /* memory (1) or register (0) */ 246 (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | 247 PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ 248 PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ 249 250 if (mem_space) 251 WARN_ON(addr0 & 0x3); /* Dword align */ 252 amdgpu_ring_write(ring, addr0); 253 amdgpu_ring_write(ring, addr1); 254 amdgpu_ring_write(ring, ref); 255 amdgpu_ring_write(ring, mask); 256 amdgpu_ring_write(ring, inv); /* poll interval */ 257 } 258 259 static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring) 260 { 261 struct amdgpu_device *adev = ring->adev; 262 uint32_t scratch_reg0_offset, xcc_offset; 263 uint32_t tmp = 0; 264 unsigned i; 265 int r; 266 267 /* Use register offset which is local to XCC in the packet */ 268 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 269 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 270 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 271 tmp = RREG32(scratch_reg0_offset); 272 273 r = amdgpu_ring_alloc(ring, 5); 274 if (r) { 275 dev_err(adev->dev, 276 "amdgpu: cp failed to lock ring %d (%d).\n", 277 ring->idx, r); 278 return r; 279 } 280 281 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 282 gfx_v12_1_ring_emit_wreg(ring, xcc_offset, 0xDEADBEEF); 283 } else { 284 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 285 amdgpu_ring_write(ring, xcc_offset - 286 PACKET3_SET_UCONFIG_REG_START); 287 amdgpu_ring_write(ring, 0xDEADBEEF); 288 } 289 amdgpu_ring_commit(ring); 290 291 for (i = 0; i < adev->usec_timeout; i++) { 292 tmp = RREG32(scratch_reg0_offset); 293 if (tmp == 0xDEADBEEF) 294 break; 295 if (amdgpu_emu_mode == 1) 296 msleep(1); 297 else 298 udelay(1); 299 } 300 301 if (i >= adev->usec_timeout) 302 r = -ETIMEDOUT; 303 return r; 304 } 305 306 static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 struct amdgpu_ib ib; 310 struct dma_fence *f = NULL; 311 unsigned index; 312 uint64_t gpu_addr; 313 volatile uint32_t *cpu_ptr; 314 long r; 315 316 /* MES KIQ fw hasn't indirect buffer support for now */ 317 if (adev->enable_mes_kiq && 318 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 319 return 0; 320 321 memset(&ib, 0, sizeof(ib)); 322 323 r = amdgpu_wb_get(adev, &index); 324 if (r) 325 return r; 326 327 gpu_addr = adev->wb.gpu_addr + (index * 4); 328 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 329 cpu_ptr = &adev->wb.wb[index]; 330 331 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 332 if (r) { 333 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 334 goto err1; 335 } 336 337 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 338 ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); 339 ib.ptr[2] = lower_32_bits(gpu_addr); 340 ib.ptr[3] = upper_32_bits(gpu_addr); 341 ib.ptr[4] = 0xDEADBEEF; 342 ib.length_dw = 5; 343 344 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 345 if (r) 346 goto err2; 347 348 r = dma_fence_wait_timeout(f, false, timeout); 349 if (r == 0) { 350 r = -ETIMEDOUT; 351 goto err2; 352 } else if (r < 0) { 353 goto err2; 354 } 355 356 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 357 r = 0; 358 else 359 r = -EINVAL; 360 err2: 361 amdgpu_ib_free(&ib, NULL); 362 dma_fence_put(f); 363 err1: 364 amdgpu_wb_free(adev, index); 365 return r; 366 } 367 368 static void gfx_v12_1_free_microcode(struct amdgpu_device *adev) 369 { 370 amdgpu_ucode_release(&adev->gfx.rlc_fw); 371 amdgpu_ucode_release(&adev->gfx.mec_fw); 372 373 kfree(adev->gfx.rlc.register_list_format); 374 } 375 376 static int gfx_v12_1_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 377 { 378 const struct psp_firmware_header_v1_0 *toc_hdr; 379 int err = 0; 380 381 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 382 AMDGPU_UCODE_REQUIRED, 383 "amdgpu/%s_toc.bin", ucode_prefix); 384 if (err) 385 goto out; 386 387 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 388 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 389 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 390 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 391 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 392 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 393 return 0; 394 out: 395 amdgpu_ucode_release(&adev->psp.toc_fw); 396 return err; 397 } 398 399 static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) 400 { 401 char ucode_prefix[15]; 402 int err; 403 const struct rlc_firmware_header_v2_0 *rlc_hdr; 404 uint16_t version_major; 405 uint16_t version_minor; 406 407 DRM_DEBUG("\n"); 408 409 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 410 411 if (!amdgpu_sriov_vf(adev)) { 412 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && 413 adev->rev_id == 0) 414 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 415 AMDGPU_UCODE_REQUIRED, 416 "amdgpu/%s_rlc_1.bin", ucode_prefix); 417 else 418 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 419 AMDGPU_UCODE_REQUIRED, 420 "amdgpu/%s_rlc.bin", ucode_prefix); 421 if (err) 422 goto out; 423 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 424 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 425 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 426 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 427 if (err) 428 goto out; 429 } 430 431 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 432 AMDGPU_UCODE_REQUIRED, 433 "amdgpu/%s_mec.bin", ucode_prefix); 434 if (err) 435 goto out; 436 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 437 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 438 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 439 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 440 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 441 442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 443 err = gfx_v12_1_init_toc_microcode(adev, ucode_prefix); 444 445 /* only one MEC for gfx 12 */ 446 adev->gfx.mec2_fw = NULL; 447 448 if (adev->gfx.imu.funcs) { 449 if (adev->gfx.imu.funcs->init_microcode) { 450 err = adev->gfx.imu.funcs->init_microcode(adev); 451 if (err) 452 dev_err(adev->dev, "Failed to load imu firmware!\n"); 453 } 454 } 455 456 out: 457 if (err) { 458 amdgpu_ucode_release(&adev->gfx.rlc_fw); 459 amdgpu_ucode_release(&adev->gfx.mec_fw); 460 } 461 462 return err; 463 } 464 465 static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev) 466 { 467 u32 count = 0; 468 const struct cs_section_def *sect = NULL; 469 const struct cs_extent_def *ext = NULL; 470 471 count += 1; 472 473 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 474 if (sect->id == SECT_CONTEXT) { 475 for (ext = sect->section; ext->extent != NULL; ++ext) 476 count += 2 + ext->reg_count; 477 } else 478 return 0; 479 } 480 481 return count; 482 } 483 484 static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 485 { 486 u32 count = 0, clustercount = 0, i; 487 const struct cs_section_def *sect = NULL; 488 const struct cs_extent_def *ext = NULL; 489 490 if (adev->gfx.rlc.cs_data == NULL) 491 return; 492 if (buffer == NULL) 493 return; 494 495 count += 1; 496 497 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 498 if (sect->id == SECT_CONTEXT) { 499 for (ext = sect->section; ext->extent != NULL; ++ext) { 500 clustercount++; 501 buffer[count++] = ext->reg_count; 502 buffer[count++] = ext->reg_index; 503 504 for (i = 0; i < ext->reg_count; i++) 505 buffer[count++] = cpu_to_le32(ext->extent[i]); 506 } 507 } else 508 return; 509 } 510 511 buffer[0] = clustercount; 512 } 513 514 static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev) 515 { 516 /* clear state block */ 517 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 518 &adev->gfx.rlc.clear_state_gpu_addr, 519 (void **)&adev->gfx.rlc.cs_ptr); 520 521 /* jump table block */ 522 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 523 &adev->gfx.rlc.cp_table_gpu_addr, 524 (void **)&adev->gfx.rlc.cp_table_ptr); 525 } 526 527 static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 528 { 529 int xcc_id, num_xcc; 530 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 531 532 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 533 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 534 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 535 536 reg_access_ctrl->grbm_cntl = 537 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 538 reg_access_ctrl->grbm_idx = 539 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 540 541 reg_access_ctrl->vfi_cmd = 542 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD); 543 reg_access_ctrl->vfi_stat = 544 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT); 545 reg_access_ctrl->vfi_addr = 546 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR); 547 reg_access_ctrl->vfi_data = 548 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA); 549 reg_access_ctrl->vfi_grbm_cntl = 550 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL); 551 reg_access_ctrl->vfi_grbm_idx = 552 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX); 553 reg_access_ctrl->vfi_grbm_cntl_data = 0; 554 reg_access_ctrl->vfi_grbm_idx_data = 0; 555 } 556 adev->gfx.rlc.rlcg_reg_access_supported = true; 557 } 558 559 static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) 560 { 561 const struct cs_section_def *cs_data; 562 int r, i, num_xcc; 563 564 adev->gfx.rlc.cs_data = gfx12_cs_data; 565 566 cs_data = adev->gfx.rlc.cs_data; 567 568 if (cs_data) { 569 /* init clear state block */ 570 r = amdgpu_gfx_rlc_init_csb(adev); 571 if (r) 572 return r; 573 } 574 575 /* init spm vmid with 0xf */ 576 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 577 for (i = 0; i < num_xcc; i++) { 578 if (adev->gfx.rlc.funcs->update_spm_vmid) 579 adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); 580 } 581 582 return 0; 583 } 584 585 static void gfx_v12_1_mec_fini(struct amdgpu_device *adev) 586 { 587 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 588 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 589 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 590 } 591 592 static int gfx_v12_1_mec_init(struct amdgpu_device *adev) 593 { 594 int r, i, num_xcc; 595 u32 *hpd; 596 size_t mec_hpd_size; 597 598 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 599 600 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 601 for (i = 0; i < num_xcc; i++) 602 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 603 AMDGPU_MAX_COMPUTE_QUEUES); 604 605 /* take ownership of the relevant compute queues */ 606 amdgpu_gfx_compute_queue_acquire(adev); 607 mec_hpd_size = adev->gfx.num_compute_rings * 608 GFX12_MEC_HPD_SIZE * num_xcc; 609 610 if (mec_hpd_size) { 611 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 612 AMDGPU_GEM_DOMAIN_GTT, 613 &adev->gfx.mec.hpd_eop_obj, 614 &adev->gfx.mec.hpd_eop_gpu_addr, 615 (void **)&hpd); 616 if (r) { 617 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 618 gfx_v12_1_mec_fini(adev); 619 return r; 620 } 621 622 memset(hpd, 0, mec_hpd_size); 623 624 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 625 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 626 } 627 628 return 0; 629 } 630 631 static uint32_t wave_read_ind(struct amdgpu_device *adev, 632 uint32_t xcc_id, uint32_t wave, 633 uint32_t address) 634 { 635 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 636 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 637 (address << SQ_IND_INDEX__INDEX__SHIFT)); 638 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 639 } 640 641 static void wave_read_regs(struct amdgpu_device *adev, 642 uint32_t xcc_id, uint32_t wave, 643 uint32_t thread, uint32_t regno, 644 uint32_t num, uint32_t *out) 645 { 646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 647 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 648 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 649 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 650 (SQ_IND_INDEX__AUTO_INCR_MASK)); 651 while (num--) 652 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 653 } 654 655 static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, 656 uint32_t xcc_id, 657 uint32_t simd, uint32_t wave, 658 uint32_t *dst, int *no_fields) 659 { 660 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 661 * field when performing a select_se_sh so it should be 662 * zero here */ 663 WARN_ON(simd != 0); 664 665 /* type 4 wave data */ 666 dst[(*no_fields)++] = 4; 667 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); 668 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); 669 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); 670 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); 671 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); 672 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); 673 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); 674 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); 675 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); 676 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); 677 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); 678 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); 679 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); 680 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); 681 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); 682 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 683 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); 684 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); 685 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); 686 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); 687 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 688 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 689 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); 690 } 691 692 static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, 693 uint32_t xcc_id, uint32_t simd, 694 uint32_t wave, uint32_t start, 695 uint32_t size, uint32_t *dst) 696 { 697 WARN_ON(simd != 0); 698 699 wave_read_regs(adev, xcc_id, wave, 0, 700 start + SQIND_WAVE_SGPRS_OFFSET, 701 size, dst); 702 } 703 704 static void gfx_v12_1_read_wave_vgprs(struct amdgpu_device *adev, 705 uint32_t xcc_id, uint32_t simd, 706 uint32_t wave, uint32_t thread, 707 uint32_t start, uint32_t size, 708 uint32_t *dst) 709 { 710 wave_read_regs(adev, xcc_id, wave, thread, 711 start + SQIND_WAVE_VGPRS_OFFSET, 712 size, dst); 713 } 714 715 static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, 716 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 717 { 718 soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 719 } 720 721 #define regGFX_IMU_PARTITION_SWITCH 0x5f8c 722 #define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 723 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 724 #define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL 725 726 static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) 727 { 728 u32 reg_data; 729 730 /* the register data is expected to be the same on all instances */ 731 reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); 732 733 return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); 734 } 735 736 static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 737 { 738 int logic_xcc; 739 int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; 740 741 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { 742 if (xcc == GET_INST(GC, logic_xcc)) 743 return logic_xcc; 744 } 745 746 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 747 return -EINVAL; 748 } 749 750 static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { 751 .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, 752 .select_se_sh = &gfx_v12_1_xcc_select_se_sh, 753 .read_wave_data = &gfx_v12_1_read_wave_data, 754 .read_wave_sgprs = &gfx_v12_1_read_wave_sgprs, 755 .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, 756 .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, 757 .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, 758 .get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp, 759 .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, 760 }; 761 762 static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) 763 { 764 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 765 case IP_VERSION(12, 1, 0): 766 adev->gfx.config.max_hw_contexts = 8; 767 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 768 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 769 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 770 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 771 break; 772 default: 773 BUG(); 774 break; 775 } 776 777 return 0; 778 } 779 780 static int gfx_v12_1_compute_ring_init(struct amdgpu_device *adev, int ring_id, 781 int xcc_id, int mec, int pipe, int queue) 782 { 783 int r; 784 unsigned irq_type; 785 struct amdgpu_ring *ring; 786 unsigned int hw_prio; 787 uint32_t xcc_doorbell_start; 788 789 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 790 ring_id]; 791 792 /* mec0 is me1 */ 793 ring->xcc_id = xcc_id; 794 ring->me = mec + 1; 795 ring->pipe = pipe; 796 ring->queue = queue; 797 798 ring->ring_obj = NULL; 799 ring->use_doorbell = true; 800 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 801 xcc_id * adev->doorbell_index.xcc_doorbell_range; 802 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 803 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 804 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 805 GFX12_MEC_HPD_SIZE; 806 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 807 sprintf(ring->name, "comp_%d.%d.%d.%d", 808 ring->xcc_id, ring->me, ring->pipe, ring->queue); 809 810 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 811 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 812 + ring->pipe; 813 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 814 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 815 /* type-2 packets are deprecated on MEC, use type-3 instead */ 816 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 817 hw_prio, NULL); 818 if (r) 819 return r; 820 821 return 0; 822 } 823 824 static struct { 825 SOC24_FIRMWARE_ID id; 826 unsigned int offset; 827 unsigned int size; 828 unsigned int size_x16; 829 unsigned int num_inst; 830 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 831 832 #define RLC_TOC_OFFSET_DWUNIT 8 833 #define RLC_SIZE_MULTIPLE 1024 834 #define RLC_TOC_UMF_SIZE_inM 23ULL 835 #define RLC_TOC_FORMAT_API 165ULL 836 837 #define RLC_NUM_INS_CODE0 1 838 #define RLC_NUM_INS_CODE1 8 839 #define RLC_NUM_INS_CODE2 2 840 #define RLC_NUM_INS_CODE3 16 841 842 static void gfx_v12_1_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 843 { 844 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 845 846 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 847 rlc_autoload_info[ucode->id].id = ucode->id; 848 rlc_autoload_info[ucode->id].offset = 849 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 850 rlc_autoload_info[ucode->id].size = 851 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 852 ucode->size * 4; 853 switch (ucode->vfflr_image_code) { 854 case 0: 855 rlc_autoload_info[ucode->id].num_inst = 856 RLC_NUM_INS_CODE0; 857 break; 858 case 1: 859 rlc_autoload_info[ucode->id].num_inst = 860 RLC_NUM_INS_CODE1; 861 break; 862 case 2: 863 rlc_autoload_info[ucode->id].num_inst = 864 RLC_NUM_INS_CODE2; 865 break; 866 case 3: 867 rlc_autoload_info[ucode->id].num_inst = 868 RLC_NUM_INS_CODE3; 869 break; 870 default: 871 dev_err(adev->dev, 872 "Invalid Instance number detected\n"); 873 break; 874 } 875 ucode++; 876 } 877 } 878 879 static uint32_t gfx_v12_1_calc_toc_total_size(struct amdgpu_device *adev) 880 { 881 uint32_t total_size = 0; 882 SOC24_FIRMWARE_ID id; 883 884 gfx_v12_1_parse_rlc_toc(adev, adev->psp.toc.start_addr); 885 886 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 887 total_size += rlc_autoload_info[id].size; 888 889 /* In case the offset in rlc toc ucode is aligned */ 890 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 891 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 892 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 893 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 894 total_size = RLC_TOC_UMF_SIZE_inM << 20; 895 896 return total_size; 897 } 898 899 static int gfx_v12_1_rlc_autoload_buffer_init(struct amdgpu_device *adev) 900 { 901 int r; 902 uint32_t total_size; 903 904 total_size = gfx_v12_1_calc_toc_total_size(adev); 905 906 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 907 AMDGPU_GEM_DOMAIN_VRAM, 908 &adev->gfx.rlc.rlc_autoload_bo, 909 &adev->gfx.rlc.rlc_autoload_gpu_addr, 910 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 911 912 if (r) { 913 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 914 return r; 915 } 916 917 return 0; 918 } 919 920 static void gfx_v12_1_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 921 SOC24_FIRMWARE_ID id, 922 const void *fw_data, 923 uint32_t fw_size) 924 { 925 uint32_t toc_offset; 926 uint32_t toc_fw_size, toc_fw_inst_size; 927 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 928 int i, num_inst; 929 930 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 931 return; 932 933 toc_offset = rlc_autoload_info[id].offset; 934 toc_fw_size = rlc_autoload_info[id].size; 935 num_inst = rlc_autoload_info[id].num_inst; 936 toc_fw_inst_size = toc_fw_size / num_inst; 937 938 if (fw_size == 0) 939 fw_size = toc_fw_inst_size; 940 941 if (fw_size > toc_fw_inst_size) 942 fw_size = toc_fw_inst_size; 943 944 for (i = 0; i < num_inst; i++) { 945 if ((num_inst == RLC_NUM_INS_CODE0) || 946 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { 947 memcpy(ptr + toc_offset + i * toc_fw_inst_size, fw_data, fw_size); 948 949 if (fw_size < toc_fw_inst_size) 950 memset(ptr + toc_offset + fw_size + i * toc_fw_inst_size, 951 0, toc_fw_inst_size - fw_size); 952 } 953 } 954 } 955 956 static void 957 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 958 { 959 void *data; 960 uint32_t size; 961 uint32_t *toc_ptr; 962 963 data = adev->psp.toc.start_addr; 964 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 965 966 toc_ptr = (uint32_t *)data + size / 4 - 2; 967 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 968 969 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 970 data, size); 971 } 972 973 static void 974 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 975 { 976 const __le32 *fw_data; 977 uint32_t fw_size; 978 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 979 const struct rlc_firmware_header_v2_0 *rlc_hdr; 980 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 981 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 982 uint16_t version_major, version_minor; 983 984 /* mec ucode */ 985 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 986 adev->gfx.mec_fw->data; 987 /* instruction */ 988 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 989 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 990 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 991 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 992 fw_data, fw_size); 993 /* data */ 994 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 995 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 996 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 997 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 998 fw_data, fw_size); 999 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1000 fw_data, fw_size); 1001 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1002 fw_data, fw_size); 1003 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1004 fw_data, fw_size); 1005 1006 /* rlc ucode */ 1007 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1008 adev->gfx.rlc_fw->data; 1009 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1010 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1011 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1012 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1013 fw_data, fw_size); 1014 1015 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1016 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1017 if (version_major == 2) { 1018 if (version_minor >= 1) { 1019 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1020 1021 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1022 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1023 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1024 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1025 fw_data, fw_size); 1026 1027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1028 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1029 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1030 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1031 fw_data, fw_size); 1032 } 1033 if (version_minor >= 2) { 1034 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1035 1036 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1037 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1038 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1039 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1040 fw_data, fw_size); 1041 1042 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1043 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1044 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1045 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1046 fw_data, fw_size); 1047 } 1048 } 1049 } 1050 1051 static void 1052 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1053 { 1054 const __le32 *fw_data; 1055 uint32_t fw_size; 1056 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1057 1058 if (adev->sdma.instance[0].fw) { 1059 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1060 adev->sdma.instance[0].fw->data; 1061 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1062 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1063 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1064 1065 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1066 fw_data, fw_size); 1067 } 1068 } 1069 1070 static void 1071 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1072 { 1073 const __le32 *fw_data; 1074 unsigned fw_size; 1075 const struct mes_firmware_header_v1_0 *mes_hdr; 1076 int pipe, ucode_id, data_id; 1077 1078 for (pipe = 0; pipe < 2; pipe++) { 1079 if (pipe == 0) { 1080 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1081 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1082 } else { 1083 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1084 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1085 } 1086 1087 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1088 adev->mes.fw[pipe]->data; 1089 1090 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1091 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1092 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1093 1094 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1095 1096 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1097 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1098 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1099 1100 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1101 } 1102 } 1103 1104 static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1105 { 1106 uint32_t rlc_g_offset, rlc_g_size; 1107 uint64_t gpu_addr; 1108 uint32_t data; 1109 int i, num_xcc; 1110 1111 /* RLC autoload sequence 2: copy ucode */ 1112 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1113 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1114 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(adev); 1115 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(adev); 1116 1117 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1118 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1119 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1120 1121 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1122 for (i = 0; i < num_xcc; i++) { 1123 WREG32_SOC15(GC, GET_INST(GC, i), 1124 regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, 1125 upper_32_bits(gpu_addr)); 1126 WREG32_SOC15(GC, GET_INST(GC, i), 1127 regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, 1128 lower_32_bits(gpu_addr)); 1129 WREG32_SOC15(GC, GET_INST(GC, i), 1130 regGFX_IMU_RLC_BOOTLOADER_SIZE, 1131 rlc_g_size); 1132 } 1133 1134 if (adev->gfx.imu.funcs) { 1135 /* RLC autoload sequence 3: load IMU fw */ 1136 if (adev->gfx.imu.funcs->load_microcode) 1137 adev->gfx.imu.funcs->load_microcode(adev); 1138 } 1139 1140 /* unhalt rlc to start autoload */ 1141 for (i = 0; i < num_xcc; i++) { 1142 data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE); 1143 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1144 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1145 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data); 1146 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1153 { 1154 uint16_t major_ver, minor_ver; 1155 int i, j, k, r, ring_id = 0; 1156 unsigned num_compute_rings; 1157 int xcc_id, num_xcc; 1158 struct amdgpu_device *adev = ip_block->adev; 1159 1160 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1161 case IP_VERSION(12, 1, 0): 1162 adev->gfx.mec.num_mec = 1; 1163 adev->gfx.mec.num_pipe_per_mec = 4; 1164 adev->gfx.mec.num_queue_per_pipe = 8; 1165 1166 if (!amdgpu_discovery_get_gc_major_minor_version( 1167 adev, &major_ver, &minor_ver)) { 1168 if (major_ver == 1 && minor_ver == 3) { 1169 adev->gfx.config.max_cu_per_sh /= 2; 1170 dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", 1171 adev->gfx.config.max_cu_per_sh); 1172 } 1173 } 1174 break; 1175 default: 1176 adev->gfx.mec.num_mec = 2; 1177 adev->gfx.mec.num_pipe_per_mec = 2; 1178 adev->gfx.mec.num_queue_per_pipe = 4; 1179 break; 1180 } 1181 1182 if (adev->gfx.num_compute_rings) { 1183 /* recalculate compute rings to use based on hardware configuration */ 1184 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1185 adev->gfx.mec.num_queue_per_pipe) / 2; 1186 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1187 num_compute_rings); 1188 } 1189 1190 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1191 1192 /* EOP Event */ 1193 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1194 GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, 1195 &adev->gfx.eop_irq); 1196 if (r) 1197 return r; 1198 1199 /* Privileged reg */ 1200 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1201 GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, 1202 &adev->gfx.priv_reg_irq); 1203 if (r) 1204 return r; 1205 1206 /* Privileged inst */ 1207 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1208 GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, 1209 &adev->gfx.priv_inst_irq); 1210 if (r) 1211 return r; 1212 1213 /* RLC POISON Error */ 1214 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, 1215 GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, 1216 &adev->gfx.rlc_poison_irq); 1217 if (r) 1218 return r; 1219 1220 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1221 1222 r = gfx_v12_1_rlc_init(adev); 1223 if (r) { 1224 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1225 return r; 1226 } 1227 1228 r = gfx_v12_1_mec_init(adev); 1229 if (r) { 1230 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1231 return r; 1232 } 1233 1234 /* set up the compute queues - allocate horizontally across pipes */ 1235 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1236 ring_id = 0; 1237 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1238 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1239 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1240 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1241 xcc_id, i, k, j)) 1242 continue; 1243 1244 r = gfx_v12_1_compute_ring_init(adev, ring_id, 1245 xcc_id, i, k, j); 1246 if (r) 1247 return r; 1248 1249 ring_id++; 1250 } 1251 } 1252 } 1253 1254 if (!adev->enable_mes_kiq) { 1255 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, xcc_id); 1256 if (r) { 1257 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1258 return r; 1259 } 1260 1261 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1262 if (r) 1263 return r; 1264 } 1265 1266 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_1_compute_mqd), xcc_id); 1267 if (r) 1268 return r; 1269 } 1270 1271 /* allocate visible FB for rlc auto-loading fw */ 1272 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1273 r = gfx_v12_1_rlc_autoload_buffer_init(adev); 1274 if (r) 1275 return r; 1276 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1277 r = gfx_v12_1_init_cp_compute_microcode_bo(adev); 1278 if (r) 1279 return r; 1280 } 1281 1282 r = gfx_v12_1_gpu_early_init(adev); 1283 if (r) 1284 return r; 1285 1286 r = amdgpu_gfx_sysfs_init(adev); 1287 if (r) 1288 return r; 1289 1290 mutex_init(&adev->gfx.mec.reset_mutex); 1291 1292 return 0; 1293 } 1294 1295 static void gfx_v12_1_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1296 { 1297 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1298 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1299 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1300 } 1301 1302 static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1303 { 1304 int i, num_xcc; 1305 struct amdgpu_device *adev = ip_block->adev; 1306 1307 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1308 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1309 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1310 1311 for (i = 0; i < num_xcc; i++) { 1312 amdgpu_gfx_mqd_sw_fini(adev, i); 1313 1314 if (!adev->enable_mes_kiq) { 1315 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1316 amdgpu_gfx_kiq_fini(adev, i); 1317 } 1318 } 1319 1320 gfx_v12_1_rlc_fini(adev); 1321 gfx_v12_1_mec_fini(adev); 1322 1323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1324 gfx_v12_1_rlc_autoload_buffer_fini(adev); 1325 1326 gfx_v12_1_free_microcode(adev); 1327 amdgpu_gfx_sysfs_fini(adev); 1328 1329 return 0; 1330 } 1331 1332 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1333 u32 sh_num, u32 instance, int xcc_id) 1334 { 1335 u32 data; 1336 1337 if (instance == 0xffffffff) 1338 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1339 INSTANCE_BROADCAST_WRITES, 1); 1340 else 1341 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1342 instance); 1343 1344 if (se_num == 0xffffffff) 1345 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1346 1); 1347 else 1348 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1349 1350 if (sh_num == 0xffffffff) 1351 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1352 1); 1353 else 1354 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1355 1356 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 1357 } 1358 1359 static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, 1360 int xcc_id) 1361 { 1362 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1363 1364 gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE); 1365 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1366 CC_GC_SA_UNIT_DISABLE, 1367 SA_DISABLE); 1368 gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE); 1369 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1370 GC_USER_SA_UNIT_DISABLE, 1371 SA_DISABLE); 1372 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1373 adev->gfx.config.max_shader_engines); 1374 1375 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1376 } 1377 1378 static u32 gfx_v12_1_get_rb_active_bitmap(struct amdgpu_device *adev, 1379 int xcc_id) 1380 { 1381 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1382 u32 rb_mask; 1383 1384 gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1385 regCC_RB_BACKEND_DISABLE); 1386 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1387 CC_RB_BACKEND_DISABLE, 1388 BACKEND_DISABLE); 1389 gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1390 regGC_USER_RB_BACKEND_DISABLE); 1391 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1392 GC_USER_RB_BACKEND_DISABLE, 1393 BACKEND_DISABLE); 1394 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1395 adev->gfx.config.max_shader_engines); 1396 1397 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1398 } 1399 1400 static void gfx_v12_1_setup_rb(struct amdgpu_device *adev) 1401 { 1402 u32 rb_bitmap_width_per_sa; 1403 u32 max_sa; 1404 u32 active_sa_bitmap; 1405 u32 global_active_rb_bitmap; 1406 u32 active_rb_bitmap = 0; 1407 u32 i; 1408 int xcc_id; 1409 1410 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 1411 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1412 active_sa_bitmap = gfx_v12_1_get_sa_active_bitmap(adev, xcc_id); 1413 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1414 global_active_rb_bitmap = gfx_v12_1_get_rb_active_bitmap(adev, xcc_id); 1415 1416 /* generate active rb bitmap according to active sa bitmap */ 1417 max_sa = adev->gfx.config.max_shader_engines * 1418 adev->gfx.config.max_sh_per_se; 1419 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1420 adev->gfx.config.max_sh_per_se; 1421 for (i = 0; i < max_sa; i++) { 1422 if (active_sa_bitmap & (1 << i)) 1423 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1424 } 1425 1426 active_rb_bitmap |= global_active_rb_bitmap; 1427 } 1428 1429 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1430 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1431 } 1432 1433 static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, 1434 int xcc_id) 1435 { 1436 int i; 1437 uint32_t sh_mem_bases; 1438 uint32_t data; 1439 1440 /* 1441 * Configure apertures: 1442 * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) 1443 * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) 1444 */ 1445 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1446 (adev->gmc.private_aperture_start >> 58)); 1447 sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, 1448 (adev->gmc.shared_aperture_start >> 48)); 1449 1450 mutex_lock(&adev->srbm_mutex); 1451 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1452 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1453 /* CP and shaders */ 1454 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1455 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1456 1457 /* Enable trap for each kfd vmid. */ 1458 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1459 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1460 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1461 1462 /* Disable VGPR deallocation instruction for each KFD vmid. */ 1463 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG); 1464 data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1); 1465 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data); 1466 } 1467 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1468 mutex_unlock(&adev->srbm_mutex); 1469 } 1470 1471 static void gfx_v12_1_tcp_harvest(struct amdgpu_device *adev) 1472 { 1473 /* TODO: harvest feature to be added later. */ 1474 } 1475 1476 static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) 1477 { 1478 } 1479 1480 static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) 1481 { 1482 /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ 1483 mutex_lock(&adev->srbm_mutex); 1484 if (!adev->gmc.noretry) { 1485 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1486 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); 1487 } else 1488 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1489 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); 1490 mutex_unlock(&adev->srbm_mutex); 1491 } 1492 1493 static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, 1494 int xcc_id) 1495 { 1496 u32 tmp; 1497 int i; 1498 1499 /* XXX SH_MEM regs */ 1500 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1501 mutex_lock(&adev->srbm_mutex); 1502 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1503 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1504 /* CP and shaders */ 1505 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1506 regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1507 if (i != 0) { 1508 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1509 (adev->gmc.private_aperture_start >> 58)); 1510 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1511 (adev->gmc.shared_aperture_start >> 48)); 1512 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); 1513 } 1514 } 1515 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1516 1517 mutex_unlock(&adev->srbm_mutex); 1518 1519 gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); 1520 gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); 1521 1522 } 1523 1524 static void gfx_v12_1_constants_init(struct amdgpu_device *adev) 1525 { 1526 int i, num_xcc; 1527 1528 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1529 1530 gfx_v12_1_setup_rb(adev); 1531 gfx_v12_1_get_cu_info(adev, &adev->gfx.cu_info); 1532 gfx_v12_1_get_tcc_info(adev); 1533 adev->gfx.config.pa_sc_tile_steering_override = 0; 1534 1535 for (i = 0; i < num_xcc; i++) 1536 gfx_v12_1_xcc_constants_init(adev, i); 1537 } 1538 1539 static void gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1540 bool enable, int xcc_id) 1541 { 1542 u32 tmp; 1543 1544 if (amdgpu_sriov_vf(adev)) 1545 return; 1546 1547 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1548 1549 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1550 enable ? 1 : 0); 1551 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1552 enable ? 1 : 0); 1553 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1554 enable ? 1 : 0); 1555 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1556 enable ? 1 : 0); 1557 1558 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1559 } 1560 1561 static int gfx_v12_1_xcc_init_csb(struct amdgpu_device *adev, 1562 int xcc_id) 1563 { 1564 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1565 1566 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI, 1567 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1568 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO, 1569 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1570 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1571 regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1572 1573 return 0; 1574 } 1575 1576 static void gfx_v12_1_xcc_rlc_stop(struct amdgpu_device *adev, 1577 int xcc_id) 1578 { 1579 u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); 1580 1581 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1582 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); 1583 } 1584 1585 static void gfx_v12_1_rlc_stop(struct amdgpu_device *adev) 1586 { 1587 int i, num_xcc; 1588 1589 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1590 for (i = 0; i < num_xcc; i++) 1591 gfx_v12_1_xcc_rlc_stop(adev, i); 1592 } 1593 1594 static void gfx_v12_1_xcc_rlc_reset(struct amdgpu_device *adev, 1595 int xcc_id) 1596 { 1597 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1598 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1599 udelay(50); 1600 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1601 GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1602 udelay(50); 1603 } 1604 1605 static void gfx_v12_1_rlc_reset(struct amdgpu_device *adev) 1606 { 1607 int i, num_xcc; 1608 1609 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1610 for (i = 0; i < num_xcc; i++) 1611 gfx_v12_1_xcc_rlc_reset(adev, i); 1612 } 1613 1614 static void gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1615 bool enable, int xcc_id) 1616 { 1617 uint32_t rlc_pg_cntl; 1618 1619 rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL); 1620 1621 if (!enable) { 1622 /* RLC_PG_CNTL[23] = 0 (default) 1623 * RLC will wait for handshake acks with SMU 1624 * GFXOFF will be enabled 1625 * RLC_PG_CNTL[23] = 1 1626 * RLC will not issue any message to SMU 1627 * hence no handshake between SMU & RLC 1628 * GFXOFF will be disabled 1629 */ 1630 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1631 } else 1632 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1633 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl); 1634 } 1635 1636 static void gfx_v12_1_xcc_rlc_start(struct amdgpu_device *adev, 1637 int xcc_id) 1638 { 1639 /* TODO: enable rlc & smu handshake until smu 1640 * and gfxoff feature works as expected */ 1641 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1642 gfx_v12_1_xcc_rlc_smu_handshake_cntl(adev, false, xcc_id); 1643 1644 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); 1645 udelay(50); 1646 } 1647 1648 static void gfx_v12_1_rlc_start(struct amdgpu_device *adev) 1649 { 1650 int i, num_xcc; 1651 1652 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1653 for (i = 0; i < num_xcc; i++) { 1654 gfx_v12_1_xcc_rlc_start(adev, i); 1655 } 1656 } 1657 1658 static void gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device *adev, 1659 int xcc_id) 1660 { 1661 uint32_t tmp; 1662 1663 /* enable Save Restore Machine */ 1664 tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL)); 1665 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1666 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1667 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp); 1668 } 1669 1670 static void gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device *adev, 1671 int xcc_id) 1672 { 1673 const struct rlc_firmware_header_v2_0 *hdr; 1674 const __le32 *fw_data; 1675 unsigned i, fw_size; 1676 1677 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1678 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1679 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1680 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1681 1682 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1683 RLCG_UCODE_LOADING_START_ADDRESS); 1684 1685 for (i = 0; i < fw_size; i++) 1686 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1687 regRLC_GPM_UCODE_DATA, 1688 le32_to_cpup(fw_data++)); 1689 1690 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1691 regRLC_GPM_UCODE_ADDR, 1692 adev->gfx.rlc_fw_version); 1693 } 1694 1695 static void gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device *adev, 1696 int xcc_id) 1697 { 1698 const struct rlc_firmware_header_v2_2 *hdr; 1699 const __le32 *fw_data; 1700 unsigned i, fw_size; 1701 u32 tmp; 1702 1703 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1704 1705 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1706 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1707 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1708 1709 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0); 1710 1711 for (i = 0; i < fw_size; i++) { 1712 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1713 msleep(1); 1714 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1715 regRLC_LX6_IRAM_DATA, 1716 le32_to_cpup(fw_data++)); 1717 } 1718 1719 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1720 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1721 1722 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1723 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1724 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1725 1726 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1727 regRLC_LX6_DRAM_ADDR, 0); 1728 for (i = 0; i < fw_size; i++) { 1729 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1730 msleep(1); 1731 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1732 regRLC_LX6_DRAM_DATA, 1733 le32_to_cpup(fw_data++)); 1734 } 1735 1736 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1737 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1738 1739 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL); 1740 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1741 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1742 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp); 1743 } 1744 1745 static int gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1746 int xcc_id) 1747 { 1748 const struct rlc_firmware_header_v2_0 *hdr; 1749 uint16_t version_major; 1750 uint16_t version_minor; 1751 1752 if (!adev->gfx.rlc_fw) 1753 return -EINVAL; 1754 1755 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1756 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1757 1758 version_major = le16_to_cpu(hdr->header.header_version_major); 1759 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1760 1761 if (version_major == 2) { 1762 gfx_v12_1_xcc_load_rlcg_microcode(adev, xcc_id); 1763 if (amdgpu_dpm == 1) { 1764 if (version_minor >= 2) 1765 gfx_v12_1_xcc_load_rlc_iram_dram_microcode(adev, xcc_id); 1766 } 1767 1768 return 0; 1769 } 1770 1771 return -EINVAL; 1772 } 1773 1774 static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, 1775 int xcc_id) 1776 { 1777 int r; 1778 1779 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1780 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1781 1782 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1783 gfx_v12_1_xcc_rlc_enable_srm(adev, xcc_id); 1784 } else { 1785 if (amdgpu_sriov_vf(adev)) { 1786 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1787 return 0; 1788 } 1789 1790 gfx_v12_1_xcc_rlc_stop(adev, xcc_id); 1791 1792 /* disable CG */ 1793 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1794 1795 /* disable PG */ 1796 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0); 1797 1798 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1799 /* legacy rlc firmware loading */ 1800 r = gfx_v12_1_xcc_rlc_load_microcode(adev, xcc_id); 1801 if (r) 1802 return r; 1803 } 1804 1805 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1806 1807 gfx_v12_1_xcc_rlc_start(adev, xcc_id); 1808 } 1809 1810 return 0; 1811 } 1812 1813 static int gfx_v12_1_rlc_resume(struct amdgpu_device *adev) 1814 { 1815 int r, i, num_xcc; 1816 1817 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1818 for (i = 0; i < num_xcc; i++) { 1819 r = gfx_v12_1_xcc_rlc_resume(adev, i); 1820 if (r) 1821 return r; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, 1828 int xcc_id) 1829 { 1830 const struct gfx_firmware_header_v2_0 *mec_hdr; 1831 uint32_t pipe_id, tmp; 1832 1833 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1834 adev->gfx.mec_fw->data; 1835 1836 /* config mec program start addr */ 1837 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 1838 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1839 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1840 mec_hdr->ucode_start_addr_lo >> 2 | 1841 mec_hdr->ucode_start_addr_hi << 30); 1842 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1843 mec_hdr->ucode_start_addr_hi >> 2); 1844 } 1845 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1846 1847 /* reset mec pipe */ 1848 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 1849 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 1850 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 1851 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 1852 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 1853 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1854 1855 /* clear mec pipe reset */ 1856 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 1857 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 1858 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 1859 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 1860 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1861 } 1862 1863 static void gfx_v12_1_config_gfx_rs64(struct amdgpu_device *adev) 1864 { 1865 int i, num_xcc; 1866 1867 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1868 1869 for (i = 0; i < num_xcc; i++) 1870 gfx_v12_1_xcc_config_gfx_rs64(adev, i); 1871 } 1872 1873 static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, 1874 int xcc_id) 1875 { 1876 const struct gfx_firmware_header_v2_0 *cp_hdr; 1877 unsigned pipe_id; 1878 1879 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1880 adev->gfx.mec_fw->data; 1881 mutex_lock(&adev->srbm_mutex); 1882 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 1883 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1884 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1885 cp_hdr->ucode_start_addr_lo >> 2 | 1886 cp_hdr->ucode_start_addr_hi << 30); 1887 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1888 cp_hdr->ucode_start_addr_hi >> 2); 1889 } 1890 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1891 mutex_unlock(&adev->srbm_mutex); 1892 } 1893 1894 static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev, 1895 int xcc_id) 1896 { 1897 uint32_t cp_status; 1898 uint32_t bootload_status; 1899 int i; 1900 1901 for (i = 0; i < adev->usec_timeout; i++) { 1902 cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT); 1903 bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1904 regRLC_RLCS_BOOTLOAD_STATUS); 1905 1906 if ((cp_status == 0) && 1907 (REG_GET_FIELD(bootload_status, 1908 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 1909 break; 1910 } 1911 udelay(1); 1912 if (amdgpu_emu_mode) 1913 msleep(10); 1914 } 1915 1916 if (i >= adev->usec_timeout) { 1917 dev_err(adev->dev, 1918 "rlc autoload: xcc%d gc ucode autoload timeout\n", xcc_id); 1919 return -ETIMEDOUT; 1920 } 1921 1922 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1923 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 1930 { 1931 int xcc_id; 1932 1933 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) 1934 gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id); 1935 1936 return 0; 1937 } 1938 1939 static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, 1940 bool enable, int xcc_id) 1941 { 1942 u32 data; 1943 1944 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 1945 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 1946 enable ? 0 : 1); 1947 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1948 enable ? 0 : 1); 1949 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1950 enable ? 0 : 1); 1951 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1952 enable ? 0 : 1); 1953 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1954 enable ? 0 : 1); 1955 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 1956 enable ? 1 : 0); 1957 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 1958 enable ? 1 : 0); 1959 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 1960 enable ? 1 : 0); 1961 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 1962 enable ? 1 : 0); 1963 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 1964 enable ? 0 : 1); 1965 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); 1966 1967 adev->gfx.kiq[xcc_id].ring.sched.ready = enable; 1968 1969 udelay(50); 1970 } 1971 1972 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev) 1973 { 1974 const struct gfx_firmware_header_v2_0 *mec_hdr; 1975 const __le32 *fw_ucode, *fw_data; 1976 u32 fw_ucode_size, fw_data_size; 1977 u32 *fw_ucode_ptr, *fw_data_ptr; 1978 int i, r, xcc_id; 1979 1980 if (!adev->gfx.mec_fw) 1981 return -EINVAL; 1982 1983 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 1984 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1985 1986 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 1987 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 1988 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 1989 1990 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1991 le32_to_cpu(mec_hdr->data_offset_bytes)); 1992 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 1993 1994 if (adev->gfx.mec.mec_fw_obj == NULL) { 1995 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 1996 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 1997 &adev->gfx.mec.mec_fw_obj, 1998 &adev->gfx.mec.mec_fw_gpu_addr, 1999 (void **)&fw_ucode_ptr); 2000 if (r) { 2001 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2002 gfx_v12_1_mec_fini(adev); 2003 return r; 2004 } 2005 2006 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2007 2008 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2009 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2010 } 2011 2012 if (adev->gfx.mec.mec_fw_data_obj == NULL) { 2013 r = amdgpu_bo_create_reserved(adev, 2014 ALIGN(fw_data_size, 64 * 1024) * 2015 adev->gfx.mec.num_pipe_per_mec * NUM_XCC(adev->gfx.xcc_mask), 2016 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2017 &adev->gfx.mec.mec_fw_data_obj, 2018 &adev->gfx.mec.mec_fw_data_gpu_addr, 2019 (void **)&fw_data_ptr); 2020 if (r) { 2021 dev_err(adev->dev, "(%d) failed to create mec fw data bo\n", r); 2022 gfx_v12_1_mec_fini(adev); 2023 return r; 2024 } 2025 2026 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 2027 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2028 u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2029 ALIGN(fw_data_size, 64 * 1024) / 4; 2030 memcpy(fw_data_ptr + offset, fw_data, fw_data_size); 2031 } 2032 } 2033 2034 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2035 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2036 } 2037 2038 return 0; 2039 } 2040 2041 static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, 2042 int xcc_id) 2043 { 2044 const struct gfx_firmware_header_v2_0 *mec_hdr; 2045 u32 fw_data_size; 2046 u32 tmp, i, usec_timeout = 50000; /* Wait for 50 ms */ 2047 2048 if (!adev->gfx.mec_fw) 2049 return -EINVAL; 2050 2051 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2052 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2053 2054 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2055 2056 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); 2057 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2058 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2059 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2060 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 2061 2062 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); 2063 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2064 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2065 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); 2066 2067 mutex_lock(&adev->srbm_mutex); 2068 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2069 soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); 2070 2071 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, 2072 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2073 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2074 ALIGN(fw_data_size, 64 * 1024))); 2075 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, 2076 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2077 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2078 ALIGN(fw_data_size, 64 * 1024))); 2079 2080 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 2081 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2082 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 2083 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2084 } 2085 mutex_unlock(&adev->srbm_mutex); 2086 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2087 2088 /* Trigger an invalidation of the L1 instruction caches */ 2089 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2090 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2091 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); 2092 2093 /* Wait for invalidation complete */ 2094 for (i = 0; i < usec_timeout; i++) { 2095 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2096 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2097 INVALIDATE_DCACHE_COMPLETE)) 2098 break; 2099 udelay(1); 2100 } 2101 2102 if (i >= usec_timeout) { 2103 dev_err(adev->dev, "failed to invalidate data cache\n"); 2104 return -EINVAL; 2105 } 2106 2107 /* Trigger an invalidation of the L1 instruction caches */ 2108 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2109 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2110 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); 2111 2112 /* Wait for invalidation complete */ 2113 for (i = 0; i < usec_timeout; i++) { 2114 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2115 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2116 INVALIDATE_CACHE_COMPLETE)) 2117 break; 2118 udelay(1); 2119 } 2120 2121 if (i >= usec_timeout) { 2122 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2123 return -EINVAL; 2124 } 2125 2126 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2127 2128 return 0; 2129 } 2130 2131 static void gfx_v12_1_xcc_kiq_setting(struct amdgpu_ring *ring, 2132 int xcc_id) 2133 { 2134 uint32_t tmp; 2135 struct amdgpu_device *adev = ring->adev; 2136 2137 /* tell RLC which is KIQ queue */ 2138 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2139 tmp &= 0xffffff00; 2140 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2141 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2142 tmp |= 0x80; 2143 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2144 } 2145 2146 static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev, 2147 int xcc_id) 2148 { 2149 /* disable gfx engine doorbell range */ 2150 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0); 2151 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0); 2152 2153 /* set compute engine doorbell range */ 2154 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER, 2155 ((adev->doorbell_index.kiq + 2156 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2157 2) << 2); 2158 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER, 2159 ((adev->doorbell_index.userqueue_end + 2160 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2161 2) << 2); 2162 } 2163 2164 static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, 2165 struct amdgpu_mqd_prop *prop) 2166 { 2167 struct v12_1_compute_mqd *mqd = m; 2168 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2169 uint32_t tmp; 2170 2171 mqd->header = 0xC0310800; 2172 mqd->compute_pipelinestat_enable = 0x00000001; 2173 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2174 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2175 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2176 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2177 mqd->compute_misc_reserved = 0x00000007; 2178 2179 eop_base_addr = prop->eop_gpu_addr >> 8; 2180 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2181 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2182 2183 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2184 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 2185 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2186 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 2187 2188 mqd->cp_hqd_eop_control = tmp; 2189 2190 /* enable doorbell? */ 2191 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2192 2193 if (prop->use_doorbell) { 2194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2195 DOORBELL_OFFSET, prop->doorbell_index); 2196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2197 DOORBELL_EN, 1); 2198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2199 DOORBELL_SOURCE, 0); 2200 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2201 DOORBELL_HIT, 0); 2202 } else { 2203 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2204 DOORBELL_EN, 0); 2205 } 2206 2207 mqd->cp_hqd_pq_doorbell_control = tmp; 2208 2209 /* disable the queue if it's active */ 2210 mqd->cp_hqd_dequeue_request = 0; 2211 mqd->cp_hqd_pq_rptr = 0; 2212 mqd->cp_hqd_pq_wptr_lo = 0; 2213 mqd->cp_hqd_pq_wptr_hi = 0; 2214 2215 /* set the pointer to the MQD */ 2216 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 2217 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2218 2219 /* set MQD vmid to 0 */ 2220 tmp = regCP_MQD_CONTROL_DEFAULT; 2221 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2222 mqd->cp_mqd_control = tmp; 2223 2224 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2225 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2226 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2227 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2228 2229 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2230 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 2231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2232 (order_base_2(prop->queue_size / 4) - 1)); 2233 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2234 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 2235 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2236 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 2237 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2238 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2239 mqd->cp_hqd_pq_control = tmp; 2240 2241 /* set the wb address whether it's enabled or not */ 2242 wb_gpu_addr = prop->rptr_gpu_addr; 2243 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2244 mqd->cp_hqd_pq_rptr_report_addr_hi = 2245 upper_32_bits(wb_gpu_addr) & 0xffff; 2246 2247 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2248 wb_gpu_addr = prop->wptr_gpu_addr; 2249 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2250 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2251 2252 tmp = 0; 2253 /* enable the doorbell if requested */ 2254 if (prop->use_doorbell) { 2255 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2256 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2257 DOORBELL_OFFSET, prop->doorbell_index); 2258 2259 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2260 DOORBELL_EN, 1); 2261 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2262 DOORBELL_SOURCE, 0); 2263 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2264 DOORBELL_HIT, 0); 2265 } 2266 2267 mqd->cp_hqd_pq_doorbell_control = tmp; 2268 2269 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2270 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 2271 2272 /* set the vmid for the queue */ 2273 mqd->cp_hqd_vmid = 0; 2274 2275 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 2276 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63); 2277 mqd->cp_hqd_persistent_state = tmp; 2278 2279 /* set MIN_IB_AVAIL_SIZE */ 2280 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 2281 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1); 2282 mqd->cp_hqd_ib_control = tmp; 2283 2284 /* set static priority for a compute queue/ring */ 2285 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 2286 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2287 2288 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : 2289 AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); 2290 2291 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 2292 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 2293 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 2294 mqd->cp_hqd_quantum = tmp; 2295 2296 mqd->cp_hqd_active = prop->hqd_active; 2297 2298 return 0; 2299 } 2300 2301 static int gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring *ring, 2302 int xcc_id) 2303 { 2304 struct amdgpu_device *adev = ring->adev; 2305 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2306 int j; 2307 2308 /* inactivate the queue */ 2309 if (amdgpu_sriov_vf(adev)) 2310 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2311 2312 /* disable wptr polling */ 2313 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2314 2315 /* write the EOP addr */ 2316 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 2317 mqd->cp_hqd_eop_base_addr_lo); 2318 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 2319 mqd->cp_hqd_eop_base_addr_hi); 2320 2321 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2322 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 2323 mqd->cp_hqd_eop_control); 2324 2325 /* enable doorbell? */ 2326 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2327 mqd->cp_hqd_pq_doorbell_control); 2328 2329 /* disable the queue if it's active */ 2330 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2331 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2332 for (j = 0; j < adev->usec_timeout; j++) { 2333 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2334 break; 2335 udelay(1); 2336 } 2337 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2338 mqd->cp_hqd_dequeue_request); 2339 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 2340 mqd->cp_hqd_pq_rptr); 2341 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2342 mqd->cp_hqd_pq_wptr_lo); 2343 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2344 mqd->cp_hqd_pq_wptr_hi); 2345 } 2346 2347 /* set the pointer to the MQD */ 2348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2349 mqd->cp_mqd_base_addr_lo); 2350 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2351 mqd->cp_mqd_base_addr_hi); 2352 2353 /* set MQD vmid to 0 */ 2354 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2355 mqd->cp_mqd_control); 2356 2357 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2358 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2359 mqd->cp_hqd_pq_base_lo); 2360 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2361 mqd->cp_hqd_pq_base_hi); 2362 2363 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2364 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2365 mqd->cp_hqd_pq_control); 2366 2367 /* set the wb address whether it's enabled or not */ 2368 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2369 mqd->cp_hqd_pq_rptr_report_addr_lo); 2370 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2371 mqd->cp_hqd_pq_rptr_report_addr_hi); 2372 2373 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2374 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2375 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2376 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2377 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2378 2379 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2380 mqd->cp_hqd_pq_doorbell_control); 2381 2382 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2383 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2384 mqd->cp_hqd_pq_wptr_lo); 2385 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2386 mqd->cp_hqd_pq_wptr_hi); 2387 2388 /* set the vmid for the queue */ 2389 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2390 2391 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2392 mqd->cp_hqd_persistent_state); 2393 2394 /* activate the queue */ 2395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2396 mqd->cp_hqd_active); 2397 2398 if (ring->use_doorbell) 2399 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2400 2401 return 0; 2402 } 2403 2404 static int gfx_v12_1_xcc_kiq_init_queue(struct amdgpu_ring *ring, 2405 int xcc_id) 2406 { 2407 struct amdgpu_device *adev = ring->adev; 2408 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2409 2410 gfx_v12_1_xcc_kiq_setting(ring, xcc_id); 2411 2412 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 2413 /* reset MQD to a clean status */ 2414 if (adev->gfx.kiq[xcc_id].mqd_backup) 2415 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(*mqd)); 2416 2417 /* reset ring buffer */ 2418 ring->wptr = 0; 2419 amdgpu_ring_clear_ring(ring); 2420 2421 mutex_lock(&adev->srbm_mutex); 2422 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2423 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2424 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2425 mutex_unlock(&adev->srbm_mutex); 2426 } else { 2427 memset((void *)mqd, 0, sizeof(*mqd)); 2428 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2429 amdgpu_ring_clear_ring(ring); 2430 mutex_lock(&adev->srbm_mutex); 2431 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2432 amdgpu_ring_init_mqd(ring); 2433 gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); 2434 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2435 mutex_unlock(&adev->srbm_mutex); 2436 2437 if (adev->gfx.kiq[xcc_id].mqd_backup) 2438 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(*mqd)); 2439 } 2440 2441 return 0; 2442 } 2443 2444 static int gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring *ring, 2445 int xcc_id) 2446 { 2447 struct amdgpu_device *adev = ring->adev; 2448 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2449 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2450 2451 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2452 memset((void *)mqd, 0, sizeof(*mqd)); 2453 mutex_lock(&adev->srbm_mutex); 2454 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2455 amdgpu_ring_init_mqd(ring); 2456 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2457 mutex_unlock(&adev->srbm_mutex); 2458 2459 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2460 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2461 } else { 2462 /* restore MQD to a clean status */ 2463 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2464 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2465 /* reset ring buffer */ 2466 ring->wptr = 0; 2467 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 2468 amdgpu_ring_clear_ring(ring); 2469 } 2470 2471 return 0; 2472 } 2473 2474 static int gfx_v12_1_xcc_kiq_resume(struct amdgpu_device *adev, 2475 int xcc_id) 2476 { 2477 struct amdgpu_ring *ring; 2478 int r; 2479 2480 ring = &adev->gfx.kiq[xcc_id].ring; 2481 2482 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2483 if (unlikely(r != 0)) 2484 return r; 2485 2486 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2487 if (unlikely(r != 0)) { 2488 amdgpu_bo_unreserve(ring->mqd_obj); 2489 return r; 2490 } 2491 2492 gfx_v12_1_xcc_kiq_init_queue(ring, xcc_id); 2493 amdgpu_bo_kunmap(ring->mqd_obj); 2494 ring->mqd_ptr = NULL; 2495 amdgpu_bo_unreserve(ring->mqd_obj); 2496 ring->sched.ready = true; 2497 return 0; 2498 } 2499 2500 static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, 2501 int xcc_id) 2502 { 2503 struct amdgpu_ring *ring = NULL; 2504 int r = 0, i; 2505 2506 if (!amdgpu_async_gfx_ring) 2507 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2508 2509 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2510 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2511 2512 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2513 if (unlikely(r != 0)) 2514 goto done; 2515 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2516 if (!r) { 2517 r = gfx_v12_1_xcc_kcq_init_queue(ring, xcc_id); 2518 amdgpu_bo_kunmap(ring->mqd_obj); 2519 ring->mqd_ptr = NULL; 2520 } 2521 amdgpu_bo_unreserve(ring->mqd_obj); 2522 if (r) 2523 goto done; 2524 } 2525 2526 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2527 done: 2528 return r; 2529 } 2530 2531 static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) 2532 { 2533 int r, i, xcc_id; 2534 struct amdgpu_ring *ring; 2535 2536 for_each_inst(xcc_id, xcc_mask) { 2537 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2538 /* legacy firmware loading */ 2539 r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); 2540 if (r) 2541 return r; 2542 } 2543 2544 /* GFX CGCG and LS is set by default */ 2545 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2546 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2547 2548 gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); 2549 2550 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2551 2552 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) { 2553 r = amdgpu_mes_kiq_hw_init(adev, xcc_id); 2554 /* 2555 * With MES, GFX KIQ ring is owned by the MES and is never 2556 * initialized/used directly by the driver, so it must 2557 * not be left flagged as ready. mes_v12_0_hw_init() clears 2558 * but clear here if MES init fails 2559 */ 2560 if (r) 2561 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 2562 } else { 2563 r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); 2564 } 2565 if (r) 2566 return r; 2567 2568 r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); 2569 if (r) 2570 return r; 2571 2572 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2573 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2574 r = amdgpu_ring_test_helper(ring); 2575 if (r) 2576 return r; 2577 } 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int gfx_v12_1_cp_resume(struct amdgpu_device *adev) 2584 { 2585 int num_xcc, num_xcp, num_xcc_per_xcp; 2586 uint16_t xcc_mask; 2587 int r = 0; 2588 2589 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2590 if (amdgpu_sriov_vf(adev)) { 2591 enum amdgpu_gfx_partition mode; 2592 2593 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2594 AMDGPU_XCP_FL_NONE); 2595 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2596 return -EINVAL; 2597 if (adev->gfx.funcs && 2598 adev->gfx.funcs->get_xccs_per_xcp) { 2599 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 2600 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2601 num_xcp = num_xcc / num_xcc_per_xcp; 2602 } else { 2603 return -EINVAL; 2604 } 2605 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2606 2607 } else { 2608 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2609 AMDGPU_XCP_FL_NONE) == 2610 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2611 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2612 amdgpu_user_partt_mode); 2613 } 2614 2615 if (r) 2616 return r; 2617 2618 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 2619 2620 return gfx_v12_1_xcc_cp_resume(adev, xcc_mask); 2621 } 2622 2623 static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev) 2624 { 2625 int r, i; 2626 bool value; 2627 2628 r = adev->gfxhub.funcs->gart_enable(adev); 2629 if (r) 2630 return r; 2631 2632 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 2633 false : true; 2634 2635 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2636 /* TODO investigate why TLB flush is needed, 2637 * are we missing a flush somewhere else? */ 2638 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2639 if (AMDGPU_IS_GFXHUB(i)) 2640 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0); 2641 } 2642 2643 return 0; 2644 } 2645 2646 static int get_gb_addr_config(struct amdgpu_device *adev) 2647 { 2648 u32 gb_addr_config; 2649 2650 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ); 2651 if (gb_addr_config == 0) 2652 return -EINVAL; 2653 2654 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2655 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG_READ, NUM_PKRS); 2656 2657 adev->gfx.config.gb_addr_config = gb_addr_config; 2658 2659 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2660 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2661 GB_ADDR_CONFIG_READ, NUM_PIPES); 2662 2663 adev->gfx.config.max_tile_pipes = 2664 adev->gfx.config.gb_addr_config_fields.num_pipes; 2665 2666 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2667 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2668 GB_ADDR_CONFIG_READ, MAX_COMPRESSED_FRAGS); 2669 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2670 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2671 GB_ADDR_CONFIG_READ, NUM_RB_PER_SE); 2672 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2673 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2674 GB_ADDR_CONFIG_READ, NUM_SHADER_ENGINES); 2675 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2676 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 2677 GB_ADDR_CONFIG_READ, PIPE_INTERLEAVE_SIZE)); 2678 2679 return 0; 2680 } 2681 2682 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, 2683 int xcc_id) 2684 { 2685 uint32_t data; 2686 2687 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 2688 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 2689 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 2690 2691 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG); 2692 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 2693 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); 2694 } 2695 2696 static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, 2697 int xcc_id) 2698 { 2699 uint32_t data; 2700 2701 /* Set the TCP UTCL0 register to enable atomics */ 2702 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); 2703 data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); 2704 2705 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); 2706 } 2707 2708 static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, 2709 int xcc_id) 2710 { 2711 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); 2712 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); 2713 } 2714 2715 static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, 2716 int xcc_id) 2717 { 2718 uint32_t data; 2719 2720 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3); 2721 data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1); 2722 2723 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); 2724 } 2725 2726 static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, 2727 int xcc_id) 2728 { 2729 uint32_t data; 2730 2731 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); 2732 data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); 2733 2734 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); 2735 } 2736 2737 static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) 2738 { 2739 int i; 2740 2741 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { 2742 gfx_v12_1_xcc_disable_burst(adev, i); 2743 gfx_v12_1_xcc_enable_atomics(adev, i); 2744 gfx_v12_1_xcc_disable_early_write_ack(adev, i); 2745 gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); 2746 } 2747 } 2748 2749 static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, 2750 bool enable) 2751 { 2752 unsigned int irq_type; 2753 int m, p, r; 2754 2755 if (!adev->gfx.disable_kq) 2756 return 0; 2757 2758 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 2759 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 2760 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2761 + (m * adev->gfx.mec.num_pipe_per_mec) 2762 + p; 2763 if (enable) 2764 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 2765 else 2766 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2767 if (r) { 2768 if (!enable) 2769 return r; 2770 goto err_unwind; 2771 } 2772 } 2773 } 2774 2775 return 0; 2776 2777 err_unwind: 2778 for (p--; p >= 0; p--) { 2779 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2780 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2781 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2782 } 2783 for (m--; m >= 0; m--) { 2784 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2785 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2786 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2787 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2788 } 2789 } 2790 return r; 2791 } 2792 2793 static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 2794 { 2795 int r, i, num_xcc; 2796 struct amdgpu_device *adev = ip_block->adev; 2797 2798 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2799 /* rlc autoload firmware */ 2800 r = gfx_v12_1_rlc_backdoor_autoload_enable(adev); 2801 if (r) 2802 return r; 2803 } else { 2804 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2805 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2806 2807 if (adev->gfx.imu.funcs) { 2808 if (adev->gfx.imu.funcs->load_microcode) 2809 adev->gfx.imu.funcs->load_microcode(adev); 2810 } 2811 2812 for (i = 0; i < num_xcc; i++) { 2813 /* disable gpa mode in backdoor loading */ 2814 gfx_v12_1_xcc_disable_gpa_mode(adev, i); 2815 } 2816 } 2817 } 2818 2819 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 2820 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2821 r = gfx_v12_1_wait_for_rlc_autoload_complete(adev); 2822 if (r) { 2823 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 2824 return r; 2825 } 2826 } 2827 2828 adev->gfx.is_poweron = true; 2829 2830 if (get_gb_addr_config(adev)) 2831 DRM_WARN("Invalid gb_addr_config !\n"); 2832 2833 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2834 gfx_v12_1_config_gfx_rs64(adev); 2835 2836 r = gfx_v12_1_gfxhub_enable(adev); 2837 if (r) 2838 return r; 2839 2840 gfx_v12_1_init_golden_registers(adev); 2841 2842 gfx_v12_1_constants_init(adev); 2843 2844 if (adev->nbio.funcs->gc_doorbell_init) 2845 adev->nbio.funcs->gc_doorbell_init(adev); 2846 2847 r = gfx_v12_1_rlc_resume(adev); 2848 if (r) 2849 return r; 2850 2851 /* 2852 * init golden registers and rlc resume may override some registers, 2853 * reconfig them here 2854 */ 2855 gfx_v12_1_tcp_harvest(adev); 2856 2857 r = gfx_v12_1_cp_resume(adev); 2858 if (r) 2859 return r; 2860 2861 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2862 if (r) 2863 return r; 2864 2865 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2866 if (r) 2867 goto err_priv_inst; 2868 2869 r = gfx_v12_1_set_userq_eop_interrupts(adev, true); 2870 if (r) 2871 goto err_userq_eop; 2872 2873 return 0; 2874 2875 err_userq_eop: 2876 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2877 err_priv_inst: 2878 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2879 return r; 2880 } 2881 2882 static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, 2883 int xcc_id) 2884 { 2885 uint32_t tmp; 2886 2887 if (!adev->no_hw_access) { 2888 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2889 DRM_ERROR("KCQ disable failed\n"); 2890 2891 amdgpu_mes_kiq_hw_fini(adev, xcc_id); 2892 } 2893 2894 if (amdgpu_sriov_vf(adev)) { 2895 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 2896 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2897 tmp &= 0xffffff00; 2898 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2899 } 2900 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2901 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2902 } 2903 2904 static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 2905 { 2906 struct amdgpu_device *adev = ip_block->adev; 2907 int i, num_xcc; 2908 2909 gfx_v12_1_set_userq_eop_interrupts(adev, false); 2910 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2911 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2912 2913 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2914 for (i = 0; i < num_xcc; i++) { 2915 gfx_v12_1_xcc_fini(adev, i); 2916 } 2917 2918 adev->gfxhub.funcs->gart_disable(adev); 2919 2920 adev->gfx.is_poweron = false; 2921 2922 return 0; 2923 } 2924 2925 static int gfx_v12_1_suspend(struct amdgpu_ip_block *ip_block) 2926 { 2927 return gfx_v12_1_hw_fini(ip_block); 2928 } 2929 2930 static int gfx_v12_1_resume(struct amdgpu_ip_block *ip_block) 2931 { 2932 return gfx_v12_1_hw_init(ip_block); 2933 } 2934 2935 static bool gfx_v12_1_is_idle(struct amdgpu_ip_block *ip_block) 2936 { 2937 struct amdgpu_device *adev = ip_block->adev; 2938 int i, num_xcc; 2939 2940 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2941 for (i = 0; i < num_xcc; i++) { 2942 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), 2943 regGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 2944 return false; 2945 } 2946 return true; 2947 } 2948 2949 static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 2950 { 2951 unsigned i; 2952 struct amdgpu_device *adev = ip_block->adev; 2953 2954 for (i = 0; i < adev->usec_timeout; i++) { 2955 if (gfx_v12_1_is_idle(ip_block)) 2956 return 0; 2957 udelay(1); 2958 } 2959 return -ETIMEDOUT; 2960 } 2961 2962 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) 2963 { 2964 uint64_t clock = 0; 2965 2966 if (adev->smuio.funcs && 2967 adev->smuio.funcs->get_gpu_clock_counter) 2968 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 2969 else 2970 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 2971 2972 return clock; 2973 } 2974 2975 static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) 2976 { 2977 struct amdgpu_device *adev = ip_block->adev; 2978 2979 2980 switch (amdgpu_user_queue) { 2981 case -1: 2982 default: 2983 adev->gfx.disable_kq = true; 2984 adev->gfx.disable_uq = true; 2985 break; 2986 case 0: 2987 adev->gfx.disable_kq = false; 2988 adev->gfx.disable_uq = true; 2989 break; 2990 } 2991 2992 adev->gfx.funcs = &gfx_v12_1_gfx_funcs; 2993 2994 if (adev->gfx.disable_kq) 2995 adev->gfx.num_compute_rings = 0; 2996 else 2997 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2998 AMDGPU_MAX_COMPUTE_RINGS); 2999 3000 gfx_v12_1_set_kiq_pm4_funcs(adev); 3001 gfx_v12_1_set_ring_funcs(adev); 3002 gfx_v12_1_set_irq_funcs(adev); 3003 gfx_v12_1_set_rlc_funcs(adev); 3004 gfx_v12_1_set_mqd_funcs(adev); 3005 gfx_v12_1_set_imu_funcs(adev); 3006 3007 gfx_v12_1_init_rlcg_reg_access_ctrl(adev); 3008 3009 amdgpu_init_rlc_reg_funcs(adev); 3010 3011 return gfx_v12_1_init_microcode(adev); 3012 } 3013 3014 static bool gfx_v12_1_is_rlc_enabled(struct amdgpu_device *adev) 3015 { 3016 uint32_t rlc_cntl; 3017 3018 /* if RLC is not enabled, do nothing */ 3019 rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 3020 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3021 } 3022 3023 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, 3024 int xcc_id) 3025 { 3026 uint32_t data; 3027 unsigned i; 3028 3029 data = RLC_SAFE_MODE__CMD_MASK; 3030 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3031 3032 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 3033 3034 /* wait for RLC_SAFE_MODE */ 3035 for (i = 0; i < adev->usec_timeout; i++) { 3036 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3037 regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3038 break; 3039 udelay(1); 3040 } 3041 } 3042 3043 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, 3044 int xcc_id) 3045 { 3046 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3047 regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3048 } 3049 3050 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 3051 bool enable) 3052 { 3053 int i, num_xcc; 3054 3055 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3056 for (i = 0; i < num_xcc; i++) 3057 gfx_v12_1_xcc_update_perf_clk(adev, enable, i); 3058 } 3059 3060 static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, 3061 int xcc_id, 3062 struct amdgpu_ring *ring, 3063 unsigned vmid) 3064 { 3065 u32 reg, data; 3066 3067 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3068 if (amdgpu_sriov_is_pp_one_vf(adev)) 3069 data = RREG32_NO_KIQ(reg); 3070 else 3071 data = RREG32(reg); 3072 3073 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3074 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3075 3076 if (amdgpu_sriov_is_pp_one_vf(adev)) 3077 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3078 else 3079 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 3080 3081 if (ring 3082 && amdgpu_sriov_is_pp_one_vf(adev) 3083 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3084 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3085 uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 3086 amdgpu_ring_emit_wreg(ring, reg, data); 3087 } 3088 } 3089 3090 static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = { 3091 .is_rlc_enabled = gfx_v12_1_is_rlc_enabled, 3092 .set_safe_mode = gfx_v12_1_xcc_set_safe_mode, 3093 .unset_safe_mode = gfx_v12_1_xcc_unset_safe_mode, 3094 .init = gfx_v12_1_rlc_init, 3095 .get_csb_size = gfx_v12_1_get_csb_size, 3096 .get_csb_buffer = gfx_v12_1_get_csb_buffer, 3097 .resume = gfx_v12_1_rlc_resume, 3098 .stop = gfx_v12_1_rlc_stop, 3099 .reset = gfx_v12_1_rlc_reset, 3100 .start = gfx_v12_1_rlc_start, 3101 .update_spm_vmid = gfx_v12_1_update_spm_vmid, 3102 }; 3103 3104 #if 0 3105 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3106 { 3107 /* TODO */ 3108 } 3109 3110 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3111 { 3112 /* TODO */ 3113 } 3114 #endif 3115 3116 static int gfx_v12_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 3117 enum amd_powergating_state state) 3118 { 3119 struct amdgpu_device *adev = ip_block->adev; 3120 bool enable = (state == AMD_PG_STATE_GATE); 3121 3122 if (amdgpu_sriov_vf(adev)) 3123 return 0; 3124 3125 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3126 case IP_VERSION(12, 1, 0): 3127 amdgpu_gfx_off_ctrl(adev, enable); 3128 break; 3129 default: 3130 break; 3131 } 3132 3133 return 0; 3134 } 3135 3136 static void gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3137 bool enable, int xcc_id) 3138 { 3139 uint32_t def, data; 3140 3141 if (!(adev->cg_flags & 3142 (AMD_CG_SUPPORT_GFX_CGCG | 3143 AMD_CG_SUPPORT_GFX_CGLS | 3144 AMD_CG_SUPPORT_GFX_3D_CGCG | 3145 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3146 return; 3147 3148 if (enable) { 3149 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3150 regRLC_CGTT_MGCG_OVERRIDE); 3151 3152 /* unset CGCG override */ 3153 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3154 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3155 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3156 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3157 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3158 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3159 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3160 3161 /* update CGCG override bits */ 3162 if (def != data) 3163 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3164 regRLC_CGTT_MGCG_OVERRIDE, data); 3165 3166 /* enable cgcg FSM(0x0000363F) */ 3167 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3168 3169 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3170 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3171 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3172 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3173 } 3174 3175 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3176 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3177 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3178 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3179 } 3180 3181 if (def != data) 3182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3183 regRLC_CGCG_CGLS_CTRL, data); 3184 3185 /* set IDLE_POLL_COUNT(0x00900100) */ 3186 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 3187 3188 data &= ~CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK; 3189 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3190 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3191 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3192 3193 if (def != data) 3194 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 3195 3196 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL); 3197 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3198 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3199 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3200 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3201 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data); 3202 } else { 3203 /* Program RLC_CGCG_CGLS_CTRL */ 3204 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3205 3206 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3207 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3208 3209 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3210 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3211 3212 if (def != data) 3213 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 3214 } 3215 } 3216 3217 static void gfx_v12_1_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3218 bool enable, int xcc_id) 3219 { 3220 uint32_t data, def; 3221 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 3222 return; 3223 3224 /* It is disabled by HW by default */ 3225 if (enable) { 3226 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3227 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3228 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3229 3230 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3231 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3232 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3233 3234 if (def != data) 3235 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3236 } 3237 } else { 3238 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3239 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3240 3241 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3242 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3243 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3244 3245 if (def != data) 3246 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3247 } 3248 } 3249 } 3250 3251 static void gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 3252 bool enable, int xcc_id) 3253 { 3254 uint32_t def, data; 3255 3256 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 3257 return; 3258 3259 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3260 3261 if (enable) 3262 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3263 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 3264 else 3265 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3266 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 3267 3268 if (def != data) 3269 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3270 } 3271 3272 static void gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device *adev, 3273 bool enable, int xcc_id) 3274 { 3275 uint32_t def, data; 3276 3277 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 3278 return; 3279 3280 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3281 3282 if (enable) 3283 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3284 else 3285 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3286 3287 if (def != data) 3288 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3289 } 3290 3291 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 3292 bool enable, int xcc_id) 3293 { 3294 uint32_t def, data; 3295 3296 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3297 return; 3298 3299 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3300 3301 if (enable) 3302 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3303 else 3304 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3305 3306 if (def != data) 3307 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3308 } 3309 3310 static int gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 3311 bool enable, int xcc_id) 3312 { 3313 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3314 3315 gfx_v12_1_xcc_update_coarse_grain_clock_gating(adev, enable, xcc_id); 3316 3317 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, enable, xcc_id); 3318 3319 gfx_v12_1_xcc_update_repeater_fgcg(adev, enable, xcc_id); 3320 3321 gfx_v12_1_xcc_update_sram_fgcg(adev, enable, xcc_id); 3322 3323 gfx_v12_1_xcc_update_perf_clk(adev, enable, xcc_id); 3324 3325 if (adev->cg_flags & 3326 (AMD_CG_SUPPORT_GFX_MGCG | 3327 AMD_CG_SUPPORT_GFX_CGLS | 3328 AMD_CG_SUPPORT_GFX_CGCG | 3329 AMD_CG_SUPPORT_GFX_3D_CGCG | 3330 AMD_CG_SUPPORT_GFX_3D_CGLS)) 3331 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, enable, xcc_id); 3332 3333 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 3334 3335 return 0; 3336 } 3337 3338 static int gfx_v12_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3339 enum amd_clockgating_state state) 3340 { 3341 struct amdgpu_device *adev = ip_block->adev; 3342 int i, num_xcc; 3343 3344 if (amdgpu_sriov_vf(adev)) 3345 return 0; 3346 3347 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3348 switch (adev->ip_versions[GC_HWIP][0]) { 3349 case IP_VERSION(12, 1, 0): 3350 for (i = 0; i < num_xcc; i++) 3351 gfx_v12_1_xcc_update_gfx_clock_gating(adev, 3352 state == AMD_CG_STATE_GATE, i); 3353 break; 3354 default: 3355 break; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static void gfx_v12_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 3362 { 3363 struct amdgpu_device *adev = ip_block->adev; 3364 int data; 3365 3366 /* AMD_CG_SUPPORT_GFX_MGCG */ 3367 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE); 3368 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3369 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3370 3371 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 3372 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 3373 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 3374 3375 /* AMD_CG_SUPPORT_GFX_FGCG */ 3376 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 3377 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 3378 3379 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 3380 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 3381 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 3382 3383 /* AMD_CG_SUPPORT_GFX_CGCG */ 3384 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); 3385 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3386 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3387 3388 /* AMD_CG_SUPPORT_GFX_CGLS */ 3389 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3390 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3391 } 3392 3393 static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring) 3394 { 3395 /* gfx12 hardware is 32bit rptr */ 3396 return *(uint32_t *)ring->rptr_cpu_addr; 3397 } 3398 3399 static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring) 3400 { 3401 u64 wptr; 3402 3403 /* XXX check if swapping is necessary on BE */ 3404 if (ring->use_doorbell) 3405 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3406 else 3407 BUG(); 3408 return wptr; 3409 } 3410 3411 static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring) 3412 { 3413 struct amdgpu_device *adev = ring->adev; 3414 3415 /* XXX check if swapping is necessary on BE */ 3416 if (ring->use_doorbell) { 3417 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 3418 ring->wptr); 3419 WDOORBELL64(ring->doorbell_index, ring->wptr); 3420 } else { 3421 BUG(); /* only DOORBELL method supported on gfx12 now */ 3422 } 3423 } 3424 3425 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, 3426 struct amdgpu_job *job, 3427 struct amdgpu_ib *ib, 3428 uint32_t flags) 3429 { 3430 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3431 u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); 3432 3433 /* Currently, there is a high possibility to get wave ID mismatch 3434 * between ME and GDS, leading to a hw deadlock, because ME generates 3435 * different wave IDs than the GDS expects. This situation happens 3436 * randomly when at least 5 compute pipes use GDS ordered append. 3437 * The wave IDs generated by ME are also wrong after suspend/resume. 3438 * Those are probably bugs somewhere else in the kernel driver. 3439 * 3440 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 3441 * GDS to 0 for this ring (me/pipe). 3442 */ 3443 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 3444 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3445 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 3446 } 3447 3448 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3449 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 3450 amdgpu_ring_write(ring, 3451 #ifdef __BIG_ENDIAN 3452 (2 << 0) | 3453 #endif 3454 lower_32_bits(ib->gpu_addr)); 3455 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3456 amdgpu_ring_write(ring, control); 3457 } 3458 3459 static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3460 u64 seq, unsigned flags) 3461 { 3462 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3463 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3464 3465 /* RELEASE_MEM - flush caches, send int */ 3466 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3467 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | 3468 PACKET3_RELEASE_MEM__GCR_GLV_WB | 3469 PACKET3_RELEASE_MEM__GCR_GL2_WB | 3470 PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | 3471 PACKET3_RELEASE_MEM__TEMPORAL(3) | 3472 PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3473 PACKET3_RELEASE_MEM__EVENT_INDEX(5))); 3474 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | 3475 PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); 3476 3477 /* 3478 * the address should be Qword aligned if 64bit write, Dword 3479 * aligned if only send 32bit data low (discard data high) 3480 */ 3481 if (write64bit) 3482 WARN_ON(addr & 0x7); 3483 else 3484 WARN_ON(addr & 0x3); 3485 amdgpu_ring_write(ring, lower_32_bits(addr)); 3486 amdgpu_ring_write(ring, upper_32_bits(addr)); 3487 amdgpu_ring_write(ring, lower_32_bits(seq)); 3488 amdgpu_ring_write(ring, upper_32_bits(seq)); 3489 amdgpu_ring_write(ring, 0); 3490 } 3491 3492 static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3493 { 3494 uint32_t seq = ring->fence_drv.sync_seq; 3495 uint64_t addr = ring->fence_drv.gpu_addr; 3496 3497 gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), 3498 upper_32_bits(addr), seq, 0xffffffff, 4); 3499 } 3500 3501 static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3502 uint16_t pasid, uint32_t flush_type, 3503 bool all_hub, uint8_t dst_sel) 3504 { 3505 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3506 amdgpu_ring_write(ring, 3507 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 3508 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3509 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3510 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3511 } 3512 3513 static void gfx_v12_1_ring_emit_vm_flush(struct amdgpu_ring *ring, 3514 unsigned vmid, uint64_t pd_addr) 3515 { 3516 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3517 3518 /* compute doesn't have PFP */ 3519 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 3520 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3521 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3522 amdgpu_ring_write(ring, 0x0); 3523 } 3524 } 3525 3526 static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3527 u64 seq, unsigned int flags) 3528 { 3529 struct amdgpu_device *adev = ring->adev; 3530 3531 /* write fence seq to the "addr" */ 3532 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3533 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3534 amdgpu_ring_write(ring, lower_32_bits(addr)); 3535 amdgpu_ring_write(ring, upper_32_bits(addr)); 3536 amdgpu_ring_write(ring, lower_32_bits(seq)); 3537 3538 if (flags & AMDGPU_FENCE_FLAG_INT) { 3539 /* set register to trigger INT */ 3540 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3541 amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); 3542 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3543 amdgpu_ring_write(ring, 0); 3544 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3545 } 3546 } 3547 3548 static void gfx_v12_1_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3549 uint32_t reg_val_offs) 3550 { 3551 struct amdgpu_device *adev = ring->adev; 3552 3553 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3554 3555 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3556 amdgpu_ring_write(ring, 0 | /* src: register*/ 3557 (5 << 8) | /* dst: memory */ 3558 (1 << 20)); /* write confirm */ 3559 amdgpu_ring_write(ring, reg); 3560 amdgpu_ring_write(ring, 0); 3561 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3562 reg_val_offs * 4)); 3563 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3564 reg_val_offs * 4)); 3565 } 3566 3567 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, 3568 uint32_t reg, 3569 uint32_t val) 3570 { 3571 uint32_t cmd = 0; 3572 3573 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3574 3575 switch (ring->funcs->type) { 3576 case AMDGPU_RING_TYPE_KIQ: 3577 cmd = (1 << 16); /* no inc addr */ 3578 break; 3579 default: 3580 cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1); 3581 break; 3582 } 3583 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3584 amdgpu_ring_write(ring, cmd); 3585 amdgpu_ring_write(ring, reg); 3586 amdgpu_ring_write(ring, 0); 3587 amdgpu_ring_write(ring, val); 3588 } 3589 3590 static void gfx_v12_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3591 uint32_t val, uint32_t mask) 3592 { 3593 gfx_v12_1_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3594 } 3595 3596 static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3597 uint32_t reg0, uint32_t reg1, 3598 uint32_t ref, uint32_t mask) 3599 { 3600 gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, 3601 ref, mask, 0x20); 3602 } 3603 3604 static void gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3605 int me, int pipe, 3606 enum amdgpu_interrupt_state state, 3607 int xcc_id) 3608 { 3609 u32 mec_int_cntl, mec_int_cntl_reg; 3610 3611 /* 3612 * amdgpu controls only the first MEC. That's why this function only 3613 * handles the setting of interrupts for this specific MEC. All other 3614 * pipes' interrupts are set by amdkfd. 3615 */ 3616 3617 if (me == 1) { 3618 switch (pipe) { 3619 case 0: 3620 mec_int_cntl_reg = SOC15_REG_OFFSET( 3621 GC, GET_INST(GC, xcc_id), 3622 regCP_ME1_PIPE0_INT_CNTL); 3623 break; 3624 case 1: 3625 mec_int_cntl_reg = SOC15_REG_OFFSET( 3626 GC, GET_INST(GC, xcc_id), 3627 regCP_ME1_PIPE1_INT_CNTL); 3628 break; 3629 case 2: 3630 mec_int_cntl_reg = SOC15_REG_OFFSET( 3631 GC, GET_INST(GC, xcc_id), 3632 regCP_ME1_PIPE2_INT_CNTL); 3633 break; 3634 case 3: 3635 mec_int_cntl_reg = SOC15_REG_OFFSET( 3636 GC, GET_INST(GC, xcc_id), 3637 regCP_ME1_PIPE3_INT_CNTL); 3638 break; 3639 default: 3640 DRM_DEBUG("invalid pipe %d\n", pipe); 3641 return; 3642 } 3643 } else { 3644 DRM_DEBUG("invalid me %d\n", me); 3645 return; 3646 } 3647 3648 switch (state) { 3649 case AMDGPU_IRQ_STATE_DISABLE: 3650 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3651 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3652 TIME_STAMP_INT_ENABLE, 0); 3653 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3654 GENERIC0_INT_ENABLE, 0); 3655 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3656 break; 3657 case AMDGPU_IRQ_STATE_ENABLE: 3658 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3659 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3660 TIME_STAMP_INT_ENABLE, 1); 3661 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3662 GENERIC0_INT_ENABLE, 1); 3663 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3664 break; 3665 default: 3666 break; 3667 } 3668 } 3669 3670 static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, 3671 struct amdgpu_irq_src *src, 3672 unsigned type, 3673 enum amdgpu_interrupt_state state) 3674 { 3675 int i, num_xcc; 3676 3677 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3678 for (i = 0; i < num_xcc; i++) { 3679 switch (type) { 3680 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3681 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3682 adev, 1, 0, state, i); 3683 break; 3684 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3685 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3686 adev, 1, 1, state, i); 3687 break; 3688 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3689 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3690 adev, 1, 2, state, i); 3691 break; 3692 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3693 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3694 adev, 1, 3, state, i); 3695 break; 3696 default: 3697 break; 3698 } 3699 } 3700 3701 return 0; 3702 } 3703 3704 static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, 3705 struct amdgpu_irq_src *source, 3706 struct amdgpu_iv_entry *entry) 3707 { 3708 u32 doorbell_offset = entry->src_data[0]; 3709 u8 me_id, pipe_id, queue_id; 3710 struct amdgpu_ring *ring; 3711 int i, xcc_id; 3712 3713 DRM_DEBUG("IH: CP EOP\n"); 3714 3715 if (adev->enable_mes && doorbell_offset) { 3716 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 3717 } else { 3718 me_id = (entry->ring_id & 0x0c) >> 2; 3719 pipe_id = (entry->ring_id & 0x03) >> 0; 3720 queue_id = (entry->ring_id & 0x70) >> 4; 3721 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3722 3723 if (xcc_id == -EINVAL) 3724 return -EINVAL; 3725 3726 switch (me_id) { 3727 case 1: 3728 case 2: 3729 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3730 ring = &adev->gfx.compute_ring 3731 [i + 3732 xcc_id * adev->gfx.num_compute_rings]; 3733 /* Per-queue interrupt is supported for MEC starting from VI. 3734 * The interrupt can only be enabled/disabled per pipe instead 3735 * of per queue. 3736 */ 3737 if ((ring->me == me_id) && 3738 (ring->pipe == pipe_id) && 3739 (ring->queue == queue_id)) 3740 amdgpu_fence_process(ring); 3741 } 3742 break; 3743 default: 3744 dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); 3745 break; 3746 } 3747 } 3748 3749 return 0; 3750 } 3751 3752 static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, 3753 struct amdgpu_irq_src *source, 3754 unsigned type, 3755 enum amdgpu_interrupt_state state) 3756 { 3757 int i, num_xcc; 3758 3759 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3760 switch (state) { 3761 case AMDGPU_IRQ_STATE_DISABLE: 3762 case AMDGPU_IRQ_STATE_ENABLE: 3763 for (i = 0; i < num_xcc; i++) 3764 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3765 PRIV_REG_INT_ENABLE, 3766 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3767 break; 3768 default: 3769 break; 3770 } 3771 3772 return 0; 3773 } 3774 3775 static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, 3776 struct amdgpu_irq_src *source, 3777 unsigned type, 3778 enum amdgpu_interrupt_state state) 3779 { 3780 int i, num_xcc; 3781 3782 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3783 switch (state) { 3784 case AMDGPU_IRQ_STATE_DISABLE: 3785 case AMDGPU_IRQ_STATE_ENABLE: 3786 for (i = 0; i < num_xcc; i++) 3787 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3788 PRIV_INSTR_INT_ENABLE, 3789 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3790 break; 3791 default: 3792 break; 3793 } 3794 3795 return 0; 3796 } 3797 3798 static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 3799 struct amdgpu_iv_entry *entry) 3800 { 3801 u8 me_id, pipe_id, queue_id; 3802 struct amdgpu_ring *ring; 3803 int i, xcc_id; 3804 3805 me_id = (entry->ring_id & 0x0c) >> 2; 3806 pipe_id = (entry->ring_id & 0x03) >> 0; 3807 queue_id = (entry->ring_id & 0x70) >> 4; 3808 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3809 3810 if (xcc_id == -EINVAL) 3811 return; 3812 3813 if (!adev->gfx.disable_kq) { 3814 switch (me_id) { 3815 case 1: 3816 case 2: 3817 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3818 ring = &adev->gfx.compute_ring 3819 [i + 3820 xcc_id * adev->gfx.num_compute_rings]; 3821 if (ring->me == me_id && ring->pipe == pipe_id && 3822 ring->queue == queue_id) 3823 drm_sched_fault(&ring->sched); 3824 } 3825 break; 3826 default: 3827 dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); 3828 break; 3829 } 3830 } 3831 } 3832 3833 static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev, 3834 struct amdgpu_irq_src *source, 3835 struct amdgpu_iv_entry *entry) 3836 { 3837 DRM_ERROR("Illegal register access in command stream\n"); 3838 gfx_v12_1_handle_priv_fault(adev, entry); 3839 return 0; 3840 } 3841 3842 static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, 3843 struct amdgpu_irq_src *source, 3844 struct amdgpu_iv_entry *entry) 3845 { 3846 DRM_ERROR("Illegal instruction in command stream\n"); 3847 gfx_v12_1_handle_priv_fault(adev, entry); 3848 return 0; 3849 } 3850 3851 static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, 3852 struct amdgpu_irq_src *source, 3853 struct amdgpu_iv_entry *entry) 3854 { 3855 uint32_t rlc_fed_status = 0; 3856 uint32_t ras_blk = RAS_BLOCK_ID__GFX; 3857 struct ras_ih_info ih_info = {0}; 3858 int i, num_xcc; 3859 3860 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3861 for (i = 0; i < num_xcc; i++) 3862 rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, 3863 GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); 3864 3865 if (!rlc_fed_status) 3866 return 0; 3867 3868 if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || 3869 REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) 3870 ras_blk = RAS_BLOCK_ID__SDMA; 3871 3872 dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); 3873 3874 ih_info.block = ras_blk; 3875 ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 3876 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 3877 return 0; 3878 } 3879 3880 static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) 3881 { 3882 const unsigned int gcr_cntl = 3883 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | 3884 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | 3885 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | 3886 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | 3887 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | 3888 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); 3889 3890 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 3891 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 3892 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 3893 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3894 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3895 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3896 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3897 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3898 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 3899 } 3900 3901 static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { 3902 .name = "gfx_v12_1", 3903 .early_init = gfx_v12_1_early_init, 3904 .sw_init = gfx_v12_1_sw_init, 3905 .sw_fini = gfx_v12_1_sw_fini, 3906 .hw_init = gfx_v12_1_hw_init, 3907 .hw_fini = gfx_v12_1_hw_fini, 3908 .suspend = gfx_v12_1_suspend, 3909 .resume = gfx_v12_1_resume, 3910 .is_idle = gfx_v12_1_is_idle, 3911 .wait_for_idle = gfx_v12_1_wait_for_idle, 3912 .set_clockgating_state = gfx_v12_1_set_clockgating_state, 3913 .set_powergating_state = gfx_v12_1_set_powergating_state, 3914 .get_clockgating_state = gfx_v12_1_get_clockgating_state, 3915 }; 3916 3917 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { 3918 .type = AMDGPU_RING_TYPE_COMPUTE, 3919 .align_mask = 0xff, 3920 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3921 .support_64bit_ptrs = true, 3922 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 3923 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3924 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3925 .emit_frame_size = 3926 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3927 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3928 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3929 2 + /* gfx_v12_1_ring_emit_vm_flush */ 3930 8 + 8 + 8 + /* gfx_v12_1_ring_emit_fence x3 for user fence, vm fence */ 3931 8, /* gfx_v12_1_emit_mem_sync */ 3932 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 3933 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 3934 .emit_fence = gfx_v12_1_ring_emit_fence, 3935 .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, 3936 .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, 3937 .test_ring = gfx_v12_1_ring_test_ring, 3938 .test_ib = gfx_v12_1_ring_test_ib, 3939 .insert_nop = amdgpu_ring_insert_nop, 3940 .pad_ib = amdgpu_ring_generic_pad_ib, 3941 .emit_wreg = gfx_v12_1_ring_emit_wreg, 3942 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 3943 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 3944 .emit_mem_sync = gfx_v12_1_emit_mem_sync, 3945 }; 3946 3947 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_kiq = { 3948 .type = AMDGPU_RING_TYPE_KIQ, 3949 .align_mask = 0xff, 3950 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3951 .support_64bit_ptrs = true, 3952 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 3953 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3954 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3955 .emit_frame_size = 3956 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3957 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3958 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3959 2 + /* gfx_v12_1_ring_emit_vm_flush */ 3960 8 + 8 + 8, /* gfx_v12_1_ring_emit_fence_kiq x3 for user fence, vm fence */ 3961 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 3962 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 3963 .emit_fence = gfx_v12_1_ring_emit_fence_kiq, 3964 .test_ring = gfx_v12_1_ring_test_ring, 3965 .test_ib = gfx_v12_1_ring_test_ib, 3966 .insert_nop = amdgpu_ring_insert_nop, 3967 .pad_ib = amdgpu_ring_generic_pad_ib, 3968 .emit_rreg = gfx_v12_1_ring_emit_rreg, 3969 .emit_wreg = gfx_v12_1_ring_emit_wreg, 3970 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 3971 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 3972 }; 3973 3974 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev) 3975 { 3976 int i, j, num_xcc; 3977 3978 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3979 for (i = 0; i < num_xcc; i++) { 3980 adev->gfx.kiq[i].ring.funcs = &gfx_v12_1_ring_funcs_kiq; 3981 3982 for (j = 0; j < adev->gfx.num_compute_rings; j++) 3983 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs = 3984 &gfx_v12_1_ring_funcs_compute; 3985 } 3986 } 3987 3988 static const struct amdgpu_irq_src_funcs gfx_v12_1_eop_irq_funcs = { 3989 .set = gfx_v12_1_set_eop_interrupt_state, 3990 .process = gfx_v12_1_eop_irq, 3991 }; 3992 3993 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_reg_irq_funcs = { 3994 .set = gfx_v12_1_set_priv_reg_fault_state, 3995 .process = gfx_v12_1_priv_reg_irq, 3996 }; 3997 3998 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { 3999 .set = gfx_v12_1_set_priv_inst_fault_state, 4000 .process = gfx_v12_1_priv_inst_irq, 4001 }; 4002 4003 static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { 4004 .process = gfx_v12_1_rlc_poison_irq, 4005 }; 4006 4007 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) 4008 { 4009 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4010 adev->gfx.eop_irq.funcs = &gfx_v12_1_eop_irq_funcs; 4011 4012 adev->gfx.priv_reg_irq.num_types = 1; 4013 adev->gfx.priv_reg_irq.funcs = &gfx_v12_1_priv_reg_irq_funcs; 4014 4015 adev->gfx.priv_inst_irq.num_types = 1; 4016 adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; 4017 4018 adev->gfx.rlc_poison_irq.num_types = 1; 4019 adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; 4020 } 4021 4022 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) 4023 { 4024 if (adev->flags & AMD_IS_APU) 4025 adev->gfx.imu.mode = MISSION_MODE; 4026 else 4027 adev->gfx.imu.mode = DEBUG_MODE; 4028 if (!amdgpu_sriov_vf(adev)) 4029 adev->gfx.imu.funcs = &gfx_v12_1_imu_funcs; 4030 } 4031 4032 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev) 4033 { 4034 adev->gfx.rlc.funcs = &gfx_v12_1_rlc_funcs; 4035 } 4036 4037 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev) 4038 { 4039 /* set compute eng mqd */ 4040 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 4041 sizeof(struct v12_1_compute_mqd); 4042 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 4043 gfx_v12_1_compute_mqd_init; 4044 } 4045 4046 static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev, 4047 u32 bitmap, int xcc_id) 4048 { 4049 u32 data; 4050 4051 if (!bitmap) 4052 return; 4053 4054 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4055 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4056 4057 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4058 } 4059 4060 static u32 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev, 4061 int xcc_id) 4062 { 4063 u32 data, mask; 4064 4065 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4066 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4067 4068 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4069 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4070 4071 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4072 4073 return (~data) & mask; 4074 } 4075 4076 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 4077 struct amdgpu_cu_info *cu_info) 4078 { 4079 int i, j, k, counter, xcc_id, active_cu_number = 0; 4080 u32 mask, bitmap; 4081 unsigned int disable_masks[2 * 2]; 4082 4083 if (!adev || !cu_info) 4084 return -EINVAL; 4085 4086 if (adev->gfx.config.max_shader_engines > 2 || 4087 adev->gfx.config.max_sh_per_se > 2) { 4088 dev_err(adev->dev, 4089 "Max SE (%d) and Max SA per SE (%d) is greater than expected\n", 4090 adev->gfx.config.max_shader_engines, 4091 adev->gfx.config.max_sh_per_se); 4092 return -EINVAL; 4093 } 4094 4095 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4096 adev->gfx.config.max_shader_engines, 4097 adev->gfx.config.max_sh_per_se); 4098 4099 mutex_lock(&adev->grbm_idx_mutex); 4100 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4101 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4102 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4103 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4104 if (!((gfx_v12_1_get_sa_active_bitmap(adev, xcc_id) >> bitmap) & 1)) 4105 continue; 4106 mask = 1; 4107 counter = 0; 4108 gfx_v12_1_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4109 gfx_v12_1_set_user_cu_inactive_bitmap_per_sh( 4110 adev, 4111 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4112 xcc_id); 4113 bitmap = gfx_v12_1_get_cu_active_bitmap_per_sh(adev, xcc_id); 4114 4115 cu_info->bitmap[xcc_id][i][j] = bitmap; 4116 4117 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4118 if (bitmap & mask) 4119 counter++; 4120 4121 mask <<= 1; 4122 } 4123 active_cu_number += counter; 4124 } 4125 } 4126 gfx_v12_1_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 4127 } 4128 mutex_unlock(&adev->grbm_idx_mutex); 4129 4130 cu_info->number = active_cu_number; 4131 cu_info->simd_per_cu = NUM_SIMD_PER_CU_GFX12_1; 4132 cu_info->lds_size = 320; 4133 4134 return 0; 4135 } 4136 4137 const struct amdgpu_ip_block_version gfx_v12_1_ip_block = { 4138 .type = AMD_IP_BLOCK_TYPE_GFX, 4139 .major = 12, 4140 .minor = 1, 4141 .rev = 0, 4142 .funcs = &gfx_v12_1_ip_funcs, 4143 }; 4144 4145 static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) 4146 { 4147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4148 uint32_t tmp_mask; 4149 int i, r; 4150 4151 /* TODO : Initialize golden regs */ 4152 /* gfx_v12_1_init_golden_registers(adev); */ 4153 4154 tmp_mask = inst_mask; 4155 for_each_inst(i, tmp_mask) 4156 gfx_v12_1_xcc_constants_init(adev, i); 4157 4158 if (!amdgpu_sriov_vf(adev)) { 4159 tmp_mask = inst_mask; 4160 for_each_inst(i, tmp_mask) { 4161 r = gfx_v12_1_xcc_rlc_resume(adev, i); 4162 if (r) 4163 return r; 4164 } 4165 } 4166 4167 r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); 4168 4169 return r; 4170 } 4171 4172 static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) 4173 { 4174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4175 int i; 4176 4177 for_each_inst(i, inst_mask) 4178 gfx_v12_1_xcc_fini(adev, i); 4179 4180 return 0; 4181 } 4182 4183 struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs = { 4184 .suspend = &gfx_v12_1_xcp_suspend, 4185 .resume = &gfx_v12_1_xcp_resume 4186 }; 4187