1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_0.h" 47 #include "nbif_v6_3_1.h" 48 #include "mes_v12_0.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 65 66 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 97 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 101 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 102 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 104 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 105 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 109 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 120 121 /* cp header registers */ 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 126 /* SE status registers */ 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 128 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 130 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 131 }; 132 133 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 134 /* compute registers */ 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 174 }; 175 176 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 177 /* gfx queue registers */ 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 203 }; 204 205 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 206 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 209 }; 210 211 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 212 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 213 }; 214 215 #define DEFAULT_SH_MEM_CONFIG \ 216 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 217 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 218 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 219 220 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 221 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 222 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 223 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 224 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 225 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 226 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 227 struct amdgpu_cu_info *cu_info); 228 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 229 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 230 u32 sh_num, u32 instance, int xcc_id); 231 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 232 233 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 234 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 235 uint32_t val); 236 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 237 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 238 uint16_t pasid, uint32_t flush_type, 239 bool all_hub, uint8_t dst_sel); 240 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 241 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 242 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 243 bool enable); 244 245 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 246 uint64_t queue_mask) 247 { 248 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 249 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 250 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 251 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 252 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 253 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 254 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 255 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 256 amdgpu_ring_write(kiq_ring, 0); 257 } 258 259 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 260 struct amdgpu_ring *ring) 261 { 262 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 263 uint64_t wptr_addr = ring->wptr_gpu_addr; 264 uint32_t me = 0, eng_sel = 0; 265 266 switch (ring->funcs->type) { 267 case AMDGPU_RING_TYPE_COMPUTE: 268 me = 1; 269 eng_sel = 0; 270 break; 271 case AMDGPU_RING_TYPE_GFX: 272 me = 0; 273 eng_sel = 4; 274 break; 275 case AMDGPU_RING_TYPE_MES: 276 me = 2; 277 eng_sel = 5; 278 break; 279 default: 280 WARN_ON(1); 281 } 282 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 284 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 285 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 286 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 287 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 288 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 289 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 290 PACKET3_MAP_QUEUES_ME((me)) | 291 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 292 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 293 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 294 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 295 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 296 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 297 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 298 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 299 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 300 } 301 302 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 303 struct amdgpu_ring *ring, 304 enum amdgpu_unmap_queues_action action, 305 u64 gpu_addr, u64 seq) 306 { 307 struct amdgpu_device *adev = kiq_ring->adev; 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 311 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 312 return; 313 } 314 315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 316 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 317 PACKET3_UNMAP_QUEUES_ACTION(action) | 318 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 319 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 320 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 321 amdgpu_ring_write(kiq_ring, 322 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 323 324 if (action == PREEMPT_QUEUES_NO_UNMAP) { 325 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 326 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 327 amdgpu_ring_write(kiq_ring, seq); 328 } else { 329 amdgpu_ring_write(kiq_ring, 0); 330 amdgpu_ring_write(kiq_ring, 0); 331 amdgpu_ring_write(kiq_ring, 0); 332 } 333 } 334 335 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 336 struct amdgpu_ring *ring, 337 u64 addr, u64 seq) 338 { 339 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 340 341 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 342 amdgpu_ring_write(kiq_ring, 343 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 344 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 345 PACKET3_QUERY_STATUS_COMMAND(2)); 346 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 347 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 348 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 349 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 350 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 351 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 352 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 353 } 354 355 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 356 uint16_t pasid, 357 uint32_t flush_type, 358 bool all_hub) 359 { 360 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 361 } 362 363 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 364 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 365 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 366 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 367 .kiq_query_status = gfx_v12_0_kiq_query_status, 368 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 369 .set_resources_size = 8, 370 .map_queues_size = 7, 371 .unmap_queues_size = 6, 372 .query_status_size = 7, 373 .invalidate_tlbs_size = 2, 374 }; 375 376 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 377 { 378 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 379 } 380 381 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 382 int mem_space, int opt, uint32_t addr0, 383 uint32_t addr1, uint32_t ref, 384 uint32_t mask, uint32_t inv) 385 { 386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 387 amdgpu_ring_write(ring, 388 /* memory (1) or register (0) */ 389 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 390 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 391 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 392 WAIT_REG_MEM_ENGINE(eng_sel))); 393 394 if (mem_space) 395 BUG_ON(addr0 & 0x3); /* Dword align */ 396 amdgpu_ring_write(ring, addr0); 397 amdgpu_ring_write(ring, addr1); 398 amdgpu_ring_write(ring, ref); 399 amdgpu_ring_write(ring, mask); 400 amdgpu_ring_write(ring, inv); /* poll interval */ 401 } 402 403 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 407 uint32_t tmp = 0; 408 unsigned i; 409 int r; 410 411 WREG32(scratch, 0xCAFEDEAD); 412 r = amdgpu_ring_alloc(ring, 5); 413 if (r) { 414 dev_err(adev->dev, 415 "amdgpu: cp failed to lock ring %d (%d).\n", 416 ring->idx, r); 417 return r; 418 } 419 420 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 421 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 422 } else { 423 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 424 amdgpu_ring_write(ring, scratch - 425 PACKET3_SET_UCONFIG_REG_START); 426 amdgpu_ring_write(ring, 0xDEADBEEF); 427 } 428 amdgpu_ring_commit(ring); 429 430 for (i = 0; i < adev->usec_timeout; i++) { 431 tmp = RREG32(scratch); 432 if (tmp == 0xDEADBEEF) 433 break; 434 if (amdgpu_emu_mode == 1) 435 msleep(1); 436 else 437 udelay(1); 438 } 439 440 if (i >= adev->usec_timeout) 441 r = -ETIMEDOUT; 442 return r; 443 } 444 445 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 struct amdgpu_ib ib; 449 struct dma_fence *f = NULL; 450 unsigned index; 451 uint64_t gpu_addr; 452 volatile uint32_t *cpu_ptr; 453 long r; 454 455 /* MES KIQ fw hasn't indirect buffer support for now */ 456 if (adev->enable_mes_kiq && 457 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 458 return 0; 459 460 memset(&ib, 0, sizeof(ib)); 461 462 if (ring->is_mes_queue) { 463 uint32_t padding, offset; 464 465 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 466 padding = amdgpu_mes_ctx_get_offs(ring, 467 AMDGPU_MES_CTX_PADDING_OFFS); 468 469 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 470 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 471 472 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 473 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 474 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 475 } else { 476 r = amdgpu_device_wb_get(adev, &index); 477 if (r) 478 return r; 479 480 gpu_addr = adev->wb.gpu_addr + (index * 4); 481 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 482 cpu_ptr = &adev->wb.wb[index]; 483 484 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 485 if (r) { 486 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 487 goto err1; 488 } 489 } 490 491 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 493 ib.ptr[2] = lower_32_bits(gpu_addr); 494 ib.ptr[3] = upper_32_bits(gpu_addr); 495 ib.ptr[4] = 0xDEADBEEF; 496 ib.length_dw = 5; 497 498 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 499 if (r) 500 goto err2; 501 502 r = dma_fence_wait_timeout(f, false, timeout); 503 if (r == 0) { 504 r = -ETIMEDOUT; 505 goto err2; 506 } else if (r < 0) { 507 goto err2; 508 } 509 510 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 511 r = 0; 512 else 513 r = -EINVAL; 514 err2: 515 if (!ring->is_mes_queue) 516 amdgpu_ib_free(&ib, NULL); 517 dma_fence_put(f); 518 err1: 519 if (!ring->is_mes_queue) 520 amdgpu_device_wb_free(adev, index); 521 return r; 522 } 523 524 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 525 { 526 amdgpu_ucode_release(&adev->gfx.pfp_fw); 527 amdgpu_ucode_release(&adev->gfx.me_fw); 528 amdgpu_ucode_release(&adev->gfx.rlc_fw); 529 amdgpu_ucode_release(&adev->gfx.mec_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 535 { 536 const struct psp_firmware_header_v1_0 *toc_hdr; 537 int err = 0; 538 539 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 540 AMDGPU_UCODE_REQUIRED, 541 "amdgpu/%s_toc.bin", ucode_prefix); 542 if (err) 543 goto out; 544 545 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 546 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 547 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 548 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 549 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 550 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 551 return 0; 552 out: 553 amdgpu_ucode_release(&adev->psp.toc_fw); 554 return err; 555 } 556 557 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 558 { 559 char ucode_prefix[15]; 560 int err; 561 const struct rlc_firmware_header_v2_0 *rlc_hdr; 562 uint16_t version_major; 563 uint16_t version_minor; 564 565 DRM_DEBUG("\n"); 566 567 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 568 569 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_pfp.bin", ucode_prefix); 572 if (err) 573 goto out; 574 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 576 577 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 578 AMDGPU_UCODE_REQUIRED, 579 "amdgpu/%s_me.bin", ucode_prefix); 580 if (err) 581 goto out; 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 583 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 584 585 if (!amdgpu_sriov_vf(adev)) { 586 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 587 AMDGPU_UCODE_REQUIRED, 588 "amdgpu/%s_rlc.bin", ucode_prefix); 589 if (err) 590 goto out; 591 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 592 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 593 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 594 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 595 if (err) 596 goto out; 597 } 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_mec.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 607 608 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 609 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 610 611 /* only one MEC for gfx 12 */ 612 adev->gfx.mec2_fw = NULL; 613 614 if (adev->gfx.imu.funcs) { 615 if (adev->gfx.imu.funcs->init_microcode) { 616 err = adev->gfx.imu.funcs->init_microcode(adev); 617 if (err) 618 dev_err(adev->dev, "Failed to load imu firmware!\n"); 619 } 620 } 621 622 out: 623 if (err) { 624 amdgpu_ucode_release(&adev->gfx.pfp_fw); 625 amdgpu_ucode_release(&adev->gfx.me_fw); 626 amdgpu_ucode_release(&adev->gfx.rlc_fw); 627 amdgpu_ucode_release(&adev->gfx.mec_fw); 628 } 629 630 return err; 631 } 632 633 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 634 { 635 u32 count = 0; 636 const struct cs_section_def *sect = NULL; 637 const struct cs_extent_def *ext = NULL; 638 639 count += 1; 640 641 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 642 if (sect->id == SECT_CONTEXT) { 643 for (ext = sect->section; ext->extent != NULL; ++ext) 644 count += 2 + ext->reg_count; 645 } else 646 return 0; 647 } 648 649 return count; 650 } 651 652 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 653 volatile u32 *buffer) 654 { 655 u32 count = 0, clustercount = 0, i; 656 const struct cs_section_def *sect = NULL; 657 const struct cs_extent_def *ext = NULL; 658 659 if (adev->gfx.rlc.cs_data == NULL) 660 return; 661 if (buffer == NULL) 662 return; 663 664 count += 1; 665 666 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 667 if (sect->id == SECT_CONTEXT) { 668 for (ext = sect->section; ext->extent != NULL; ++ext) { 669 clustercount++; 670 buffer[count++] = ext->reg_count; 671 buffer[count++] = ext->reg_index; 672 673 for (i = 0; i < ext->reg_count; i++) 674 buffer[count++] = cpu_to_le32(ext->extent[i]); 675 } 676 } else 677 return; 678 } 679 680 buffer[0] = clustercount; 681 } 682 683 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 684 { 685 /* clear state block */ 686 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 687 &adev->gfx.rlc.clear_state_gpu_addr, 688 (void **)&adev->gfx.rlc.cs_ptr); 689 690 /* jump table block */ 691 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 692 &adev->gfx.rlc.cp_table_gpu_addr, 693 (void **)&adev->gfx.rlc.cp_table_ptr); 694 } 695 696 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 697 { 698 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 699 700 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 701 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 702 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 703 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 704 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 705 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 706 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 707 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 708 adev->gfx.rlc.rlcg_reg_access_supported = true; 709 } 710 711 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 712 { 713 const struct cs_section_def *cs_data; 714 int r; 715 716 adev->gfx.rlc.cs_data = gfx12_cs_data; 717 718 cs_data = adev->gfx.rlc.cs_data; 719 720 if (cs_data) { 721 /* init clear state block */ 722 r = amdgpu_gfx_rlc_init_csb(adev); 723 if (r) 724 return r; 725 } 726 727 /* init spm vmid with 0xf */ 728 if (adev->gfx.rlc.funcs->update_spm_vmid) 729 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 730 731 return 0; 732 } 733 734 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 735 { 736 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 737 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 738 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 739 } 740 741 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 742 { 743 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 744 745 amdgpu_gfx_graphics_queue_acquire(adev); 746 } 747 748 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 749 { 750 int r; 751 u32 *hpd; 752 size_t mec_hpd_size; 753 754 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 755 756 /* take ownership of the relevant compute queues */ 757 amdgpu_gfx_compute_queue_acquire(adev); 758 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 759 760 if (mec_hpd_size) { 761 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 762 AMDGPU_GEM_DOMAIN_GTT, 763 &adev->gfx.mec.hpd_eop_obj, 764 &adev->gfx.mec.hpd_eop_gpu_addr, 765 (void **)&hpd); 766 if (r) { 767 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 768 gfx_v12_0_mec_fini(adev); 769 return r; 770 } 771 772 memset(hpd, 0, mec_hpd_size); 773 774 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 775 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 776 } 777 778 return 0; 779 } 780 781 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 782 { 783 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 784 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 785 (address << SQ_IND_INDEX__INDEX__SHIFT)); 786 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 787 } 788 789 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 790 uint32_t thread, uint32_t regno, 791 uint32_t num, uint32_t *out) 792 { 793 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 794 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 795 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 796 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 797 (SQ_IND_INDEX__AUTO_INCR_MASK)); 798 while (num--) 799 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 800 } 801 802 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 803 uint32_t xcc_id, 804 uint32_t simd, uint32_t wave, 805 uint32_t *dst, int *no_fields) 806 { 807 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 808 * field when performing a select_se_sh so it should be 809 * zero here */ 810 WARN_ON(simd != 0); 811 812 /* type 4 wave data */ 813 dst[(*no_fields)++] = 4; 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 837 } 838 839 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 840 uint32_t xcc_id, uint32_t simd, 841 uint32_t wave, uint32_t start, 842 uint32_t size, uint32_t *dst) 843 { 844 WARN_ON(simd != 0); 845 846 wave_read_regs( 847 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 848 dst); 849 } 850 851 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 852 uint32_t xcc_id, uint32_t simd, 853 uint32_t wave, uint32_t thread, 854 uint32_t start, uint32_t size, 855 uint32_t *dst) 856 { 857 wave_read_regs( 858 adev, wave, thread, 859 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 860 } 861 862 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 863 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 864 { 865 soc24_grbm_select(adev, me, pipe, q, vm); 866 } 867 868 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 869 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 870 .select_se_sh = &gfx_v12_0_select_se_sh, 871 .read_wave_data = &gfx_v12_0_read_wave_data, 872 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 873 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 874 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 875 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 876 }; 877 878 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 879 { 880 881 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 882 case IP_VERSION(12, 0, 0): 883 case IP_VERSION(12, 0, 1): 884 adev->gfx.config.max_hw_contexts = 8; 885 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 886 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 887 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 888 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 889 break; 890 default: 891 BUG(); 892 break; 893 } 894 895 return 0; 896 } 897 898 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 899 int me, int pipe, int queue) 900 { 901 int r; 902 struct amdgpu_ring *ring; 903 unsigned int irq_type; 904 905 ring = &adev->gfx.gfx_ring[ring_id]; 906 907 ring->me = me; 908 ring->pipe = pipe; 909 ring->queue = queue; 910 911 ring->ring_obj = NULL; 912 ring->use_doorbell = true; 913 914 if (!ring_id) 915 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 916 else 917 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 918 ring->vm_hub = AMDGPU_GFXHUB(0); 919 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 920 921 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 922 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 923 AMDGPU_RING_PRIO_DEFAULT, NULL); 924 if (r) 925 return r; 926 return 0; 927 } 928 929 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 930 int mec, int pipe, int queue) 931 { 932 int r; 933 unsigned irq_type; 934 struct amdgpu_ring *ring; 935 unsigned int hw_prio; 936 937 ring = &adev->gfx.compute_ring[ring_id]; 938 939 /* mec0 is me1 */ 940 ring->me = mec + 1; 941 ring->pipe = pipe; 942 ring->queue = queue; 943 944 ring->ring_obj = NULL; 945 ring->use_doorbell = true; 946 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 947 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 948 + (ring_id * GFX12_MEC_HPD_SIZE); 949 ring->vm_hub = AMDGPU_GFXHUB(0); 950 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 951 952 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 953 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 954 + ring->pipe; 955 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 956 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 957 /* type-2 packets are deprecated on MEC, use type-3 instead */ 958 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 959 hw_prio, NULL); 960 if (r) 961 return r; 962 963 return 0; 964 } 965 966 static struct { 967 SOC24_FIRMWARE_ID id; 968 unsigned int offset; 969 unsigned int size; 970 unsigned int size_x16; 971 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 972 973 #define RLC_TOC_OFFSET_DWUNIT 8 974 #define RLC_SIZE_MULTIPLE 1024 975 #define RLC_TOC_UMF_SIZE_inM 23ULL 976 #define RLC_TOC_FORMAT_API 165ULL 977 978 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 979 { 980 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 981 982 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 983 rlc_autoload_info[ucode->id].id = ucode->id; 984 rlc_autoload_info[ucode->id].offset = 985 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 986 rlc_autoload_info[ucode->id].size = 987 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 988 ucode->size * 4; 989 ucode++; 990 } 991 } 992 993 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 994 { 995 uint32_t total_size = 0; 996 SOC24_FIRMWARE_ID id; 997 998 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 999 1000 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1001 total_size += rlc_autoload_info[id].size; 1002 1003 /* In case the offset in rlc toc ucode is aligned */ 1004 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1005 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1006 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1007 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1008 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1009 1010 return total_size; 1011 } 1012 1013 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1014 { 1015 int r; 1016 uint32_t total_size; 1017 1018 total_size = gfx_v12_0_calc_toc_total_size(adev); 1019 1020 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1021 AMDGPU_GEM_DOMAIN_VRAM, 1022 &adev->gfx.rlc.rlc_autoload_bo, 1023 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1024 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1025 1026 if (r) { 1027 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1028 return r; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1035 SOC24_FIRMWARE_ID id, 1036 const void *fw_data, 1037 uint32_t fw_size) 1038 { 1039 uint32_t toc_offset; 1040 uint32_t toc_fw_size; 1041 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1042 1043 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1044 return; 1045 1046 toc_offset = rlc_autoload_info[id].offset; 1047 toc_fw_size = rlc_autoload_info[id].size; 1048 1049 if (fw_size == 0) 1050 fw_size = toc_fw_size; 1051 1052 if (fw_size > toc_fw_size) 1053 fw_size = toc_fw_size; 1054 1055 memcpy(ptr + toc_offset, fw_data, fw_size); 1056 1057 if (fw_size < toc_fw_size) 1058 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1059 } 1060 1061 static void 1062 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1063 { 1064 void *data; 1065 uint32_t size; 1066 uint32_t *toc_ptr; 1067 1068 data = adev->psp.toc.start_addr; 1069 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1070 1071 toc_ptr = (uint32_t *)data + size / 4 - 2; 1072 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1073 1074 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1075 data, size); 1076 } 1077 1078 static void 1079 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1080 { 1081 const __le32 *fw_data; 1082 uint32_t fw_size; 1083 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1084 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1085 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1086 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1087 uint16_t version_major, version_minor; 1088 1089 /* pfp ucode */ 1090 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1091 adev->gfx.pfp_fw->data; 1092 /* instruction */ 1093 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1094 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1095 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1096 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1097 fw_data, fw_size); 1098 /* data */ 1099 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1100 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1101 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1102 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1103 fw_data, fw_size); 1104 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1105 fw_data, fw_size); 1106 /* me ucode */ 1107 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1108 adev->gfx.me_fw->data; 1109 /* instruction */ 1110 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1111 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1112 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1113 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1114 fw_data, fw_size); 1115 /* data */ 1116 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1117 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1118 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1119 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1120 fw_data, fw_size); 1121 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1122 fw_data, fw_size); 1123 /* mec ucode */ 1124 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1125 adev->gfx.mec_fw->data; 1126 /* instruction */ 1127 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1128 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1129 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1130 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1131 fw_data, fw_size); 1132 /* data */ 1133 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1134 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1135 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1136 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1137 fw_data, fw_size); 1138 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1139 fw_data, fw_size); 1140 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1141 fw_data, fw_size); 1142 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1143 fw_data, fw_size); 1144 1145 /* rlc ucode */ 1146 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1147 adev->gfx.rlc_fw->data; 1148 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1149 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1150 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1151 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1152 fw_data, fw_size); 1153 1154 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1155 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1156 if (version_major == 2) { 1157 if (version_minor >= 1) { 1158 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1159 1160 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1161 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1162 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1164 fw_data, fw_size); 1165 1166 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1167 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1168 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1170 fw_data, fw_size); 1171 } 1172 if (version_minor >= 2) { 1173 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1174 1175 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1176 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1177 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1179 fw_data, fw_size); 1180 1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1182 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1183 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1185 fw_data, fw_size); 1186 } 1187 } 1188 } 1189 1190 static void 1191 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1192 { 1193 const __le32 *fw_data; 1194 uint32_t fw_size; 1195 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1196 1197 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1198 adev->sdma.instance[0].fw->data; 1199 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1200 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1201 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1202 1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1204 fw_data, fw_size); 1205 } 1206 1207 static void 1208 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1209 { 1210 const __le32 *fw_data; 1211 unsigned fw_size; 1212 const struct mes_firmware_header_v1_0 *mes_hdr; 1213 int pipe, ucode_id, data_id; 1214 1215 for (pipe = 0; pipe < 2; pipe++) { 1216 if (pipe == 0) { 1217 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1218 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1219 } else { 1220 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1221 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1222 } 1223 1224 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1225 adev->mes.fw[pipe]->data; 1226 1227 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1228 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1229 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1230 1231 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1232 1233 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1234 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1235 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1236 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1238 } 1239 } 1240 1241 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1242 { 1243 uint32_t rlc_g_offset, rlc_g_size; 1244 uint64_t gpu_addr; 1245 uint32_t data; 1246 1247 /* RLC autoload sequence 2: copy ucode */ 1248 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1250 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1251 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1252 1253 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1254 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1255 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1256 1257 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1258 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1259 1260 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1261 1262 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1263 /* RLC autoload sequence 3: load IMU fw */ 1264 if (adev->gfx.imu.funcs->load_microcode) 1265 adev->gfx.imu.funcs->load_microcode(adev); 1266 /* RLC autoload sequence 4 init IMU fw */ 1267 if (adev->gfx.imu.funcs->setup_imu) 1268 adev->gfx.imu.funcs->setup_imu(adev); 1269 if (adev->gfx.imu.funcs->start_imu) 1270 adev->gfx.imu.funcs->start_imu(adev); 1271 1272 /* RLC autoload sequence 5 disable gpa mode */ 1273 gfx_v12_0_disable_gpa_mode(adev); 1274 } else { 1275 /* unhalt rlc to start autoload without imu */ 1276 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1277 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1278 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1279 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1280 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1287 { 1288 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1289 uint32_t *ptr; 1290 uint32_t inst; 1291 1292 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1293 if (!ptr) { 1294 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1295 adev->gfx.ip_dump_core = NULL; 1296 } else { 1297 adev->gfx.ip_dump_core = ptr; 1298 } 1299 1300 /* Allocate memory for compute queue registers for all the instances */ 1301 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1302 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1303 adev->gfx.mec.num_queue_per_pipe; 1304 1305 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1306 if (!ptr) { 1307 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1308 adev->gfx.ip_dump_compute_queues = NULL; 1309 } else { 1310 adev->gfx.ip_dump_compute_queues = ptr; 1311 } 1312 1313 /* Allocate memory for gfx queue registers for all the instances */ 1314 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1315 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1316 adev->gfx.me.num_queue_per_pipe; 1317 1318 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1319 if (!ptr) { 1320 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1321 adev->gfx.ip_dump_gfx_queues = NULL; 1322 } else { 1323 adev->gfx.ip_dump_gfx_queues = ptr; 1324 } 1325 } 1326 1327 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1328 { 1329 int i, j, k, r, ring_id = 0; 1330 unsigned num_compute_rings; 1331 int xcc_id = 0; 1332 struct amdgpu_device *adev = ip_block->adev; 1333 1334 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1335 case IP_VERSION(12, 0, 0): 1336 case IP_VERSION(12, 0, 1): 1337 adev->gfx.me.num_me = 1; 1338 adev->gfx.me.num_pipe_per_me = 1; 1339 adev->gfx.me.num_queue_per_pipe = 1; 1340 adev->gfx.mec.num_mec = 2; 1341 adev->gfx.mec.num_pipe_per_mec = 2; 1342 adev->gfx.mec.num_queue_per_pipe = 4; 1343 break; 1344 default: 1345 adev->gfx.me.num_me = 1; 1346 adev->gfx.me.num_pipe_per_me = 1; 1347 adev->gfx.me.num_queue_per_pipe = 1; 1348 adev->gfx.mec.num_mec = 1; 1349 adev->gfx.mec.num_pipe_per_mec = 4; 1350 adev->gfx.mec.num_queue_per_pipe = 8; 1351 break; 1352 } 1353 1354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1355 default: 1356 adev->gfx.enable_cleaner_shader = false; 1357 break; 1358 } 1359 1360 /* recalculate compute rings to use based on hardware configuration */ 1361 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe) / 2; 1363 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1364 num_compute_rings); 1365 1366 /* EOP Event */ 1367 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1368 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1369 &adev->gfx.eop_irq); 1370 if (r) 1371 return r; 1372 1373 /* Bad opcode Event */ 1374 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1375 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1376 &adev->gfx.bad_op_irq); 1377 if (r) 1378 return r; 1379 1380 /* Privileged reg */ 1381 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1382 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1383 &adev->gfx.priv_reg_irq); 1384 if (r) 1385 return r; 1386 1387 /* Privileged inst */ 1388 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1389 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1390 &adev->gfx.priv_inst_irq); 1391 if (r) 1392 return r; 1393 1394 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1395 1396 gfx_v12_0_me_init(adev); 1397 1398 r = gfx_v12_0_rlc_init(adev); 1399 if (r) { 1400 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1401 return r; 1402 } 1403 1404 r = gfx_v12_0_mec_init(adev); 1405 if (r) { 1406 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1407 return r; 1408 } 1409 1410 /* set up the gfx ring */ 1411 for (i = 0; i < adev->gfx.me.num_me; i++) { 1412 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1413 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1414 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1415 continue; 1416 1417 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1418 i, k, j); 1419 if (r) 1420 return r; 1421 ring_id++; 1422 } 1423 } 1424 } 1425 1426 ring_id = 0; 1427 /* set up the compute queues - allocate horizontally across pipes */ 1428 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1429 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1430 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1431 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1432 0, i, k, j)) 1433 continue; 1434 1435 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1436 i, k, j); 1437 if (r) 1438 return r; 1439 1440 ring_id++; 1441 } 1442 } 1443 } 1444 1445 adev->gfx.gfx_supported_reset = 1446 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1447 adev->gfx.compute_supported_reset = 1448 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1449 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1450 case IP_VERSION(12, 0, 0): 1451 case IP_VERSION(12, 0, 1): 1452 if ((adev->gfx.me_fw_version >= 2660) && 1453 (adev->gfx.mec_fw_version >= 2920)) { 1454 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1455 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1456 } 1457 } 1458 1459 if (!adev->enable_mes_kiq) { 1460 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1461 if (r) { 1462 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1463 return r; 1464 } 1465 1466 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1467 if (r) 1468 return r; 1469 } 1470 1471 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1472 if (r) 1473 return r; 1474 1475 /* allocate visible FB for rlc auto-loading fw */ 1476 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1477 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1478 if (r) 1479 return r; 1480 } 1481 1482 r = gfx_v12_0_gpu_early_init(adev); 1483 if (r) 1484 return r; 1485 1486 gfx_v12_0_alloc_ip_dump(adev); 1487 1488 r = amdgpu_gfx_sysfs_init(adev); 1489 if (r) 1490 return r; 1491 1492 return 0; 1493 } 1494 1495 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1496 { 1497 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1498 &adev->gfx.pfp.pfp_fw_gpu_addr, 1499 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1500 1501 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1502 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1503 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1504 } 1505 1506 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1507 { 1508 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1509 &adev->gfx.me.me_fw_gpu_addr, 1510 (void **)&adev->gfx.me.me_fw_ptr); 1511 1512 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1513 &adev->gfx.me.me_fw_data_gpu_addr, 1514 (void **)&adev->gfx.me.me_fw_data_ptr); 1515 } 1516 1517 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1518 { 1519 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1520 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1521 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1522 } 1523 1524 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1525 { 1526 int i; 1527 struct amdgpu_device *adev = ip_block->adev; 1528 1529 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1530 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1531 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1532 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1533 1534 amdgpu_gfx_mqd_sw_fini(adev, 0); 1535 1536 if (!adev->enable_mes_kiq) { 1537 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1538 amdgpu_gfx_kiq_fini(adev, 0); 1539 } 1540 1541 gfx_v12_0_pfp_fini(adev); 1542 gfx_v12_0_me_fini(adev); 1543 gfx_v12_0_rlc_fini(adev); 1544 gfx_v12_0_mec_fini(adev); 1545 1546 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1547 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1548 1549 gfx_v12_0_free_microcode(adev); 1550 1551 amdgpu_gfx_sysfs_fini(adev); 1552 1553 kfree(adev->gfx.ip_dump_core); 1554 kfree(adev->gfx.ip_dump_compute_queues); 1555 kfree(adev->gfx.ip_dump_gfx_queues); 1556 1557 return 0; 1558 } 1559 1560 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1561 u32 sh_num, u32 instance, int xcc_id) 1562 { 1563 u32 data; 1564 1565 if (instance == 0xffffffff) 1566 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1567 INSTANCE_BROADCAST_WRITES, 1); 1568 else 1569 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1570 instance); 1571 1572 if (se_num == 0xffffffff) 1573 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1574 1); 1575 else 1576 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1577 1578 if (sh_num == 0xffffffff) 1579 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1580 1); 1581 else 1582 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1583 1584 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1585 } 1586 1587 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1588 { 1589 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1590 1591 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1592 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1593 GRBM_CC_GC_SA_UNIT_DISABLE, 1594 SA_DISABLE); 1595 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1596 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1597 GRBM_GC_USER_SA_UNIT_DISABLE, 1598 SA_DISABLE); 1599 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1600 adev->gfx.config.max_shader_engines); 1601 1602 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1603 } 1604 1605 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1606 { 1607 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1608 u32 rb_mask; 1609 1610 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1611 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1612 CC_RB_BACKEND_DISABLE, 1613 BACKEND_DISABLE); 1614 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1615 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1616 GC_USER_RB_BACKEND_DISABLE, 1617 BACKEND_DISABLE); 1618 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1619 adev->gfx.config.max_shader_engines); 1620 1621 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1622 } 1623 1624 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1625 { 1626 u32 rb_bitmap_per_sa; 1627 u32 rb_bitmap_width_per_sa; 1628 u32 max_sa; 1629 u32 active_sa_bitmap; 1630 u32 global_active_rb_bitmap; 1631 u32 active_rb_bitmap = 0; 1632 u32 i; 1633 1634 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1635 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1636 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1637 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1638 1639 /* generate active rb bitmap according to active sa bitmap */ 1640 max_sa = adev->gfx.config.max_shader_engines * 1641 adev->gfx.config.max_sh_per_se; 1642 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1643 adev->gfx.config.max_sh_per_se; 1644 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1645 1646 for (i = 0; i < max_sa; i++) { 1647 if (active_sa_bitmap & (1 << i)) 1648 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1649 } 1650 1651 active_rb_bitmap &= global_active_rb_bitmap; 1652 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1653 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1654 } 1655 1656 #define LDS_APP_BASE 0x1 1657 #define SCRATCH_APP_BASE 0x2 1658 1659 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1660 { 1661 int i; 1662 uint32_t sh_mem_bases; 1663 uint32_t data; 1664 1665 /* 1666 * Configure apertures: 1667 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1668 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1669 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1670 */ 1671 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1672 SCRATCH_APP_BASE; 1673 1674 mutex_lock(&adev->srbm_mutex); 1675 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1676 soc24_grbm_select(adev, 0, 0, 0, i); 1677 /* CP and shaders */ 1678 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1679 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1680 1681 /* Enable trap for each kfd vmid. */ 1682 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1683 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1684 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1685 } 1686 soc24_grbm_select(adev, 0, 0, 0, 0); 1687 mutex_unlock(&adev->srbm_mutex); 1688 } 1689 1690 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1691 { 1692 /* TODO: harvest feature to be added later. */ 1693 } 1694 1695 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1696 { 1697 } 1698 1699 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1700 { 1701 u32 tmp; 1702 int i; 1703 1704 if (!amdgpu_sriov_vf(adev)) 1705 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1706 1707 gfx_v12_0_setup_rb(adev); 1708 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1709 gfx_v12_0_get_tcc_info(adev); 1710 adev->gfx.config.pa_sc_tile_steering_override = 0; 1711 1712 /* XXX SH_MEM regs */ 1713 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1714 mutex_lock(&adev->srbm_mutex); 1715 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1716 soc24_grbm_select(adev, 0, 0, 0, i); 1717 /* CP and shaders */ 1718 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1719 if (i != 0) { 1720 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1721 (adev->gmc.private_aperture_start >> 48)); 1722 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1723 (adev->gmc.shared_aperture_start >> 48)); 1724 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1725 } 1726 } 1727 soc24_grbm_select(adev, 0, 0, 0, 0); 1728 1729 mutex_unlock(&adev->srbm_mutex); 1730 1731 gfx_v12_0_init_compute_vmid(adev); 1732 } 1733 1734 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1735 int me, int pipe) 1736 { 1737 if (me != 0) 1738 return 0; 1739 1740 switch (pipe) { 1741 case 0: 1742 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1743 default: 1744 return 0; 1745 } 1746 } 1747 1748 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1749 int me, int pipe) 1750 { 1751 /* 1752 * amdgpu controls only the first MEC. That's why this function only 1753 * handles the setting of interrupts for this specific MEC. All other 1754 * pipes' interrupts are set by amdkfd. 1755 */ 1756 if (me != 1) 1757 return 0; 1758 1759 switch (pipe) { 1760 case 0: 1761 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1762 case 1: 1763 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1764 default: 1765 return 0; 1766 } 1767 } 1768 1769 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1770 bool enable) 1771 { 1772 u32 tmp, cp_int_cntl_reg; 1773 int i, j; 1774 1775 if (amdgpu_sriov_vf(adev)) 1776 return; 1777 1778 for (i = 0; i < adev->gfx.me.num_me; i++) { 1779 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1780 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1781 1782 if (cp_int_cntl_reg) { 1783 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1784 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1785 enable ? 1 : 0); 1786 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1787 enable ? 1 : 0); 1788 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1789 enable ? 1 : 0); 1790 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1791 enable ? 1 : 0); 1792 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1793 } 1794 } 1795 } 1796 } 1797 1798 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1799 { 1800 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1801 1802 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1803 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1804 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1805 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1806 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1807 1808 return 0; 1809 } 1810 1811 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1812 { 1813 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1814 1815 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1816 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1817 } 1818 1819 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1820 { 1821 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1822 udelay(50); 1823 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1824 udelay(50); 1825 } 1826 1827 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1828 bool enable) 1829 { 1830 uint32_t rlc_pg_cntl; 1831 1832 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1833 1834 if (!enable) { 1835 /* RLC_PG_CNTL[23] = 0 (default) 1836 * RLC will wait for handshake acks with SMU 1837 * GFXOFF will be enabled 1838 * RLC_PG_CNTL[23] = 1 1839 * RLC will not issue any message to SMU 1840 * hence no handshake between SMU & RLC 1841 * GFXOFF will be disabled 1842 */ 1843 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1844 } else 1845 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1846 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1847 } 1848 1849 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1850 { 1851 /* TODO: enable rlc & smu handshake until smu 1852 * and gfxoff feature works as expected */ 1853 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1854 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1855 1856 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1857 udelay(50); 1858 } 1859 1860 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1861 { 1862 uint32_t tmp; 1863 1864 /* enable Save Restore Machine */ 1865 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1866 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1867 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1868 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1869 } 1870 1871 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1872 { 1873 const struct rlc_firmware_header_v2_0 *hdr; 1874 const __le32 *fw_data; 1875 unsigned i, fw_size; 1876 1877 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1878 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1879 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1880 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1881 1882 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1883 RLCG_UCODE_LOADING_START_ADDRESS); 1884 1885 for (i = 0; i < fw_size; i++) 1886 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1887 le32_to_cpup(fw_data++)); 1888 1889 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1890 } 1891 1892 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1893 { 1894 const struct rlc_firmware_header_v2_2 *hdr; 1895 const __le32 *fw_data; 1896 unsigned i, fw_size; 1897 u32 tmp; 1898 1899 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1900 1901 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1902 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1903 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1904 1905 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1906 1907 for (i = 0; i < fw_size; i++) { 1908 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1909 msleep(1); 1910 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1911 le32_to_cpup(fw_data++)); 1912 } 1913 1914 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1915 1916 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1917 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1918 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1919 1920 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1921 for (i = 0; i < fw_size; i++) { 1922 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1923 msleep(1); 1924 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1925 le32_to_cpup(fw_data++)); 1926 } 1927 1928 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1929 1930 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1931 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1932 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1933 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1934 } 1935 1936 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1937 { 1938 const struct rlc_firmware_header_v2_0 *hdr; 1939 uint16_t version_major; 1940 uint16_t version_minor; 1941 1942 if (!adev->gfx.rlc_fw) 1943 return -EINVAL; 1944 1945 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1946 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1947 1948 version_major = le16_to_cpu(hdr->header.header_version_major); 1949 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1950 1951 if (version_major == 2) { 1952 gfx_v12_0_load_rlcg_microcode(adev); 1953 if (amdgpu_dpm == 1) { 1954 if (version_minor >= 2) 1955 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1956 } 1957 1958 return 0; 1959 } 1960 1961 return -EINVAL; 1962 } 1963 1964 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1965 { 1966 int r; 1967 1968 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1969 gfx_v12_0_init_csb(adev); 1970 1971 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1972 gfx_v12_0_rlc_enable_srm(adev); 1973 } else { 1974 if (amdgpu_sriov_vf(adev)) { 1975 gfx_v12_0_init_csb(adev); 1976 return 0; 1977 } 1978 1979 adev->gfx.rlc.funcs->stop(adev); 1980 1981 /* disable CG */ 1982 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1983 1984 /* disable PG */ 1985 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1986 1987 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1988 /* legacy rlc firmware loading */ 1989 r = gfx_v12_0_rlc_load_microcode(adev); 1990 if (r) 1991 return r; 1992 } 1993 1994 gfx_v12_0_init_csb(adev); 1995 1996 adev->gfx.rlc.funcs->start(adev); 1997 } 1998 1999 return 0; 2000 } 2001 2002 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2003 { 2004 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2005 const struct gfx_firmware_header_v2_0 *me_hdr; 2006 const struct gfx_firmware_header_v2_0 *mec_hdr; 2007 uint32_t pipe_id, tmp; 2008 2009 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2010 adev->gfx.mec_fw->data; 2011 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2012 adev->gfx.me_fw->data; 2013 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2014 adev->gfx.pfp_fw->data; 2015 2016 /* config pfp program start addr */ 2017 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2018 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2019 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2020 (pfp_hdr->ucode_start_addr_hi << 30) | 2021 (pfp_hdr->ucode_start_addr_lo >> 2)); 2022 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2023 pfp_hdr->ucode_start_addr_hi >> 2); 2024 } 2025 soc24_grbm_select(adev, 0, 0, 0, 0); 2026 2027 /* reset pfp pipe */ 2028 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2029 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2030 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2031 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2032 2033 /* clear pfp pipe reset */ 2034 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2035 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2036 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2037 2038 /* config me program start addr */ 2039 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2040 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2041 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2042 (me_hdr->ucode_start_addr_hi << 30) | 2043 (me_hdr->ucode_start_addr_lo >> 2)); 2044 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2045 me_hdr->ucode_start_addr_hi>>2); 2046 } 2047 soc24_grbm_select(adev, 0, 0, 0, 0); 2048 2049 /* reset me pipe */ 2050 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2051 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2052 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2053 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2054 2055 /* clear me pipe reset */ 2056 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2057 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2058 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2059 2060 /* config mec program start addr */ 2061 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2062 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2063 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2064 mec_hdr->ucode_start_addr_lo >> 2 | 2065 mec_hdr->ucode_start_addr_hi << 30); 2066 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2067 mec_hdr->ucode_start_addr_hi >> 2); 2068 } 2069 soc24_grbm_select(adev, 0, 0, 0, 0); 2070 2071 /* reset mec pipe */ 2072 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2073 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2074 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2075 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2076 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2077 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2078 2079 /* clear mec pipe reset */ 2080 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2081 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2082 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2083 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2084 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2085 } 2086 2087 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2088 { 2089 const struct gfx_firmware_header_v2_0 *cp_hdr; 2090 unsigned pipe_id, tmp; 2091 2092 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2093 adev->gfx.pfp_fw->data; 2094 mutex_lock(&adev->srbm_mutex); 2095 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2096 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2097 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2098 (cp_hdr->ucode_start_addr_hi << 30) | 2099 (cp_hdr->ucode_start_addr_lo >> 2)); 2100 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2101 cp_hdr->ucode_start_addr_hi>>2); 2102 2103 /* 2104 * Program CP_ME_CNTL to reset given PIPE to take 2105 * effect of CP_PFP_PRGRM_CNTR_START. 2106 */ 2107 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2108 if (pipe_id == 0) 2109 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2110 PFP_PIPE0_RESET, 1); 2111 else 2112 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2113 PFP_PIPE1_RESET, 1); 2114 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2115 2116 /* Clear pfp pipe0 reset bit. */ 2117 if (pipe_id == 0) 2118 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2119 PFP_PIPE0_RESET, 0); 2120 else 2121 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2122 PFP_PIPE1_RESET, 0); 2123 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2124 } 2125 soc24_grbm_select(adev, 0, 0, 0, 0); 2126 mutex_unlock(&adev->srbm_mutex); 2127 } 2128 2129 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2130 { 2131 const struct gfx_firmware_header_v2_0 *cp_hdr; 2132 unsigned pipe_id, tmp; 2133 2134 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2135 adev->gfx.me_fw->data; 2136 mutex_lock(&adev->srbm_mutex); 2137 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2138 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2139 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2140 (cp_hdr->ucode_start_addr_hi << 30) | 2141 (cp_hdr->ucode_start_addr_lo >> 2) ); 2142 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2143 cp_hdr->ucode_start_addr_hi>>2); 2144 2145 /* 2146 * Program CP_ME_CNTL to reset given PIPE to take 2147 * effect of CP_ME_PRGRM_CNTR_START. 2148 */ 2149 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2150 if (pipe_id == 0) 2151 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2152 ME_PIPE0_RESET, 1); 2153 else 2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2155 ME_PIPE1_RESET, 1); 2156 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2157 2158 /* Clear pfp pipe0 reset bit. */ 2159 if (pipe_id == 0) 2160 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2161 ME_PIPE0_RESET, 0); 2162 else 2163 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2164 ME_PIPE1_RESET, 0); 2165 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2166 } 2167 soc24_grbm_select(adev, 0, 0, 0, 0); 2168 mutex_unlock(&adev->srbm_mutex); 2169 } 2170 2171 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2172 { 2173 const struct gfx_firmware_header_v2_0 *cp_hdr; 2174 unsigned pipe_id; 2175 2176 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2177 adev->gfx.mec_fw->data; 2178 mutex_lock(&adev->srbm_mutex); 2179 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2180 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2181 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2182 cp_hdr->ucode_start_addr_lo >> 2 | 2183 cp_hdr->ucode_start_addr_hi << 30); 2184 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2185 cp_hdr->ucode_start_addr_hi >> 2); 2186 } 2187 soc24_grbm_select(adev, 0, 0, 0, 0); 2188 mutex_unlock(&adev->srbm_mutex); 2189 } 2190 2191 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2192 { 2193 uint32_t cp_status; 2194 uint32_t bootload_status; 2195 int i; 2196 2197 for (i = 0; i < adev->usec_timeout; i++) { 2198 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2199 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2200 2201 if ((cp_status == 0) && 2202 (REG_GET_FIELD(bootload_status, 2203 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2204 break; 2205 } 2206 udelay(1); 2207 if (amdgpu_emu_mode) 2208 msleep(10); 2209 } 2210 2211 if (i >= adev->usec_timeout) { 2212 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2213 return -ETIMEDOUT; 2214 } 2215 2216 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2217 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2218 gfx_v12_0_set_me_ucode_start_addr(adev); 2219 gfx_v12_0_set_mec_ucode_start_addr(adev); 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2226 { 2227 int i; 2228 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2229 2230 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2231 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2232 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2233 2234 for (i = 0; i < adev->usec_timeout; i++) { 2235 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2236 break; 2237 udelay(1); 2238 } 2239 2240 if (i >= adev->usec_timeout) 2241 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2242 2243 return 0; 2244 } 2245 2246 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2247 { 2248 int r; 2249 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2250 const __le32 *fw_ucode, *fw_data; 2251 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2252 uint32_t tmp; 2253 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2254 2255 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2256 adev->gfx.pfp_fw->data; 2257 2258 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2259 2260 /* instruction */ 2261 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2262 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2263 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2264 /* data */ 2265 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2266 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2267 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2268 2269 /* 64kb align */ 2270 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2271 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2272 &adev->gfx.pfp.pfp_fw_obj, 2273 &adev->gfx.pfp.pfp_fw_gpu_addr, 2274 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2275 if (r) { 2276 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2277 gfx_v12_0_pfp_fini(adev); 2278 return r; 2279 } 2280 2281 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2282 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2283 &adev->gfx.pfp.pfp_fw_data_obj, 2284 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2285 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2286 if (r) { 2287 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2288 gfx_v12_0_pfp_fini(adev); 2289 return r; 2290 } 2291 2292 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2293 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2294 2295 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2296 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2297 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2298 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2299 2300 if (amdgpu_emu_mode == 1) 2301 adev->hdp.funcs->flush_hdp(adev, NULL); 2302 2303 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2304 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2305 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2306 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2307 2308 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2309 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2310 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2311 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2312 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2313 2314 /* 2315 * Programming any of the CP_PFP_IC_BASE registers 2316 * forces invalidation of the ME L1 I$. Wait for the 2317 * invalidation complete 2318 */ 2319 for (i = 0; i < usec_timeout; i++) { 2320 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2321 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2322 INVALIDATE_CACHE_COMPLETE)) 2323 break; 2324 udelay(1); 2325 } 2326 2327 if (i >= usec_timeout) { 2328 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2329 return -EINVAL; 2330 } 2331 2332 /* Prime the L1 instruction caches */ 2333 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2334 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2335 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2336 /* Waiting for cache primed*/ 2337 for (i = 0; i < usec_timeout; i++) { 2338 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2339 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2340 ICACHE_PRIMED)) 2341 break; 2342 udelay(1); 2343 } 2344 2345 if (i >= usec_timeout) { 2346 dev_err(adev->dev, "failed to prime instruction cache\n"); 2347 return -EINVAL; 2348 } 2349 2350 mutex_lock(&adev->srbm_mutex); 2351 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2352 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2353 2354 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2355 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2356 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2357 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2358 } 2359 soc24_grbm_select(adev, 0, 0, 0, 0); 2360 mutex_unlock(&adev->srbm_mutex); 2361 2362 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2363 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2364 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2365 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2366 2367 /* Invalidate the data caches */ 2368 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2369 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2370 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2371 2372 for (i = 0; i < usec_timeout; i++) { 2373 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2374 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2375 INVALIDATE_DCACHE_COMPLETE)) 2376 break; 2377 udelay(1); 2378 } 2379 2380 if (i >= usec_timeout) { 2381 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2382 return -EINVAL; 2383 } 2384 2385 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2386 2387 return 0; 2388 } 2389 2390 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2391 { 2392 int r; 2393 const struct gfx_firmware_header_v2_0 *me_hdr; 2394 const __le32 *fw_ucode, *fw_data; 2395 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2396 uint32_t tmp; 2397 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2398 2399 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2400 adev->gfx.me_fw->data; 2401 2402 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2403 2404 /* instruction */ 2405 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2406 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2407 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2408 /* data */ 2409 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2410 le32_to_cpu(me_hdr->data_offset_bytes)); 2411 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2412 2413 /* 64kb align*/ 2414 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2415 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2416 &adev->gfx.me.me_fw_obj, 2417 &adev->gfx.me.me_fw_gpu_addr, 2418 (void **)&adev->gfx.me.me_fw_ptr); 2419 if (r) { 2420 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2421 gfx_v12_0_me_fini(adev); 2422 return r; 2423 } 2424 2425 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2426 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2427 &adev->gfx.me.me_fw_data_obj, 2428 &adev->gfx.me.me_fw_data_gpu_addr, 2429 (void **)&adev->gfx.me.me_fw_data_ptr); 2430 if (r) { 2431 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2432 gfx_v12_0_pfp_fini(adev); 2433 return r; 2434 } 2435 2436 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2437 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2438 2439 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2440 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2441 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2442 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2443 2444 if (amdgpu_emu_mode == 1) 2445 adev->hdp.funcs->flush_hdp(adev, NULL); 2446 2447 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2448 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2449 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2450 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2451 2452 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2453 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2454 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2455 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2456 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2457 2458 /* 2459 * Programming any of the CP_ME_IC_BASE registers 2460 * forces invalidation of the ME L1 I$. Wait for the 2461 * invalidation complete 2462 */ 2463 for (i = 0; i < usec_timeout; i++) { 2464 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2465 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2466 INVALIDATE_CACHE_COMPLETE)) 2467 break; 2468 udelay(1); 2469 } 2470 2471 if (i >= usec_timeout) { 2472 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2473 return -EINVAL; 2474 } 2475 2476 /* Prime the instruction caches */ 2477 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2478 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2479 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2480 2481 /* Waiting for instruction cache primed*/ 2482 for (i = 0; i < usec_timeout; i++) { 2483 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2484 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2485 ICACHE_PRIMED)) 2486 break; 2487 udelay(1); 2488 } 2489 2490 if (i >= usec_timeout) { 2491 dev_err(adev->dev, "failed to prime instruction cache\n"); 2492 return -EINVAL; 2493 } 2494 2495 mutex_lock(&adev->srbm_mutex); 2496 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2497 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2498 2499 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2500 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2501 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2502 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2503 } 2504 soc24_grbm_select(adev, 0, 0, 0, 0); 2505 mutex_unlock(&adev->srbm_mutex); 2506 2507 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2508 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2509 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2510 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2511 2512 /* Invalidate the data caches */ 2513 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2514 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2515 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2516 2517 for (i = 0; i < usec_timeout; i++) { 2518 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2519 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2520 INVALIDATE_DCACHE_COMPLETE)) 2521 break; 2522 udelay(1); 2523 } 2524 2525 if (i >= usec_timeout) { 2526 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2527 return -EINVAL; 2528 } 2529 2530 gfx_v12_0_set_me_ucode_start_addr(adev); 2531 2532 return 0; 2533 } 2534 2535 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2536 { 2537 int r; 2538 2539 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2540 return -EINVAL; 2541 2542 gfx_v12_0_cp_gfx_enable(adev, false); 2543 2544 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2545 if (r) { 2546 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2547 return r; 2548 } 2549 2550 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2551 if (r) { 2552 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2553 return r; 2554 } 2555 2556 return 0; 2557 } 2558 2559 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2560 { 2561 /* init the CP */ 2562 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2563 adev->gfx.config.max_hw_contexts - 1); 2564 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2565 2566 if (!amdgpu_async_gfx_ring) 2567 gfx_v12_0_cp_gfx_enable(adev, true); 2568 2569 return 0; 2570 } 2571 2572 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2573 CP_PIPE_ID pipe) 2574 { 2575 u32 tmp; 2576 2577 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2578 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2579 2580 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2581 } 2582 2583 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2584 struct amdgpu_ring *ring) 2585 { 2586 u32 tmp; 2587 2588 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2589 if (ring->use_doorbell) { 2590 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2591 DOORBELL_OFFSET, ring->doorbell_index); 2592 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2593 DOORBELL_EN, 1); 2594 } else { 2595 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2596 DOORBELL_EN, 0); 2597 } 2598 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2599 2600 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2601 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2602 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2603 2604 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2605 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2606 } 2607 2608 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2609 { 2610 struct amdgpu_ring *ring; 2611 u32 tmp; 2612 u32 rb_bufsz; 2613 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2614 u32 i; 2615 2616 /* Set the write pointer delay */ 2617 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2618 2619 /* set the RB to use vmid 0 */ 2620 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2621 2622 /* Init gfx ring 0 for pipe 0 */ 2623 mutex_lock(&adev->srbm_mutex); 2624 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2625 2626 /* Set ring buffer size */ 2627 ring = &adev->gfx.gfx_ring[0]; 2628 rb_bufsz = order_base_2(ring->ring_size / 8); 2629 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2630 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2631 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2632 2633 /* Initialize the ring buffer's write pointers */ 2634 ring->wptr = 0; 2635 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2636 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2637 2638 /* set the wb address whether it's enabled or not */ 2639 rptr_addr = ring->rptr_gpu_addr; 2640 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2641 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2642 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2643 2644 wptr_gpu_addr = ring->wptr_gpu_addr; 2645 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2646 lower_32_bits(wptr_gpu_addr)); 2647 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2648 upper_32_bits(wptr_gpu_addr)); 2649 2650 mdelay(1); 2651 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2652 2653 rb_addr = ring->gpu_addr >> 8; 2654 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2655 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2656 2657 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2658 2659 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2660 mutex_unlock(&adev->srbm_mutex); 2661 2662 /* Switch to pipe 0 */ 2663 mutex_lock(&adev->srbm_mutex); 2664 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2665 mutex_unlock(&adev->srbm_mutex); 2666 2667 /* start the ring */ 2668 gfx_v12_0_cp_gfx_start(adev); 2669 2670 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2671 ring = &adev->gfx.gfx_ring[i]; 2672 ring->sched.ready = true; 2673 } 2674 2675 return 0; 2676 } 2677 2678 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2679 { 2680 u32 data; 2681 2682 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2683 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2684 enable ? 0 : 1); 2685 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2686 enable ? 0 : 1); 2687 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2688 enable ? 0 : 1); 2689 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2690 enable ? 0 : 1); 2691 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2692 enable ? 0 : 1); 2693 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2694 enable ? 1 : 0); 2695 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2696 enable ? 1 : 0); 2697 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2698 enable ? 1 : 0); 2699 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2700 enable ? 1 : 0); 2701 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2702 enable ? 0 : 1); 2703 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2704 2705 adev->gfx.kiq[0].ring.sched.ready = enable; 2706 2707 udelay(50); 2708 } 2709 2710 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2711 { 2712 const struct gfx_firmware_header_v2_0 *mec_hdr; 2713 const __le32 *fw_ucode, *fw_data; 2714 u32 tmp, fw_ucode_size, fw_data_size; 2715 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2716 u32 *fw_ucode_ptr, *fw_data_ptr; 2717 int r; 2718 2719 if (!adev->gfx.mec_fw) 2720 return -EINVAL; 2721 2722 gfx_v12_0_cp_compute_enable(adev, false); 2723 2724 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2725 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2726 2727 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2728 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2729 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2730 2731 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2732 le32_to_cpu(mec_hdr->data_offset_bytes)); 2733 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2734 2735 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2736 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2737 &adev->gfx.mec.mec_fw_obj, 2738 &adev->gfx.mec.mec_fw_gpu_addr, 2739 (void **)&fw_ucode_ptr); 2740 if (r) { 2741 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2742 gfx_v12_0_mec_fini(adev); 2743 return r; 2744 } 2745 2746 r = amdgpu_bo_create_reserved(adev, 2747 ALIGN(fw_data_size, 64 * 1024) * 2748 adev->gfx.mec.num_pipe_per_mec, 2749 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2750 &adev->gfx.mec.mec_fw_data_obj, 2751 &adev->gfx.mec.mec_fw_data_gpu_addr, 2752 (void **)&fw_data_ptr); 2753 if (r) { 2754 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2755 gfx_v12_0_mec_fini(adev); 2756 return r; 2757 } 2758 2759 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2760 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2761 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2762 } 2763 2764 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2765 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2766 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2767 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2768 2769 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2770 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2771 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2772 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2773 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2774 2775 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2776 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2777 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2778 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2779 2780 mutex_lock(&adev->srbm_mutex); 2781 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2782 soc24_grbm_select(adev, 1, i, 0, 0); 2783 2784 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2785 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2786 i * ALIGN(fw_data_size, 64 * 1024))); 2787 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2788 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2789 i * ALIGN(fw_data_size, 64 * 1024))); 2790 2791 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2792 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2793 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2794 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2795 } 2796 mutex_unlock(&adev->srbm_mutex); 2797 soc24_grbm_select(adev, 0, 0, 0, 0); 2798 2799 /* Trigger an invalidation of the L1 instruction caches */ 2800 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2801 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2802 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2803 2804 /* Wait for invalidation complete */ 2805 for (i = 0; i < usec_timeout; i++) { 2806 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2807 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2808 INVALIDATE_DCACHE_COMPLETE)) 2809 break; 2810 udelay(1); 2811 } 2812 2813 if (i >= usec_timeout) { 2814 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2815 return -EINVAL; 2816 } 2817 2818 /* Trigger an invalidation of the L1 instruction caches */ 2819 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2820 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2821 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2822 2823 /* Wait for invalidation complete */ 2824 for (i = 0; i < usec_timeout; i++) { 2825 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2826 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2827 INVALIDATE_CACHE_COMPLETE)) 2828 break; 2829 udelay(1); 2830 } 2831 2832 if (i >= usec_timeout) { 2833 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2834 return -EINVAL; 2835 } 2836 2837 gfx_v12_0_set_mec_ucode_start_addr(adev); 2838 2839 return 0; 2840 } 2841 2842 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2843 { 2844 uint32_t tmp; 2845 struct amdgpu_device *adev = ring->adev; 2846 2847 /* tell RLC which is KIQ queue */ 2848 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2849 tmp &= 0xffffff00; 2850 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2851 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2852 } 2853 2854 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2855 { 2856 /* set graphics engine doorbell range */ 2857 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2858 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2859 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2860 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2861 2862 /* set compute engine doorbell range */ 2863 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2864 (adev->doorbell_index.kiq * 2) << 2); 2865 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2866 (adev->doorbell_index.userqueue_end * 2) << 2); 2867 } 2868 2869 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2870 struct amdgpu_mqd_prop *prop) 2871 { 2872 struct v12_gfx_mqd *mqd = m; 2873 uint64_t hqd_gpu_addr, wb_gpu_addr; 2874 uint32_t tmp; 2875 uint32_t rb_bufsz; 2876 2877 /* set up gfx hqd wptr */ 2878 mqd->cp_gfx_hqd_wptr = 0; 2879 mqd->cp_gfx_hqd_wptr_hi = 0; 2880 2881 /* set the pointer to the MQD */ 2882 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2883 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2884 2885 /* set up mqd control */ 2886 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2887 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2888 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2889 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2890 mqd->cp_gfx_mqd_control = tmp; 2891 2892 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2893 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2894 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2895 mqd->cp_gfx_hqd_vmid = 0; 2896 2897 /* set up default queue priority level 2898 * 0x0 = low priority, 0x1 = high priority */ 2899 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2900 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2901 mqd->cp_gfx_hqd_queue_priority = tmp; 2902 2903 /* set up time quantum */ 2904 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2905 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2906 mqd->cp_gfx_hqd_quantum = tmp; 2907 2908 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2909 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2910 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2911 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2912 2913 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2914 wb_gpu_addr = prop->rptr_gpu_addr; 2915 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2916 mqd->cp_gfx_hqd_rptr_addr_hi = 2917 upper_32_bits(wb_gpu_addr) & 0xffff; 2918 2919 /* set up rb_wptr_poll addr */ 2920 wb_gpu_addr = prop->wptr_gpu_addr; 2921 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2922 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2923 2924 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2925 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2926 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2927 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2928 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2929 #ifdef __BIG_ENDIAN 2930 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2931 #endif 2932 mqd->cp_gfx_hqd_cntl = tmp; 2933 2934 /* set up cp_doorbell_control */ 2935 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2936 if (prop->use_doorbell) { 2937 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2938 DOORBELL_OFFSET, prop->doorbell_index); 2939 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2940 DOORBELL_EN, 1); 2941 } else 2942 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2943 DOORBELL_EN, 0); 2944 mqd->cp_rb_doorbell_control = tmp; 2945 2946 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2947 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2948 2949 /* active the queue */ 2950 mqd->cp_gfx_hqd_active = 1; 2951 2952 return 0; 2953 } 2954 2955 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2956 { 2957 struct amdgpu_device *adev = ring->adev; 2958 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2959 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2960 2961 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2962 memset((void *)mqd, 0, sizeof(*mqd)); 2963 mutex_lock(&adev->srbm_mutex); 2964 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2965 amdgpu_ring_init_mqd(ring); 2966 soc24_grbm_select(adev, 0, 0, 0, 0); 2967 mutex_unlock(&adev->srbm_mutex); 2968 if (adev->gfx.me.mqd_backup[mqd_idx]) 2969 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2970 } else { 2971 /* restore mqd with the backup copy */ 2972 if (adev->gfx.me.mqd_backup[mqd_idx]) 2973 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2974 /* reset the ring */ 2975 ring->wptr = 0; 2976 *ring->wptr_cpu_addr = 0; 2977 amdgpu_ring_clear_ring(ring); 2978 } 2979 2980 return 0; 2981 } 2982 2983 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2984 { 2985 int r, i; 2986 struct amdgpu_ring *ring; 2987 2988 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2989 ring = &adev->gfx.gfx_ring[i]; 2990 2991 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2992 if (unlikely(r != 0)) 2993 goto done; 2994 2995 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2996 if (!r) { 2997 r = gfx_v12_0_kgq_init_queue(ring, false); 2998 amdgpu_bo_kunmap(ring->mqd_obj); 2999 ring->mqd_ptr = NULL; 3000 } 3001 amdgpu_bo_unreserve(ring->mqd_obj); 3002 if (r) 3003 goto done; 3004 } 3005 3006 r = amdgpu_gfx_enable_kgq(adev, 0); 3007 if (r) 3008 goto done; 3009 3010 r = gfx_v12_0_cp_gfx_start(adev); 3011 if (r) 3012 goto done; 3013 3014 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3015 ring = &adev->gfx.gfx_ring[i]; 3016 ring->sched.ready = true; 3017 } 3018 done: 3019 return r; 3020 } 3021 3022 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3023 struct amdgpu_mqd_prop *prop) 3024 { 3025 struct v12_compute_mqd *mqd = m; 3026 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3027 uint32_t tmp; 3028 3029 mqd->header = 0xC0310800; 3030 mqd->compute_pipelinestat_enable = 0x00000001; 3031 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3032 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3033 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3034 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3035 mqd->compute_misc_reserved = 0x00000007; 3036 3037 eop_base_addr = prop->eop_gpu_addr >> 8; 3038 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3039 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3040 3041 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3042 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3043 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3044 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3045 3046 mqd->cp_hqd_eop_control = tmp; 3047 3048 /* enable doorbell? */ 3049 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3050 3051 if (prop->use_doorbell) { 3052 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3053 DOORBELL_OFFSET, prop->doorbell_index); 3054 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3055 DOORBELL_EN, 1); 3056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3057 DOORBELL_SOURCE, 0); 3058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3059 DOORBELL_HIT, 0); 3060 } else { 3061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3062 DOORBELL_EN, 0); 3063 } 3064 3065 mqd->cp_hqd_pq_doorbell_control = tmp; 3066 3067 /* disable the queue if it's active */ 3068 mqd->cp_hqd_dequeue_request = 0; 3069 mqd->cp_hqd_pq_rptr = 0; 3070 mqd->cp_hqd_pq_wptr_lo = 0; 3071 mqd->cp_hqd_pq_wptr_hi = 0; 3072 3073 /* set the pointer to the MQD */ 3074 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3075 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3076 3077 /* set MQD vmid to 0 */ 3078 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3079 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3080 mqd->cp_mqd_control = tmp; 3081 3082 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3083 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3084 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3085 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3086 3087 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3088 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3089 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3090 (order_base_2(prop->queue_size / 4) - 1)); 3091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3092 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3093 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3094 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3095 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3096 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3097 mqd->cp_hqd_pq_control = tmp; 3098 3099 /* set the wb address whether it's enabled or not */ 3100 wb_gpu_addr = prop->rptr_gpu_addr; 3101 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3102 mqd->cp_hqd_pq_rptr_report_addr_hi = 3103 upper_32_bits(wb_gpu_addr) & 0xffff; 3104 3105 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3106 wb_gpu_addr = prop->wptr_gpu_addr; 3107 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3108 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3109 3110 tmp = 0; 3111 /* enable the doorbell if requested */ 3112 if (prop->use_doorbell) { 3113 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3114 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3115 DOORBELL_OFFSET, prop->doorbell_index); 3116 3117 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3118 DOORBELL_EN, 1); 3119 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3120 DOORBELL_SOURCE, 0); 3121 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3122 DOORBELL_HIT, 0); 3123 } 3124 3125 mqd->cp_hqd_pq_doorbell_control = tmp; 3126 3127 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3128 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3129 3130 /* set the vmid for the queue */ 3131 mqd->cp_hqd_vmid = 0; 3132 3133 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3135 mqd->cp_hqd_persistent_state = tmp; 3136 3137 /* set MIN_IB_AVAIL_SIZE */ 3138 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3139 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3140 mqd->cp_hqd_ib_control = tmp; 3141 3142 /* set static priority for a compute queue/ring */ 3143 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3144 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3145 3146 mqd->cp_hqd_active = prop->hqd_active; 3147 3148 return 0; 3149 } 3150 3151 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3152 { 3153 struct amdgpu_device *adev = ring->adev; 3154 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3155 int j; 3156 3157 /* inactivate the queue */ 3158 if (amdgpu_sriov_vf(adev)) 3159 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3160 3161 /* disable wptr polling */ 3162 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3163 3164 /* write the EOP addr */ 3165 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3166 mqd->cp_hqd_eop_base_addr_lo); 3167 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3168 mqd->cp_hqd_eop_base_addr_hi); 3169 3170 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3171 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3172 mqd->cp_hqd_eop_control); 3173 3174 /* enable doorbell? */ 3175 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3176 mqd->cp_hqd_pq_doorbell_control); 3177 3178 /* disable the queue if it's active */ 3179 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3180 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3181 for (j = 0; j < adev->usec_timeout; j++) { 3182 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3183 break; 3184 udelay(1); 3185 } 3186 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3187 mqd->cp_hqd_dequeue_request); 3188 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3189 mqd->cp_hqd_pq_rptr); 3190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3191 mqd->cp_hqd_pq_wptr_lo); 3192 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3193 mqd->cp_hqd_pq_wptr_hi); 3194 } 3195 3196 /* set the pointer to the MQD */ 3197 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3198 mqd->cp_mqd_base_addr_lo); 3199 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3200 mqd->cp_mqd_base_addr_hi); 3201 3202 /* set MQD vmid to 0 */ 3203 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3204 mqd->cp_mqd_control); 3205 3206 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3208 mqd->cp_hqd_pq_base_lo); 3209 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3210 mqd->cp_hqd_pq_base_hi); 3211 3212 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3213 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3214 mqd->cp_hqd_pq_control); 3215 3216 /* set the wb address whether it's enabled or not */ 3217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3218 mqd->cp_hqd_pq_rptr_report_addr_lo); 3219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3220 mqd->cp_hqd_pq_rptr_report_addr_hi); 3221 3222 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3223 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3224 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3225 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3226 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3227 3228 /* enable the doorbell if requested */ 3229 if (ring->use_doorbell) { 3230 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3231 (adev->doorbell_index.kiq * 2) << 2); 3232 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3233 (adev->doorbell_index.userqueue_end * 2) << 2); 3234 } 3235 3236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3237 mqd->cp_hqd_pq_doorbell_control); 3238 3239 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3240 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3241 mqd->cp_hqd_pq_wptr_lo); 3242 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3243 mqd->cp_hqd_pq_wptr_hi); 3244 3245 /* set the vmid for the queue */ 3246 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3247 3248 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3249 mqd->cp_hqd_persistent_state); 3250 3251 /* activate the queue */ 3252 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3253 mqd->cp_hqd_active); 3254 3255 if (ring->use_doorbell) 3256 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3257 3258 return 0; 3259 } 3260 3261 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3262 { 3263 struct amdgpu_device *adev = ring->adev; 3264 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3265 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3266 3267 gfx_v12_0_kiq_setting(ring); 3268 3269 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3270 /* reset MQD to a clean status */ 3271 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3272 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3273 3274 /* reset ring buffer */ 3275 ring->wptr = 0; 3276 amdgpu_ring_clear_ring(ring); 3277 3278 mutex_lock(&adev->srbm_mutex); 3279 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3280 gfx_v12_0_kiq_init_register(ring); 3281 soc24_grbm_select(adev, 0, 0, 0, 0); 3282 mutex_unlock(&adev->srbm_mutex); 3283 } else { 3284 memset((void *)mqd, 0, sizeof(*mqd)); 3285 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3286 amdgpu_ring_clear_ring(ring); 3287 mutex_lock(&adev->srbm_mutex); 3288 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3289 amdgpu_ring_init_mqd(ring); 3290 gfx_v12_0_kiq_init_register(ring); 3291 soc24_grbm_select(adev, 0, 0, 0, 0); 3292 mutex_unlock(&adev->srbm_mutex); 3293 3294 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3295 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3302 { 3303 struct amdgpu_device *adev = ring->adev; 3304 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3305 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3306 3307 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3308 memset((void *)mqd, 0, sizeof(*mqd)); 3309 mutex_lock(&adev->srbm_mutex); 3310 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3311 amdgpu_ring_init_mqd(ring); 3312 soc24_grbm_select(adev, 0, 0, 0, 0); 3313 mutex_unlock(&adev->srbm_mutex); 3314 3315 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3316 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3317 } else { 3318 /* restore MQD to a clean status */ 3319 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3320 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3321 /* reset ring buffer */ 3322 ring->wptr = 0; 3323 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3324 amdgpu_ring_clear_ring(ring); 3325 } 3326 3327 return 0; 3328 } 3329 3330 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3331 { 3332 struct amdgpu_ring *ring; 3333 int r; 3334 3335 ring = &adev->gfx.kiq[0].ring; 3336 3337 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3338 if (unlikely(r != 0)) 3339 return r; 3340 3341 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3342 if (unlikely(r != 0)) { 3343 amdgpu_bo_unreserve(ring->mqd_obj); 3344 return r; 3345 } 3346 3347 gfx_v12_0_kiq_init_queue(ring); 3348 amdgpu_bo_kunmap(ring->mqd_obj); 3349 ring->mqd_ptr = NULL; 3350 amdgpu_bo_unreserve(ring->mqd_obj); 3351 ring->sched.ready = true; 3352 return 0; 3353 } 3354 3355 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3356 { 3357 struct amdgpu_ring *ring = NULL; 3358 int r = 0, i; 3359 3360 if (!amdgpu_async_gfx_ring) 3361 gfx_v12_0_cp_compute_enable(adev, true); 3362 3363 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3364 ring = &adev->gfx.compute_ring[i]; 3365 3366 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3367 if (unlikely(r != 0)) 3368 goto done; 3369 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3370 if (!r) { 3371 r = gfx_v12_0_kcq_init_queue(ring, false); 3372 amdgpu_bo_kunmap(ring->mqd_obj); 3373 ring->mqd_ptr = NULL; 3374 } 3375 amdgpu_bo_unreserve(ring->mqd_obj); 3376 if (r) 3377 goto done; 3378 } 3379 3380 r = amdgpu_gfx_enable_kcq(adev, 0); 3381 done: 3382 return r; 3383 } 3384 3385 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3386 { 3387 int r, i; 3388 struct amdgpu_ring *ring; 3389 3390 if (!(adev->flags & AMD_IS_APU)) 3391 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3392 3393 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3394 /* legacy firmware loading */ 3395 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3396 if (r) 3397 return r; 3398 3399 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3400 if (r) 3401 return r; 3402 } 3403 3404 gfx_v12_0_cp_set_doorbell_range(adev); 3405 3406 if (amdgpu_async_gfx_ring) { 3407 gfx_v12_0_cp_compute_enable(adev, true); 3408 gfx_v12_0_cp_gfx_enable(adev, true); 3409 } 3410 3411 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3412 r = amdgpu_mes_kiq_hw_init(adev); 3413 else 3414 r = gfx_v12_0_kiq_resume(adev); 3415 if (r) 3416 return r; 3417 3418 r = gfx_v12_0_kcq_resume(adev); 3419 if (r) 3420 return r; 3421 3422 if (!amdgpu_async_gfx_ring) { 3423 r = gfx_v12_0_cp_gfx_resume(adev); 3424 if (r) 3425 return r; 3426 } else { 3427 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3428 if (r) 3429 return r; 3430 } 3431 3432 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3433 ring = &adev->gfx.gfx_ring[i]; 3434 r = amdgpu_ring_test_helper(ring); 3435 if (r) 3436 return r; 3437 } 3438 3439 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3440 ring = &adev->gfx.compute_ring[i]; 3441 r = amdgpu_ring_test_helper(ring); 3442 if (r) 3443 return r; 3444 } 3445 3446 return 0; 3447 } 3448 3449 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3450 { 3451 gfx_v12_0_cp_gfx_enable(adev, enable); 3452 gfx_v12_0_cp_compute_enable(adev, enable); 3453 } 3454 3455 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3456 { 3457 int r; 3458 bool value; 3459 3460 r = adev->gfxhub.funcs->gart_enable(adev); 3461 if (r) 3462 return r; 3463 3464 adev->hdp.funcs->flush_hdp(adev, NULL); 3465 3466 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3467 false : true; 3468 3469 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3470 /* TODO investigate why this and the hdp flush above is needed, 3471 * are we missing a flush somewhere else? */ 3472 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3473 3474 return 0; 3475 } 3476 3477 static int get_gb_addr_config(struct amdgpu_device *adev) 3478 { 3479 u32 gb_addr_config; 3480 3481 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3482 if (gb_addr_config == 0) 3483 return -EINVAL; 3484 3485 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3486 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3487 3488 adev->gfx.config.gb_addr_config = gb_addr_config; 3489 3490 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3491 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3492 GB_ADDR_CONFIG, NUM_PIPES); 3493 3494 adev->gfx.config.max_tile_pipes = 3495 adev->gfx.config.gb_addr_config_fields.num_pipes; 3496 3497 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3498 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3499 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3500 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3501 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3502 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3503 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3504 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3505 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3506 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3507 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3508 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3509 3510 return 0; 3511 } 3512 3513 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3514 { 3515 uint32_t data; 3516 3517 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3518 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3519 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3520 3521 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3522 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3523 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3524 } 3525 3526 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3527 { 3528 if (amdgpu_sriov_vf(adev)) 3529 return; 3530 3531 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3532 case IP_VERSION(12, 0, 0): 3533 case IP_VERSION(12, 0, 1): 3534 soc15_program_register_sequence(adev, 3535 golden_settings_gc_12_0, 3536 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3537 3538 if (adev->rev_id == 0) 3539 soc15_program_register_sequence(adev, 3540 golden_settings_gc_12_0_rev0, 3541 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3542 break; 3543 default: 3544 break; 3545 } 3546 } 3547 3548 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3549 { 3550 int r; 3551 struct amdgpu_device *adev = ip_block->adev; 3552 3553 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3554 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3555 /* RLC autoload sequence 1: Program rlc ram */ 3556 if (adev->gfx.imu.funcs->program_rlc_ram) 3557 adev->gfx.imu.funcs->program_rlc_ram(adev); 3558 } 3559 /* rlc autoload firmware */ 3560 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3561 if (r) 3562 return r; 3563 } else { 3564 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3565 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3566 if (adev->gfx.imu.funcs->load_microcode) 3567 adev->gfx.imu.funcs->load_microcode(adev); 3568 if (adev->gfx.imu.funcs->setup_imu) 3569 adev->gfx.imu.funcs->setup_imu(adev); 3570 if (adev->gfx.imu.funcs->start_imu) 3571 adev->gfx.imu.funcs->start_imu(adev); 3572 } 3573 3574 /* disable gpa mode in backdoor loading */ 3575 gfx_v12_0_disable_gpa_mode(adev); 3576 } 3577 } 3578 3579 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3580 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3581 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3582 if (r) { 3583 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3584 return r; 3585 } 3586 } 3587 3588 if (!amdgpu_emu_mode) 3589 gfx_v12_0_init_golden_registers(adev); 3590 3591 adev->gfx.is_poweron = true; 3592 3593 if (get_gb_addr_config(adev)) 3594 DRM_WARN("Invalid gb_addr_config !\n"); 3595 3596 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3597 gfx_v12_0_config_gfx_rs64(adev); 3598 3599 r = gfx_v12_0_gfxhub_enable(adev); 3600 if (r) 3601 return r; 3602 3603 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3604 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3605 (amdgpu_dpm == 1)) { 3606 /** 3607 * For gfx 12, rlc firmware loading relies on smu firmware is 3608 * loaded firstly, so in direct type, it has to load smc ucode 3609 * here before rlc. 3610 */ 3611 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3612 if (r) 3613 return r; 3614 } 3615 3616 gfx_v12_0_constants_init(adev); 3617 3618 if (adev->nbio.funcs->gc_doorbell_init) 3619 adev->nbio.funcs->gc_doorbell_init(adev); 3620 3621 r = gfx_v12_0_rlc_resume(adev); 3622 if (r) 3623 return r; 3624 3625 /* 3626 * init golden registers and rlc resume may override some registers, 3627 * reconfig them here 3628 */ 3629 gfx_v12_0_tcp_harvest(adev); 3630 3631 r = gfx_v12_0_cp_resume(adev); 3632 if (r) 3633 return r; 3634 3635 return r; 3636 } 3637 3638 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3639 { 3640 struct amdgpu_device *adev = ip_block->adev; 3641 uint32_t tmp; 3642 3643 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3644 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3645 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3646 3647 if (!adev->no_hw_access) { 3648 if (amdgpu_async_gfx_ring) { 3649 if (amdgpu_gfx_disable_kgq(adev, 0)) 3650 DRM_ERROR("KGQ disable failed\n"); 3651 } 3652 3653 if (amdgpu_gfx_disable_kcq(adev, 0)) 3654 DRM_ERROR("KCQ disable failed\n"); 3655 3656 amdgpu_mes_kiq_hw_fini(adev); 3657 } 3658 3659 if (amdgpu_sriov_vf(adev)) { 3660 gfx_v12_0_cp_gfx_enable(adev, false); 3661 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3662 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3663 tmp &= 0xffffff00; 3664 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3665 3666 return 0; 3667 } 3668 gfx_v12_0_cp_enable(adev, false); 3669 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3670 3671 adev->gfxhub.funcs->gart_disable(adev); 3672 3673 adev->gfx.is_poweron = false; 3674 3675 return 0; 3676 } 3677 3678 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3679 { 3680 return gfx_v12_0_hw_fini(ip_block); 3681 } 3682 3683 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3684 { 3685 return gfx_v12_0_hw_init(ip_block); 3686 } 3687 3688 static bool gfx_v12_0_is_idle(void *handle) 3689 { 3690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3691 3692 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3693 GRBM_STATUS, GUI_ACTIVE)) 3694 return false; 3695 else 3696 return true; 3697 } 3698 3699 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3700 { 3701 unsigned i; 3702 u32 tmp; 3703 struct amdgpu_device *adev = ip_block->adev; 3704 3705 for (i = 0; i < adev->usec_timeout; i++) { 3706 /* read MC_STATUS */ 3707 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3708 GRBM_STATUS__GUI_ACTIVE_MASK; 3709 3710 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3711 return 0; 3712 udelay(1); 3713 } 3714 return -ETIMEDOUT; 3715 } 3716 3717 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3718 { 3719 uint64_t clock = 0; 3720 3721 if (adev->smuio.funcs && 3722 adev->smuio.funcs->get_gpu_clock_counter) 3723 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3724 else 3725 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3726 3727 return clock; 3728 } 3729 3730 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3731 { 3732 struct amdgpu_device *adev = ip_block->adev; 3733 3734 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3735 3736 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3737 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3738 AMDGPU_MAX_COMPUTE_RINGS); 3739 3740 gfx_v12_0_set_kiq_pm4_funcs(adev); 3741 gfx_v12_0_set_ring_funcs(adev); 3742 gfx_v12_0_set_irq_funcs(adev); 3743 gfx_v12_0_set_rlc_funcs(adev); 3744 gfx_v12_0_set_mqd_funcs(adev); 3745 gfx_v12_0_set_imu_funcs(adev); 3746 3747 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3748 3749 return gfx_v12_0_init_microcode(adev); 3750 } 3751 3752 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3753 { 3754 struct amdgpu_device *adev = ip_block->adev; 3755 int r; 3756 3757 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3758 if (r) 3759 return r; 3760 3761 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3762 if (r) 3763 return r; 3764 3765 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3766 if (r) 3767 return r; 3768 3769 return 0; 3770 } 3771 3772 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3773 { 3774 uint32_t rlc_cntl; 3775 3776 /* if RLC is not enabled, do nothing */ 3777 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3778 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3779 } 3780 3781 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3782 int xcc_id) 3783 { 3784 uint32_t data; 3785 unsigned i; 3786 3787 data = RLC_SAFE_MODE__CMD_MASK; 3788 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3789 3790 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3791 3792 /* wait for RLC_SAFE_MODE */ 3793 for (i = 0; i < adev->usec_timeout; i++) { 3794 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3795 RLC_SAFE_MODE, CMD)) 3796 break; 3797 udelay(1); 3798 } 3799 } 3800 3801 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3802 int xcc_id) 3803 { 3804 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3805 } 3806 3807 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3808 bool enable) 3809 { 3810 uint32_t def, data; 3811 3812 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3813 return; 3814 3815 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3816 3817 if (enable) 3818 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3819 else 3820 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3821 3822 if (def != data) 3823 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3824 } 3825 3826 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3827 struct amdgpu_ring *ring, 3828 unsigned vmid) 3829 { 3830 u32 reg, data; 3831 3832 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3833 if (amdgpu_sriov_is_pp_one_vf(adev)) 3834 data = RREG32_NO_KIQ(reg); 3835 else 3836 data = RREG32(reg); 3837 3838 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3839 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3840 3841 if (amdgpu_sriov_is_pp_one_vf(adev)) 3842 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3843 else 3844 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3845 3846 if (ring 3847 && amdgpu_sriov_is_pp_one_vf(adev) 3848 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3849 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3850 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3851 amdgpu_ring_emit_wreg(ring, reg, data); 3852 } 3853 } 3854 3855 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3856 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3857 .set_safe_mode = gfx_v12_0_set_safe_mode, 3858 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3859 .init = gfx_v12_0_rlc_init, 3860 .get_csb_size = gfx_v12_0_get_csb_size, 3861 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3862 .resume = gfx_v12_0_rlc_resume, 3863 .stop = gfx_v12_0_rlc_stop, 3864 .reset = gfx_v12_0_rlc_reset, 3865 .start = gfx_v12_0_rlc_start, 3866 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3867 }; 3868 3869 #if 0 3870 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3871 { 3872 /* TODO */ 3873 } 3874 3875 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3876 { 3877 /* TODO */ 3878 } 3879 #endif 3880 3881 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3882 enum amd_powergating_state state) 3883 { 3884 struct amdgpu_device *adev = ip_block->adev; 3885 bool enable = (state == AMD_PG_STATE_GATE); 3886 3887 if (amdgpu_sriov_vf(adev)) 3888 return 0; 3889 3890 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3891 case IP_VERSION(12, 0, 0): 3892 case IP_VERSION(12, 0, 1): 3893 amdgpu_gfx_off_ctrl(adev, enable); 3894 break; 3895 default: 3896 break; 3897 } 3898 3899 return 0; 3900 } 3901 3902 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3903 bool enable) 3904 { 3905 uint32_t def, data; 3906 3907 if (!(adev->cg_flags & 3908 (AMD_CG_SUPPORT_GFX_CGCG | 3909 AMD_CG_SUPPORT_GFX_CGLS | 3910 AMD_CG_SUPPORT_GFX_3D_CGCG | 3911 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3912 return; 3913 3914 if (enable) { 3915 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3916 3917 /* unset CGCG override */ 3918 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3919 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3920 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3921 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3922 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3923 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3924 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3925 3926 /* update CGCG override bits */ 3927 if (def != data) 3928 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3929 3930 /* enable cgcg FSM(0x0000363F) */ 3931 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3932 3933 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3934 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3935 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3936 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3937 } 3938 3939 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3940 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3941 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3942 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3943 } 3944 3945 if (def != data) 3946 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3947 3948 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3949 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3950 3951 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3952 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3953 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3954 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3955 } 3956 3957 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3958 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3959 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3960 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3961 } 3962 3963 if (def != data) 3964 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3965 3966 /* set IDLE_POLL_COUNT(0x00900100) */ 3967 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3968 3969 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3970 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3971 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3972 3973 if (def != data) 3974 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3975 3976 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3977 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3978 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3979 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3980 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3981 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3982 3983 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3984 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3985 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3986 3987 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3988 if (adev->sdma.num_instances > 1) { 3989 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3990 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3991 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3992 } 3993 } else { 3994 /* Program RLC_CGCG_CGLS_CTRL */ 3995 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3996 3997 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3998 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3999 4000 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4001 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4002 4003 if (def != data) 4004 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4005 4006 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4007 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4008 4009 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4010 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4011 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4012 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4013 4014 if (def != data) 4015 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4016 4017 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4018 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4019 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4020 4021 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4022 if (adev->sdma.num_instances > 1) { 4023 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4024 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4025 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4026 } 4027 } 4028 } 4029 4030 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4031 bool enable) 4032 { 4033 uint32_t data, def; 4034 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4035 return; 4036 4037 /* It is disabled by HW by default */ 4038 if (enable) { 4039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4040 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4041 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4042 4043 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4044 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4045 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4046 4047 if (def != data) 4048 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4049 } 4050 } else { 4051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4052 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4053 4054 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4055 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4056 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4057 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4060 } 4061 } 4062 } 4063 4064 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4065 bool enable) 4066 { 4067 uint32_t def, data; 4068 4069 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4070 return; 4071 4072 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4073 4074 if (enable) 4075 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4076 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4077 else 4078 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4079 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4080 4081 if (def != data) 4082 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4083 } 4084 4085 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4086 bool enable) 4087 { 4088 uint32_t def, data; 4089 4090 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4091 return; 4092 4093 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4094 4095 if (enable) 4096 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4097 else 4098 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4099 4100 if (def != data) 4101 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4102 } 4103 4104 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4105 bool enable) 4106 { 4107 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4108 4109 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4110 4111 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4112 4113 gfx_v12_0_update_repeater_fgcg(adev, enable); 4114 4115 gfx_v12_0_update_sram_fgcg(adev, enable); 4116 4117 gfx_v12_0_update_perf_clk(adev, enable); 4118 4119 if (adev->cg_flags & 4120 (AMD_CG_SUPPORT_GFX_MGCG | 4121 AMD_CG_SUPPORT_GFX_CGLS | 4122 AMD_CG_SUPPORT_GFX_CGCG | 4123 AMD_CG_SUPPORT_GFX_3D_CGCG | 4124 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4125 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4126 4127 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4128 4129 return 0; 4130 } 4131 4132 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4133 enum amd_clockgating_state state) 4134 { 4135 struct amdgpu_device *adev = ip_block->adev; 4136 4137 if (amdgpu_sriov_vf(adev)) 4138 return 0; 4139 4140 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4141 case IP_VERSION(12, 0, 0): 4142 case IP_VERSION(12, 0, 1): 4143 gfx_v12_0_update_gfx_clock_gating(adev, 4144 state == AMD_CG_STATE_GATE); 4145 break; 4146 default: 4147 break; 4148 } 4149 4150 return 0; 4151 } 4152 4153 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 4154 { 4155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4156 int data; 4157 4158 /* AMD_CG_SUPPORT_GFX_MGCG */ 4159 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4160 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4161 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4162 4163 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4164 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4165 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4166 4167 /* AMD_CG_SUPPORT_GFX_FGCG */ 4168 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4169 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4170 4171 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4172 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4173 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4174 4175 /* AMD_CG_SUPPORT_GFX_CGCG */ 4176 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4177 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4178 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4179 4180 /* AMD_CG_SUPPORT_GFX_CGLS */ 4181 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4182 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4183 4184 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4185 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4186 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4187 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4188 4189 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4190 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4191 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4192 } 4193 4194 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4195 { 4196 /* gfx12 is 32bit rptr*/ 4197 return *(uint32_t *)ring->rptr_cpu_addr; 4198 } 4199 4200 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4201 { 4202 struct amdgpu_device *adev = ring->adev; 4203 u64 wptr; 4204 4205 /* XXX check if swapping is necessary on BE */ 4206 if (ring->use_doorbell) { 4207 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4208 } else { 4209 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4210 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4211 } 4212 4213 return wptr; 4214 } 4215 4216 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4217 { 4218 struct amdgpu_device *adev = ring->adev; 4219 uint32_t *wptr_saved; 4220 uint32_t *is_queue_unmap; 4221 uint64_t aggregated_db_index; 4222 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4223 uint64_t wptr_tmp; 4224 4225 if (ring->is_mes_queue) { 4226 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4227 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4228 sizeof(uint32_t)); 4229 aggregated_db_index = 4230 amdgpu_mes_get_aggregated_doorbell_index(adev, 4231 ring->hw_prio); 4232 4233 wptr_tmp = ring->wptr & ring->buf_mask; 4234 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4235 *wptr_saved = wptr_tmp; 4236 /* assume doorbell always being used by mes mapped queue */ 4237 if (*is_queue_unmap) { 4238 WDOORBELL64(aggregated_db_index, wptr_tmp); 4239 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4240 } else { 4241 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4242 4243 if (*is_queue_unmap) 4244 WDOORBELL64(aggregated_db_index, wptr_tmp); 4245 } 4246 } else { 4247 if (ring->use_doorbell) { 4248 /* XXX check if swapping is necessary on BE */ 4249 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4250 ring->wptr); 4251 WDOORBELL64(ring->doorbell_index, ring->wptr); 4252 } else { 4253 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4254 lower_32_bits(ring->wptr)); 4255 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4256 upper_32_bits(ring->wptr)); 4257 } 4258 } 4259 } 4260 4261 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4262 { 4263 /* gfx12 hardware is 32bit rptr */ 4264 return *(uint32_t *)ring->rptr_cpu_addr; 4265 } 4266 4267 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4268 { 4269 u64 wptr; 4270 4271 /* XXX check if swapping is necessary on BE */ 4272 if (ring->use_doorbell) 4273 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4274 else 4275 BUG(); 4276 return wptr; 4277 } 4278 4279 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4280 { 4281 struct amdgpu_device *adev = ring->adev; 4282 uint32_t *wptr_saved; 4283 uint32_t *is_queue_unmap; 4284 uint64_t aggregated_db_index; 4285 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4286 uint64_t wptr_tmp; 4287 4288 if (ring->is_mes_queue) { 4289 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4290 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4291 sizeof(uint32_t)); 4292 aggregated_db_index = 4293 amdgpu_mes_get_aggregated_doorbell_index(adev, 4294 ring->hw_prio); 4295 4296 wptr_tmp = ring->wptr & ring->buf_mask; 4297 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4298 *wptr_saved = wptr_tmp; 4299 /* assume doorbell always used by mes mapped queue */ 4300 if (*is_queue_unmap) { 4301 WDOORBELL64(aggregated_db_index, wptr_tmp); 4302 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4303 } else { 4304 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4305 4306 if (*is_queue_unmap) 4307 WDOORBELL64(aggregated_db_index, wptr_tmp); 4308 } 4309 } else { 4310 /* XXX check if swapping is necessary on BE */ 4311 if (ring->use_doorbell) { 4312 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4313 ring->wptr); 4314 WDOORBELL64(ring->doorbell_index, ring->wptr); 4315 } else { 4316 BUG(); /* only DOORBELL method supported on gfx12 now */ 4317 } 4318 } 4319 } 4320 4321 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4322 { 4323 struct amdgpu_device *adev = ring->adev; 4324 u32 ref_and_mask, reg_mem_engine; 4325 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4326 4327 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4328 switch (ring->me) { 4329 case 1: 4330 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4331 break; 4332 case 2: 4333 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4334 break; 4335 default: 4336 return; 4337 } 4338 reg_mem_engine = 0; 4339 } else { 4340 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4341 reg_mem_engine = 1; /* pfp */ 4342 } 4343 4344 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4345 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4346 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4347 ref_and_mask, ref_and_mask, 0x20); 4348 } 4349 4350 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4351 struct amdgpu_job *job, 4352 struct amdgpu_ib *ib, 4353 uint32_t flags) 4354 { 4355 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4356 u32 header, control = 0; 4357 4358 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4359 4360 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4361 4362 control |= ib->length_dw | (vmid << 24); 4363 4364 if (ring->is_mes_queue) 4365 /* inherit vmid from mqd */ 4366 control |= 0x400000; 4367 4368 amdgpu_ring_write(ring, header); 4369 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4370 amdgpu_ring_write(ring, 4371 #ifdef __BIG_ENDIAN 4372 (2 << 0) | 4373 #endif 4374 lower_32_bits(ib->gpu_addr)); 4375 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4376 amdgpu_ring_write(ring, control); 4377 } 4378 4379 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4380 struct amdgpu_job *job, 4381 struct amdgpu_ib *ib, 4382 uint32_t flags) 4383 { 4384 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4385 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4386 4387 if (ring->is_mes_queue) 4388 /* inherit vmid from mqd */ 4389 control |= 0x40000000; 4390 4391 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4392 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4393 amdgpu_ring_write(ring, 4394 #ifdef __BIG_ENDIAN 4395 (2 << 0) | 4396 #endif 4397 lower_32_bits(ib->gpu_addr)); 4398 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4399 amdgpu_ring_write(ring, control); 4400 } 4401 4402 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4403 u64 seq, unsigned flags) 4404 { 4405 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4406 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4407 4408 /* RELEASE_MEM - flush caches, send int */ 4409 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4410 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4411 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4412 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4413 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4414 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4415 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4416 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4417 4418 /* 4419 * the address should be Qword aligned if 64bit write, Dword 4420 * aligned if only send 32bit data low (discard data high) 4421 */ 4422 if (write64bit) 4423 BUG_ON(addr & 0x7); 4424 else 4425 BUG_ON(addr & 0x3); 4426 amdgpu_ring_write(ring, lower_32_bits(addr)); 4427 amdgpu_ring_write(ring, upper_32_bits(addr)); 4428 amdgpu_ring_write(ring, lower_32_bits(seq)); 4429 amdgpu_ring_write(ring, upper_32_bits(seq)); 4430 amdgpu_ring_write(ring, ring->is_mes_queue ? 4431 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4432 } 4433 4434 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4435 { 4436 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4437 uint32_t seq = ring->fence_drv.sync_seq; 4438 uint64_t addr = ring->fence_drv.gpu_addr; 4439 4440 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4441 upper_32_bits(addr), seq, 0xffffffff, 4); 4442 } 4443 4444 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4445 uint16_t pasid, uint32_t flush_type, 4446 bool all_hub, uint8_t dst_sel) 4447 { 4448 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4449 amdgpu_ring_write(ring, 4450 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4451 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4452 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4453 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4454 } 4455 4456 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4457 unsigned vmid, uint64_t pd_addr) 4458 { 4459 if (ring->is_mes_queue) 4460 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4461 else 4462 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4463 4464 /* compute doesn't have PFP */ 4465 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4466 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4467 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4468 amdgpu_ring_write(ring, 0x0); 4469 } 4470 } 4471 4472 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4473 u64 seq, unsigned int flags) 4474 { 4475 struct amdgpu_device *adev = ring->adev; 4476 4477 /* we only allocate 32bit for each seq wb address */ 4478 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4479 4480 /* write fence seq to the "addr" */ 4481 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4482 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4483 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4484 amdgpu_ring_write(ring, lower_32_bits(addr)); 4485 amdgpu_ring_write(ring, upper_32_bits(addr)); 4486 amdgpu_ring_write(ring, lower_32_bits(seq)); 4487 4488 if (flags & AMDGPU_FENCE_FLAG_INT) { 4489 /* set register to trigger INT */ 4490 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4491 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4492 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4493 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4494 amdgpu_ring_write(ring, 0); 4495 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4496 } 4497 } 4498 4499 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4500 uint32_t flags) 4501 { 4502 uint32_t dw2 = 0; 4503 4504 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4505 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4506 /* set load_global_config & load_global_uconfig */ 4507 dw2 |= 0x8001; 4508 /* set load_cs_sh_regs */ 4509 dw2 |= 0x01000000; 4510 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4511 dw2 |= 0x10002; 4512 } 4513 4514 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4515 amdgpu_ring_write(ring, dw2); 4516 amdgpu_ring_write(ring, 0); 4517 } 4518 4519 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4520 uint64_t addr) 4521 { 4522 unsigned ret; 4523 4524 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4525 amdgpu_ring_write(ring, lower_32_bits(addr)); 4526 amdgpu_ring_write(ring, upper_32_bits(addr)); 4527 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4528 amdgpu_ring_write(ring, 0); 4529 ret = ring->wptr & ring->buf_mask; 4530 /* patch dummy value later */ 4531 amdgpu_ring_write(ring, 0); 4532 4533 return ret; 4534 } 4535 4536 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4537 { 4538 int i, r = 0; 4539 struct amdgpu_device *adev = ring->adev; 4540 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4541 struct amdgpu_ring *kiq_ring = &kiq->ring; 4542 unsigned long flags; 4543 4544 if (adev->enable_mes) 4545 return -EINVAL; 4546 4547 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4548 return -EINVAL; 4549 4550 spin_lock_irqsave(&kiq->ring_lock, flags); 4551 4552 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4553 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4554 return -ENOMEM; 4555 } 4556 4557 /* assert preemption condition */ 4558 amdgpu_ring_set_preempt_cond_exec(ring, false); 4559 4560 /* assert IB preemption, emit the trailing fence */ 4561 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4562 ring->trail_fence_gpu_addr, 4563 ++ring->trail_seq); 4564 amdgpu_ring_commit(kiq_ring); 4565 4566 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4567 4568 /* poll the trailing fence */ 4569 for (i = 0; i < adev->usec_timeout; i++) { 4570 if (ring->trail_seq == 4571 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4572 break; 4573 udelay(1); 4574 } 4575 4576 if (i >= adev->usec_timeout) { 4577 r = -EINVAL; 4578 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4579 } 4580 4581 /* deassert preemption condition */ 4582 amdgpu_ring_set_preempt_cond_exec(ring, true); 4583 return r; 4584 } 4585 4586 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4587 bool start, 4588 bool secure) 4589 { 4590 uint32_t v = secure ? FRAME_TMZ : 0; 4591 4592 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4593 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4594 } 4595 4596 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4597 uint32_t reg_val_offs) 4598 { 4599 struct amdgpu_device *adev = ring->adev; 4600 4601 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4602 amdgpu_ring_write(ring, 0 | /* src: register*/ 4603 (5 << 8) | /* dst: memory */ 4604 (1 << 20)); /* write confirm */ 4605 amdgpu_ring_write(ring, reg); 4606 amdgpu_ring_write(ring, 0); 4607 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4608 reg_val_offs * 4)); 4609 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4610 reg_val_offs * 4)); 4611 } 4612 4613 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4614 uint32_t reg, 4615 uint32_t val) 4616 { 4617 uint32_t cmd = 0; 4618 4619 switch (ring->funcs->type) { 4620 case AMDGPU_RING_TYPE_GFX: 4621 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4622 break; 4623 case AMDGPU_RING_TYPE_KIQ: 4624 cmd = (1 << 16); /* no inc addr */ 4625 break; 4626 default: 4627 cmd = WR_CONFIRM; 4628 break; 4629 } 4630 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4631 amdgpu_ring_write(ring, cmd); 4632 amdgpu_ring_write(ring, reg); 4633 amdgpu_ring_write(ring, 0); 4634 amdgpu_ring_write(ring, val); 4635 } 4636 4637 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4638 uint32_t val, uint32_t mask) 4639 { 4640 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4641 } 4642 4643 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4644 uint32_t reg0, uint32_t reg1, 4645 uint32_t ref, uint32_t mask) 4646 { 4647 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4648 4649 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4650 ref, mask, 0x20); 4651 } 4652 4653 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4654 unsigned vmid) 4655 { 4656 struct amdgpu_device *adev = ring->adev; 4657 uint32_t value = 0; 4658 4659 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4660 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4661 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4662 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4663 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4664 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4665 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4666 } 4667 4668 static void 4669 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4670 uint32_t me, uint32_t pipe, 4671 enum amdgpu_interrupt_state state) 4672 { 4673 uint32_t cp_int_cntl, cp_int_cntl_reg; 4674 4675 if (!me) { 4676 switch (pipe) { 4677 case 0: 4678 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4679 break; 4680 default: 4681 DRM_DEBUG("invalid pipe %d\n", pipe); 4682 return; 4683 } 4684 } else { 4685 DRM_DEBUG("invalid me %d\n", me); 4686 return; 4687 } 4688 4689 switch (state) { 4690 case AMDGPU_IRQ_STATE_DISABLE: 4691 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4692 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4693 TIME_STAMP_INT_ENABLE, 0); 4694 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4695 GENERIC0_INT_ENABLE, 0); 4696 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4697 break; 4698 case AMDGPU_IRQ_STATE_ENABLE: 4699 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4700 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4701 TIME_STAMP_INT_ENABLE, 1); 4702 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4703 GENERIC0_INT_ENABLE, 1); 4704 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4705 break; 4706 default: 4707 break; 4708 } 4709 } 4710 4711 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4712 int me, int pipe, 4713 enum amdgpu_interrupt_state state) 4714 { 4715 u32 mec_int_cntl, mec_int_cntl_reg; 4716 4717 /* 4718 * amdgpu controls only the first MEC. That's why this function only 4719 * handles the setting of interrupts for this specific MEC. All other 4720 * pipes' interrupts are set by amdkfd. 4721 */ 4722 4723 if (me == 1) { 4724 switch (pipe) { 4725 case 0: 4726 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4727 break; 4728 case 1: 4729 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4730 break; 4731 default: 4732 DRM_DEBUG("invalid pipe %d\n", pipe); 4733 return; 4734 } 4735 } else { 4736 DRM_DEBUG("invalid me %d\n", me); 4737 return; 4738 } 4739 4740 switch (state) { 4741 case AMDGPU_IRQ_STATE_DISABLE: 4742 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4743 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4744 TIME_STAMP_INT_ENABLE, 0); 4745 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4746 GENERIC0_INT_ENABLE, 0); 4747 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4748 break; 4749 case AMDGPU_IRQ_STATE_ENABLE: 4750 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4751 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4752 TIME_STAMP_INT_ENABLE, 1); 4753 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4754 GENERIC0_INT_ENABLE, 1); 4755 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4756 break; 4757 default: 4758 break; 4759 } 4760 } 4761 4762 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4763 struct amdgpu_irq_src *src, 4764 unsigned type, 4765 enum amdgpu_interrupt_state state) 4766 { 4767 switch (type) { 4768 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4769 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4770 break; 4771 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4772 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4773 break; 4774 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4775 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4776 break; 4777 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4778 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4779 break; 4780 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4781 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4782 break; 4783 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4784 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4785 break; 4786 default: 4787 break; 4788 } 4789 return 0; 4790 } 4791 4792 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4793 struct amdgpu_irq_src *source, 4794 struct amdgpu_iv_entry *entry) 4795 { 4796 int i; 4797 u8 me_id, pipe_id, queue_id; 4798 struct amdgpu_ring *ring; 4799 uint32_t mes_queue_id = entry->src_data[0]; 4800 4801 DRM_DEBUG("IH: CP EOP\n"); 4802 4803 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4804 struct amdgpu_mes_queue *queue; 4805 4806 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4807 4808 spin_lock(&adev->mes.queue_id_lock); 4809 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4810 if (queue) { 4811 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4812 amdgpu_fence_process(queue->ring); 4813 } 4814 spin_unlock(&adev->mes.queue_id_lock); 4815 } else { 4816 me_id = (entry->ring_id & 0x0c) >> 2; 4817 pipe_id = (entry->ring_id & 0x03) >> 0; 4818 queue_id = (entry->ring_id & 0x70) >> 4; 4819 4820 switch (me_id) { 4821 case 0: 4822 if (pipe_id == 0) 4823 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4824 else 4825 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4826 break; 4827 case 1: 4828 case 2: 4829 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4830 ring = &adev->gfx.compute_ring[i]; 4831 /* Per-queue interrupt is supported for MEC starting from VI. 4832 * The interrupt can only be enabled/disabled per pipe instead 4833 * of per queue. 4834 */ 4835 if ((ring->me == me_id) && 4836 (ring->pipe == pipe_id) && 4837 (ring->queue == queue_id)) 4838 amdgpu_fence_process(ring); 4839 } 4840 break; 4841 } 4842 } 4843 4844 return 0; 4845 } 4846 4847 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4848 struct amdgpu_irq_src *source, 4849 unsigned int type, 4850 enum amdgpu_interrupt_state state) 4851 { 4852 u32 cp_int_cntl_reg, cp_int_cntl; 4853 int i, j; 4854 4855 switch (state) { 4856 case AMDGPU_IRQ_STATE_DISABLE: 4857 case AMDGPU_IRQ_STATE_ENABLE: 4858 for (i = 0; i < adev->gfx.me.num_me; i++) { 4859 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4860 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4861 4862 if (cp_int_cntl_reg) { 4863 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4864 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4865 PRIV_REG_INT_ENABLE, 4866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4867 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4868 } 4869 } 4870 } 4871 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4872 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4873 /* MECs start at 1 */ 4874 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4875 4876 if (cp_int_cntl_reg) { 4877 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4878 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4879 PRIV_REG_INT_ENABLE, 4880 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4881 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4882 } 4883 } 4884 } 4885 break; 4886 default: 4887 break; 4888 } 4889 4890 return 0; 4891 } 4892 4893 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4894 struct amdgpu_irq_src *source, 4895 unsigned type, 4896 enum amdgpu_interrupt_state state) 4897 { 4898 u32 cp_int_cntl_reg, cp_int_cntl; 4899 int i, j; 4900 4901 switch (state) { 4902 case AMDGPU_IRQ_STATE_DISABLE: 4903 case AMDGPU_IRQ_STATE_ENABLE: 4904 for (i = 0; i < adev->gfx.me.num_me; i++) { 4905 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4906 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4907 4908 if (cp_int_cntl_reg) { 4909 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4910 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4911 OPCODE_ERROR_INT_ENABLE, 4912 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4913 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4914 } 4915 } 4916 } 4917 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4918 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4919 /* MECs start at 1 */ 4920 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4921 4922 if (cp_int_cntl_reg) { 4923 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4924 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4925 OPCODE_ERROR_INT_ENABLE, 4926 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4927 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4928 } 4929 } 4930 } 4931 break; 4932 default: 4933 break; 4934 } 4935 return 0; 4936 } 4937 4938 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4939 struct amdgpu_irq_src *source, 4940 unsigned int type, 4941 enum amdgpu_interrupt_state state) 4942 { 4943 u32 cp_int_cntl_reg, cp_int_cntl; 4944 int i, j; 4945 4946 switch (state) { 4947 case AMDGPU_IRQ_STATE_DISABLE: 4948 case AMDGPU_IRQ_STATE_ENABLE: 4949 for (i = 0; i < adev->gfx.me.num_me; i++) { 4950 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4951 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4952 4953 if (cp_int_cntl_reg) { 4954 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4955 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4956 PRIV_INSTR_INT_ENABLE, 4957 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4958 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4959 } 4960 } 4961 } 4962 break; 4963 default: 4964 break; 4965 } 4966 4967 return 0; 4968 } 4969 4970 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4971 struct amdgpu_iv_entry *entry) 4972 { 4973 u8 me_id, pipe_id, queue_id; 4974 struct amdgpu_ring *ring; 4975 int i; 4976 4977 me_id = (entry->ring_id & 0x0c) >> 2; 4978 pipe_id = (entry->ring_id & 0x03) >> 0; 4979 queue_id = (entry->ring_id & 0x70) >> 4; 4980 4981 switch (me_id) { 4982 case 0: 4983 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4984 ring = &adev->gfx.gfx_ring[i]; 4985 if (ring->me == me_id && ring->pipe == pipe_id && 4986 ring->queue == queue_id) 4987 drm_sched_fault(&ring->sched); 4988 } 4989 break; 4990 case 1: 4991 case 2: 4992 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4993 ring = &adev->gfx.compute_ring[i]; 4994 if (ring->me == me_id && ring->pipe == pipe_id && 4995 ring->queue == queue_id) 4996 drm_sched_fault(&ring->sched); 4997 } 4998 break; 4999 default: 5000 BUG(); 5001 break; 5002 } 5003 } 5004 5005 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5006 struct amdgpu_irq_src *source, 5007 struct amdgpu_iv_entry *entry) 5008 { 5009 DRM_ERROR("Illegal register access in command stream\n"); 5010 gfx_v12_0_handle_priv_fault(adev, entry); 5011 return 0; 5012 } 5013 5014 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5015 struct amdgpu_irq_src *source, 5016 struct amdgpu_iv_entry *entry) 5017 { 5018 DRM_ERROR("Illegal opcode in command stream \n"); 5019 gfx_v12_0_handle_priv_fault(adev, entry); 5020 return 0; 5021 } 5022 5023 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5024 struct amdgpu_irq_src *source, 5025 struct amdgpu_iv_entry *entry) 5026 { 5027 DRM_ERROR("Illegal instruction in command stream\n"); 5028 gfx_v12_0_handle_priv_fault(adev, entry); 5029 return 0; 5030 } 5031 5032 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5033 { 5034 const unsigned int gcr_cntl = 5035 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5036 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5037 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5038 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5039 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5040 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5041 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5042 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5043 5044 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5045 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5046 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5047 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5048 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5049 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5050 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5051 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5052 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5053 } 5054 5055 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5056 { 5057 /* Header itself is a NOP packet */ 5058 if (num_nop == 1) { 5059 amdgpu_ring_write(ring, ring->funcs->nop); 5060 return; 5061 } 5062 5063 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5064 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5065 5066 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5067 amdgpu_ring_insert_nop(ring, num_nop - 1); 5068 } 5069 5070 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5071 { 5072 /* Emit the cleaner shader */ 5073 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5074 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5075 } 5076 5077 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5078 { 5079 struct amdgpu_device *adev = ip_block->adev; 5080 uint32_t i, j, k, reg, index = 0; 5081 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5082 5083 if (!adev->gfx.ip_dump_core) 5084 return; 5085 5086 for (i = 0; i < reg_count; i++) 5087 drm_printf(p, "%-50s \t 0x%08x\n", 5088 gc_reg_list_12_0[i].reg_name, 5089 adev->gfx.ip_dump_core[i]); 5090 5091 /* print compute queue registers for all instances */ 5092 if (!adev->gfx.ip_dump_compute_queues) 5093 return; 5094 5095 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5096 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5097 adev->gfx.mec.num_mec, 5098 adev->gfx.mec.num_pipe_per_mec, 5099 adev->gfx.mec.num_queue_per_pipe); 5100 5101 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5102 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5103 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5104 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5105 for (reg = 0; reg < reg_count; reg++) { 5106 drm_printf(p, "%-50s \t 0x%08x\n", 5107 gc_cp_reg_list_12[reg].reg_name, 5108 adev->gfx.ip_dump_compute_queues[index + reg]); 5109 } 5110 index += reg_count; 5111 } 5112 } 5113 } 5114 5115 /* print gfx queue registers for all instances */ 5116 if (!adev->gfx.ip_dump_gfx_queues) 5117 return; 5118 5119 index = 0; 5120 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5121 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5122 adev->gfx.me.num_me, 5123 adev->gfx.me.num_pipe_per_me, 5124 adev->gfx.me.num_queue_per_pipe); 5125 5126 for (i = 0; i < adev->gfx.me.num_me; i++) { 5127 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5128 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5129 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5130 for (reg = 0; reg < reg_count; reg++) { 5131 drm_printf(p, "%-50s \t 0x%08x\n", 5132 gc_gfx_queue_reg_list_12[reg].reg_name, 5133 adev->gfx.ip_dump_gfx_queues[index + reg]); 5134 } 5135 index += reg_count; 5136 } 5137 } 5138 } 5139 } 5140 5141 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5142 { 5143 struct amdgpu_device *adev = ip_block->adev; 5144 uint32_t i, j, k, reg, index = 0; 5145 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5146 5147 if (!adev->gfx.ip_dump_core) 5148 return; 5149 5150 amdgpu_gfx_off_ctrl(adev, false); 5151 for (i = 0; i < reg_count; i++) 5152 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5153 amdgpu_gfx_off_ctrl(adev, true); 5154 5155 /* dump compute queue registers for all instances */ 5156 if (!adev->gfx.ip_dump_compute_queues) 5157 return; 5158 5159 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5160 amdgpu_gfx_off_ctrl(adev, false); 5161 mutex_lock(&adev->srbm_mutex); 5162 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5163 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5164 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5165 /* ME0 is for GFX so start from 1 for CP */ 5166 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5167 for (reg = 0; reg < reg_count; reg++) { 5168 adev->gfx.ip_dump_compute_queues[index + reg] = 5169 RREG32(SOC15_REG_ENTRY_OFFSET( 5170 gc_cp_reg_list_12[reg])); 5171 } 5172 index += reg_count; 5173 } 5174 } 5175 } 5176 soc24_grbm_select(adev, 0, 0, 0, 0); 5177 mutex_unlock(&adev->srbm_mutex); 5178 amdgpu_gfx_off_ctrl(adev, true); 5179 5180 /* dump gfx queue registers for all instances */ 5181 if (!adev->gfx.ip_dump_gfx_queues) 5182 return; 5183 5184 index = 0; 5185 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5186 amdgpu_gfx_off_ctrl(adev, false); 5187 mutex_lock(&adev->srbm_mutex); 5188 for (i = 0; i < adev->gfx.me.num_me; i++) { 5189 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5190 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5191 soc24_grbm_select(adev, i, j, k, 0); 5192 5193 for (reg = 0; reg < reg_count; reg++) { 5194 adev->gfx.ip_dump_gfx_queues[index + reg] = 5195 RREG32(SOC15_REG_ENTRY_OFFSET( 5196 gc_gfx_queue_reg_list_12[reg])); 5197 } 5198 index += reg_count; 5199 } 5200 } 5201 } 5202 soc24_grbm_select(adev, 0, 0, 0, 0); 5203 mutex_unlock(&adev->srbm_mutex); 5204 amdgpu_gfx_off_ctrl(adev, true); 5205 } 5206 5207 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5208 { 5209 struct amdgpu_device *adev = ring->adev; 5210 int r; 5211 5212 if (amdgpu_sriov_vf(adev)) 5213 return -EINVAL; 5214 5215 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5216 if (r) { 5217 dev_err(adev->dev, "reset via MES failed %d\n", r); 5218 return r; 5219 } 5220 5221 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5222 if (unlikely(r != 0)) { 5223 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5224 return r; 5225 } 5226 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5227 if (!r) { 5228 r = gfx_v12_0_kgq_init_queue(ring, true); 5229 amdgpu_bo_kunmap(ring->mqd_obj); 5230 ring->mqd_ptr = NULL; 5231 } 5232 amdgpu_bo_unreserve(ring->mqd_obj); 5233 if (r) { 5234 DRM_ERROR("fail to unresv mqd_obj\n"); 5235 return r; 5236 } 5237 5238 r = amdgpu_mes_map_legacy_queue(adev, ring); 5239 if (r) { 5240 dev_err(adev->dev, "failed to remap kgq\n"); 5241 return r; 5242 } 5243 5244 return amdgpu_ring_test_ring(ring); 5245 } 5246 5247 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5248 { 5249 struct amdgpu_device *adev = ring->adev; 5250 int r; 5251 5252 if (amdgpu_sriov_vf(adev)) 5253 return -EINVAL; 5254 5255 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5256 if (r) { 5257 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5258 return r; 5259 } 5260 5261 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5262 if (unlikely(r != 0)) { 5263 DRM_ERROR("fail to resv mqd_obj\n"); 5264 return r; 5265 } 5266 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5267 if (!r) { 5268 r = gfx_v12_0_kcq_init_queue(ring, true); 5269 amdgpu_bo_kunmap(ring->mqd_obj); 5270 ring->mqd_ptr = NULL; 5271 } 5272 amdgpu_bo_unreserve(ring->mqd_obj); 5273 if (r) { 5274 DRM_ERROR("fail to unresv mqd_obj\n"); 5275 return r; 5276 } 5277 r = amdgpu_mes_map_legacy_queue(adev, ring); 5278 if (r) { 5279 dev_err(adev->dev, "failed to remap kcq\n"); 5280 return r; 5281 } 5282 5283 return amdgpu_ring_test_ring(ring); 5284 } 5285 5286 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5287 .name = "gfx_v12_0", 5288 .early_init = gfx_v12_0_early_init, 5289 .late_init = gfx_v12_0_late_init, 5290 .sw_init = gfx_v12_0_sw_init, 5291 .sw_fini = gfx_v12_0_sw_fini, 5292 .hw_init = gfx_v12_0_hw_init, 5293 .hw_fini = gfx_v12_0_hw_fini, 5294 .suspend = gfx_v12_0_suspend, 5295 .resume = gfx_v12_0_resume, 5296 .is_idle = gfx_v12_0_is_idle, 5297 .wait_for_idle = gfx_v12_0_wait_for_idle, 5298 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5299 .set_powergating_state = gfx_v12_0_set_powergating_state, 5300 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5301 .dump_ip_state = gfx_v12_ip_dump, 5302 .print_ip_state = gfx_v12_ip_print, 5303 }; 5304 5305 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5306 .type = AMDGPU_RING_TYPE_GFX, 5307 .align_mask = 0xff, 5308 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5309 .support_64bit_ptrs = true, 5310 .secure_submission_supported = true, 5311 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5312 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5313 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5314 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5315 5 + /* COND_EXEC */ 5316 7 + /* PIPELINE_SYNC */ 5317 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5318 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5319 2 + /* VM_FLUSH */ 5320 8 + /* FENCE for VM_FLUSH */ 5321 5 + /* COND_EXEC */ 5322 7 + /* HDP_flush */ 5323 4 + /* VGT_flush */ 5324 31 + /* DE_META */ 5325 3 + /* CNTX_CTRL */ 5326 5 + /* HDP_INVL */ 5327 8 + 8 + /* FENCE x2 */ 5328 8 + /* gfx_v12_0_emit_mem_sync */ 5329 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5330 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5331 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5332 .emit_fence = gfx_v12_0_ring_emit_fence, 5333 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5334 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5335 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5336 .test_ring = gfx_v12_0_ring_test_ring, 5337 .test_ib = gfx_v12_0_ring_test_ib, 5338 .insert_nop = gfx_v12_ring_insert_nop, 5339 .pad_ib = amdgpu_ring_generic_pad_ib, 5340 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5341 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5342 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5343 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5344 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5345 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5346 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5347 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5348 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5349 .reset = gfx_v12_0_reset_kgq, 5350 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5351 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5352 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5353 }; 5354 5355 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5356 .type = AMDGPU_RING_TYPE_COMPUTE, 5357 .align_mask = 0xff, 5358 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5359 .support_64bit_ptrs = true, 5360 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5361 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5362 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5363 .emit_frame_size = 5364 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5365 5 + /* hdp invalidate */ 5366 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5367 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5368 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5369 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5370 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5371 8 + /* gfx_v12_0_emit_mem_sync */ 5372 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5373 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5374 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5375 .emit_fence = gfx_v12_0_ring_emit_fence, 5376 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5377 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5378 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5379 .test_ring = gfx_v12_0_ring_test_ring, 5380 .test_ib = gfx_v12_0_ring_test_ib, 5381 .insert_nop = gfx_v12_ring_insert_nop, 5382 .pad_ib = amdgpu_ring_generic_pad_ib, 5383 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5384 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5385 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5386 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5387 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5388 .reset = gfx_v12_0_reset_kcq, 5389 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5390 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5391 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5392 }; 5393 5394 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5395 .type = AMDGPU_RING_TYPE_KIQ, 5396 .align_mask = 0xff, 5397 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5398 .support_64bit_ptrs = true, 5399 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5400 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5401 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5402 .emit_frame_size = 5403 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5404 5 + /*hdp invalidate */ 5405 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5406 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5407 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5408 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5409 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5410 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5411 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5412 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5413 .test_ring = gfx_v12_0_ring_test_ring, 5414 .test_ib = gfx_v12_0_ring_test_ib, 5415 .insert_nop = amdgpu_ring_insert_nop, 5416 .pad_ib = amdgpu_ring_generic_pad_ib, 5417 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5418 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5419 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5420 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5421 }; 5422 5423 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5424 { 5425 int i; 5426 5427 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5428 5429 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5430 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5431 5432 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5433 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5434 } 5435 5436 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5437 .set = gfx_v12_0_set_eop_interrupt_state, 5438 .process = gfx_v12_0_eop_irq, 5439 }; 5440 5441 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5442 .set = gfx_v12_0_set_priv_reg_fault_state, 5443 .process = gfx_v12_0_priv_reg_irq, 5444 }; 5445 5446 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5447 .set = gfx_v12_0_set_bad_op_fault_state, 5448 .process = gfx_v12_0_bad_op_irq, 5449 }; 5450 5451 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5452 .set = gfx_v12_0_set_priv_inst_fault_state, 5453 .process = gfx_v12_0_priv_inst_irq, 5454 }; 5455 5456 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5457 { 5458 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5459 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5460 5461 adev->gfx.priv_reg_irq.num_types = 1; 5462 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5463 5464 adev->gfx.bad_op_irq.num_types = 1; 5465 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5466 5467 adev->gfx.priv_inst_irq.num_types = 1; 5468 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5469 } 5470 5471 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5472 { 5473 if (adev->flags & AMD_IS_APU) 5474 adev->gfx.imu.mode = MISSION_MODE; 5475 else 5476 adev->gfx.imu.mode = DEBUG_MODE; 5477 5478 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5479 } 5480 5481 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5482 { 5483 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5484 } 5485 5486 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5487 { 5488 /* set gfx eng mqd */ 5489 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5490 sizeof(struct v12_gfx_mqd); 5491 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5492 gfx_v12_0_gfx_mqd_init; 5493 /* set compute eng mqd */ 5494 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5495 sizeof(struct v12_compute_mqd); 5496 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5497 gfx_v12_0_compute_mqd_init; 5498 } 5499 5500 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5501 u32 bitmap) 5502 { 5503 u32 data; 5504 5505 if (!bitmap) 5506 return; 5507 5508 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5509 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5510 5511 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5512 } 5513 5514 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5515 { 5516 u32 data, wgp_bitmask; 5517 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5518 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5519 5520 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5521 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5522 5523 wgp_bitmask = 5524 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5525 5526 return (~data) & wgp_bitmask; 5527 } 5528 5529 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5530 { 5531 u32 wgp_idx, wgp_active_bitmap; 5532 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5533 5534 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5535 cu_active_bitmap = 0; 5536 5537 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5538 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5539 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5540 if (wgp_active_bitmap & (1 << wgp_idx)) 5541 cu_active_bitmap |= cu_bitmap_per_wgp; 5542 } 5543 5544 return cu_active_bitmap; 5545 } 5546 5547 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5548 struct amdgpu_cu_info *cu_info) 5549 { 5550 int i, j, k, counter, active_cu_number = 0; 5551 u32 mask, bitmap; 5552 unsigned disable_masks[8 * 2]; 5553 5554 if (!adev || !cu_info) 5555 return -EINVAL; 5556 5557 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5558 5559 mutex_lock(&adev->grbm_idx_mutex); 5560 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5561 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5562 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5563 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5564 continue; 5565 mask = 1; 5566 counter = 0; 5567 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5568 if (i < 8 && j < 2) 5569 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5570 adev, disable_masks[i * 2 + j]); 5571 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5572 5573 /** 5574 * GFX12 could support more than 4 SEs, while the bitmap 5575 * in cu_info struct is 4x4 and ioctl interface struct 5576 * drm_amdgpu_info_device should keep stable. 5577 * So we use last two columns of bitmap to store cu mask for 5578 * SEs 4 to 7, the layout of the bitmap is as below: 5579 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5580 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5581 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5582 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5583 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5584 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5585 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5586 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5587 */ 5588 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5589 5590 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5591 if (bitmap & mask) 5592 counter++; 5593 5594 mask <<= 1; 5595 } 5596 active_cu_number += counter; 5597 } 5598 } 5599 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5600 mutex_unlock(&adev->grbm_idx_mutex); 5601 5602 cu_info->number = active_cu_number; 5603 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5604 5605 return 0; 5606 } 5607 5608 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5609 .type = AMD_IP_BLOCK_TYPE_GFX, 5610 .major = 12, 5611 .minor = 0, 5612 .rev = 0, 5613 .funcs = &gfx_v12_0_ip_funcs, 5614 }; 5615