1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 48 #define GFX12_NUM_GFX_RINGS 1 49 #define GFX12_MEC_HPD_SIZE 2048 50 51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 52 53 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 54 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 55 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 56 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 57 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 58 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 59 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 60 61 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 62 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 63 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 64 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 65 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 66 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 67 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 68 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 69 70 71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 81 82 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 83 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 84 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 114 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 118 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 121 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 124 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 136 137 /* cp header registers */ 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 /* SE status registers */ 143 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 144 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 145 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 146 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 147 }; 148 149 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 150 /* compute registers */ 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 190 }; 191 192 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 193 /* gfx queue registers */ 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 219 }; 220 221 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 222 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 225 }; 226 227 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 228 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 229 }; 230 231 #define DEFAULT_SH_MEM_CONFIG \ 232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 234 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 235 236 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 237 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 238 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 239 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 240 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 241 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 242 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 243 struct amdgpu_cu_info *cu_info); 244 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 245 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 246 u32 sh_num, u32 instance, int xcc_id); 247 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 248 249 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 250 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 251 uint32_t val); 252 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 253 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 254 uint16_t pasid, uint32_t flush_type, 255 bool all_hub, uint8_t dst_sel); 256 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 257 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 258 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 259 bool enable); 260 261 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 262 uint64_t queue_mask) 263 { 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 265 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 266 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 267 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 268 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 269 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 270 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 271 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 272 amdgpu_ring_write(kiq_ring, 0); 273 } 274 275 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 276 struct amdgpu_ring *ring) 277 { 278 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 279 uint64_t wptr_addr = ring->wptr_gpu_addr; 280 uint32_t me = 0, eng_sel = 0; 281 282 switch (ring->funcs->type) { 283 case AMDGPU_RING_TYPE_COMPUTE: 284 me = 1; 285 eng_sel = 0; 286 break; 287 case AMDGPU_RING_TYPE_GFX: 288 me = 0; 289 eng_sel = 4; 290 break; 291 case AMDGPU_RING_TYPE_MES: 292 me = 2; 293 eng_sel = 5; 294 break; 295 default: 296 WARN_ON(1); 297 } 298 299 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 300 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 301 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 302 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 303 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 304 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 305 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 306 PACKET3_MAP_QUEUES_ME((me)) | 307 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 308 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 309 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 310 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 311 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 312 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 313 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 314 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 315 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 316 } 317 318 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 319 struct amdgpu_ring *ring, 320 enum amdgpu_unmap_queues_action action, 321 u64 gpu_addr, u64 seq) 322 { 323 struct amdgpu_device *adev = kiq_ring->adev; 324 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 325 326 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 327 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 328 return; 329 } 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_UNMAP_QUEUES_ACTION(action) | 334 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 335 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 336 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 337 amdgpu_ring_write(kiq_ring, 338 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 339 340 if (action == PREEMPT_QUEUES_NO_UNMAP) { 341 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 343 amdgpu_ring_write(kiq_ring, seq); 344 } else { 345 amdgpu_ring_write(kiq_ring, 0); 346 amdgpu_ring_write(kiq_ring, 0); 347 amdgpu_ring_write(kiq_ring, 0); 348 } 349 } 350 351 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 352 struct amdgpu_ring *ring, 353 u64 addr, u64 seq) 354 { 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 358 amdgpu_ring_write(kiq_ring, 359 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 360 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 361 PACKET3_QUERY_STATUS_COMMAND(2)); 362 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 363 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 364 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 365 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 366 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 367 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 368 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 369 } 370 371 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 372 uint16_t pasid, 373 uint32_t flush_type, 374 bool all_hub) 375 { 376 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 377 } 378 379 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 380 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 381 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 382 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 383 .kiq_query_status = gfx_v12_0_kiq_query_status, 384 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 385 .set_resources_size = 8, 386 .map_queues_size = 7, 387 .unmap_queues_size = 6, 388 .query_status_size = 7, 389 .invalidate_tlbs_size = 2, 390 }; 391 392 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 393 { 394 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 395 } 396 397 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 398 int mem_space, int opt, uint32_t addr0, 399 uint32_t addr1, uint32_t ref, 400 uint32_t mask, uint32_t inv) 401 { 402 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 403 amdgpu_ring_write(ring, 404 /* memory (1) or register (0) */ 405 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 406 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 407 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 408 WAIT_REG_MEM_ENGINE(eng_sel))); 409 410 if (mem_space) 411 BUG_ON(addr0 & 0x3); /* Dword align */ 412 amdgpu_ring_write(ring, addr0); 413 amdgpu_ring_write(ring, addr1); 414 amdgpu_ring_write(ring, ref); 415 amdgpu_ring_write(ring, mask); 416 amdgpu_ring_write(ring, inv); /* poll interval */ 417 } 418 419 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 420 { 421 struct amdgpu_device *adev = ring->adev; 422 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 423 uint32_t tmp = 0; 424 unsigned i; 425 int r; 426 427 WREG32(scratch, 0xCAFEDEAD); 428 r = amdgpu_ring_alloc(ring, 5); 429 if (r) { 430 dev_err(adev->dev, 431 "amdgpu: cp failed to lock ring %d (%d).\n", 432 ring->idx, r); 433 return r; 434 } 435 436 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 437 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 438 } else { 439 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 440 amdgpu_ring_write(ring, scratch - 441 PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 } 444 amdgpu_ring_commit(ring); 445 446 for (i = 0; i < adev->usec_timeout; i++) { 447 tmp = RREG32(scratch); 448 if (tmp == 0xDEADBEEF) 449 break; 450 if (amdgpu_emu_mode == 1) 451 msleep(1); 452 else 453 udelay(1); 454 } 455 456 if (i >= adev->usec_timeout) 457 r = -ETIMEDOUT; 458 return r; 459 } 460 461 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 462 { 463 struct amdgpu_device *adev = ring->adev; 464 struct amdgpu_ib ib; 465 struct dma_fence *f = NULL; 466 unsigned index; 467 uint64_t gpu_addr; 468 volatile uint32_t *cpu_ptr; 469 long r; 470 471 /* MES KIQ fw hasn't indirect buffer support for now */ 472 if (adev->enable_mes_kiq && 473 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 474 return 0; 475 476 memset(&ib, 0, sizeof(ib)); 477 478 if (ring->is_mes_queue) { 479 uint32_t padding, offset; 480 481 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 482 padding = amdgpu_mes_ctx_get_offs(ring, 483 AMDGPU_MES_CTX_PADDING_OFFS); 484 485 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 486 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 487 488 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 489 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 490 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 491 } else { 492 r = amdgpu_device_wb_get(adev, &index); 493 if (r) 494 return r; 495 496 gpu_addr = adev->wb.gpu_addr + (index * 4); 497 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 498 cpu_ptr = &adev->wb.wb[index]; 499 500 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 501 if (r) { 502 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 503 goto err1; 504 } 505 } 506 507 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 508 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 509 ib.ptr[2] = lower_32_bits(gpu_addr); 510 ib.ptr[3] = upper_32_bits(gpu_addr); 511 ib.ptr[4] = 0xDEADBEEF; 512 ib.length_dw = 5; 513 514 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 515 if (r) 516 goto err2; 517 518 r = dma_fence_wait_timeout(f, false, timeout); 519 if (r == 0) { 520 r = -ETIMEDOUT; 521 goto err2; 522 } else if (r < 0) { 523 goto err2; 524 } 525 526 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 527 r = 0; 528 else 529 r = -EINVAL; 530 err2: 531 if (!ring->is_mes_queue) 532 amdgpu_ib_free(&ib, NULL); 533 dma_fence_put(f); 534 err1: 535 if (!ring->is_mes_queue) 536 amdgpu_device_wb_free(adev, index); 537 return r; 538 } 539 540 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 541 { 542 amdgpu_ucode_release(&adev->gfx.pfp_fw); 543 amdgpu_ucode_release(&adev->gfx.me_fw); 544 amdgpu_ucode_release(&adev->gfx.rlc_fw); 545 amdgpu_ucode_release(&adev->gfx.mec_fw); 546 547 kfree(adev->gfx.rlc.register_list_format); 548 } 549 550 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 551 { 552 const struct psp_firmware_header_v1_0 *toc_hdr; 553 int err = 0; 554 555 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 556 AMDGPU_UCODE_REQUIRED, 557 "amdgpu/%s_toc.bin", ucode_prefix); 558 if (err) 559 goto out; 560 561 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 562 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 563 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 564 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 565 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 566 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 567 return 0; 568 out: 569 amdgpu_ucode_release(&adev->psp.toc_fw); 570 return err; 571 } 572 573 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 574 { 575 char ucode_prefix[15]; 576 int err; 577 const struct rlc_firmware_header_v2_0 *rlc_hdr; 578 uint16_t version_major; 579 uint16_t version_minor; 580 581 DRM_DEBUG("\n"); 582 583 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 584 585 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 586 AMDGPU_UCODE_REQUIRED, 587 "amdgpu/%s_pfp.bin", ucode_prefix); 588 if (err) 589 goto out; 590 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 591 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 592 593 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 594 AMDGPU_UCODE_REQUIRED, 595 "amdgpu/%s_me.bin", ucode_prefix); 596 if (err) 597 goto out; 598 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 599 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 600 601 if (!amdgpu_sriov_vf(adev)) { 602 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 603 AMDGPU_UCODE_REQUIRED, 604 "amdgpu/%s_rlc.bin", ucode_prefix); 605 if (err) 606 goto out; 607 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 608 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 609 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 610 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 611 if (err) 612 goto out; 613 } 614 615 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 616 AMDGPU_UCODE_REQUIRED, 617 "amdgpu/%s_mec.bin", ucode_prefix); 618 if (err) 619 goto out; 620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 622 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 623 624 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 625 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 626 627 /* only one MEC for gfx 12 */ 628 adev->gfx.mec2_fw = NULL; 629 630 if (adev->gfx.imu.funcs) { 631 if (adev->gfx.imu.funcs->init_microcode) { 632 err = adev->gfx.imu.funcs->init_microcode(adev); 633 if (err) 634 dev_err(adev->dev, "Failed to load imu firmware!\n"); 635 } 636 } 637 638 out: 639 if (err) { 640 amdgpu_ucode_release(&adev->gfx.pfp_fw); 641 amdgpu_ucode_release(&adev->gfx.me_fw); 642 amdgpu_ucode_release(&adev->gfx.rlc_fw); 643 amdgpu_ucode_release(&adev->gfx.mec_fw); 644 } 645 646 return err; 647 } 648 649 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 650 { 651 u32 count = 0; 652 const struct cs_section_def *sect = NULL; 653 const struct cs_extent_def *ext = NULL; 654 655 count += 1; 656 657 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 658 if (sect->id == SECT_CONTEXT) { 659 for (ext = sect->section; ext->extent != NULL; ++ext) 660 count += 2 + ext->reg_count; 661 } else 662 return 0; 663 } 664 665 return count; 666 } 667 668 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 669 volatile u32 *buffer) 670 { 671 u32 count = 0, clustercount = 0, i; 672 const struct cs_section_def *sect = NULL; 673 const struct cs_extent_def *ext = NULL; 674 675 if (adev->gfx.rlc.cs_data == NULL) 676 return; 677 if (buffer == NULL) 678 return; 679 680 count += 1; 681 682 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 683 if (sect->id == SECT_CONTEXT) { 684 for (ext = sect->section; ext->extent != NULL; ++ext) { 685 clustercount++; 686 buffer[count++] = ext->reg_count; 687 buffer[count++] = ext->reg_index; 688 689 for (i = 0; i < ext->reg_count; i++) 690 buffer[count++] = cpu_to_le32(ext->extent[i]); 691 } 692 } else 693 return; 694 } 695 696 buffer[0] = clustercount; 697 } 698 699 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 700 { 701 /* clear state block */ 702 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 703 &adev->gfx.rlc.clear_state_gpu_addr, 704 (void **)&adev->gfx.rlc.cs_ptr); 705 706 /* jump table block */ 707 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 708 &adev->gfx.rlc.cp_table_gpu_addr, 709 (void **)&adev->gfx.rlc.cp_table_ptr); 710 } 711 712 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 713 { 714 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 715 716 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 717 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 718 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 719 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 720 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 721 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 722 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 723 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 724 adev->gfx.rlc.rlcg_reg_access_supported = true; 725 } 726 727 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 728 { 729 const struct cs_section_def *cs_data; 730 int r; 731 732 adev->gfx.rlc.cs_data = gfx12_cs_data; 733 734 cs_data = adev->gfx.rlc.cs_data; 735 736 if (cs_data) { 737 /* init clear state block */ 738 r = amdgpu_gfx_rlc_init_csb(adev); 739 if (r) 740 return r; 741 } 742 743 /* init spm vmid with 0xf */ 744 if (adev->gfx.rlc.funcs->update_spm_vmid) 745 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 746 747 return 0; 748 } 749 750 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 751 { 752 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 753 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 754 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 755 } 756 757 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 758 { 759 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 760 761 amdgpu_gfx_graphics_queue_acquire(adev); 762 } 763 764 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 765 { 766 int r; 767 u32 *hpd; 768 size_t mec_hpd_size; 769 770 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 771 772 /* take ownership of the relevant compute queues */ 773 amdgpu_gfx_compute_queue_acquire(adev); 774 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 775 776 if (mec_hpd_size) { 777 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 778 AMDGPU_GEM_DOMAIN_GTT, 779 &adev->gfx.mec.hpd_eop_obj, 780 &adev->gfx.mec.hpd_eop_gpu_addr, 781 (void **)&hpd); 782 if (r) { 783 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 784 gfx_v12_0_mec_fini(adev); 785 return r; 786 } 787 788 memset(hpd, 0, mec_hpd_size); 789 790 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 791 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 792 } 793 794 return 0; 795 } 796 797 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 798 { 799 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 800 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 801 (address << SQ_IND_INDEX__INDEX__SHIFT)); 802 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 803 } 804 805 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 806 uint32_t thread, uint32_t regno, 807 uint32_t num, uint32_t *out) 808 { 809 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 810 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 811 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 812 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 813 (SQ_IND_INDEX__AUTO_INCR_MASK)); 814 while (num--) 815 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 816 } 817 818 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 819 uint32_t xcc_id, 820 uint32_t simd, uint32_t wave, 821 uint32_t *dst, int *no_fields) 822 { 823 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 824 * field when performing a select_se_sh so it should be 825 * zero here */ 826 WARN_ON(simd != 0); 827 828 /* type 4 wave data */ 829 dst[(*no_fields)++] = 4; 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 837 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 838 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 839 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 840 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 841 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 842 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 843 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 853 } 854 855 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 856 uint32_t xcc_id, uint32_t simd, 857 uint32_t wave, uint32_t start, 858 uint32_t size, uint32_t *dst) 859 { 860 WARN_ON(simd != 0); 861 862 wave_read_regs( 863 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 864 dst); 865 } 866 867 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 868 uint32_t xcc_id, uint32_t simd, 869 uint32_t wave, uint32_t thread, 870 uint32_t start, uint32_t size, 871 uint32_t *dst) 872 { 873 wave_read_regs( 874 adev, wave, thread, 875 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 876 } 877 878 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 879 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 880 { 881 soc24_grbm_select(adev, me, pipe, q, vm); 882 } 883 884 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 885 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 886 .select_se_sh = &gfx_v12_0_select_se_sh, 887 .read_wave_data = &gfx_v12_0_read_wave_data, 888 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 889 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 890 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 891 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 892 }; 893 894 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 895 { 896 897 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 898 case IP_VERSION(12, 0, 0): 899 case IP_VERSION(12, 0, 1): 900 adev->gfx.config.max_hw_contexts = 8; 901 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 902 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 903 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 904 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 905 break; 906 default: 907 BUG(); 908 break; 909 } 910 911 return 0; 912 } 913 914 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 915 int me, int pipe, int queue) 916 { 917 int r; 918 struct amdgpu_ring *ring; 919 unsigned int irq_type; 920 921 ring = &adev->gfx.gfx_ring[ring_id]; 922 923 ring->me = me; 924 ring->pipe = pipe; 925 ring->queue = queue; 926 927 ring->ring_obj = NULL; 928 ring->use_doorbell = true; 929 930 if (!ring_id) 931 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 932 else 933 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 934 ring->vm_hub = AMDGPU_GFXHUB(0); 935 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 936 937 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 938 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 939 AMDGPU_RING_PRIO_DEFAULT, NULL); 940 if (r) 941 return r; 942 return 0; 943 } 944 945 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 946 int mec, int pipe, int queue) 947 { 948 int r; 949 unsigned irq_type; 950 struct amdgpu_ring *ring; 951 unsigned int hw_prio; 952 953 ring = &adev->gfx.compute_ring[ring_id]; 954 955 /* mec0 is me1 */ 956 ring->me = mec + 1; 957 ring->pipe = pipe; 958 ring->queue = queue; 959 960 ring->ring_obj = NULL; 961 ring->use_doorbell = true; 962 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 963 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 964 + (ring_id * GFX12_MEC_HPD_SIZE); 965 ring->vm_hub = AMDGPU_GFXHUB(0); 966 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 967 968 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 969 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 970 + ring->pipe; 971 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 972 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 973 /* type-2 packets are deprecated on MEC, use type-3 instead */ 974 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 975 hw_prio, NULL); 976 if (r) 977 return r; 978 979 return 0; 980 } 981 982 static struct { 983 SOC24_FIRMWARE_ID id; 984 unsigned int offset; 985 unsigned int size; 986 unsigned int size_x16; 987 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 988 989 #define RLC_TOC_OFFSET_DWUNIT 8 990 #define RLC_SIZE_MULTIPLE 1024 991 #define RLC_TOC_UMF_SIZE_inM 23ULL 992 #define RLC_TOC_FORMAT_API 165ULL 993 994 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 995 { 996 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 997 998 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 999 rlc_autoload_info[ucode->id].id = ucode->id; 1000 rlc_autoload_info[ucode->id].offset = 1001 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1002 rlc_autoload_info[ucode->id].size = 1003 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1004 ucode->size * 4; 1005 ucode++; 1006 } 1007 } 1008 1009 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1010 { 1011 uint32_t total_size = 0; 1012 SOC24_FIRMWARE_ID id; 1013 1014 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1015 1016 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1017 total_size += rlc_autoload_info[id].size; 1018 1019 /* In case the offset in rlc toc ucode is aligned */ 1020 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1021 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1022 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1023 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1024 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1025 1026 return total_size; 1027 } 1028 1029 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1030 { 1031 int r; 1032 uint32_t total_size; 1033 1034 total_size = gfx_v12_0_calc_toc_total_size(adev); 1035 1036 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1037 AMDGPU_GEM_DOMAIN_VRAM, 1038 &adev->gfx.rlc.rlc_autoload_bo, 1039 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1040 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1041 1042 if (r) { 1043 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1044 return r; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1051 SOC24_FIRMWARE_ID id, 1052 const void *fw_data, 1053 uint32_t fw_size) 1054 { 1055 uint32_t toc_offset; 1056 uint32_t toc_fw_size; 1057 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1058 1059 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1060 return; 1061 1062 toc_offset = rlc_autoload_info[id].offset; 1063 toc_fw_size = rlc_autoload_info[id].size; 1064 1065 if (fw_size == 0) 1066 fw_size = toc_fw_size; 1067 1068 if (fw_size > toc_fw_size) 1069 fw_size = toc_fw_size; 1070 1071 memcpy(ptr + toc_offset, fw_data, fw_size); 1072 1073 if (fw_size < toc_fw_size) 1074 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1075 } 1076 1077 static void 1078 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1079 { 1080 void *data; 1081 uint32_t size; 1082 uint32_t *toc_ptr; 1083 1084 data = adev->psp.toc.start_addr; 1085 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1086 1087 toc_ptr = (uint32_t *)data + size / 4 - 2; 1088 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1089 1090 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1091 data, size); 1092 } 1093 1094 static void 1095 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1096 { 1097 const __le32 *fw_data; 1098 uint32_t fw_size; 1099 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1100 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1101 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1102 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1103 uint16_t version_major, version_minor; 1104 1105 /* pfp ucode */ 1106 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1107 adev->gfx.pfp_fw->data; 1108 /* instruction */ 1109 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1110 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1111 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1112 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1113 fw_data, fw_size); 1114 /* data */ 1115 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1116 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1117 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1118 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1119 fw_data, fw_size); 1120 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1121 fw_data, fw_size); 1122 /* me ucode */ 1123 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1124 adev->gfx.me_fw->data; 1125 /* instruction */ 1126 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1127 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1128 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1129 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1130 fw_data, fw_size); 1131 /* data */ 1132 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1133 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1134 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1135 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1136 fw_data, fw_size); 1137 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1138 fw_data, fw_size); 1139 /* mec ucode */ 1140 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1141 adev->gfx.mec_fw->data; 1142 /* instruction */ 1143 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1144 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1145 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1146 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1147 fw_data, fw_size); 1148 /* data */ 1149 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1150 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1151 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1152 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1153 fw_data, fw_size); 1154 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1155 fw_data, fw_size); 1156 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1157 fw_data, fw_size); 1158 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1159 fw_data, fw_size); 1160 1161 /* rlc ucode */ 1162 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1163 adev->gfx.rlc_fw->data; 1164 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1165 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1166 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1168 fw_data, fw_size); 1169 1170 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1171 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1172 if (version_major == 2) { 1173 if (version_minor >= 1) { 1174 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1175 1176 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1177 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1178 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1179 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1180 fw_data, fw_size); 1181 1182 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1183 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1184 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1186 fw_data, fw_size); 1187 } 1188 if (version_minor >= 2) { 1189 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1190 1191 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1192 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1193 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1194 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1195 fw_data, fw_size); 1196 1197 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1198 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1199 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1200 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1201 fw_data, fw_size); 1202 } 1203 } 1204 } 1205 1206 static void 1207 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1208 { 1209 const __le32 *fw_data; 1210 uint32_t fw_size; 1211 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1212 1213 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1214 adev->sdma.instance[0].fw->data; 1215 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1216 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1217 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1218 1219 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1220 fw_data, fw_size); 1221 } 1222 1223 static void 1224 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1225 { 1226 const __le32 *fw_data; 1227 unsigned fw_size; 1228 const struct mes_firmware_header_v1_0 *mes_hdr; 1229 int pipe, ucode_id, data_id; 1230 1231 for (pipe = 0; pipe < 2; pipe++) { 1232 if (pipe == 0) { 1233 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1234 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1235 } else { 1236 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1237 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1238 } 1239 1240 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1241 adev->mes.fw[pipe]->data; 1242 1243 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1244 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1245 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1246 1247 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1248 1249 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1250 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1251 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1252 1253 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1254 } 1255 } 1256 1257 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1258 { 1259 uint32_t rlc_g_offset, rlc_g_size; 1260 uint64_t gpu_addr; 1261 uint32_t data; 1262 1263 /* RLC autoload sequence 2: copy ucode */ 1264 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1265 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1266 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1267 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1268 1269 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1270 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1271 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1272 1273 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1275 1276 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1277 1278 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1279 /* RLC autoload sequence 3: load IMU fw */ 1280 if (adev->gfx.imu.funcs->load_microcode) 1281 adev->gfx.imu.funcs->load_microcode(adev); 1282 /* RLC autoload sequence 4 init IMU fw */ 1283 if (adev->gfx.imu.funcs->setup_imu) 1284 adev->gfx.imu.funcs->setup_imu(adev); 1285 if (adev->gfx.imu.funcs->start_imu) 1286 adev->gfx.imu.funcs->start_imu(adev); 1287 1288 /* RLC autoload sequence 5 disable gpa mode */ 1289 gfx_v12_0_disable_gpa_mode(adev); 1290 } else { 1291 /* unhalt rlc to start autoload without imu */ 1292 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1293 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1294 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1295 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1296 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1303 { 1304 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1305 uint32_t *ptr; 1306 uint32_t inst; 1307 1308 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1309 if (!ptr) { 1310 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1311 adev->gfx.ip_dump_core = NULL; 1312 } else { 1313 adev->gfx.ip_dump_core = ptr; 1314 } 1315 1316 /* Allocate memory for compute queue registers for all the instances */ 1317 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1318 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1319 adev->gfx.mec.num_queue_per_pipe; 1320 1321 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1322 if (!ptr) { 1323 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1324 adev->gfx.ip_dump_compute_queues = NULL; 1325 } else { 1326 adev->gfx.ip_dump_compute_queues = ptr; 1327 } 1328 1329 /* Allocate memory for gfx queue registers for all the instances */ 1330 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1331 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1332 adev->gfx.me.num_queue_per_pipe; 1333 1334 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1335 if (!ptr) { 1336 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1337 adev->gfx.ip_dump_gfx_queues = NULL; 1338 } else { 1339 adev->gfx.ip_dump_gfx_queues = ptr; 1340 } 1341 } 1342 1343 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1344 { 1345 int i, j, k, r, ring_id = 0; 1346 unsigned num_compute_rings; 1347 int xcc_id = 0; 1348 struct amdgpu_device *adev = ip_block->adev; 1349 1350 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1351 1352 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1353 case IP_VERSION(12, 0, 0): 1354 case IP_VERSION(12, 0, 1): 1355 adev->gfx.me.num_me = 1; 1356 adev->gfx.me.num_pipe_per_me = 1; 1357 adev->gfx.me.num_queue_per_pipe = 1; 1358 adev->gfx.mec.num_mec = 2; 1359 adev->gfx.mec.num_pipe_per_mec = 2; 1360 adev->gfx.mec.num_queue_per_pipe = 4; 1361 break; 1362 default: 1363 adev->gfx.me.num_me = 1; 1364 adev->gfx.me.num_pipe_per_me = 1; 1365 adev->gfx.me.num_queue_per_pipe = 1; 1366 adev->gfx.mec.num_mec = 1; 1367 adev->gfx.mec.num_pipe_per_mec = 4; 1368 adev->gfx.mec.num_queue_per_pipe = 8; 1369 break; 1370 } 1371 1372 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1373 case IP_VERSION(12, 0, 0): 1374 case IP_VERSION(12, 0, 1): 1375 if (adev->gfx.me_fw_version >= 2480 && 1376 adev->gfx.pfp_fw_version >= 2530 && 1377 adev->gfx.mec_fw_version >= 2680 && 1378 adev->mes.fw_version[0] >= 100) 1379 adev->gfx.enable_cleaner_shader = true; 1380 break; 1381 default: 1382 adev->gfx.enable_cleaner_shader = false; 1383 break; 1384 } 1385 1386 /* recalculate compute rings to use based on hardware configuration */ 1387 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1388 adev->gfx.mec.num_queue_per_pipe) / 2; 1389 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1390 num_compute_rings); 1391 1392 /* EOP Event */ 1393 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1394 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1395 &adev->gfx.eop_irq); 1396 if (r) 1397 return r; 1398 1399 /* Bad opcode Event */ 1400 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1401 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1402 &adev->gfx.bad_op_irq); 1403 if (r) 1404 return r; 1405 1406 /* Privileged reg */ 1407 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1408 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1409 &adev->gfx.priv_reg_irq); 1410 if (r) 1411 return r; 1412 1413 /* Privileged inst */ 1414 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1415 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1416 &adev->gfx.priv_inst_irq); 1417 if (r) 1418 return r; 1419 1420 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1421 1422 gfx_v12_0_me_init(adev); 1423 1424 r = gfx_v12_0_rlc_init(adev); 1425 if (r) { 1426 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1427 return r; 1428 } 1429 1430 r = gfx_v12_0_mec_init(adev); 1431 if (r) { 1432 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1433 return r; 1434 } 1435 1436 /* set up the gfx ring */ 1437 for (i = 0; i < adev->gfx.me.num_me; i++) { 1438 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1439 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1440 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1441 continue; 1442 1443 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1444 i, k, j); 1445 if (r) 1446 return r; 1447 ring_id++; 1448 } 1449 } 1450 } 1451 1452 ring_id = 0; 1453 /* set up the compute queues - allocate horizontally across pipes */ 1454 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1455 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1456 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1457 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1458 0, i, k, j)) 1459 continue; 1460 1461 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1462 i, k, j); 1463 if (r) 1464 return r; 1465 1466 ring_id++; 1467 } 1468 } 1469 } 1470 1471 adev->gfx.gfx_supported_reset = 1472 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1473 adev->gfx.compute_supported_reset = 1474 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1475 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1476 case IP_VERSION(12, 0, 0): 1477 case IP_VERSION(12, 0, 1): 1478 if ((adev->gfx.me_fw_version >= 2660) && 1479 (adev->gfx.mec_fw_version >= 2920)) { 1480 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1481 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1482 } 1483 } 1484 1485 if (!adev->enable_mes_kiq) { 1486 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1487 if (r) { 1488 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1489 return r; 1490 } 1491 1492 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1493 if (r) 1494 return r; 1495 } 1496 1497 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1498 if (r) 1499 return r; 1500 1501 /* allocate visible FB for rlc auto-loading fw */ 1502 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1503 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1504 if (r) 1505 return r; 1506 } 1507 1508 r = gfx_v12_0_gpu_early_init(adev); 1509 if (r) 1510 return r; 1511 1512 gfx_v12_0_alloc_ip_dump(adev); 1513 1514 r = amdgpu_gfx_sysfs_init(adev); 1515 if (r) 1516 return r; 1517 1518 return 0; 1519 } 1520 1521 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1522 { 1523 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1524 &adev->gfx.pfp.pfp_fw_gpu_addr, 1525 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1526 1527 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1528 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1529 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1530 } 1531 1532 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1533 { 1534 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1535 &adev->gfx.me.me_fw_gpu_addr, 1536 (void **)&adev->gfx.me.me_fw_ptr); 1537 1538 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1539 &adev->gfx.me.me_fw_data_gpu_addr, 1540 (void **)&adev->gfx.me.me_fw_data_ptr); 1541 } 1542 1543 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1544 { 1545 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1546 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1547 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1548 } 1549 1550 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1551 { 1552 int i; 1553 struct amdgpu_device *adev = ip_block->adev; 1554 1555 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1556 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1557 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1558 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1559 1560 amdgpu_gfx_mqd_sw_fini(adev, 0); 1561 1562 if (!adev->enable_mes_kiq) { 1563 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1564 amdgpu_gfx_kiq_fini(adev, 0); 1565 } 1566 1567 gfx_v12_0_pfp_fini(adev); 1568 gfx_v12_0_me_fini(adev); 1569 gfx_v12_0_rlc_fini(adev); 1570 gfx_v12_0_mec_fini(adev); 1571 1572 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1573 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1574 1575 gfx_v12_0_free_microcode(adev); 1576 1577 amdgpu_gfx_sysfs_fini(adev); 1578 1579 kfree(adev->gfx.ip_dump_core); 1580 kfree(adev->gfx.ip_dump_compute_queues); 1581 kfree(adev->gfx.ip_dump_gfx_queues); 1582 1583 return 0; 1584 } 1585 1586 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1587 u32 sh_num, u32 instance, int xcc_id) 1588 { 1589 u32 data; 1590 1591 if (instance == 0xffffffff) 1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1593 INSTANCE_BROADCAST_WRITES, 1); 1594 else 1595 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1596 instance); 1597 1598 if (se_num == 0xffffffff) 1599 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1600 1); 1601 else 1602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1603 1604 if (sh_num == 0xffffffff) 1605 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1606 1); 1607 else 1608 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1609 1610 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1611 } 1612 1613 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1614 { 1615 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1616 1617 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1618 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1619 GRBM_CC_GC_SA_UNIT_DISABLE, 1620 SA_DISABLE); 1621 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1622 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1623 GRBM_GC_USER_SA_UNIT_DISABLE, 1624 SA_DISABLE); 1625 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1626 adev->gfx.config.max_shader_engines); 1627 1628 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1629 } 1630 1631 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1632 { 1633 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1634 u32 rb_mask; 1635 1636 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1637 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1638 CC_RB_BACKEND_DISABLE, 1639 BACKEND_DISABLE); 1640 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1641 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1642 GC_USER_RB_BACKEND_DISABLE, 1643 BACKEND_DISABLE); 1644 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1645 adev->gfx.config.max_shader_engines); 1646 1647 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1648 } 1649 1650 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1651 { 1652 u32 rb_bitmap_per_sa; 1653 u32 rb_bitmap_width_per_sa; 1654 u32 max_sa; 1655 u32 active_sa_bitmap; 1656 u32 global_active_rb_bitmap; 1657 u32 active_rb_bitmap = 0; 1658 u32 i; 1659 1660 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1661 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1662 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1663 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1664 1665 /* generate active rb bitmap according to active sa bitmap */ 1666 max_sa = adev->gfx.config.max_shader_engines * 1667 adev->gfx.config.max_sh_per_se; 1668 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1669 adev->gfx.config.max_sh_per_se; 1670 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1671 1672 for (i = 0; i < max_sa; i++) { 1673 if (active_sa_bitmap & (1 << i)) 1674 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1675 } 1676 1677 active_rb_bitmap &= global_active_rb_bitmap; 1678 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1679 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1680 } 1681 1682 #define LDS_APP_BASE 0x1 1683 #define SCRATCH_APP_BASE 0x2 1684 1685 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1686 { 1687 int i; 1688 uint32_t sh_mem_bases; 1689 uint32_t data; 1690 1691 /* 1692 * Configure apertures: 1693 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1694 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1695 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1696 */ 1697 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1698 SCRATCH_APP_BASE; 1699 1700 mutex_lock(&adev->srbm_mutex); 1701 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1702 soc24_grbm_select(adev, 0, 0, 0, i); 1703 /* CP and shaders */ 1704 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1705 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1706 1707 /* Enable trap for each kfd vmid. */ 1708 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1709 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1710 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1711 } 1712 soc24_grbm_select(adev, 0, 0, 0, 0); 1713 mutex_unlock(&adev->srbm_mutex); 1714 } 1715 1716 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1717 { 1718 /* TODO: harvest feature to be added later. */ 1719 } 1720 1721 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1722 { 1723 } 1724 1725 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1726 { 1727 u32 tmp; 1728 int i; 1729 1730 if (!amdgpu_sriov_vf(adev)) 1731 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1732 1733 gfx_v12_0_setup_rb(adev); 1734 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1735 gfx_v12_0_get_tcc_info(adev); 1736 adev->gfx.config.pa_sc_tile_steering_override = 0; 1737 1738 /* XXX SH_MEM regs */ 1739 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1740 mutex_lock(&adev->srbm_mutex); 1741 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1742 soc24_grbm_select(adev, 0, 0, 0, i); 1743 /* CP and shaders */ 1744 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1745 if (i != 0) { 1746 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1747 (adev->gmc.private_aperture_start >> 48)); 1748 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1749 (adev->gmc.shared_aperture_start >> 48)); 1750 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1751 } 1752 } 1753 soc24_grbm_select(adev, 0, 0, 0, 0); 1754 1755 mutex_unlock(&adev->srbm_mutex); 1756 1757 gfx_v12_0_init_compute_vmid(adev); 1758 } 1759 1760 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1761 int me, int pipe) 1762 { 1763 if (me != 0) 1764 return 0; 1765 1766 switch (pipe) { 1767 case 0: 1768 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1769 default: 1770 return 0; 1771 } 1772 } 1773 1774 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1775 int me, int pipe) 1776 { 1777 /* 1778 * amdgpu controls only the first MEC. That's why this function only 1779 * handles the setting of interrupts for this specific MEC. All other 1780 * pipes' interrupts are set by amdkfd. 1781 */ 1782 if (me != 1) 1783 return 0; 1784 1785 switch (pipe) { 1786 case 0: 1787 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1788 case 1: 1789 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1790 default: 1791 return 0; 1792 } 1793 } 1794 1795 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1796 bool enable) 1797 { 1798 u32 tmp, cp_int_cntl_reg; 1799 int i, j; 1800 1801 if (amdgpu_sriov_vf(adev)) 1802 return; 1803 1804 for (i = 0; i < adev->gfx.me.num_me; i++) { 1805 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1806 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1807 1808 if (cp_int_cntl_reg) { 1809 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1810 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1811 enable ? 1 : 0); 1812 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1813 enable ? 1 : 0); 1814 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1815 enable ? 1 : 0); 1816 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1817 enable ? 1 : 0); 1818 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1819 } 1820 } 1821 } 1822 } 1823 1824 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1825 { 1826 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1827 1828 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1829 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1830 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1831 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1832 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1833 1834 return 0; 1835 } 1836 1837 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1838 { 1839 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1840 1841 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1842 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1843 } 1844 1845 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1846 { 1847 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1848 udelay(50); 1849 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1850 udelay(50); 1851 } 1852 1853 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1854 bool enable) 1855 { 1856 uint32_t rlc_pg_cntl; 1857 1858 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1859 1860 if (!enable) { 1861 /* RLC_PG_CNTL[23] = 0 (default) 1862 * RLC will wait for handshake acks with SMU 1863 * GFXOFF will be enabled 1864 * RLC_PG_CNTL[23] = 1 1865 * RLC will not issue any message to SMU 1866 * hence no handshake between SMU & RLC 1867 * GFXOFF will be disabled 1868 */ 1869 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1870 } else 1871 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1872 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1873 } 1874 1875 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1876 { 1877 /* TODO: enable rlc & smu handshake until smu 1878 * and gfxoff feature works as expected */ 1879 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1880 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1881 1882 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1883 udelay(50); 1884 } 1885 1886 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1887 { 1888 uint32_t tmp; 1889 1890 /* enable Save Restore Machine */ 1891 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1892 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1893 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1894 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1895 } 1896 1897 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1898 { 1899 const struct rlc_firmware_header_v2_0 *hdr; 1900 const __le32 *fw_data; 1901 unsigned i, fw_size; 1902 1903 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1904 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1905 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1906 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1907 1908 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1909 RLCG_UCODE_LOADING_START_ADDRESS); 1910 1911 for (i = 0; i < fw_size; i++) 1912 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1913 le32_to_cpup(fw_data++)); 1914 1915 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1916 } 1917 1918 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1919 { 1920 const struct rlc_firmware_header_v2_2 *hdr; 1921 const __le32 *fw_data; 1922 unsigned i, fw_size; 1923 u32 tmp; 1924 1925 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1926 1927 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1928 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1929 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1930 1931 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1932 1933 for (i = 0; i < fw_size; i++) { 1934 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1935 msleep(1); 1936 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1937 le32_to_cpup(fw_data++)); 1938 } 1939 1940 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1941 1942 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1943 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1944 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1945 1946 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1947 for (i = 0; i < fw_size; i++) { 1948 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1949 msleep(1); 1950 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1951 le32_to_cpup(fw_data++)); 1952 } 1953 1954 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1955 1956 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1957 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1958 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1959 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1960 } 1961 1962 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1963 { 1964 const struct rlc_firmware_header_v2_0 *hdr; 1965 uint16_t version_major; 1966 uint16_t version_minor; 1967 1968 if (!adev->gfx.rlc_fw) 1969 return -EINVAL; 1970 1971 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1972 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1973 1974 version_major = le16_to_cpu(hdr->header.header_version_major); 1975 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1976 1977 if (version_major == 2) { 1978 gfx_v12_0_load_rlcg_microcode(adev); 1979 if (amdgpu_dpm == 1) { 1980 if (version_minor >= 2) 1981 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1982 } 1983 1984 return 0; 1985 } 1986 1987 return -EINVAL; 1988 } 1989 1990 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1991 { 1992 int r; 1993 1994 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1995 gfx_v12_0_init_csb(adev); 1996 1997 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1998 gfx_v12_0_rlc_enable_srm(adev); 1999 } else { 2000 if (amdgpu_sriov_vf(adev)) { 2001 gfx_v12_0_init_csb(adev); 2002 return 0; 2003 } 2004 2005 adev->gfx.rlc.funcs->stop(adev); 2006 2007 /* disable CG */ 2008 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2009 2010 /* disable PG */ 2011 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2012 2013 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2014 /* legacy rlc firmware loading */ 2015 r = gfx_v12_0_rlc_load_microcode(adev); 2016 if (r) 2017 return r; 2018 } 2019 2020 gfx_v12_0_init_csb(adev); 2021 2022 adev->gfx.rlc.funcs->start(adev); 2023 } 2024 2025 return 0; 2026 } 2027 2028 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2029 { 2030 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2031 const struct gfx_firmware_header_v2_0 *me_hdr; 2032 const struct gfx_firmware_header_v2_0 *mec_hdr; 2033 uint32_t pipe_id, tmp; 2034 2035 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2036 adev->gfx.mec_fw->data; 2037 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2038 adev->gfx.me_fw->data; 2039 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2040 adev->gfx.pfp_fw->data; 2041 2042 /* config pfp program start addr */ 2043 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2044 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2045 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2046 (pfp_hdr->ucode_start_addr_hi << 30) | 2047 (pfp_hdr->ucode_start_addr_lo >> 2)); 2048 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2049 pfp_hdr->ucode_start_addr_hi >> 2); 2050 } 2051 soc24_grbm_select(adev, 0, 0, 0, 0); 2052 2053 /* reset pfp pipe */ 2054 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2055 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2056 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2057 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2058 2059 /* clear pfp pipe reset */ 2060 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2061 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2062 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2063 2064 /* config me program start addr */ 2065 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2066 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2067 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2068 (me_hdr->ucode_start_addr_hi << 30) | 2069 (me_hdr->ucode_start_addr_lo >> 2)); 2070 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2071 me_hdr->ucode_start_addr_hi>>2); 2072 } 2073 soc24_grbm_select(adev, 0, 0, 0, 0); 2074 2075 /* reset me pipe */ 2076 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2077 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2079 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2080 2081 /* clear me pipe reset */ 2082 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2083 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2084 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2085 2086 /* config mec program start addr */ 2087 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2088 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2089 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2090 mec_hdr->ucode_start_addr_lo >> 2 | 2091 mec_hdr->ucode_start_addr_hi << 30); 2092 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2093 mec_hdr->ucode_start_addr_hi >> 2); 2094 } 2095 soc24_grbm_select(adev, 0, 0, 0, 0); 2096 2097 /* reset mec pipe */ 2098 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2099 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2100 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2101 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2102 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2103 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2104 2105 /* clear mec pipe reset */ 2106 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2107 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2108 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2109 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2110 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2111 } 2112 2113 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2114 { 2115 const struct gfx_firmware_header_v2_0 *cp_hdr; 2116 unsigned pipe_id, tmp; 2117 2118 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2119 adev->gfx.pfp_fw->data; 2120 mutex_lock(&adev->srbm_mutex); 2121 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2122 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2123 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2124 (cp_hdr->ucode_start_addr_hi << 30) | 2125 (cp_hdr->ucode_start_addr_lo >> 2)); 2126 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2127 cp_hdr->ucode_start_addr_hi>>2); 2128 2129 /* 2130 * Program CP_ME_CNTL to reset given PIPE to take 2131 * effect of CP_PFP_PRGRM_CNTR_START. 2132 */ 2133 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2134 if (pipe_id == 0) 2135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2136 PFP_PIPE0_RESET, 1); 2137 else 2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2139 PFP_PIPE1_RESET, 1); 2140 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2141 2142 /* Clear pfp pipe0 reset bit. */ 2143 if (pipe_id == 0) 2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2145 PFP_PIPE0_RESET, 0); 2146 else 2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2148 PFP_PIPE1_RESET, 0); 2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2150 } 2151 soc24_grbm_select(adev, 0, 0, 0, 0); 2152 mutex_unlock(&adev->srbm_mutex); 2153 } 2154 2155 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2156 { 2157 const struct gfx_firmware_header_v2_0 *cp_hdr; 2158 unsigned pipe_id, tmp; 2159 2160 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2161 adev->gfx.me_fw->data; 2162 mutex_lock(&adev->srbm_mutex); 2163 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2164 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2165 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2166 (cp_hdr->ucode_start_addr_hi << 30) | 2167 (cp_hdr->ucode_start_addr_lo >> 2) ); 2168 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2169 cp_hdr->ucode_start_addr_hi>>2); 2170 2171 /* 2172 * Program CP_ME_CNTL to reset given PIPE to take 2173 * effect of CP_ME_PRGRM_CNTR_START. 2174 */ 2175 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2176 if (pipe_id == 0) 2177 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2178 ME_PIPE0_RESET, 1); 2179 else 2180 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2181 ME_PIPE1_RESET, 1); 2182 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2183 2184 /* Clear pfp pipe0 reset bit. */ 2185 if (pipe_id == 0) 2186 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2187 ME_PIPE0_RESET, 0); 2188 else 2189 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2190 ME_PIPE1_RESET, 0); 2191 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2192 } 2193 soc24_grbm_select(adev, 0, 0, 0, 0); 2194 mutex_unlock(&adev->srbm_mutex); 2195 } 2196 2197 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2198 { 2199 const struct gfx_firmware_header_v2_0 *cp_hdr; 2200 unsigned pipe_id; 2201 2202 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2203 adev->gfx.mec_fw->data; 2204 mutex_lock(&adev->srbm_mutex); 2205 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2206 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2207 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2208 cp_hdr->ucode_start_addr_lo >> 2 | 2209 cp_hdr->ucode_start_addr_hi << 30); 2210 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2211 cp_hdr->ucode_start_addr_hi >> 2); 2212 } 2213 soc24_grbm_select(adev, 0, 0, 0, 0); 2214 mutex_unlock(&adev->srbm_mutex); 2215 } 2216 2217 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2218 { 2219 uint32_t cp_status; 2220 uint32_t bootload_status; 2221 int i; 2222 2223 for (i = 0; i < adev->usec_timeout; i++) { 2224 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2225 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2226 2227 if ((cp_status == 0) && 2228 (REG_GET_FIELD(bootload_status, 2229 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2230 break; 2231 } 2232 udelay(1); 2233 if (amdgpu_emu_mode) 2234 msleep(10); 2235 } 2236 2237 if (i >= adev->usec_timeout) { 2238 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2239 return -ETIMEDOUT; 2240 } 2241 2242 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2243 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2244 gfx_v12_0_set_me_ucode_start_addr(adev); 2245 gfx_v12_0_set_mec_ucode_start_addr(adev); 2246 } 2247 2248 return 0; 2249 } 2250 2251 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2252 { 2253 int i; 2254 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2255 2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2259 2260 for (i = 0; i < adev->usec_timeout; i++) { 2261 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2262 break; 2263 udelay(1); 2264 } 2265 2266 if (i >= adev->usec_timeout) 2267 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2268 2269 return 0; 2270 } 2271 2272 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2273 { 2274 int r; 2275 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2276 const __le32 *fw_ucode, *fw_data; 2277 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2278 uint32_t tmp; 2279 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2280 2281 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2282 adev->gfx.pfp_fw->data; 2283 2284 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2285 2286 /* instruction */ 2287 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2288 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2289 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2290 /* data */ 2291 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2292 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2293 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2294 2295 /* 64kb align */ 2296 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2297 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2298 &adev->gfx.pfp.pfp_fw_obj, 2299 &adev->gfx.pfp.pfp_fw_gpu_addr, 2300 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2301 if (r) { 2302 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2303 gfx_v12_0_pfp_fini(adev); 2304 return r; 2305 } 2306 2307 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2308 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2309 &adev->gfx.pfp.pfp_fw_data_obj, 2310 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2311 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2312 if (r) { 2313 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2314 gfx_v12_0_pfp_fini(adev); 2315 return r; 2316 } 2317 2318 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2319 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2320 2321 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2322 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2323 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2324 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2325 2326 if (amdgpu_emu_mode == 1) 2327 adev->hdp.funcs->flush_hdp(adev, NULL); 2328 2329 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2330 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2331 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2332 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2333 2334 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2335 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2336 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2337 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2338 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2339 2340 /* 2341 * Programming any of the CP_PFP_IC_BASE registers 2342 * forces invalidation of the ME L1 I$. Wait for the 2343 * invalidation complete 2344 */ 2345 for (i = 0; i < usec_timeout; i++) { 2346 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2347 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2348 INVALIDATE_CACHE_COMPLETE)) 2349 break; 2350 udelay(1); 2351 } 2352 2353 if (i >= usec_timeout) { 2354 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2355 return -EINVAL; 2356 } 2357 2358 /* Prime the L1 instruction caches */ 2359 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2360 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2361 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2362 /* Waiting for cache primed*/ 2363 for (i = 0; i < usec_timeout; i++) { 2364 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2365 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2366 ICACHE_PRIMED)) 2367 break; 2368 udelay(1); 2369 } 2370 2371 if (i >= usec_timeout) { 2372 dev_err(adev->dev, "failed to prime instruction cache\n"); 2373 return -EINVAL; 2374 } 2375 2376 mutex_lock(&adev->srbm_mutex); 2377 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2378 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2379 2380 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2381 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2382 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2383 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2384 } 2385 soc24_grbm_select(adev, 0, 0, 0, 0); 2386 mutex_unlock(&adev->srbm_mutex); 2387 2388 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2389 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2390 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2391 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2392 2393 /* Invalidate the data caches */ 2394 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2395 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2396 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2397 2398 for (i = 0; i < usec_timeout; i++) { 2399 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2400 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2401 INVALIDATE_DCACHE_COMPLETE)) 2402 break; 2403 udelay(1); 2404 } 2405 2406 if (i >= usec_timeout) { 2407 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2408 return -EINVAL; 2409 } 2410 2411 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2412 2413 return 0; 2414 } 2415 2416 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2417 { 2418 int r; 2419 const struct gfx_firmware_header_v2_0 *me_hdr; 2420 const __le32 *fw_ucode, *fw_data; 2421 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2422 uint32_t tmp; 2423 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2424 2425 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2426 adev->gfx.me_fw->data; 2427 2428 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2429 2430 /* instruction */ 2431 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2432 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2433 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2434 /* data */ 2435 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2436 le32_to_cpu(me_hdr->data_offset_bytes)); 2437 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2438 2439 /* 64kb align*/ 2440 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2441 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2442 &adev->gfx.me.me_fw_obj, 2443 &adev->gfx.me.me_fw_gpu_addr, 2444 (void **)&adev->gfx.me.me_fw_ptr); 2445 if (r) { 2446 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2447 gfx_v12_0_me_fini(adev); 2448 return r; 2449 } 2450 2451 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2452 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2453 &adev->gfx.me.me_fw_data_obj, 2454 &adev->gfx.me.me_fw_data_gpu_addr, 2455 (void **)&adev->gfx.me.me_fw_data_ptr); 2456 if (r) { 2457 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2458 gfx_v12_0_me_fini(adev); 2459 return r; 2460 } 2461 2462 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2463 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2464 2465 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2466 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2467 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2468 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2469 2470 if (amdgpu_emu_mode == 1) 2471 adev->hdp.funcs->flush_hdp(adev, NULL); 2472 2473 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2474 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2475 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2476 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2477 2478 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2479 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2480 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2481 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2482 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2483 2484 /* 2485 * Programming any of the CP_ME_IC_BASE registers 2486 * forces invalidation of the ME L1 I$. Wait for the 2487 * invalidation complete 2488 */ 2489 for (i = 0; i < usec_timeout; i++) { 2490 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2491 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2492 INVALIDATE_CACHE_COMPLETE)) 2493 break; 2494 udelay(1); 2495 } 2496 2497 if (i >= usec_timeout) { 2498 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2499 return -EINVAL; 2500 } 2501 2502 /* Prime the instruction caches */ 2503 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2504 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2505 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2506 2507 /* Waiting for instruction cache primed*/ 2508 for (i = 0; i < usec_timeout; i++) { 2509 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2510 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2511 ICACHE_PRIMED)) 2512 break; 2513 udelay(1); 2514 } 2515 2516 if (i >= usec_timeout) { 2517 dev_err(adev->dev, "failed to prime instruction cache\n"); 2518 return -EINVAL; 2519 } 2520 2521 mutex_lock(&adev->srbm_mutex); 2522 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2523 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2524 2525 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2526 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2527 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2528 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2529 } 2530 soc24_grbm_select(adev, 0, 0, 0, 0); 2531 mutex_unlock(&adev->srbm_mutex); 2532 2533 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2534 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2535 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2536 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2537 2538 /* Invalidate the data caches */ 2539 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2540 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2541 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2542 2543 for (i = 0; i < usec_timeout; i++) { 2544 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2545 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2546 INVALIDATE_DCACHE_COMPLETE)) 2547 break; 2548 udelay(1); 2549 } 2550 2551 if (i >= usec_timeout) { 2552 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2553 return -EINVAL; 2554 } 2555 2556 gfx_v12_0_set_me_ucode_start_addr(adev); 2557 2558 return 0; 2559 } 2560 2561 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2562 { 2563 int r; 2564 2565 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2566 return -EINVAL; 2567 2568 gfx_v12_0_cp_gfx_enable(adev, false); 2569 2570 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2571 if (r) { 2572 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2573 return r; 2574 } 2575 2576 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2577 if (r) { 2578 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2579 return r; 2580 } 2581 2582 return 0; 2583 } 2584 2585 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2586 { 2587 /* init the CP */ 2588 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2589 adev->gfx.config.max_hw_contexts - 1); 2590 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2591 2592 if (!amdgpu_async_gfx_ring) 2593 gfx_v12_0_cp_gfx_enable(adev, true); 2594 2595 return 0; 2596 } 2597 2598 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2599 CP_PIPE_ID pipe) 2600 { 2601 u32 tmp; 2602 2603 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2604 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2605 2606 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2607 } 2608 2609 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2610 struct amdgpu_ring *ring) 2611 { 2612 u32 tmp; 2613 2614 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2615 if (ring->use_doorbell) { 2616 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2617 DOORBELL_OFFSET, ring->doorbell_index); 2618 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2619 DOORBELL_EN, 1); 2620 } else { 2621 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2622 DOORBELL_EN, 0); 2623 } 2624 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2625 2626 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2627 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2628 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2629 2630 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2631 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2632 } 2633 2634 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2635 { 2636 struct amdgpu_ring *ring; 2637 u32 tmp; 2638 u32 rb_bufsz; 2639 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2640 2641 /* Set the write pointer delay */ 2642 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2643 2644 /* set the RB to use vmid 0 */ 2645 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2646 2647 /* Init gfx ring 0 for pipe 0 */ 2648 mutex_lock(&adev->srbm_mutex); 2649 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2650 2651 /* Set ring buffer size */ 2652 ring = &adev->gfx.gfx_ring[0]; 2653 rb_bufsz = order_base_2(ring->ring_size / 8); 2654 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2655 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2656 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2657 2658 /* Initialize the ring buffer's write pointers */ 2659 ring->wptr = 0; 2660 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2661 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2662 2663 /* set the wb address whether it's enabled or not */ 2664 rptr_addr = ring->rptr_gpu_addr; 2665 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2666 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2667 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2668 2669 wptr_gpu_addr = ring->wptr_gpu_addr; 2670 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2671 lower_32_bits(wptr_gpu_addr)); 2672 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2673 upper_32_bits(wptr_gpu_addr)); 2674 2675 mdelay(1); 2676 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2677 2678 rb_addr = ring->gpu_addr >> 8; 2679 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2680 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2681 2682 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2683 2684 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2685 mutex_unlock(&adev->srbm_mutex); 2686 2687 /* Switch to pipe 0 */ 2688 mutex_lock(&adev->srbm_mutex); 2689 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2690 mutex_unlock(&adev->srbm_mutex); 2691 2692 /* start the ring */ 2693 gfx_v12_0_cp_gfx_start(adev); 2694 return 0; 2695 } 2696 2697 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2698 { 2699 u32 data; 2700 2701 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2702 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2703 enable ? 0 : 1); 2704 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2705 enable ? 0 : 1); 2706 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2707 enable ? 0 : 1); 2708 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2709 enable ? 0 : 1); 2710 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2711 enable ? 0 : 1); 2712 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2713 enable ? 1 : 0); 2714 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2715 enable ? 1 : 0); 2716 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2717 enable ? 1 : 0); 2718 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2719 enable ? 1 : 0); 2720 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2721 enable ? 0 : 1); 2722 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2723 2724 adev->gfx.kiq[0].ring.sched.ready = enable; 2725 2726 udelay(50); 2727 } 2728 2729 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2730 { 2731 const struct gfx_firmware_header_v2_0 *mec_hdr; 2732 const __le32 *fw_ucode, *fw_data; 2733 u32 tmp, fw_ucode_size, fw_data_size; 2734 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2735 u32 *fw_ucode_ptr, *fw_data_ptr; 2736 int r; 2737 2738 if (!adev->gfx.mec_fw) 2739 return -EINVAL; 2740 2741 gfx_v12_0_cp_compute_enable(adev, false); 2742 2743 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2744 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2745 2746 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2747 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2748 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2749 2750 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2751 le32_to_cpu(mec_hdr->data_offset_bytes)); 2752 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2753 2754 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2755 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2756 &adev->gfx.mec.mec_fw_obj, 2757 &adev->gfx.mec.mec_fw_gpu_addr, 2758 (void **)&fw_ucode_ptr); 2759 if (r) { 2760 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2761 gfx_v12_0_mec_fini(adev); 2762 return r; 2763 } 2764 2765 r = amdgpu_bo_create_reserved(adev, 2766 ALIGN(fw_data_size, 64 * 1024) * 2767 adev->gfx.mec.num_pipe_per_mec, 2768 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2769 &adev->gfx.mec.mec_fw_data_obj, 2770 &adev->gfx.mec.mec_fw_data_gpu_addr, 2771 (void **)&fw_data_ptr); 2772 if (r) { 2773 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2774 gfx_v12_0_mec_fini(adev); 2775 return r; 2776 } 2777 2778 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2779 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2780 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2781 } 2782 2783 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2784 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2785 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2786 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2787 2788 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2789 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2790 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2791 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2792 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2793 2794 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2795 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2796 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2797 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2798 2799 mutex_lock(&adev->srbm_mutex); 2800 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2801 soc24_grbm_select(adev, 1, i, 0, 0); 2802 2803 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2804 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2805 i * ALIGN(fw_data_size, 64 * 1024))); 2806 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2807 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2808 i * ALIGN(fw_data_size, 64 * 1024))); 2809 2810 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2811 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2812 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2813 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2814 } 2815 mutex_unlock(&adev->srbm_mutex); 2816 soc24_grbm_select(adev, 0, 0, 0, 0); 2817 2818 /* Trigger an invalidation of the L1 instruction caches */ 2819 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2820 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2821 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2822 2823 /* Wait for invalidation complete */ 2824 for (i = 0; i < usec_timeout; i++) { 2825 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2826 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2827 INVALIDATE_DCACHE_COMPLETE)) 2828 break; 2829 udelay(1); 2830 } 2831 2832 if (i >= usec_timeout) { 2833 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2834 return -EINVAL; 2835 } 2836 2837 /* Trigger an invalidation of the L1 instruction caches */ 2838 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2839 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2840 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2841 2842 /* Wait for invalidation complete */ 2843 for (i = 0; i < usec_timeout; i++) { 2844 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2845 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2846 INVALIDATE_CACHE_COMPLETE)) 2847 break; 2848 udelay(1); 2849 } 2850 2851 if (i >= usec_timeout) { 2852 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2853 return -EINVAL; 2854 } 2855 2856 gfx_v12_0_set_mec_ucode_start_addr(adev); 2857 2858 return 0; 2859 } 2860 2861 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2862 { 2863 uint32_t tmp; 2864 struct amdgpu_device *adev = ring->adev; 2865 2866 /* tell RLC which is KIQ queue */ 2867 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2868 tmp &= 0xffffff00; 2869 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2870 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2871 } 2872 2873 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2874 { 2875 /* set graphics engine doorbell range */ 2876 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2877 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2878 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2879 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2880 2881 /* set compute engine doorbell range */ 2882 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2883 (adev->doorbell_index.kiq * 2) << 2); 2884 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2885 (adev->doorbell_index.userqueue_end * 2) << 2); 2886 } 2887 2888 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2889 struct amdgpu_mqd_prop *prop) 2890 { 2891 struct v12_gfx_mqd *mqd = m; 2892 uint64_t hqd_gpu_addr, wb_gpu_addr; 2893 uint32_t tmp; 2894 uint32_t rb_bufsz; 2895 2896 /* set up gfx hqd wptr */ 2897 mqd->cp_gfx_hqd_wptr = 0; 2898 mqd->cp_gfx_hqd_wptr_hi = 0; 2899 2900 /* set the pointer to the MQD */ 2901 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2902 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2903 2904 /* set up mqd control */ 2905 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2906 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2907 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2908 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2909 mqd->cp_gfx_mqd_control = tmp; 2910 2911 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2912 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2914 mqd->cp_gfx_hqd_vmid = 0; 2915 2916 /* set up default queue priority level 2917 * 0x0 = low priority, 0x1 = high priority */ 2918 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2919 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2920 mqd->cp_gfx_hqd_queue_priority = tmp; 2921 2922 /* set up time quantum */ 2923 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2924 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2925 mqd->cp_gfx_hqd_quantum = tmp; 2926 2927 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2928 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2929 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2930 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2931 2932 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2933 wb_gpu_addr = prop->rptr_gpu_addr; 2934 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2935 mqd->cp_gfx_hqd_rptr_addr_hi = 2936 upper_32_bits(wb_gpu_addr) & 0xffff; 2937 2938 /* set up rb_wptr_poll addr */ 2939 wb_gpu_addr = prop->wptr_gpu_addr; 2940 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2941 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2942 2943 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2944 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2945 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 2946 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2947 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2948 #ifdef __BIG_ENDIAN 2949 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2950 #endif 2951 mqd->cp_gfx_hqd_cntl = tmp; 2952 2953 /* set up cp_doorbell_control */ 2954 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 2955 if (prop->use_doorbell) { 2956 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2957 DOORBELL_OFFSET, prop->doorbell_index); 2958 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2959 DOORBELL_EN, 1); 2960 } else 2961 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2962 DOORBELL_EN, 0); 2963 mqd->cp_rb_doorbell_control = tmp; 2964 2965 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2966 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 2967 2968 /* active the queue */ 2969 mqd->cp_gfx_hqd_active = 1; 2970 2971 return 0; 2972 } 2973 2974 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2975 { 2976 struct amdgpu_device *adev = ring->adev; 2977 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2978 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2979 2980 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2981 memset((void *)mqd, 0, sizeof(*mqd)); 2982 mutex_lock(&adev->srbm_mutex); 2983 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2984 amdgpu_ring_init_mqd(ring); 2985 soc24_grbm_select(adev, 0, 0, 0, 0); 2986 mutex_unlock(&adev->srbm_mutex); 2987 if (adev->gfx.me.mqd_backup[mqd_idx]) 2988 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2989 } else { 2990 /* restore mqd with the backup copy */ 2991 if (adev->gfx.me.mqd_backup[mqd_idx]) 2992 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2993 /* reset the ring */ 2994 ring->wptr = 0; 2995 *ring->wptr_cpu_addr = 0; 2996 amdgpu_ring_clear_ring(ring); 2997 } 2998 2999 return 0; 3000 } 3001 3002 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3003 { 3004 int r, i; 3005 struct amdgpu_ring *ring; 3006 3007 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3008 ring = &adev->gfx.gfx_ring[i]; 3009 3010 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3011 if (unlikely(r != 0)) 3012 goto done; 3013 3014 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3015 if (!r) { 3016 r = gfx_v12_0_kgq_init_queue(ring, false); 3017 amdgpu_bo_kunmap(ring->mqd_obj); 3018 ring->mqd_ptr = NULL; 3019 } 3020 amdgpu_bo_unreserve(ring->mqd_obj); 3021 if (r) 3022 goto done; 3023 } 3024 3025 r = amdgpu_gfx_enable_kgq(adev, 0); 3026 if (r) 3027 goto done; 3028 3029 r = gfx_v12_0_cp_gfx_start(adev); 3030 if (r) 3031 goto done; 3032 3033 done: 3034 return r; 3035 } 3036 3037 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3038 struct amdgpu_mqd_prop *prop) 3039 { 3040 struct v12_compute_mqd *mqd = m; 3041 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3042 uint32_t tmp; 3043 3044 mqd->header = 0xC0310800; 3045 mqd->compute_pipelinestat_enable = 0x00000001; 3046 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3047 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3048 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3049 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3050 mqd->compute_misc_reserved = 0x00000007; 3051 3052 eop_base_addr = prop->eop_gpu_addr >> 8; 3053 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3054 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3055 3056 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3057 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3058 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3059 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3060 3061 mqd->cp_hqd_eop_control = tmp; 3062 3063 /* enable doorbell? */ 3064 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3065 3066 if (prop->use_doorbell) { 3067 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3068 DOORBELL_OFFSET, prop->doorbell_index); 3069 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3070 DOORBELL_EN, 1); 3071 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3072 DOORBELL_SOURCE, 0); 3073 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3074 DOORBELL_HIT, 0); 3075 } else { 3076 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3077 DOORBELL_EN, 0); 3078 } 3079 3080 mqd->cp_hqd_pq_doorbell_control = tmp; 3081 3082 /* disable the queue if it's active */ 3083 mqd->cp_hqd_dequeue_request = 0; 3084 mqd->cp_hqd_pq_rptr = 0; 3085 mqd->cp_hqd_pq_wptr_lo = 0; 3086 mqd->cp_hqd_pq_wptr_hi = 0; 3087 3088 /* set the pointer to the MQD */ 3089 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3090 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3091 3092 /* set MQD vmid to 0 */ 3093 tmp = regCP_MQD_CONTROL_DEFAULT; 3094 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3095 mqd->cp_mqd_control = tmp; 3096 3097 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3098 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3099 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3100 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3101 3102 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3103 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3104 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3105 (order_base_2(prop->queue_size / 4) - 1)); 3106 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3107 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3108 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3109 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3110 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3111 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3112 mqd->cp_hqd_pq_control = tmp; 3113 3114 /* set the wb address whether it's enabled or not */ 3115 wb_gpu_addr = prop->rptr_gpu_addr; 3116 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3117 mqd->cp_hqd_pq_rptr_report_addr_hi = 3118 upper_32_bits(wb_gpu_addr) & 0xffff; 3119 3120 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3121 wb_gpu_addr = prop->wptr_gpu_addr; 3122 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3123 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3124 3125 tmp = 0; 3126 /* enable the doorbell if requested */ 3127 if (prop->use_doorbell) { 3128 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3130 DOORBELL_OFFSET, prop->doorbell_index); 3131 3132 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3133 DOORBELL_EN, 1); 3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3135 DOORBELL_SOURCE, 0); 3136 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3137 DOORBELL_HIT, 0); 3138 } 3139 3140 mqd->cp_hqd_pq_doorbell_control = tmp; 3141 3142 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3143 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3144 3145 /* set the vmid for the queue */ 3146 mqd->cp_hqd_vmid = 0; 3147 3148 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3149 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3150 mqd->cp_hqd_persistent_state = tmp; 3151 3152 /* set MIN_IB_AVAIL_SIZE */ 3153 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3154 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3155 mqd->cp_hqd_ib_control = tmp; 3156 3157 /* set static priority for a compute queue/ring */ 3158 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3159 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3160 3161 mqd->cp_hqd_active = prop->hqd_active; 3162 3163 return 0; 3164 } 3165 3166 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3167 { 3168 struct amdgpu_device *adev = ring->adev; 3169 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3170 int j; 3171 3172 /* inactivate the queue */ 3173 if (amdgpu_sriov_vf(adev)) 3174 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3175 3176 /* disable wptr polling */ 3177 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3178 3179 /* write the EOP addr */ 3180 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3181 mqd->cp_hqd_eop_base_addr_lo); 3182 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3183 mqd->cp_hqd_eop_base_addr_hi); 3184 3185 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3186 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3187 mqd->cp_hqd_eop_control); 3188 3189 /* enable doorbell? */ 3190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3191 mqd->cp_hqd_pq_doorbell_control); 3192 3193 /* disable the queue if it's active */ 3194 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3195 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3196 for (j = 0; j < adev->usec_timeout; j++) { 3197 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3198 break; 3199 udelay(1); 3200 } 3201 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3202 mqd->cp_hqd_dequeue_request); 3203 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3204 mqd->cp_hqd_pq_rptr); 3205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3206 mqd->cp_hqd_pq_wptr_lo); 3207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3208 mqd->cp_hqd_pq_wptr_hi); 3209 } 3210 3211 /* set the pointer to the MQD */ 3212 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3213 mqd->cp_mqd_base_addr_lo); 3214 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3215 mqd->cp_mqd_base_addr_hi); 3216 3217 /* set MQD vmid to 0 */ 3218 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3219 mqd->cp_mqd_control); 3220 3221 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3223 mqd->cp_hqd_pq_base_lo); 3224 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3225 mqd->cp_hqd_pq_base_hi); 3226 3227 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3228 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3229 mqd->cp_hqd_pq_control); 3230 3231 /* set the wb address whether it's enabled or not */ 3232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3233 mqd->cp_hqd_pq_rptr_report_addr_lo); 3234 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3235 mqd->cp_hqd_pq_rptr_report_addr_hi); 3236 3237 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3238 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3239 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3240 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3241 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3242 3243 /* enable the doorbell if requested */ 3244 if (ring->use_doorbell) { 3245 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3246 (adev->doorbell_index.kiq * 2) << 2); 3247 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3248 (adev->doorbell_index.userqueue_end * 2) << 2); 3249 } 3250 3251 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3252 mqd->cp_hqd_pq_doorbell_control); 3253 3254 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3255 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3256 mqd->cp_hqd_pq_wptr_lo); 3257 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3258 mqd->cp_hqd_pq_wptr_hi); 3259 3260 /* set the vmid for the queue */ 3261 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3262 3263 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3264 mqd->cp_hqd_persistent_state); 3265 3266 /* activate the queue */ 3267 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3268 mqd->cp_hqd_active); 3269 3270 if (ring->use_doorbell) 3271 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3272 3273 return 0; 3274 } 3275 3276 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3277 { 3278 struct amdgpu_device *adev = ring->adev; 3279 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3280 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3281 3282 gfx_v12_0_kiq_setting(ring); 3283 3284 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3285 /* reset MQD to a clean status */ 3286 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3287 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3288 3289 /* reset ring buffer */ 3290 ring->wptr = 0; 3291 amdgpu_ring_clear_ring(ring); 3292 3293 mutex_lock(&adev->srbm_mutex); 3294 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3295 gfx_v12_0_kiq_init_register(ring); 3296 soc24_grbm_select(adev, 0, 0, 0, 0); 3297 mutex_unlock(&adev->srbm_mutex); 3298 } else { 3299 memset((void *)mqd, 0, sizeof(*mqd)); 3300 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3301 amdgpu_ring_clear_ring(ring); 3302 mutex_lock(&adev->srbm_mutex); 3303 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3304 amdgpu_ring_init_mqd(ring); 3305 gfx_v12_0_kiq_init_register(ring); 3306 soc24_grbm_select(adev, 0, 0, 0, 0); 3307 mutex_unlock(&adev->srbm_mutex); 3308 3309 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3310 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3317 { 3318 struct amdgpu_device *adev = ring->adev; 3319 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3320 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3321 3322 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3323 memset((void *)mqd, 0, sizeof(*mqd)); 3324 mutex_lock(&adev->srbm_mutex); 3325 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3326 amdgpu_ring_init_mqd(ring); 3327 soc24_grbm_select(adev, 0, 0, 0, 0); 3328 mutex_unlock(&adev->srbm_mutex); 3329 3330 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3331 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3332 } else { 3333 /* restore MQD to a clean status */ 3334 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3335 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3336 /* reset ring buffer */ 3337 ring->wptr = 0; 3338 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3339 amdgpu_ring_clear_ring(ring); 3340 } 3341 3342 return 0; 3343 } 3344 3345 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3346 { 3347 struct amdgpu_ring *ring; 3348 int r; 3349 3350 ring = &adev->gfx.kiq[0].ring; 3351 3352 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3353 if (unlikely(r != 0)) 3354 return r; 3355 3356 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3357 if (unlikely(r != 0)) { 3358 amdgpu_bo_unreserve(ring->mqd_obj); 3359 return r; 3360 } 3361 3362 gfx_v12_0_kiq_init_queue(ring); 3363 amdgpu_bo_kunmap(ring->mqd_obj); 3364 ring->mqd_ptr = NULL; 3365 amdgpu_bo_unreserve(ring->mqd_obj); 3366 ring->sched.ready = true; 3367 return 0; 3368 } 3369 3370 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3371 { 3372 struct amdgpu_ring *ring = NULL; 3373 int r = 0, i; 3374 3375 if (!amdgpu_async_gfx_ring) 3376 gfx_v12_0_cp_compute_enable(adev, true); 3377 3378 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3379 ring = &adev->gfx.compute_ring[i]; 3380 3381 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3382 if (unlikely(r != 0)) 3383 goto done; 3384 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3385 if (!r) { 3386 r = gfx_v12_0_kcq_init_queue(ring, false); 3387 amdgpu_bo_kunmap(ring->mqd_obj); 3388 ring->mqd_ptr = NULL; 3389 } 3390 amdgpu_bo_unreserve(ring->mqd_obj); 3391 if (r) 3392 goto done; 3393 } 3394 3395 r = amdgpu_gfx_enable_kcq(adev, 0); 3396 done: 3397 return r; 3398 } 3399 3400 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3401 { 3402 int r, i; 3403 struct amdgpu_ring *ring; 3404 3405 if (!(adev->flags & AMD_IS_APU)) 3406 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3407 3408 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3409 /* legacy firmware loading */ 3410 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3411 if (r) 3412 return r; 3413 3414 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3415 if (r) 3416 return r; 3417 } 3418 3419 gfx_v12_0_cp_set_doorbell_range(adev); 3420 3421 if (amdgpu_async_gfx_ring) { 3422 gfx_v12_0_cp_compute_enable(adev, true); 3423 gfx_v12_0_cp_gfx_enable(adev, true); 3424 } 3425 3426 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3427 r = amdgpu_mes_kiq_hw_init(adev); 3428 else 3429 r = gfx_v12_0_kiq_resume(adev); 3430 if (r) 3431 return r; 3432 3433 r = gfx_v12_0_kcq_resume(adev); 3434 if (r) 3435 return r; 3436 3437 if (!amdgpu_async_gfx_ring) { 3438 r = gfx_v12_0_cp_gfx_resume(adev); 3439 if (r) 3440 return r; 3441 } else { 3442 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3443 if (r) 3444 return r; 3445 } 3446 3447 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3448 ring = &adev->gfx.gfx_ring[i]; 3449 r = amdgpu_ring_test_helper(ring); 3450 if (r) 3451 return r; 3452 } 3453 3454 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3455 ring = &adev->gfx.compute_ring[i]; 3456 r = amdgpu_ring_test_helper(ring); 3457 if (r) 3458 return r; 3459 } 3460 3461 return 0; 3462 } 3463 3464 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3465 { 3466 gfx_v12_0_cp_gfx_enable(adev, enable); 3467 gfx_v12_0_cp_compute_enable(adev, enable); 3468 } 3469 3470 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3471 { 3472 int r; 3473 bool value; 3474 3475 r = adev->gfxhub.funcs->gart_enable(adev); 3476 if (r) 3477 return r; 3478 3479 adev->hdp.funcs->flush_hdp(adev, NULL); 3480 3481 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3482 false : true; 3483 3484 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3485 /* TODO investigate why this and the hdp flush above is needed, 3486 * are we missing a flush somewhere else? */ 3487 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3488 3489 return 0; 3490 } 3491 3492 static int get_gb_addr_config(struct amdgpu_device *adev) 3493 { 3494 u32 gb_addr_config; 3495 3496 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3497 if (gb_addr_config == 0) 3498 return -EINVAL; 3499 3500 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3501 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3502 3503 adev->gfx.config.gb_addr_config = gb_addr_config; 3504 3505 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3506 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3507 GB_ADDR_CONFIG, NUM_PIPES); 3508 3509 adev->gfx.config.max_tile_pipes = 3510 adev->gfx.config.gb_addr_config_fields.num_pipes; 3511 3512 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3513 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3514 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3515 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3516 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3517 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3518 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3519 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3520 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3521 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3522 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3523 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3524 3525 return 0; 3526 } 3527 3528 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3529 { 3530 uint32_t data; 3531 3532 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3533 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3534 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3535 3536 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3537 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3538 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3539 } 3540 3541 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3542 { 3543 if (amdgpu_sriov_vf(adev)) 3544 return; 3545 3546 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3547 case IP_VERSION(12, 0, 0): 3548 case IP_VERSION(12, 0, 1): 3549 soc15_program_register_sequence(adev, 3550 golden_settings_gc_12_0, 3551 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3552 3553 if (adev->rev_id == 0) 3554 soc15_program_register_sequence(adev, 3555 golden_settings_gc_12_0_rev0, 3556 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3557 break; 3558 default: 3559 break; 3560 } 3561 } 3562 3563 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3564 { 3565 int r; 3566 struct amdgpu_device *adev = ip_block->adev; 3567 3568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3569 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3570 /* RLC autoload sequence 1: Program rlc ram */ 3571 if (adev->gfx.imu.funcs->program_rlc_ram) 3572 adev->gfx.imu.funcs->program_rlc_ram(adev); 3573 } 3574 /* rlc autoload firmware */ 3575 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3576 if (r) 3577 return r; 3578 } else { 3579 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3580 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3581 if (adev->gfx.imu.funcs->load_microcode) 3582 adev->gfx.imu.funcs->load_microcode(adev); 3583 if (adev->gfx.imu.funcs->setup_imu) 3584 adev->gfx.imu.funcs->setup_imu(adev); 3585 if (adev->gfx.imu.funcs->start_imu) 3586 adev->gfx.imu.funcs->start_imu(adev); 3587 } 3588 3589 /* disable gpa mode in backdoor loading */ 3590 gfx_v12_0_disable_gpa_mode(adev); 3591 } 3592 } 3593 3594 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3595 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3596 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3597 if (r) { 3598 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3599 return r; 3600 } 3601 } 3602 3603 if (!amdgpu_emu_mode) 3604 gfx_v12_0_init_golden_registers(adev); 3605 3606 adev->gfx.is_poweron = true; 3607 3608 if (get_gb_addr_config(adev)) 3609 DRM_WARN("Invalid gb_addr_config !\n"); 3610 3611 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3612 gfx_v12_0_config_gfx_rs64(adev); 3613 3614 r = gfx_v12_0_gfxhub_enable(adev); 3615 if (r) 3616 return r; 3617 3618 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3619 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3620 (amdgpu_dpm == 1)) { 3621 /** 3622 * For gfx 12, rlc firmware loading relies on smu firmware is 3623 * loaded firstly, so in direct type, it has to load smc ucode 3624 * here before rlc. 3625 */ 3626 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3627 if (r) 3628 return r; 3629 } 3630 3631 gfx_v12_0_constants_init(adev); 3632 3633 if (adev->nbio.funcs->gc_doorbell_init) 3634 adev->nbio.funcs->gc_doorbell_init(adev); 3635 3636 r = gfx_v12_0_rlc_resume(adev); 3637 if (r) 3638 return r; 3639 3640 /* 3641 * init golden registers and rlc resume may override some registers, 3642 * reconfig them here 3643 */ 3644 gfx_v12_0_tcp_harvest(adev); 3645 3646 r = gfx_v12_0_cp_resume(adev); 3647 if (r) 3648 return r; 3649 3650 return r; 3651 } 3652 3653 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3654 { 3655 struct amdgpu_device *adev = ip_block->adev; 3656 uint32_t tmp; 3657 3658 cancel_delayed_work_sync(&adev->gfx.idle_work); 3659 3660 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3661 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3662 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3663 3664 if (!adev->no_hw_access) { 3665 if (amdgpu_async_gfx_ring) { 3666 if (amdgpu_gfx_disable_kgq(adev, 0)) 3667 DRM_ERROR("KGQ disable failed\n"); 3668 } 3669 3670 if (amdgpu_gfx_disable_kcq(adev, 0)) 3671 DRM_ERROR("KCQ disable failed\n"); 3672 3673 amdgpu_mes_kiq_hw_fini(adev); 3674 } 3675 3676 if (amdgpu_sriov_vf(adev)) { 3677 gfx_v12_0_cp_gfx_enable(adev, false); 3678 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3679 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3680 tmp &= 0xffffff00; 3681 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3682 3683 return 0; 3684 } 3685 gfx_v12_0_cp_enable(adev, false); 3686 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3687 3688 adev->gfxhub.funcs->gart_disable(adev); 3689 3690 adev->gfx.is_poweron = false; 3691 3692 return 0; 3693 } 3694 3695 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3696 { 3697 return gfx_v12_0_hw_fini(ip_block); 3698 } 3699 3700 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3701 { 3702 return gfx_v12_0_hw_init(ip_block); 3703 } 3704 3705 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3706 { 3707 struct amdgpu_device *adev = ip_block->adev; 3708 3709 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3710 GRBM_STATUS, GUI_ACTIVE)) 3711 return false; 3712 else 3713 return true; 3714 } 3715 3716 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3717 { 3718 unsigned i; 3719 u32 tmp; 3720 struct amdgpu_device *adev = ip_block->adev; 3721 3722 for (i = 0; i < adev->usec_timeout; i++) { 3723 /* read MC_STATUS */ 3724 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3725 GRBM_STATUS__GUI_ACTIVE_MASK; 3726 3727 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3728 return 0; 3729 udelay(1); 3730 } 3731 return -ETIMEDOUT; 3732 } 3733 3734 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3735 { 3736 uint64_t clock = 0; 3737 3738 if (adev->smuio.funcs && 3739 adev->smuio.funcs->get_gpu_clock_counter) 3740 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3741 else 3742 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3743 3744 return clock; 3745 } 3746 3747 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3748 { 3749 struct amdgpu_device *adev = ip_block->adev; 3750 3751 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3752 3753 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3754 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3755 AMDGPU_MAX_COMPUTE_RINGS); 3756 3757 gfx_v12_0_set_kiq_pm4_funcs(adev); 3758 gfx_v12_0_set_ring_funcs(adev); 3759 gfx_v12_0_set_irq_funcs(adev); 3760 gfx_v12_0_set_rlc_funcs(adev); 3761 gfx_v12_0_set_mqd_funcs(adev); 3762 gfx_v12_0_set_imu_funcs(adev); 3763 3764 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3765 3766 return gfx_v12_0_init_microcode(adev); 3767 } 3768 3769 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3770 { 3771 struct amdgpu_device *adev = ip_block->adev; 3772 int r; 3773 3774 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3775 if (r) 3776 return r; 3777 3778 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3779 if (r) 3780 return r; 3781 3782 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3783 if (r) 3784 return r; 3785 3786 return 0; 3787 } 3788 3789 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3790 { 3791 uint32_t rlc_cntl; 3792 3793 /* if RLC is not enabled, do nothing */ 3794 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3795 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3796 } 3797 3798 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3799 int xcc_id) 3800 { 3801 uint32_t data; 3802 unsigned i; 3803 3804 data = RLC_SAFE_MODE__CMD_MASK; 3805 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3806 3807 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3808 3809 /* wait for RLC_SAFE_MODE */ 3810 for (i = 0; i < adev->usec_timeout; i++) { 3811 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3812 RLC_SAFE_MODE, CMD)) 3813 break; 3814 udelay(1); 3815 } 3816 } 3817 3818 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3819 int xcc_id) 3820 { 3821 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3822 } 3823 3824 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3825 bool enable) 3826 { 3827 uint32_t def, data; 3828 3829 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3830 return; 3831 3832 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3833 3834 if (enable) 3835 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3836 else 3837 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3838 3839 if (def != data) 3840 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3841 } 3842 3843 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3844 struct amdgpu_ring *ring, 3845 unsigned vmid) 3846 { 3847 u32 reg, data; 3848 3849 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3850 if (amdgpu_sriov_is_pp_one_vf(adev)) 3851 data = RREG32_NO_KIQ(reg); 3852 else 3853 data = RREG32(reg); 3854 3855 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3856 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3857 3858 if (amdgpu_sriov_is_pp_one_vf(adev)) 3859 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3860 else 3861 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3862 3863 if (ring 3864 && amdgpu_sriov_is_pp_one_vf(adev) 3865 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3866 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3867 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3868 amdgpu_ring_emit_wreg(ring, reg, data); 3869 } 3870 } 3871 3872 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3873 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3874 .set_safe_mode = gfx_v12_0_set_safe_mode, 3875 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3876 .init = gfx_v12_0_rlc_init, 3877 .get_csb_size = gfx_v12_0_get_csb_size, 3878 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3879 .resume = gfx_v12_0_rlc_resume, 3880 .stop = gfx_v12_0_rlc_stop, 3881 .reset = gfx_v12_0_rlc_reset, 3882 .start = gfx_v12_0_rlc_start, 3883 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3884 }; 3885 3886 #if 0 3887 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3888 { 3889 /* TODO */ 3890 } 3891 3892 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3893 { 3894 /* TODO */ 3895 } 3896 #endif 3897 3898 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3899 enum amd_powergating_state state) 3900 { 3901 struct amdgpu_device *adev = ip_block->adev; 3902 bool enable = (state == AMD_PG_STATE_GATE); 3903 3904 if (amdgpu_sriov_vf(adev)) 3905 return 0; 3906 3907 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3908 case IP_VERSION(12, 0, 0): 3909 case IP_VERSION(12, 0, 1): 3910 amdgpu_gfx_off_ctrl(adev, enable); 3911 break; 3912 default: 3913 break; 3914 } 3915 3916 return 0; 3917 } 3918 3919 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3920 bool enable) 3921 { 3922 uint32_t def, data; 3923 3924 if (!(adev->cg_flags & 3925 (AMD_CG_SUPPORT_GFX_CGCG | 3926 AMD_CG_SUPPORT_GFX_CGLS | 3927 AMD_CG_SUPPORT_GFX_3D_CGCG | 3928 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3929 return; 3930 3931 if (enable) { 3932 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3933 3934 /* unset CGCG override */ 3935 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3936 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3937 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3938 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3939 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3940 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3941 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3942 3943 /* update CGCG override bits */ 3944 if (def != data) 3945 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3946 3947 /* enable cgcg FSM(0x0000363F) */ 3948 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3949 3950 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3951 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3952 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3953 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3954 } 3955 3956 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3957 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3958 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3959 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3960 } 3961 3962 if (def != data) 3963 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3964 3965 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3966 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3967 3968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3969 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3970 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3971 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3972 } 3973 3974 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3975 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3976 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3977 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3978 } 3979 3980 if (def != data) 3981 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3982 3983 /* set IDLE_POLL_COUNT(0x00900100) */ 3984 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3985 3986 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3987 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3988 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3989 3990 if (def != data) 3991 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3992 3993 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3994 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3995 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3996 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3997 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3998 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3999 4000 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4001 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4002 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4003 4004 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4005 if (adev->sdma.num_instances > 1) { 4006 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4007 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4008 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4009 } 4010 } else { 4011 /* Program RLC_CGCG_CGLS_CTRL */ 4012 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4013 4014 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4015 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4016 4017 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4018 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4019 4020 if (def != data) 4021 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4022 4023 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4024 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4025 4026 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4027 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4028 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4029 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4030 4031 if (def != data) 4032 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4033 } 4034 } 4035 4036 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4037 bool enable) 4038 { 4039 uint32_t data, def; 4040 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4041 return; 4042 4043 /* It is disabled by HW by default */ 4044 if (enable) { 4045 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4046 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4047 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4048 4049 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4050 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4051 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4052 4053 if (def != data) 4054 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4055 } 4056 } else { 4057 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4058 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4059 4060 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4061 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4062 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4063 4064 if (def != data) 4065 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4066 } 4067 } 4068 } 4069 4070 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4071 bool enable) 4072 { 4073 uint32_t def, data; 4074 4075 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4076 return; 4077 4078 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4079 4080 if (enable) 4081 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4082 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4083 else 4084 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4085 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4086 4087 if (def != data) 4088 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4089 } 4090 4091 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4092 bool enable) 4093 { 4094 uint32_t def, data; 4095 4096 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4097 return; 4098 4099 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4100 4101 if (enable) 4102 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4103 else 4104 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4105 4106 if (def != data) 4107 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4108 } 4109 4110 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4111 bool enable) 4112 { 4113 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4114 4115 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4116 4117 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4118 4119 gfx_v12_0_update_repeater_fgcg(adev, enable); 4120 4121 gfx_v12_0_update_sram_fgcg(adev, enable); 4122 4123 gfx_v12_0_update_perf_clk(adev, enable); 4124 4125 if (adev->cg_flags & 4126 (AMD_CG_SUPPORT_GFX_MGCG | 4127 AMD_CG_SUPPORT_GFX_CGLS | 4128 AMD_CG_SUPPORT_GFX_CGCG | 4129 AMD_CG_SUPPORT_GFX_3D_CGCG | 4130 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4131 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4132 4133 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4134 4135 return 0; 4136 } 4137 4138 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4139 enum amd_clockgating_state state) 4140 { 4141 struct amdgpu_device *adev = ip_block->adev; 4142 4143 if (amdgpu_sriov_vf(adev)) 4144 return 0; 4145 4146 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4147 case IP_VERSION(12, 0, 0): 4148 case IP_VERSION(12, 0, 1): 4149 gfx_v12_0_update_gfx_clock_gating(adev, 4150 state == AMD_CG_STATE_GATE); 4151 break; 4152 default: 4153 break; 4154 } 4155 4156 return 0; 4157 } 4158 4159 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4160 { 4161 struct amdgpu_device *adev = ip_block->adev; 4162 int data; 4163 4164 /* AMD_CG_SUPPORT_GFX_MGCG */ 4165 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4166 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4167 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4168 4169 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4170 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4171 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4172 4173 /* AMD_CG_SUPPORT_GFX_FGCG */ 4174 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4175 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4176 4177 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4178 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4179 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4180 4181 /* AMD_CG_SUPPORT_GFX_CGCG */ 4182 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4183 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4184 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4185 4186 /* AMD_CG_SUPPORT_GFX_CGLS */ 4187 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4188 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4189 4190 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4191 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4192 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4193 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4194 4195 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4196 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4197 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4198 } 4199 4200 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4201 { 4202 /* gfx12 is 32bit rptr*/ 4203 return *(uint32_t *)ring->rptr_cpu_addr; 4204 } 4205 4206 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4207 { 4208 struct amdgpu_device *adev = ring->adev; 4209 u64 wptr; 4210 4211 /* XXX check if swapping is necessary on BE */ 4212 if (ring->use_doorbell) { 4213 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4214 } else { 4215 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4216 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4217 } 4218 4219 return wptr; 4220 } 4221 4222 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4223 { 4224 struct amdgpu_device *adev = ring->adev; 4225 uint32_t *wptr_saved; 4226 uint32_t *is_queue_unmap; 4227 uint64_t aggregated_db_index; 4228 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4229 uint64_t wptr_tmp; 4230 4231 if (ring->is_mes_queue) { 4232 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4233 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4234 sizeof(uint32_t)); 4235 aggregated_db_index = 4236 amdgpu_mes_get_aggregated_doorbell_index(adev, 4237 ring->hw_prio); 4238 4239 wptr_tmp = ring->wptr & ring->buf_mask; 4240 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4241 *wptr_saved = wptr_tmp; 4242 /* assume doorbell always being used by mes mapped queue */ 4243 if (*is_queue_unmap) { 4244 WDOORBELL64(aggregated_db_index, wptr_tmp); 4245 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4246 } else { 4247 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4248 4249 if (*is_queue_unmap) 4250 WDOORBELL64(aggregated_db_index, wptr_tmp); 4251 } 4252 } else { 4253 if (ring->use_doorbell) { 4254 /* XXX check if swapping is necessary on BE */ 4255 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4256 ring->wptr); 4257 WDOORBELL64(ring->doorbell_index, ring->wptr); 4258 } else { 4259 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4260 lower_32_bits(ring->wptr)); 4261 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4262 upper_32_bits(ring->wptr)); 4263 } 4264 } 4265 } 4266 4267 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4268 { 4269 /* gfx12 hardware is 32bit rptr */ 4270 return *(uint32_t *)ring->rptr_cpu_addr; 4271 } 4272 4273 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4274 { 4275 u64 wptr; 4276 4277 /* XXX check if swapping is necessary on BE */ 4278 if (ring->use_doorbell) 4279 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4280 else 4281 BUG(); 4282 return wptr; 4283 } 4284 4285 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4286 { 4287 struct amdgpu_device *adev = ring->adev; 4288 uint32_t *wptr_saved; 4289 uint32_t *is_queue_unmap; 4290 uint64_t aggregated_db_index; 4291 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4292 uint64_t wptr_tmp; 4293 4294 if (ring->is_mes_queue) { 4295 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4296 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4297 sizeof(uint32_t)); 4298 aggregated_db_index = 4299 amdgpu_mes_get_aggregated_doorbell_index(adev, 4300 ring->hw_prio); 4301 4302 wptr_tmp = ring->wptr & ring->buf_mask; 4303 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4304 *wptr_saved = wptr_tmp; 4305 /* assume doorbell always used by mes mapped queue */ 4306 if (*is_queue_unmap) { 4307 WDOORBELL64(aggregated_db_index, wptr_tmp); 4308 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4309 } else { 4310 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4311 4312 if (*is_queue_unmap) 4313 WDOORBELL64(aggregated_db_index, wptr_tmp); 4314 } 4315 } else { 4316 /* XXX check if swapping is necessary on BE */ 4317 if (ring->use_doorbell) { 4318 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4319 ring->wptr); 4320 WDOORBELL64(ring->doorbell_index, ring->wptr); 4321 } else { 4322 BUG(); /* only DOORBELL method supported on gfx12 now */ 4323 } 4324 } 4325 } 4326 4327 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4328 { 4329 struct amdgpu_device *adev = ring->adev; 4330 u32 ref_and_mask, reg_mem_engine; 4331 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4332 4333 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4334 switch (ring->me) { 4335 case 1: 4336 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4337 break; 4338 case 2: 4339 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4340 break; 4341 default: 4342 return; 4343 } 4344 reg_mem_engine = 0; 4345 } else { 4346 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4347 reg_mem_engine = 1; /* pfp */ 4348 } 4349 4350 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4351 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4352 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4353 ref_and_mask, ref_and_mask, 0x20); 4354 } 4355 4356 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4357 struct amdgpu_job *job, 4358 struct amdgpu_ib *ib, 4359 uint32_t flags) 4360 { 4361 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4362 u32 header, control = 0; 4363 4364 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4365 4366 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4367 4368 control |= ib->length_dw | (vmid << 24); 4369 4370 if (ring->is_mes_queue) 4371 /* inherit vmid from mqd */ 4372 control |= 0x400000; 4373 4374 amdgpu_ring_write(ring, header); 4375 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4376 amdgpu_ring_write(ring, 4377 #ifdef __BIG_ENDIAN 4378 (2 << 0) | 4379 #endif 4380 lower_32_bits(ib->gpu_addr)); 4381 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4382 amdgpu_ring_write(ring, control); 4383 } 4384 4385 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4386 struct amdgpu_job *job, 4387 struct amdgpu_ib *ib, 4388 uint32_t flags) 4389 { 4390 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4391 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4392 4393 if (ring->is_mes_queue) 4394 /* inherit vmid from mqd */ 4395 control |= 0x40000000; 4396 4397 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4398 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4399 amdgpu_ring_write(ring, 4400 #ifdef __BIG_ENDIAN 4401 (2 << 0) | 4402 #endif 4403 lower_32_bits(ib->gpu_addr)); 4404 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4405 amdgpu_ring_write(ring, control); 4406 } 4407 4408 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4409 u64 seq, unsigned flags) 4410 { 4411 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4412 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4413 4414 /* RELEASE_MEM - flush caches, send int */ 4415 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4416 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4417 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4418 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4419 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4420 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4421 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4422 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4423 4424 /* 4425 * the address should be Qword aligned if 64bit write, Dword 4426 * aligned if only send 32bit data low (discard data high) 4427 */ 4428 if (write64bit) 4429 BUG_ON(addr & 0x7); 4430 else 4431 BUG_ON(addr & 0x3); 4432 amdgpu_ring_write(ring, lower_32_bits(addr)); 4433 amdgpu_ring_write(ring, upper_32_bits(addr)); 4434 amdgpu_ring_write(ring, lower_32_bits(seq)); 4435 amdgpu_ring_write(ring, upper_32_bits(seq)); 4436 amdgpu_ring_write(ring, ring->is_mes_queue ? 4437 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4438 } 4439 4440 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4441 { 4442 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4443 uint32_t seq = ring->fence_drv.sync_seq; 4444 uint64_t addr = ring->fence_drv.gpu_addr; 4445 4446 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4447 upper_32_bits(addr), seq, 0xffffffff, 4); 4448 } 4449 4450 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4451 uint16_t pasid, uint32_t flush_type, 4452 bool all_hub, uint8_t dst_sel) 4453 { 4454 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4455 amdgpu_ring_write(ring, 4456 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4457 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4458 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4459 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4460 } 4461 4462 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4463 unsigned vmid, uint64_t pd_addr) 4464 { 4465 if (ring->is_mes_queue) 4466 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4467 else 4468 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4469 4470 /* compute doesn't have PFP */ 4471 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4472 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4473 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4474 amdgpu_ring_write(ring, 0x0); 4475 } 4476 } 4477 4478 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4479 u64 seq, unsigned int flags) 4480 { 4481 struct amdgpu_device *adev = ring->adev; 4482 4483 /* we only allocate 32bit for each seq wb address */ 4484 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4485 4486 /* write fence seq to the "addr" */ 4487 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4488 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4489 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4490 amdgpu_ring_write(ring, lower_32_bits(addr)); 4491 amdgpu_ring_write(ring, upper_32_bits(addr)); 4492 amdgpu_ring_write(ring, lower_32_bits(seq)); 4493 4494 if (flags & AMDGPU_FENCE_FLAG_INT) { 4495 /* set register to trigger INT */ 4496 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4497 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4498 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4499 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4500 amdgpu_ring_write(ring, 0); 4501 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4502 } 4503 } 4504 4505 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4506 uint32_t flags) 4507 { 4508 uint32_t dw2 = 0; 4509 4510 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4511 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4512 /* set load_global_config & load_global_uconfig */ 4513 dw2 |= 0x8001; 4514 /* set load_cs_sh_regs */ 4515 dw2 |= 0x01000000; 4516 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4517 dw2 |= 0x10002; 4518 } 4519 4520 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4521 amdgpu_ring_write(ring, dw2); 4522 amdgpu_ring_write(ring, 0); 4523 } 4524 4525 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4526 uint64_t addr) 4527 { 4528 unsigned ret; 4529 4530 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4531 amdgpu_ring_write(ring, lower_32_bits(addr)); 4532 amdgpu_ring_write(ring, upper_32_bits(addr)); 4533 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4534 amdgpu_ring_write(ring, 0); 4535 ret = ring->wptr & ring->buf_mask; 4536 /* patch dummy value later */ 4537 amdgpu_ring_write(ring, 0); 4538 4539 return ret; 4540 } 4541 4542 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4543 { 4544 int i, r = 0; 4545 struct amdgpu_device *adev = ring->adev; 4546 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4547 struct amdgpu_ring *kiq_ring = &kiq->ring; 4548 unsigned long flags; 4549 4550 if (adev->enable_mes) 4551 return -EINVAL; 4552 4553 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4554 return -EINVAL; 4555 4556 spin_lock_irqsave(&kiq->ring_lock, flags); 4557 4558 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4559 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4560 return -ENOMEM; 4561 } 4562 4563 /* assert preemption condition */ 4564 amdgpu_ring_set_preempt_cond_exec(ring, false); 4565 4566 /* assert IB preemption, emit the trailing fence */ 4567 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4568 ring->trail_fence_gpu_addr, 4569 ++ring->trail_seq); 4570 amdgpu_ring_commit(kiq_ring); 4571 4572 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4573 4574 /* poll the trailing fence */ 4575 for (i = 0; i < adev->usec_timeout; i++) { 4576 if (ring->trail_seq == 4577 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4578 break; 4579 udelay(1); 4580 } 4581 4582 if (i >= adev->usec_timeout) { 4583 r = -EINVAL; 4584 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4585 } 4586 4587 /* deassert preemption condition */ 4588 amdgpu_ring_set_preempt_cond_exec(ring, true); 4589 return r; 4590 } 4591 4592 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4593 bool start, 4594 bool secure) 4595 { 4596 uint32_t v = secure ? FRAME_TMZ : 0; 4597 4598 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4599 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4600 } 4601 4602 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4603 uint32_t reg_val_offs) 4604 { 4605 struct amdgpu_device *adev = ring->adev; 4606 4607 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4608 amdgpu_ring_write(ring, 0 | /* src: register*/ 4609 (5 << 8) | /* dst: memory */ 4610 (1 << 20)); /* write confirm */ 4611 amdgpu_ring_write(ring, reg); 4612 amdgpu_ring_write(ring, 0); 4613 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4614 reg_val_offs * 4)); 4615 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4616 reg_val_offs * 4)); 4617 } 4618 4619 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4620 uint32_t reg, 4621 uint32_t val) 4622 { 4623 uint32_t cmd = 0; 4624 4625 switch (ring->funcs->type) { 4626 case AMDGPU_RING_TYPE_GFX: 4627 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4628 break; 4629 case AMDGPU_RING_TYPE_KIQ: 4630 cmd = (1 << 16); /* no inc addr */ 4631 break; 4632 default: 4633 cmd = WR_CONFIRM; 4634 break; 4635 } 4636 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4637 amdgpu_ring_write(ring, cmd); 4638 amdgpu_ring_write(ring, reg); 4639 amdgpu_ring_write(ring, 0); 4640 amdgpu_ring_write(ring, val); 4641 } 4642 4643 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4644 uint32_t val, uint32_t mask) 4645 { 4646 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4647 } 4648 4649 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4650 uint32_t reg0, uint32_t reg1, 4651 uint32_t ref, uint32_t mask) 4652 { 4653 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4654 4655 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4656 ref, mask, 0x20); 4657 } 4658 4659 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4660 unsigned vmid) 4661 { 4662 struct amdgpu_device *adev = ring->adev; 4663 uint32_t value = 0; 4664 4665 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4666 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4667 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4668 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4669 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4670 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4671 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4672 } 4673 4674 static void 4675 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4676 uint32_t me, uint32_t pipe, 4677 enum amdgpu_interrupt_state state) 4678 { 4679 uint32_t cp_int_cntl, cp_int_cntl_reg; 4680 4681 if (!me) { 4682 switch (pipe) { 4683 case 0: 4684 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4685 break; 4686 default: 4687 DRM_DEBUG("invalid pipe %d\n", pipe); 4688 return; 4689 } 4690 } else { 4691 DRM_DEBUG("invalid me %d\n", me); 4692 return; 4693 } 4694 4695 switch (state) { 4696 case AMDGPU_IRQ_STATE_DISABLE: 4697 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4698 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4699 TIME_STAMP_INT_ENABLE, 0); 4700 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4701 GENERIC0_INT_ENABLE, 0); 4702 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4703 break; 4704 case AMDGPU_IRQ_STATE_ENABLE: 4705 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4706 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4707 TIME_STAMP_INT_ENABLE, 1); 4708 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4709 GENERIC0_INT_ENABLE, 1); 4710 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4711 break; 4712 default: 4713 break; 4714 } 4715 } 4716 4717 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4718 int me, int pipe, 4719 enum amdgpu_interrupt_state state) 4720 { 4721 u32 mec_int_cntl, mec_int_cntl_reg; 4722 4723 /* 4724 * amdgpu controls only the first MEC. That's why this function only 4725 * handles the setting of interrupts for this specific MEC. All other 4726 * pipes' interrupts are set by amdkfd. 4727 */ 4728 4729 if (me == 1) { 4730 switch (pipe) { 4731 case 0: 4732 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4733 break; 4734 case 1: 4735 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4736 break; 4737 default: 4738 DRM_DEBUG("invalid pipe %d\n", pipe); 4739 return; 4740 } 4741 } else { 4742 DRM_DEBUG("invalid me %d\n", me); 4743 return; 4744 } 4745 4746 switch (state) { 4747 case AMDGPU_IRQ_STATE_DISABLE: 4748 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4749 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4750 TIME_STAMP_INT_ENABLE, 0); 4751 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4752 GENERIC0_INT_ENABLE, 0); 4753 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4754 break; 4755 case AMDGPU_IRQ_STATE_ENABLE: 4756 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4757 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4758 TIME_STAMP_INT_ENABLE, 1); 4759 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4760 GENERIC0_INT_ENABLE, 1); 4761 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4762 break; 4763 default: 4764 break; 4765 } 4766 } 4767 4768 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4769 struct amdgpu_irq_src *src, 4770 unsigned type, 4771 enum amdgpu_interrupt_state state) 4772 { 4773 switch (type) { 4774 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4775 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4776 break; 4777 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4778 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4779 break; 4780 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4781 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4782 break; 4783 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4784 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4785 break; 4786 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4787 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4788 break; 4789 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4790 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4791 break; 4792 default: 4793 break; 4794 } 4795 return 0; 4796 } 4797 4798 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4799 struct amdgpu_irq_src *source, 4800 struct amdgpu_iv_entry *entry) 4801 { 4802 int i; 4803 u8 me_id, pipe_id, queue_id; 4804 struct amdgpu_ring *ring; 4805 uint32_t mes_queue_id = entry->src_data[0]; 4806 4807 DRM_DEBUG("IH: CP EOP\n"); 4808 4809 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4810 struct amdgpu_mes_queue *queue; 4811 4812 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4813 4814 spin_lock(&adev->mes.queue_id_lock); 4815 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4816 if (queue) { 4817 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4818 amdgpu_fence_process(queue->ring); 4819 } 4820 spin_unlock(&adev->mes.queue_id_lock); 4821 } else { 4822 me_id = (entry->ring_id & 0x0c) >> 2; 4823 pipe_id = (entry->ring_id & 0x03) >> 0; 4824 queue_id = (entry->ring_id & 0x70) >> 4; 4825 4826 switch (me_id) { 4827 case 0: 4828 if (pipe_id == 0) 4829 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4830 else 4831 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4832 break; 4833 case 1: 4834 case 2: 4835 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4836 ring = &adev->gfx.compute_ring[i]; 4837 /* Per-queue interrupt is supported for MEC starting from VI. 4838 * The interrupt can only be enabled/disabled per pipe instead 4839 * of per queue. 4840 */ 4841 if ((ring->me == me_id) && 4842 (ring->pipe == pipe_id) && 4843 (ring->queue == queue_id)) 4844 amdgpu_fence_process(ring); 4845 } 4846 break; 4847 } 4848 } 4849 4850 return 0; 4851 } 4852 4853 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4854 struct amdgpu_irq_src *source, 4855 unsigned int type, 4856 enum amdgpu_interrupt_state state) 4857 { 4858 u32 cp_int_cntl_reg, cp_int_cntl; 4859 int i, j; 4860 4861 switch (state) { 4862 case AMDGPU_IRQ_STATE_DISABLE: 4863 case AMDGPU_IRQ_STATE_ENABLE: 4864 for (i = 0; i < adev->gfx.me.num_me; i++) { 4865 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4866 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4867 4868 if (cp_int_cntl_reg) { 4869 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4870 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4871 PRIV_REG_INT_ENABLE, 4872 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4873 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4874 } 4875 } 4876 } 4877 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4878 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4879 /* MECs start at 1 */ 4880 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4881 4882 if (cp_int_cntl_reg) { 4883 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4884 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4885 PRIV_REG_INT_ENABLE, 4886 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4887 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4888 } 4889 } 4890 } 4891 break; 4892 default: 4893 break; 4894 } 4895 4896 return 0; 4897 } 4898 4899 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4900 struct amdgpu_irq_src *source, 4901 unsigned type, 4902 enum amdgpu_interrupt_state state) 4903 { 4904 u32 cp_int_cntl_reg, cp_int_cntl; 4905 int i, j; 4906 4907 switch (state) { 4908 case AMDGPU_IRQ_STATE_DISABLE: 4909 case AMDGPU_IRQ_STATE_ENABLE: 4910 for (i = 0; i < adev->gfx.me.num_me; i++) { 4911 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4912 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4913 4914 if (cp_int_cntl_reg) { 4915 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4916 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4917 OPCODE_ERROR_INT_ENABLE, 4918 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4919 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4920 } 4921 } 4922 } 4923 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4924 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4925 /* MECs start at 1 */ 4926 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4927 4928 if (cp_int_cntl_reg) { 4929 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4930 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4931 OPCODE_ERROR_INT_ENABLE, 4932 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4933 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4934 } 4935 } 4936 } 4937 break; 4938 default: 4939 break; 4940 } 4941 return 0; 4942 } 4943 4944 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4945 struct amdgpu_irq_src *source, 4946 unsigned int type, 4947 enum amdgpu_interrupt_state state) 4948 { 4949 u32 cp_int_cntl_reg, cp_int_cntl; 4950 int i, j; 4951 4952 switch (state) { 4953 case AMDGPU_IRQ_STATE_DISABLE: 4954 case AMDGPU_IRQ_STATE_ENABLE: 4955 for (i = 0; i < adev->gfx.me.num_me; i++) { 4956 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4957 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4958 4959 if (cp_int_cntl_reg) { 4960 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4961 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4962 PRIV_INSTR_INT_ENABLE, 4963 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4964 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4965 } 4966 } 4967 } 4968 break; 4969 default: 4970 break; 4971 } 4972 4973 return 0; 4974 } 4975 4976 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4977 struct amdgpu_iv_entry *entry) 4978 { 4979 u8 me_id, pipe_id, queue_id; 4980 struct amdgpu_ring *ring; 4981 int i; 4982 4983 me_id = (entry->ring_id & 0x0c) >> 2; 4984 pipe_id = (entry->ring_id & 0x03) >> 0; 4985 queue_id = (entry->ring_id & 0x70) >> 4; 4986 4987 switch (me_id) { 4988 case 0: 4989 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4990 ring = &adev->gfx.gfx_ring[i]; 4991 if (ring->me == me_id && ring->pipe == pipe_id && 4992 ring->queue == queue_id) 4993 drm_sched_fault(&ring->sched); 4994 } 4995 break; 4996 case 1: 4997 case 2: 4998 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4999 ring = &adev->gfx.compute_ring[i]; 5000 if (ring->me == me_id && ring->pipe == pipe_id && 5001 ring->queue == queue_id) 5002 drm_sched_fault(&ring->sched); 5003 } 5004 break; 5005 default: 5006 BUG(); 5007 break; 5008 } 5009 } 5010 5011 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5012 struct amdgpu_irq_src *source, 5013 struct amdgpu_iv_entry *entry) 5014 { 5015 DRM_ERROR("Illegal register access in command stream\n"); 5016 gfx_v12_0_handle_priv_fault(adev, entry); 5017 return 0; 5018 } 5019 5020 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5021 struct amdgpu_irq_src *source, 5022 struct amdgpu_iv_entry *entry) 5023 { 5024 DRM_ERROR("Illegal opcode in command stream \n"); 5025 gfx_v12_0_handle_priv_fault(adev, entry); 5026 return 0; 5027 } 5028 5029 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5030 struct amdgpu_irq_src *source, 5031 struct amdgpu_iv_entry *entry) 5032 { 5033 DRM_ERROR("Illegal instruction in command stream\n"); 5034 gfx_v12_0_handle_priv_fault(adev, entry); 5035 return 0; 5036 } 5037 5038 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5039 { 5040 const unsigned int gcr_cntl = 5041 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5042 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5043 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5044 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5045 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5046 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5047 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5048 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5049 5050 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5051 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5052 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5053 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5054 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5055 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5056 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5057 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5058 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5059 } 5060 5061 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5062 { 5063 /* Header itself is a NOP packet */ 5064 if (num_nop == 1) { 5065 amdgpu_ring_write(ring, ring->funcs->nop); 5066 return; 5067 } 5068 5069 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5070 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5071 5072 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5073 amdgpu_ring_insert_nop(ring, num_nop - 1); 5074 } 5075 5076 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5077 { 5078 /* Emit the cleaner shader */ 5079 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5080 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5081 } 5082 5083 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5084 { 5085 struct amdgpu_device *adev = ip_block->adev; 5086 uint32_t i, j, k, reg, index = 0; 5087 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5088 5089 if (!adev->gfx.ip_dump_core) 5090 return; 5091 5092 for (i = 0; i < reg_count; i++) 5093 drm_printf(p, "%-50s \t 0x%08x\n", 5094 gc_reg_list_12_0[i].reg_name, 5095 adev->gfx.ip_dump_core[i]); 5096 5097 /* print compute queue registers for all instances */ 5098 if (!adev->gfx.ip_dump_compute_queues) 5099 return; 5100 5101 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5102 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5103 adev->gfx.mec.num_mec, 5104 adev->gfx.mec.num_pipe_per_mec, 5105 adev->gfx.mec.num_queue_per_pipe); 5106 5107 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5108 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5109 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5110 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5111 for (reg = 0; reg < reg_count; reg++) { 5112 drm_printf(p, "%-50s \t 0x%08x\n", 5113 gc_cp_reg_list_12[reg].reg_name, 5114 adev->gfx.ip_dump_compute_queues[index + reg]); 5115 } 5116 index += reg_count; 5117 } 5118 } 5119 } 5120 5121 /* print gfx queue registers for all instances */ 5122 if (!adev->gfx.ip_dump_gfx_queues) 5123 return; 5124 5125 index = 0; 5126 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5127 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5128 adev->gfx.me.num_me, 5129 adev->gfx.me.num_pipe_per_me, 5130 adev->gfx.me.num_queue_per_pipe); 5131 5132 for (i = 0; i < adev->gfx.me.num_me; i++) { 5133 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5134 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5135 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5136 for (reg = 0; reg < reg_count; reg++) { 5137 drm_printf(p, "%-50s \t 0x%08x\n", 5138 gc_gfx_queue_reg_list_12[reg].reg_name, 5139 adev->gfx.ip_dump_gfx_queues[index + reg]); 5140 } 5141 index += reg_count; 5142 } 5143 } 5144 } 5145 } 5146 5147 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5148 { 5149 struct amdgpu_device *adev = ip_block->adev; 5150 uint32_t i, j, k, reg, index = 0; 5151 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5152 5153 if (!adev->gfx.ip_dump_core) 5154 return; 5155 5156 amdgpu_gfx_off_ctrl(adev, false); 5157 for (i = 0; i < reg_count; i++) 5158 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5159 amdgpu_gfx_off_ctrl(adev, true); 5160 5161 /* dump compute queue registers for all instances */ 5162 if (!adev->gfx.ip_dump_compute_queues) 5163 return; 5164 5165 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5166 amdgpu_gfx_off_ctrl(adev, false); 5167 mutex_lock(&adev->srbm_mutex); 5168 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5169 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5170 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5171 /* ME0 is for GFX so start from 1 for CP */ 5172 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5173 for (reg = 0; reg < reg_count; reg++) { 5174 adev->gfx.ip_dump_compute_queues[index + reg] = 5175 RREG32(SOC15_REG_ENTRY_OFFSET( 5176 gc_cp_reg_list_12[reg])); 5177 } 5178 index += reg_count; 5179 } 5180 } 5181 } 5182 soc24_grbm_select(adev, 0, 0, 0, 0); 5183 mutex_unlock(&adev->srbm_mutex); 5184 amdgpu_gfx_off_ctrl(adev, true); 5185 5186 /* dump gfx queue registers for all instances */ 5187 if (!adev->gfx.ip_dump_gfx_queues) 5188 return; 5189 5190 index = 0; 5191 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5192 amdgpu_gfx_off_ctrl(adev, false); 5193 mutex_lock(&adev->srbm_mutex); 5194 for (i = 0; i < adev->gfx.me.num_me; i++) { 5195 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5196 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5197 soc24_grbm_select(adev, i, j, k, 0); 5198 5199 for (reg = 0; reg < reg_count; reg++) { 5200 adev->gfx.ip_dump_gfx_queues[index + reg] = 5201 RREG32(SOC15_REG_ENTRY_OFFSET( 5202 gc_gfx_queue_reg_list_12[reg])); 5203 } 5204 index += reg_count; 5205 } 5206 } 5207 } 5208 soc24_grbm_select(adev, 0, 0, 0, 0); 5209 mutex_unlock(&adev->srbm_mutex); 5210 amdgpu_gfx_off_ctrl(adev, true); 5211 } 5212 5213 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5214 { 5215 struct amdgpu_device *adev = ring->adev; 5216 int r; 5217 5218 if (amdgpu_sriov_vf(adev)) 5219 return -EINVAL; 5220 5221 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5222 if (r) { 5223 dev_err(adev->dev, "reset via MES failed %d\n", r); 5224 return r; 5225 } 5226 5227 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5228 if (unlikely(r != 0)) { 5229 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5230 return r; 5231 } 5232 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5233 if (!r) { 5234 r = gfx_v12_0_kgq_init_queue(ring, true); 5235 amdgpu_bo_kunmap(ring->mqd_obj); 5236 ring->mqd_ptr = NULL; 5237 } 5238 amdgpu_bo_unreserve(ring->mqd_obj); 5239 if (r) { 5240 DRM_ERROR("fail to unresv mqd_obj\n"); 5241 return r; 5242 } 5243 5244 r = amdgpu_mes_map_legacy_queue(adev, ring); 5245 if (r) { 5246 dev_err(adev->dev, "failed to remap kgq\n"); 5247 return r; 5248 } 5249 5250 return amdgpu_ring_test_ring(ring); 5251 } 5252 5253 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5254 { 5255 struct amdgpu_device *adev = ring->adev; 5256 int r; 5257 5258 if (amdgpu_sriov_vf(adev)) 5259 return -EINVAL; 5260 5261 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5262 if (r) { 5263 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5264 return r; 5265 } 5266 5267 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5268 if (unlikely(r != 0)) { 5269 DRM_ERROR("fail to resv mqd_obj\n"); 5270 return r; 5271 } 5272 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5273 if (!r) { 5274 r = gfx_v12_0_kcq_init_queue(ring, true); 5275 amdgpu_bo_kunmap(ring->mqd_obj); 5276 ring->mqd_ptr = NULL; 5277 } 5278 amdgpu_bo_unreserve(ring->mqd_obj); 5279 if (r) { 5280 DRM_ERROR("fail to unresv mqd_obj\n"); 5281 return r; 5282 } 5283 r = amdgpu_mes_map_legacy_queue(adev, ring); 5284 if (r) { 5285 dev_err(adev->dev, "failed to remap kcq\n"); 5286 return r; 5287 } 5288 5289 return amdgpu_ring_test_ring(ring); 5290 } 5291 5292 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5293 { 5294 amdgpu_gfx_profile_ring_begin_use(ring); 5295 5296 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5297 } 5298 5299 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5300 { 5301 amdgpu_gfx_profile_ring_end_use(ring); 5302 5303 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5304 } 5305 5306 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5307 .name = "gfx_v12_0", 5308 .early_init = gfx_v12_0_early_init, 5309 .late_init = gfx_v12_0_late_init, 5310 .sw_init = gfx_v12_0_sw_init, 5311 .sw_fini = gfx_v12_0_sw_fini, 5312 .hw_init = gfx_v12_0_hw_init, 5313 .hw_fini = gfx_v12_0_hw_fini, 5314 .suspend = gfx_v12_0_suspend, 5315 .resume = gfx_v12_0_resume, 5316 .is_idle = gfx_v12_0_is_idle, 5317 .wait_for_idle = gfx_v12_0_wait_for_idle, 5318 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5319 .set_powergating_state = gfx_v12_0_set_powergating_state, 5320 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5321 .dump_ip_state = gfx_v12_ip_dump, 5322 .print_ip_state = gfx_v12_ip_print, 5323 }; 5324 5325 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5326 .type = AMDGPU_RING_TYPE_GFX, 5327 .align_mask = 0xff, 5328 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5329 .support_64bit_ptrs = true, 5330 .secure_submission_supported = true, 5331 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5332 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5333 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5334 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5335 5 + /* COND_EXEC */ 5336 7 + /* PIPELINE_SYNC */ 5337 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5338 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5339 2 + /* VM_FLUSH */ 5340 8 + /* FENCE for VM_FLUSH */ 5341 5 + /* COND_EXEC */ 5342 7 + /* HDP_flush */ 5343 4 + /* VGT_flush */ 5344 31 + /* DE_META */ 5345 3 + /* CNTX_CTRL */ 5346 5 + /* HDP_INVL */ 5347 8 + 8 + /* FENCE x2 */ 5348 8 + /* gfx_v12_0_emit_mem_sync */ 5349 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5350 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5351 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5352 .emit_fence = gfx_v12_0_ring_emit_fence, 5353 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5354 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5355 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5356 .test_ring = gfx_v12_0_ring_test_ring, 5357 .test_ib = gfx_v12_0_ring_test_ib, 5358 .insert_nop = gfx_v12_ring_insert_nop, 5359 .pad_ib = amdgpu_ring_generic_pad_ib, 5360 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5361 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5362 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5363 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5364 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5365 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5366 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5367 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5368 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5369 .reset = gfx_v12_0_reset_kgq, 5370 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5371 .begin_use = gfx_v12_0_ring_begin_use, 5372 .end_use = gfx_v12_0_ring_end_use, 5373 }; 5374 5375 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5376 .type = AMDGPU_RING_TYPE_COMPUTE, 5377 .align_mask = 0xff, 5378 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5379 .support_64bit_ptrs = true, 5380 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5381 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5382 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5383 .emit_frame_size = 5384 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5385 5 + /* hdp invalidate */ 5386 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5387 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5388 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5389 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5390 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5391 8 + /* gfx_v12_0_emit_mem_sync */ 5392 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5393 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5394 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5395 .emit_fence = gfx_v12_0_ring_emit_fence, 5396 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5397 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5398 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5399 .test_ring = gfx_v12_0_ring_test_ring, 5400 .test_ib = gfx_v12_0_ring_test_ib, 5401 .insert_nop = gfx_v12_ring_insert_nop, 5402 .pad_ib = amdgpu_ring_generic_pad_ib, 5403 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5404 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5405 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5406 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5407 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5408 .reset = gfx_v12_0_reset_kcq, 5409 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5410 .begin_use = gfx_v12_0_ring_begin_use, 5411 .end_use = gfx_v12_0_ring_end_use, 5412 }; 5413 5414 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5415 .type = AMDGPU_RING_TYPE_KIQ, 5416 .align_mask = 0xff, 5417 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5418 .support_64bit_ptrs = true, 5419 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5420 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5421 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5422 .emit_frame_size = 5423 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5424 5 + /*hdp invalidate */ 5425 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5426 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5427 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5428 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5429 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5430 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5431 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5432 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5433 .test_ring = gfx_v12_0_ring_test_ring, 5434 .test_ib = gfx_v12_0_ring_test_ib, 5435 .insert_nop = amdgpu_ring_insert_nop, 5436 .pad_ib = amdgpu_ring_generic_pad_ib, 5437 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5438 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5439 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5440 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5441 }; 5442 5443 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5444 { 5445 int i; 5446 5447 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5448 5449 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5450 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5451 5452 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5453 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5454 } 5455 5456 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5457 .set = gfx_v12_0_set_eop_interrupt_state, 5458 .process = gfx_v12_0_eop_irq, 5459 }; 5460 5461 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5462 .set = gfx_v12_0_set_priv_reg_fault_state, 5463 .process = gfx_v12_0_priv_reg_irq, 5464 }; 5465 5466 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5467 .set = gfx_v12_0_set_bad_op_fault_state, 5468 .process = gfx_v12_0_bad_op_irq, 5469 }; 5470 5471 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5472 .set = gfx_v12_0_set_priv_inst_fault_state, 5473 .process = gfx_v12_0_priv_inst_irq, 5474 }; 5475 5476 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5477 { 5478 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5479 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5480 5481 adev->gfx.priv_reg_irq.num_types = 1; 5482 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5483 5484 adev->gfx.bad_op_irq.num_types = 1; 5485 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5486 5487 adev->gfx.priv_inst_irq.num_types = 1; 5488 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5489 } 5490 5491 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5492 { 5493 if (adev->flags & AMD_IS_APU) 5494 adev->gfx.imu.mode = MISSION_MODE; 5495 else 5496 adev->gfx.imu.mode = DEBUG_MODE; 5497 5498 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5499 } 5500 5501 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5502 { 5503 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5504 } 5505 5506 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5507 { 5508 /* set gfx eng mqd */ 5509 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5510 sizeof(struct v12_gfx_mqd); 5511 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5512 gfx_v12_0_gfx_mqd_init; 5513 /* set compute eng mqd */ 5514 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5515 sizeof(struct v12_compute_mqd); 5516 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5517 gfx_v12_0_compute_mqd_init; 5518 } 5519 5520 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5521 u32 bitmap) 5522 { 5523 u32 data; 5524 5525 if (!bitmap) 5526 return; 5527 5528 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5529 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5530 5531 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5532 } 5533 5534 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5535 { 5536 u32 data, wgp_bitmask; 5537 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5538 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5539 5540 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5541 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5542 5543 wgp_bitmask = 5544 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5545 5546 return (~data) & wgp_bitmask; 5547 } 5548 5549 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5550 { 5551 u32 wgp_idx, wgp_active_bitmap; 5552 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5553 5554 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5555 cu_active_bitmap = 0; 5556 5557 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5558 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5559 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5560 if (wgp_active_bitmap & (1 << wgp_idx)) 5561 cu_active_bitmap |= cu_bitmap_per_wgp; 5562 } 5563 5564 return cu_active_bitmap; 5565 } 5566 5567 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5568 struct amdgpu_cu_info *cu_info) 5569 { 5570 int i, j, k, counter, active_cu_number = 0; 5571 u32 mask, bitmap; 5572 unsigned disable_masks[8 * 2]; 5573 5574 if (!adev || !cu_info) 5575 return -EINVAL; 5576 5577 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5578 5579 mutex_lock(&adev->grbm_idx_mutex); 5580 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5581 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5582 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5583 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5584 continue; 5585 mask = 1; 5586 counter = 0; 5587 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5588 if (i < 8 && j < 2) 5589 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5590 adev, disable_masks[i * 2 + j]); 5591 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5592 5593 /** 5594 * GFX12 could support more than 4 SEs, while the bitmap 5595 * in cu_info struct is 4x4 and ioctl interface struct 5596 * drm_amdgpu_info_device should keep stable. 5597 * So we use last two columns of bitmap to store cu mask for 5598 * SEs 4 to 7, the layout of the bitmap is as below: 5599 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5600 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5601 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5602 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5603 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5604 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5605 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5606 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5607 */ 5608 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5609 5610 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5611 if (bitmap & mask) 5612 counter++; 5613 5614 mask <<= 1; 5615 } 5616 active_cu_number += counter; 5617 } 5618 } 5619 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5620 mutex_unlock(&adev->grbm_idx_mutex); 5621 5622 cu_info->number = active_cu_number; 5623 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5624 5625 return 0; 5626 } 5627 5628 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5629 .type = AMD_IP_BLOCK_TYPE_GFX, 5630 .major = 12, 5631 .minor = 0, 5632 .rev = 0, 5633 .funcs = &gfx_v12_0_ip_funcs, 5634 }; 5635