1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 282 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 283 uint32_t val); 284 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 285 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 286 uint16_t pasid, uint32_t flush_type, 287 bool all_hub, uint8_t dst_sel); 288 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 291 bool enable); 292 293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 294 uint64_t queue_mask) 295 { 296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 304 amdgpu_ring_write(kiq_ring, 0); 305 } 306 307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 308 struct amdgpu_ring *ring) 309 { 310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 311 uint64_t wptr_addr = ring->wptr_gpu_addr; 312 uint32_t me = 0, eng_sel = 0; 313 314 switch (ring->funcs->type) { 315 case AMDGPU_RING_TYPE_COMPUTE: 316 me = 1; 317 eng_sel = 0; 318 break; 319 case AMDGPU_RING_TYPE_GFX: 320 me = 0; 321 eng_sel = 4; 322 break; 323 case AMDGPU_RING_TYPE_MES: 324 me = 2; 325 eng_sel = 5; 326 break; 327 default: 328 WARN_ON(1); 329 } 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 338 PACKET3_MAP_QUEUES_ME((me)) | 339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 348 } 349 350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 351 struct amdgpu_ring *ring, 352 enum amdgpu_unmap_queues_action action, 353 u64 gpu_addr, u64 seq) 354 { 355 struct amdgpu_device *adev = kiq_ring->adev; 356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 357 358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 360 gpu_addr, seq, 0); 361 return; 362 } 363 364 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 366 PACKET3_UNMAP_QUEUES_ACTION(action) | 367 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 368 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 369 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 370 amdgpu_ring_write(kiq_ring, 371 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 372 373 if (action == PREEMPT_QUEUES_NO_UNMAP) { 374 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 376 amdgpu_ring_write(kiq_ring, seq); 377 } else { 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 amdgpu_ring_write(kiq_ring, 0); 381 } 382 } 383 384 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 385 struct amdgpu_ring *ring, 386 u64 addr, u64 seq) 387 { 388 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 389 390 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 391 amdgpu_ring_write(kiq_ring, 392 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 393 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 394 PACKET3_QUERY_STATUS_COMMAND(2)); 395 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 396 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 397 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 400 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 401 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 402 } 403 404 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 405 uint16_t pasid, 406 uint32_t flush_type, 407 bool all_hub) 408 { 409 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 410 } 411 412 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 413 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 414 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 415 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 416 .kiq_query_status = gfx_v12_0_kiq_query_status, 417 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 418 .set_resources_size = 8, 419 .map_queues_size = 7, 420 .unmap_queues_size = 6, 421 .query_status_size = 7, 422 .invalidate_tlbs_size = 2, 423 }; 424 425 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 426 { 427 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 428 } 429 430 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 431 int mem_space, int opt, uint32_t addr0, 432 uint32_t addr1, uint32_t ref, 433 uint32_t mask, uint32_t inv) 434 { 435 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 436 amdgpu_ring_write(ring, 437 /* memory (1) or register (0) */ 438 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 439 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 440 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 441 WAIT_REG_MEM_ENGINE(eng_sel))); 442 443 if (mem_space) 444 BUG_ON(addr0 & 0x3); /* Dword align */ 445 amdgpu_ring_write(ring, addr0); 446 amdgpu_ring_write(ring, addr1); 447 amdgpu_ring_write(ring, ref); 448 amdgpu_ring_write(ring, mask); 449 amdgpu_ring_write(ring, inv); /* poll interval */ 450 } 451 452 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 453 { 454 struct amdgpu_device *adev = ring->adev; 455 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 456 uint32_t tmp = 0; 457 unsigned i; 458 int r; 459 460 WREG32(scratch, 0xCAFEDEAD); 461 r = amdgpu_ring_alloc(ring, 5); 462 if (r) { 463 dev_err(adev->dev, 464 "amdgpu: cp failed to lock ring %d (%d).\n", 465 ring->idx, r); 466 return r; 467 } 468 469 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 470 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 471 } else { 472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 473 amdgpu_ring_write(ring, scratch - 474 PACKET3_SET_UCONFIG_REG_START); 475 amdgpu_ring_write(ring, 0xDEADBEEF); 476 } 477 amdgpu_ring_commit(ring); 478 479 for (i = 0; i < adev->usec_timeout; i++) { 480 tmp = RREG32(scratch); 481 if (tmp == 0xDEADBEEF) 482 break; 483 if (amdgpu_emu_mode == 1) 484 msleep(1); 485 else 486 udelay(1); 487 } 488 489 if (i >= adev->usec_timeout) 490 r = -ETIMEDOUT; 491 return r; 492 } 493 494 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 495 { 496 struct amdgpu_device *adev = ring->adev; 497 struct amdgpu_ib ib; 498 struct dma_fence *f = NULL; 499 unsigned index; 500 uint64_t gpu_addr; 501 uint32_t *cpu_ptr; 502 long r; 503 504 /* MES KIQ fw hasn't indirect buffer support for now */ 505 if (adev->enable_mes_kiq && 506 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 507 return 0; 508 509 memset(&ib, 0, sizeof(ib)); 510 511 r = amdgpu_device_wb_get(adev, &index); 512 if (r) 513 return r; 514 515 gpu_addr = adev->wb.gpu_addr + (index * 4); 516 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 517 cpu_ptr = &adev->wb.wb[index]; 518 519 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 520 if (r) { 521 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 522 goto err1; 523 } 524 525 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 526 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 527 ib.ptr[2] = lower_32_bits(gpu_addr); 528 ib.ptr[3] = upper_32_bits(gpu_addr); 529 ib.ptr[4] = 0xDEADBEEF; 530 ib.length_dw = 5; 531 532 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 533 if (r) 534 goto err2; 535 536 r = dma_fence_wait_timeout(f, false, timeout); 537 if (r == 0) { 538 r = -ETIMEDOUT; 539 goto err2; 540 } else if (r < 0) { 541 goto err2; 542 } 543 544 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 545 r = 0; 546 else 547 r = -EINVAL; 548 err2: 549 amdgpu_ib_free(&ib, NULL); 550 dma_fence_put(f); 551 err1: 552 amdgpu_device_wb_free(adev, index); 553 return r; 554 } 555 556 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 557 { 558 amdgpu_ucode_release(&adev->gfx.pfp_fw); 559 amdgpu_ucode_release(&adev->gfx.me_fw); 560 amdgpu_ucode_release(&adev->gfx.rlc_fw); 561 amdgpu_ucode_release(&adev->gfx.mec_fw); 562 563 kfree(adev->gfx.rlc.register_list_format); 564 } 565 566 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 567 { 568 const struct psp_firmware_header_v1_0 *toc_hdr; 569 int err = 0; 570 571 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_toc.bin", ucode_prefix); 574 if (err) 575 goto out; 576 577 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 578 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 579 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 580 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 581 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 582 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 583 return 0; 584 out: 585 amdgpu_ucode_release(&adev->psp.toc_fw); 586 return err; 587 } 588 589 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 590 { 591 char ucode_prefix[30]; 592 int err; 593 const struct rlc_firmware_header_v2_0 *rlc_hdr; 594 uint16_t version_major; 595 uint16_t version_minor; 596 597 DRM_DEBUG("\n"); 598 599 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 600 601 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 602 AMDGPU_UCODE_REQUIRED, 603 "amdgpu/%s_pfp.bin", ucode_prefix); 604 if (err) 605 goto out; 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 607 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 608 609 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 610 AMDGPU_UCODE_REQUIRED, 611 "amdgpu/%s_me.bin", ucode_prefix); 612 if (err) 613 goto out; 614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 615 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 616 617 if (!amdgpu_sriov_vf(adev)) { 618 if (amdgpu_is_kicker_fw(adev)) 619 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 620 AMDGPU_UCODE_REQUIRED, 621 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 622 else 623 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 624 AMDGPU_UCODE_REQUIRED, 625 "amdgpu/%s_rlc.bin", ucode_prefix); 626 if (err) 627 goto out; 628 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 629 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 630 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 631 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 632 if (err) 633 goto out; 634 } 635 636 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 637 AMDGPU_UCODE_REQUIRED, 638 "amdgpu/%s_mec.bin", ucode_prefix); 639 if (err) 640 goto out; 641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 643 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 644 645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 646 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 647 648 /* only one MEC for gfx 12 */ 649 adev->gfx.mec2_fw = NULL; 650 651 if (adev->gfx.imu.funcs) { 652 if (adev->gfx.imu.funcs->init_microcode) { 653 err = adev->gfx.imu.funcs->init_microcode(adev); 654 if (err) 655 dev_err(adev->dev, "Failed to load imu firmware!\n"); 656 } 657 } 658 659 out: 660 if (err) { 661 amdgpu_ucode_release(&adev->gfx.pfp_fw); 662 amdgpu_ucode_release(&adev->gfx.me_fw); 663 amdgpu_ucode_release(&adev->gfx.rlc_fw); 664 amdgpu_ucode_release(&adev->gfx.mec_fw); 665 } 666 667 return err; 668 } 669 670 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 671 { 672 u32 count = 0; 673 const struct cs_section_def *sect = NULL; 674 const struct cs_extent_def *ext = NULL; 675 676 count += 1; 677 678 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 679 if (sect->id == SECT_CONTEXT) { 680 for (ext = sect->section; ext->extent != NULL; ++ext) 681 count += 2 + ext->reg_count; 682 } else 683 return 0; 684 } 685 686 return count; 687 } 688 689 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 690 { 691 u32 count = 0, clustercount = 0, i; 692 const struct cs_section_def *sect = NULL; 693 const struct cs_extent_def *ext = NULL; 694 695 if (adev->gfx.rlc.cs_data == NULL) 696 return; 697 if (buffer == NULL) 698 return; 699 700 count += 1; 701 702 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 703 if (sect->id == SECT_CONTEXT) { 704 for (ext = sect->section; ext->extent != NULL; ++ext) { 705 clustercount++; 706 buffer[count++] = ext->reg_count; 707 buffer[count++] = ext->reg_index; 708 709 for (i = 0; i < ext->reg_count; i++) 710 buffer[count++] = cpu_to_le32(ext->extent[i]); 711 } 712 } else 713 return; 714 } 715 716 buffer[0] = clustercount; 717 } 718 719 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 720 { 721 /* clear state block */ 722 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 723 &adev->gfx.rlc.clear_state_gpu_addr, 724 (void **)&adev->gfx.rlc.cs_ptr); 725 726 /* jump table block */ 727 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 728 &adev->gfx.rlc.cp_table_gpu_addr, 729 (void **)&adev->gfx.rlc.cp_table_ptr); 730 } 731 732 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 733 { 734 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 735 736 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 737 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 738 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 739 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 740 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 741 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 742 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 743 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 744 adev->gfx.rlc.rlcg_reg_access_supported = true; 745 } 746 747 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 748 { 749 const struct cs_section_def *cs_data; 750 int r; 751 752 adev->gfx.rlc.cs_data = gfx12_cs_data; 753 754 cs_data = adev->gfx.rlc.cs_data; 755 756 if (cs_data) { 757 /* init clear state block */ 758 r = amdgpu_gfx_rlc_init_csb(adev); 759 if (r) 760 return r; 761 } 762 763 /* init spm vmid with 0xf */ 764 if (adev->gfx.rlc.funcs->update_spm_vmid) 765 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 766 767 return 0; 768 } 769 770 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 771 { 772 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 774 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 775 } 776 777 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 778 { 779 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 780 781 amdgpu_gfx_graphics_queue_acquire(adev); 782 } 783 784 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 785 { 786 int r; 787 u32 *hpd; 788 size_t mec_hpd_size; 789 790 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 791 792 /* take ownership of the relevant compute queues */ 793 amdgpu_gfx_compute_queue_acquire(adev); 794 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 795 796 if (mec_hpd_size) { 797 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 798 AMDGPU_GEM_DOMAIN_GTT, 799 &adev->gfx.mec.hpd_eop_obj, 800 &adev->gfx.mec.hpd_eop_gpu_addr, 801 (void **)&hpd); 802 if (r) { 803 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 804 gfx_v12_0_mec_fini(adev); 805 return r; 806 } 807 808 memset(hpd, 0, mec_hpd_size); 809 810 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 811 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 812 } 813 814 return 0; 815 } 816 817 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 818 { 819 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 820 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 821 (address << SQ_IND_INDEX__INDEX__SHIFT)); 822 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 823 } 824 825 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 826 uint32_t thread, uint32_t regno, 827 uint32_t num, uint32_t *out) 828 { 829 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 830 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 831 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 832 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 833 (SQ_IND_INDEX__AUTO_INCR_MASK)); 834 while (num--) 835 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 836 } 837 838 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 839 uint32_t xcc_id, 840 uint32_t simd, uint32_t wave, 841 uint32_t *dst, int *no_fields) 842 { 843 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 844 * field when performing a select_se_sh so it should be 845 * zero here */ 846 WARN_ON(simd != 0); 847 848 /* type 4 wave data */ 849 dst[(*no_fields)++] = 4; 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 873 } 874 875 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 876 uint32_t xcc_id, uint32_t simd, 877 uint32_t wave, uint32_t start, 878 uint32_t size, uint32_t *dst) 879 { 880 WARN_ON(simd != 0); 881 882 wave_read_regs( 883 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 884 dst); 885 } 886 887 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 888 uint32_t xcc_id, uint32_t simd, 889 uint32_t wave, uint32_t thread, 890 uint32_t start, uint32_t size, 891 uint32_t *dst) 892 { 893 wave_read_regs( 894 adev, wave, thread, 895 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 896 } 897 898 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 899 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 900 { 901 soc24_grbm_select(adev, me, pipe, q, vm); 902 } 903 904 /* all sizes are in bytes */ 905 #define MQD_SHADOW_BASE_SIZE 73728 906 #define MQD_SHADOW_BASE_ALIGNMENT 256 907 #define MQD_FWWORKAREA_SIZE 484 908 #define MQD_FWWORKAREA_ALIGNMENT 256 909 910 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 911 struct amdgpu_gfx_shadow_info *shadow_info) 912 { 913 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 914 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 915 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 916 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 917 } 918 919 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 920 struct amdgpu_gfx_shadow_info *shadow_info, 921 bool skip_check) 922 { 923 if (adev->gfx.cp_gfx_shadow || skip_check) { 924 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 925 return 0; 926 } 927 928 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 929 return -EINVAL; 930 } 931 932 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 933 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 934 .select_se_sh = &gfx_v12_0_select_se_sh, 935 .read_wave_data = &gfx_v12_0_read_wave_data, 936 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 937 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 938 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 939 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 940 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 941 }; 942 943 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 944 { 945 946 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 947 case IP_VERSION(12, 0, 0): 948 case IP_VERSION(12, 0, 1): 949 adev->gfx.config.max_hw_contexts = 8; 950 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 951 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 952 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 953 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 954 break; 955 default: 956 BUG(); 957 break; 958 } 959 960 return 0; 961 } 962 963 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 964 int me, int pipe, int queue) 965 { 966 int r; 967 struct amdgpu_ring *ring; 968 unsigned int irq_type; 969 970 ring = &adev->gfx.gfx_ring[ring_id]; 971 972 ring->me = me; 973 ring->pipe = pipe; 974 ring->queue = queue; 975 976 ring->ring_obj = NULL; 977 ring->use_doorbell = true; 978 979 if (!ring_id) 980 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 981 else 982 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 983 ring->vm_hub = AMDGPU_GFXHUB(0); 984 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 985 986 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 987 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 988 AMDGPU_RING_PRIO_DEFAULT, NULL); 989 if (r) 990 return r; 991 return 0; 992 } 993 994 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 995 int mec, int pipe, int queue) 996 { 997 int r; 998 unsigned irq_type; 999 struct amdgpu_ring *ring; 1000 unsigned int hw_prio; 1001 1002 ring = &adev->gfx.compute_ring[ring_id]; 1003 1004 /* mec0 is me1 */ 1005 ring->me = mec + 1; 1006 ring->pipe = pipe; 1007 ring->queue = queue; 1008 1009 ring->ring_obj = NULL; 1010 ring->use_doorbell = true; 1011 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1012 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1013 + (ring_id * GFX12_MEC_HPD_SIZE); 1014 ring->vm_hub = AMDGPU_GFXHUB(0); 1015 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1016 1017 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1018 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1019 + ring->pipe; 1020 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1021 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1022 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1023 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1024 hw_prio, NULL); 1025 if (r) 1026 return r; 1027 1028 return 0; 1029 } 1030 1031 static struct { 1032 SOC24_FIRMWARE_ID id; 1033 unsigned int offset; 1034 unsigned int size; 1035 unsigned int size_x16; 1036 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1037 1038 #define RLC_TOC_OFFSET_DWUNIT 8 1039 #define RLC_SIZE_MULTIPLE 1024 1040 #define RLC_TOC_UMF_SIZE_inM 23ULL 1041 #define RLC_TOC_FORMAT_API 165ULL 1042 1043 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1044 { 1045 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1046 1047 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1048 rlc_autoload_info[ucode->id].id = ucode->id; 1049 rlc_autoload_info[ucode->id].offset = 1050 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1051 rlc_autoload_info[ucode->id].size = 1052 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1053 ucode->size * 4; 1054 ucode++; 1055 } 1056 } 1057 1058 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1059 { 1060 uint32_t total_size = 0; 1061 SOC24_FIRMWARE_ID id; 1062 1063 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1064 1065 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1066 total_size += rlc_autoload_info[id].size; 1067 1068 /* In case the offset in rlc toc ucode is aligned */ 1069 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1070 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1071 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1072 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1073 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1074 1075 return total_size; 1076 } 1077 1078 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1079 { 1080 int r; 1081 uint32_t total_size; 1082 1083 total_size = gfx_v12_0_calc_toc_total_size(adev); 1084 1085 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1086 AMDGPU_GEM_DOMAIN_VRAM, 1087 &adev->gfx.rlc.rlc_autoload_bo, 1088 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1089 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1090 1091 if (r) { 1092 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1093 return r; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1100 SOC24_FIRMWARE_ID id, 1101 const void *fw_data, 1102 uint32_t fw_size) 1103 { 1104 uint32_t toc_offset; 1105 uint32_t toc_fw_size; 1106 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1107 1108 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1109 return; 1110 1111 toc_offset = rlc_autoload_info[id].offset; 1112 toc_fw_size = rlc_autoload_info[id].size; 1113 1114 if (fw_size == 0) 1115 fw_size = toc_fw_size; 1116 1117 if (fw_size > toc_fw_size) 1118 fw_size = toc_fw_size; 1119 1120 memcpy(ptr + toc_offset, fw_data, fw_size); 1121 1122 if (fw_size < toc_fw_size) 1123 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1124 } 1125 1126 static void 1127 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1128 { 1129 void *data; 1130 uint32_t size; 1131 uint32_t *toc_ptr; 1132 1133 data = adev->psp.toc.start_addr; 1134 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1135 1136 toc_ptr = (uint32_t *)data + size / 4 - 2; 1137 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1138 1139 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1140 data, size); 1141 } 1142 1143 static void 1144 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1145 { 1146 const __le32 *fw_data; 1147 uint32_t fw_size; 1148 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1149 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1150 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1151 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1152 uint16_t version_major, version_minor; 1153 1154 /* pfp ucode */ 1155 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1156 adev->gfx.pfp_fw->data; 1157 /* instruction */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1162 fw_data, fw_size); 1163 /* data */ 1164 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1165 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1166 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1168 fw_data, fw_size); 1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1170 fw_data, fw_size); 1171 /* me ucode */ 1172 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1173 adev->gfx.me_fw->data; 1174 /* instruction */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1179 fw_data, fw_size); 1180 /* data */ 1181 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1182 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1183 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1185 fw_data, fw_size); 1186 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1187 fw_data, fw_size); 1188 /* mec ucode */ 1189 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1190 adev->gfx.mec_fw->data; 1191 /* instruction */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1196 fw_data, fw_size); 1197 /* data */ 1198 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1199 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1200 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1202 fw_data, fw_size); 1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1204 fw_data, fw_size); 1205 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1206 fw_data, fw_size); 1207 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1208 fw_data, fw_size); 1209 1210 /* rlc ucode */ 1211 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1212 adev->gfx.rlc_fw->data; 1213 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1214 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1215 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1217 fw_data, fw_size); 1218 1219 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1220 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1221 if (version_major == 2) { 1222 if (version_minor >= 1) { 1223 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1229 fw_data, fw_size); 1230 1231 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1232 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1233 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1234 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1235 fw_data, fw_size); 1236 } 1237 if (version_minor >= 2) { 1238 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1244 fw_data, fw_size); 1245 1246 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1247 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1248 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1250 fw_data, fw_size); 1251 } 1252 } 1253 } 1254 1255 static void 1256 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1257 { 1258 const __le32 *fw_data; 1259 uint32_t fw_size; 1260 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1261 1262 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1263 adev->sdma.instance[0].fw->data; 1264 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1265 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1266 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1267 1268 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1269 fw_data, fw_size); 1270 } 1271 1272 static void 1273 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1274 { 1275 const __le32 *fw_data; 1276 unsigned fw_size; 1277 const struct mes_firmware_header_v1_0 *mes_hdr; 1278 int pipe, ucode_id, data_id; 1279 1280 for (pipe = 0; pipe < 2; pipe++) { 1281 if (pipe == 0) { 1282 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1283 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1284 } else { 1285 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1286 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1287 } 1288 1289 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1290 adev->mes.fw[pipe]->data; 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1297 1298 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1299 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1300 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1301 1302 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1303 } 1304 } 1305 1306 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1307 { 1308 uint32_t rlc_g_offset, rlc_g_size; 1309 uint64_t gpu_addr; 1310 uint32_t data; 1311 1312 /* RLC autoload sequence 2: copy ucode */ 1313 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1314 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1315 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1316 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1317 1318 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1319 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1320 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1321 1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1323 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1324 1325 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1326 1327 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1328 /* RLC autoload sequence 3: load IMU fw */ 1329 if (adev->gfx.imu.funcs->load_microcode) 1330 adev->gfx.imu.funcs->load_microcode(adev); 1331 /* RLC autoload sequence 4 init IMU fw */ 1332 if (adev->gfx.imu.funcs->setup_imu) 1333 adev->gfx.imu.funcs->setup_imu(adev); 1334 if (adev->gfx.imu.funcs->start_imu) 1335 adev->gfx.imu.funcs->start_imu(adev); 1336 1337 /* RLC autoload sequence 5 disable gpa mode */ 1338 gfx_v12_0_disable_gpa_mode(adev); 1339 } else { 1340 /* unhalt rlc to start autoload without imu */ 1341 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1342 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1343 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1344 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1345 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1346 } 1347 1348 return 0; 1349 } 1350 1351 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1352 { 1353 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1354 uint32_t *ptr; 1355 uint32_t inst; 1356 1357 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1358 if (!ptr) { 1359 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1360 adev->gfx.ip_dump_core = NULL; 1361 } else { 1362 adev->gfx.ip_dump_core = ptr; 1363 } 1364 1365 /* Allocate memory for compute queue registers for all the instances */ 1366 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1367 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1368 adev->gfx.mec.num_queue_per_pipe; 1369 1370 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1371 if (!ptr) { 1372 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1373 adev->gfx.ip_dump_compute_queues = NULL; 1374 } else { 1375 adev->gfx.ip_dump_compute_queues = ptr; 1376 } 1377 1378 /* Allocate memory for gfx queue registers for all the instances */ 1379 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1380 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1381 adev->gfx.me.num_queue_per_pipe; 1382 1383 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1384 if (!ptr) { 1385 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1386 adev->gfx.ip_dump_gfx_queues = NULL; 1387 } else { 1388 adev->gfx.ip_dump_gfx_queues = ptr; 1389 } 1390 } 1391 1392 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1393 { 1394 int i, j, k, r, ring_id = 0; 1395 unsigned num_compute_rings; 1396 int xcc_id = 0; 1397 struct amdgpu_device *adev = ip_block->adev; 1398 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1399 1400 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1401 1402 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1403 case IP_VERSION(12, 0, 0): 1404 case IP_VERSION(12, 0, 1): 1405 adev->gfx.me.num_me = 1; 1406 adev->gfx.me.num_pipe_per_me = 1; 1407 adev->gfx.me.num_queue_per_pipe = 8; 1408 adev->gfx.mec.num_mec = 1; 1409 adev->gfx.mec.num_pipe_per_mec = 2; 1410 adev->gfx.mec.num_queue_per_pipe = 4; 1411 break; 1412 default: 1413 adev->gfx.me.num_me = 1; 1414 adev->gfx.me.num_pipe_per_me = 1; 1415 adev->gfx.me.num_queue_per_pipe = 1; 1416 adev->gfx.mec.num_mec = 1; 1417 adev->gfx.mec.num_pipe_per_mec = 4; 1418 adev->gfx.mec.num_queue_per_pipe = 8; 1419 break; 1420 } 1421 1422 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1423 case IP_VERSION(12, 0, 0): 1424 case IP_VERSION(12, 0, 1): 1425 if (!adev->gfx.disable_uq && 1426 adev->gfx.me_fw_version >= 2780 && 1427 adev->gfx.pfp_fw_version >= 2840 && 1428 adev->gfx.mec_fw_version >= 3050 && 1429 adev->mes.fw_version[0] >= 123) { 1430 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1431 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1432 } 1433 break; 1434 default: 1435 break; 1436 } 1437 1438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1439 case IP_VERSION(12, 0, 0): 1440 case IP_VERSION(12, 0, 1): 1441 if (adev->gfx.me_fw_version >= 2480 && 1442 adev->gfx.pfp_fw_version >= 2530 && 1443 adev->gfx.mec_fw_version >= 2680 && 1444 adev->mes.fw_version[0] >= 100) 1445 adev->gfx.enable_cleaner_shader = true; 1446 break; 1447 default: 1448 adev->gfx.enable_cleaner_shader = false; 1449 break; 1450 } 1451 1452 if (adev->gfx.num_compute_rings) { 1453 /* recalculate compute rings to use based on hardware configuration */ 1454 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1455 adev->gfx.mec.num_queue_per_pipe) / 2; 1456 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1457 num_compute_rings); 1458 } 1459 1460 /* EOP Event */ 1461 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1462 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1463 &adev->gfx.eop_irq); 1464 if (r) 1465 return r; 1466 1467 /* Bad opcode Event */ 1468 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1469 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1470 &adev->gfx.bad_op_irq); 1471 if (r) 1472 return r; 1473 1474 /* Privileged reg */ 1475 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1476 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1477 &adev->gfx.priv_reg_irq); 1478 if (r) 1479 return r; 1480 1481 /* Privileged inst */ 1482 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1483 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1484 &adev->gfx.priv_inst_irq); 1485 if (r) 1486 return r; 1487 1488 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1489 1490 gfx_v12_0_me_init(adev); 1491 1492 r = gfx_v12_0_rlc_init(adev); 1493 if (r) { 1494 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1495 return r; 1496 } 1497 1498 r = gfx_v12_0_mec_init(adev); 1499 if (r) { 1500 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1501 return r; 1502 } 1503 1504 if (adev->gfx.num_gfx_rings) { 1505 /* set up the gfx ring */ 1506 for (i = 0; i < adev->gfx.me.num_me; i++) { 1507 for (j = 0; j < num_queue_per_pipe; j++) { 1508 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1509 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1510 continue; 1511 1512 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1513 i, k, j); 1514 if (r) 1515 return r; 1516 ring_id++; 1517 } 1518 } 1519 } 1520 } 1521 1522 if (adev->gfx.num_compute_rings) { 1523 ring_id = 0; 1524 /* set up the compute queues - allocate horizontally across pipes */ 1525 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1526 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1527 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1528 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1529 0, i, k, j)) 1530 continue; 1531 1532 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1533 i, k, j); 1534 if (r) 1535 return r; 1536 1537 ring_id++; 1538 } 1539 } 1540 } 1541 } 1542 1543 adev->gfx.gfx_supported_reset = 1544 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1545 adev->gfx.compute_supported_reset = 1546 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1547 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1548 case IP_VERSION(12, 0, 0): 1549 case IP_VERSION(12, 0, 1): 1550 if ((adev->gfx.me_fw_version >= 2660) && 1551 (adev->gfx.mec_fw_version >= 2920) && 1552 !amdgpu_sriov_vf(adev) && 1553 !adev->debug_disable_gpu_ring_reset) { 1554 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1555 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1556 } 1557 break; 1558 default: 1559 break; 1560 } 1561 1562 if (!adev->enable_mes_kiq) { 1563 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1564 if (r) { 1565 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1566 return r; 1567 } 1568 1569 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1570 if (r) 1571 return r; 1572 } 1573 1574 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1575 if (r) 1576 return r; 1577 1578 /* allocate visible FB for rlc auto-loading fw */ 1579 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1580 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1581 if (r) 1582 return r; 1583 } 1584 1585 r = gfx_v12_0_gpu_early_init(adev); 1586 if (r) 1587 return r; 1588 1589 gfx_v12_0_alloc_ip_dump(adev); 1590 1591 r = amdgpu_gfx_sysfs_init(adev); 1592 if (r) 1593 return r; 1594 1595 return 0; 1596 } 1597 1598 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1599 { 1600 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1601 &adev->gfx.pfp.pfp_fw_gpu_addr, 1602 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1603 1604 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1605 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1606 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1607 } 1608 1609 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1610 { 1611 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1612 &adev->gfx.me.me_fw_gpu_addr, 1613 (void **)&adev->gfx.me.me_fw_ptr); 1614 1615 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1616 &adev->gfx.me.me_fw_data_gpu_addr, 1617 (void **)&adev->gfx.me.me_fw_data_ptr); 1618 } 1619 1620 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1621 { 1622 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1623 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1624 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1625 } 1626 1627 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1628 { 1629 int i; 1630 struct amdgpu_device *adev = ip_block->adev; 1631 1632 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1633 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1634 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1635 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1636 1637 amdgpu_gfx_mqd_sw_fini(adev, 0); 1638 1639 if (!adev->enable_mes_kiq) { 1640 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1641 amdgpu_gfx_kiq_fini(adev, 0); 1642 } 1643 1644 gfx_v12_0_pfp_fini(adev); 1645 gfx_v12_0_me_fini(adev); 1646 gfx_v12_0_rlc_fini(adev); 1647 gfx_v12_0_mec_fini(adev); 1648 1649 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1650 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1651 1652 gfx_v12_0_free_microcode(adev); 1653 1654 amdgpu_gfx_sysfs_fini(adev); 1655 1656 kfree(adev->gfx.ip_dump_core); 1657 kfree(adev->gfx.ip_dump_compute_queues); 1658 kfree(adev->gfx.ip_dump_gfx_queues); 1659 1660 return 0; 1661 } 1662 1663 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1664 u32 sh_num, u32 instance, int xcc_id) 1665 { 1666 u32 data; 1667 1668 if (instance == 0xffffffff) 1669 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1670 INSTANCE_BROADCAST_WRITES, 1); 1671 else 1672 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1673 instance); 1674 1675 if (se_num == 0xffffffff) 1676 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1677 1); 1678 else 1679 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1680 1681 if (sh_num == 0xffffffff) 1682 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1683 1); 1684 else 1685 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1686 1687 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1688 } 1689 1690 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1691 { 1692 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1693 1694 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1695 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1696 GRBM_CC_GC_SA_UNIT_DISABLE, 1697 SA_DISABLE); 1698 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1699 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1700 GRBM_GC_USER_SA_UNIT_DISABLE, 1701 SA_DISABLE); 1702 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1703 adev->gfx.config.max_shader_engines); 1704 1705 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1706 } 1707 1708 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1709 { 1710 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1711 u32 rb_mask; 1712 1713 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1714 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1715 CC_RB_BACKEND_DISABLE, 1716 BACKEND_DISABLE); 1717 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1718 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1719 GC_USER_RB_BACKEND_DISABLE, 1720 BACKEND_DISABLE); 1721 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1722 adev->gfx.config.max_shader_engines); 1723 1724 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1725 } 1726 1727 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1728 { 1729 u32 rb_bitmap_per_sa; 1730 u32 rb_bitmap_width_per_sa; 1731 u32 max_sa; 1732 u32 active_sa_bitmap; 1733 u32 global_active_rb_bitmap; 1734 u32 active_rb_bitmap = 0; 1735 u32 i; 1736 1737 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1738 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1739 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1740 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1741 1742 /* generate active rb bitmap according to active sa bitmap */ 1743 max_sa = adev->gfx.config.max_shader_engines * 1744 adev->gfx.config.max_sh_per_se; 1745 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1746 adev->gfx.config.max_sh_per_se; 1747 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1748 1749 for (i = 0; i < max_sa; i++) { 1750 if (active_sa_bitmap & (1 << i)) 1751 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1752 } 1753 1754 active_rb_bitmap &= global_active_rb_bitmap; 1755 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1756 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1757 } 1758 1759 #define LDS_APP_BASE 0x1 1760 #define SCRATCH_APP_BASE 0x2 1761 1762 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1763 { 1764 int i; 1765 uint32_t sh_mem_bases; 1766 uint32_t data; 1767 1768 /* 1769 * Configure apertures: 1770 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1771 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1772 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1773 */ 1774 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1775 SCRATCH_APP_BASE; 1776 1777 mutex_lock(&adev->srbm_mutex); 1778 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1779 soc24_grbm_select(adev, 0, 0, 0, i); 1780 /* CP and shaders */ 1781 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1782 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1783 1784 /* Enable trap for each kfd vmid. */ 1785 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1786 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1787 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1788 } 1789 soc24_grbm_select(adev, 0, 0, 0, 0); 1790 mutex_unlock(&adev->srbm_mutex); 1791 } 1792 1793 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1794 { 1795 /* TODO: harvest feature to be added later. */ 1796 } 1797 1798 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1799 { 1800 } 1801 1802 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1803 { 1804 u32 tmp; 1805 int i; 1806 1807 if (!amdgpu_sriov_vf(adev)) 1808 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1809 1810 gfx_v12_0_setup_rb(adev); 1811 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1812 gfx_v12_0_get_tcc_info(adev); 1813 adev->gfx.config.pa_sc_tile_steering_override = 0; 1814 1815 /* XXX SH_MEM regs */ 1816 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1817 mutex_lock(&adev->srbm_mutex); 1818 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1819 soc24_grbm_select(adev, 0, 0, 0, i); 1820 /* CP and shaders */ 1821 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1822 if (i != 0) { 1823 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1824 (adev->gmc.private_aperture_start >> 48)); 1825 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1826 (adev->gmc.shared_aperture_start >> 48)); 1827 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1828 } 1829 } 1830 soc24_grbm_select(adev, 0, 0, 0, 0); 1831 1832 mutex_unlock(&adev->srbm_mutex); 1833 1834 gfx_v12_0_init_compute_vmid(adev); 1835 } 1836 1837 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1838 int me, int pipe) 1839 { 1840 if (me != 0) 1841 return 0; 1842 1843 switch (pipe) { 1844 case 0: 1845 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1846 default: 1847 return 0; 1848 } 1849 } 1850 1851 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1852 int me, int pipe) 1853 { 1854 /* 1855 * amdgpu controls only the first MEC. That's why this function only 1856 * handles the setting of interrupts for this specific MEC. All other 1857 * pipes' interrupts are set by amdkfd. 1858 */ 1859 if (me != 1) 1860 return 0; 1861 1862 switch (pipe) { 1863 case 0: 1864 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1865 case 1: 1866 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1867 default: 1868 return 0; 1869 } 1870 } 1871 1872 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1873 bool enable) 1874 { 1875 u32 tmp, cp_int_cntl_reg; 1876 int i, j; 1877 1878 if (amdgpu_sriov_vf(adev)) 1879 return; 1880 1881 for (i = 0; i < adev->gfx.me.num_me; i++) { 1882 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1883 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1884 1885 if (cp_int_cntl_reg) { 1886 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1887 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1888 enable ? 1 : 0); 1889 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1890 enable ? 1 : 0); 1891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1892 enable ? 1 : 0); 1893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1894 enable ? 1 : 0); 1895 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1896 } 1897 } 1898 } 1899 } 1900 1901 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1902 { 1903 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1904 1905 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1906 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1907 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1908 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1909 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1910 1911 return 0; 1912 } 1913 1914 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1915 { 1916 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1917 1918 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1919 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1920 } 1921 1922 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1923 { 1924 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1925 udelay(50); 1926 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1927 udelay(50); 1928 } 1929 1930 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1931 bool enable) 1932 { 1933 uint32_t rlc_pg_cntl; 1934 1935 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1936 1937 if (!enable) { 1938 /* RLC_PG_CNTL[23] = 0 (default) 1939 * RLC will wait for handshake acks with SMU 1940 * GFXOFF will be enabled 1941 * RLC_PG_CNTL[23] = 1 1942 * RLC will not issue any message to SMU 1943 * hence no handshake between SMU & RLC 1944 * GFXOFF will be disabled 1945 */ 1946 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1947 } else 1948 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1949 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1950 } 1951 1952 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1953 { 1954 /* TODO: enable rlc & smu handshake until smu 1955 * and gfxoff feature works as expected */ 1956 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1957 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1958 1959 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1960 udelay(50); 1961 } 1962 1963 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1964 { 1965 uint32_t tmp; 1966 1967 /* enable Save Restore Machine */ 1968 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1969 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1970 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1971 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1972 } 1973 1974 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1975 { 1976 const struct rlc_firmware_header_v2_0 *hdr; 1977 const __le32 *fw_data; 1978 unsigned i, fw_size; 1979 1980 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1981 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1982 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1983 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1984 1985 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1986 RLCG_UCODE_LOADING_START_ADDRESS); 1987 1988 for (i = 0; i < fw_size; i++) 1989 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1990 le32_to_cpup(fw_data++)); 1991 1992 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1993 } 1994 1995 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1996 { 1997 const struct rlc_firmware_header_v2_2 *hdr; 1998 const __le32 *fw_data; 1999 unsigned i, fw_size; 2000 u32 tmp; 2001 2002 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2003 2004 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2005 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2006 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2007 2008 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2009 2010 for (i = 0; i < fw_size; i++) { 2011 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2012 msleep(1); 2013 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2014 le32_to_cpup(fw_data++)); 2015 } 2016 2017 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2018 2019 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2020 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2021 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2022 2023 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2024 for (i = 0; i < fw_size; i++) { 2025 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2026 msleep(1); 2027 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2028 le32_to_cpup(fw_data++)); 2029 } 2030 2031 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2032 2033 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2034 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2035 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2036 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2037 } 2038 2039 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2040 { 2041 const struct rlc_firmware_header_v2_0 *hdr; 2042 uint16_t version_major; 2043 uint16_t version_minor; 2044 2045 if (!adev->gfx.rlc_fw) 2046 return -EINVAL; 2047 2048 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2049 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2050 2051 version_major = le16_to_cpu(hdr->header.header_version_major); 2052 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2053 2054 if (version_major == 2) { 2055 gfx_v12_0_load_rlcg_microcode(adev); 2056 if (amdgpu_dpm == 1) { 2057 if (version_minor >= 2) 2058 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2059 } 2060 2061 return 0; 2062 } 2063 2064 return -EINVAL; 2065 } 2066 2067 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2068 { 2069 int r; 2070 2071 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2072 gfx_v12_0_init_csb(adev); 2073 2074 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2075 gfx_v12_0_rlc_enable_srm(adev); 2076 } else { 2077 if (amdgpu_sriov_vf(adev)) { 2078 gfx_v12_0_init_csb(adev); 2079 return 0; 2080 } 2081 2082 adev->gfx.rlc.funcs->stop(adev); 2083 2084 /* disable CG */ 2085 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2086 2087 /* disable PG */ 2088 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2089 2090 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2091 /* legacy rlc firmware loading */ 2092 r = gfx_v12_0_rlc_load_microcode(adev); 2093 if (r) 2094 return r; 2095 } 2096 2097 gfx_v12_0_init_csb(adev); 2098 2099 adev->gfx.rlc.funcs->start(adev); 2100 } 2101 2102 return 0; 2103 } 2104 2105 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2106 { 2107 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2108 const struct gfx_firmware_header_v2_0 *me_hdr; 2109 const struct gfx_firmware_header_v2_0 *mec_hdr; 2110 uint32_t pipe_id, tmp; 2111 2112 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2113 adev->gfx.mec_fw->data; 2114 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2115 adev->gfx.me_fw->data; 2116 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2117 adev->gfx.pfp_fw->data; 2118 2119 /* config pfp program start addr */ 2120 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2121 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2122 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2123 (pfp_hdr->ucode_start_addr_hi << 30) | 2124 (pfp_hdr->ucode_start_addr_lo >> 2)); 2125 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2126 pfp_hdr->ucode_start_addr_hi >> 2); 2127 } 2128 soc24_grbm_select(adev, 0, 0, 0, 0); 2129 2130 /* reset pfp pipe */ 2131 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2133 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2134 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2135 2136 /* clear pfp pipe reset */ 2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2139 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2140 2141 /* config me program start addr */ 2142 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2143 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2144 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2145 (me_hdr->ucode_start_addr_hi << 30) | 2146 (me_hdr->ucode_start_addr_lo >> 2)); 2147 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2148 me_hdr->ucode_start_addr_hi>>2); 2149 } 2150 soc24_grbm_select(adev, 0, 0, 0, 0); 2151 2152 /* reset me pipe */ 2153 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2155 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2156 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2157 2158 /* clear me pipe reset */ 2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2160 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2161 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2162 2163 /* config mec program start addr */ 2164 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2165 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2166 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2167 mec_hdr->ucode_start_addr_lo >> 2 | 2168 mec_hdr->ucode_start_addr_hi << 30); 2169 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2170 mec_hdr->ucode_start_addr_hi >> 2); 2171 } 2172 soc24_grbm_select(adev, 0, 0, 0, 0); 2173 2174 /* reset mec pipe */ 2175 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2178 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2179 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2180 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2181 2182 /* clear mec pipe reset */ 2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2184 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2185 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2186 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2187 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2188 } 2189 2190 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2191 { 2192 const struct gfx_firmware_header_v2_0 *cp_hdr; 2193 unsigned pipe_id, tmp; 2194 2195 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2196 adev->gfx.pfp_fw->data; 2197 mutex_lock(&adev->srbm_mutex); 2198 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2199 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2200 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2201 (cp_hdr->ucode_start_addr_hi << 30) | 2202 (cp_hdr->ucode_start_addr_lo >> 2)); 2203 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2204 cp_hdr->ucode_start_addr_hi>>2); 2205 2206 /* 2207 * Program CP_ME_CNTL to reset given PIPE to take 2208 * effect of CP_PFP_PRGRM_CNTR_START. 2209 */ 2210 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2211 if (pipe_id == 0) 2212 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2213 PFP_PIPE0_RESET, 1); 2214 else 2215 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2216 PFP_PIPE1_RESET, 1); 2217 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2218 2219 /* Clear pfp pipe0 reset bit. */ 2220 if (pipe_id == 0) 2221 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2222 PFP_PIPE0_RESET, 0); 2223 else 2224 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2225 PFP_PIPE1_RESET, 0); 2226 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2227 } 2228 soc24_grbm_select(adev, 0, 0, 0, 0); 2229 mutex_unlock(&adev->srbm_mutex); 2230 } 2231 2232 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2233 { 2234 const struct gfx_firmware_header_v2_0 *cp_hdr; 2235 unsigned pipe_id, tmp; 2236 2237 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2238 adev->gfx.me_fw->data; 2239 mutex_lock(&adev->srbm_mutex); 2240 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2241 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2242 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2243 (cp_hdr->ucode_start_addr_hi << 30) | 2244 (cp_hdr->ucode_start_addr_lo >> 2) ); 2245 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2246 cp_hdr->ucode_start_addr_hi>>2); 2247 2248 /* 2249 * Program CP_ME_CNTL to reset given PIPE to take 2250 * effect of CP_ME_PRGRM_CNTR_START. 2251 */ 2252 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2253 if (pipe_id == 0) 2254 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2255 ME_PIPE0_RESET, 1); 2256 else 2257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2258 ME_PIPE1_RESET, 1); 2259 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2260 2261 /* Clear pfp pipe0 reset bit. */ 2262 if (pipe_id == 0) 2263 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2264 ME_PIPE0_RESET, 0); 2265 else 2266 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2267 ME_PIPE1_RESET, 0); 2268 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2269 } 2270 soc24_grbm_select(adev, 0, 0, 0, 0); 2271 mutex_unlock(&adev->srbm_mutex); 2272 } 2273 2274 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2275 { 2276 const struct gfx_firmware_header_v2_0 *cp_hdr; 2277 unsigned pipe_id; 2278 2279 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2280 adev->gfx.mec_fw->data; 2281 mutex_lock(&adev->srbm_mutex); 2282 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2283 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2284 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2285 cp_hdr->ucode_start_addr_lo >> 2 | 2286 cp_hdr->ucode_start_addr_hi << 30); 2287 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2288 cp_hdr->ucode_start_addr_hi >> 2); 2289 } 2290 soc24_grbm_select(adev, 0, 0, 0, 0); 2291 mutex_unlock(&adev->srbm_mutex); 2292 } 2293 2294 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2295 { 2296 uint32_t cp_status; 2297 uint32_t bootload_status; 2298 int i; 2299 2300 for (i = 0; i < adev->usec_timeout; i++) { 2301 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2302 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2303 2304 if ((cp_status == 0) && 2305 (REG_GET_FIELD(bootload_status, 2306 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2307 break; 2308 } 2309 udelay(1); 2310 if (amdgpu_emu_mode) 2311 msleep(10); 2312 } 2313 2314 if (i >= adev->usec_timeout) { 2315 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2316 return -ETIMEDOUT; 2317 } 2318 2319 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2320 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2321 gfx_v12_0_set_me_ucode_start_addr(adev); 2322 gfx_v12_0_set_mec_ucode_start_addr(adev); 2323 } 2324 2325 return 0; 2326 } 2327 2328 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2329 { 2330 int i; 2331 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2332 2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2334 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2335 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2336 2337 for (i = 0; i < adev->usec_timeout; i++) { 2338 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2339 break; 2340 udelay(1); 2341 } 2342 2343 if (i >= adev->usec_timeout) 2344 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2345 2346 return 0; 2347 } 2348 2349 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2350 { 2351 int r; 2352 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2353 const __le32 *fw_ucode, *fw_data; 2354 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2355 uint32_t tmp; 2356 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2357 2358 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2359 adev->gfx.pfp_fw->data; 2360 2361 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2362 2363 /* instruction */ 2364 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2365 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2366 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2367 /* data */ 2368 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2369 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2370 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2371 2372 /* 64kb align */ 2373 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2374 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2375 &adev->gfx.pfp.pfp_fw_obj, 2376 &adev->gfx.pfp.pfp_fw_gpu_addr, 2377 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2378 if (r) { 2379 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2380 gfx_v12_0_pfp_fini(adev); 2381 return r; 2382 } 2383 2384 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2385 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2386 &adev->gfx.pfp.pfp_fw_data_obj, 2387 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2388 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2389 if (r) { 2390 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2391 gfx_v12_0_pfp_fini(adev); 2392 return r; 2393 } 2394 2395 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2396 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2397 2398 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2399 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2400 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2401 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2402 2403 if (amdgpu_emu_mode == 1) 2404 amdgpu_device_flush_hdp(adev, NULL); 2405 2406 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2407 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2408 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2409 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2410 2411 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2412 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2413 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2414 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2415 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2416 2417 /* 2418 * Programming any of the CP_PFP_IC_BASE registers 2419 * forces invalidation of the ME L1 I$. Wait for the 2420 * invalidation complete 2421 */ 2422 for (i = 0; i < usec_timeout; i++) { 2423 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2424 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2425 INVALIDATE_CACHE_COMPLETE)) 2426 break; 2427 udelay(1); 2428 } 2429 2430 if (i >= usec_timeout) { 2431 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2432 return -EINVAL; 2433 } 2434 2435 /* Prime the L1 instruction caches */ 2436 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2437 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2438 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2439 /* Waiting for cache primed*/ 2440 for (i = 0; i < usec_timeout; i++) { 2441 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2442 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2443 ICACHE_PRIMED)) 2444 break; 2445 udelay(1); 2446 } 2447 2448 if (i >= usec_timeout) { 2449 dev_err(adev->dev, "failed to prime instruction cache\n"); 2450 return -EINVAL; 2451 } 2452 2453 mutex_lock(&adev->srbm_mutex); 2454 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2455 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2456 2457 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2458 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2459 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2460 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2461 } 2462 soc24_grbm_select(adev, 0, 0, 0, 0); 2463 mutex_unlock(&adev->srbm_mutex); 2464 2465 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2466 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2467 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2468 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2469 2470 /* Invalidate the data caches */ 2471 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2472 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2473 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2474 2475 for (i = 0; i < usec_timeout; i++) { 2476 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2477 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2478 INVALIDATE_DCACHE_COMPLETE)) 2479 break; 2480 udelay(1); 2481 } 2482 2483 if (i >= usec_timeout) { 2484 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2485 return -EINVAL; 2486 } 2487 2488 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2489 2490 return 0; 2491 } 2492 2493 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2494 { 2495 int r; 2496 const struct gfx_firmware_header_v2_0 *me_hdr; 2497 const __le32 *fw_ucode, *fw_data; 2498 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2499 uint32_t tmp; 2500 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2501 2502 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2503 adev->gfx.me_fw->data; 2504 2505 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2506 2507 /* instruction */ 2508 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2509 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2510 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2511 /* data */ 2512 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2513 le32_to_cpu(me_hdr->data_offset_bytes)); 2514 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2515 2516 /* 64kb align*/ 2517 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2518 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2519 &adev->gfx.me.me_fw_obj, 2520 &adev->gfx.me.me_fw_gpu_addr, 2521 (void **)&adev->gfx.me.me_fw_ptr); 2522 if (r) { 2523 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2524 gfx_v12_0_me_fini(adev); 2525 return r; 2526 } 2527 2528 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2529 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2530 &adev->gfx.me.me_fw_data_obj, 2531 &adev->gfx.me.me_fw_data_gpu_addr, 2532 (void **)&adev->gfx.me.me_fw_data_ptr); 2533 if (r) { 2534 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2535 gfx_v12_0_me_fini(adev); 2536 return r; 2537 } 2538 2539 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2540 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2541 2542 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2543 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2544 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2545 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2546 2547 if (amdgpu_emu_mode == 1) 2548 amdgpu_device_flush_hdp(adev, NULL); 2549 2550 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2551 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2552 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2553 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2554 2555 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2557 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2558 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2559 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2560 2561 /* 2562 * Programming any of the CP_ME_IC_BASE registers 2563 * forces invalidation of the ME L1 I$. Wait for the 2564 * invalidation complete 2565 */ 2566 for (i = 0; i < usec_timeout; i++) { 2567 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2568 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2569 INVALIDATE_CACHE_COMPLETE)) 2570 break; 2571 udelay(1); 2572 } 2573 2574 if (i >= usec_timeout) { 2575 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2576 return -EINVAL; 2577 } 2578 2579 /* Prime the instruction caches */ 2580 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2581 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2582 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2583 2584 /* Waiting for instruction cache primed*/ 2585 for (i = 0; i < usec_timeout; i++) { 2586 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2587 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2588 ICACHE_PRIMED)) 2589 break; 2590 udelay(1); 2591 } 2592 2593 if (i >= usec_timeout) { 2594 dev_err(adev->dev, "failed to prime instruction cache\n"); 2595 return -EINVAL; 2596 } 2597 2598 mutex_lock(&adev->srbm_mutex); 2599 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2600 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2601 2602 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2603 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2604 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2605 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2606 } 2607 soc24_grbm_select(adev, 0, 0, 0, 0); 2608 mutex_unlock(&adev->srbm_mutex); 2609 2610 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2611 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2612 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2613 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2614 2615 /* Invalidate the data caches */ 2616 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2617 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2618 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2619 2620 for (i = 0; i < usec_timeout; i++) { 2621 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2622 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2623 INVALIDATE_DCACHE_COMPLETE)) 2624 break; 2625 udelay(1); 2626 } 2627 2628 if (i >= usec_timeout) { 2629 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2630 return -EINVAL; 2631 } 2632 2633 gfx_v12_0_set_me_ucode_start_addr(adev); 2634 2635 return 0; 2636 } 2637 2638 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2639 { 2640 int r; 2641 2642 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2643 return -EINVAL; 2644 2645 gfx_v12_0_cp_gfx_enable(adev, false); 2646 2647 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2648 if (r) { 2649 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2650 return r; 2651 } 2652 2653 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2654 if (r) { 2655 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2656 return r; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2663 { 2664 /* init the CP */ 2665 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2666 adev->gfx.config.max_hw_contexts - 1); 2667 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2668 2669 if (!amdgpu_async_gfx_ring) 2670 gfx_v12_0_cp_gfx_enable(adev, true); 2671 2672 return 0; 2673 } 2674 2675 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2676 CP_PIPE_ID pipe) 2677 { 2678 u32 tmp; 2679 2680 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2681 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2682 2683 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2684 } 2685 2686 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2687 struct amdgpu_ring *ring) 2688 { 2689 u32 tmp; 2690 2691 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2692 if (ring->use_doorbell) { 2693 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2694 DOORBELL_OFFSET, ring->doorbell_index); 2695 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2696 DOORBELL_EN, 1); 2697 } else { 2698 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2699 DOORBELL_EN, 0); 2700 } 2701 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2702 2703 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2704 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2705 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2706 2707 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2708 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2709 } 2710 2711 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2712 { 2713 struct amdgpu_ring *ring; 2714 u32 tmp; 2715 u32 rb_bufsz; 2716 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2717 2718 /* Set the write pointer delay */ 2719 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2720 2721 /* set the RB to use vmid 0 */ 2722 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2723 2724 /* Init gfx ring 0 for pipe 0 */ 2725 mutex_lock(&adev->srbm_mutex); 2726 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2727 2728 /* Set ring buffer size */ 2729 ring = &adev->gfx.gfx_ring[0]; 2730 rb_bufsz = order_base_2(ring->ring_size / 8); 2731 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2732 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2733 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2734 2735 /* Initialize the ring buffer's write pointers */ 2736 ring->wptr = 0; 2737 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2738 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2739 2740 /* set the wb address whether it's enabled or not */ 2741 rptr_addr = ring->rptr_gpu_addr; 2742 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2743 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2744 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2745 2746 wptr_gpu_addr = ring->wptr_gpu_addr; 2747 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2748 lower_32_bits(wptr_gpu_addr)); 2749 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2750 upper_32_bits(wptr_gpu_addr)); 2751 2752 mdelay(1); 2753 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2754 2755 rb_addr = ring->gpu_addr >> 8; 2756 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2757 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2758 2759 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2760 2761 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2762 mutex_unlock(&adev->srbm_mutex); 2763 2764 /* Switch to pipe 0 */ 2765 mutex_lock(&adev->srbm_mutex); 2766 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2767 mutex_unlock(&adev->srbm_mutex); 2768 2769 /* start the ring */ 2770 gfx_v12_0_cp_gfx_start(adev); 2771 return 0; 2772 } 2773 2774 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2775 { 2776 u32 data; 2777 2778 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2779 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2780 enable ? 0 : 1); 2781 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2782 enable ? 0 : 1); 2783 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2784 enable ? 0 : 1); 2785 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2786 enable ? 0 : 1); 2787 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2788 enable ? 0 : 1); 2789 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2790 enable ? 1 : 0); 2791 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2792 enable ? 1 : 0); 2793 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2794 enable ? 1 : 0); 2795 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2796 enable ? 1 : 0); 2797 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2798 enable ? 0 : 1); 2799 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2800 2801 adev->gfx.kiq[0].ring.sched.ready = enable; 2802 2803 udelay(50); 2804 } 2805 2806 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2807 { 2808 const struct gfx_firmware_header_v2_0 *mec_hdr; 2809 const __le32 *fw_ucode, *fw_data; 2810 u32 tmp, fw_ucode_size, fw_data_size; 2811 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2812 u32 *fw_ucode_ptr, *fw_data_ptr; 2813 int r; 2814 2815 if (!adev->gfx.mec_fw) 2816 return -EINVAL; 2817 2818 gfx_v12_0_cp_compute_enable(adev, false); 2819 2820 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2821 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2822 2823 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2824 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2825 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2826 2827 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2828 le32_to_cpu(mec_hdr->data_offset_bytes)); 2829 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2830 2831 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2832 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2833 &adev->gfx.mec.mec_fw_obj, 2834 &adev->gfx.mec.mec_fw_gpu_addr, 2835 (void **)&fw_ucode_ptr); 2836 if (r) { 2837 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2838 gfx_v12_0_mec_fini(adev); 2839 return r; 2840 } 2841 2842 r = amdgpu_bo_create_reserved(adev, 2843 ALIGN(fw_data_size, 64 * 1024) * 2844 adev->gfx.mec.num_pipe_per_mec, 2845 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2846 &adev->gfx.mec.mec_fw_data_obj, 2847 &adev->gfx.mec.mec_fw_data_gpu_addr, 2848 (void **)&fw_data_ptr); 2849 if (r) { 2850 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2851 gfx_v12_0_mec_fini(adev); 2852 return r; 2853 } 2854 2855 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2856 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2857 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2858 } 2859 2860 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2861 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2862 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2863 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2864 2865 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2866 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2867 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2868 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2869 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2870 2871 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2872 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2873 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2874 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2875 2876 mutex_lock(&adev->srbm_mutex); 2877 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2878 soc24_grbm_select(adev, 1, i, 0, 0); 2879 2880 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2881 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2882 i * ALIGN(fw_data_size, 64 * 1024))); 2883 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2884 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2885 i * ALIGN(fw_data_size, 64 * 1024))); 2886 2887 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2888 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2889 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2890 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2891 } 2892 mutex_unlock(&adev->srbm_mutex); 2893 soc24_grbm_select(adev, 0, 0, 0, 0); 2894 2895 /* Trigger an invalidation of the L1 instruction caches */ 2896 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2897 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2898 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2899 2900 /* Wait for invalidation complete */ 2901 for (i = 0; i < usec_timeout; i++) { 2902 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2903 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2904 INVALIDATE_DCACHE_COMPLETE)) 2905 break; 2906 udelay(1); 2907 } 2908 2909 if (i >= usec_timeout) { 2910 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2911 return -EINVAL; 2912 } 2913 2914 /* Trigger an invalidation of the L1 instruction caches */ 2915 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2916 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2917 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2918 2919 /* Wait for invalidation complete */ 2920 for (i = 0; i < usec_timeout; i++) { 2921 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2922 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2923 INVALIDATE_CACHE_COMPLETE)) 2924 break; 2925 udelay(1); 2926 } 2927 2928 if (i >= usec_timeout) { 2929 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2930 return -EINVAL; 2931 } 2932 2933 gfx_v12_0_set_mec_ucode_start_addr(adev); 2934 2935 return 0; 2936 } 2937 2938 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2939 { 2940 uint32_t tmp; 2941 struct amdgpu_device *adev = ring->adev; 2942 2943 /* tell RLC which is KIQ queue */ 2944 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2945 tmp &= 0xffffff00; 2946 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2947 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2948 } 2949 2950 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2951 { 2952 /* set graphics engine doorbell range */ 2953 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2954 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2955 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2956 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2957 2958 /* set compute engine doorbell range */ 2959 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2960 (adev->doorbell_index.kiq * 2) << 2); 2961 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2962 (adev->doorbell_index.userqueue_end * 2) << 2); 2963 } 2964 2965 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2966 struct amdgpu_mqd_prop *prop) 2967 { 2968 struct v12_gfx_mqd *mqd = m; 2969 uint64_t hqd_gpu_addr, wb_gpu_addr; 2970 uint32_t tmp; 2971 uint32_t rb_bufsz; 2972 2973 /* set up gfx hqd wptr */ 2974 mqd->cp_gfx_hqd_wptr = 0; 2975 mqd->cp_gfx_hqd_wptr_hi = 0; 2976 2977 /* set the pointer to the MQD */ 2978 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2979 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2980 2981 /* set up mqd control */ 2982 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2983 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2984 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2985 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2986 mqd->cp_gfx_mqd_control = tmp; 2987 2988 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2989 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2990 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2991 mqd->cp_gfx_hqd_vmid = 0; 2992 2993 /* set up default queue priority level 2994 * 0x0 = low priority, 0x1 = high priority */ 2995 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2996 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2997 mqd->cp_gfx_hqd_queue_priority = tmp; 2998 2999 /* set up time quantum */ 3000 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3001 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3002 mqd->cp_gfx_hqd_quantum = tmp; 3003 3004 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3005 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3006 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3007 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3008 3009 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3010 wb_gpu_addr = prop->rptr_gpu_addr; 3011 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3012 mqd->cp_gfx_hqd_rptr_addr_hi = 3013 upper_32_bits(wb_gpu_addr) & 0xffff; 3014 3015 /* set up rb_wptr_poll addr */ 3016 wb_gpu_addr = prop->wptr_gpu_addr; 3017 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3018 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3019 3020 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3021 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3022 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3023 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3024 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3025 #ifdef __BIG_ENDIAN 3026 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3027 #endif 3028 if (prop->tmz_queue) 3029 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3030 if (!prop->kernel_queue) 3031 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3032 mqd->cp_gfx_hqd_cntl = tmp; 3033 3034 /* set up cp_doorbell_control */ 3035 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3036 if (prop->use_doorbell) { 3037 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3038 DOORBELL_OFFSET, prop->doorbell_index); 3039 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3040 DOORBELL_EN, 1); 3041 } else 3042 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3043 DOORBELL_EN, 0); 3044 mqd->cp_rb_doorbell_control = tmp; 3045 3046 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3047 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3048 3049 /* active the queue */ 3050 mqd->cp_gfx_hqd_active = 1; 3051 3052 /* set gfx UQ items */ 3053 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3054 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3055 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3056 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3057 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3058 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3059 3060 return 0; 3061 } 3062 3063 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3064 { 3065 struct amdgpu_device *adev = ring->adev; 3066 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3067 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3068 3069 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3070 memset((void *)mqd, 0, sizeof(*mqd)); 3071 mutex_lock(&adev->srbm_mutex); 3072 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3073 amdgpu_ring_init_mqd(ring); 3074 soc24_grbm_select(adev, 0, 0, 0, 0); 3075 mutex_unlock(&adev->srbm_mutex); 3076 if (adev->gfx.me.mqd_backup[mqd_idx]) 3077 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3078 } else { 3079 /* restore mqd with the backup copy */ 3080 if (adev->gfx.me.mqd_backup[mqd_idx]) 3081 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3082 /* reset the ring */ 3083 ring->wptr = 0; 3084 *ring->wptr_cpu_addr = 0; 3085 amdgpu_ring_clear_ring(ring); 3086 } 3087 3088 return 0; 3089 } 3090 3091 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3092 { 3093 int i, r; 3094 3095 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3096 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3097 if (r) 3098 return r; 3099 } 3100 3101 r = amdgpu_gfx_enable_kgq(adev, 0); 3102 if (r) 3103 return r; 3104 3105 return gfx_v12_0_cp_gfx_start(adev); 3106 } 3107 3108 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3109 struct amdgpu_mqd_prop *prop) 3110 { 3111 struct v12_compute_mqd *mqd = m; 3112 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3113 uint32_t tmp; 3114 3115 mqd->header = 0xC0310800; 3116 mqd->compute_pipelinestat_enable = 0x00000001; 3117 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3118 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3119 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3120 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3121 mqd->compute_misc_reserved = 0x00000007; 3122 3123 eop_base_addr = prop->eop_gpu_addr >> 8; 3124 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3125 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3126 3127 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3128 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3130 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3131 3132 mqd->cp_hqd_eop_control = tmp; 3133 3134 /* enable doorbell? */ 3135 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3136 3137 if (prop->use_doorbell) { 3138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3139 DOORBELL_OFFSET, prop->doorbell_index); 3140 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3141 DOORBELL_EN, 1); 3142 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3143 DOORBELL_SOURCE, 0); 3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3145 DOORBELL_HIT, 0); 3146 } else { 3147 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3148 DOORBELL_EN, 0); 3149 } 3150 3151 mqd->cp_hqd_pq_doorbell_control = tmp; 3152 3153 /* disable the queue if it's active */ 3154 mqd->cp_hqd_dequeue_request = 0; 3155 mqd->cp_hqd_pq_rptr = 0; 3156 mqd->cp_hqd_pq_wptr_lo = 0; 3157 mqd->cp_hqd_pq_wptr_hi = 0; 3158 3159 /* set the pointer to the MQD */ 3160 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3161 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3162 3163 /* set MQD vmid to 0 */ 3164 tmp = regCP_MQD_CONTROL_DEFAULT; 3165 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3166 mqd->cp_mqd_control = tmp; 3167 3168 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3169 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3170 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3171 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3172 3173 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3174 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3176 (order_base_2(prop->queue_size / 4) - 1)); 3177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3178 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3181 if (prop->kernel_queue) { 3182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3184 } 3185 if (prop->tmz_queue) 3186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3187 mqd->cp_hqd_pq_control = tmp; 3188 3189 /* set the wb address whether it's enabled or not */ 3190 wb_gpu_addr = prop->rptr_gpu_addr; 3191 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3192 mqd->cp_hqd_pq_rptr_report_addr_hi = 3193 upper_32_bits(wb_gpu_addr) & 0xffff; 3194 3195 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3196 wb_gpu_addr = prop->wptr_gpu_addr; 3197 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3198 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3199 3200 tmp = 0; 3201 /* enable the doorbell if requested */ 3202 if (prop->use_doorbell) { 3203 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3204 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3205 DOORBELL_OFFSET, prop->doorbell_index); 3206 3207 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3208 DOORBELL_EN, 1); 3209 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3210 DOORBELL_SOURCE, 0); 3211 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3212 DOORBELL_HIT, 0); 3213 } 3214 3215 mqd->cp_hqd_pq_doorbell_control = tmp; 3216 3217 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3218 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3219 3220 /* set the vmid for the queue */ 3221 mqd->cp_hqd_vmid = 0; 3222 3223 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3224 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3225 mqd->cp_hqd_persistent_state = tmp; 3226 3227 /* set MIN_IB_AVAIL_SIZE */ 3228 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3229 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3230 mqd->cp_hqd_ib_control = tmp; 3231 3232 /* set static priority for a compute queue/ring */ 3233 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3234 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3235 3236 mqd->cp_hqd_active = prop->hqd_active; 3237 3238 /* set UQ fenceaddress */ 3239 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3240 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3241 3242 return 0; 3243 } 3244 3245 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3246 { 3247 struct amdgpu_device *adev = ring->adev; 3248 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3249 int j; 3250 3251 /* inactivate the queue */ 3252 if (amdgpu_sriov_vf(adev)) 3253 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3254 3255 /* disable wptr polling */ 3256 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3257 3258 /* write the EOP addr */ 3259 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3260 mqd->cp_hqd_eop_base_addr_lo); 3261 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3262 mqd->cp_hqd_eop_base_addr_hi); 3263 3264 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3265 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3266 mqd->cp_hqd_eop_control); 3267 3268 /* enable doorbell? */ 3269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3270 mqd->cp_hqd_pq_doorbell_control); 3271 3272 /* disable the queue if it's active */ 3273 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3274 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3275 for (j = 0; j < adev->usec_timeout; j++) { 3276 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3277 break; 3278 udelay(1); 3279 } 3280 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3281 mqd->cp_hqd_dequeue_request); 3282 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3283 mqd->cp_hqd_pq_rptr); 3284 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3285 mqd->cp_hqd_pq_wptr_lo); 3286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3287 mqd->cp_hqd_pq_wptr_hi); 3288 } 3289 3290 /* set the pointer to the MQD */ 3291 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3292 mqd->cp_mqd_base_addr_lo); 3293 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3294 mqd->cp_mqd_base_addr_hi); 3295 3296 /* set MQD vmid to 0 */ 3297 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3298 mqd->cp_mqd_control); 3299 3300 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3301 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3302 mqd->cp_hqd_pq_base_lo); 3303 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3304 mqd->cp_hqd_pq_base_hi); 3305 3306 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3307 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3308 mqd->cp_hqd_pq_control); 3309 3310 /* set the wb address whether it's enabled or not */ 3311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3312 mqd->cp_hqd_pq_rptr_report_addr_lo); 3313 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3314 mqd->cp_hqd_pq_rptr_report_addr_hi); 3315 3316 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3317 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3318 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3320 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3321 3322 /* enable the doorbell if requested */ 3323 if (ring->use_doorbell) { 3324 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3325 (adev->doorbell_index.kiq * 2) << 2); 3326 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3327 (adev->doorbell_index.userqueue_end * 2) << 2); 3328 } 3329 3330 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3331 mqd->cp_hqd_pq_doorbell_control); 3332 3333 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3335 mqd->cp_hqd_pq_wptr_lo); 3336 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3337 mqd->cp_hqd_pq_wptr_hi); 3338 3339 /* set the vmid for the queue */ 3340 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3341 3342 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3343 mqd->cp_hqd_persistent_state); 3344 3345 /* activate the queue */ 3346 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3347 mqd->cp_hqd_active); 3348 3349 if (ring->use_doorbell) 3350 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3351 3352 return 0; 3353 } 3354 3355 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3356 { 3357 struct amdgpu_device *adev = ring->adev; 3358 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3359 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3360 3361 gfx_v12_0_kiq_setting(ring); 3362 3363 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3364 /* reset MQD to a clean status */ 3365 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3366 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3367 3368 /* reset ring buffer */ 3369 ring->wptr = 0; 3370 amdgpu_ring_clear_ring(ring); 3371 3372 mutex_lock(&adev->srbm_mutex); 3373 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3374 gfx_v12_0_kiq_init_register(ring); 3375 soc24_grbm_select(adev, 0, 0, 0, 0); 3376 mutex_unlock(&adev->srbm_mutex); 3377 } else { 3378 memset((void *)mqd, 0, sizeof(*mqd)); 3379 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3380 amdgpu_ring_clear_ring(ring); 3381 mutex_lock(&adev->srbm_mutex); 3382 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3383 amdgpu_ring_init_mqd(ring); 3384 gfx_v12_0_kiq_init_register(ring); 3385 soc24_grbm_select(adev, 0, 0, 0, 0); 3386 mutex_unlock(&adev->srbm_mutex); 3387 3388 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3389 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3390 } 3391 3392 return 0; 3393 } 3394 3395 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3396 { 3397 struct amdgpu_device *adev = ring->adev; 3398 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3399 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3400 3401 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3402 memset((void *)mqd, 0, sizeof(*mqd)); 3403 mutex_lock(&adev->srbm_mutex); 3404 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3405 amdgpu_ring_init_mqd(ring); 3406 soc24_grbm_select(adev, 0, 0, 0, 0); 3407 mutex_unlock(&adev->srbm_mutex); 3408 3409 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3410 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3411 } else { 3412 /* restore MQD to a clean status */ 3413 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3414 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3415 /* reset ring buffer */ 3416 ring->wptr = 0; 3417 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3418 amdgpu_ring_clear_ring(ring); 3419 } 3420 3421 return 0; 3422 } 3423 3424 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3425 { 3426 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3427 adev->gfx.kiq[0].ring.sched.ready = true; 3428 return 0; 3429 } 3430 3431 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3432 { 3433 int i, r; 3434 3435 if (!amdgpu_async_gfx_ring) 3436 gfx_v12_0_cp_compute_enable(adev, true); 3437 3438 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3439 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3440 if (r) 3441 return r; 3442 } 3443 3444 return amdgpu_gfx_enable_kcq(adev, 0); 3445 } 3446 3447 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3448 { 3449 int r, i; 3450 struct amdgpu_ring *ring; 3451 3452 if (!(adev->flags & AMD_IS_APU)) 3453 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3454 3455 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3456 /* legacy firmware loading */ 3457 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3458 if (r) 3459 return r; 3460 3461 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3462 if (r) 3463 return r; 3464 } 3465 3466 gfx_v12_0_cp_set_doorbell_range(adev); 3467 3468 if (amdgpu_async_gfx_ring) { 3469 gfx_v12_0_cp_compute_enable(adev, true); 3470 gfx_v12_0_cp_gfx_enable(adev, true); 3471 } 3472 3473 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3474 r = amdgpu_mes_kiq_hw_init(adev, 0); 3475 else 3476 r = gfx_v12_0_kiq_resume(adev); 3477 if (r) 3478 return r; 3479 3480 r = gfx_v12_0_kcq_resume(adev); 3481 if (r) 3482 return r; 3483 3484 if (!amdgpu_async_gfx_ring) { 3485 r = gfx_v12_0_cp_gfx_resume(adev); 3486 if (r) 3487 return r; 3488 } else { 3489 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3490 if (r) 3491 return r; 3492 } 3493 3494 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3495 ring = &adev->gfx.gfx_ring[i]; 3496 r = amdgpu_ring_test_helper(ring); 3497 if (r) 3498 return r; 3499 } 3500 3501 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3502 ring = &adev->gfx.compute_ring[i]; 3503 r = amdgpu_ring_test_helper(ring); 3504 if (r) 3505 return r; 3506 } 3507 3508 return 0; 3509 } 3510 3511 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3512 { 3513 gfx_v12_0_cp_gfx_enable(adev, enable); 3514 gfx_v12_0_cp_compute_enable(adev, enable); 3515 } 3516 3517 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3518 { 3519 int r; 3520 bool value; 3521 3522 r = adev->gfxhub.funcs->gart_enable(adev); 3523 if (r) 3524 return r; 3525 3526 amdgpu_device_flush_hdp(adev, NULL); 3527 3528 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3529 3530 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3531 /* TODO investigate why this and the hdp flush above is needed, 3532 * are we missing a flush somewhere else? */ 3533 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3534 3535 return 0; 3536 } 3537 3538 static int get_gb_addr_config(struct amdgpu_device *adev) 3539 { 3540 u32 gb_addr_config; 3541 3542 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3543 if (gb_addr_config == 0) 3544 return -EINVAL; 3545 3546 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3547 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3548 3549 adev->gfx.config.gb_addr_config = gb_addr_config; 3550 3551 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3552 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3553 GB_ADDR_CONFIG, NUM_PIPES); 3554 3555 adev->gfx.config.max_tile_pipes = 3556 adev->gfx.config.gb_addr_config_fields.num_pipes; 3557 3558 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3559 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3560 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3561 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3562 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3563 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3564 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3565 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3566 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3567 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3568 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3569 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3570 3571 return 0; 3572 } 3573 3574 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3575 { 3576 uint32_t data; 3577 3578 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3579 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3580 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3581 3582 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3583 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3584 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3585 } 3586 3587 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3588 { 3589 if (amdgpu_sriov_vf(adev)) 3590 return; 3591 3592 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3593 case IP_VERSION(12, 0, 0): 3594 case IP_VERSION(12, 0, 1): 3595 soc15_program_register_sequence(adev, 3596 golden_settings_gc_12_0, 3597 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3598 3599 if (adev->rev_id == 0) 3600 soc15_program_register_sequence(adev, 3601 golden_settings_gc_12_0_rev0, 3602 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3603 break; 3604 default: 3605 break; 3606 } 3607 } 3608 3609 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3610 { 3611 int r; 3612 struct amdgpu_device *adev = ip_block->adev; 3613 3614 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3615 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3616 /* RLC autoload sequence 1: Program rlc ram */ 3617 if (adev->gfx.imu.funcs->program_rlc_ram) 3618 adev->gfx.imu.funcs->program_rlc_ram(adev); 3619 } 3620 /* rlc autoload firmware */ 3621 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3622 if (r) 3623 return r; 3624 } else { 3625 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3626 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3627 if (adev->gfx.imu.funcs->load_microcode) 3628 adev->gfx.imu.funcs->load_microcode(adev); 3629 if (adev->gfx.imu.funcs->setup_imu) 3630 adev->gfx.imu.funcs->setup_imu(adev); 3631 if (adev->gfx.imu.funcs->start_imu) 3632 adev->gfx.imu.funcs->start_imu(adev); 3633 } 3634 3635 /* disable gpa mode in backdoor loading */ 3636 gfx_v12_0_disable_gpa_mode(adev); 3637 } 3638 } 3639 3640 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3641 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3642 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3643 if (r) { 3644 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3645 return r; 3646 } 3647 } 3648 3649 if (!amdgpu_emu_mode) 3650 gfx_v12_0_init_golden_registers(adev); 3651 3652 adev->gfx.is_poweron = true; 3653 3654 if (get_gb_addr_config(adev)) 3655 DRM_WARN("Invalid gb_addr_config !\n"); 3656 3657 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3658 gfx_v12_0_config_gfx_rs64(adev); 3659 3660 r = gfx_v12_0_gfxhub_enable(adev); 3661 if (r) 3662 return r; 3663 3664 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3665 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3666 (amdgpu_dpm == 1)) { 3667 /** 3668 * For gfx 12, rlc firmware loading relies on smu firmware is 3669 * loaded firstly, so in direct type, it has to load smc ucode 3670 * here before rlc. 3671 */ 3672 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3673 if (r) 3674 return r; 3675 } 3676 3677 gfx_v12_0_constants_init(adev); 3678 3679 if (adev->nbio.funcs->gc_doorbell_init) 3680 adev->nbio.funcs->gc_doorbell_init(adev); 3681 3682 r = gfx_v12_0_rlc_resume(adev); 3683 if (r) 3684 return r; 3685 3686 /* 3687 * init golden registers and rlc resume may override some registers, 3688 * reconfig them here 3689 */ 3690 gfx_v12_0_tcp_harvest(adev); 3691 3692 r = gfx_v12_0_cp_resume(adev); 3693 if (r) 3694 return r; 3695 3696 return r; 3697 } 3698 3699 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3700 bool enable) 3701 { 3702 unsigned int irq_type; 3703 int m, p, r; 3704 3705 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3706 for (m = 0; m < adev->gfx.me.num_me; m++) { 3707 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3708 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3709 if (enable) 3710 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3711 irq_type); 3712 else 3713 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3714 irq_type); 3715 if (r) 3716 return r; 3717 } 3718 } 3719 } 3720 3721 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3722 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3723 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3724 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3725 + (m * adev->gfx.mec.num_pipe_per_mec) 3726 + p; 3727 if (enable) 3728 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3729 irq_type); 3730 else 3731 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3732 irq_type); 3733 if (r) 3734 return r; 3735 } 3736 } 3737 } 3738 3739 return 0; 3740 } 3741 3742 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3743 { 3744 struct amdgpu_device *adev = ip_block->adev; 3745 uint32_t tmp; 3746 3747 cancel_delayed_work_sync(&adev->gfx.idle_work); 3748 3749 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3750 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3751 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3752 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3753 3754 if (!adev->no_hw_access) { 3755 if (amdgpu_async_gfx_ring) { 3756 if (amdgpu_gfx_disable_kgq(adev, 0)) 3757 DRM_ERROR("KGQ disable failed\n"); 3758 } 3759 3760 if (amdgpu_gfx_disable_kcq(adev, 0)) 3761 DRM_ERROR("KCQ disable failed\n"); 3762 3763 amdgpu_mes_kiq_hw_fini(adev, 0); 3764 } 3765 3766 if (amdgpu_sriov_vf(adev)) { 3767 gfx_v12_0_cp_gfx_enable(adev, false); 3768 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3769 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3770 tmp &= 0xffffff00; 3771 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3772 3773 return 0; 3774 } 3775 gfx_v12_0_cp_enable(adev, false); 3776 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3777 3778 adev->gfxhub.funcs->gart_disable(adev); 3779 3780 adev->gfx.is_poweron = false; 3781 3782 return 0; 3783 } 3784 3785 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3786 { 3787 return gfx_v12_0_hw_fini(ip_block); 3788 } 3789 3790 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3791 { 3792 return gfx_v12_0_hw_init(ip_block); 3793 } 3794 3795 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3796 { 3797 struct amdgpu_device *adev = ip_block->adev; 3798 3799 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3800 GRBM_STATUS, GUI_ACTIVE)) 3801 return false; 3802 else 3803 return true; 3804 } 3805 3806 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3807 { 3808 unsigned i; 3809 u32 tmp; 3810 struct amdgpu_device *adev = ip_block->adev; 3811 3812 for (i = 0; i < adev->usec_timeout; i++) { 3813 /* read MC_STATUS */ 3814 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3815 GRBM_STATUS__GUI_ACTIVE_MASK; 3816 3817 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3818 return 0; 3819 udelay(1); 3820 } 3821 return -ETIMEDOUT; 3822 } 3823 3824 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3825 { 3826 uint64_t clock = 0; 3827 3828 if (adev->smuio.funcs && 3829 adev->smuio.funcs->get_gpu_clock_counter) 3830 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3831 else 3832 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3833 3834 return clock; 3835 } 3836 3837 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3838 { 3839 struct amdgpu_device *adev = ip_block->adev; 3840 3841 switch (amdgpu_user_queue) { 3842 case -1: 3843 case 0: 3844 default: 3845 adev->gfx.disable_kq = false; 3846 adev->gfx.disable_uq = true; 3847 break; 3848 case 1: 3849 adev->gfx.disable_kq = false; 3850 adev->gfx.disable_uq = false; 3851 break; 3852 case 2: 3853 adev->gfx.disable_kq = true; 3854 adev->gfx.disable_uq = false; 3855 break; 3856 } 3857 3858 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3859 3860 if (adev->gfx.disable_kq) { 3861 adev->gfx.num_gfx_rings = 0; 3862 adev->gfx.num_compute_rings = 0; 3863 } else { 3864 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3865 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3866 AMDGPU_MAX_COMPUTE_RINGS); 3867 } 3868 3869 gfx_v12_0_set_kiq_pm4_funcs(adev); 3870 gfx_v12_0_set_ring_funcs(adev); 3871 gfx_v12_0_set_irq_funcs(adev); 3872 gfx_v12_0_set_rlc_funcs(adev); 3873 gfx_v12_0_set_mqd_funcs(adev); 3874 gfx_v12_0_set_imu_funcs(adev); 3875 3876 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3877 3878 return gfx_v12_0_init_microcode(adev); 3879 } 3880 3881 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3882 { 3883 struct amdgpu_device *adev = ip_block->adev; 3884 int r; 3885 3886 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3887 if (r) 3888 return r; 3889 3890 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3891 if (r) 3892 return r; 3893 3894 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3895 if (r) 3896 return r; 3897 3898 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3899 if (r) 3900 return r; 3901 3902 return 0; 3903 } 3904 3905 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3906 { 3907 uint32_t rlc_cntl; 3908 3909 /* if RLC is not enabled, do nothing */ 3910 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3911 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3912 } 3913 3914 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3915 int xcc_id) 3916 { 3917 uint32_t data; 3918 unsigned i; 3919 3920 data = RLC_SAFE_MODE__CMD_MASK; 3921 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3922 3923 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3924 3925 /* wait for RLC_SAFE_MODE */ 3926 for (i = 0; i < adev->usec_timeout; i++) { 3927 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3928 RLC_SAFE_MODE, CMD)) 3929 break; 3930 udelay(1); 3931 } 3932 } 3933 3934 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3935 int xcc_id) 3936 { 3937 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3938 } 3939 3940 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3941 bool enable) 3942 { 3943 uint32_t def, data; 3944 3945 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3946 return; 3947 3948 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3949 3950 if (enable) 3951 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3952 else 3953 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3954 3955 if (def != data) 3956 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3957 } 3958 3959 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3960 int xcc_id, 3961 struct amdgpu_ring *ring, 3962 unsigned vmid) 3963 { 3964 u32 reg, data; 3965 3966 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3967 if (amdgpu_sriov_is_pp_one_vf(adev)) 3968 data = RREG32_NO_KIQ(reg); 3969 else 3970 data = RREG32(reg); 3971 3972 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3973 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3974 3975 if (amdgpu_sriov_is_pp_one_vf(adev)) 3976 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3977 else 3978 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3979 3980 if (ring 3981 && amdgpu_sriov_is_pp_one_vf(adev) 3982 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3983 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3984 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3985 amdgpu_ring_emit_wreg(ring, reg, data); 3986 } 3987 } 3988 3989 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3990 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3991 .set_safe_mode = gfx_v12_0_set_safe_mode, 3992 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3993 .init = gfx_v12_0_rlc_init, 3994 .get_csb_size = gfx_v12_0_get_csb_size, 3995 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3996 .resume = gfx_v12_0_rlc_resume, 3997 .stop = gfx_v12_0_rlc_stop, 3998 .reset = gfx_v12_0_rlc_reset, 3999 .start = gfx_v12_0_rlc_start, 4000 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4001 }; 4002 4003 #if 0 4004 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4005 { 4006 /* TODO */ 4007 } 4008 4009 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4010 { 4011 /* TODO */ 4012 } 4013 #endif 4014 4015 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4016 enum amd_powergating_state state) 4017 { 4018 struct amdgpu_device *adev = ip_block->adev; 4019 bool enable = (state == AMD_PG_STATE_GATE); 4020 4021 if (amdgpu_sriov_vf(adev)) 4022 return 0; 4023 4024 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4025 case IP_VERSION(12, 0, 0): 4026 case IP_VERSION(12, 0, 1): 4027 amdgpu_gfx_off_ctrl(adev, enable); 4028 break; 4029 default: 4030 break; 4031 } 4032 4033 return 0; 4034 } 4035 4036 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4037 bool enable) 4038 { 4039 uint32_t def, data; 4040 4041 if (!(adev->cg_flags & 4042 (AMD_CG_SUPPORT_GFX_CGCG | 4043 AMD_CG_SUPPORT_GFX_CGLS | 4044 AMD_CG_SUPPORT_GFX_3D_CGCG | 4045 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4046 return; 4047 4048 if (enable) { 4049 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4050 4051 /* unset CGCG override */ 4052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4053 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4055 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4056 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4057 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4058 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4059 4060 /* update CGCG override bits */ 4061 if (def != data) 4062 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4063 4064 /* enable cgcg FSM(0x0000363F) */ 4065 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4066 4067 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4068 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4069 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4070 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4071 } 4072 4073 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4074 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4075 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4076 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4077 } 4078 4079 if (def != data) 4080 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4081 4082 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4083 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4084 4085 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4086 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4087 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4088 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4089 } 4090 4091 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4092 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4093 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4094 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4095 } 4096 4097 if (def != data) 4098 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4099 4100 /* set IDLE_POLL_COUNT(0x00900100) */ 4101 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4102 4103 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4104 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4105 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4106 4107 if (def != data) 4108 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4109 4110 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4111 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4112 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4113 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4114 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4115 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4116 4117 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4118 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4119 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4120 4121 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4122 if (adev->sdma.num_instances > 1) { 4123 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4124 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4125 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4126 } 4127 } else { 4128 /* Program RLC_CGCG_CGLS_CTRL */ 4129 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4130 4131 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4132 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4133 4134 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4135 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4136 4137 if (def != data) 4138 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4139 4140 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4141 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4142 4143 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4144 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4145 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4146 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4147 4148 if (def != data) 4149 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4150 } 4151 } 4152 4153 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4154 bool enable) 4155 { 4156 uint32_t data, def; 4157 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4158 return; 4159 4160 /* It is disabled by HW by default */ 4161 if (enable) { 4162 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4163 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4164 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4165 4166 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4167 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4168 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4169 4170 if (def != data) 4171 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4172 } 4173 } else { 4174 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4175 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4176 4177 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4178 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4179 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4180 4181 if (def != data) 4182 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4183 } 4184 } 4185 } 4186 4187 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4188 bool enable) 4189 { 4190 uint32_t def, data; 4191 4192 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4193 return; 4194 4195 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4196 4197 if (enable) 4198 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4199 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4200 else 4201 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4202 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4203 4204 if (def != data) 4205 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4206 } 4207 4208 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4209 bool enable) 4210 { 4211 uint32_t def, data; 4212 4213 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4214 return; 4215 4216 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4217 4218 if (enable) 4219 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4220 else 4221 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4222 4223 if (def != data) 4224 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4225 } 4226 4227 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4228 bool enable) 4229 { 4230 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4231 4232 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4233 4234 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4235 4236 gfx_v12_0_update_repeater_fgcg(adev, enable); 4237 4238 gfx_v12_0_update_sram_fgcg(adev, enable); 4239 4240 gfx_v12_0_update_perf_clk(adev, enable); 4241 4242 if (adev->cg_flags & 4243 (AMD_CG_SUPPORT_GFX_MGCG | 4244 AMD_CG_SUPPORT_GFX_CGLS | 4245 AMD_CG_SUPPORT_GFX_CGCG | 4246 AMD_CG_SUPPORT_GFX_3D_CGCG | 4247 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4248 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4249 4250 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4251 4252 return 0; 4253 } 4254 4255 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4256 enum amd_clockgating_state state) 4257 { 4258 struct amdgpu_device *adev = ip_block->adev; 4259 4260 if (amdgpu_sriov_vf(adev)) 4261 return 0; 4262 4263 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4264 case IP_VERSION(12, 0, 0): 4265 case IP_VERSION(12, 0, 1): 4266 gfx_v12_0_update_gfx_clock_gating(adev, 4267 state == AMD_CG_STATE_GATE); 4268 break; 4269 default: 4270 break; 4271 } 4272 4273 return 0; 4274 } 4275 4276 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4277 { 4278 struct amdgpu_device *adev = ip_block->adev; 4279 int data; 4280 4281 /* AMD_CG_SUPPORT_GFX_MGCG */ 4282 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4283 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4284 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4285 4286 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4287 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4288 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4289 4290 /* AMD_CG_SUPPORT_GFX_FGCG */ 4291 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4292 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4293 4294 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4295 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4296 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4297 4298 /* AMD_CG_SUPPORT_GFX_CGCG */ 4299 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4300 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4301 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4302 4303 /* AMD_CG_SUPPORT_GFX_CGLS */ 4304 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4305 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4306 4307 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4308 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4309 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4310 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4311 4312 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4313 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4314 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4315 } 4316 4317 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4318 { 4319 /* gfx12 is 32bit rptr*/ 4320 return *(uint32_t *)ring->rptr_cpu_addr; 4321 } 4322 4323 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4324 { 4325 struct amdgpu_device *adev = ring->adev; 4326 u64 wptr; 4327 4328 /* XXX check if swapping is necessary on BE */ 4329 if (ring->use_doorbell) { 4330 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4331 } else { 4332 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4333 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4334 } 4335 4336 return wptr; 4337 } 4338 4339 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4340 { 4341 struct amdgpu_device *adev = ring->adev; 4342 4343 if (ring->use_doorbell) { 4344 /* XXX check if swapping is necessary on BE */ 4345 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4346 ring->wptr); 4347 WDOORBELL64(ring->doorbell_index, ring->wptr); 4348 } else { 4349 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4350 lower_32_bits(ring->wptr)); 4351 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4352 upper_32_bits(ring->wptr)); 4353 } 4354 } 4355 4356 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4357 { 4358 /* gfx12 hardware is 32bit rptr */ 4359 return *(uint32_t *)ring->rptr_cpu_addr; 4360 } 4361 4362 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4363 { 4364 u64 wptr; 4365 4366 /* XXX check if swapping is necessary on BE */ 4367 if (ring->use_doorbell) 4368 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4369 else 4370 BUG(); 4371 return wptr; 4372 } 4373 4374 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4375 { 4376 struct amdgpu_device *adev = ring->adev; 4377 4378 /* XXX check if swapping is necessary on BE */ 4379 if (ring->use_doorbell) { 4380 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4381 ring->wptr); 4382 WDOORBELL64(ring->doorbell_index, ring->wptr); 4383 } else { 4384 BUG(); /* only DOORBELL method supported on gfx12 now */ 4385 } 4386 } 4387 4388 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4389 { 4390 struct amdgpu_device *adev = ring->adev; 4391 u32 ref_and_mask, reg_mem_engine; 4392 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4393 4394 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4395 switch (ring->me) { 4396 case 1: 4397 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4398 break; 4399 case 2: 4400 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4401 break; 4402 default: 4403 return; 4404 } 4405 reg_mem_engine = 0; 4406 } else { 4407 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4408 reg_mem_engine = 1; /* pfp */ 4409 } 4410 4411 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4412 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4413 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4414 ref_and_mask, ref_and_mask, 0x20); 4415 } 4416 4417 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4418 struct amdgpu_job *job, 4419 struct amdgpu_ib *ib, 4420 uint32_t flags) 4421 { 4422 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4423 u32 header, control = 0; 4424 4425 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4426 4427 control |= ib->length_dw | (vmid << 24); 4428 4429 amdgpu_ring_write(ring, header); 4430 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4431 amdgpu_ring_write(ring, 4432 #ifdef __BIG_ENDIAN 4433 (2 << 0) | 4434 #endif 4435 lower_32_bits(ib->gpu_addr)); 4436 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4437 amdgpu_ring_write(ring, control); 4438 } 4439 4440 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4441 struct amdgpu_job *job, 4442 struct amdgpu_ib *ib, 4443 uint32_t flags) 4444 { 4445 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4446 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4447 4448 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4449 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4450 amdgpu_ring_write(ring, 4451 #ifdef __BIG_ENDIAN 4452 (2 << 0) | 4453 #endif 4454 lower_32_bits(ib->gpu_addr)); 4455 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4456 amdgpu_ring_write(ring, control); 4457 } 4458 4459 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4460 u64 seq, unsigned flags) 4461 { 4462 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4463 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4464 4465 /* RELEASE_MEM - flush caches, send int */ 4466 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4467 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4468 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4469 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4470 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4471 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4472 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4473 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4474 4475 /* 4476 * the address should be Qword aligned if 64bit write, Dword 4477 * aligned if only send 32bit data low (discard data high) 4478 */ 4479 if (write64bit) 4480 BUG_ON(addr & 0x7); 4481 else 4482 BUG_ON(addr & 0x3); 4483 amdgpu_ring_write(ring, lower_32_bits(addr)); 4484 amdgpu_ring_write(ring, upper_32_bits(addr)); 4485 amdgpu_ring_write(ring, lower_32_bits(seq)); 4486 amdgpu_ring_write(ring, upper_32_bits(seq)); 4487 amdgpu_ring_write(ring, 0); 4488 } 4489 4490 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4491 { 4492 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4493 uint32_t seq = ring->fence_drv.sync_seq; 4494 uint64_t addr = ring->fence_drv.gpu_addr; 4495 4496 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4497 upper_32_bits(addr), seq, 0xffffffff, 4); 4498 } 4499 4500 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4501 uint16_t pasid, uint32_t flush_type, 4502 bool all_hub, uint8_t dst_sel) 4503 { 4504 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4505 amdgpu_ring_write(ring, 4506 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4507 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4508 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4509 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4510 } 4511 4512 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4513 unsigned vmid, uint64_t pd_addr) 4514 { 4515 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4516 4517 /* compute doesn't have PFP */ 4518 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4519 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4520 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4521 amdgpu_ring_write(ring, 0x0); 4522 } 4523 } 4524 4525 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4526 u64 seq, unsigned int flags) 4527 { 4528 struct amdgpu_device *adev = ring->adev; 4529 4530 /* we only allocate 32bit for each seq wb address */ 4531 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4532 4533 /* write fence seq to the "addr" */ 4534 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4535 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4536 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4537 amdgpu_ring_write(ring, lower_32_bits(addr)); 4538 amdgpu_ring_write(ring, upper_32_bits(addr)); 4539 amdgpu_ring_write(ring, lower_32_bits(seq)); 4540 4541 if (flags & AMDGPU_FENCE_FLAG_INT) { 4542 /* set register to trigger INT */ 4543 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4544 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4545 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4546 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4547 amdgpu_ring_write(ring, 0); 4548 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4549 } 4550 } 4551 4552 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4553 uint32_t flags) 4554 { 4555 uint32_t dw2 = 0; 4556 4557 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4558 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4559 /* set load_global_config & load_global_uconfig */ 4560 dw2 |= 0x8001; 4561 /* set load_cs_sh_regs */ 4562 dw2 |= 0x01000000; 4563 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4564 dw2 |= 0x10002; 4565 } 4566 4567 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4568 amdgpu_ring_write(ring, dw2); 4569 amdgpu_ring_write(ring, 0); 4570 } 4571 4572 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4573 uint64_t addr) 4574 { 4575 unsigned ret; 4576 4577 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4578 amdgpu_ring_write(ring, lower_32_bits(addr)); 4579 amdgpu_ring_write(ring, upper_32_bits(addr)); 4580 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4581 amdgpu_ring_write(ring, 0); 4582 ret = ring->wptr & ring->buf_mask; 4583 /* patch dummy value later */ 4584 amdgpu_ring_write(ring, 0); 4585 4586 return ret; 4587 } 4588 4589 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4590 { 4591 int i, r = 0; 4592 struct amdgpu_device *adev = ring->adev; 4593 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4594 struct amdgpu_ring *kiq_ring = &kiq->ring; 4595 unsigned long flags; 4596 4597 if (adev->enable_mes) 4598 return -EINVAL; 4599 4600 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4601 return -EINVAL; 4602 4603 spin_lock_irqsave(&kiq->ring_lock, flags); 4604 4605 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4606 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4607 return -ENOMEM; 4608 } 4609 4610 /* assert preemption condition */ 4611 amdgpu_ring_set_preempt_cond_exec(ring, false); 4612 4613 /* assert IB preemption, emit the trailing fence */ 4614 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4615 ring->trail_fence_gpu_addr, 4616 ++ring->trail_seq); 4617 amdgpu_ring_commit(kiq_ring); 4618 4619 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4620 4621 /* poll the trailing fence */ 4622 for (i = 0; i < adev->usec_timeout; i++) { 4623 if (ring->trail_seq == 4624 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4625 break; 4626 udelay(1); 4627 } 4628 4629 if (i >= adev->usec_timeout) { 4630 r = -EINVAL; 4631 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4632 } 4633 4634 /* deassert preemption condition */ 4635 amdgpu_ring_set_preempt_cond_exec(ring, true); 4636 return r; 4637 } 4638 4639 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4640 bool start, 4641 bool secure) 4642 { 4643 uint32_t v = secure ? FRAME_TMZ : 0; 4644 4645 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4646 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4647 } 4648 4649 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4650 uint32_t reg_val_offs) 4651 { 4652 struct amdgpu_device *adev = ring->adev; 4653 4654 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4655 amdgpu_ring_write(ring, 0 | /* src: register*/ 4656 (5 << 8) | /* dst: memory */ 4657 (1 << 20)); /* write confirm */ 4658 amdgpu_ring_write(ring, reg); 4659 amdgpu_ring_write(ring, 0); 4660 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4661 reg_val_offs * 4)); 4662 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4663 reg_val_offs * 4)); 4664 } 4665 4666 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4667 uint32_t reg, 4668 uint32_t val) 4669 { 4670 uint32_t cmd = 0; 4671 4672 switch (ring->funcs->type) { 4673 case AMDGPU_RING_TYPE_GFX: 4674 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4675 break; 4676 case AMDGPU_RING_TYPE_KIQ: 4677 cmd = (1 << 16); /* no inc addr */ 4678 break; 4679 default: 4680 cmd = WR_CONFIRM; 4681 break; 4682 } 4683 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4684 amdgpu_ring_write(ring, cmd); 4685 amdgpu_ring_write(ring, reg); 4686 amdgpu_ring_write(ring, 0); 4687 amdgpu_ring_write(ring, val); 4688 } 4689 4690 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4691 uint32_t val, uint32_t mask) 4692 { 4693 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4694 } 4695 4696 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4697 uint32_t reg0, uint32_t reg1, 4698 uint32_t ref, uint32_t mask) 4699 { 4700 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4701 4702 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4703 ref, mask, 0x20); 4704 } 4705 4706 static void 4707 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4708 uint32_t me, uint32_t pipe, 4709 enum amdgpu_interrupt_state state) 4710 { 4711 uint32_t cp_int_cntl, cp_int_cntl_reg; 4712 4713 if (!me) { 4714 switch (pipe) { 4715 case 0: 4716 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4717 break; 4718 default: 4719 DRM_DEBUG("invalid pipe %d\n", pipe); 4720 return; 4721 } 4722 } else { 4723 DRM_DEBUG("invalid me %d\n", me); 4724 return; 4725 } 4726 4727 switch (state) { 4728 case AMDGPU_IRQ_STATE_DISABLE: 4729 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4730 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4731 TIME_STAMP_INT_ENABLE, 0); 4732 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4733 GENERIC0_INT_ENABLE, 0); 4734 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4735 break; 4736 case AMDGPU_IRQ_STATE_ENABLE: 4737 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4738 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4739 TIME_STAMP_INT_ENABLE, 1); 4740 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4741 GENERIC0_INT_ENABLE, 1); 4742 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4743 break; 4744 default: 4745 break; 4746 } 4747 } 4748 4749 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4750 int me, int pipe, 4751 enum amdgpu_interrupt_state state) 4752 { 4753 u32 mec_int_cntl, mec_int_cntl_reg; 4754 4755 /* 4756 * amdgpu controls only the first MEC. That's why this function only 4757 * handles the setting of interrupts for this specific MEC. All other 4758 * pipes' interrupts are set by amdkfd. 4759 */ 4760 4761 if (me == 1) { 4762 switch (pipe) { 4763 case 0: 4764 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4765 break; 4766 case 1: 4767 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4768 break; 4769 default: 4770 DRM_DEBUG("invalid pipe %d\n", pipe); 4771 return; 4772 } 4773 } else { 4774 DRM_DEBUG("invalid me %d\n", me); 4775 return; 4776 } 4777 4778 switch (state) { 4779 case AMDGPU_IRQ_STATE_DISABLE: 4780 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4781 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4782 TIME_STAMP_INT_ENABLE, 0); 4783 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4784 GENERIC0_INT_ENABLE, 0); 4785 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4786 break; 4787 case AMDGPU_IRQ_STATE_ENABLE: 4788 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4789 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4790 TIME_STAMP_INT_ENABLE, 1); 4791 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4792 GENERIC0_INT_ENABLE, 1); 4793 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4794 break; 4795 default: 4796 break; 4797 } 4798 } 4799 4800 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4801 struct amdgpu_irq_src *src, 4802 unsigned type, 4803 enum amdgpu_interrupt_state state) 4804 { 4805 switch (type) { 4806 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4807 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4808 break; 4809 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4810 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4811 break; 4812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4813 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4814 break; 4815 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4816 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4817 break; 4818 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4819 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4820 break; 4821 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4822 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4823 break; 4824 default: 4825 break; 4826 } 4827 return 0; 4828 } 4829 4830 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4831 struct amdgpu_irq_src *source, 4832 struct amdgpu_iv_entry *entry) 4833 { 4834 u32 doorbell_offset = entry->src_data[0]; 4835 u8 me_id, pipe_id, queue_id; 4836 struct amdgpu_ring *ring; 4837 int i; 4838 4839 DRM_DEBUG("IH: CP EOP\n"); 4840 4841 if (adev->enable_mes && doorbell_offset) { 4842 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4843 struct xarray *xa = &adev->userq_xa; 4844 unsigned long flags; 4845 4846 xa_lock_irqsave(xa, flags); 4847 fence_drv = xa_load(xa, doorbell_offset); 4848 if (fence_drv) 4849 amdgpu_userq_fence_driver_process(fence_drv); 4850 xa_unlock_irqrestore(xa, flags); 4851 } else { 4852 me_id = (entry->ring_id & 0x0c) >> 2; 4853 pipe_id = (entry->ring_id & 0x03) >> 0; 4854 queue_id = (entry->ring_id & 0x70) >> 4; 4855 4856 switch (me_id) { 4857 case 0: 4858 if (pipe_id == 0) 4859 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4860 else 4861 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4862 break; 4863 case 1: 4864 case 2: 4865 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4866 ring = &adev->gfx.compute_ring[i]; 4867 /* Per-queue interrupt is supported for MEC starting from VI. 4868 * The interrupt can only be enabled/disabled per pipe instead 4869 * of per queue. 4870 */ 4871 if ((ring->me == me_id) && 4872 (ring->pipe == pipe_id) && 4873 (ring->queue == queue_id)) 4874 amdgpu_fence_process(ring); 4875 } 4876 break; 4877 } 4878 } 4879 4880 return 0; 4881 } 4882 4883 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4884 struct amdgpu_irq_src *source, 4885 unsigned int type, 4886 enum amdgpu_interrupt_state state) 4887 { 4888 u32 cp_int_cntl_reg, cp_int_cntl; 4889 int i, j; 4890 4891 switch (state) { 4892 case AMDGPU_IRQ_STATE_DISABLE: 4893 case AMDGPU_IRQ_STATE_ENABLE: 4894 for (i = 0; i < adev->gfx.me.num_me; i++) { 4895 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4896 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4897 4898 if (cp_int_cntl_reg) { 4899 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4900 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4901 PRIV_REG_INT_ENABLE, 4902 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4903 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4904 } 4905 } 4906 } 4907 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4908 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4909 /* MECs start at 1 */ 4910 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4911 4912 if (cp_int_cntl_reg) { 4913 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4914 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4915 PRIV_REG_INT_ENABLE, 4916 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4917 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4918 } 4919 } 4920 } 4921 break; 4922 default: 4923 break; 4924 } 4925 4926 return 0; 4927 } 4928 4929 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4930 struct amdgpu_irq_src *source, 4931 unsigned type, 4932 enum amdgpu_interrupt_state state) 4933 { 4934 u32 cp_int_cntl_reg, cp_int_cntl; 4935 int i, j; 4936 4937 switch (state) { 4938 case AMDGPU_IRQ_STATE_DISABLE: 4939 case AMDGPU_IRQ_STATE_ENABLE: 4940 for (i = 0; i < adev->gfx.me.num_me; i++) { 4941 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4942 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4943 4944 if (cp_int_cntl_reg) { 4945 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4946 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4947 OPCODE_ERROR_INT_ENABLE, 4948 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4949 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4950 } 4951 } 4952 } 4953 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4954 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4955 /* MECs start at 1 */ 4956 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4957 4958 if (cp_int_cntl_reg) { 4959 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4960 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4961 OPCODE_ERROR_INT_ENABLE, 4962 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4963 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4964 } 4965 } 4966 } 4967 break; 4968 default: 4969 break; 4970 } 4971 return 0; 4972 } 4973 4974 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4975 struct amdgpu_irq_src *source, 4976 unsigned int type, 4977 enum amdgpu_interrupt_state state) 4978 { 4979 u32 cp_int_cntl_reg, cp_int_cntl; 4980 int i, j; 4981 4982 switch (state) { 4983 case AMDGPU_IRQ_STATE_DISABLE: 4984 case AMDGPU_IRQ_STATE_ENABLE: 4985 for (i = 0; i < adev->gfx.me.num_me; i++) { 4986 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4987 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4988 4989 if (cp_int_cntl_reg) { 4990 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4991 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4992 PRIV_INSTR_INT_ENABLE, 4993 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4994 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4995 } 4996 } 4997 } 4998 break; 4999 default: 5000 break; 5001 } 5002 5003 return 0; 5004 } 5005 5006 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5007 struct amdgpu_iv_entry *entry) 5008 { 5009 u8 me_id, pipe_id, queue_id; 5010 struct amdgpu_ring *ring; 5011 int i; 5012 5013 me_id = (entry->ring_id & 0x0c) >> 2; 5014 pipe_id = (entry->ring_id & 0x03) >> 0; 5015 queue_id = (entry->ring_id & 0x70) >> 4; 5016 5017 if (!adev->gfx.disable_kq) { 5018 switch (me_id) { 5019 case 0: 5020 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5021 ring = &adev->gfx.gfx_ring[i]; 5022 if (ring->me == me_id && ring->pipe == pipe_id && 5023 ring->queue == queue_id) 5024 drm_sched_fault(&ring->sched); 5025 } 5026 break; 5027 case 1: 5028 case 2: 5029 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5030 ring = &adev->gfx.compute_ring[i]; 5031 if (ring->me == me_id && ring->pipe == pipe_id && 5032 ring->queue == queue_id) 5033 drm_sched_fault(&ring->sched); 5034 } 5035 break; 5036 default: 5037 BUG(); 5038 break; 5039 } 5040 } 5041 } 5042 5043 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5044 struct amdgpu_irq_src *source, 5045 struct amdgpu_iv_entry *entry) 5046 { 5047 DRM_ERROR("Illegal register access in command stream\n"); 5048 gfx_v12_0_handle_priv_fault(adev, entry); 5049 return 0; 5050 } 5051 5052 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5053 struct amdgpu_irq_src *source, 5054 struct amdgpu_iv_entry *entry) 5055 { 5056 DRM_ERROR("Illegal opcode in command stream \n"); 5057 gfx_v12_0_handle_priv_fault(adev, entry); 5058 return 0; 5059 } 5060 5061 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5062 struct amdgpu_irq_src *source, 5063 struct amdgpu_iv_entry *entry) 5064 { 5065 DRM_ERROR("Illegal instruction in command stream\n"); 5066 gfx_v12_0_handle_priv_fault(adev, entry); 5067 return 0; 5068 } 5069 5070 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5071 { 5072 const unsigned int gcr_cntl = 5073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5079 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5080 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5081 5082 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5083 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5084 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5085 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5086 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5087 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5088 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5089 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5090 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5091 } 5092 5093 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5094 { 5095 /* Header itself is a NOP packet */ 5096 if (num_nop == 1) { 5097 amdgpu_ring_write(ring, ring->funcs->nop); 5098 return; 5099 } 5100 5101 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5102 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5103 5104 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5105 amdgpu_ring_insert_nop(ring, num_nop - 1); 5106 } 5107 5108 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5109 { 5110 /* Emit the cleaner shader */ 5111 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5112 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5113 } 5114 5115 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5116 { 5117 struct amdgpu_device *adev = ip_block->adev; 5118 uint32_t i, j, k, reg, index = 0; 5119 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5120 5121 if (!adev->gfx.ip_dump_core) 5122 return; 5123 5124 for (i = 0; i < reg_count; i++) 5125 drm_printf(p, "%-50s \t 0x%08x\n", 5126 gc_reg_list_12_0[i].reg_name, 5127 adev->gfx.ip_dump_core[i]); 5128 5129 /* print compute queue registers for all instances */ 5130 if (!adev->gfx.ip_dump_compute_queues) 5131 return; 5132 5133 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5134 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5135 adev->gfx.mec.num_mec, 5136 adev->gfx.mec.num_pipe_per_mec, 5137 adev->gfx.mec.num_queue_per_pipe); 5138 5139 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5140 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5141 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5142 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5143 for (reg = 0; reg < reg_count; reg++) { 5144 drm_printf(p, "%-50s \t 0x%08x\n", 5145 gc_cp_reg_list_12[reg].reg_name, 5146 adev->gfx.ip_dump_compute_queues[index + reg]); 5147 } 5148 index += reg_count; 5149 } 5150 } 5151 } 5152 5153 /* print gfx queue registers for all instances */ 5154 if (!adev->gfx.ip_dump_gfx_queues) 5155 return; 5156 5157 index = 0; 5158 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5159 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5160 adev->gfx.me.num_me, 5161 adev->gfx.me.num_pipe_per_me, 5162 adev->gfx.me.num_queue_per_pipe); 5163 5164 for (i = 0; i < adev->gfx.me.num_me; i++) { 5165 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5166 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5167 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5168 for (reg = 0; reg < reg_count; reg++) { 5169 drm_printf(p, "%-50s \t 0x%08x\n", 5170 gc_gfx_queue_reg_list_12[reg].reg_name, 5171 adev->gfx.ip_dump_gfx_queues[index + reg]); 5172 } 5173 index += reg_count; 5174 } 5175 } 5176 } 5177 } 5178 5179 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5180 { 5181 struct amdgpu_device *adev = ip_block->adev; 5182 uint32_t i, j, k, reg, index = 0; 5183 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5184 5185 if (!adev->gfx.ip_dump_core) 5186 return; 5187 5188 amdgpu_gfx_off_ctrl(adev, false); 5189 for (i = 0; i < reg_count; i++) 5190 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5191 amdgpu_gfx_off_ctrl(adev, true); 5192 5193 /* dump compute queue registers for all instances */ 5194 if (!adev->gfx.ip_dump_compute_queues) 5195 return; 5196 5197 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5198 amdgpu_gfx_off_ctrl(adev, false); 5199 mutex_lock(&adev->srbm_mutex); 5200 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5201 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5202 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5203 /* ME0 is for GFX so start from 1 for CP */ 5204 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5205 for (reg = 0; reg < reg_count; reg++) { 5206 adev->gfx.ip_dump_compute_queues[index + reg] = 5207 RREG32(SOC15_REG_ENTRY_OFFSET( 5208 gc_cp_reg_list_12[reg])); 5209 } 5210 index += reg_count; 5211 } 5212 } 5213 } 5214 soc24_grbm_select(adev, 0, 0, 0, 0); 5215 mutex_unlock(&adev->srbm_mutex); 5216 amdgpu_gfx_off_ctrl(adev, true); 5217 5218 /* dump gfx queue registers for all instances */ 5219 if (!adev->gfx.ip_dump_gfx_queues) 5220 return; 5221 5222 index = 0; 5223 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5224 amdgpu_gfx_off_ctrl(adev, false); 5225 mutex_lock(&adev->srbm_mutex); 5226 for (i = 0; i < adev->gfx.me.num_me; i++) { 5227 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5228 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5229 soc24_grbm_select(adev, i, j, k, 0); 5230 5231 for (reg = 0; reg < reg_count; reg++) { 5232 adev->gfx.ip_dump_gfx_queues[index + reg] = 5233 RREG32(SOC15_REG_ENTRY_OFFSET( 5234 gc_gfx_queue_reg_list_12[reg])); 5235 } 5236 index += reg_count; 5237 } 5238 } 5239 } 5240 soc24_grbm_select(adev, 0, 0, 0, 0); 5241 mutex_unlock(&adev->srbm_mutex); 5242 amdgpu_gfx_off_ctrl(adev, true); 5243 } 5244 5245 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5246 { 5247 /* Disable the pipe reset until the CPFW fully support it.*/ 5248 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5249 return false; 5250 } 5251 5252 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5253 { 5254 struct amdgpu_device *adev = ring->adev; 5255 uint32_t reset_pipe = 0, clean_pipe = 0; 5256 int r; 5257 5258 if (!gfx_v12_pipe_reset_support(adev)) 5259 return -EOPNOTSUPP; 5260 5261 gfx_v12_0_set_safe_mode(adev, 0); 5262 mutex_lock(&adev->srbm_mutex); 5263 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5264 5265 switch (ring->pipe) { 5266 case 0: 5267 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5268 PFP_PIPE0_RESET, 1); 5269 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5270 ME_PIPE0_RESET, 1); 5271 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5272 PFP_PIPE0_RESET, 0); 5273 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5274 ME_PIPE0_RESET, 0); 5275 break; 5276 case 1: 5277 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5278 PFP_PIPE1_RESET, 1); 5279 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5280 ME_PIPE1_RESET, 1); 5281 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5282 PFP_PIPE1_RESET, 0); 5283 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5284 ME_PIPE1_RESET, 0); 5285 break; 5286 default: 5287 break; 5288 } 5289 5290 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5291 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5292 5293 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5294 RS64_FW_UC_START_ADDR_LO; 5295 soc24_grbm_select(adev, 0, 0, 0, 0); 5296 mutex_unlock(&adev->srbm_mutex); 5297 gfx_v12_0_unset_safe_mode(adev, 0); 5298 5299 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5300 r == 0 ? "successfully" : "failed"); 5301 /* Sometimes the ME start pc counter can't cache correctly, so the 5302 * PC check only as a reference and pipe reset result rely on the 5303 * later ring test. 5304 */ 5305 return 0; 5306 } 5307 5308 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5309 unsigned int vmid, 5310 struct amdgpu_fence *timedout_fence) 5311 { 5312 struct amdgpu_device *adev = ring->adev; 5313 int r; 5314 5315 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5316 5317 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); 5318 if (r) { 5319 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5320 r = gfx_v12_reset_gfx_pipe(ring); 5321 if (r) 5322 return r; 5323 } 5324 5325 r = gfx_v12_0_kgq_init_queue(ring, true); 5326 if (r) { 5327 dev_err(adev->dev, "failed to init kgq\n"); 5328 return r; 5329 } 5330 5331 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5332 if (r) { 5333 dev_err(adev->dev, "failed to remap kgq\n"); 5334 return r; 5335 } 5336 5337 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5338 } 5339 5340 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5341 { 5342 struct amdgpu_device *adev = ring->adev; 5343 uint32_t reset_pipe = 0, clean_pipe = 0; 5344 int r = 0; 5345 5346 if (!gfx_v12_pipe_reset_support(adev)) 5347 return -EOPNOTSUPP; 5348 5349 gfx_v12_0_set_safe_mode(adev, 0); 5350 mutex_lock(&adev->srbm_mutex); 5351 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5352 5353 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5354 clean_pipe = reset_pipe; 5355 5356 if (adev->gfx.rs64_enable) { 5357 switch (ring->pipe) { 5358 case 0: 5359 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5360 MEC_PIPE0_RESET, 1); 5361 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5362 MEC_PIPE0_RESET, 0); 5363 break; 5364 case 1: 5365 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5366 MEC_PIPE1_RESET, 1); 5367 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5368 MEC_PIPE1_RESET, 0); 5369 break; 5370 case 2: 5371 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5372 MEC_PIPE2_RESET, 1); 5373 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5374 MEC_PIPE2_RESET, 0); 5375 break; 5376 case 3: 5377 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5378 MEC_PIPE3_RESET, 1); 5379 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5380 MEC_PIPE3_RESET, 0); 5381 break; 5382 default: 5383 break; 5384 } 5385 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5386 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5387 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5388 RS64_FW_UC_START_ADDR_LO; 5389 } else { 5390 switch (ring->pipe) { 5391 case 0: 5392 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5393 MEC_ME1_PIPE0_RESET, 1); 5394 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5395 MEC_ME1_PIPE0_RESET, 0); 5396 break; 5397 case 1: 5398 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5399 MEC_ME1_PIPE1_RESET, 1); 5400 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5401 MEC_ME1_PIPE1_RESET, 0); 5402 break; 5403 default: 5404 break; 5405 } 5406 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5407 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5408 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5409 * the driver won't run into the F32 mode. 5410 */ 5411 } 5412 5413 soc24_grbm_select(adev, 0, 0, 0, 0); 5414 mutex_unlock(&adev->srbm_mutex); 5415 gfx_v12_0_unset_safe_mode(adev, 0); 5416 5417 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5418 r == 0 ? "successfully" : "failed"); 5419 /* Need the ring test to verify the pipe reset result.*/ 5420 return 0; 5421 } 5422 5423 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5424 unsigned int vmid, 5425 struct amdgpu_fence *timedout_fence) 5426 { 5427 struct amdgpu_device *adev = ring->adev; 5428 int r; 5429 5430 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5431 5432 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); 5433 if (r) { 5434 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5435 r = gfx_v12_0_reset_compute_pipe(ring); 5436 if (r) 5437 return r; 5438 } 5439 5440 r = gfx_v12_0_kcq_init_queue(ring, true); 5441 if (r) { 5442 dev_err(adev->dev, "failed to init kcq\n"); 5443 return r; 5444 } 5445 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5446 if (r) { 5447 dev_err(adev->dev, "failed to remap kcq\n"); 5448 return r; 5449 } 5450 5451 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5452 } 5453 5454 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5455 { 5456 amdgpu_gfx_profile_ring_begin_use(ring); 5457 5458 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5459 } 5460 5461 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5462 { 5463 amdgpu_gfx_profile_ring_end_use(ring); 5464 5465 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5466 } 5467 5468 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5469 .name = "gfx_v12_0", 5470 .early_init = gfx_v12_0_early_init, 5471 .late_init = gfx_v12_0_late_init, 5472 .sw_init = gfx_v12_0_sw_init, 5473 .sw_fini = gfx_v12_0_sw_fini, 5474 .hw_init = gfx_v12_0_hw_init, 5475 .hw_fini = gfx_v12_0_hw_fini, 5476 .suspend = gfx_v12_0_suspend, 5477 .resume = gfx_v12_0_resume, 5478 .is_idle = gfx_v12_0_is_idle, 5479 .wait_for_idle = gfx_v12_0_wait_for_idle, 5480 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5481 .set_powergating_state = gfx_v12_0_set_powergating_state, 5482 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5483 .dump_ip_state = gfx_v12_ip_dump, 5484 .print_ip_state = gfx_v12_ip_print, 5485 }; 5486 5487 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5488 .type = AMDGPU_RING_TYPE_GFX, 5489 .align_mask = 0xff, 5490 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5491 .support_64bit_ptrs = true, 5492 .secure_submission_supported = true, 5493 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5494 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5495 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5496 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5497 5 + /* COND_EXEC */ 5498 7 + /* PIPELINE_SYNC */ 5499 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5500 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5501 2 + /* VM_FLUSH */ 5502 8 + /* FENCE for VM_FLUSH */ 5503 5 + /* COND_EXEC */ 5504 7 + /* HDP_flush */ 5505 4 + /* VGT_flush */ 5506 31 + /* DE_META */ 5507 3 + /* CNTX_CTRL */ 5508 5 + /* HDP_INVL */ 5509 8 + 8 + /* FENCE x2 */ 5510 8 + /* gfx_v12_0_emit_mem_sync */ 5511 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5512 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5513 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5514 .emit_fence = gfx_v12_0_ring_emit_fence, 5515 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5516 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5517 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5518 .test_ring = gfx_v12_0_ring_test_ring, 5519 .test_ib = gfx_v12_0_ring_test_ib, 5520 .insert_nop = gfx_v12_ring_insert_nop, 5521 .pad_ib = amdgpu_ring_generic_pad_ib, 5522 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5523 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5524 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5525 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5526 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5527 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5528 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5529 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5530 .reset = gfx_v12_0_reset_kgq, 5531 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5532 .begin_use = gfx_v12_0_ring_begin_use, 5533 .end_use = gfx_v12_0_ring_end_use, 5534 }; 5535 5536 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5537 .type = AMDGPU_RING_TYPE_COMPUTE, 5538 .align_mask = 0xff, 5539 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5540 .support_64bit_ptrs = true, 5541 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5542 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5543 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5544 .emit_frame_size = 5545 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5546 5 + /* hdp invalidate */ 5547 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5548 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5549 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5550 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5551 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5552 8 + /* gfx_v12_0_emit_mem_sync */ 5553 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5554 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5555 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5556 .emit_fence = gfx_v12_0_ring_emit_fence, 5557 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5558 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5559 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5560 .test_ring = gfx_v12_0_ring_test_ring, 5561 .test_ib = gfx_v12_0_ring_test_ib, 5562 .insert_nop = gfx_v12_ring_insert_nop, 5563 .pad_ib = amdgpu_ring_generic_pad_ib, 5564 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5565 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5566 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5567 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5568 .reset = gfx_v12_0_reset_kcq, 5569 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5570 .begin_use = gfx_v12_0_ring_begin_use, 5571 .end_use = gfx_v12_0_ring_end_use, 5572 }; 5573 5574 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5575 .type = AMDGPU_RING_TYPE_KIQ, 5576 .align_mask = 0xff, 5577 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5578 .support_64bit_ptrs = true, 5579 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5580 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5581 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5582 .emit_frame_size = 5583 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5584 5 + /*hdp invalidate */ 5585 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5586 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5587 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5588 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5589 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5590 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5591 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5592 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5593 .test_ring = gfx_v12_0_ring_test_ring, 5594 .test_ib = gfx_v12_0_ring_test_ib, 5595 .insert_nop = amdgpu_ring_insert_nop, 5596 .pad_ib = amdgpu_ring_generic_pad_ib, 5597 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5598 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5599 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5600 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5601 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5602 }; 5603 5604 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5605 { 5606 int i; 5607 5608 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5609 5610 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5611 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5612 5613 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5614 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5615 } 5616 5617 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5618 .set = gfx_v12_0_set_eop_interrupt_state, 5619 .process = gfx_v12_0_eop_irq, 5620 }; 5621 5622 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5623 .set = gfx_v12_0_set_priv_reg_fault_state, 5624 .process = gfx_v12_0_priv_reg_irq, 5625 }; 5626 5627 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5628 .set = gfx_v12_0_set_bad_op_fault_state, 5629 .process = gfx_v12_0_bad_op_irq, 5630 }; 5631 5632 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5633 .set = gfx_v12_0_set_priv_inst_fault_state, 5634 .process = gfx_v12_0_priv_inst_irq, 5635 }; 5636 5637 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5638 { 5639 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5640 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5641 5642 adev->gfx.priv_reg_irq.num_types = 1; 5643 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5644 5645 adev->gfx.bad_op_irq.num_types = 1; 5646 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5647 5648 adev->gfx.priv_inst_irq.num_types = 1; 5649 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5650 } 5651 5652 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5653 { 5654 if (adev->flags & AMD_IS_APU) 5655 adev->gfx.imu.mode = MISSION_MODE; 5656 else 5657 adev->gfx.imu.mode = DEBUG_MODE; 5658 5659 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5660 } 5661 5662 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5663 { 5664 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5665 } 5666 5667 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5668 { 5669 /* set gfx eng mqd */ 5670 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5671 sizeof(struct v12_gfx_mqd); 5672 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5673 gfx_v12_0_gfx_mqd_init; 5674 /* set compute eng mqd */ 5675 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5676 sizeof(struct v12_compute_mqd); 5677 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5678 gfx_v12_0_compute_mqd_init; 5679 } 5680 5681 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5682 u32 bitmap) 5683 { 5684 u32 data; 5685 5686 if (!bitmap) 5687 return; 5688 5689 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5690 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5691 5692 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5693 } 5694 5695 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5696 { 5697 u32 data, wgp_bitmask; 5698 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5699 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5700 5701 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5702 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5703 5704 wgp_bitmask = 5705 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5706 5707 return (~data) & wgp_bitmask; 5708 } 5709 5710 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5711 { 5712 u32 wgp_idx, wgp_active_bitmap; 5713 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5714 5715 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5716 cu_active_bitmap = 0; 5717 5718 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5719 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5720 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5721 if (wgp_active_bitmap & (1 << wgp_idx)) 5722 cu_active_bitmap |= cu_bitmap_per_wgp; 5723 } 5724 5725 return cu_active_bitmap; 5726 } 5727 5728 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5729 struct amdgpu_cu_info *cu_info) 5730 { 5731 int i, j, k, counter, active_cu_number = 0; 5732 u32 mask, bitmap; 5733 unsigned disable_masks[8 * 2]; 5734 5735 if (!adev || !cu_info) 5736 return -EINVAL; 5737 5738 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5739 5740 mutex_lock(&adev->grbm_idx_mutex); 5741 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5742 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5743 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5744 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5745 continue; 5746 mask = 1; 5747 counter = 0; 5748 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5749 if (i < 8 && j < 2) 5750 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5751 adev, disable_masks[i * 2 + j]); 5752 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5753 5754 /** 5755 * GFX12 could support more than 4 SEs, while the bitmap 5756 * in cu_info struct is 4x4 and ioctl interface struct 5757 * drm_amdgpu_info_device should keep stable. 5758 * So we use last two columns of bitmap to store cu mask for 5759 * SEs 4 to 7, the layout of the bitmap is as below: 5760 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5761 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5762 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5763 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5764 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5765 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5766 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5767 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5768 */ 5769 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5770 5771 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5772 if (bitmap & mask) 5773 counter++; 5774 5775 mask <<= 1; 5776 } 5777 active_cu_number += counter; 5778 } 5779 } 5780 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5781 mutex_unlock(&adev->grbm_idx_mutex); 5782 5783 cu_info->number = active_cu_number; 5784 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5785 5786 return 0; 5787 } 5788 5789 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5790 .type = AMD_IP_BLOCK_TYPE_GFX, 5791 .major = 12, 5792 .minor = 0, 5793 .rev = 0, 5794 .funcs = &gfx_v12_0_ip_funcs, 5795 }; 5796