1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 48 #define GFX12_NUM_GFX_RINGS 1 49 #define GFX12_MEC_HPD_SIZE 2048 50 51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 52 53 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 54 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 55 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 56 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 57 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 58 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 59 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 60 61 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 62 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 63 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 64 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 65 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 66 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 67 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 68 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 69 70 71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 81 82 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 83 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 84 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 114 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 118 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 121 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 124 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 136 /* cp header registers */ 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 /* SE status registers */ 146 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 147 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 150 }; 151 152 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 153 /* compute registers */ 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 193 /* cp header registers */ 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 }; 203 204 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 205 /* gfx queue registers */ 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 231 /* cp header registers */ 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 }; 249 250 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 251 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 254 }; 255 256 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 257 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 258 }; 259 260 #define DEFAULT_SH_MEM_CONFIG \ 261 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 262 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 263 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 264 265 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 266 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 267 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 268 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 271 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 272 struct amdgpu_cu_info *cu_info); 273 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 274 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 275 u32 sh_num, u32 instance, int xcc_id); 276 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 277 278 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 279 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 280 uint32_t val); 281 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 282 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 283 uint16_t pasid, uint32_t flush_type, 284 bool all_hub, uint8_t dst_sel); 285 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 286 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 287 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 288 bool enable); 289 290 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 291 uint64_t queue_mask) 292 { 293 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 294 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 295 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 296 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 297 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 298 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 299 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 301 amdgpu_ring_write(kiq_ring, 0); 302 } 303 304 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 305 struct amdgpu_ring *ring) 306 { 307 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 308 uint64_t wptr_addr = ring->wptr_gpu_addr; 309 uint32_t me = 0, eng_sel = 0; 310 311 switch (ring->funcs->type) { 312 case AMDGPU_RING_TYPE_COMPUTE: 313 me = 1; 314 eng_sel = 0; 315 break; 316 case AMDGPU_RING_TYPE_GFX: 317 me = 0; 318 eng_sel = 4; 319 break; 320 case AMDGPU_RING_TYPE_MES: 321 me = 2; 322 eng_sel = 5; 323 break; 324 default: 325 WARN_ON(1); 326 } 327 328 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 329 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 330 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 331 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 332 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 333 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 334 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 335 PACKET3_MAP_QUEUES_ME((me)) | 336 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 337 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 338 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 339 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 340 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 341 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 345 } 346 347 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 348 struct amdgpu_ring *ring, 349 enum amdgpu_unmap_queues_action action, 350 u64 gpu_addr, u64 seq) 351 { 352 struct amdgpu_device *adev = kiq_ring->adev; 353 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 354 355 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 356 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 357 return; 358 } 359 360 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 361 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 362 PACKET3_UNMAP_QUEUES_ACTION(action) | 363 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 364 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 365 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 366 amdgpu_ring_write(kiq_ring, 367 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 368 369 if (action == PREEMPT_QUEUES_NO_UNMAP) { 370 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 371 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 372 amdgpu_ring_write(kiq_ring, seq); 373 } else { 374 amdgpu_ring_write(kiq_ring, 0); 375 amdgpu_ring_write(kiq_ring, 0); 376 amdgpu_ring_write(kiq_ring, 0); 377 } 378 } 379 380 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 381 struct amdgpu_ring *ring, 382 u64 addr, u64 seq) 383 { 384 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 385 386 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 387 amdgpu_ring_write(kiq_ring, 388 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 389 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 390 PACKET3_QUERY_STATUS_COMMAND(2)); 391 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 392 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 393 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 394 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 395 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 396 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 397 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 398 } 399 400 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 401 uint16_t pasid, 402 uint32_t flush_type, 403 bool all_hub) 404 { 405 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 406 } 407 408 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 409 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 410 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 411 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 412 .kiq_query_status = gfx_v12_0_kiq_query_status, 413 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 414 .set_resources_size = 8, 415 .map_queues_size = 7, 416 .unmap_queues_size = 6, 417 .query_status_size = 7, 418 .invalidate_tlbs_size = 2, 419 }; 420 421 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 422 { 423 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 424 } 425 426 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 427 int mem_space, int opt, uint32_t addr0, 428 uint32_t addr1, uint32_t ref, 429 uint32_t mask, uint32_t inv) 430 { 431 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 432 amdgpu_ring_write(ring, 433 /* memory (1) or register (0) */ 434 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 435 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 436 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 437 WAIT_REG_MEM_ENGINE(eng_sel))); 438 439 if (mem_space) 440 BUG_ON(addr0 & 0x3); /* Dword align */ 441 amdgpu_ring_write(ring, addr0); 442 amdgpu_ring_write(ring, addr1); 443 amdgpu_ring_write(ring, ref); 444 amdgpu_ring_write(ring, mask); 445 amdgpu_ring_write(ring, inv); /* poll interval */ 446 } 447 448 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 449 { 450 struct amdgpu_device *adev = ring->adev; 451 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 452 uint32_t tmp = 0; 453 unsigned i; 454 int r; 455 456 WREG32(scratch, 0xCAFEDEAD); 457 r = amdgpu_ring_alloc(ring, 5); 458 if (r) { 459 dev_err(adev->dev, 460 "amdgpu: cp failed to lock ring %d (%d).\n", 461 ring->idx, r); 462 return r; 463 } 464 465 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 466 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 467 } else { 468 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 469 amdgpu_ring_write(ring, scratch - 470 PACKET3_SET_UCONFIG_REG_START); 471 amdgpu_ring_write(ring, 0xDEADBEEF); 472 } 473 amdgpu_ring_commit(ring); 474 475 for (i = 0; i < adev->usec_timeout; i++) { 476 tmp = RREG32(scratch); 477 if (tmp == 0xDEADBEEF) 478 break; 479 if (amdgpu_emu_mode == 1) 480 msleep(1); 481 else 482 udelay(1); 483 } 484 485 if (i >= adev->usec_timeout) 486 r = -ETIMEDOUT; 487 return r; 488 } 489 490 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 491 { 492 struct amdgpu_device *adev = ring->adev; 493 struct amdgpu_ib ib; 494 struct dma_fence *f = NULL; 495 unsigned index; 496 uint64_t gpu_addr; 497 volatile uint32_t *cpu_ptr; 498 long r; 499 500 /* MES KIQ fw hasn't indirect buffer support for now */ 501 if (adev->enable_mes_kiq && 502 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 503 return 0; 504 505 memset(&ib, 0, sizeof(ib)); 506 507 if (ring->is_mes_queue) { 508 uint32_t padding, offset; 509 510 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 511 padding = amdgpu_mes_ctx_get_offs(ring, 512 AMDGPU_MES_CTX_PADDING_OFFS); 513 514 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 515 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 516 517 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 518 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 519 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 520 } else { 521 r = amdgpu_device_wb_get(adev, &index); 522 if (r) 523 return r; 524 525 gpu_addr = adev->wb.gpu_addr + (index * 4); 526 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 527 cpu_ptr = &adev->wb.wb[index]; 528 529 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 530 if (r) { 531 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 532 goto err1; 533 } 534 } 535 536 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 537 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 538 ib.ptr[2] = lower_32_bits(gpu_addr); 539 ib.ptr[3] = upper_32_bits(gpu_addr); 540 ib.ptr[4] = 0xDEADBEEF; 541 ib.length_dw = 5; 542 543 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 544 if (r) 545 goto err2; 546 547 r = dma_fence_wait_timeout(f, false, timeout); 548 if (r == 0) { 549 r = -ETIMEDOUT; 550 goto err2; 551 } else if (r < 0) { 552 goto err2; 553 } 554 555 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 556 r = 0; 557 else 558 r = -EINVAL; 559 err2: 560 if (!ring->is_mes_queue) 561 amdgpu_ib_free(&ib, NULL); 562 dma_fence_put(f); 563 err1: 564 if (!ring->is_mes_queue) 565 amdgpu_device_wb_free(adev, index); 566 return r; 567 } 568 569 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 570 { 571 amdgpu_ucode_release(&adev->gfx.pfp_fw); 572 amdgpu_ucode_release(&adev->gfx.me_fw); 573 amdgpu_ucode_release(&adev->gfx.rlc_fw); 574 amdgpu_ucode_release(&adev->gfx.mec_fw); 575 576 kfree(adev->gfx.rlc.register_list_format); 577 } 578 579 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 580 { 581 const struct psp_firmware_header_v1_0 *toc_hdr; 582 int err = 0; 583 584 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 585 AMDGPU_UCODE_REQUIRED, 586 "amdgpu/%s_toc.bin", ucode_prefix); 587 if (err) 588 goto out; 589 590 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 591 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 592 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 593 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 594 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 595 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 596 return 0; 597 out: 598 amdgpu_ucode_release(&adev->psp.toc_fw); 599 return err; 600 } 601 602 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 603 { 604 char ucode_prefix[15]; 605 int err; 606 const struct rlc_firmware_header_v2_0 *rlc_hdr; 607 uint16_t version_major; 608 uint16_t version_minor; 609 610 DRM_DEBUG("\n"); 611 612 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 613 614 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 615 AMDGPU_UCODE_REQUIRED, 616 "amdgpu/%s_pfp.bin", ucode_prefix); 617 if (err) 618 goto out; 619 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 621 622 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 623 AMDGPU_UCODE_REQUIRED, 624 "amdgpu/%s_me.bin", ucode_prefix); 625 if (err) 626 goto out; 627 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 628 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 629 630 if (!amdgpu_sriov_vf(adev)) { 631 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 632 AMDGPU_UCODE_REQUIRED, 633 "amdgpu/%s_rlc.bin", ucode_prefix); 634 if (err) 635 goto out; 636 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 637 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 638 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 639 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 640 if (err) 641 goto out; 642 } 643 644 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 645 AMDGPU_UCODE_REQUIRED, 646 "amdgpu/%s_mec.bin", ucode_prefix); 647 if (err) 648 goto out; 649 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 650 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 651 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 652 653 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 654 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 655 656 /* only one MEC for gfx 12 */ 657 adev->gfx.mec2_fw = NULL; 658 659 if (adev->gfx.imu.funcs) { 660 if (adev->gfx.imu.funcs->init_microcode) { 661 err = adev->gfx.imu.funcs->init_microcode(adev); 662 if (err) 663 dev_err(adev->dev, "Failed to load imu firmware!\n"); 664 } 665 } 666 667 out: 668 if (err) { 669 amdgpu_ucode_release(&adev->gfx.pfp_fw); 670 amdgpu_ucode_release(&adev->gfx.me_fw); 671 amdgpu_ucode_release(&adev->gfx.rlc_fw); 672 amdgpu_ucode_release(&adev->gfx.mec_fw); 673 } 674 675 return err; 676 } 677 678 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 679 { 680 u32 count = 0; 681 const struct cs_section_def *sect = NULL; 682 const struct cs_extent_def *ext = NULL; 683 684 count += 1; 685 686 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 687 if (sect->id == SECT_CONTEXT) { 688 for (ext = sect->section; ext->extent != NULL; ++ext) 689 count += 2 + ext->reg_count; 690 } else 691 return 0; 692 } 693 694 return count; 695 } 696 697 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 698 volatile u32 *buffer) 699 { 700 u32 count = 0, clustercount = 0, i; 701 const struct cs_section_def *sect = NULL; 702 const struct cs_extent_def *ext = NULL; 703 704 if (adev->gfx.rlc.cs_data == NULL) 705 return; 706 if (buffer == NULL) 707 return; 708 709 count += 1; 710 711 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 712 if (sect->id == SECT_CONTEXT) { 713 for (ext = sect->section; ext->extent != NULL; ++ext) { 714 clustercount++; 715 buffer[count++] = ext->reg_count; 716 buffer[count++] = ext->reg_index; 717 718 for (i = 0; i < ext->reg_count; i++) 719 buffer[count++] = cpu_to_le32(ext->extent[i]); 720 } 721 } else 722 return; 723 } 724 725 buffer[0] = clustercount; 726 } 727 728 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 729 { 730 /* clear state block */ 731 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 732 &adev->gfx.rlc.clear_state_gpu_addr, 733 (void **)&adev->gfx.rlc.cs_ptr); 734 735 /* jump table block */ 736 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 737 &adev->gfx.rlc.cp_table_gpu_addr, 738 (void **)&adev->gfx.rlc.cp_table_ptr); 739 } 740 741 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 742 { 743 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 744 745 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 746 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 747 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 748 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 749 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 750 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 751 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 752 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 753 adev->gfx.rlc.rlcg_reg_access_supported = true; 754 } 755 756 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 757 { 758 const struct cs_section_def *cs_data; 759 int r; 760 761 adev->gfx.rlc.cs_data = gfx12_cs_data; 762 763 cs_data = adev->gfx.rlc.cs_data; 764 765 if (cs_data) { 766 /* init clear state block */ 767 r = amdgpu_gfx_rlc_init_csb(adev); 768 if (r) 769 return r; 770 } 771 772 /* init spm vmid with 0xf */ 773 if (adev->gfx.rlc.funcs->update_spm_vmid) 774 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 775 776 return 0; 777 } 778 779 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 780 { 781 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 782 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 783 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 784 } 785 786 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 787 { 788 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 789 790 amdgpu_gfx_graphics_queue_acquire(adev); 791 } 792 793 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 794 { 795 int r; 796 u32 *hpd; 797 size_t mec_hpd_size; 798 799 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 800 801 /* take ownership of the relevant compute queues */ 802 amdgpu_gfx_compute_queue_acquire(adev); 803 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 804 805 if (mec_hpd_size) { 806 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 807 AMDGPU_GEM_DOMAIN_GTT, 808 &adev->gfx.mec.hpd_eop_obj, 809 &adev->gfx.mec.hpd_eop_gpu_addr, 810 (void **)&hpd); 811 if (r) { 812 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 813 gfx_v12_0_mec_fini(adev); 814 return r; 815 } 816 817 memset(hpd, 0, mec_hpd_size); 818 819 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 820 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 821 } 822 823 return 0; 824 } 825 826 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 827 { 828 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 829 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 830 (address << SQ_IND_INDEX__INDEX__SHIFT)); 831 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 832 } 833 834 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 835 uint32_t thread, uint32_t regno, 836 uint32_t num, uint32_t *out) 837 { 838 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 839 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 840 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 841 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 842 (SQ_IND_INDEX__AUTO_INCR_MASK)); 843 while (num--) 844 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 845 } 846 847 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 848 uint32_t xcc_id, 849 uint32_t simd, uint32_t wave, 850 uint32_t *dst, int *no_fields) 851 { 852 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 853 * field when performing a select_se_sh so it should be 854 * zero here */ 855 WARN_ON(simd != 0); 856 857 /* type 4 wave data */ 858 dst[(*no_fields)++] = 4; 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 873 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 874 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 875 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 876 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 877 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 878 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 879 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 880 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 881 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 882 } 883 884 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 885 uint32_t xcc_id, uint32_t simd, 886 uint32_t wave, uint32_t start, 887 uint32_t size, uint32_t *dst) 888 { 889 WARN_ON(simd != 0); 890 891 wave_read_regs( 892 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 893 dst); 894 } 895 896 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 897 uint32_t xcc_id, uint32_t simd, 898 uint32_t wave, uint32_t thread, 899 uint32_t start, uint32_t size, 900 uint32_t *dst) 901 { 902 wave_read_regs( 903 adev, wave, thread, 904 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 905 } 906 907 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 908 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 909 { 910 soc24_grbm_select(adev, me, pipe, q, vm); 911 } 912 913 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 914 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 915 .select_se_sh = &gfx_v12_0_select_se_sh, 916 .read_wave_data = &gfx_v12_0_read_wave_data, 917 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 918 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 919 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 920 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 921 }; 922 923 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 924 { 925 926 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 927 case IP_VERSION(12, 0, 0): 928 case IP_VERSION(12, 0, 1): 929 adev->gfx.config.max_hw_contexts = 8; 930 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 931 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 932 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 933 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 934 break; 935 default: 936 BUG(); 937 break; 938 } 939 940 return 0; 941 } 942 943 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 944 int me, int pipe, int queue) 945 { 946 int r; 947 struct amdgpu_ring *ring; 948 unsigned int irq_type; 949 950 ring = &adev->gfx.gfx_ring[ring_id]; 951 952 ring->me = me; 953 ring->pipe = pipe; 954 ring->queue = queue; 955 956 ring->ring_obj = NULL; 957 ring->use_doorbell = true; 958 959 if (!ring_id) 960 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 961 else 962 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 963 ring->vm_hub = AMDGPU_GFXHUB(0); 964 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 965 966 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 967 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 968 AMDGPU_RING_PRIO_DEFAULT, NULL); 969 if (r) 970 return r; 971 return 0; 972 } 973 974 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 975 int mec, int pipe, int queue) 976 { 977 int r; 978 unsigned irq_type; 979 struct amdgpu_ring *ring; 980 unsigned int hw_prio; 981 982 ring = &adev->gfx.compute_ring[ring_id]; 983 984 /* mec0 is me1 */ 985 ring->me = mec + 1; 986 ring->pipe = pipe; 987 ring->queue = queue; 988 989 ring->ring_obj = NULL; 990 ring->use_doorbell = true; 991 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 992 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 993 + (ring_id * GFX12_MEC_HPD_SIZE); 994 ring->vm_hub = AMDGPU_GFXHUB(0); 995 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 996 997 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 998 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 999 + ring->pipe; 1000 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1001 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1002 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1003 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1004 hw_prio, NULL); 1005 if (r) 1006 return r; 1007 1008 return 0; 1009 } 1010 1011 static struct { 1012 SOC24_FIRMWARE_ID id; 1013 unsigned int offset; 1014 unsigned int size; 1015 unsigned int size_x16; 1016 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1017 1018 #define RLC_TOC_OFFSET_DWUNIT 8 1019 #define RLC_SIZE_MULTIPLE 1024 1020 #define RLC_TOC_UMF_SIZE_inM 23ULL 1021 #define RLC_TOC_FORMAT_API 165ULL 1022 1023 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1024 { 1025 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1026 1027 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1028 rlc_autoload_info[ucode->id].id = ucode->id; 1029 rlc_autoload_info[ucode->id].offset = 1030 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1031 rlc_autoload_info[ucode->id].size = 1032 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1033 ucode->size * 4; 1034 ucode++; 1035 } 1036 } 1037 1038 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1039 { 1040 uint32_t total_size = 0; 1041 SOC24_FIRMWARE_ID id; 1042 1043 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1044 1045 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1046 total_size += rlc_autoload_info[id].size; 1047 1048 /* In case the offset in rlc toc ucode is aligned */ 1049 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1050 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1051 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1052 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1053 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1054 1055 return total_size; 1056 } 1057 1058 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1059 { 1060 int r; 1061 uint32_t total_size; 1062 1063 total_size = gfx_v12_0_calc_toc_total_size(adev); 1064 1065 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1066 AMDGPU_GEM_DOMAIN_VRAM, 1067 &adev->gfx.rlc.rlc_autoload_bo, 1068 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1069 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1070 1071 if (r) { 1072 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1073 return r; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1080 SOC24_FIRMWARE_ID id, 1081 const void *fw_data, 1082 uint32_t fw_size) 1083 { 1084 uint32_t toc_offset; 1085 uint32_t toc_fw_size; 1086 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1087 1088 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1089 return; 1090 1091 toc_offset = rlc_autoload_info[id].offset; 1092 toc_fw_size = rlc_autoload_info[id].size; 1093 1094 if (fw_size == 0) 1095 fw_size = toc_fw_size; 1096 1097 if (fw_size > toc_fw_size) 1098 fw_size = toc_fw_size; 1099 1100 memcpy(ptr + toc_offset, fw_data, fw_size); 1101 1102 if (fw_size < toc_fw_size) 1103 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1104 } 1105 1106 static void 1107 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1108 { 1109 void *data; 1110 uint32_t size; 1111 uint32_t *toc_ptr; 1112 1113 data = adev->psp.toc.start_addr; 1114 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1115 1116 toc_ptr = (uint32_t *)data + size / 4 - 2; 1117 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1118 1119 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1120 data, size); 1121 } 1122 1123 static void 1124 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1125 { 1126 const __le32 *fw_data; 1127 uint32_t fw_size; 1128 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1129 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1130 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1131 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1132 uint16_t version_major, version_minor; 1133 1134 /* pfp ucode */ 1135 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1136 adev->gfx.pfp_fw->data; 1137 /* instruction */ 1138 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1139 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1140 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1141 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1142 fw_data, fw_size); 1143 /* data */ 1144 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1145 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1146 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1147 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1148 fw_data, fw_size); 1149 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1150 fw_data, fw_size); 1151 /* me ucode */ 1152 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1153 adev->gfx.me_fw->data; 1154 /* instruction */ 1155 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1156 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1157 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1158 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1159 fw_data, fw_size); 1160 /* data */ 1161 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1162 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1163 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1164 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1165 fw_data, fw_size); 1166 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1167 fw_data, fw_size); 1168 /* mec ucode */ 1169 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1170 adev->gfx.mec_fw->data; 1171 /* instruction */ 1172 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1173 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1174 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1175 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1176 fw_data, fw_size); 1177 /* data */ 1178 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1179 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1180 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1181 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1182 fw_data, fw_size); 1183 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1184 fw_data, fw_size); 1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1186 fw_data, fw_size); 1187 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1188 fw_data, fw_size); 1189 1190 /* rlc ucode */ 1191 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1192 adev->gfx.rlc_fw->data; 1193 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1194 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1195 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1196 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1197 fw_data, fw_size); 1198 1199 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1200 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1201 if (version_major == 2) { 1202 if (version_minor >= 1) { 1203 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1204 1205 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1206 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1207 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1208 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1209 fw_data, fw_size); 1210 1211 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1212 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1213 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1214 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1215 fw_data, fw_size); 1216 } 1217 if (version_minor >= 2) { 1218 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1219 1220 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1221 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1222 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1223 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1224 fw_data, fw_size); 1225 1226 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1227 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1228 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1229 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1230 fw_data, fw_size); 1231 } 1232 } 1233 } 1234 1235 static void 1236 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1237 { 1238 const __le32 *fw_data; 1239 uint32_t fw_size; 1240 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1241 1242 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1243 adev->sdma.instance[0].fw->data; 1244 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1245 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1246 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1247 1248 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1249 fw_data, fw_size); 1250 } 1251 1252 static void 1253 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1254 { 1255 const __le32 *fw_data; 1256 unsigned fw_size; 1257 const struct mes_firmware_header_v1_0 *mes_hdr; 1258 int pipe, ucode_id, data_id; 1259 1260 for (pipe = 0; pipe < 2; pipe++) { 1261 if (pipe == 0) { 1262 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1263 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1264 } else { 1265 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1266 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1267 } 1268 1269 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1270 adev->mes.fw[pipe]->data; 1271 1272 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1273 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1274 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1275 1276 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1277 1278 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1279 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1280 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1281 1282 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1283 } 1284 } 1285 1286 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1287 { 1288 uint32_t rlc_g_offset, rlc_g_size; 1289 uint64_t gpu_addr; 1290 uint32_t data; 1291 1292 /* RLC autoload sequence 2: copy ucode */ 1293 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1294 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1295 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1296 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1297 1298 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1299 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1300 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1301 1302 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1303 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1304 1305 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1306 1307 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1308 /* RLC autoload sequence 3: load IMU fw */ 1309 if (adev->gfx.imu.funcs->load_microcode) 1310 adev->gfx.imu.funcs->load_microcode(adev); 1311 /* RLC autoload sequence 4 init IMU fw */ 1312 if (adev->gfx.imu.funcs->setup_imu) 1313 adev->gfx.imu.funcs->setup_imu(adev); 1314 if (adev->gfx.imu.funcs->start_imu) 1315 adev->gfx.imu.funcs->start_imu(adev); 1316 1317 /* RLC autoload sequence 5 disable gpa mode */ 1318 gfx_v12_0_disable_gpa_mode(adev); 1319 } else { 1320 /* unhalt rlc to start autoload without imu */ 1321 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1322 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1323 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1324 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1325 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1332 { 1333 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1334 uint32_t *ptr; 1335 uint32_t inst; 1336 1337 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1338 if (!ptr) { 1339 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1340 adev->gfx.ip_dump_core = NULL; 1341 } else { 1342 adev->gfx.ip_dump_core = ptr; 1343 } 1344 1345 /* Allocate memory for compute queue registers for all the instances */ 1346 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1347 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1348 adev->gfx.mec.num_queue_per_pipe; 1349 1350 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1351 if (!ptr) { 1352 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1353 adev->gfx.ip_dump_compute_queues = NULL; 1354 } else { 1355 adev->gfx.ip_dump_compute_queues = ptr; 1356 } 1357 1358 /* Allocate memory for gfx queue registers for all the instances */ 1359 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1360 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1361 adev->gfx.me.num_queue_per_pipe; 1362 1363 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1364 if (!ptr) { 1365 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1366 adev->gfx.ip_dump_gfx_queues = NULL; 1367 } else { 1368 adev->gfx.ip_dump_gfx_queues = ptr; 1369 } 1370 } 1371 1372 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1373 { 1374 int i, j, k, r, ring_id = 0; 1375 unsigned num_compute_rings; 1376 int xcc_id = 0; 1377 struct amdgpu_device *adev = ip_block->adev; 1378 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1379 1380 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1381 1382 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1383 case IP_VERSION(12, 0, 0): 1384 case IP_VERSION(12, 0, 1): 1385 adev->gfx.me.num_me = 1; 1386 adev->gfx.me.num_pipe_per_me = 1; 1387 adev->gfx.me.num_queue_per_pipe = 8; 1388 adev->gfx.mec.num_mec = 1; 1389 adev->gfx.mec.num_pipe_per_mec = 2; 1390 adev->gfx.mec.num_queue_per_pipe = 4; 1391 break; 1392 default: 1393 adev->gfx.me.num_me = 1; 1394 adev->gfx.me.num_pipe_per_me = 1; 1395 adev->gfx.me.num_queue_per_pipe = 1; 1396 adev->gfx.mec.num_mec = 1; 1397 adev->gfx.mec.num_pipe_per_mec = 4; 1398 adev->gfx.mec.num_queue_per_pipe = 8; 1399 break; 1400 } 1401 1402 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1403 case IP_VERSION(12, 0, 0): 1404 case IP_VERSION(12, 0, 1): 1405 if (adev->gfx.me_fw_version >= 2480 && 1406 adev->gfx.pfp_fw_version >= 2530 && 1407 adev->gfx.mec_fw_version >= 2680 && 1408 adev->mes.fw_version[0] >= 100) 1409 adev->gfx.enable_cleaner_shader = true; 1410 break; 1411 default: 1412 adev->gfx.enable_cleaner_shader = false; 1413 break; 1414 } 1415 1416 /* recalculate compute rings to use based on hardware configuration */ 1417 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1418 adev->gfx.mec.num_queue_per_pipe) / 2; 1419 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1420 num_compute_rings); 1421 1422 /* EOP Event */ 1423 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1424 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1425 &adev->gfx.eop_irq); 1426 if (r) 1427 return r; 1428 1429 /* Bad opcode Event */ 1430 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1431 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1432 &adev->gfx.bad_op_irq); 1433 if (r) 1434 return r; 1435 1436 /* Privileged reg */ 1437 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1438 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1439 &adev->gfx.priv_reg_irq); 1440 if (r) 1441 return r; 1442 1443 /* Privileged inst */ 1444 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1445 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1446 &adev->gfx.priv_inst_irq); 1447 if (r) 1448 return r; 1449 1450 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1451 1452 gfx_v12_0_me_init(adev); 1453 1454 r = gfx_v12_0_rlc_init(adev); 1455 if (r) { 1456 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1457 return r; 1458 } 1459 1460 r = gfx_v12_0_mec_init(adev); 1461 if (r) { 1462 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1463 return r; 1464 } 1465 1466 /* set up the gfx ring */ 1467 for (i = 0; i < adev->gfx.me.num_me; i++) { 1468 for (j = 0; j < num_queue_per_pipe; j++) { 1469 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1470 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1471 continue; 1472 1473 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1474 i, k, j); 1475 if (r) 1476 return r; 1477 ring_id++; 1478 } 1479 } 1480 } 1481 1482 ring_id = 0; 1483 /* set up the compute queues - allocate horizontally across pipes */ 1484 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1485 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1486 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1487 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1488 0, i, k, j)) 1489 continue; 1490 1491 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1492 i, k, j); 1493 if (r) 1494 return r; 1495 1496 ring_id++; 1497 } 1498 } 1499 } 1500 1501 adev->gfx.gfx_supported_reset = 1502 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1503 adev->gfx.compute_supported_reset = 1504 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1505 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1506 case IP_VERSION(12, 0, 0): 1507 case IP_VERSION(12, 0, 1): 1508 if ((adev->gfx.me_fw_version >= 2660) && 1509 (adev->gfx.mec_fw_version >= 2920)) { 1510 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1511 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1512 } 1513 } 1514 1515 if (!adev->enable_mes_kiq) { 1516 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1517 if (r) { 1518 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1519 return r; 1520 } 1521 1522 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1523 if (r) 1524 return r; 1525 } 1526 1527 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1528 if (r) 1529 return r; 1530 1531 /* allocate visible FB for rlc auto-loading fw */ 1532 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1533 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1534 if (r) 1535 return r; 1536 } 1537 1538 r = gfx_v12_0_gpu_early_init(adev); 1539 if (r) 1540 return r; 1541 1542 gfx_v12_0_alloc_ip_dump(adev); 1543 1544 r = amdgpu_gfx_sysfs_init(adev); 1545 if (r) 1546 return r; 1547 1548 return 0; 1549 } 1550 1551 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1552 { 1553 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1554 &adev->gfx.pfp.pfp_fw_gpu_addr, 1555 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1556 1557 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1558 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1559 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1560 } 1561 1562 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1563 { 1564 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1565 &adev->gfx.me.me_fw_gpu_addr, 1566 (void **)&adev->gfx.me.me_fw_ptr); 1567 1568 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1569 &adev->gfx.me.me_fw_data_gpu_addr, 1570 (void **)&adev->gfx.me.me_fw_data_ptr); 1571 } 1572 1573 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1574 { 1575 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1576 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1577 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1578 } 1579 1580 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1581 { 1582 int i; 1583 struct amdgpu_device *adev = ip_block->adev; 1584 1585 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1586 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1587 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1588 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1589 1590 amdgpu_gfx_mqd_sw_fini(adev, 0); 1591 1592 if (!adev->enable_mes_kiq) { 1593 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1594 amdgpu_gfx_kiq_fini(adev, 0); 1595 } 1596 1597 gfx_v12_0_pfp_fini(adev); 1598 gfx_v12_0_me_fini(adev); 1599 gfx_v12_0_rlc_fini(adev); 1600 gfx_v12_0_mec_fini(adev); 1601 1602 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1603 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1604 1605 gfx_v12_0_free_microcode(adev); 1606 1607 amdgpu_gfx_sysfs_fini(adev); 1608 1609 kfree(adev->gfx.ip_dump_core); 1610 kfree(adev->gfx.ip_dump_compute_queues); 1611 kfree(adev->gfx.ip_dump_gfx_queues); 1612 1613 return 0; 1614 } 1615 1616 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1617 u32 sh_num, u32 instance, int xcc_id) 1618 { 1619 u32 data; 1620 1621 if (instance == 0xffffffff) 1622 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1623 INSTANCE_BROADCAST_WRITES, 1); 1624 else 1625 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1626 instance); 1627 1628 if (se_num == 0xffffffff) 1629 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1630 1); 1631 else 1632 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1633 1634 if (sh_num == 0xffffffff) 1635 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1636 1); 1637 else 1638 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1639 1640 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1641 } 1642 1643 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1644 { 1645 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1646 1647 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1648 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1649 GRBM_CC_GC_SA_UNIT_DISABLE, 1650 SA_DISABLE); 1651 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1652 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1653 GRBM_GC_USER_SA_UNIT_DISABLE, 1654 SA_DISABLE); 1655 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1656 adev->gfx.config.max_shader_engines); 1657 1658 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1659 } 1660 1661 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1662 { 1663 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1664 u32 rb_mask; 1665 1666 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1667 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1668 CC_RB_BACKEND_DISABLE, 1669 BACKEND_DISABLE); 1670 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1671 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1672 GC_USER_RB_BACKEND_DISABLE, 1673 BACKEND_DISABLE); 1674 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1675 adev->gfx.config.max_shader_engines); 1676 1677 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1678 } 1679 1680 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1681 { 1682 u32 rb_bitmap_per_sa; 1683 u32 rb_bitmap_width_per_sa; 1684 u32 max_sa; 1685 u32 active_sa_bitmap; 1686 u32 global_active_rb_bitmap; 1687 u32 active_rb_bitmap = 0; 1688 u32 i; 1689 1690 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1691 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1692 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1693 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1694 1695 /* generate active rb bitmap according to active sa bitmap */ 1696 max_sa = adev->gfx.config.max_shader_engines * 1697 adev->gfx.config.max_sh_per_se; 1698 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1699 adev->gfx.config.max_sh_per_se; 1700 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1701 1702 for (i = 0; i < max_sa; i++) { 1703 if (active_sa_bitmap & (1 << i)) 1704 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1705 } 1706 1707 active_rb_bitmap &= global_active_rb_bitmap; 1708 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1709 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1710 } 1711 1712 #define LDS_APP_BASE 0x1 1713 #define SCRATCH_APP_BASE 0x2 1714 1715 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1716 { 1717 int i; 1718 uint32_t sh_mem_bases; 1719 uint32_t data; 1720 1721 /* 1722 * Configure apertures: 1723 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1724 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1725 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1726 */ 1727 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1728 SCRATCH_APP_BASE; 1729 1730 mutex_lock(&adev->srbm_mutex); 1731 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1732 soc24_grbm_select(adev, 0, 0, 0, i); 1733 /* CP and shaders */ 1734 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1735 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1736 1737 /* Enable trap for each kfd vmid. */ 1738 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1739 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1740 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1741 } 1742 soc24_grbm_select(adev, 0, 0, 0, 0); 1743 mutex_unlock(&adev->srbm_mutex); 1744 } 1745 1746 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1747 { 1748 /* TODO: harvest feature to be added later. */ 1749 } 1750 1751 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1752 { 1753 } 1754 1755 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1756 { 1757 u32 tmp; 1758 int i; 1759 1760 if (!amdgpu_sriov_vf(adev)) 1761 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1762 1763 gfx_v12_0_setup_rb(adev); 1764 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1765 gfx_v12_0_get_tcc_info(adev); 1766 adev->gfx.config.pa_sc_tile_steering_override = 0; 1767 1768 /* XXX SH_MEM regs */ 1769 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1770 mutex_lock(&adev->srbm_mutex); 1771 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1772 soc24_grbm_select(adev, 0, 0, 0, i); 1773 /* CP and shaders */ 1774 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1775 if (i != 0) { 1776 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1777 (adev->gmc.private_aperture_start >> 48)); 1778 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1779 (adev->gmc.shared_aperture_start >> 48)); 1780 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1781 } 1782 } 1783 soc24_grbm_select(adev, 0, 0, 0, 0); 1784 1785 mutex_unlock(&adev->srbm_mutex); 1786 1787 gfx_v12_0_init_compute_vmid(adev); 1788 } 1789 1790 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1791 int me, int pipe) 1792 { 1793 if (me != 0) 1794 return 0; 1795 1796 switch (pipe) { 1797 case 0: 1798 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1799 default: 1800 return 0; 1801 } 1802 } 1803 1804 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1805 int me, int pipe) 1806 { 1807 /* 1808 * amdgpu controls only the first MEC. That's why this function only 1809 * handles the setting of interrupts for this specific MEC. All other 1810 * pipes' interrupts are set by amdkfd. 1811 */ 1812 if (me != 1) 1813 return 0; 1814 1815 switch (pipe) { 1816 case 0: 1817 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1818 case 1: 1819 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1820 default: 1821 return 0; 1822 } 1823 } 1824 1825 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1826 bool enable) 1827 { 1828 u32 tmp, cp_int_cntl_reg; 1829 int i, j; 1830 1831 if (amdgpu_sriov_vf(adev)) 1832 return; 1833 1834 for (i = 0; i < adev->gfx.me.num_me; i++) { 1835 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1836 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1837 1838 if (cp_int_cntl_reg) { 1839 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1840 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1841 enable ? 1 : 0); 1842 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1843 enable ? 1 : 0); 1844 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1845 enable ? 1 : 0); 1846 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1847 enable ? 1 : 0); 1848 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1849 } 1850 } 1851 } 1852 } 1853 1854 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1855 { 1856 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1857 1858 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1859 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1860 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1861 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1862 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1863 1864 return 0; 1865 } 1866 1867 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1868 { 1869 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1870 1871 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1872 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1873 } 1874 1875 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1876 { 1877 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1878 udelay(50); 1879 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1880 udelay(50); 1881 } 1882 1883 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1884 bool enable) 1885 { 1886 uint32_t rlc_pg_cntl; 1887 1888 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1889 1890 if (!enable) { 1891 /* RLC_PG_CNTL[23] = 0 (default) 1892 * RLC will wait for handshake acks with SMU 1893 * GFXOFF will be enabled 1894 * RLC_PG_CNTL[23] = 1 1895 * RLC will not issue any message to SMU 1896 * hence no handshake between SMU & RLC 1897 * GFXOFF will be disabled 1898 */ 1899 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1900 } else 1901 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1902 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1903 } 1904 1905 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1906 { 1907 /* TODO: enable rlc & smu handshake until smu 1908 * and gfxoff feature works as expected */ 1909 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1910 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1911 1912 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1913 udelay(50); 1914 } 1915 1916 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1917 { 1918 uint32_t tmp; 1919 1920 /* enable Save Restore Machine */ 1921 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1922 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1923 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1924 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1925 } 1926 1927 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1928 { 1929 const struct rlc_firmware_header_v2_0 *hdr; 1930 const __le32 *fw_data; 1931 unsigned i, fw_size; 1932 1933 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1934 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1935 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1936 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1937 1938 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1939 RLCG_UCODE_LOADING_START_ADDRESS); 1940 1941 for (i = 0; i < fw_size; i++) 1942 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1943 le32_to_cpup(fw_data++)); 1944 1945 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1946 } 1947 1948 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1949 { 1950 const struct rlc_firmware_header_v2_2 *hdr; 1951 const __le32 *fw_data; 1952 unsigned i, fw_size; 1953 u32 tmp; 1954 1955 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1956 1957 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1958 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1959 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1960 1961 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1962 1963 for (i = 0; i < fw_size; i++) { 1964 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1965 msleep(1); 1966 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1967 le32_to_cpup(fw_data++)); 1968 } 1969 1970 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1971 1972 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1973 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1974 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1975 1976 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1977 for (i = 0; i < fw_size; i++) { 1978 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1979 msleep(1); 1980 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1981 le32_to_cpup(fw_data++)); 1982 } 1983 1984 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1985 1986 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1987 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1988 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1989 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1990 } 1991 1992 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1993 { 1994 const struct rlc_firmware_header_v2_0 *hdr; 1995 uint16_t version_major; 1996 uint16_t version_minor; 1997 1998 if (!adev->gfx.rlc_fw) 1999 return -EINVAL; 2000 2001 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2002 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2003 2004 version_major = le16_to_cpu(hdr->header.header_version_major); 2005 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2006 2007 if (version_major == 2) { 2008 gfx_v12_0_load_rlcg_microcode(adev); 2009 if (amdgpu_dpm == 1) { 2010 if (version_minor >= 2) 2011 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2012 } 2013 2014 return 0; 2015 } 2016 2017 return -EINVAL; 2018 } 2019 2020 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2021 { 2022 int r; 2023 2024 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2025 gfx_v12_0_init_csb(adev); 2026 2027 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2028 gfx_v12_0_rlc_enable_srm(adev); 2029 } else { 2030 if (amdgpu_sriov_vf(adev)) { 2031 gfx_v12_0_init_csb(adev); 2032 return 0; 2033 } 2034 2035 adev->gfx.rlc.funcs->stop(adev); 2036 2037 /* disable CG */ 2038 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2039 2040 /* disable PG */ 2041 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2042 2043 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2044 /* legacy rlc firmware loading */ 2045 r = gfx_v12_0_rlc_load_microcode(adev); 2046 if (r) 2047 return r; 2048 } 2049 2050 gfx_v12_0_init_csb(adev); 2051 2052 adev->gfx.rlc.funcs->start(adev); 2053 } 2054 2055 return 0; 2056 } 2057 2058 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2059 { 2060 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2061 const struct gfx_firmware_header_v2_0 *me_hdr; 2062 const struct gfx_firmware_header_v2_0 *mec_hdr; 2063 uint32_t pipe_id, tmp; 2064 2065 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2066 adev->gfx.mec_fw->data; 2067 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2068 adev->gfx.me_fw->data; 2069 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2070 adev->gfx.pfp_fw->data; 2071 2072 /* config pfp program start addr */ 2073 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2074 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2075 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2076 (pfp_hdr->ucode_start_addr_hi << 30) | 2077 (pfp_hdr->ucode_start_addr_lo >> 2)); 2078 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2079 pfp_hdr->ucode_start_addr_hi >> 2); 2080 } 2081 soc24_grbm_select(adev, 0, 0, 0, 0); 2082 2083 /* reset pfp pipe */ 2084 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2085 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2086 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2087 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2088 2089 /* clear pfp pipe reset */ 2090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2091 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2092 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2093 2094 /* config me program start addr */ 2095 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2096 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2097 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2098 (me_hdr->ucode_start_addr_hi << 30) | 2099 (me_hdr->ucode_start_addr_lo >> 2)); 2100 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2101 me_hdr->ucode_start_addr_hi>>2); 2102 } 2103 soc24_grbm_select(adev, 0, 0, 0, 0); 2104 2105 /* reset me pipe */ 2106 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2107 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2108 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2109 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2110 2111 /* clear me pipe reset */ 2112 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2113 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2114 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2115 2116 /* config mec program start addr */ 2117 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2118 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2119 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2120 mec_hdr->ucode_start_addr_lo >> 2 | 2121 mec_hdr->ucode_start_addr_hi << 30); 2122 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2123 mec_hdr->ucode_start_addr_hi >> 2); 2124 } 2125 soc24_grbm_select(adev, 0, 0, 0, 0); 2126 2127 /* reset mec pipe */ 2128 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2129 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2130 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2131 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2132 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2133 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2134 2135 /* clear mec pipe reset */ 2136 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2137 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2138 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2139 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2140 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2141 } 2142 2143 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2144 { 2145 const struct gfx_firmware_header_v2_0 *cp_hdr; 2146 unsigned pipe_id, tmp; 2147 2148 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2149 adev->gfx.pfp_fw->data; 2150 mutex_lock(&adev->srbm_mutex); 2151 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2152 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2153 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2154 (cp_hdr->ucode_start_addr_hi << 30) | 2155 (cp_hdr->ucode_start_addr_lo >> 2)); 2156 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2157 cp_hdr->ucode_start_addr_hi>>2); 2158 2159 /* 2160 * Program CP_ME_CNTL to reset given PIPE to take 2161 * effect of CP_PFP_PRGRM_CNTR_START. 2162 */ 2163 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2164 if (pipe_id == 0) 2165 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2166 PFP_PIPE0_RESET, 1); 2167 else 2168 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2169 PFP_PIPE1_RESET, 1); 2170 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2171 2172 /* Clear pfp pipe0 reset bit. */ 2173 if (pipe_id == 0) 2174 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2175 PFP_PIPE0_RESET, 0); 2176 else 2177 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2178 PFP_PIPE1_RESET, 0); 2179 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2180 } 2181 soc24_grbm_select(adev, 0, 0, 0, 0); 2182 mutex_unlock(&adev->srbm_mutex); 2183 } 2184 2185 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2186 { 2187 const struct gfx_firmware_header_v2_0 *cp_hdr; 2188 unsigned pipe_id, tmp; 2189 2190 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2191 adev->gfx.me_fw->data; 2192 mutex_lock(&adev->srbm_mutex); 2193 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2194 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2195 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2196 (cp_hdr->ucode_start_addr_hi << 30) | 2197 (cp_hdr->ucode_start_addr_lo >> 2) ); 2198 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2199 cp_hdr->ucode_start_addr_hi>>2); 2200 2201 /* 2202 * Program CP_ME_CNTL to reset given PIPE to take 2203 * effect of CP_ME_PRGRM_CNTR_START. 2204 */ 2205 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2206 if (pipe_id == 0) 2207 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2208 ME_PIPE0_RESET, 1); 2209 else 2210 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2211 ME_PIPE1_RESET, 1); 2212 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2213 2214 /* Clear pfp pipe0 reset bit. */ 2215 if (pipe_id == 0) 2216 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2217 ME_PIPE0_RESET, 0); 2218 else 2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2220 ME_PIPE1_RESET, 0); 2221 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2222 } 2223 soc24_grbm_select(adev, 0, 0, 0, 0); 2224 mutex_unlock(&adev->srbm_mutex); 2225 } 2226 2227 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2228 { 2229 const struct gfx_firmware_header_v2_0 *cp_hdr; 2230 unsigned pipe_id; 2231 2232 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2233 adev->gfx.mec_fw->data; 2234 mutex_lock(&adev->srbm_mutex); 2235 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2236 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2237 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2238 cp_hdr->ucode_start_addr_lo >> 2 | 2239 cp_hdr->ucode_start_addr_hi << 30); 2240 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2241 cp_hdr->ucode_start_addr_hi >> 2); 2242 } 2243 soc24_grbm_select(adev, 0, 0, 0, 0); 2244 mutex_unlock(&adev->srbm_mutex); 2245 } 2246 2247 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2248 { 2249 uint32_t cp_status; 2250 uint32_t bootload_status; 2251 int i; 2252 2253 for (i = 0; i < adev->usec_timeout; i++) { 2254 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2255 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2256 2257 if ((cp_status == 0) && 2258 (REG_GET_FIELD(bootload_status, 2259 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2260 break; 2261 } 2262 udelay(1); 2263 if (amdgpu_emu_mode) 2264 msleep(10); 2265 } 2266 2267 if (i >= adev->usec_timeout) { 2268 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2269 return -ETIMEDOUT; 2270 } 2271 2272 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2273 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2274 gfx_v12_0_set_me_ucode_start_addr(adev); 2275 gfx_v12_0_set_mec_ucode_start_addr(adev); 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2282 { 2283 int i; 2284 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2285 2286 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2287 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2288 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2289 2290 for (i = 0; i < adev->usec_timeout; i++) { 2291 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2292 break; 2293 udelay(1); 2294 } 2295 2296 if (i >= adev->usec_timeout) 2297 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2298 2299 return 0; 2300 } 2301 2302 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2303 { 2304 int r; 2305 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2306 const __le32 *fw_ucode, *fw_data; 2307 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2308 uint32_t tmp; 2309 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2310 2311 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2312 adev->gfx.pfp_fw->data; 2313 2314 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2315 2316 /* instruction */ 2317 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2318 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2319 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2320 /* data */ 2321 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2322 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2323 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2324 2325 /* 64kb align */ 2326 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2327 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2328 &adev->gfx.pfp.pfp_fw_obj, 2329 &adev->gfx.pfp.pfp_fw_gpu_addr, 2330 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2331 if (r) { 2332 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2333 gfx_v12_0_pfp_fini(adev); 2334 return r; 2335 } 2336 2337 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2338 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2339 &adev->gfx.pfp.pfp_fw_data_obj, 2340 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2341 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2342 if (r) { 2343 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2344 gfx_v12_0_pfp_fini(adev); 2345 return r; 2346 } 2347 2348 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2349 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2350 2351 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2352 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2353 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2354 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2355 2356 if (amdgpu_emu_mode == 1) 2357 adev->hdp.funcs->flush_hdp(adev, NULL); 2358 2359 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2360 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2361 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2362 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2363 2364 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2365 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2366 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2367 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2368 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2369 2370 /* 2371 * Programming any of the CP_PFP_IC_BASE registers 2372 * forces invalidation of the ME L1 I$. Wait for the 2373 * invalidation complete 2374 */ 2375 for (i = 0; i < usec_timeout; i++) { 2376 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2377 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2378 INVALIDATE_CACHE_COMPLETE)) 2379 break; 2380 udelay(1); 2381 } 2382 2383 if (i >= usec_timeout) { 2384 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2385 return -EINVAL; 2386 } 2387 2388 /* Prime the L1 instruction caches */ 2389 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2390 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2391 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2392 /* Waiting for cache primed*/ 2393 for (i = 0; i < usec_timeout; i++) { 2394 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2395 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2396 ICACHE_PRIMED)) 2397 break; 2398 udelay(1); 2399 } 2400 2401 if (i >= usec_timeout) { 2402 dev_err(adev->dev, "failed to prime instruction cache\n"); 2403 return -EINVAL; 2404 } 2405 2406 mutex_lock(&adev->srbm_mutex); 2407 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2408 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2409 2410 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2411 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2412 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2413 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2414 } 2415 soc24_grbm_select(adev, 0, 0, 0, 0); 2416 mutex_unlock(&adev->srbm_mutex); 2417 2418 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2419 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2420 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2421 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2422 2423 /* Invalidate the data caches */ 2424 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2425 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2426 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2427 2428 for (i = 0; i < usec_timeout; i++) { 2429 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2430 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2431 INVALIDATE_DCACHE_COMPLETE)) 2432 break; 2433 udelay(1); 2434 } 2435 2436 if (i >= usec_timeout) { 2437 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2438 return -EINVAL; 2439 } 2440 2441 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2442 2443 return 0; 2444 } 2445 2446 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2447 { 2448 int r; 2449 const struct gfx_firmware_header_v2_0 *me_hdr; 2450 const __le32 *fw_ucode, *fw_data; 2451 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2452 uint32_t tmp; 2453 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2454 2455 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2456 adev->gfx.me_fw->data; 2457 2458 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2459 2460 /* instruction */ 2461 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2462 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2463 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2464 /* data */ 2465 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2466 le32_to_cpu(me_hdr->data_offset_bytes)); 2467 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2468 2469 /* 64kb align*/ 2470 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2471 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2472 &adev->gfx.me.me_fw_obj, 2473 &adev->gfx.me.me_fw_gpu_addr, 2474 (void **)&adev->gfx.me.me_fw_ptr); 2475 if (r) { 2476 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2477 gfx_v12_0_me_fini(adev); 2478 return r; 2479 } 2480 2481 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2482 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2483 &adev->gfx.me.me_fw_data_obj, 2484 &adev->gfx.me.me_fw_data_gpu_addr, 2485 (void **)&adev->gfx.me.me_fw_data_ptr); 2486 if (r) { 2487 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2488 gfx_v12_0_me_fini(adev); 2489 return r; 2490 } 2491 2492 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2493 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2494 2495 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2496 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2497 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2498 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2499 2500 if (amdgpu_emu_mode == 1) 2501 adev->hdp.funcs->flush_hdp(adev, NULL); 2502 2503 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2504 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2505 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2506 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2507 2508 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2509 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2510 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2511 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2512 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2513 2514 /* 2515 * Programming any of the CP_ME_IC_BASE registers 2516 * forces invalidation of the ME L1 I$. Wait for the 2517 * invalidation complete 2518 */ 2519 for (i = 0; i < usec_timeout; i++) { 2520 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2521 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2522 INVALIDATE_CACHE_COMPLETE)) 2523 break; 2524 udelay(1); 2525 } 2526 2527 if (i >= usec_timeout) { 2528 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2529 return -EINVAL; 2530 } 2531 2532 /* Prime the instruction caches */ 2533 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2534 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2535 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2536 2537 /* Waiting for instruction cache primed*/ 2538 for (i = 0; i < usec_timeout; i++) { 2539 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2540 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2541 ICACHE_PRIMED)) 2542 break; 2543 udelay(1); 2544 } 2545 2546 if (i >= usec_timeout) { 2547 dev_err(adev->dev, "failed to prime instruction cache\n"); 2548 return -EINVAL; 2549 } 2550 2551 mutex_lock(&adev->srbm_mutex); 2552 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2553 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2554 2555 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2556 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2557 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2558 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2559 } 2560 soc24_grbm_select(adev, 0, 0, 0, 0); 2561 mutex_unlock(&adev->srbm_mutex); 2562 2563 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2564 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2565 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2566 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2567 2568 /* Invalidate the data caches */ 2569 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2570 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2571 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2572 2573 for (i = 0; i < usec_timeout; i++) { 2574 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2575 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2576 INVALIDATE_DCACHE_COMPLETE)) 2577 break; 2578 udelay(1); 2579 } 2580 2581 if (i >= usec_timeout) { 2582 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2583 return -EINVAL; 2584 } 2585 2586 gfx_v12_0_set_me_ucode_start_addr(adev); 2587 2588 return 0; 2589 } 2590 2591 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2592 { 2593 int r; 2594 2595 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2596 return -EINVAL; 2597 2598 gfx_v12_0_cp_gfx_enable(adev, false); 2599 2600 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2601 if (r) { 2602 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2603 return r; 2604 } 2605 2606 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2607 if (r) { 2608 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2609 return r; 2610 } 2611 2612 return 0; 2613 } 2614 2615 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2616 { 2617 /* init the CP */ 2618 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2619 adev->gfx.config.max_hw_contexts - 1); 2620 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2621 2622 if (!amdgpu_async_gfx_ring) 2623 gfx_v12_0_cp_gfx_enable(adev, true); 2624 2625 return 0; 2626 } 2627 2628 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2629 CP_PIPE_ID pipe) 2630 { 2631 u32 tmp; 2632 2633 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2634 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2635 2636 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2637 } 2638 2639 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2640 struct amdgpu_ring *ring) 2641 { 2642 u32 tmp; 2643 2644 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2645 if (ring->use_doorbell) { 2646 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2647 DOORBELL_OFFSET, ring->doorbell_index); 2648 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2649 DOORBELL_EN, 1); 2650 } else { 2651 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2652 DOORBELL_EN, 0); 2653 } 2654 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2655 2656 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2657 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2658 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2659 2660 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2661 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2662 } 2663 2664 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2665 { 2666 struct amdgpu_ring *ring; 2667 u32 tmp; 2668 u32 rb_bufsz; 2669 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2670 2671 /* Set the write pointer delay */ 2672 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2673 2674 /* set the RB to use vmid 0 */ 2675 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2676 2677 /* Init gfx ring 0 for pipe 0 */ 2678 mutex_lock(&adev->srbm_mutex); 2679 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2680 2681 /* Set ring buffer size */ 2682 ring = &adev->gfx.gfx_ring[0]; 2683 rb_bufsz = order_base_2(ring->ring_size / 8); 2684 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2685 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2686 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2687 2688 /* Initialize the ring buffer's write pointers */ 2689 ring->wptr = 0; 2690 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2691 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2692 2693 /* set the wb address whether it's enabled or not */ 2694 rptr_addr = ring->rptr_gpu_addr; 2695 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2696 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2697 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2698 2699 wptr_gpu_addr = ring->wptr_gpu_addr; 2700 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2701 lower_32_bits(wptr_gpu_addr)); 2702 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2703 upper_32_bits(wptr_gpu_addr)); 2704 2705 mdelay(1); 2706 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2707 2708 rb_addr = ring->gpu_addr >> 8; 2709 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2710 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2711 2712 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2713 2714 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2715 mutex_unlock(&adev->srbm_mutex); 2716 2717 /* Switch to pipe 0 */ 2718 mutex_lock(&adev->srbm_mutex); 2719 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2720 mutex_unlock(&adev->srbm_mutex); 2721 2722 /* start the ring */ 2723 gfx_v12_0_cp_gfx_start(adev); 2724 return 0; 2725 } 2726 2727 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2728 { 2729 u32 data; 2730 2731 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2732 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2733 enable ? 0 : 1); 2734 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2735 enable ? 0 : 1); 2736 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2737 enable ? 0 : 1); 2738 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2739 enable ? 0 : 1); 2740 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2741 enable ? 0 : 1); 2742 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2743 enable ? 1 : 0); 2744 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2745 enable ? 1 : 0); 2746 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2747 enable ? 1 : 0); 2748 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2749 enable ? 1 : 0); 2750 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2751 enable ? 0 : 1); 2752 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2753 2754 adev->gfx.kiq[0].ring.sched.ready = enable; 2755 2756 udelay(50); 2757 } 2758 2759 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2760 { 2761 const struct gfx_firmware_header_v2_0 *mec_hdr; 2762 const __le32 *fw_ucode, *fw_data; 2763 u32 tmp, fw_ucode_size, fw_data_size; 2764 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2765 u32 *fw_ucode_ptr, *fw_data_ptr; 2766 int r; 2767 2768 if (!adev->gfx.mec_fw) 2769 return -EINVAL; 2770 2771 gfx_v12_0_cp_compute_enable(adev, false); 2772 2773 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2774 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2775 2776 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2777 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2778 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2779 2780 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2781 le32_to_cpu(mec_hdr->data_offset_bytes)); 2782 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2783 2784 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2785 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2786 &adev->gfx.mec.mec_fw_obj, 2787 &adev->gfx.mec.mec_fw_gpu_addr, 2788 (void **)&fw_ucode_ptr); 2789 if (r) { 2790 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2791 gfx_v12_0_mec_fini(adev); 2792 return r; 2793 } 2794 2795 r = amdgpu_bo_create_reserved(adev, 2796 ALIGN(fw_data_size, 64 * 1024) * 2797 adev->gfx.mec.num_pipe_per_mec, 2798 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2799 &adev->gfx.mec.mec_fw_data_obj, 2800 &adev->gfx.mec.mec_fw_data_gpu_addr, 2801 (void **)&fw_data_ptr); 2802 if (r) { 2803 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2804 gfx_v12_0_mec_fini(adev); 2805 return r; 2806 } 2807 2808 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2809 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2810 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2811 } 2812 2813 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2814 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2815 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2816 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2817 2818 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2819 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2820 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2821 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2822 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2823 2824 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2825 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2826 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2827 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2828 2829 mutex_lock(&adev->srbm_mutex); 2830 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2831 soc24_grbm_select(adev, 1, i, 0, 0); 2832 2833 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2834 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2835 i * ALIGN(fw_data_size, 64 * 1024))); 2836 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2837 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2838 i * ALIGN(fw_data_size, 64 * 1024))); 2839 2840 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2841 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2842 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2843 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2844 } 2845 mutex_unlock(&adev->srbm_mutex); 2846 soc24_grbm_select(adev, 0, 0, 0, 0); 2847 2848 /* Trigger an invalidation of the L1 instruction caches */ 2849 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2850 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2851 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2852 2853 /* Wait for invalidation complete */ 2854 for (i = 0; i < usec_timeout; i++) { 2855 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2856 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2857 INVALIDATE_DCACHE_COMPLETE)) 2858 break; 2859 udelay(1); 2860 } 2861 2862 if (i >= usec_timeout) { 2863 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2864 return -EINVAL; 2865 } 2866 2867 /* Trigger an invalidation of the L1 instruction caches */ 2868 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2869 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2870 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2871 2872 /* Wait for invalidation complete */ 2873 for (i = 0; i < usec_timeout; i++) { 2874 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2875 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2876 INVALIDATE_CACHE_COMPLETE)) 2877 break; 2878 udelay(1); 2879 } 2880 2881 if (i >= usec_timeout) { 2882 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2883 return -EINVAL; 2884 } 2885 2886 gfx_v12_0_set_mec_ucode_start_addr(adev); 2887 2888 return 0; 2889 } 2890 2891 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2892 { 2893 uint32_t tmp; 2894 struct amdgpu_device *adev = ring->adev; 2895 2896 /* tell RLC which is KIQ queue */ 2897 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2898 tmp &= 0xffffff00; 2899 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2900 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2901 } 2902 2903 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2904 { 2905 /* set graphics engine doorbell range */ 2906 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2907 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2908 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2909 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2910 2911 /* set compute engine doorbell range */ 2912 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2913 (adev->doorbell_index.kiq * 2) << 2); 2914 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2915 (adev->doorbell_index.userqueue_end * 2) << 2); 2916 } 2917 2918 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2919 struct amdgpu_mqd_prop *prop) 2920 { 2921 struct v12_gfx_mqd *mqd = m; 2922 uint64_t hqd_gpu_addr, wb_gpu_addr; 2923 uint32_t tmp; 2924 uint32_t rb_bufsz; 2925 2926 /* set up gfx hqd wptr */ 2927 mqd->cp_gfx_hqd_wptr = 0; 2928 mqd->cp_gfx_hqd_wptr_hi = 0; 2929 2930 /* set the pointer to the MQD */ 2931 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2932 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2933 2934 /* set up mqd control */ 2935 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2936 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2937 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2938 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2939 mqd->cp_gfx_mqd_control = tmp; 2940 2941 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2942 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2943 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2944 mqd->cp_gfx_hqd_vmid = 0; 2945 2946 /* set up default queue priority level 2947 * 0x0 = low priority, 0x1 = high priority */ 2948 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2949 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2950 mqd->cp_gfx_hqd_queue_priority = tmp; 2951 2952 /* set up time quantum */ 2953 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2954 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2955 mqd->cp_gfx_hqd_quantum = tmp; 2956 2957 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2958 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2959 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2960 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2961 2962 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2963 wb_gpu_addr = prop->rptr_gpu_addr; 2964 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2965 mqd->cp_gfx_hqd_rptr_addr_hi = 2966 upper_32_bits(wb_gpu_addr) & 0xffff; 2967 2968 /* set up rb_wptr_poll addr */ 2969 wb_gpu_addr = prop->wptr_gpu_addr; 2970 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2971 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2972 2973 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2974 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2975 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 2976 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2977 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2978 #ifdef __BIG_ENDIAN 2979 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2980 #endif 2981 mqd->cp_gfx_hqd_cntl = tmp; 2982 2983 /* set up cp_doorbell_control */ 2984 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 2985 if (prop->use_doorbell) { 2986 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2987 DOORBELL_OFFSET, prop->doorbell_index); 2988 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2989 DOORBELL_EN, 1); 2990 } else 2991 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2992 DOORBELL_EN, 0); 2993 mqd->cp_rb_doorbell_control = tmp; 2994 2995 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2996 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 2997 2998 /* active the queue */ 2999 mqd->cp_gfx_hqd_active = 1; 3000 3001 return 0; 3002 } 3003 3004 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3005 { 3006 struct amdgpu_device *adev = ring->adev; 3007 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3008 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3009 3010 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3011 memset((void *)mqd, 0, sizeof(*mqd)); 3012 mutex_lock(&adev->srbm_mutex); 3013 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3014 amdgpu_ring_init_mqd(ring); 3015 soc24_grbm_select(adev, 0, 0, 0, 0); 3016 mutex_unlock(&adev->srbm_mutex); 3017 if (adev->gfx.me.mqd_backup[mqd_idx]) 3018 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3019 } else { 3020 /* restore mqd with the backup copy */ 3021 if (adev->gfx.me.mqd_backup[mqd_idx]) 3022 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3023 /* reset the ring */ 3024 ring->wptr = 0; 3025 *ring->wptr_cpu_addr = 0; 3026 amdgpu_ring_clear_ring(ring); 3027 } 3028 3029 return 0; 3030 } 3031 3032 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3033 { 3034 int i, r; 3035 3036 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3037 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3038 if (r) 3039 return r; 3040 } 3041 3042 r = amdgpu_gfx_enable_kgq(adev, 0); 3043 if (r) 3044 return r; 3045 3046 return gfx_v12_0_cp_gfx_start(adev); 3047 } 3048 3049 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3050 struct amdgpu_mqd_prop *prop) 3051 { 3052 struct v12_compute_mqd *mqd = m; 3053 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3054 uint32_t tmp; 3055 3056 mqd->header = 0xC0310800; 3057 mqd->compute_pipelinestat_enable = 0x00000001; 3058 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3059 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3060 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3061 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3062 mqd->compute_misc_reserved = 0x00000007; 3063 3064 eop_base_addr = prop->eop_gpu_addr >> 8; 3065 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3066 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3067 3068 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3069 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3070 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3071 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3072 3073 mqd->cp_hqd_eop_control = tmp; 3074 3075 /* enable doorbell? */ 3076 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3077 3078 if (prop->use_doorbell) { 3079 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3080 DOORBELL_OFFSET, prop->doorbell_index); 3081 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3082 DOORBELL_EN, 1); 3083 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3084 DOORBELL_SOURCE, 0); 3085 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3086 DOORBELL_HIT, 0); 3087 } else { 3088 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3089 DOORBELL_EN, 0); 3090 } 3091 3092 mqd->cp_hqd_pq_doorbell_control = tmp; 3093 3094 /* disable the queue if it's active */ 3095 mqd->cp_hqd_dequeue_request = 0; 3096 mqd->cp_hqd_pq_rptr = 0; 3097 mqd->cp_hqd_pq_wptr_lo = 0; 3098 mqd->cp_hqd_pq_wptr_hi = 0; 3099 3100 /* set the pointer to the MQD */ 3101 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3102 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3103 3104 /* set MQD vmid to 0 */ 3105 tmp = regCP_MQD_CONTROL_DEFAULT; 3106 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3107 mqd->cp_mqd_control = tmp; 3108 3109 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3110 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3111 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3112 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3113 3114 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3115 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3116 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3117 (order_base_2(prop->queue_size / 4) - 1)); 3118 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3119 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3120 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3121 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3122 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3123 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3124 mqd->cp_hqd_pq_control = tmp; 3125 3126 /* set the wb address whether it's enabled or not */ 3127 wb_gpu_addr = prop->rptr_gpu_addr; 3128 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3129 mqd->cp_hqd_pq_rptr_report_addr_hi = 3130 upper_32_bits(wb_gpu_addr) & 0xffff; 3131 3132 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3133 wb_gpu_addr = prop->wptr_gpu_addr; 3134 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3135 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3136 3137 tmp = 0; 3138 /* enable the doorbell if requested */ 3139 if (prop->use_doorbell) { 3140 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3142 DOORBELL_OFFSET, prop->doorbell_index); 3143 3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3145 DOORBELL_EN, 1); 3146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3147 DOORBELL_SOURCE, 0); 3148 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3149 DOORBELL_HIT, 0); 3150 } 3151 3152 mqd->cp_hqd_pq_doorbell_control = tmp; 3153 3154 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3155 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3156 3157 /* set the vmid for the queue */ 3158 mqd->cp_hqd_vmid = 0; 3159 3160 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3161 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3162 mqd->cp_hqd_persistent_state = tmp; 3163 3164 /* set MIN_IB_AVAIL_SIZE */ 3165 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3166 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3167 mqd->cp_hqd_ib_control = tmp; 3168 3169 /* set static priority for a compute queue/ring */ 3170 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3171 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3172 3173 mqd->cp_hqd_active = prop->hqd_active; 3174 3175 return 0; 3176 } 3177 3178 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3179 { 3180 struct amdgpu_device *adev = ring->adev; 3181 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3182 int j; 3183 3184 /* inactivate the queue */ 3185 if (amdgpu_sriov_vf(adev)) 3186 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3187 3188 /* disable wptr polling */ 3189 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3190 3191 /* write the EOP addr */ 3192 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3193 mqd->cp_hqd_eop_base_addr_lo); 3194 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3195 mqd->cp_hqd_eop_base_addr_hi); 3196 3197 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3198 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3199 mqd->cp_hqd_eop_control); 3200 3201 /* enable doorbell? */ 3202 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3203 mqd->cp_hqd_pq_doorbell_control); 3204 3205 /* disable the queue if it's active */ 3206 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3207 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3208 for (j = 0; j < adev->usec_timeout; j++) { 3209 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3210 break; 3211 udelay(1); 3212 } 3213 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3214 mqd->cp_hqd_dequeue_request); 3215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3216 mqd->cp_hqd_pq_rptr); 3217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3218 mqd->cp_hqd_pq_wptr_lo); 3219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3220 mqd->cp_hqd_pq_wptr_hi); 3221 } 3222 3223 /* set the pointer to the MQD */ 3224 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3225 mqd->cp_mqd_base_addr_lo); 3226 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3227 mqd->cp_mqd_base_addr_hi); 3228 3229 /* set MQD vmid to 0 */ 3230 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3231 mqd->cp_mqd_control); 3232 3233 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3234 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3235 mqd->cp_hqd_pq_base_lo); 3236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3237 mqd->cp_hqd_pq_base_hi); 3238 3239 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3240 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3241 mqd->cp_hqd_pq_control); 3242 3243 /* set the wb address whether it's enabled or not */ 3244 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3245 mqd->cp_hqd_pq_rptr_report_addr_lo); 3246 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3247 mqd->cp_hqd_pq_rptr_report_addr_hi); 3248 3249 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3250 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3251 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3252 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3253 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3254 3255 /* enable the doorbell if requested */ 3256 if (ring->use_doorbell) { 3257 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3258 (adev->doorbell_index.kiq * 2) << 2); 3259 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3260 (adev->doorbell_index.userqueue_end * 2) << 2); 3261 } 3262 3263 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3264 mqd->cp_hqd_pq_doorbell_control); 3265 3266 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3268 mqd->cp_hqd_pq_wptr_lo); 3269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3270 mqd->cp_hqd_pq_wptr_hi); 3271 3272 /* set the vmid for the queue */ 3273 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3274 3275 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3276 mqd->cp_hqd_persistent_state); 3277 3278 /* activate the queue */ 3279 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3280 mqd->cp_hqd_active); 3281 3282 if (ring->use_doorbell) 3283 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3284 3285 return 0; 3286 } 3287 3288 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3289 { 3290 struct amdgpu_device *adev = ring->adev; 3291 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3292 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3293 3294 gfx_v12_0_kiq_setting(ring); 3295 3296 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3297 /* reset MQD to a clean status */ 3298 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3299 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3300 3301 /* reset ring buffer */ 3302 ring->wptr = 0; 3303 amdgpu_ring_clear_ring(ring); 3304 3305 mutex_lock(&adev->srbm_mutex); 3306 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3307 gfx_v12_0_kiq_init_register(ring); 3308 soc24_grbm_select(adev, 0, 0, 0, 0); 3309 mutex_unlock(&adev->srbm_mutex); 3310 } else { 3311 memset((void *)mqd, 0, sizeof(*mqd)); 3312 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3313 amdgpu_ring_clear_ring(ring); 3314 mutex_lock(&adev->srbm_mutex); 3315 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3316 amdgpu_ring_init_mqd(ring); 3317 gfx_v12_0_kiq_init_register(ring); 3318 soc24_grbm_select(adev, 0, 0, 0, 0); 3319 mutex_unlock(&adev->srbm_mutex); 3320 3321 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3322 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3323 } 3324 3325 return 0; 3326 } 3327 3328 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3329 { 3330 struct amdgpu_device *adev = ring->adev; 3331 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3332 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3333 3334 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3335 memset((void *)mqd, 0, sizeof(*mqd)); 3336 mutex_lock(&adev->srbm_mutex); 3337 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3338 amdgpu_ring_init_mqd(ring); 3339 soc24_grbm_select(adev, 0, 0, 0, 0); 3340 mutex_unlock(&adev->srbm_mutex); 3341 3342 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3343 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3344 } else { 3345 /* restore MQD to a clean status */ 3346 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3347 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3348 /* reset ring buffer */ 3349 ring->wptr = 0; 3350 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3351 amdgpu_ring_clear_ring(ring); 3352 } 3353 3354 return 0; 3355 } 3356 3357 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3358 { 3359 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3360 adev->gfx.kiq[0].ring.sched.ready = true; 3361 return 0; 3362 } 3363 3364 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3365 { 3366 int i, r; 3367 3368 if (!amdgpu_async_gfx_ring) 3369 gfx_v12_0_cp_compute_enable(adev, true); 3370 3371 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3372 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3373 if (r) 3374 return r; 3375 } 3376 3377 return amdgpu_gfx_enable_kcq(adev, 0); 3378 } 3379 3380 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3381 { 3382 int r, i; 3383 struct amdgpu_ring *ring; 3384 3385 if (!(adev->flags & AMD_IS_APU)) 3386 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3387 3388 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3389 /* legacy firmware loading */ 3390 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3391 if (r) 3392 return r; 3393 3394 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3395 if (r) 3396 return r; 3397 } 3398 3399 gfx_v12_0_cp_set_doorbell_range(adev); 3400 3401 if (amdgpu_async_gfx_ring) { 3402 gfx_v12_0_cp_compute_enable(adev, true); 3403 gfx_v12_0_cp_gfx_enable(adev, true); 3404 } 3405 3406 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3407 r = amdgpu_mes_kiq_hw_init(adev); 3408 else 3409 r = gfx_v12_0_kiq_resume(adev); 3410 if (r) 3411 return r; 3412 3413 r = gfx_v12_0_kcq_resume(adev); 3414 if (r) 3415 return r; 3416 3417 if (!amdgpu_async_gfx_ring) { 3418 r = gfx_v12_0_cp_gfx_resume(adev); 3419 if (r) 3420 return r; 3421 } else { 3422 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3423 if (r) 3424 return r; 3425 } 3426 3427 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3428 ring = &adev->gfx.gfx_ring[i]; 3429 r = amdgpu_ring_test_helper(ring); 3430 if (r) 3431 return r; 3432 } 3433 3434 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3435 ring = &adev->gfx.compute_ring[i]; 3436 r = amdgpu_ring_test_helper(ring); 3437 if (r) 3438 return r; 3439 } 3440 3441 return 0; 3442 } 3443 3444 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3445 { 3446 gfx_v12_0_cp_gfx_enable(adev, enable); 3447 gfx_v12_0_cp_compute_enable(adev, enable); 3448 } 3449 3450 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3451 { 3452 int r; 3453 bool value; 3454 3455 r = adev->gfxhub.funcs->gart_enable(adev); 3456 if (r) 3457 return r; 3458 3459 adev->hdp.funcs->flush_hdp(adev, NULL); 3460 3461 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3462 false : true; 3463 3464 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3465 /* TODO investigate why this and the hdp flush above is needed, 3466 * are we missing a flush somewhere else? */ 3467 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3468 3469 return 0; 3470 } 3471 3472 static int get_gb_addr_config(struct amdgpu_device *adev) 3473 { 3474 u32 gb_addr_config; 3475 3476 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3477 if (gb_addr_config == 0) 3478 return -EINVAL; 3479 3480 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3481 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3482 3483 adev->gfx.config.gb_addr_config = gb_addr_config; 3484 3485 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3486 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3487 GB_ADDR_CONFIG, NUM_PIPES); 3488 3489 adev->gfx.config.max_tile_pipes = 3490 adev->gfx.config.gb_addr_config_fields.num_pipes; 3491 3492 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3493 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3494 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3495 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3496 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3497 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3498 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3499 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3500 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3501 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3502 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3503 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3504 3505 return 0; 3506 } 3507 3508 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3509 { 3510 uint32_t data; 3511 3512 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3513 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3514 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3515 3516 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3517 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3518 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3519 } 3520 3521 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3522 { 3523 if (amdgpu_sriov_vf(adev)) 3524 return; 3525 3526 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3527 case IP_VERSION(12, 0, 0): 3528 case IP_VERSION(12, 0, 1): 3529 soc15_program_register_sequence(adev, 3530 golden_settings_gc_12_0, 3531 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3532 3533 if (adev->rev_id == 0) 3534 soc15_program_register_sequence(adev, 3535 golden_settings_gc_12_0_rev0, 3536 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3537 break; 3538 default: 3539 break; 3540 } 3541 } 3542 3543 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3544 { 3545 int r; 3546 struct amdgpu_device *adev = ip_block->adev; 3547 3548 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3549 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3550 /* RLC autoload sequence 1: Program rlc ram */ 3551 if (adev->gfx.imu.funcs->program_rlc_ram) 3552 adev->gfx.imu.funcs->program_rlc_ram(adev); 3553 } 3554 /* rlc autoload firmware */ 3555 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3556 if (r) 3557 return r; 3558 } else { 3559 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3560 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3561 if (adev->gfx.imu.funcs->load_microcode) 3562 adev->gfx.imu.funcs->load_microcode(adev); 3563 if (adev->gfx.imu.funcs->setup_imu) 3564 adev->gfx.imu.funcs->setup_imu(adev); 3565 if (adev->gfx.imu.funcs->start_imu) 3566 adev->gfx.imu.funcs->start_imu(adev); 3567 } 3568 3569 /* disable gpa mode in backdoor loading */ 3570 gfx_v12_0_disable_gpa_mode(adev); 3571 } 3572 } 3573 3574 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3575 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3576 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3577 if (r) { 3578 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3579 return r; 3580 } 3581 } 3582 3583 if (!amdgpu_emu_mode) 3584 gfx_v12_0_init_golden_registers(adev); 3585 3586 adev->gfx.is_poweron = true; 3587 3588 if (get_gb_addr_config(adev)) 3589 DRM_WARN("Invalid gb_addr_config !\n"); 3590 3591 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3592 gfx_v12_0_config_gfx_rs64(adev); 3593 3594 r = gfx_v12_0_gfxhub_enable(adev); 3595 if (r) 3596 return r; 3597 3598 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3599 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3600 (amdgpu_dpm == 1)) { 3601 /** 3602 * For gfx 12, rlc firmware loading relies on smu firmware is 3603 * loaded firstly, so in direct type, it has to load smc ucode 3604 * here before rlc. 3605 */ 3606 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3607 if (r) 3608 return r; 3609 } 3610 3611 gfx_v12_0_constants_init(adev); 3612 3613 if (adev->nbio.funcs->gc_doorbell_init) 3614 adev->nbio.funcs->gc_doorbell_init(adev); 3615 3616 r = gfx_v12_0_rlc_resume(adev); 3617 if (r) 3618 return r; 3619 3620 /* 3621 * init golden registers and rlc resume may override some registers, 3622 * reconfig them here 3623 */ 3624 gfx_v12_0_tcp_harvest(adev); 3625 3626 r = gfx_v12_0_cp_resume(adev); 3627 if (r) 3628 return r; 3629 3630 return r; 3631 } 3632 3633 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3634 { 3635 struct amdgpu_device *adev = ip_block->adev; 3636 uint32_t tmp; 3637 3638 cancel_delayed_work_sync(&adev->gfx.idle_work); 3639 3640 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3641 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3642 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3643 3644 if (!adev->no_hw_access) { 3645 if (amdgpu_async_gfx_ring) { 3646 if (amdgpu_gfx_disable_kgq(adev, 0)) 3647 DRM_ERROR("KGQ disable failed\n"); 3648 } 3649 3650 if (amdgpu_gfx_disable_kcq(adev, 0)) 3651 DRM_ERROR("KCQ disable failed\n"); 3652 3653 amdgpu_mes_kiq_hw_fini(adev); 3654 } 3655 3656 if (amdgpu_sriov_vf(adev)) { 3657 gfx_v12_0_cp_gfx_enable(adev, false); 3658 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3659 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3660 tmp &= 0xffffff00; 3661 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3662 3663 return 0; 3664 } 3665 gfx_v12_0_cp_enable(adev, false); 3666 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3667 3668 adev->gfxhub.funcs->gart_disable(adev); 3669 3670 adev->gfx.is_poweron = false; 3671 3672 return 0; 3673 } 3674 3675 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3676 { 3677 return gfx_v12_0_hw_fini(ip_block); 3678 } 3679 3680 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3681 { 3682 return gfx_v12_0_hw_init(ip_block); 3683 } 3684 3685 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3686 { 3687 struct amdgpu_device *adev = ip_block->adev; 3688 3689 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3690 GRBM_STATUS, GUI_ACTIVE)) 3691 return false; 3692 else 3693 return true; 3694 } 3695 3696 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3697 { 3698 unsigned i; 3699 u32 tmp; 3700 struct amdgpu_device *adev = ip_block->adev; 3701 3702 for (i = 0; i < adev->usec_timeout; i++) { 3703 /* read MC_STATUS */ 3704 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3705 GRBM_STATUS__GUI_ACTIVE_MASK; 3706 3707 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3708 return 0; 3709 udelay(1); 3710 } 3711 return -ETIMEDOUT; 3712 } 3713 3714 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3715 { 3716 uint64_t clock = 0; 3717 3718 if (adev->smuio.funcs && 3719 adev->smuio.funcs->get_gpu_clock_counter) 3720 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3721 else 3722 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3723 3724 return clock; 3725 } 3726 3727 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3728 { 3729 struct amdgpu_device *adev = ip_block->adev; 3730 3731 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3732 3733 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3734 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3735 AMDGPU_MAX_COMPUTE_RINGS); 3736 3737 gfx_v12_0_set_kiq_pm4_funcs(adev); 3738 gfx_v12_0_set_ring_funcs(adev); 3739 gfx_v12_0_set_irq_funcs(adev); 3740 gfx_v12_0_set_rlc_funcs(adev); 3741 gfx_v12_0_set_mqd_funcs(adev); 3742 gfx_v12_0_set_imu_funcs(adev); 3743 3744 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3745 3746 return gfx_v12_0_init_microcode(adev); 3747 } 3748 3749 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3750 { 3751 struct amdgpu_device *adev = ip_block->adev; 3752 int r; 3753 3754 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3755 if (r) 3756 return r; 3757 3758 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3759 if (r) 3760 return r; 3761 3762 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3763 if (r) 3764 return r; 3765 3766 return 0; 3767 } 3768 3769 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3770 { 3771 uint32_t rlc_cntl; 3772 3773 /* if RLC is not enabled, do nothing */ 3774 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3775 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3776 } 3777 3778 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3779 int xcc_id) 3780 { 3781 uint32_t data; 3782 unsigned i; 3783 3784 data = RLC_SAFE_MODE__CMD_MASK; 3785 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3786 3787 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3788 3789 /* wait for RLC_SAFE_MODE */ 3790 for (i = 0; i < adev->usec_timeout; i++) { 3791 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3792 RLC_SAFE_MODE, CMD)) 3793 break; 3794 udelay(1); 3795 } 3796 } 3797 3798 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3799 int xcc_id) 3800 { 3801 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3802 } 3803 3804 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3805 bool enable) 3806 { 3807 uint32_t def, data; 3808 3809 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3810 return; 3811 3812 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3813 3814 if (enable) 3815 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3816 else 3817 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3818 3819 if (def != data) 3820 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3821 } 3822 3823 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3824 struct amdgpu_ring *ring, 3825 unsigned vmid) 3826 { 3827 u32 reg, data; 3828 3829 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3830 if (amdgpu_sriov_is_pp_one_vf(adev)) 3831 data = RREG32_NO_KIQ(reg); 3832 else 3833 data = RREG32(reg); 3834 3835 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3836 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3837 3838 if (amdgpu_sriov_is_pp_one_vf(adev)) 3839 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3840 else 3841 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3842 3843 if (ring 3844 && amdgpu_sriov_is_pp_one_vf(adev) 3845 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3846 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3847 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3848 amdgpu_ring_emit_wreg(ring, reg, data); 3849 } 3850 } 3851 3852 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3853 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3854 .set_safe_mode = gfx_v12_0_set_safe_mode, 3855 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3856 .init = gfx_v12_0_rlc_init, 3857 .get_csb_size = gfx_v12_0_get_csb_size, 3858 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3859 .resume = gfx_v12_0_rlc_resume, 3860 .stop = gfx_v12_0_rlc_stop, 3861 .reset = gfx_v12_0_rlc_reset, 3862 .start = gfx_v12_0_rlc_start, 3863 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3864 }; 3865 3866 #if 0 3867 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3868 { 3869 /* TODO */ 3870 } 3871 3872 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3873 { 3874 /* TODO */ 3875 } 3876 #endif 3877 3878 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3879 enum amd_powergating_state state) 3880 { 3881 struct amdgpu_device *adev = ip_block->adev; 3882 bool enable = (state == AMD_PG_STATE_GATE); 3883 3884 if (amdgpu_sriov_vf(adev)) 3885 return 0; 3886 3887 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3888 case IP_VERSION(12, 0, 0): 3889 case IP_VERSION(12, 0, 1): 3890 amdgpu_gfx_off_ctrl(adev, enable); 3891 break; 3892 default: 3893 break; 3894 } 3895 3896 return 0; 3897 } 3898 3899 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3900 bool enable) 3901 { 3902 uint32_t def, data; 3903 3904 if (!(adev->cg_flags & 3905 (AMD_CG_SUPPORT_GFX_CGCG | 3906 AMD_CG_SUPPORT_GFX_CGLS | 3907 AMD_CG_SUPPORT_GFX_3D_CGCG | 3908 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3909 return; 3910 3911 if (enable) { 3912 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3913 3914 /* unset CGCG override */ 3915 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3916 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3917 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3918 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3920 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3921 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3922 3923 /* update CGCG override bits */ 3924 if (def != data) 3925 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3926 3927 /* enable cgcg FSM(0x0000363F) */ 3928 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3929 3930 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3931 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3932 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3933 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3934 } 3935 3936 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3937 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3938 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3939 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3940 } 3941 3942 if (def != data) 3943 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3944 3945 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3946 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3947 3948 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3949 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3950 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3951 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3952 } 3953 3954 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3955 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3956 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3957 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3958 } 3959 3960 if (def != data) 3961 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3962 3963 /* set IDLE_POLL_COUNT(0x00900100) */ 3964 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3965 3966 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3967 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3968 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3969 3970 if (def != data) 3971 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3972 3973 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3974 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3975 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3976 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3977 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3978 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3979 3980 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3981 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3982 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3983 3984 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3985 if (adev->sdma.num_instances > 1) { 3986 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3987 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3988 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3989 } 3990 } else { 3991 /* Program RLC_CGCG_CGLS_CTRL */ 3992 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3993 3994 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3995 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3996 3997 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3998 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3999 4000 if (def != data) 4001 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4002 4003 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4004 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4005 4006 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4007 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4008 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4009 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4010 4011 if (def != data) 4012 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4013 } 4014 } 4015 4016 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4017 bool enable) 4018 { 4019 uint32_t data, def; 4020 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4021 return; 4022 4023 /* It is disabled by HW by default */ 4024 if (enable) { 4025 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4026 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4027 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4028 4029 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4030 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4031 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4032 4033 if (def != data) 4034 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4035 } 4036 } else { 4037 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4038 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4039 4040 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4041 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4042 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4043 4044 if (def != data) 4045 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4046 } 4047 } 4048 } 4049 4050 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4051 bool enable) 4052 { 4053 uint32_t def, data; 4054 4055 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4056 return; 4057 4058 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4059 4060 if (enable) 4061 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4062 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4063 else 4064 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4065 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4066 4067 if (def != data) 4068 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4069 } 4070 4071 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4072 bool enable) 4073 { 4074 uint32_t def, data; 4075 4076 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4077 return; 4078 4079 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4080 4081 if (enable) 4082 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4083 else 4084 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4085 4086 if (def != data) 4087 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4088 } 4089 4090 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4091 bool enable) 4092 { 4093 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4094 4095 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4096 4097 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4098 4099 gfx_v12_0_update_repeater_fgcg(adev, enable); 4100 4101 gfx_v12_0_update_sram_fgcg(adev, enable); 4102 4103 gfx_v12_0_update_perf_clk(adev, enable); 4104 4105 if (adev->cg_flags & 4106 (AMD_CG_SUPPORT_GFX_MGCG | 4107 AMD_CG_SUPPORT_GFX_CGLS | 4108 AMD_CG_SUPPORT_GFX_CGCG | 4109 AMD_CG_SUPPORT_GFX_3D_CGCG | 4110 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4111 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4112 4113 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4114 4115 return 0; 4116 } 4117 4118 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4119 enum amd_clockgating_state state) 4120 { 4121 struct amdgpu_device *adev = ip_block->adev; 4122 4123 if (amdgpu_sriov_vf(adev)) 4124 return 0; 4125 4126 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4127 case IP_VERSION(12, 0, 0): 4128 case IP_VERSION(12, 0, 1): 4129 gfx_v12_0_update_gfx_clock_gating(adev, 4130 state == AMD_CG_STATE_GATE); 4131 break; 4132 default: 4133 break; 4134 } 4135 4136 return 0; 4137 } 4138 4139 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4140 { 4141 struct amdgpu_device *adev = ip_block->adev; 4142 int data; 4143 4144 /* AMD_CG_SUPPORT_GFX_MGCG */ 4145 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4146 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4147 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4148 4149 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4150 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4151 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4152 4153 /* AMD_CG_SUPPORT_GFX_FGCG */ 4154 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4155 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4156 4157 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4158 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4159 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4160 4161 /* AMD_CG_SUPPORT_GFX_CGCG */ 4162 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4163 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4164 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4165 4166 /* AMD_CG_SUPPORT_GFX_CGLS */ 4167 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4168 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4169 4170 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4171 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4172 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4173 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4174 4175 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4176 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4177 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4178 } 4179 4180 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4181 { 4182 /* gfx12 is 32bit rptr*/ 4183 return *(uint32_t *)ring->rptr_cpu_addr; 4184 } 4185 4186 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4187 { 4188 struct amdgpu_device *adev = ring->adev; 4189 u64 wptr; 4190 4191 /* XXX check if swapping is necessary on BE */ 4192 if (ring->use_doorbell) { 4193 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4194 } else { 4195 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4196 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4197 } 4198 4199 return wptr; 4200 } 4201 4202 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4203 { 4204 struct amdgpu_device *adev = ring->adev; 4205 uint32_t *wptr_saved; 4206 uint32_t *is_queue_unmap; 4207 uint64_t aggregated_db_index; 4208 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4209 uint64_t wptr_tmp; 4210 4211 if (ring->is_mes_queue) { 4212 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4213 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4214 sizeof(uint32_t)); 4215 aggregated_db_index = 4216 amdgpu_mes_get_aggregated_doorbell_index(adev, 4217 ring->hw_prio); 4218 4219 wptr_tmp = ring->wptr & ring->buf_mask; 4220 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4221 *wptr_saved = wptr_tmp; 4222 /* assume doorbell always being used by mes mapped queue */ 4223 if (*is_queue_unmap) { 4224 WDOORBELL64(aggregated_db_index, wptr_tmp); 4225 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4226 } else { 4227 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4228 4229 if (*is_queue_unmap) 4230 WDOORBELL64(aggregated_db_index, wptr_tmp); 4231 } 4232 } else { 4233 if (ring->use_doorbell) { 4234 /* XXX check if swapping is necessary on BE */ 4235 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4236 ring->wptr); 4237 WDOORBELL64(ring->doorbell_index, ring->wptr); 4238 } else { 4239 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4240 lower_32_bits(ring->wptr)); 4241 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4242 upper_32_bits(ring->wptr)); 4243 } 4244 } 4245 } 4246 4247 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4248 { 4249 /* gfx12 hardware is 32bit rptr */ 4250 return *(uint32_t *)ring->rptr_cpu_addr; 4251 } 4252 4253 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4254 { 4255 u64 wptr; 4256 4257 /* XXX check if swapping is necessary on BE */ 4258 if (ring->use_doorbell) 4259 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4260 else 4261 BUG(); 4262 return wptr; 4263 } 4264 4265 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4266 { 4267 struct amdgpu_device *adev = ring->adev; 4268 uint32_t *wptr_saved; 4269 uint32_t *is_queue_unmap; 4270 uint64_t aggregated_db_index; 4271 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4272 uint64_t wptr_tmp; 4273 4274 if (ring->is_mes_queue) { 4275 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4276 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4277 sizeof(uint32_t)); 4278 aggregated_db_index = 4279 amdgpu_mes_get_aggregated_doorbell_index(adev, 4280 ring->hw_prio); 4281 4282 wptr_tmp = ring->wptr & ring->buf_mask; 4283 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4284 *wptr_saved = wptr_tmp; 4285 /* assume doorbell always used by mes mapped queue */ 4286 if (*is_queue_unmap) { 4287 WDOORBELL64(aggregated_db_index, wptr_tmp); 4288 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4289 } else { 4290 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4291 4292 if (*is_queue_unmap) 4293 WDOORBELL64(aggregated_db_index, wptr_tmp); 4294 } 4295 } else { 4296 /* XXX check if swapping is necessary on BE */ 4297 if (ring->use_doorbell) { 4298 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4299 ring->wptr); 4300 WDOORBELL64(ring->doorbell_index, ring->wptr); 4301 } else { 4302 BUG(); /* only DOORBELL method supported on gfx12 now */ 4303 } 4304 } 4305 } 4306 4307 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4308 { 4309 struct amdgpu_device *adev = ring->adev; 4310 u32 ref_and_mask, reg_mem_engine; 4311 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4312 4313 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4314 switch (ring->me) { 4315 case 1: 4316 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4317 break; 4318 case 2: 4319 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4320 break; 4321 default: 4322 return; 4323 } 4324 reg_mem_engine = 0; 4325 } else { 4326 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4327 reg_mem_engine = 1; /* pfp */ 4328 } 4329 4330 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4331 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4332 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4333 ref_and_mask, ref_and_mask, 0x20); 4334 } 4335 4336 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4337 struct amdgpu_job *job, 4338 struct amdgpu_ib *ib, 4339 uint32_t flags) 4340 { 4341 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4342 u32 header, control = 0; 4343 4344 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4345 4346 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4347 4348 control |= ib->length_dw | (vmid << 24); 4349 4350 if (ring->is_mes_queue) 4351 /* inherit vmid from mqd */ 4352 control |= 0x400000; 4353 4354 amdgpu_ring_write(ring, header); 4355 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4356 amdgpu_ring_write(ring, 4357 #ifdef __BIG_ENDIAN 4358 (2 << 0) | 4359 #endif 4360 lower_32_bits(ib->gpu_addr)); 4361 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4362 amdgpu_ring_write(ring, control); 4363 } 4364 4365 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4366 struct amdgpu_job *job, 4367 struct amdgpu_ib *ib, 4368 uint32_t flags) 4369 { 4370 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4371 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4372 4373 if (ring->is_mes_queue) 4374 /* inherit vmid from mqd */ 4375 control |= 0x40000000; 4376 4377 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4378 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4379 amdgpu_ring_write(ring, 4380 #ifdef __BIG_ENDIAN 4381 (2 << 0) | 4382 #endif 4383 lower_32_bits(ib->gpu_addr)); 4384 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4385 amdgpu_ring_write(ring, control); 4386 } 4387 4388 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4389 u64 seq, unsigned flags) 4390 { 4391 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4392 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4393 4394 /* RELEASE_MEM - flush caches, send int */ 4395 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4396 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4397 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4398 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4399 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4400 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4401 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4402 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4403 4404 /* 4405 * the address should be Qword aligned if 64bit write, Dword 4406 * aligned if only send 32bit data low (discard data high) 4407 */ 4408 if (write64bit) 4409 BUG_ON(addr & 0x7); 4410 else 4411 BUG_ON(addr & 0x3); 4412 amdgpu_ring_write(ring, lower_32_bits(addr)); 4413 amdgpu_ring_write(ring, upper_32_bits(addr)); 4414 amdgpu_ring_write(ring, lower_32_bits(seq)); 4415 amdgpu_ring_write(ring, upper_32_bits(seq)); 4416 amdgpu_ring_write(ring, ring->is_mes_queue ? 4417 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4418 } 4419 4420 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4421 { 4422 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4423 uint32_t seq = ring->fence_drv.sync_seq; 4424 uint64_t addr = ring->fence_drv.gpu_addr; 4425 4426 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4427 upper_32_bits(addr), seq, 0xffffffff, 4); 4428 } 4429 4430 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4431 uint16_t pasid, uint32_t flush_type, 4432 bool all_hub, uint8_t dst_sel) 4433 { 4434 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4435 amdgpu_ring_write(ring, 4436 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4437 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4438 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4439 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4440 } 4441 4442 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4443 unsigned vmid, uint64_t pd_addr) 4444 { 4445 if (ring->is_mes_queue) 4446 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4447 else 4448 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4449 4450 /* compute doesn't have PFP */ 4451 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4452 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4453 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4454 amdgpu_ring_write(ring, 0x0); 4455 } 4456 } 4457 4458 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4459 u64 seq, unsigned int flags) 4460 { 4461 struct amdgpu_device *adev = ring->adev; 4462 4463 /* we only allocate 32bit for each seq wb address */ 4464 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4465 4466 /* write fence seq to the "addr" */ 4467 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4468 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4469 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4470 amdgpu_ring_write(ring, lower_32_bits(addr)); 4471 amdgpu_ring_write(ring, upper_32_bits(addr)); 4472 amdgpu_ring_write(ring, lower_32_bits(seq)); 4473 4474 if (flags & AMDGPU_FENCE_FLAG_INT) { 4475 /* set register to trigger INT */ 4476 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4477 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4478 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4479 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4480 amdgpu_ring_write(ring, 0); 4481 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4482 } 4483 } 4484 4485 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4486 uint32_t flags) 4487 { 4488 uint32_t dw2 = 0; 4489 4490 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4491 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4492 /* set load_global_config & load_global_uconfig */ 4493 dw2 |= 0x8001; 4494 /* set load_cs_sh_regs */ 4495 dw2 |= 0x01000000; 4496 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4497 dw2 |= 0x10002; 4498 } 4499 4500 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4501 amdgpu_ring_write(ring, dw2); 4502 amdgpu_ring_write(ring, 0); 4503 } 4504 4505 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4506 uint64_t addr) 4507 { 4508 unsigned ret; 4509 4510 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4511 amdgpu_ring_write(ring, lower_32_bits(addr)); 4512 amdgpu_ring_write(ring, upper_32_bits(addr)); 4513 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4514 amdgpu_ring_write(ring, 0); 4515 ret = ring->wptr & ring->buf_mask; 4516 /* patch dummy value later */ 4517 amdgpu_ring_write(ring, 0); 4518 4519 return ret; 4520 } 4521 4522 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4523 { 4524 int i, r = 0; 4525 struct amdgpu_device *adev = ring->adev; 4526 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4527 struct amdgpu_ring *kiq_ring = &kiq->ring; 4528 unsigned long flags; 4529 4530 if (adev->enable_mes) 4531 return -EINVAL; 4532 4533 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4534 return -EINVAL; 4535 4536 spin_lock_irqsave(&kiq->ring_lock, flags); 4537 4538 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4539 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4540 return -ENOMEM; 4541 } 4542 4543 /* assert preemption condition */ 4544 amdgpu_ring_set_preempt_cond_exec(ring, false); 4545 4546 /* assert IB preemption, emit the trailing fence */ 4547 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4548 ring->trail_fence_gpu_addr, 4549 ++ring->trail_seq); 4550 amdgpu_ring_commit(kiq_ring); 4551 4552 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4553 4554 /* poll the trailing fence */ 4555 for (i = 0; i < adev->usec_timeout; i++) { 4556 if (ring->trail_seq == 4557 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4558 break; 4559 udelay(1); 4560 } 4561 4562 if (i >= adev->usec_timeout) { 4563 r = -EINVAL; 4564 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4565 } 4566 4567 /* deassert preemption condition */ 4568 amdgpu_ring_set_preempt_cond_exec(ring, true); 4569 return r; 4570 } 4571 4572 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4573 bool start, 4574 bool secure) 4575 { 4576 uint32_t v = secure ? FRAME_TMZ : 0; 4577 4578 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4579 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4580 } 4581 4582 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4583 uint32_t reg_val_offs) 4584 { 4585 struct amdgpu_device *adev = ring->adev; 4586 4587 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4588 amdgpu_ring_write(ring, 0 | /* src: register*/ 4589 (5 << 8) | /* dst: memory */ 4590 (1 << 20)); /* write confirm */ 4591 amdgpu_ring_write(ring, reg); 4592 amdgpu_ring_write(ring, 0); 4593 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4594 reg_val_offs * 4)); 4595 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4596 reg_val_offs * 4)); 4597 } 4598 4599 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4600 uint32_t reg, 4601 uint32_t val) 4602 { 4603 uint32_t cmd = 0; 4604 4605 switch (ring->funcs->type) { 4606 case AMDGPU_RING_TYPE_GFX: 4607 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4608 break; 4609 case AMDGPU_RING_TYPE_KIQ: 4610 cmd = (1 << 16); /* no inc addr */ 4611 break; 4612 default: 4613 cmd = WR_CONFIRM; 4614 break; 4615 } 4616 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4617 amdgpu_ring_write(ring, cmd); 4618 amdgpu_ring_write(ring, reg); 4619 amdgpu_ring_write(ring, 0); 4620 amdgpu_ring_write(ring, val); 4621 } 4622 4623 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4624 uint32_t val, uint32_t mask) 4625 { 4626 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4627 } 4628 4629 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4630 uint32_t reg0, uint32_t reg1, 4631 uint32_t ref, uint32_t mask) 4632 { 4633 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4634 4635 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4636 ref, mask, 0x20); 4637 } 4638 4639 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4640 unsigned vmid) 4641 { 4642 struct amdgpu_device *adev = ring->adev; 4643 uint32_t value = 0; 4644 4645 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4646 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4647 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4648 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4649 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4650 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4651 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4652 } 4653 4654 static void 4655 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4656 uint32_t me, uint32_t pipe, 4657 enum amdgpu_interrupt_state state) 4658 { 4659 uint32_t cp_int_cntl, cp_int_cntl_reg; 4660 4661 if (!me) { 4662 switch (pipe) { 4663 case 0: 4664 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4665 break; 4666 default: 4667 DRM_DEBUG("invalid pipe %d\n", pipe); 4668 return; 4669 } 4670 } else { 4671 DRM_DEBUG("invalid me %d\n", me); 4672 return; 4673 } 4674 4675 switch (state) { 4676 case AMDGPU_IRQ_STATE_DISABLE: 4677 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4678 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4679 TIME_STAMP_INT_ENABLE, 0); 4680 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4681 GENERIC0_INT_ENABLE, 0); 4682 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4683 break; 4684 case AMDGPU_IRQ_STATE_ENABLE: 4685 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4686 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4687 TIME_STAMP_INT_ENABLE, 1); 4688 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4689 GENERIC0_INT_ENABLE, 1); 4690 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4691 break; 4692 default: 4693 break; 4694 } 4695 } 4696 4697 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4698 int me, int pipe, 4699 enum amdgpu_interrupt_state state) 4700 { 4701 u32 mec_int_cntl, mec_int_cntl_reg; 4702 4703 /* 4704 * amdgpu controls only the first MEC. That's why this function only 4705 * handles the setting of interrupts for this specific MEC. All other 4706 * pipes' interrupts are set by amdkfd. 4707 */ 4708 4709 if (me == 1) { 4710 switch (pipe) { 4711 case 0: 4712 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4713 break; 4714 case 1: 4715 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4716 break; 4717 default: 4718 DRM_DEBUG("invalid pipe %d\n", pipe); 4719 return; 4720 } 4721 } else { 4722 DRM_DEBUG("invalid me %d\n", me); 4723 return; 4724 } 4725 4726 switch (state) { 4727 case AMDGPU_IRQ_STATE_DISABLE: 4728 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4730 TIME_STAMP_INT_ENABLE, 0); 4731 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4732 GENERIC0_INT_ENABLE, 0); 4733 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4734 break; 4735 case AMDGPU_IRQ_STATE_ENABLE: 4736 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4737 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4738 TIME_STAMP_INT_ENABLE, 1); 4739 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4740 GENERIC0_INT_ENABLE, 1); 4741 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4742 break; 4743 default: 4744 break; 4745 } 4746 } 4747 4748 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4749 struct amdgpu_irq_src *src, 4750 unsigned type, 4751 enum amdgpu_interrupt_state state) 4752 { 4753 switch (type) { 4754 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4755 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4756 break; 4757 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4758 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4759 break; 4760 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4761 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4762 break; 4763 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4764 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4765 break; 4766 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4767 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4768 break; 4769 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4770 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4771 break; 4772 default: 4773 break; 4774 } 4775 return 0; 4776 } 4777 4778 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4779 struct amdgpu_irq_src *source, 4780 struct amdgpu_iv_entry *entry) 4781 { 4782 int i; 4783 u8 me_id, pipe_id, queue_id; 4784 struct amdgpu_ring *ring; 4785 uint32_t mes_queue_id = entry->src_data[0]; 4786 4787 DRM_DEBUG("IH: CP EOP\n"); 4788 4789 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4790 struct amdgpu_mes_queue *queue; 4791 4792 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4793 4794 spin_lock(&adev->mes.queue_id_lock); 4795 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4796 if (queue) { 4797 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4798 amdgpu_fence_process(queue->ring); 4799 } 4800 spin_unlock(&adev->mes.queue_id_lock); 4801 } else { 4802 me_id = (entry->ring_id & 0x0c) >> 2; 4803 pipe_id = (entry->ring_id & 0x03) >> 0; 4804 queue_id = (entry->ring_id & 0x70) >> 4; 4805 4806 switch (me_id) { 4807 case 0: 4808 if (pipe_id == 0) 4809 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4810 else 4811 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4812 break; 4813 case 1: 4814 case 2: 4815 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4816 ring = &adev->gfx.compute_ring[i]; 4817 /* Per-queue interrupt is supported for MEC starting from VI. 4818 * The interrupt can only be enabled/disabled per pipe instead 4819 * of per queue. 4820 */ 4821 if ((ring->me == me_id) && 4822 (ring->pipe == pipe_id) && 4823 (ring->queue == queue_id)) 4824 amdgpu_fence_process(ring); 4825 } 4826 break; 4827 } 4828 } 4829 4830 return 0; 4831 } 4832 4833 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4834 struct amdgpu_irq_src *source, 4835 unsigned int type, 4836 enum amdgpu_interrupt_state state) 4837 { 4838 u32 cp_int_cntl_reg, cp_int_cntl; 4839 int i, j; 4840 4841 switch (state) { 4842 case AMDGPU_IRQ_STATE_DISABLE: 4843 case AMDGPU_IRQ_STATE_ENABLE: 4844 for (i = 0; i < adev->gfx.me.num_me; i++) { 4845 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4846 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4847 4848 if (cp_int_cntl_reg) { 4849 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4850 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4851 PRIV_REG_INT_ENABLE, 4852 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4853 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4854 } 4855 } 4856 } 4857 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4858 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4859 /* MECs start at 1 */ 4860 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4861 4862 if (cp_int_cntl_reg) { 4863 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4864 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4865 PRIV_REG_INT_ENABLE, 4866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4867 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4868 } 4869 } 4870 } 4871 break; 4872 default: 4873 break; 4874 } 4875 4876 return 0; 4877 } 4878 4879 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4880 struct amdgpu_irq_src *source, 4881 unsigned type, 4882 enum amdgpu_interrupt_state state) 4883 { 4884 u32 cp_int_cntl_reg, cp_int_cntl; 4885 int i, j; 4886 4887 switch (state) { 4888 case AMDGPU_IRQ_STATE_DISABLE: 4889 case AMDGPU_IRQ_STATE_ENABLE: 4890 for (i = 0; i < adev->gfx.me.num_me; i++) { 4891 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4892 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4893 4894 if (cp_int_cntl_reg) { 4895 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4897 OPCODE_ERROR_INT_ENABLE, 4898 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4900 } 4901 } 4902 } 4903 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4904 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4905 /* MECs start at 1 */ 4906 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4907 4908 if (cp_int_cntl_reg) { 4909 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4910 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4911 OPCODE_ERROR_INT_ENABLE, 4912 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4913 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4914 } 4915 } 4916 } 4917 break; 4918 default: 4919 break; 4920 } 4921 return 0; 4922 } 4923 4924 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4925 struct amdgpu_irq_src *source, 4926 unsigned int type, 4927 enum amdgpu_interrupt_state state) 4928 { 4929 u32 cp_int_cntl_reg, cp_int_cntl; 4930 int i, j; 4931 4932 switch (state) { 4933 case AMDGPU_IRQ_STATE_DISABLE: 4934 case AMDGPU_IRQ_STATE_ENABLE: 4935 for (i = 0; i < adev->gfx.me.num_me; i++) { 4936 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4937 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4938 4939 if (cp_int_cntl_reg) { 4940 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4941 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4942 PRIV_INSTR_INT_ENABLE, 4943 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4944 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4945 } 4946 } 4947 } 4948 break; 4949 default: 4950 break; 4951 } 4952 4953 return 0; 4954 } 4955 4956 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4957 struct amdgpu_iv_entry *entry) 4958 { 4959 u8 me_id, pipe_id, queue_id; 4960 struct amdgpu_ring *ring; 4961 int i; 4962 4963 me_id = (entry->ring_id & 0x0c) >> 2; 4964 pipe_id = (entry->ring_id & 0x03) >> 0; 4965 queue_id = (entry->ring_id & 0x70) >> 4; 4966 4967 switch (me_id) { 4968 case 0: 4969 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4970 ring = &adev->gfx.gfx_ring[i]; 4971 if (ring->me == me_id && ring->pipe == pipe_id && 4972 ring->queue == queue_id) 4973 drm_sched_fault(&ring->sched); 4974 } 4975 break; 4976 case 1: 4977 case 2: 4978 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4979 ring = &adev->gfx.compute_ring[i]; 4980 if (ring->me == me_id && ring->pipe == pipe_id && 4981 ring->queue == queue_id) 4982 drm_sched_fault(&ring->sched); 4983 } 4984 break; 4985 default: 4986 BUG(); 4987 break; 4988 } 4989 } 4990 4991 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 4992 struct amdgpu_irq_src *source, 4993 struct amdgpu_iv_entry *entry) 4994 { 4995 DRM_ERROR("Illegal register access in command stream\n"); 4996 gfx_v12_0_handle_priv_fault(adev, entry); 4997 return 0; 4998 } 4999 5000 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5001 struct amdgpu_irq_src *source, 5002 struct amdgpu_iv_entry *entry) 5003 { 5004 DRM_ERROR("Illegal opcode in command stream \n"); 5005 gfx_v12_0_handle_priv_fault(adev, entry); 5006 return 0; 5007 } 5008 5009 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5010 struct amdgpu_irq_src *source, 5011 struct amdgpu_iv_entry *entry) 5012 { 5013 DRM_ERROR("Illegal instruction in command stream\n"); 5014 gfx_v12_0_handle_priv_fault(adev, entry); 5015 return 0; 5016 } 5017 5018 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5019 { 5020 const unsigned int gcr_cntl = 5021 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5022 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5023 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5024 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5025 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5026 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5027 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5028 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5029 5030 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5031 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5032 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5033 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5034 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5035 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5036 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5037 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5038 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5039 } 5040 5041 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5042 { 5043 /* Header itself is a NOP packet */ 5044 if (num_nop == 1) { 5045 amdgpu_ring_write(ring, ring->funcs->nop); 5046 return; 5047 } 5048 5049 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5050 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5051 5052 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5053 amdgpu_ring_insert_nop(ring, num_nop - 1); 5054 } 5055 5056 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5057 { 5058 /* Emit the cleaner shader */ 5059 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5060 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5061 } 5062 5063 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5064 { 5065 struct amdgpu_device *adev = ip_block->adev; 5066 uint32_t i, j, k, reg, index = 0; 5067 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5068 5069 if (!adev->gfx.ip_dump_core) 5070 return; 5071 5072 for (i = 0; i < reg_count; i++) 5073 drm_printf(p, "%-50s \t 0x%08x\n", 5074 gc_reg_list_12_0[i].reg_name, 5075 adev->gfx.ip_dump_core[i]); 5076 5077 /* print compute queue registers for all instances */ 5078 if (!adev->gfx.ip_dump_compute_queues) 5079 return; 5080 5081 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5082 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5083 adev->gfx.mec.num_mec, 5084 adev->gfx.mec.num_pipe_per_mec, 5085 adev->gfx.mec.num_queue_per_pipe); 5086 5087 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5088 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5089 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5090 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5091 for (reg = 0; reg < reg_count; reg++) { 5092 drm_printf(p, "%-50s \t 0x%08x\n", 5093 gc_cp_reg_list_12[reg].reg_name, 5094 adev->gfx.ip_dump_compute_queues[index + reg]); 5095 } 5096 index += reg_count; 5097 } 5098 } 5099 } 5100 5101 /* print gfx queue registers for all instances */ 5102 if (!adev->gfx.ip_dump_gfx_queues) 5103 return; 5104 5105 index = 0; 5106 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5107 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5108 adev->gfx.me.num_me, 5109 adev->gfx.me.num_pipe_per_me, 5110 adev->gfx.me.num_queue_per_pipe); 5111 5112 for (i = 0; i < adev->gfx.me.num_me; i++) { 5113 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5114 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5115 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5116 for (reg = 0; reg < reg_count; reg++) { 5117 drm_printf(p, "%-50s \t 0x%08x\n", 5118 gc_gfx_queue_reg_list_12[reg].reg_name, 5119 adev->gfx.ip_dump_gfx_queues[index + reg]); 5120 } 5121 index += reg_count; 5122 } 5123 } 5124 } 5125 } 5126 5127 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5128 { 5129 struct amdgpu_device *adev = ip_block->adev; 5130 uint32_t i, j, k, reg, index = 0; 5131 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5132 5133 if (!adev->gfx.ip_dump_core) 5134 return; 5135 5136 amdgpu_gfx_off_ctrl(adev, false); 5137 for (i = 0; i < reg_count; i++) 5138 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5139 amdgpu_gfx_off_ctrl(adev, true); 5140 5141 /* dump compute queue registers for all instances */ 5142 if (!adev->gfx.ip_dump_compute_queues) 5143 return; 5144 5145 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5146 amdgpu_gfx_off_ctrl(adev, false); 5147 mutex_lock(&adev->srbm_mutex); 5148 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5149 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5150 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5151 /* ME0 is for GFX so start from 1 for CP */ 5152 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5153 for (reg = 0; reg < reg_count; reg++) { 5154 adev->gfx.ip_dump_compute_queues[index + reg] = 5155 RREG32(SOC15_REG_ENTRY_OFFSET( 5156 gc_cp_reg_list_12[reg])); 5157 } 5158 index += reg_count; 5159 } 5160 } 5161 } 5162 soc24_grbm_select(adev, 0, 0, 0, 0); 5163 mutex_unlock(&adev->srbm_mutex); 5164 amdgpu_gfx_off_ctrl(adev, true); 5165 5166 /* dump gfx queue registers for all instances */ 5167 if (!adev->gfx.ip_dump_gfx_queues) 5168 return; 5169 5170 index = 0; 5171 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5172 amdgpu_gfx_off_ctrl(adev, false); 5173 mutex_lock(&adev->srbm_mutex); 5174 for (i = 0; i < adev->gfx.me.num_me; i++) { 5175 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5176 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5177 soc24_grbm_select(adev, i, j, k, 0); 5178 5179 for (reg = 0; reg < reg_count; reg++) { 5180 adev->gfx.ip_dump_gfx_queues[index + reg] = 5181 RREG32(SOC15_REG_ENTRY_OFFSET( 5182 gc_gfx_queue_reg_list_12[reg])); 5183 } 5184 index += reg_count; 5185 } 5186 } 5187 } 5188 soc24_grbm_select(adev, 0, 0, 0, 0); 5189 mutex_unlock(&adev->srbm_mutex); 5190 amdgpu_gfx_off_ctrl(adev, true); 5191 } 5192 5193 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5194 { 5195 /* Disable the pipe reset until the CPFW fully support it.*/ 5196 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5197 return false; 5198 } 5199 5200 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5201 { 5202 struct amdgpu_device *adev = ring->adev; 5203 uint32_t reset_pipe = 0, clean_pipe = 0; 5204 int r; 5205 5206 if (!gfx_v12_pipe_reset_support(adev)) 5207 return -EOPNOTSUPP; 5208 5209 gfx_v12_0_set_safe_mode(adev, 0); 5210 mutex_lock(&adev->srbm_mutex); 5211 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5212 5213 switch (ring->pipe) { 5214 case 0: 5215 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5216 PFP_PIPE0_RESET, 1); 5217 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5218 ME_PIPE0_RESET, 1); 5219 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5220 PFP_PIPE0_RESET, 0); 5221 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5222 ME_PIPE0_RESET, 0); 5223 break; 5224 case 1: 5225 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5226 PFP_PIPE1_RESET, 1); 5227 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5228 ME_PIPE1_RESET, 1); 5229 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5230 PFP_PIPE1_RESET, 0); 5231 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5232 ME_PIPE1_RESET, 0); 5233 break; 5234 default: 5235 break; 5236 } 5237 5238 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5239 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5240 5241 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5242 RS64_FW_UC_START_ADDR_LO; 5243 soc24_grbm_select(adev, 0, 0, 0, 0); 5244 mutex_unlock(&adev->srbm_mutex); 5245 gfx_v12_0_unset_safe_mode(adev, 0); 5246 5247 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5248 r == 0 ? "successfully" : "failed"); 5249 /* Sometimes the ME start pc counter can't cache correctly, so the 5250 * PC check only as a reference and pipe reset result rely on the 5251 * later ring test. 5252 */ 5253 return 0; 5254 } 5255 5256 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5257 { 5258 struct amdgpu_device *adev = ring->adev; 5259 int r; 5260 5261 if (amdgpu_sriov_vf(adev)) 5262 return -EINVAL; 5263 5264 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5265 if (r) { 5266 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5267 r = gfx_v12_reset_gfx_pipe(ring); 5268 if (r) 5269 return r; 5270 } 5271 5272 r = gfx_v12_0_kgq_init_queue(ring, true); 5273 if (r) { 5274 dev_err(adev->dev, "failed to init kgq\n"); 5275 return r; 5276 } 5277 5278 r = amdgpu_mes_map_legacy_queue(adev, ring); 5279 if (r) { 5280 dev_err(adev->dev, "failed to remap kgq\n"); 5281 return r; 5282 } 5283 5284 return amdgpu_ring_test_ring(ring); 5285 } 5286 5287 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5288 { 5289 struct amdgpu_device *adev = ring->adev; 5290 int r; 5291 5292 if (amdgpu_sriov_vf(adev)) 5293 return -EINVAL; 5294 5295 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5296 if (r) { 5297 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5298 return r; 5299 } 5300 5301 r = gfx_v12_0_kcq_init_queue(ring, true); 5302 if (r) { 5303 dev_err(adev->dev, "failed to init kcq\n"); 5304 return r; 5305 } 5306 r = amdgpu_mes_map_legacy_queue(adev, ring); 5307 if (r) { 5308 dev_err(adev->dev, "failed to remap kcq\n"); 5309 return r; 5310 } 5311 5312 return amdgpu_ring_test_ring(ring); 5313 } 5314 5315 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5316 { 5317 amdgpu_gfx_profile_ring_begin_use(ring); 5318 5319 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5320 } 5321 5322 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5323 { 5324 amdgpu_gfx_profile_ring_end_use(ring); 5325 5326 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5327 } 5328 5329 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5330 .name = "gfx_v12_0", 5331 .early_init = gfx_v12_0_early_init, 5332 .late_init = gfx_v12_0_late_init, 5333 .sw_init = gfx_v12_0_sw_init, 5334 .sw_fini = gfx_v12_0_sw_fini, 5335 .hw_init = gfx_v12_0_hw_init, 5336 .hw_fini = gfx_v12_0_hw_fini, 5337 .suspend = gfx_v12_0_suspend, 5338 .resume = gfx_v12_0_resume, 5339 .is_idle = gfx_v12_0_is_idle, 5340 .wait_for_idle = gfx_v12_0_wait_for_idle, 5341 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5342 .set_powergating_state = gfx_v12_0_set_powergating_state, 5343 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5344 .dump_ip_state = gfx_v12_ip_dump, 5345 .print_ip_state = gfx_v12_ip_print, 5346 }; 5347 5348 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5349 .type = AMDGPU_RING_TYPE_GFX, 5350 .align_mask = 0xff, 5351 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5352 .support_64bit_ptrs = true, 5353 .secure_submission_supported = true, 5354 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5355 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5356 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5357 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5358 5 + /* COND_EXEC */ 5359 7 + /* PIPELINE_SYNC */ 5360 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5361 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5362 2 + /* VM_FLUSH */ 5363 8 + /* FENCE for VM_FLUSH */ 5364 5 + /* COND_EXEC */ 5365 7 + /* HDP_flush */ 5366 4 + /* VGT_flush */ 5367 31 + /* DE_META */ 5368 3 + /* CNTX_CTRL */ 5369 5 + /* HDP_INVL */ 5370 8 + 8 + /* FENCE x2 */ 5371 8 + /* gfx_v12_0_emit_mem_sync */ 5372 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5373 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5374 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5375 .emit_fence = gfx_v12_0_ring_emit_fence, 5376 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5377 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5378 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5379 .test_ring = gfx_v12_0_ring_test_ring, 5380 .test_ib = gfx_v12_0_ring_test_ib, 5381 .insert_nop = gfx_v12_ring_insert_nop, 5382 .pad_ib = amdgpu_ring_generic_pad_ib, 5383 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5384 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5385 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5386 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5387 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5388 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5389 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5390 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5391 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5392 .reset = gfx_v12_0_reset_kgq, 5393 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5394 .begin_use = gfx_v12_0_ring_begin_use, 5395 .end_use = gfx_v12_0_ring_end_use, 5396 }; 5397 5398 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5399 .type = AMDGPU_RING_TYPE_COMPUTE, 5400 .align_mask = 0xff, 5401 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5402 .support_64bit_ptrs = true, 5403 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5404 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5405 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5406 .emit_frame_size = 5407 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5408 5 + /* hdp invalidate */ 5409 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5410 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5411 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5412 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5413 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5414 8 + /* gfx_v12_0_emit_mem_sync */ 5415 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5416 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5417 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5418 .emit_fence = gfx_v12_0_ring_emit_fence, 5419 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5420 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5421 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5422 .test_ring = gfx_v12_0_ring_test_ring, 5423 .test_ib = gfx_v12_0_ring_test_ib, 5424 .insert_nop = gfx_v12_ring_insert_nop, 5425 .pad_ib = amdgpu_ring_generic_pad_ib, 5426 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5427 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5428 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5429 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5430 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5431 .reset = gfx_v12_0_reset_kcq, 5432 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5433 .begin_use = gfx_v12_0_ring_begin_use, 5434 .end_use = gfx_v12_0_ring_end_use, 5435 }; 5436 5437 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5438 .type = AMDGPU_RING_TYPE_KIQ, 5439 .align_mask = 0xff, 5440 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5441 .support_64bit_ptrs = true, 5442 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5443 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5444 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5445 .emit_frame_size = 5446 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5447 5 + /*hdp invalidate */ 5448 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5449 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5450 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5451 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5452 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5453 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5454 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5455 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5456 .test_ring = gfx_v12_0_ring_test_ring, 5457 .test_ib = gfx_v12_0_ring_test_ib, 5458 .insert_nop = amdgpu_ring_insert_nop, 5459 .pad_ib = amdgpu_ring_generic_pad_ib, 5460 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5461 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5462 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5463 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5464 }; 5465 5466 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5467 { 5468 int i; 5469 5470 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5471 5472 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5473 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5474 5475 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5476 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5477 } 5478 5479 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5480 .set = gfx_v12_0_set_eop_interrupt_state, 5481 .process = gfx_v12_0_eop_irq, 5482 }; 5483 5484 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5485 .set = gfx_v12_0_set_priv_reg_fault_state, 5486 .process = gfx_v12_0_priv_reg_irq, 5487 }; 5488 5489 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5490 .set = gfx_v12_0_set_bad_op_fault_state, 5491 .process = gfx_v12_0_bad_op_irq, 5492 }; 5493 5494 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5495 .set = gfx_v12_0_set_priv_inst_fault_state, 5496 .process = gfx_v12_0_priv_inst_irq, 5497 }; 5498 5499 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5500 { 5501 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5502 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5503 5504 adev->gfx.priv_reg_irq.num_types = 1; 5505 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5506 5507 adev->gfx.bad_op_irq.num_types = 1; 5508 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5509 5510 adev->gfx.priv_inst_irq.num_types = 1; 5511 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5512 } 5513 5514 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5515 { 5516 if (adev->flags & AMD_IS_APU) 5517 adev->gfx.imu.mode = MISSION_MODE; 5518 else 5519 adev->gfx.imu.mode = DEBUG_MODE; 5520 5521 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5522 } 5523 5524 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5525 { 5526 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5527 } 5528 5529 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5530 { 5531 /* set gfx eng mqd */ 5532 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5533 sizeof(struct v12_gfx_mqd); 5534 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5535 gfx_v12_0_gfx_mqd_init; 5536 /* set compute eng mqd */ 5537 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5538 sizeof(struct v12_compute_mqd); 5539 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5540 gfx_v12_0_compute_mqd_init; 5541 } 5542 5543 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5544 u32 bitmap) 5545 { 5546 u32 data; 5547 5548 if (!bitmap) 5549 return; 5550 5551 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5552 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5553 5554 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5555 } 5556 5557 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5558 { 5559 u32 data, wgp_bitmask; 5560 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5561 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5562 5563 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5564 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5565 5566 wgp_bitmask = 5567 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5568 5569 return (~data) & wgp_bitmask; 5570 } 5571 5572 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5573 { 5574 u32 wgp_idx, wgp_active_bitmap; 5575 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5576 5577 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5578 cu_active_bitmap = 0; 5579 5580 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5581 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5582 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5583 if (wgp_active_bitmap & (1 << wgp_idx)) 5584 cu_active_bitmap |= cu_bitmap_per_wgp; 5585 } 5586 5587 return cu_active_bitmap; 5588 } 5589 5590 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5591 struct amdgpu_cu_info *cu_info) 5592 { 5593 int i, j, k, counter, active_cu_number = 0; 5594 u32 mask, bitmap; 5595 unsigned disable_masks[8 * 2]; 5596 5597 if (!adev || !cu_info) 5598 return -EINVAL; 5599 5600 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5601 5602 mutex_lock(&adev->grbm_idx_mutex); 5603 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5604 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5605 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5606 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5607 continue; 5608 mask = 1; 5609 counter = 0; 5610 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5611 if (i < 8 && j < 2) 5612 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5613 adev, disable_masks[i * 2 + j]); 5614 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5615 5616 /** 5617 * GFX12 could support more than 4 SEs, while the bitmap 5618 * in cu_info struct is 4x4 and ioctl interface struct 5619 * drm_amdgpu_info_device should keep stable. 5620 * So we use last two columns of bitmap to store cu mask for 5621 * SEs 4 to 7, the layout of the bitmap is as below: 5622 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5623 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5624 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5625 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5626 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5627 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5628 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5629 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5630 */ 5631 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5632 5633 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5634 if (bitmap & mask) 5635 counter++; 5636 5637 mask <<= 1; 5638 } 5639 active_cu_number += counter; 5640 } 5641 } 5642 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5643 mutex_unlock(&adev->grbm_idx_mutex); 5644 5645 cu_info->number = active_cu_number; 5646 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5647 5648 return 0; 5649 } 5650 5651 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5652 .type = AMD_IP_BLOCK_TYPE_GFX, 5653 .major = 12, 5654 .minor = 0, 5655 .rev = 0, 5656 .funcs = &gfx_v12_0_ip_funcs, 5657 }; 5658