1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 48 #define GFX12_NUM_GFX_RINGS 1 49 #define GFX12_MEC_HPD_SIZE 2048 50 51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 52 53 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 54 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 55 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 56 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 57 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 58 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 59 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 60 61 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 62 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 63 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 64 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 65 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 66 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 67 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 68 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 69 70 71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 81 82 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 83 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 84 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 114 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 118 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 121 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 124 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 136 137 /* cp header registers */ 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 /* SE status registers */ 143 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 144 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 145 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 146 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 147 }; 148 149 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 150 /* compute registers */ 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 190 }; 191 192 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 193 /* gfx queue registers */ 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 219 }; 220 221 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 222 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 225 }; 226 227 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 228 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 229 }; 230 231 #define DEFAULT_SH_MEM_CONFIG \ 232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 234 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 235 236 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 237 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 238 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 239 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 240 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 241 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 242 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 243 struct amdgpu_cu_info *cu_info); 244 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 245 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 246 u32 sh_num, u32 instance, int xcc_id); 247 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 248 249 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 250 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 251 uint32_t val); 252 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 253 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 254 uint16_t pasid, uint32_t flush_type, 255 bool all_hub, uint8_t dst_sel); 256 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 257 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 258 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 259 bool enable); 260 261 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 262 uint64_t queue_mask) 263 { 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 265 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 266 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 267 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 268 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 269 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 270 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 271 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 272 amdgpu_ring_write(kiq_ring, 0); 273 } 274 275 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 276 struct amdgpu_ring *ring) 277 { 278 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 279 uint64_t wptr_addr = ring->wptr_gpu_addr; 280 uint32_t me = 0, eng_sel = 0; 281 282 switch (ring->funcs->type) { 283 case AMDGPU_RING_TYPE_COMPUTE: 284 me = 1; 285 eng_sel = 0; 286 break; 287 case AMDGPU_RING_TYPE_GFX: 288 me = 0; 289 eng_sel = 4; 290 break; 291 case AMDGPU_RING_TYPE_MES: 292 me = 2; 293 eng_sel = 5; 294 break; 295 default: 296 WARN_ON(1); 297 } 298 299 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 300 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 301 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 302 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 303 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 304 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 305 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 306 PACKET3_MAP_QUEUES_ME((me)) | 307 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 308 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 309 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 310 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 311 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 312 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 313 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 314 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 315 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 316 } 317 318 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 319 struct amdgpu_ring *ring, 320 enum amdgpu_unmap_queues_action action, 321 u64 gpu_addr, u64 seq) 322 { 323 struct amdgpu_device *adev = kiq_ring->adev; 324 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 325 326 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 327 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 328 return; 329 } 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_UNMAP_QUEUES_ACTION(action) | 334 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 335 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 336 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 337 amdgpu_ring_write(kiq_ring, 338 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 339 340 if (action == PREEMPT_QUEUES_NO_UNMAP) { 341 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 343 amdgpu_ring_write(kiq_ring, seq); 344 } else { 345 amdgpu_ring_write(kiq_ring, 0); 346 amdgpu_ring_write(kiq_ring, 0); 347 amdgpu_ring_write(kiq_ring, 0); 348 } 349 } 350 351 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 352 struct amdgpu_ring *ring, 353 u64 addr, u64 seq) 354 { 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 358 amdgpu_ring_write(kiq_ring, 359 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 360 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 361 PACKET3_QUERY_STATUS_COMMAND(2)); 362 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 363 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 364 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 365 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 366 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 367 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 368 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 369 } 370 371 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 372 uint16_t pasid, 373 uint32_t flush_type, 374 bool all_hub) 375 { 376 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 377 } 378 379 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 380 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 381 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 382 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 383 .kiq_query_status = gfx_v12_0_kiq_query_status, 384 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 385 .set_resources_size = 8, 386 .map_queues_size = 7, 387 .unmap_queues_size = 6, 388 .query_status_size = 7, 389 .invalidate_tlbs_size = 2, 390 }; 391 392 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 393 { 394 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 395 } 396 397 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 398 int mem_space, int opt, uint32_t addr0, 399 uint32_t addr1, uint32_t ref, 400 uint32_t mask, uint32_t inv) 401 { 402 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 403 amdgpu_ring_write(ring, 404 /* memory (1) or register (0) */ 405 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 406 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 407 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 408 WAIT_REG_MEM_ENGINE(eng_sel))); 409 410 if (mem_space) 411 BUG_ON(addr0 & 0x3); /* Dword align */ 412 amdgpu_ring_write(ring, addr0); 413 amdgpu_ring_write(ring, addr1); 414 amdgpu_ring_write(ring, ref); 415 amdgpu_ring_write(ring, mask); 416 amdgpu_ring_write(ring, inv); /* poll interval */ 417 } 418 419 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 420 { 421 struct amdgpu_device *adev = ring->adev; 422 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 423 uint32_t tmp = 0; 424 unsigned i; 425 int r; 426 427 WREG32(scratch, 0xCAFEDEAD); 428 r = amdgpu_ring_alloc(ring, 5); 429 if (r) { 430 dev_err(adev->dev, 431 "amdgpu: cp failed to lock ring %d (%d).\n", 432 ring->idx, r); 433 return r; 434 } 435 436 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 437 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 438 } else { 439 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 440 amdgpu_ring_write(ring, scratch - 441 PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 } 444 amdgpu_ring_commit(ring); 445 446 for (i = 0; i < adev->usec_timeout; i++) { 447 tmp = RREG32(scratch); 448 if (tmp == 0xDEADBEEF) 449 break; 450 if (amdgpu_emu_mode == 1) 451 msleep(1); 452 else 453 udelay(1); 454 } 455 456 if (i >= adev->usec_timeout) 457 r = -ETIMEDOUT; 458 return r; 459 } 460 461 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 462 { 463 struct amdgpu_device *adev = ring->adev; 464 struct amdgpu_ib ib; 465 struct dma_fence *f = NULL; 466 unsigned index; 467 uint64_t gpu_addr; 468 volatile uint32_t *cpu_ptr; 469 long r; 470 471 /* MES KIQ fw hasn't indirect buffer support for now */ 472 if (adev->enable_mes_kiq && 473 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 474 return 0; 475 476 memset(&ib, 0, sizeof(ib)); 477 478 if (ring->is_mes_queue) { 479 uint32_t padding, offset; 480 481 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 482 padding = amdgpu_mes_ctx_get_offs(ring, 483 AMDGPU_MES_CTX_PADDING_OFFS); 484 485 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 486 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 487 488 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 489 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 490 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 491 } else { 492 r = amdgpu_device_wb_get(adev, &index); 493 if (r) 494 return r; 495 496 gpu_addr = adev->wb.gpu_addr + (index * 4); 497 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 498 cpu_ptr = &adev->wb.wb[index]; 499 500 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 501 if (r) { 502 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 503 goto err1; 504 } 505 } 506 507 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 508 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 509 ib.ptr[2] = lower_32_bits(gpu_addr); 510 ib.ptr[3] = upper_32_bits(gpu_addr); 511 ib.ptr[4] = 0xDEADBEEF; 512 ib.length_dw = 5; 513 514 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 515 if (r) 516 goto err2; 517 518 r = dma_fence_wait_timeout(f, false, timeout); 519 if (r == 0) { 520 r = -ETIMEDOUT; 521 goto err2; 522 } else if (r < 0) { 523 goto err2; 524 } 525 526 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 527 r = 0; 528 else 529 r = -EINVAL; 530 err2: 531 if (!ring->is_mes_queue) 532 amdgpu_ib_free(&ib, NULL); 533 dma_fence_put(f); 534 err1: 535 if (!ring->is_mes_queue) 536 amdgpu_device_wb_free(adev, index); 537 return r; 538 } 539 540 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 541 { 542 amdgpu_ucode_release(&adev->gfx.pfp_fw); 543 amdgpu_ucode_release(&adev->gfx.me_fw); 544 amdgpu_ucode_release(&adev->gfx.rlc_fw); 545 amdgpu_ucode_release(&adev->gfx.mec_fw); 546 547 kfree(adev->gfx.rlc.register_list_format); 548 } 549 550 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 551 { 552 const struct psp_firmware_header_v1_0 *toc_hdr; 553 int err = 0; 554 555 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 556 AMDGPU_UCODE_REQUIRED, 557 "amdgpu/%s_toc.bin", ucode_prefix); 558 if (err) 559 goto out; 560 561 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 562 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 563 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 564 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 565 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 566 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 567 return 0; 568 out: 569 amdgpu_ucode_release(&adev->psp.toc_fw); 570 return err; 571 } 572 573 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 574 { 575 char ucode_prefix[15]; 576 int err; 577 const struct rlc_firmware_header_v2_0 *rlc_hdr; 578 uint16_t version_major; 579 uint16_t version_minor; 580 581 DRM_DEBUG("\n"); 582 583 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 584 585 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 586 AMDGPU_UCODE_REQUIRED, 587 "amdgpu/%s_pfp.bin", ucode_prefix); 588 if (err) 589 goto out; 590 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 591 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 592 593 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 594 AMDGPU_UCODE_REQUIRED, 595 "amdgpu/%s_me.bin", ucode_prefix); 596 if (err) 597 goto out; 598 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 599 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 600 601 if (!amdgpu_sriov_vf(adev)) { 602 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 603 AMDGPU_UCODE_REQUIRED, 604 "amdgpu/%s_rlc.bin", ucode_prefix); 605 if (err) 606 goto out; 607 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 608 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 609 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 610 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 611 if (err) 612 goto out; 613 } 614 615 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 616 AMDGPU_UCODE_REQUIRED, 617 "amdgpu/%s_mec.bin", ucode_prefix); 618 if (err) 619 goto out; 620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 622 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 623 624 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 625 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 626 627 /* only one MEC for gfx 12 */ 628 adev->gfx.mec2_fw = NULL; 629 630 if (adev->gfx.imu.funcs) { 631 if (adev->gfx.imu.funcs->init_microcode) { 632 err = adev->gfx.imu.funcs->init_microcode(adev); 633 if (err) 634 dev_err(adev->dev, "Failed to load imu firmware!\n"); 635 } 636 } 637 638 out: 639 if (err) { 640 amdgpu_ucode_release(&adev->gfx.pfp_fw); 641 amdgpu_ucode_release(&adev->gfx.me_fw); 642 amdgpu_ucode_release(&adev->gfx.rlc_fw); 643 amdgpu_ucode_release(&adev->gfx.mec_fw); 644 } 645 646 return err; 647 } 648 649 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 650 { 651 u32 count = 0; 652 const struct cs_section_def *sect = NULL; 653 const struct cs_extent_def *ext = NULL; 654 655 count += 1; 656 657 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 658 if (sect->id == SECT_CONTEXT) { 659 for (ext = sect->section; ext->extent != NULL; ++ext) 660 count += 2 + ext->reg_count; 661 } else 662 return 0; 663 } 664 665 return count; 666 } 667 668 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 669 volatile u32 *buffer) 670 { 671 u32 count = 0, clustercount = 0, i; 672 const struct cs_section_def *sect = NULL; 673 const struct cs_extent_def *ext = NULL; 674 675 if (adev->gfx.rlc.cs_data == NULL) 676 return; 677 if (buffer == NULL) 678 return; 679 680 count += 1; 681 682 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 683 if (sect->id == SECT_CONTEXT) { 684 for (ext = sect->section; ext->extent != NULL; ++ext) { 685 clustercount++; 686 buffer[count++] = ext->reg_count; 687 buffer[count++] = ext->reg_index; 688 689 for (i = 0; i < ext->reg_count; i++) 690 buffer[count++] = cpu_to_le32(ext->extent[i]); 691 } 692 } else 693 return; 694 } 695 696 buffer[0] = clustercount; 697 } 698 699 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 700 { 701 /* clear state block */ 702 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 703 &adev->gfx.rlc.clear_state_gpu_addr, 704 (void **)&adev->gfx.rlc.cs_ptr); 705 706 /* jump table block */ 707 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 708 &adev->gfx.rlc.cp_table_gpu_addr, 709 (void **)&adev->gfx.rlc.cp_table_ptr); 710 } 711 712 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 713 { 714 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 715 716 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 717 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 718 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 719 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 720 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 721 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 722 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 723 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 724 adev->gfx.rlc.rlcg_reg_access_supported = true; 725 } 726 727 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 728 { 729 const struct cs_section_def *cs_data; 730 int r; 731 732 adev->gfx.rlc.cs_data = gfx12_cs_data; 733 734 cs_data = adev->gfx.rlc.cs_data; 735 736 if (cs_data) { 737 /* init clear state block */ 738 r = amdgpu_gfx_rlc_init_csb(adev); 739 if (r) 740 return r; 741 } 742 743 /* init spm vmid with 0xf */ 744 if (adev->gfx.rlc.funcs->update_spm_vmid) 745 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 746 747 return 0; 748 } 749 750 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 751 { 752 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 753 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 754 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 755 } 756 757 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 758 { 759 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 760 761 amdgpu_gfx_graphics_queue_acquire(adev); 762 } 763 764 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 765 { 766 int r; 767 u32 *hpd; 768 size_t mec_hpd_size; 769 770 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 771 772 /* take ownership of the relevant compute queues */ 773 amdgpu_gfx_compute_queue_acquire(adev); 774 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 775 776 if (mec_hpd_size) { 777 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 778 AMDGPU_GEM_DOMAIN_GTT, 779 &adev->gfx.mec.hpd_eop_obj, 780 &adev->gfx.mec.hpd_eop_gpu_addr, 781 (void **)&hpd); 782 if (r) { 783 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 784 gfx_v12_0_mec_fini(adev); 785 return r; 786 } 787 788 memset(hpd, 0, mec_hpd_size); 789 790 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 791 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 792 } 793 794 return 0; 795 } 796 797 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 798 { 799 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 800 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 801 (address << SQ_IND_INDEX__INDEX__SHIFT)); 802 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 803 } 804 805 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 806 uint32_t thread, uint32_t regno, 807 uint32_t num, uint32_t *out) 808 { 809 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 810 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 811 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 812 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 813 (SQ_IND_INDEX__AUTO_INCR_MASK)); 814 while (num--) 815 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 816 } 817 818 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 819 uint32_t xcc_id, 820 uint32_t simd, uint32_t wave, 821 uint32_t *dst, int *no_fields) 822 { 823 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 824 * field when performing a select_se_sh so it should be 825 * zero here */ 826 WARN_ON(simd != 0); 827 828 /* type 4 wave data */ 829 dst[(*no_fields)++] = 4; 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 837 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 838 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 839 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 840 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 841 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 842 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 843 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 853 } 854 855 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 856 uint32_t xcc_id, uint32_t simd, 857 uint32_t wave, uint32_t start, 858 uint32_t size, uint32_t *dst) 859 { 860 WARN_ON(simd != 0); 861 862 wave_read_regs( 863 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 864 dst); 865 } 866 867 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 868 uint32_t xcc_id, uint32_t simd, 869 uint32_t wave, uint32_t thread, 870 uint32_t start, uint32_t size, 871 uint32_t *dst) 872 { 873 wave_read_regs( 874 adev, wave, thread, 875 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 876 } 877 878 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 879 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 880 { 881 soc24_grbm_select(adev, me, pipe, q, vm); 882 } 883 884 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 885 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 886 .select_se_sh = &gfx_v12_0_select_se_sh, 887 .read_wave_data = &gfx_v12_0_read_wave_data, 888 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 889 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 890 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 891 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 892 }; 893 894 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 895 { 896 897 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 898 case IP_VERSION(12, 0, 0): 899 case IP_VERSION(12, 0, 1): 900 adev->gfx.config.max_hw_contexts = 8; 901 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 902 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 903 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 904 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 905 break; 906 default: 907 BUG(); 908 break; 909 } 910 911 return 0; 912 } 913 914 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 915 int me, int pipe, int queue) 916 { 917 int r; 918 struct amdgpu_ring *ring; 919 unsigned int irq_type; 920 921 ring = &adev->gfx.gfx_ring[ring_id]; 922 923 ring->me = me; 924 ring->pipe = pipe; 925 ring->queue = queue; 926 927 ring->ring_obj = NULL; 928 ring->use_doorbell = true; 929 930 if (!ring_id) 931 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 932 else 933 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 934 ring->vm_hub = AMDGPU_GFXHUB(0); 935 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 936 937 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 938 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 939 AMDGPU_RING_PRIO_DEFAULT, NULL); 940 if (r) 941 return r; 942 return 0; 943 } 944 945 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 946 int mec, int pipe, int queue) 947 { 948 int r; 949 unsigned irq_type; 950 struct amdgpu_ring *ring; 951 unsigned int hw_prio; 952 953 ring = &adev->gfx.compute_ring[ring_id]; 954 955 /* mec0 is me1 */ 956 ring->me = mec + 1; 957 ring->pipe = pipe; 958 ring->queue = queue; 959 960 ring->ring_obj = NULL; 961 ring->use_doorbell = true; 962 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 963 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 964 + (ring_id * GFX12_MEC_HPD_SIZE); 965 ring->vm_hub = AMDGPU_GFXHUB(0); 966 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 967 968 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 969 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 970 + ring->pipe; 971 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 972 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 973 /* type-2 packets are deprecated on MEC, use type-3 instead */ 974 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 975 hw_prio, NULL); 976 if (r) 977 return r; 978 979 return 0; 980 } 981 982 static struct { 983 SOC24_FIRMWARE_ID id; 984 unsigned int offset; 985 unsigned int size; 986 unsigned int size_x16; 987 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 988 989 #define RLC_TOC_OFFSET_DWUNIT 8 990 #define RLC_SIZE_MULTIPLE 1024 991 #define RLC_TOC_UMF_SIZE_inM 23ULL 992 #define RLC_TOC_FORMAT_API 165ULL 993 994 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 995 { 996 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 997 998 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 999 rlc_autoload_info[ucode->id].id = ucode->id; 1000 rlc_autoload_info[ucode->id].offset = 1001 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1002 rlc_autoload_info[ucode->id].size = 1003 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1004 ucode->size * 4; 1005 ucode++; 1006 } 1007 } 1008 1009 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1010 { 1011 uint32_t total_size = 0; 1012 SOC24_FIRMWARE_ID id; 1013 1014 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1015 1016 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1017 total_size += rlc_autoload_info[id].size; 1018 1019 /* In case the offset in rlc toc ucode is aligned */ 1020 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1021 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1022 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1023 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1024 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1025 1026 return total_size; 1027 } 1028 1029 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1030 { 1031 int r; 1032 uint32_t total_size; 1033 1034 total_size = gfx_v12_0_calc_toc_total_size(adev); 1035 1036 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1037 AMDGPU_GEM_DOMAIN_VRAM, 1038 &adev->gfx.rlc.rlc_autoload_bo, 1039 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1040 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1041 1042 if (r) { 1043 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1044 return r; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1051 SOC24_FIRMWARE_ID id, 1052 const void *fw_data, 1053 uint32_t fw_size) 1054 { 1055 uint32_t toc_offset; 1056 uint32_t toc_fw_size; 1057 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1058 1059 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1060 return; 1061 1062 toc_offset = rlc_autoload_info[id].offset; 1063 toc_fw_size = rlc_autoload_info[id].size; 1064 1065 if (fw_size == 0) 1066 fw_size = toc_fw_size; 1067 1068 if (fw_size > toc_fw_size) 1069 fw_size = toc_fw_size; 1070 1071 memcpy(ptr + toc_offset, fw_data, fw_size); 1072 1073 if (fw_size < toc_fw_size) 1074 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1075 } 1076 1077 static void 1078 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1079 { 1080 void *data; 1081 uint32_t size; 1082 uint32_t *toc_ptr; 1083 1084 data = adev->psp.toc.start_addr; 1085 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1086 1087 toc_ptr = (uint32_t *)data + size / 4 - 2; 1088 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1089 1090 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1091 data, size); 1092 } 1093 1094 static void 1095 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1096 { 1097 const __le32 *fw_data; 1098 uint32_t fw_size; 1099 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1100 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1101 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1102 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1103 uint16_t version_major, version_minor; 1104 1105 /* pfp ucode */ 1106 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1107 adev->gfx.pfp_fw->data; 1108 /* instruction */ 1109 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1110 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1111 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1112 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1113 fw_data, fw_size); 1114 /* data */ 1115 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1116 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1117 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1118 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1119 fw_data, fw_size); 1120 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1121 fw_data, fw_size); 1122 /* me ucode */ 1123 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1124 adev->gfx.me_fw->data; 1125 /* instruction */ 1126 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1127 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1128 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1129 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1130 fw_data, fw_size); 1131 /* data */ 1132 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1133 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1134 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1135 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1136 fw_data, fw_size); 1137 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1138 fw_data, fw_size); 1139 /* mec ucode */ 1140 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1141 adev->gfx.mec_fw->data; 1142 /* instruction */ 1143 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1144 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1145 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1146 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1147 fw_data, fw_size); 1148 /* data */ 1149 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1150 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1151 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1152 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1153 fw_data, fw_size); 1154 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1155 fw_data, fw_size); 1156 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1157 fw_data, fw_size); 1158 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1159 fw_data, fw_size); 1160 1161 /* rlc ucode */ 1162 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1163 adev->gfx.rlc_fw->data; 1164 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1165 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1166 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1168 fw_data, fw_size); 1169 1170 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1171 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1172 if (version_major == 2) { 1173 if (version_minor >= 1) { 1174 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1175 1176 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1177 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1178 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1179 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1180 fw_data, fw_size); 1181 1182 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1183 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1184 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1186 fw_data, fw_size); 1187 } 1188 if (version_minor >= 2) { 1189 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1190 1191 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1192 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1193 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1194 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1195 fw_data, fw_size); 1196 1197 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1198 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1199 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1200 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1201 fw_data, fw_size); 1202 } 1203 } 1204 } 1205 1206 static void 1207 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1208 { 1209 const __le32 *fw_data; 1210 uint32_t fw_size; 1211 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1212 1213 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1214 adev->sdma.instance[0].fw->data; 1215 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1216 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1217 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1218 1219 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1220 fw_data, fw_size); 1221 } 1222 1223 static void 1224 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1225 { 1226 const __le32 *fw_data; 1227 unsigned fw_size; 1228 const struct mes_firmware_header_v1_0 *mes_hdr; 1229 int pipe, ucode_id, data_id; 1230 1231 for (pipe = 0; pipe < 2; pipe++) { 1232 if (pipe == 0) { 1233 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1234 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1235 } else { 1236 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1237 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1238 } 1239 1240 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1241 adev->mes.fw[pipe]->data; 1242 1243 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1244 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1245 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1246 1247 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1248 1249 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1250 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1251 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1252 1253 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1254 } 1255 } 1256 1257 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1258 { 1259 uint32_t rlc_g_offset, rlc_g_size; 1260 uint64_t gpu_addr; 1261 uint32_t data; 1262 1263 /* RLC autoload sequence 2: copy ucode */ 1264 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1265 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1266 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1267 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1268 1269 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1270 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1271 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1272 1273 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1275 1276 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1277 1278 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1279 /* RLC autoload sequence 3: load IMU fw */ 1280 if (adev->gfx.imu.funcs->load_microcode) 1281 adev->gfx.imu.funcs->load_microcode(adev); 1282 /* RLC autoload sequence 4 init IMU fw */ 1283 if (adev->gfx.imu.funcs->setup_imu) 1284 adev->gfx.imu.funcs->setup_imu(adev); 1285 if (adev->gfx.imu.funcs->start_imu) 1286 adev->gfx.imu.funcs->start_imu(adev); 1287 1288 /* RLC autoload sequence 5 disable gpa mode */ 1289 gfx_v12_0_disable_gpa_mode(adev); 1290 } else { 1291 /* unhalt rlc to start autoload without imu */ 1292 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1293 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1294 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1295 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1296 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1303 { 1304 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1305 uint32_t *ptr; 1306 uint32_t inst; 1307 1308 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1309 if (!ptr) { 1310 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1311 adev->gfx.ip_dump_core = NULL; 1312 } else { 1313 adev->gfx.ip_dump_core = ptr; 1314 } 1315 1316 /* Allocate memory for compute queue registers for all the instances */ 1317 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1318 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1319 adev->gfx.mec.num_queue_per_pipe; 1320 1321 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1322 if (!ptr) { 1323 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1324 adev->gfx.ip_dump_compute_queues = NULL; 1325 } else { 1326 adev->gfx.ip_dump_compute_queues = ptr; 1327 } 1328 1329 /* Allocate memory for gfx queue registers for all the instances */ 1330 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1331 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1332 adev->gfx.me.num_queue_per_pipe; 1333 1334 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1335 if (!ptr) { 1336 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1337 adev->gfx.ip_dump_gfx_queues = NULL; 1338 } else { 1339 adev->gfx.ip_dump_gfx_queues = ptr; 1340 } 1341 } 1342 1343 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1344 { 1345 int i, j, k, r, ring_id = 0; 1346 unsigned num_compute_rings; 1347 int xcc_id = 0; 1348 struct amdgpu_device *adev = ip_block->adev; 1349 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1350 1351 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1352 1353 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1354 case IP_VERSION(12, 0, 0): 1355 case IP_VERSION(12, 0, 1): 1356 adev->gfx.me.num_me = 1; 1357 adev->gfx.me.num_pipe_per_me = 1; 1358 adev->gfx.me.num_queue_per_pipe = 8; 1359 adev->gfx.mec.num_mec = 1; 1360 adev->gfx.mec.num_pipe_per_mec = 2; 1361 adev->gfx.mec.num_queue_per_pipe = 4; 1362 break; 1363 default: 1364 adev->gfx.me.num_me = 1; 1365 adev->gfx.me.num_pipe_per_me = 1; 1366 adev->gfx.me.num_queue_per_pipe = 1; 1367 adev->gfx.mec.num_mec = 1; 1368 adev->gfx.mec.num_pipe_per_mec = 4; 1369 adev->gfx.mec.num_queue_per_pipe = 8; 1370 break; 1371 } 1372 1373 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1374 case IP_VERSION(12, 0, 0): 1375 case IP_VERSION(12, 0, 1): 1376 if (adev->gfx.me_fw_version >= 2480 && 1377 adev->gfx.pfp_fw_version >= 2530 && 1378 adev->gfx.mec_fw_version >= 2680 && 1379 adev->mes.fw_version[0] >= 100) 1380 adev->gfx.enable_cleaner_shader = true; 1381 break; 1382 default: 1383 adev->gfx.enable_cleaner_shader = false; 1384 break; 1385 } 1386 1387 /* recalculate compute rings to use based on hardware configuration */ 1388 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1389 adev->gfx.mec.num_queue_per_pipe) / 2; 1390 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1391 num_compute_rings); 1392 1393 /* EOP Event */ 1394 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1395 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1396 &adev->gfx.eop_irq); 1397 if (r) 1398 return r; 1399 1400 /* Bad opcode Event */ 1401 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1402 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1403 &adev->gfx.bad_op_irq); 1404 if (r) 1405 return r; 1406 1407 /* Privileged reg */ 1408 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1409 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1410 &adev->gfx.priv_reg_irq); 1411 if (r) 1412 return r; 1413 1414 /* Privileged inst */ 1415 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1416 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1417 &adev->gfx.priv_inst_irq); 1418 if (r) 1419 return r; 1420 1421 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1422 1423 gfx_v12_0_me_init(adev); 1424 1425 r = gfx_v12_0_rlc_init(adev); 1426 if (r) { 1427 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1428 return r; 1429 } 1430 1431 r = gfx_v12_0_mec_init(adev); 1432 if (r) { 1433 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1434 return r; 1435 } 1436 1437 /* set up the gfx ring */ 1438 for (i = 0; i < adev->gfx.me.num_me; i++) { 1439 for (j = 0; j < num_queue_per_pipe; j++) { 1440 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1441 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1442 continue; 1443 1444 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1445 i, k, j); 1446 if (r) 1447 return r; 1448 ring_id++; 1449 } 1450 } 1451 } 1452 1453 ring_id = 0; 1454 /* set up the compute queues - allocate horizontally across pipes */ 1455 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1456 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1457 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1458 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1459 0, i, k, j)) 1460 continue; 1461 1462 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1463 i, k, j); 1464 if (r) 1465 return r; 1466 1467 ring_id++; 1468 } 1469 } 1470 } 1471 1472 adev->gfx.gfx_supported_reset = 1473 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1474 adev->gfx.compute_supported_reset = 1475 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1476 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1477 case IP_VERSION(12, 0, 0): 1478 case IP_VERSION(12, 0, 1): 1479 if ((adev->gfx.me_fw_version >= 2660) && 1480 (adev->gfx.mec_fw_version >= 2920)) { 1481 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1482 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1483 } 1484 } 1485 1486 if (!adev->enable_mes_kiq) { 1487 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1488 if (r) { 1489 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1490 return r; 1491 } 1492 1493 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1494 if (r) 1495 return r; 1496 } 1497 1498 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1499 if (r) 1500 return r; 1501 1502 /* allocate visible FB for rlc auto-loading fw */ 1503 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1504 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1505 if (r) 1506 return r; 1507 } 1508 1509 r = gfx_v12_0_gpu_early_init(adev); 1510 if (r) 1511 return r; 1512 1513 gfx_v12_0_alloc_ip_dump(adev); 1514 1515 r = amdgpu_gfx_sysfs_init(adev); 1516 if (r) 1517 return r; 1518 1519 return 0; 1520 } 1521 1522 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1523 { 1524 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1525 &adev->gfx.pfp.pfp_fw_gpu_addr, 1526 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1527 1528 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1529 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1530 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1531 } 1532 1533 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1534 { 1535 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1536 &adev->gfx.me.me_fw_gpu_addr, 1537 (void **)&adev->gfx.me.me_fw_ptr); 1538 1539 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1540 &adev->gfx.me.me_fw_data_gpu_addr, 1541 (void **)&adev->gfx.me.me_fw_data_ptr); 1542 } 1543 1544 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1545 { 1546 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1547 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1548 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1549 } 1550 1551 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1552 { 1553 int i; 1554 struct amdgpu_device *adev = ip_block->adev; 1555 1556 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1557 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1558 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1559 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1560 1561 amdgpu_gfx_mqd_sw_fini(adev, 0); 1562 1563 if (!adev->enable_mes_kiq) { 1564 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1565 amdgpu_gfx_kiq_fini(adev, 0); 1566 } 1567 1568 gfx_v12_0_pfp_fini(adev); 1569 gfx_v12_0_me_fini(adev); 1570 gfx_v12_0_rlc_fini(adev); 1571 gfx_v12_0_mec_fini(adev); 1572 1573 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1574 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1575 1576 gfx_v12_0_free_microcode(adev); 1577 1578 amdgpu_gfx_sysfs_fini(adev); 1579 1580 kfree(adev->gfx.ip_dump_core); 1581 kfree(adev->gfx.ip_dump_compute_queues); 1582 kfree(adev->gfx.ip_dump_gfx_queues); 1583 1584 return 0; 1585 } 1586 1587 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1588 u32 sh_num, u32 instance, int xcc_id) 1589 { 1590 u32 data; 1591 1592 if (instance == 0xffffffff) 1593 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1594 INSTANCE_BROADCAST_WRITES, 1); 1595 else 1596 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1597 instance); 1598 1599 if (se_num == 0xffffffff) 1600 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1601 1); 1602 else 1603 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1604 1605 if (sh_num == 0xffffffff) 1606 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1607 1); 1608 else 1609 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1610 1611 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1612 } 1613 1614 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1615 { 1616 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1617 1618 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1619 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1620 GRBM_CC_GC_SA_UNIT_DISABLE, 1621 SA_DISABLE); 1622 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1623 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1624 GRBM_GC_USER_SA_UNIT_DISABLE, 1625 SA_DISABLE); 1626 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1627 adev->gfx.config.max_shader_engines); 1628 1629 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1630 } 1631 1632 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1633 { 1634 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1635 u32 rb_mask; 1636 1637 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1638 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1639 CC_RB_BACKEND_DISABLE, 1640 BACKEND_DISABLE); 1641 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1642 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1643 GC_USER_RB_BACKEND_DISABLE, 1644 BACKEND_DISABLE); 1645 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1646 adev->gfx.config.max_shader_engines); 1647 1648 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1649 } 1650 1651 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1652 { 1653 u32 rb_bitmap_per_sa; 1654 u32 rb_bitmap_width_per_sa; 1655 u32 max_sa; 1656 u32 active_sa_bitmap; 1657 u32 global_active_rb_bitmap; 1658 u32 active_rb_bitmap = 0; 1659 u32 i; 1660 1661 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1662 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1663 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1664 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1665 1666 /* generate active rb bitmap according to active sa bitmap */ 1667 max_sa = adev->gfx.config.max_shader_engines * 1668 adev->gfx.config.max_sh_per_se; 1669 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1670 adev->gfx.config.max_sh_per_se; 1671 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1672 1673 for (i = 0; i < max_sa; i++) { 1674 if (active_sa_bitmap & (1 << i)) 1675 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1676 } 1677 1678 active_rb_bitmap &= global_active_rb_bitmap; 1679 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1680 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1681 } 1682 1683 #define LDS_APP_BASE 0x1 1684 #define SCRATCH_APP_BASE 0x2 1685 1686 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1687 { 1688 int i; 1689 uint32_t sh_mem_bases; 1690 uint32_t data; 1691 1692 /* 1693 * Configure apertures: 1694 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1695 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1696 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1697 */ 1698 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1699 SCRATCH_APP_BASE; 1700 1701 mutex_lock(&adev->srbm_mutex); 1702 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1703 soc24_grbm_select(adev, 0, 0, 0, i); 1704 /* CP and shaders */ 1705 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1706 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1707 1708 /* Enable trap for each kfd vmid. */ 1709 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1710 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1711 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1712 } 1713 soc24_grbm_select(adev, 0, 0, 0, 0); 1714 mutex_unlock(&adev->srbm_mutex); 1715 } 1716 1717 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1718 { 1719 /* TODO: harvest feature to be added later. */ 1720 } 1721 1722 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1723 { 1724 } 1725 1726 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1727 { 1728 u32 tmp; 1729 int i; 1730 1731 if (!amdgpu_sriov_vf(adev)) 1732 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1733 1734 gfx_v12_0_setup_rb(adev); 1735 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1736 gfx_v12_0_get_tcc_info(adev); 1737 adev->gfx.config.pa_sc_tile_steering_override = 0; 1738 1739 /* XXX SH_MEM regs */ 1740 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1741 mutex_lock(&adev->srbm_mutex); 1742 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1743 soc24_grbm_select(adev, 0, 0, 0, i); 1744 /* CP and shaders */ 1745 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1746 if (i != 0) { 1747 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1748 (adev->gmc.private_aperture_start >> 48)); 1749 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1750 (adev->gmc.shared_aperture_start >> 48)); 1751 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1752 } 1753 } 1754 soc24_grbm_select(adev, 0, 0, 0, 0); 1755 1756 mutex_unlock(&adev->srbm_mutex); 1757 1758 gfx_v12_0_init_compute_vmid(adev); 1759 } 1760 1761 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1762 int me, int pipe) 1763 { 1764 if (me != 0) 1765 return 0; 1766 1767 switch (pipe) { 1768 case 0: 1769 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1770 default: 1771 return 0; 1772 } 1773 } 1774 1775 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1776 int me, int pipe) 1777 { 1778 /* 1779 * amdgpu controls only the first MEC. That's why this function only 1780 * handles the setting of interrupts for this specific MEC. All other 1781 * pipes' interrupts are set by amdkfd. 1782 */ 1783 if (me != 1) 1784 return 0; 1785 1786 switch (pipe) { 1787 case 0: 1788 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1789 case 1: 1790 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1791 default: 1792 return 0; 1793 } 1794 } 1795 1796 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1797 bool enable) 1798 { 1799 u32 tmp, cp_int_cntl_reg; 1800 int i, j; 1801 1802 if (amdgpu_sriov_vf(adev)) 1803 return; 1804 1805 for (i = 0; i < adev->gfx.me.num_me; i++) { 1806 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1807 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1808 1809 if (cp_int_cntl_reg) { 1810 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1811 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1812 enable ? 1 : 0); 1813 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1814 enable ? 1 : 0); 1815 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1816 enable ? 1 : 0); 1817 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1818 enable ? 1 : 0); 1819 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1820 } 1821 } 1822 } 1823 } 1824 1825 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1826 { 1827 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1828 1829 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1830 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1831 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1832 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1833 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1834 1835 return 0; 1836 } 1837 1838 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1839 { 1840 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1841 1842 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1843 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1844 } 1845 1846 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1847 { 1848 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1849 udelay(50); 1850 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1851 udelay(50); 1852 } 1853 1854 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1855 bool enable) 1856 { 1857 uint32_t rlc_pg_cntl; 1858 1859 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1860 1861 if (!enable) { 1862 /* RLC_PG_CNTL[23] = 0 (default) 1863 * RLC will wait for handshake acks with SMU 1864 * GFXOFF will be enabled 1865 * RLC_PG_CNTL[23] = 1 1866 * RLC will not issue any message to SMU 1867 * hence no handshake between SMU & RLC 1868 * GFXOFF will be disabled 1869 */ 1870 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1871 } else 1872 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1873 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1874 } 1875 1876 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1877 { 1878 /* TODO: enable rlc & smu handshake until smu 1879 * and gfxoff feature works as expected */ 1880 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1881 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1882 1883 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1884 udelay(50); 1885 } 1886 1887 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1888 { 1889 uint32_t tmp; 1890 1891 /* enable Save Restore Machine */ 1892 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1893 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1894 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1895 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1896 } 1897 1898 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1899 { 1900 const struct rlc_firmware_header_v2_0 *hdr; 1901 const __le32 *fw_data; 1902 unsigned i, fw_size; 1903 1904 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1905 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1906 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1907 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1908 1909 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1910 RLCG_UCODE_LOADING_START_ADDRESS); 1911 1912 for (i = 0; i < fw_size; i++) 1913 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1914 le32_to_cpup(fw_data++)); 1915 1916 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1917 } 1918 1919 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1920 { 1921 const struct rlc_firmware_header_v2_2 *hdr; 1922 const __le32 *fw_data; 1923 unsigned i, fw_size; 1924 u32 tmp; 1925 1926 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1927 1928 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1929 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1930 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1931 1932 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1933 1934 for (i = 0; i < fw_size; i++) { 1935 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1936 msleep(1); 1937 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1938 le32_to_cpup(fw_data++)); 1939 } 1940 1941 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1942 1943 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1944 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1945 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1946 1947 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1948 for (i = 0; i < fw_size; i++) { 1949 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1950 msleep(1); 1951 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1952 le32_to_cpup(fw_data++)); 1953 } 1954 1955 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1956 1957 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1958 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1959 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1960 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1961 } 1962 1963 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1964 { 1965 const struct rlc_firmware_header_v2_0 *hdr; 1966 uint16_t version_major; 1967 uint16_t version_minor; 1968 1969 if (!adev->gfx.rlc_fw) 1970 return -EINVAL; 1971 1972 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1973 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1974 1975 version_major = le16_to_cpu(hdr->header.header_version_major); 1976 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1977 1978 if (version_major == 2) { 1979 gfx_v12_0_load_rlcg_microcode(adev); 1980 if (amdgpu_dpm == 1) { 1981 if (version_minor >= 2) 1982 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1983 } 1984 1985 return 0; 1986 } 1987 1988 return -EINVAL; 1989 } 1990 1991 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1992 { 1993 int r; 1994 1995 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1996 gfx_v12_0_init_csb(adev); 1997 1998 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1999 gfx_v12_0_rlc_enable_srm(adev); 2000 } else { 2001 if (amdgpu_sriov_vf(adev)) { 2002 gfx_v12_0_init_csb(adev); 2003 return 0; 2004 } 2005 2006 adev->gfx.rlc.funcs->stop(adev); 2007 2008 /* disable CG */ 2009 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2010 2011 /* disable PG */ 2012 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2013 2014 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2015 /* legacy rlc firmware loading */ 2016 r = gfx_v12_0_rlc_load_microcode(adev); 2017 if (r) 2018 return r; 2019 } 2020 2021 gfx_v12_0_init_csb(adev); 2022 2023 adev->gfx.rlc.funcs->start(adev); 2024 } 2025 2026 return 0; 2027 } 2028 2029 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2030 { 2031 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2032 const struct gfx_firmware_header_v2_0 *me_hdr; 2033 const struct gfx_firmware_header_v2_0 *mec_hdr; 2034 uint32_t pipe_id, tmp; 2035 2036 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2037 adev->gfx.mec_fw->data; 2038 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2039 adev->gfx.me_fw->data; 2040 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2041 adev->gfx.pfp_fw->data; 2042 2043 /* config pfp program start addr */ 2044 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2045 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2046 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2047 (pfp_hdr->ucode_start_addr_hi << 30) | 2048 (pfp_hdr->ucode_start_addr_lo >> 2)); 2049 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2050 pfp_hdr->ucode_start_addr_hi >> 2); 2051 } 2052 soc24_grbm_select(adev, 0, 0, 0, 0); 2053 2054 /* reset pfp pipe */ 2055 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2056 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2057 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2058 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2059 2060 /* clear pfp pipe reset */ 2061 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2062 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2063 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2064 2065 /* config me program start addr */ 2066 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2067 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2068 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2069 (me_hdr->ucode_start_addr_hi << 30) | 2070 (me_hdr->ucode_start_addr_lo >> 2)); 2071 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2072 me_hdr->ucode_start_addr_hi>>2); 2073 } 2074 soc24_grbm_select(adev, 0, 0, 0, 0); 2075 2076 /* reset me pipe */ 2077 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2079 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2080 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2081 2082 /* clear me pipe reset */ 2083 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2084 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2085 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2086 2087 /* config mec program start addr */ 2088 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2089 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2090 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2091 mec_hdr->ucode_start_addr_lo >> 2 | 2092 mec_hdr->ucode_start_addr_hi << 30); 2093 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2094 mec_hdr->ucode_start_addr_hi >> 2); 2095 } 2096 soc24_grbm_select(adev, 0, 0, 0, 0); 2097 2098 /* reset mec pipe */ 2099 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2100 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2101 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2102 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2103 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2104 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2105 2106 /* clear mec pipe reset */ 2107 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2108 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2109 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2110 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2111 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2112 } 2113 2114 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2115 { 2116 const struct gfx_firmware_header_v2_0 *cp_hdr; 2117 unsigned pipe_id, tmp; 2118 2119 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2120 adev->gfx.pfp_fw->data; 2121 mutex_lock(&adev->srbm_mutex); 2122 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2123 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2124 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2125 (cp_hdr->ucode_start_addr_hi << 30) | 2126 (cp_hdr->ucode_start_addr_lo >> 2)); 2127 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2128 cp_hdr->ucode_start_addr_hi>>2); 2129 2130 /* 2131 * Program CP_ME_CNTL to reset given PIPE to take 2132 * effect of CP_PFP_PRGRM_CNTR_START. 2133 */ 2134 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2135 if (pipe_id == 0) 2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2137 PFP_PIPE0_RESET, 1); 2138 else 2139 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2140 PFP_PIPE1_RESET, 1); 2141 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2142 2143 /* Clear pfp pipe0 reset bit. */ 2144 if (pipe_id == 0) 2145 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2146 PFP_PIPE0_RESET, 0); 2147 else 2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2149 PFP_PIPE1_RESET, 0); 2150 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2151 } 2152 soc24_grbm_select(adev, 0, 0, 0, 0); 2153 mutex_unlock(&adev->srbm_mutex); 2154 } 2155 2156 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2157 { 2158 const struct gfx_firmware_header_v2_0 *cp_hdr; 2159 unsigned pipe_id, tmp; 2160 2161 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2162 adev->gfx.me_fw->data; 2163 mutex_lock(&adev->srbm_mutex); 2164 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2165 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2166 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2167 (cp_hdr->ucode_start_addr_hi << 30) | 2168 (cp_hdr->ucode_start_addr_lo >> 2) ); 2169 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2170 cp_hdr->ucode_start_addr_hi>>2); 2171 2172 /* 2173 * Program CP_ME_CNTL to reset given PIPE to take 2174 * effect of CP_ME_PRGRM_CNTR_START. 2175 */ 2176 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2177 if (pipe_id == 0) 2178 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2179 ME_PIPE0_RESET, 1); 2180 else 2181 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2182 ME_PIPE1_RESET, 1); 2183 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2184 2185 /* Clear pfp pipe0 reset bit. */ 2186 if (pipe_id == 0) 2187 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2188 ME_PIPE0_RESET, 0); 2189 else 2190 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2191 ME_PIPE1_RESET, 0); 2192 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2193 } 2194 soc24_grbm_select(adev, 0, 0, 0, 0); 2195 mutex_unlock(&adev->srbm_mutex); 2196 } 2197 2198 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2199 { 2200 const struct gfx_firmware_header_v2_0 *cp_hdr; 2201 unsigned pipe_id; 2202 2203 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2204 adev->gfx.mec_fw->data; 2205 mutex_lock(&adev->srbm_mutex); 2206 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2207 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2208 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2209 cp_hdr->ucode_start_addr_lo >> 2 | 2210 cp_hdr->ucode_start_addr_hi << 30); 2211 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2212 cp_hdr->ucode_start_addr_hi >> 2); 2213 } 2214 soc24_grbm_select(adev, 0, 0, 0, 0); 2215 mutex_unlock(&adev->srbm_mutex); 2216 } 2217 2218 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2219 { 2220 uint32_t cp_status; 2221 uint32_t bootload_status; 2222 int i; 2223 2224 for (i = 0; i < adev->usec_timeout; i++) { 2225 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2226 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2227 2228 if ((cp_status == 0) && 2229 (REG_GET_FIELD(bootload_status, 2230 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2231 break; 2232 } 2233 udelay(1); 2234 if (amdgpu_emu_mode) 2235 msleep(10); 2236 } 2237 2238 if (i >= adev->usec_timeout) { 2239 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2240 return -ETIMEDOUT; 2241 } 2242 2243 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2244 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2245 gfx_v12_0_set_me_ucode_start_addr(adev); 2246 gfx_v12_0_set_mec_ucode_start_addr(adev); 2247 } 2248 2249 return 0; 2250 } 2251 2252 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2253 { 2254 int i; 2255 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2256 2257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2259 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2260 2261 for (i = 0; i < adev->usec_timeout; i++) { 2262 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2263 break; 2264 udelay(1); 2265 } 2266 2267 if (i >= adev->usec_timeout) 2268 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2269 2270 return 0; 2271 } 2272 2273 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2274 { 2275 int r; 2276 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2277 const __le32 *fw_ucode, *fw_data; 2278 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2279 uint32_t tmp; 2280 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2281 2282 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2283 adev->gfx.pfp_fw->data; 2284 2285 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2286 2287 /* instruction */ 2288 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2289 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2290 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2291 /* data */ 2292 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2293 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2294 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2295 2296 /* 64kb align */ 2297 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2298 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2299 &adev->gfx.pfp.pfp_fw_obj, 2300 &adev->gfx.pfp.pfp_fw_gpu_addr, 2301 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2302 if (r) { 2303 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2304 gfx_v12_0_pfp_fini(adev); 2305 return r; 2306 } 2307 2308 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2309 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2310 &adev->gfx.pfp.pfp_fw_data_obj, 2311 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2312 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2313 if (r) { 2314 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2315 gfx_v12_0_pfp_fini(adev); 2316 return r; 2317 } 2318 2319 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2320 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2321 2322 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2323 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2324 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2325 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2326 2327 if (amdgpu_emu_mode == 1) 2328 adev->hdp.funcs->flush_hdp(adev, NULL); 2329 2330 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2331 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2332 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2333 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2334 2335 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2336 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2337 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2338 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2339 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2340 2341 /* 2342 * Programming any of the CP_PFP_IC_BASE registers 2343 * forces invalidation of the ME L1 I$. Wait for the 2344 * invalidation complete 2345 */ 2346 for (i = 0; i < usec_timeout; i++) { 2347 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2348 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2349 INVALIDATE_CACHE_COMPLETE)) 2350 break; 2351 udelay(1); 2352 } 2353 2354 if (i >= usec_timeout) { 2355 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2356 return -EINVAL; 2357 } 2358 2359 /* Prime the L1 instruction caches */ 2360 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2361 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2362 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2363 /* Waiting for cache primed*/ 2364 for (i = 0; i < usec_timeout; i++) { 2365 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2366 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2367 ICACHE_PRIMED)) 2368 break; 2369 udelay(1); 2370 } 2371 2372 if (i >= usec_timeout) { 2373 dev_err(adev->dev, "failed to prime instruction cache\n"); 2374 return -EINVAL; 2375 } 2376 2377 mutex_lock(&adev->srbm_mutex); 2378 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2379 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2380 2381 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2382 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2383 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2384 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2385 } 2386 soc24_grbm_select(adev, 0, 0, 0, 0); 2387 mutex_unlock(&adev->srbm_mutex); 2388 2389 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2390 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2391 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2392 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2393 2394 /* Invalidate the data caches */ 2395 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2396 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2397 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2398 2399 for (i = 0; i < usec_timeout; i++) { 2400 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2401 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2402 INVALIDATE_DCACHE_COMPLETE)) 2403 break; 2404 udelay(1); 2405 } 2406 2407 if (i >= usec_timeout) { 2408 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2409 return -EINVAL; 2410 } 2411 2412 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2413 2414 return 0; 2415 } 2416 2417 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2418 { 2419 int r; 2420 const struct gfx_firmware_header_v2_0 *me_hdr; 2421 const __le32 *fw_ucode, *fw_data; 2422 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2423 uint32_t tmp; 2424 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2425 2426 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2427 adev->gfx.me_fw->data; 2428 2429 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2430 2431 /* instruction */ 2432 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2433 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2434 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2435 /* data */ 2436 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2437 le32_to_cpu(me_hdr->data_offset_bytes)); 2438 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2439 2440 /* 64kb align*/ 2441 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2442 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2443 &adev->gfx.me.me_fw_obj, 2444 &adev->gfx.me.me_fw_gpu_addr, 2445 (void **)&adev->gfx.me.me_fw_ptr); 2446 if (r) { 2447 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2448 gfx_v12_0_me_fini(adev); 2449 return r; 2450 } 2451 2452 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2453 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2454 &adev->gfx.me.me_fw_data_obj, 2455 &adev->gfx.me.me_fw_data_gpu_addr, 2456 (void **)&adev->gfx.me.me_fw_data_ptr); 2457 if (r) { 2458 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2459 gfx_v12_0_me_fini(adev); 2460 return r; 2461 } 2462 2463 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2464 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2465 2466 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2467 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2468 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2469 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2470 2471 if (amdgpu_emu_mode == 1) 2472 adev->hdp.funcs->flush_hdp(adev, NULL); 2473 2474 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2475 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2476 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2477 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2478 2479 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2480 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2481 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2482 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2483 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2484 2485 /* 2486 * Programming any of the CP_ME_IC_BASE registers 2487 * forces invalidation of the ME L1 I$. Wait for the 2488 * invalidation complete 2489 */ 2490 for (i = 0; i < usec_timeout; i++) { 2491 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2492 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2493 INVALIDATE_CACHE_COMPLETE)) 2494 break; 2495 udelay(1); 2496 } 2497 2498 if (i >= usec_timeout) { 2499 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2500 return -EINVAL; 2501 } 2502 2503 /* Prime the instruction caches */ 2504 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2505 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2506 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2507 2508 /* Waiting for instruction cache primed*/ 2509 for (i = 0; i < usec_timeout; i++) { 2510 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2511 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2512 ICACHE_PRIMED)) 2513 break; 2514 udelay(1); 2515 } 2516 2517 if (i >= usec_timeout) { 2518 dev_err(adev->dev, "failed to prime instruction cache\n"); 2519 return -EINVAL; 2520 } 2521 2522 mutex_lock(&adev->srbm_mutex); 2523 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2524 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2525 2526 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2527 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2528 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2529 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2530 } 2531 soc24_grbm_select(adev, 0, 0, 0, 0); 2532 mutex_unlock(&adev->srbm_mutex); 2533 2534 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2535 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2536 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2537 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2538 2539 /* Invalidate the data caches */ 2540 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2541 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2542 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2543 2544 for (i = 0; i < usec_timeout; i++) { 2545 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2546 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2547 INVALIDATE_DCACHE_COMPLETE)) 2548 break; 2549 udelay(1); 2550 } 2551 2552 if (i >= usec_timeout) { 2553 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2554 return -EINVAL; 2555 } 2556 2557 gfx_v12_0_set_me_ucode_start_addr(adev); 2558 2559 return 0; 2560 } 2561 2562 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2563 { 2564 int r; 2565 2566 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2567 return -EINVAL; 2568 2569 gfx_v12_0_cp_gfx_enable(adev, false); 2570 2571 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2572 if (r) { 2573 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2574 return r; 2575 } 2576 2577 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2578 if (r) { 2579 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2580 return r; 2581 } 2582 2583 return 0; 2584 } 2585 2586 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2587 { 2588 /* init the CP */ 2589 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2590 adev->gfx.config.max_hw_contexts - 1); 2591 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2592 2593 if (!amdgpu_async_gfx_ring) 2594 gfx_v12_0_cp_gfx_enable(adev, true); 2595 2596 return 0; 2597 } 2598 2599 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2600 CP_PIPE_ID pipe) 2601 { 2602 u32 tmp; 2603 2604 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2605 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2606 2607 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2608 } 2609 2610 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2611 struct amdgpu_ring *ring) 2612 { 2613 u32 tmp; 2614 2615 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2616 if (ring->use_doorbell) { 2617 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2618 DOORBELL_OFFSET, ring->doorbell_index); 2619 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2620 DOORBELL_EN, 1); 2621 } else { 2622 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2623 DOORBELL_EN, 0); 2624 } 2625 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2626 2627 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2628 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2629 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2630 2631 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2632 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2633 } 2634 2635 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2636 { 2637 struct amdgpu_ring *ring; 2638 u32 tmp; 2639 u32 rb_bufsz; 2640 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2641 2642 /* Set the write pointer delay */ 2643 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2644 2645 /* set the RB to use vmid 0 */ 2646 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2647 2648 /* Init gfx ring 0 for pipe 0 */ 2649 mutex_lock(&adev->srbm_mutex); 2650 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2651 2652 /* Set ring buffer size */ 2653 ring = &adev->gfx.gfx_ring[0]; 2654 rb_bufsz = order_base_2(ring->ring_size / 8); 2655 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2656 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2657 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2658 2659 /* Initialize the ring buffer's write pointers */ 2660 ring->wptr = 0; 2661 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2662 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2663 2664 /* set the wb address whether it's enabled or not */ 2665 rptr_addr = ring->rptr_gpu_addr; 2666 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2667 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2668 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2669 2670 wptr_gpu_addr = ring->wptr_gpu_addr; 2671 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2672 lower_32_bits(wptr_gpu_addr)); 2673 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2674 upper_32_bits(wptr_gpu_addr)); 2675 2676 mdelay(1); 2677 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2678 2679 rb_addr = ring->gpu_addr >> 8; 2680 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2681 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2682 2683 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2684 2685 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2686 mutex_unlock(&adev->srbm_mutex); 2687 2688 /* Switch to pipe 0 */ 2689 mutex_lock(&adev->srbm_mutex); 2690 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2691 mutex_unlock(&adev->srbm_mutex); 2692 2693 /* start the ring */ 2694 gfx_v12_0_cp_gfx_start(adev); 2695 return 0; 2696 } 2697 2698 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2699 { 2700 u32 data; 2701 2702 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2703 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2704 enable ? 0 : 1); 2705 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2706 enable ? 0 : 1); 2707 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2708 enable ? 0 : 1); 2709 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2710 enable ? 0 : 1); 2711 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2712 enable ? 0 : 1); 2713 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2714 enable ? 1 : 0); 2715 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2716 enable ? 1 : 0); 2717 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2718 enable ? 1 : 0); 2719 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2720 enable ? 1 : 0); 2721 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2722 enable ? 0 : 1); 2723 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2724 2725 adev->gfx.kiq[0].ring.sched.ready = enable; 2726 2727 udelay(50); 2728 } 2729 2730 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2731 { 2732 const struct gfx_firmware_header_v2_0 *mec_hdr; 2733 const __le32 *fw_ucode, *fw_data; 2734 u32 tmp, fw_ucode_size, fw_data_size; 2735 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2736 u32 *fw_ucode_ptr, *fw_data_ptr; 2737 int r; 2738 2739 if (!adev->gfx.mec_fw) 2740 return -EINVAL; 2741 2742 gfx_v12_0_cp_compute_enable(adev, false); 2743 2744 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2745 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2746 2747 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2748 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2749 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2750 2751 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2752 le32_to_cpu(mec_hdr->data_offset_bytes)); 2753 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2754 2755 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2756 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2757 &adev->gfx.mec.mec_fw_obj, 2758 &adev->gfx.mec.mec_fw_gpu_addr, 2759 (void **)&fw_ucode_ptr); 2760 if (r) { 2761 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2762 gfx_v12_0_mec_fini(adev); 2763 return r; 2764 } 2765 2766 r = amdgpu_bo_create_reserved(adev, 2767 ALIGN(fw_data_size, 64 * 1024) * 2768 adev->gfx.mec.num_pipe_per_mec, 2769 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2770 &adev->gfx.mec.mec_fw_data_obj, 2771 &adev->gfx.mec.mec_fw_data_gpu_addr, 2772 (void **)&fw_data_ptr); 2773 if (r) { 2774 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2775 gfx_v12_0_mec_fini(adev); 2776 return r; 2777 } 2778 2779 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2780 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2781 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2782 } 2783 2784 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2785 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2786 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2787 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2788 2789 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2790 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2791 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2792 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2793 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2794 2795 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2796 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2797 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2798 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2799 2800 mutex_lock(&adev->srbm_mutex); 2801 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2802 soc24_grbm_select(adev, 1, i, 0, 0); 2803 2804 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2805 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2806 i * ALIGN(fw_data_size, 64 * 1024))); 2807 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2808 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2809 i * ALIGN(fw_data_size, 64 * 1024))); 2810 2811 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2812 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2813 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2814 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2815 } 2816 mutex_unlock(&adev->srbm_mutex); 2817 soc24_grbm_select(adev, 0, 0, 0, 0); 2818 2819 /* Trigger an invalidation of the L1 instruction caches */ 2820 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2821 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2822 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2823 2824 /* Wait for invalidation complete */ 2825 for (i = 0; i < usec_timeout; i++) { 2826 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2827 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2828 INVALIDATE_DCACHE_COMPLETE)) 2829 break; 2830 udelay(1); 2831 } 2832 2833 if (i >= usec_timeout) { 2834 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2835 return -EINVAL; 2836 } 2837 2838 /* Trigger an invalidation of the L1 instruction caches */ 2839 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2840 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2841 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2842 2843 /* Wait for invalidation complete */ 2844 for (i = 0; i < usec_timeout; i++) { 2845 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2846 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2847 INVALIDATE_CACHE_COMPLETE)) 2848 break; 2849 udelay(1); 2850 } 2851 2852 if (i >= usec_timeout) { 2853 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2854 return -EINVAL; 2855 } 2856 2857 gfx_v12_0_set_mec_ucode_start_addr(adev); 2858 2859 return 0; 2860 } 2861 2862 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2863 { 2864 uint32_t tmp; 2865 struct amdgpu_device *adev = ring->adev; 2866 2867 /* tell RLC which is KIQ queue */ 2868 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2869 tmp &= 0xffffff00; 2870 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2871 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2872 } 2873 2874 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2875 { 2876 /* set graphics engine doorbell range */ 2877 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2878 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2879 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2880 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2881 2882 /* set compute engine doorbell range */ 2883 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2884 (adev->doorbell_index.kiq * 2) << 2); 2885 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2886 (adev->doorbell_index.userqueue_end * 2) << 2); 2887 } 2888 2889 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2890 struct amdgpu_mqd_prop *prop) 2891 { 2892 struct v12_gfx_mqd *mqd = m; 2893 uint64_t hqd_gpu_addr, wb_gpu_addr; 2894 uint32_t tmp; 2895 uint32_t rb_bufsz; 2896 2897 /* set up gfx hqd wptr */ 2898 mqd->cp_gfx_hqd_wptr = 0; 2899 mqd->cp_gfx_hqd_wptr_hi = 0; 2900 2901 /* set the pointer to the MQD */ 2902 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2903 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2904 2905 /* set up mqd control */ 2906 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2907 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2908 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2909 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2910 mqd->cp_gfx_mqd_control = tmp; 2911 2912 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2913 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2914 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2915 mqd->cp_gfx_hqd_vmid = 0; 2916 2917 /* set up default queue priority level 2918 * 0x0 = low priority, 0x1 = high priority */ 2919 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2920 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2921 mqd->cp_gfx_hqd_queue_priority = tmp; 2922 2923 /* set up time quantum */ 2924 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2925 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2926 mqd->cp_gfx_hqd_quantum = tmp; 2927 2928 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2929 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2930 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2931 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2932 2933 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2934 wb_gpu_addr = prop->rptr_gpu_addr; 2935 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2936 mqd->cp_gfx_hqd_rptr_addr_hi = 2937 upper_32_bits(wb_gpu_addr) & 0xffff; 2938 2939 /* set up rb_wptr_poll addr */ 2940 wb_gpu_addr = prop->wptr_gpu_addr; 2941 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2942 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2943 2944 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2945 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2946 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 2947 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2948 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2949 #ifdef __BIG_ENDIAN 2950 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2951 #endif 2952 mqd->cp_gfx_hqd_cntl = tmp; 2953 2954 /* set up cp_doorbell_control */ 2955 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 2956 if (prop->use_doorbell) { 2957 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2958 DOORBELL_OFFSET, prop->doorbell_index); 2959 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2960 DOORBELL_EN, 1); 2961 } else 2962 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2963 DOORBELL_EN, 0); 2964 mqd->cp_rb_doorbell_control = tmp; 2965 2966 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2967 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 2968 2969 /* active the queue */ 2970 mqd->cp_gfx_hqd_active = 1; 2971 2972 return 0; 2973 } 2974 2975 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2976 { 2977 struct amdgpu_device *adev = ring->adev; 2978 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2979 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2980 2981 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2982 memset((void *)mqd, 0, sizeof(*mqd)); 2983 mutex_lock(&adev->srbm_mutex); 2984 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2985 amdgpu_ring_init_mqd(ring); 2986 soc24_grbm_select(adev, 0, 0, 0, 0); 2987 mutex_unlock(&adev->srbm_mutex); 2988 if (adev->gfx.me.mqd_backup[mqd_idx]) 2989 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2990 } else { 2991 /* restore mqd with the backup copy */ 2992 if (adev->gfx.me.mqd_backup[mqd_idx]) 2993 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2994 /* reset the ring */ 2995 ring->wptr = 0; 2996 *ring->wptr_cpu_addr = 0; 2997 amdgpu_ring_clear_ring(ring); 2998 } 2999 3000 return 0; 3001 } 3002 3003 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3004 { 3005 int i, r; 3006 3007 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3008 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3009 if (r) 3010 return r; 3011 } 3012 3013 r = amdgpu_gfx_enable_kgq(adev, 0); 3014 if (r) 3015 return r; 3016 3017 return gfx_v12_0_cp_gfx_start(adev); 3018 } 3019 3020 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3021 struct amdgpu_mqd_prop *prop) 3022 { 3023 struct v12_compute_mqd *mqd = m; 3024 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3025 uint32_t tmp; 3026 3027 mqd->header = 0xC0310800; 3028 mqd->compute_pipelinestat_enable = 0x00000001; 3029 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3030 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3031 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3032 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3033 mqd->compute_misc_reserved = 0x00000007; 3034 3035 eop_base_addr = prop->eop_gpu_addr >> 8; 3036 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3037 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3038 3039 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3040 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3041 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3042 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3043 3044 mqd->cp_hqd_eop_control = tmp; 3045 3046 /* enable doorbell? */ 3047 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3048 3049 if (prop->use_doorbell) { 3050 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3051 DOORBELL_OFFSET, prop->doorbell_index); 3052 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3053 DOORBELL_EN, 1); 3054 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3055 DOORBELL_SOURCE, 0); 3056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3057 DOORBELL_HIT, 0); 3058 } else { 3059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3060 DOORBELL_EN, 0); 3061 } 3062 3063 mqd->cp_hqd_pq_doorbell_control = tmp; 3064 3065 /* disable the queue if it's active */ 3066 mqd->cp_hqd_dequeue_request = 0; 3067 mqd->cp_hqd_pq_rptr = 0; 3068 mqd->cp_hqd_pq_wptr_lo = 0; 3069 mqd->cp_hqd_pq_wptr_hi = 0; 3070 3071 /* set the pointer to the MQD */ 3072 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3073 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3074 3075 /* set MQD vmid to 0 */ 3076 tmp = regCP_MQD_CONTROL_DEFAULT; 3077 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3078 mqd->cp_mqd_control = tmp; 3079 3080 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3081 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3082 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3083 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3084 3085 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3086 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3087 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3088 (order_base_2(prop->queue_size / 4) - 1)); 3089 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3090 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3093 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3094 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3095 mqd->cp_hqd_pq_control = tmp; 3096 3097 /* set the wb address whether it's enabled or not */ 3098 wb_gpu_addr = prop->rptr_gpu_addr; 3099 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3100 mqd->cp_hqd_pq_rptr_report_addr_hi = 3101 upper_32_bits(wb_gpu_addr) & 0xffff; 3102 3103 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3104 wb_gpu_addr = prop->wptr_gpu_addr; 3105 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3106 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3107 3108 tmp = 0; 3109 /* enable the doorbell if requested */ 3110 if (prop->use_doorbell) { 3111 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3112 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3113 DOORBELL_OFFSET, prop->doorbell_index); 3114 3115 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3116 DOORBELL_EN, 1); 3117 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3118 DOORBELL_SOURCE, 0); 3119 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3120 DOORBELL_HIT, 0); 3121 } 3122 3123 mqd->cp_hqd_pq_doorbell_control = tmp; 3124 3125 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3126 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3127 3128 /* set the vmid for the queue */ 3129 mqd->cp_hqd_vmid = 0; 3130 3131 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3132 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3133 mqd->cp_hqd_persistent_state = tmp; 3134 3135 /* set MIN_IB_AVAIL_SIZE */ 3136 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3137 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3138 mqd->cp_hqd_ib_control = tmp; 3139 3140 /* set static priority for a compute queue/ring */ 3141 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3142 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3143 3144 mqd->cp_hqd_active = prop->hqd_active; 3145 3146 return 0; 3147 } 3148 3149 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3150 { 3151 struct amdgpu_device *adev = ring->adev; 3152 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3153 int j; 3154 3155 /* inactivate the queue */ 3156 if (amdgpu_sriov_vf(adev)) 3157 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3158 3159 /* disable wptr polling */ 3160 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3161 3162 /* write the EOP addr */ 3163 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3164 mqd->cp_hqd_eop_base_addr_lo); 3165 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3166 mqd->cp_hqd_eop_base_addr_hi); 3167 3168 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3169 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3170 mqd->cp_hqd_eop_control); 3171 3172 /* enable doorbell? */ 3173 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3174 mqd->cp_hqd_pq_doorbell_control); 3175 3176 /* disable the queue if it's active */ 3177 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3178 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3179 for (j = 0; j < adev->usec_timeout; j++) { 3180 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3181 break; 3182 udelay(1); 3183 } 3184 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3185 mqd->cp_hqd_dequeue_request); 3186 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3187 mqd->cp_hqd_pq_rptr); 3188 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3189 mqd->cp_hqd_pq_wptr_lo); 3190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3191 mqd->cp_hqd_pq_wptr_hi); 3192 } 3193 3194 /* set the pointer to the MQD */ 3195 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3196 mqd->cp_mqd_base_addr_lo); 3197 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3198 mqd->cp_mqd_base_addr_hi); 3199 3200 /* set MQD vmid to 0 */ 3201 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3202 mqd->cp_mqd_control); 3203 3204 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3206 mqd->cp_hqd_pq_base_lo); 3207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3208 mqd->cp_hqd_pq_base_hi); 3209 3210 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3211 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3212 mqd->cp_hqd_pq_control); 3213 3214 /* set the wb address whether it's enabled or not */ 3215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3216 mqd->cp_hqd_pq_rptr_report_addr_lo); 3217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3218 mqd->cp_hqd_pq_rptr_report_addr_hi); 3219 3220 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3221 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3222 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3223 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3224 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3225 3226 /* enable the doorbell if requested */ 3227 if (ring->use_doorbell) { 3228 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3229 (adev->doorbell_index.kiq * 2) << 2); 3230 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3231 (adev->doorbell_index.userqueue_end * 2) << 2); 3232 } 3233 3234 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3235 mqd->cp_hqd_pq_doorbell_control); 3236 3237 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3238 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3239 mqd->cp_hqd_pq_wptr_lo); 3240 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3241 mqd->cp_hqd_pq_wptr_hi); 3242 3243 /* set the vmid for the queue */ 3244 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3245 3246 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3247 mqd->cp_hqd_persistent_state); 3248 3249 /* activate the queue */ 3250 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3251 mqd->cp_hqd_active); 3252 3253 if (ring->use_doorbell) 3254 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3255 3256 return 0; 3257 } 3258 3259 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3260 { 3261 struct amdgpu_device *adev = ring->adev; 3262 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3263 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3264 3265 gfx_v12_0_kiq_setting(ring); 3266 3267 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3268 /* reset MQD to a clean status */ 3269 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3270 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3271 3272 /* reset ring buffer */ 3273 ring->wptr = 0; 3274 amdgpu_ring_clear_ring(ring); 3275 3276 mutex_lock(&adev->srbm_mutex); 3277 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3278 gfx_v12_0_kiq_init_register(ring); 3279 soc24_grbm_select(adev, 0, 0, 0, 0); 3280 mutex_unlock(&adev->srbm_mutex); 3281 } else { 3282 memset((void *)mqd, 0, sizeof(*mqd)); 3283 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3284 amdgpu_ring_clear_ring(ring); 3285 mutex_lock(&adev->srbm_mutex); 3286 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3287 amdgpu_ring_init_mqd(ring); 3288 gfx_v12_0_kiq_init_register(ring); 3289 soc24_grbm_select(adev, 0, 0, 0, 0); 3290 mutex_unlock(&adev->srbm_mutex); 3291 3292 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3293 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3294 } 3295 3296 return 0; 3297 } 3298 3299 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3300 { 3301 struct amdgpu_device *adev = ring->adev; 3302 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3303 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3304 3305 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3306 memset((void *)mqd, 0, sizeof(*mqd)); 3307 mutex_lock(&adev->srbm_mutex); 3308 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3309 amdgpu_ring_init_mqd(ring); 3310 soc24_grbm_select(adev, 0, 0, 0, 0); 3311 mutex_unlock(&adev->srbm_mutex); 3312 3313 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3314 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3315 } else { 3316 /* restore MQD to a clean status */ 3317 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3318 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3319 /* reset ring buffer */ 3320 ring->wptr = 0; 3321 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3322 amdgpu_ring_clear_ring(ring); 3323 } 3324 3325 return 0; 3326 } 3327 3328 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3329 { 3330 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3331 adev->gfx.kiq[0].ring.sched.ready = true; 3332 return 0; 3333 } 3334 3335 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3336 { 3337 int i, r; 3338 3339 if (!amdgpu_async_gfx_ring) 3340 gfx_v12_0_cp_compute_enable(adev, true); 3341 3342 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3343 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3344 if (r) 3345 return r; 3346 } 3347 3348 return amdgpu_gfx_enable_kcq(adev, 0); 3349 } 3350 3351 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3352 { 3353 int r, i; 3354 struct amdgpu_ring *ring; 3355 3356 if (!(adev->flags & AMD_IS_APU)) 3357 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3358 3359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3360 /* legacy firmware loading */ 3361 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3362 if (r) 3363 return r; 3364 3365 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3366 if (r) 3367 return r; 3368 } 3369 3370 gfx_v12_0_cp_set_doorbell_range(adev); 3371 3372 if (amdgpu_async_gfx_ring) { 3373 gfx_v12_0_cp_compute_enable(adev, true); 3374 gfx_v12_0_cp_gfx_enable(adev, true); 3375 } 3376 3377 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3378 r = amdgpu_mes_kiq_hw_init(adev); 3379 else 3380 r = gfx_v12_0_kiq_resume(adev); 3381 if (r) 3382 return r; 3383 3384 r = gfx_v12_0_kcq_resume(adev); 3385 if (r) 3386 return r; 3387 3388 if (!amdgpu_async_gfx_ring) { 3389 r = gfx_v12_0_cp_gfx_resume(adev); 3390 if (r) 3391 return r; 3392 } else { 3393 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3394 if (r) 3395 return r; 3396 } 3397 3398 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3399 ring = &adev->gfx.gfx_ring[i]; 3400 r = amdgpu_ring_test_helper(ring); 3401 if (r) 3402 return r; 3403 } 3404 3405 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3406 ring = &adev->gfx.compute_ring[i]; 3407 r = amdgpu_ring_test_helper(ring); 3408 if (r) 3409 return r; 3410 } 3411 3412 return 0; 3413 } 3414 3415 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3416 { 3417 gfx_v12_0_cp_gfx_enable(adev, enable); 3418 gfx_v12_0_cp_compute_enable(adev, enable); 3419 } 3420 3421 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3422 { 3423 int r; 3424 bool value; 3425 3426 r = adev->gfxhub.funcs->gart_enable(adev); 3427 if (r) 3428 return r; 3429 3430 adev->hdp.funcs->flush_hdp(adev, NULL); 3431 3432 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3433 false : true; 3434 3435 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3436 /* TODO investigate why this and the hdp flush above is needed, 3437 * are we missing a flush somewhere else? */ 3438 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3439 3440 return 0; 3441 } 3442 3443 static int get_gb_addr_config(struct amdgpu_device *adev) 3444 { 3445 u32 gb_addr_config; 3446 3447 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3448 if (gb_addr_config == 0) 3449 return -EINVAL; 3450 3451 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3452 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3453 3454 adev->gfx.config.gb_addr_config = gb_addr_config; 3455 3456 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3457 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3458 GB_ADDR_CONFIG, NUM_PIPES); 3459 3460 adev->gfx.config.max_tile_pipes = 3461 adev->gfx.config.gb_addr_config_fields.num_pipes; 3462 3463 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3464 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3465 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3466 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3467 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3468 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3469 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3470 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3471 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3472 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3473 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3474 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3475 3476 return 0; 3477 } 3478 3479 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3480 { 3481 uint32_t data; 3482 3483 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3484 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3485 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3486 3487 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3488 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3489 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3490 } 3491 3492 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3493 { 3494 if (amdgpu_sriov_vf(adev)) 3495 return; 3496 3497 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3498 case IP_VERSION(12, 0, 0): 3499 case IP_VERSION(12, 0, 1): 3500 soc15_program_register_sequence(adev, 3501 golden_settings_gc_12_0, 3502 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3503 3504 if (adev->rev_id == 0) 3505 soc15_program_register_sequence(adev, 3506 golden_settings_gc_12_0_rev0, 3507 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3508 break; 3509 default: 3510 break; 3511 } 3512 } 3513 3514 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3515 { 3516 int r; 3517 struct amdgpu_device *adev = ip_block->adev; 3518 3519 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3520 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3521 /* RLC autoload sequence 1: Program rlc ram */ 3522 if (adev->gfx.imu.funcs->program_rlc_ram) 3523 adev->gfx.imu.funcs->program_rlc_ram(adev); 3524 } 3525 /* rlc autoload firmware */ 3526 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3527 if (r) 3528 return r; 3529 } else { 3530 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3531 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3532 if (adev->gfx.imu.funcs->load_microcode) 3533 adev->gfx.imu.funcs->load_microcode(adev); 3534 if (adev->gfx.imu.funcs->setup_imu) 3535 adev->gfx.imu.funcs->setup_imu(adev); 3536 if (adev->gfx.imu.funcs->start_imu) 3537 adev->gfx.imu.funcs->start_imu(adev); 3538 } 3539 3540 /* disable gpa mode in backdoor loading */ 3541 gfx_v12_0_disable_gpa_mode(adev); 3542 } 3543 } 3544 3545 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3546 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3547 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3548 if (r) { 3549 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3550 return r; 3551 } 3552 } 3553 3554 if (!amdgpu_emu_mode) 3555 gfx_v12_0_init_golden_registers(adev); 3556 3557 adev->gfx.is_poweron = true; 3558 3559 if (get_gb_addr_config(adev)) 3560 DRM_WARN("Invalid gb_addr_config !\n"); 3561 3562 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3563 gfx_v12_0_config_gfx_rs64(adev); 3564 3565 r = gfx_v12_0_gfxhub_enable(adev); 3566 if (r) 3567 return r; 3568 3569 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3570 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3571 (amdgpu_dpm == 1)) { 3572 /** 3573 * For gfx 12, rlc firmware loading relies on smu firmware is 3574 * loaded firstly, so in direct type, it has to load smc ucode 3575 * here before rlc. 3576 */ 3577 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3578 if (r) 3579 return r; 3580 } 3581 3582 gfx_v12_0_constants_init(adev); 3583 3584 if (adev->nbio.funcs->gc_doorbell_init) 3585 adev->nbio.funcs->gc_doorbell_init(adev); 3586 3587 r = gfx_v12_0_rlc_resume(adev); 3588 if (r) 3589 return r; 3590 3591 /* 3592 * init golden registers and rlc resume may override some registers, 3593 * reconfig them here 3594 */ 3595 gfx_v12_0_tcp_harvest(adev); 3596 3597 r = gfx_v12_0_cp_resume(adev); 3598 if (r) 3599 return r; 3600 3601 return r; 3602 } 3603 3604 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3605 { 3606 struct amdgpu_device *adev = ip_block->adev; 3607 uint32_t tmp; 3608 3609 cancel_delayed_work_sync(&adev->gfx.idle_work); 3610 3611 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3612 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3613 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3614 3615 if (!adev->no_hw_access) { 3616 if (amdgpu_async_gfx_ring) { 3617 if (amdgpu_gfx_disable_kgq(adev, 0)) 3618 DRM_ERROR("KGQ disable failed\n"); 3619 } 3620 3621 if (amdgpu_gfx_disable_kcq(adev, 0)) 3622 DRM_ERROR("KCQ disable failed\n"); 3623 3624 amdgpu_mes_kiq_hw_fini(adev); 3625 } 3626 3627 if (amdgpu_sriov_vf(adev)) { 3628 gfx_v12_0_cp_gfx_enable(adev, false); 3629 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3630 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3631 tmp &= 0xffffff00; 3632 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3633 3634 return 0; 3635 } 3636 gfx_v12_0_cp_enable(adev, false); 3637 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3638 3639 adev->gfxhub.funcs->gart_disable(adev); 3640 3641 adev->gfx.is_poweron = false; 3642 3643 return 0; 3644 } 3645 3646 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3647 { 3648 return gfx_v12_0_hw_fini(ip_block); 3649 } 3650 3651 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3652 { 3653 return gfx_v12_0_hw_init(ip_block); 3654 } 3655 3656 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3657 { 3658 struct amdgpu_device *adev = ip_block->adev; 3659 3660 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3661 GRBM_STATUS, GUI_ACTIVE)) 3662 return false; 3663 else 3664 return true; 3665 } 3666 3667 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3668 { 3669 unsigned i; 3670 u32 tmp; 3671 struct amdgpu_device *adev = ip_block->adev; 3672 3673 for (i = 0; i < adev->usec_timeout; i++) { 3674 /* read MC_STATUS */ 3675 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3676 GRBM_STATUS__GUI_ACTIVE_MASK; 3677 3678 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3679 return 0; 3680 udelay(1); 3681 } 3682 return -ETIMEDOUT; 3683 } 3684 3685 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3686 { 3687 uint64_t clock = 0; 3688 3689 if (adev->smuio.funcs && 3690 adev->smuio.funcs->get_gpu_clock_counter) 3691 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3692 else 3693 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3694 3695 return clock; 3696 } 3697 3698 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3699 { 3700 struct amdgpu_device *adev = ip_block->adev; 3701 3702 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3703 3704 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3705 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3706 AMDGPU_MAX_COMPUTE_RINGS); 3707 3708 gfx_v12_0_set_kiq_pm4_funcs(adev); 3709 gfx_v12_0_set_ring_funcs(adev); 3710 gfx_v12_0_set_irq_funcs(adev); 3711 gfx_v12_0_set_rlc_funcs(adev); 3712 gfx_v12_0_set_mqd_funcs(adev); 3713 gfx_v12_0_set_imu_funcs(adev); 3714 3715 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3716 3717 return gfx_v12_0_init_microcode(adev); 3718 } 3719 3720 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3721 { 3722 struct amdgpu_device *adev = ip_block->adev; 3723 int r; 3724 3725 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3726 if (r) 3727 return r; 3728 3729 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3730 if (r) 3731 return r; 3732 3733 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3734 if (r) 3735 return r; 3736 3737 return 0; 3738 } 3739 3740 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3741 { 3742 uint32_t rlc_cntl; 3743 3744 /* if RLC is not enabled, do nothing */ 3745 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3746 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3747 } 3748 3749 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3750 int xcc_id) 3751 { 3752 uint32_t data; 3753 unsigned i; 3754 3755 data = RLC_SAFE_MODE__CMD_MASK; 3756 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3757 3758 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3759 3760 /* wait for RLC_SAFE_MODE */ 3761 for (i = 0; i < adev->usec_timeout; i++) { 3762 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3763 RLC_SAFE_MODE, CMD)) 3764 break; 3765 udelay(1); 3766 } 3767 } 3768 3769 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3770 int xcc_id) 3771 { 3772 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3773 } 3774 3775 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3776 bool enable) 3777 { 3778 uint32_t def, data; 3779 3780 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3781 return; 3782 3783 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3784 3785 if (enable) 3786 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3787 else 3788 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3789 3790 if (def != data) 3791 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3792 } 3793 3794 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3795 struct amdgpu_ring *ring, 3796 unsigned vmid) 3797 { 3798 u32 reg, data; 3799 3800 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3801 if (amdgpu_sriov_is_pp_one_vf(adev)) 3802 data = RREG32_NO_KIQ(reg); 3803 else 3804 data = RREG32(reg); 3805 3806 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3807 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3808 3809 if (amdgpu_sriov_is_pp_one_vf(adev)) 3810 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3811 else 3812 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3813 3814 if (ring 3815 && amdgpu_sriov_is_pp_one_vf(adev) 3816 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3817 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3818 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3819 amdgpu_ring_emit_wreg(ring, reg, data); 3820 } 3821 } 3822 3823 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3824 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3825 .set_safe_mode = gfx_v12_0_set_safe_mode, 3826 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3827 .init = gfx_v12_0_rlc_init, 3828 .get_csb_size = gfx_v12_0_get_csb_size, 3829 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3830 .resume = gfx_v12_0_rlc_resume, 3831 .stop = gfx_v12_0_rlc_stop, 3832 .reset = gfx_v12_0_rlc_reset, 3833 .start = gfx_v12_0_rlc_start, 3834 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3835 }; 3836 3837 #if 0 3838 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3839 { 3840 /* TODO */ 3841 } 3842 3843 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3844 { 3845 /* TODO */ 3846 } 3847 #endif 3848 3849 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3850 enum amd_powergating_state state) 3851 { 3852 struct amdgpu_device *adev = ip_block->adev; 3853 bool enable = (state == AMD_PG_STATE_GATE); 3854 3855 if (amdgpu_sriov_vf(adev)) 3856 return 0; 3857 3858 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3859 case IP_VERSION(12, 0, 0): 3860 case IP_VERSION(12, 0, 1): 3861 amdgpu_gfx_off_ctrl(adev, enable); 3862 break; 3863 default: 3864 break; 3865 } 3866 3867 return 0; 3868 } 3869 3870 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3871 bool enable) 3872 { 3873 uint32_t def, data; 3874 3875 if (!(adev->cg_flags & 3876 (AMD_CG_SUPPORT_GFX_CGCG | 3877 AMD_CG_SUPPORT_GFX_CGLS | 3878 AMD_CG_SUPPORT_GFX_3D_CGCG | 3879 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3880 return; 3881 3882 if (enable) { 3883 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3884 3885 /* unset CGCG override */ 3886 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3887 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3888 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3889 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3890 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3891 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3892 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3893 3894 /* update CGCG override bits */ 3895 if (def != data) 3896 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3897 3898 /* enable cgcg FSM(0x0000363F) */ 3899 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3900 3901 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3902 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3903 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3904 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3905 } 3906 3907 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3908 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3909 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3910 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3911 } 3912 3913 if (def != data) 3914 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3915 3916 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3917 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3918 3919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3920 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3921 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3922 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3923 } 3924 3925 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3926 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3927 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3928 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3929 } 3930 3931 if (def != data) 3932 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3933 3934 /* set IDLE_POLL_COUNT(0x00900100) */ 3935 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3936 3937 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3938 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3939 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3940 3941 if (def != data) 3942 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3943 3944 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3945 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3946 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3947 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3948 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3949 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3950 3951 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3952 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3953 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3954 3955 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3956 if (adev->sdma.num_instances > 1) { 3957 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3958 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3959 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3960 } 3961 } else { 3962 /* Program RLC_CGCG_CGLS_CTRL */ 3963 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3964 3965 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3966 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3967 3968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3969 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3970 3971 if (def != data) 3972 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3973 3974 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3975 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3976 3977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 3978 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3979 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3980 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3981 3982 if (def != data) 3983 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3984 } 3985 } 3986 3987 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3988 bool enable) 3989 { 3990 uint32_t data, def; 3991 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 3992 return; 3993 3994 /* It is disabled by HW by default */ 3995 if (enable) { 3996 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3997 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3998 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3999 4000 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4001 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4002 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4003 4004 if (def != data) 4005 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4006 } 4007 } else { 4008 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4009 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4010 4011 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4012 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4013 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4014 4015 if (def != data) 4016 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4017 } 4018 } 4019 } 4020 4021 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4022 bool enable) 4023 { 4024 uint32_t def, data; 4025 4026 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4027 return; 4028 4029 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4030 4031 if (enable) 4032 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4033 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4034 else 4035 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4036 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4037 4038 if (def != data) 4039 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4040 } 4041 4042 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4043 bool enable) 4044 { 4045 uint32_t def, data; 4046 4047 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4048 return; 4049 4050 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4051 4052 if (enable) 4053 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4054 else 4055 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4056 4057 if (def != data) 4058 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4059 } 4060 4061 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4062 bool enable) 4063 { 4064 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4065 4066 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4067 4068 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4069 4070 gfx_v12_0_update_repeater_fgcg(adev, enable); 4071 4072 gfx_v12_0_update_sram_fgcg(adev, enable); 4073 4074 gfx_v12_0_update_perf_clk(adev, enable); 4075 4076 if (adev->cg_flags & 4077 (AMD_CG_SUPPORT_GFX_MGCG | 4078 AMD_CG_SUPPORT_GFX_CGLS | 4079 AMD_CG_SUPPORT_GFX_CGCG | 4080 AMD_CG_SUPPORT_GFX_3D_CGCG | 4081 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4082 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4083 4084 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4085 4086 return 0; 4087 } 4088 4089 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4090 enum amd_clockgating_state state) 4091 { 4092 struct amdgpu_device *adev = ip_block->adev; 4093 4094 if (amdgpu_sriov_vf(adev)) 4095 return 0; 4096 4097 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4098 case IP_VERSION(12, 0, 0): 4099 case IP_VERSION(12, 0, 1): 4100 gfx_v12_0_update_gfx_clock_gating(adev, 4101 state == AMD_CG_STATE_GATE); 4102 break; 4103 default: 4104 break; 4105 } 4106 4107 return 0; 4108 } 4109 4110 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4111 { 4112 struct amdgpu_device *adev = ip_block->adev; 4113 int data; 4114 4115 /* AMD_CG_SUPPORT_GFX_MGCG */ 4116 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4117 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4118 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4119 4120 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4121 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4122 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4123 4124 /* AMD_CG_SUPPORT_GFX_FGCG */ 4125 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4126 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4127 4128 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4129 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4130 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4131 4132 /* AMD_CG_SUPPORT_GFX_CGCG */ 4133 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4134 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4135 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4136 4137 /* AMD_CG_SUPPORT_GFX_CGLS */ 4138 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4139 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4140 4141 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4142 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4143 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4144 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4145 4146 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4147 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4148 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4149 } 4150 4151 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4152 { 4153 /* gfx12 is 32bit rptr*/ 4154 return *(uint32_t *)ring->rptr_cpu_addr; 4155 } 4156 4157 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4158 { 4159 struct amdgpu_device *adev = ring->adev; 4160 u64 wptr; 4161 4162 /* XXX check if swapping is necessary on BE */ 4163 if (ring->use_doorbell) { 4164 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4165 } else { 4166 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4167 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4168 } 4169 4170 return wptr; 4171 } 4172 4173 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4174 { 4175 struct amdgpu_device *adev = ring->adev; 4176 uint32_t *wptr_saved; 4177 uint32_t *is_queue_unmap; 4178 uint64_t aggregated_db_index; 4179 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4180 uint64_t wptr_tmp; 4181 4182 if (ring->is_mes_queue) { 4183 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4184 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4185 sizeof(uint32_t)); 4186 aggregated_db_index = 4187 amdgpu_mes_get_aggregated_doorbell_index(adev, 4188 ring->hw_prio); 4189 4190 wptr_tmp = ring->wptr & ring->buf_mask; 4191 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4192 *wptr_saved = wptr_tmp; 4193 /* assume doorbell always being used by mes mapped queue */ 4194 if (*is_queue_unmap) { 4195 WDOORBELL64(aggregated_db_index, wptr_tmp); 4196 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4197 } else { 4198 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4199 4200 if (*is_queue_unmap) 4201 WDOORBELL64(aggregated_db_index, wptr_tmp); 4202 } 4203 } else { 4204 if (ring->use_doorbell) { 4205 /* XXX check if swapping is necessary on BE */ 4206 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4207 ring->wptr); 4208 WDOORBELL64(ring->doorbell_index, ring->wptr); 4209 } else { 4210 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4211 lower_32_bits(ring->wptr)); 4212 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4213 upper_32_bits(ring->wptr)); 4214 } 4215 } 4216 } 4217 4218 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4219 { 4220 /* gfx12 hardware is 32bit rptr */ 4221 return *(uint32_t *)ring->rptr_cpu_addr; 4222 } 4223 4224 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4225 { 4226 u64 wptr; 4227 4228 /* XXX check if swapping is necessary on BE */ 4229 if (ring->use_doorbell) 4230 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4231 else 4232 BUG(); 4233 return wptr; 4234 } 4235 4236 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4237 { 4238 struct amdgpu_device *adev = ring->adev; 4239 uint32_t *wptr_saved; 4240 uint32_t *is_queue_unmap; 4241 uint64_t aggregated_db_index; 4242 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4243 uint64_t wptr_tmp; 4244 4245 if (ring->is_mes_queue) { 4246 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4247 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4248 sizeof(uint32_t)); 4249 aggregated_db_index = 4250 amdgpu_mes_get_aggregated_doorbell_index(adev, 4251 ring->hw_prio); 4252 4253 wptr_tmp = ring->wptr & ring->buf_mask; 4254 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4255 *wptr_saved = wptr_tmp; 4256 /* assume doorbell always used by mes mapped queue */ 4257 if (*is_queue_unmap) { 4258 WDOORBELL64(aggregated_db_index, wptr_tmp); 4259 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4260 } else { 4261 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4262 4263 if (*is_queue_unmap) 4264 WDOORBELL64(aggregated_db_index, wptr_tmp); 4265 } 4266 } else { 4267 /* XXX check if swapping is necessary on BE */ 4268 if (ring->use_doorbell) { 4269 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4270 ring->wptr); 4271 WDOORBELL64(ring->doorbell_index, ring->wptr); 4272 } else { 4273 BUG(); /* only DOORBELL method supported on gfx12 now */ 4274 } 4275 } 4276 } 4277 4278 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4279 { 4280 struct amdgpu_device *adev = ring->adev; 4281 u32 ref_and_mask, reg_mem_engine; 4282 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4283 4284 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4285 switch (ring->me) { 4286 case 1: 4287 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4288 break; 4289 case 2: 4290 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4291 break; 4292 default: 4293 return; 4294 } 4295 reg_mem_engine = 0; 4296 } else { 4297 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4298 reg_mem_engine = 1; /* pfp */ 4299 } 4300 4301 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4302 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4303 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4304 ref_and_mask, ref_and_mask, 0x20); 4305 } 4306 4307 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4308 struct amdgpu_job *job, 4309 struct amdgpu_ib *ib, 4310 uint32_t flags) 4311 { 4312 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4313 u32 header, control = 0; 4314 4315 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4316 4317 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4318 4319 control |= ib->length_dw | (vmid << 24); 4320 4321 if (ring->is_mes_queue) 4322 /* inherit vmid from mqd */ 4323 control |= 0x400000; 4324 4325 amdgpu_ring_write(ring, header); 4326 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4327 amdgpu_ring_write(ring, 4328 #ifdef __BIG_ENDIAN 4329 (2 << 0) | 4330 #endif 4331 lower_32_bits(ib->gpu_addr)); 4332 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4333 amdgpu_ring_write(ring, control); 4334 } 4335 4336 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4337 struct amdgpu_job *job, 4338 struct amdgpu_ib *ib, 4339 uint32_t flags) 4340 { 4341 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4342 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4343 4344 if (ring->is_mes_queue) 4345 /* inherit vmid from mqd */ 4346 control |= 0x40000000; 4347 4348 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4349 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4350 amdgpu_ring_write(ring, 4351 #ifdef __BIG_ENDIAN 4352 (2 << 0) | 4353 #endif 4354 lower_32_bits(ib->gpu_addr)); 4355 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4356 amdgpu_ring_write(ring, control); 4357 } 4358 4359 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4360 u64 seq, unsigned flags) 4361 { 4362 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4363 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4364 4365 /* RELEASE_MEM - flush caches, send int */ 4366 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4367 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4368 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4369 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4370 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4371 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4372 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4373 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4374 4375 /* 4376 * the address should be Qword aligned if 64bit write, Dword 4377 * aligned if only send 32bit data low (discard data high) 4378 */ 4379 if (write64bit) 4380 BUG_ON(addr & 0x7); 4381 else 4382 BUG_ON(addr & 0x3); 4383 amdgpu_ring_write(ring, lower_32_bits(addr)); 4384 amdgpu_ring_write(ring, upper_32_bits(addr)); 4385 amdgpu_ring_write(ring, lower_32_bits(seq)); 4386 amdgpu_ring_write(ring, upper_32_bits(seq)); 4387 amdgpu_ring_write(ring, ring->is_mes_queue ? 4388 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4389 } 4390 4391 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4392 { 4393 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4394 uint32_t seq = ring->fence_drv.sync_seq; 4395 uint64_t addr = ring->fence_drv.gpu_addr; 4396 4397 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4398 upper_32_bits(addr), seq, 0xffffffff, 4); 4399 } 4400 4401 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4402 uint16_t pasid, uint32_t flush_type, 4403 bool all_hub, uint8_t dst_sel) 4404 { 4405 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4406 amdgpu_ring_write(ring, 4407 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4408 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4409 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4410 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4411 } 4412 4413 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4414 unsigned vmid, uint64_t pd_addr) 4415 { 4416 if (ring->is_mes_queue) 4417 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4418 else 4419 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4420 4421 /* compute doesn't have PFP */ 4422 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4423 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4424 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4425 amdgpu_ring_write(ring, 0x0); 4426 } 4427 } 4428 4429 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4430 u64 seq, unsigned int flags) 4431 { 4432 struct amdgpu_device *adev = ring->adev; 4433 4434 /* we only allocate 32bit for each seq wb address */ 4435 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4436 4437 /* write fence seq to the "addr" */ 4438 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4439 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4440 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4441 amdgpu_ring_write(ring, lower_32_bits(addr)); 4442 amdgpu_ring_write(ring, upper_32_bits(addr)); 4443 amdgpu_ring_write(ring, lower_32_bits(seq)); 4444 4445 if (flags & AMDGPU_FENCE_FLAG_INT) { 4446 /* set register to trigger INT */ 4447 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4448 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4449 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4450 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4451 amdgpu_ring_write(ring, 0); 4452 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4453 } 4454 } 4455 4456 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4457 uint32_t flags) 4458 { 4459 uint32_t dw2 = 0; 4460 4461 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4462 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4463 /* set load_global_config & load_global_uconfig */ 4464 dw2 |= 0x8001; 4465 /* set load_cs_sh_regs */ 4466 dw2 |= 0x01000000; 4467 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4468 dw2 |= 0x10002; 4469 } 4470 4471 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4472 amdgpu_ring_write(ring, dw2); 4473 amdgpu_ring_write(ring, 0); 4474 } 4475 4476 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4477 uint64_t addr) 4478 { 4479 unsigned ret; 4480 4481 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4482 amdgpu_ring_write(ring, lower_32_bits(addr)); 4483 amdgpu_ring_write(ring, upper_32_bits(addr)); 4484 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4485 amdgpu_ring_write(ring, 0); 4486 ret = ring->wptr & ring->buf_mask; 4487 /* patch dummy value later */ 4488 amdgpu_ring_write(ring, 0); 4489 4490 return ret; 4491 } 4492 4493 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4494 { 4495 int i, r = 0; 4496 struct amdgpu_device *adev = ring->adev; 4497 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4498 struct amdgpu_ring *kiq_ring = &kiq->ring; 4499 unsigned long flags; 4500 4501 if (adev->enable_mes) 4502 return -EINVAL; 4503 4504 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4505 return -EINVAL; 4506 4507 spin_lock_irqsave(&kiq->ring_lock, flags); 4508 4509 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4510 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4511 return -ENOMEM; 4512 } 4513 4514 /* assert preemption condition */ 4515 amdgpu_ring_set_preempt_cond_exec(ring, false); 4516 4517 /* assert IB preemption, emit the trailing fence */ 4518 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4519 ring->trail_fence_gpu_addr, 4520 ++ring->trail_seq); 4521 amdgpu_ring_commit(kiq_ring); 4522 4523 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4524 4525 /* poll the trailing fence */ 4526 for (i = 0; i < adev->usec_timeout; i++) { 4527 if (ring->trail_seq == 4528 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4529 break; 4530 udelay(1); 4531 } 4532 4533 if (i >= adev->usec_timeout) { 4534 r = -EINVAL; 4535 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4536 } 4537 4538 /* deassert preemption condition */ 4539 amdgpu_ring_set_preempt_cond_exec(ring, true); 4540 return r; 4541 } 4542 4543 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4544 bool start, 4545 bool secure) 4546 { 4547 uint32_t v = secure ? FRAME_TMZ : 0; 4548 4549 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4550 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4551 } 4552 4553 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4554 uint32_t reg_val_offs) 4555 { 4556 struct amdgpu_device *adev = ring->adev; 4557 4558 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4559 amdgpu_ring_write(ring, 0 | /* src: register*/ 4560 (5 << 8) | /* dst: memory */ 4561 (1 << 20)); /* write confirm */ 4562 amdgpu_ring_write(ring, reg); 4563 amdgpu_ring_write(ring, 0); 4564 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4565 reg_val_offs * 4)); 4566 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4567 reg_val_offs * 4)); 4568 } 4569 4570 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4571 uint32_t reg, 4572 uint32_t val) 4573 { 4574 uint32_t cmd = 0; 4575 4576 switch (ring->funcs->type) { 4577 case AMDGPU_RING_TYPE_GFX: 4578 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4579 break; 4580 case AMDGPU_RING_TYPE_KIQ: 4581 cmd = (1 << 16); /* no inc addr */ 4582 break; 4583 default: 4584 cmd = WR_CONFIRM; 4585 break; 4586 } 4587 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4588 amdgpu_ring_write(ring, cmd); 4589 amdgpu_ring_write(ring, reg); 4590 amdgpu_ring_write(ring, 0); 4591 amdgpu_ring_write(ring, val); 4592 } 4593 4594 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4595 uint32_t val, uint32_t mask) 4596 { 4597 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4598 } 4599 4600 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4601 uint32_t reg0, uint32_t reg1, 4602 uint32_t ref, uint32_t mask) 4603 { 4604 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4605 4606 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4607 ref, mask, 0x20); 4608 } 4609 4610 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4611 unsigned vmid) 4612 { 4613 struct amdgpu_device *adev = ring->adev; 4614 uint32_t value = 0; 4615 4616 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4617 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4618 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4619 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4620 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4621 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4622 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4623 } 4624 4625 static void 4626 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4627 uint32_t me, uint32_t pipe, 4628 enum amdgpu_interrupt_state state) 4629 { 4630 uint32_t cp_int_cntl, cp_int_cntl_reg; 4631 4632 if (!me) { 4633 switch (pipe) { 4634 case 0: 4635 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4636 break; 4637 default: 4638 DRM_DEBUG("invalid pipe %d\n", pipe); 4639 return; 4640 } 4641 } else { 4642 DRM_DEBUG("invalid me %d\n", me); 4643 return; 4644 } 4645 4646 switch (state) { 4647 case AMDGPU_IRQ_STATE_DISABLE: 4648 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4649 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4650 TIME_STAMP_INT_ENABLE, 0); 4651 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4652 GENERIC0_INT_ENABLE, 0); 4653 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4654 break; 4655 case AMDGPU_IRQ_STATE_ENABLE: 4656 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4657 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4658 TIME_STAMP_INT_ENABLE, 1); 4659 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4660 GENERIC0_INT_ENABLE, 1); 4661 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4662 break; 4663 default: 4664 break; 4665 } 4666 } 4667 4668 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4669 int me, int pipe, 4670 enum amdgpu_interrupt_state state) 4671 { 4672 u32 mec_int_cntl, mec_int_cntl_reg; 4673 4674 /* 4675 * amdgpu controls only the first MEC. That's why this function only 4676 * handles the setting of interrupts for this specific MEC. All other 4677 * pipes' interrupts are set by amdkfd. 4678 */ 4679 4680 if (me == 1) { 4681 switch (pipe) { 4682 case 0: 4683 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4684 break; 4685 case 1: 4686 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4687 break; 4688 default: 4689 DRM_DEBUG("invalid pipe %d\n", pipe); 4690 return; 4691 } 4692 } else { 4693 DRM_DEBUG("invalid me %d\n", me); 4694 return; 4695 } 4696 4697 switch (state) { 4698 case AMDGPU_IRQ_STATE_DISABLE: 4699 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4700 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4701 TIME_STAMP_INT_ENABLE, 0); 4702 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4703 GENERIC0_INT_ENABLE, 0); 4704 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4705 break; 4706 case AMDGPU_IRQ_STATE_ENABLE: 4707 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4708 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4709 TIME_STAMP_INT_ENABLE, 1); 4710 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4711 GENERIC0_INT_ENABLE, 1); 4712 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4713 break; 4714 default: 4715 break; 4716 } 4717 } 4718 4719 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4720 struct amdgpu_irq_src *src, 4721 unsigned type, 4722 enum amdgpu_interrupt_state state) 4723 { 4724 switch (type) { 4725 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4726 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4727 break; 4728 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4729 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4730 break; 4731 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4732 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4733 break; 4734 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4735 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4736 break; 4737 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4738 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4739 break; 4740 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4741 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4742 break; 4743 default: 4744 break; 4745 } 4746 return 0; 4747 } 4748 4749 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4750 struct amdgpu_irq_src *source, 4751 struct amdgpu_iv_entry *entry) 4752 { 4753 int i; 4754 u8 me_id, pipe_id, queue_id; 4755 struct amdgpu_ring *ring; 4756 uint32_t mes_queue_id = entry->src_data[0]; 4757 4758 DRM_DEBUG("IH: CP EOP\n"); 4759 4760 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4761 struct amdgpu_mes_queue *queue; 4762 4763 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4764 4765 spin_lock(&adev->mes.queue_id_lock); 4766 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4767 if (queue) { 4768 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4769 amdgpu_fence_process(queue->ring); 4770 } 4771 spin_unlock(&adev->mes.queue_id_lock); 4772 } else { 4773 me_id = (entry->ring_id & 0x0c) >> 2; 4774 pipe_id = (entry->ring_id & 0x03) >> 0; 4775 queue_id = (entry->ring_id & 0x70) >> 4; 4776 4777 switch (me_id) { 4778 case 0: 4779 if (pipe_id == 0) 4780 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4781 else 4782 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4783 break; 4784 case 1: 4785 case 2: 4786 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4787 ring = &adev->gfx.compute_ring[i]; 4788 /* Per-queue interrupt is supported for MEC starting from VI. 4789 * The interrupt can only be enabled/disabled per pipe instead 4790 * of per queue. 4791 */ 4792 if ((ring->me == me_id) && 4793 (ring->pipe == pipe_id) && 4794 (ring->queue == queue_id)) 4795 amdgpu_fence_process(ring); 4796 } 4797 break; 4798 } 4799 } 4800 4801 return 0; 4802 } 4803 4804 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4805 struct amdgpu_irq_src *source, 4806 unsigned int type, 4807 enum amdgpu_interrupt_state state) 4808 { 4809 u32 cp_int_cntl_reg, cp_int_cntl; 4810 int i, j; 4811 4812 switch (state) { 4813 case AMDGPU_IRQ_STATE_DISABLE: 4814 case AMDGPU_IRQ_STATE_ENABLE: 4815 for (i = 0; i < adev->gfx.me.num_me; i++) { 4816 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4817 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4818 4819 if (cp_int_cntl_reg) { 4820 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4821 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4822 PRIV_REG_INT_ENABLE, 4823 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4824 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4825 } 4826 } 4827 } 4828 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4829 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4830 /* MECs start at 1 */ 4831 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4832 4833 if (cp_int_cntl_reg) { 4834 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4835 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4836 PRIV_REG_INT_ENABLE, 4837 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4838 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4839 } 4840 } 4841 } 4842 break; 4843 default: 4844 break; 4845 } 4846 4847 return 0; 4848 } 4849 4850 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4851 struct amdgpu_irq_src *source, 4852 unsigned type, 4853 enum amdgpu_interrupt_state state) 4854 { 4855 u32 cp_int_cntl_reg, cp_int_cntl; 4856 int i, j; 4857 4858 switch (state) { 4859 case AMDGPU_IRQ_STATE_DISABLE: 4860 case AMDGPU_IRQ_STATE_ENABLE: 4861 for (i = 0; i < adev->gfx.me.num_me; i++) { 4862 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4863 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4864 4865 if (cp_int_cntl_reg) { 4866 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4867 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4868 OPCODE_ERROR_INT_ENABLE, 4869 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4870 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4871 } 4872 } 4873 } 4874 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4875 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4876 /* MECs start at 1 */ 4877 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4878 4879 if (cp_int_cntl_reg) { 4880 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4881 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4882 OPCODE_ERROR_INT_ENABLE, 4883 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4884 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4885 } 4886 } 4887 } 4888 break; 4889 default: 4890 break; 4891 } 4892 return 0; 4893 } 4894 4895 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4896 struct amdgpu_irq_src *source, 4897 unsigned int type, 4898 enum amdgpu_interrupt_state state) 4899 { 4900 u32 cp_int_cntl_reg, cp_int_cntl; 4901 int i, j; 4902 4903 switch (state) { 4904 case AMDGPU_IRQ_STATE_DISABLE: 4905 case AMDGPU_IRQ_STATE_ENABLE: 4906 for (i = 0; i < adev->gfx.me.num_me; i++) { 4907 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4908 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4909 4910 if (cp_int_cntl_reg) { 4911 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4912 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4913 PRIV_INSTR_INT_ENABLE, 4914 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4915 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4916 } 4917 } 4918 } 4919 break; 4920 default: 4921 break; 4922 } 4923 4924 return 0; 4925 } 4926 4927 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4928 struct amdgpu_iv_entry *entry) 4929 { 4930 u8 me_id, pipe_id, queue_id; 4931 struct amdgpu_ring *ring; 4932 int i; 4933 4934 me_id = (entry->ring_id & 0x0c) >> 2; 4935 pipe_id = (entry->ring_id & 0x03) >> 0; 4936 queue_id = (entry->ring_id & 0x70) >> 4; 4937 4938 switch (me_id) { 4939 case 0: 4940 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4941 ring = &adev->gfx.gfx_ring[i]; 4942 if (ring->me == me_id && ring->pipe == pipe_id && 4943 ring->queue == queue_id) 4944 drm_sched_fault(&ring->sched); 4945 } 4946 break; 4947 case 1: 4948 case 2: 4949 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4950 ring = &adev->gfx.compute_ring[i]; 4951 if (ring->me == me_id && ring->pipe == pipe_id && 4952 ring->queue == queue_id) 4953 drm_sched_fault(&ring->sched); 4954 } 4955 break; 4956 default: 4957 BUG(); 4958 break; 4959 } 4960 } 4961 4962 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 4963 struct amdgpu_irq_src *source, 4964 struct amdgpu_iv_entry *entry) 4965 { 4966 DRM_ERROR("Illegal register access in command stream\n"); 4967 gfx_v12_0_handle_priv_fault(adev, entry); 4968 return 0; 4969 } 4970 4971 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 4972 struct amdgpu_irq_src *source, 4973 struct amdgpu_iv_entry *entry) 4974 { 4975 DRM_ERROR("Illegal opcode in command stream \n"); 4976 gfx_v12_0_handle_priv_fault(adev, entry); 4977 return 0; 4978 } 4979 4980 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 4981 struct amdgpu_irq_src *source, 4982 struct amdgpu_iv_entry *entry) 4983 { 4984 DRM_ERROR("Illegal instruction in command stream\n"); 4985 gfx_v12_0_handle_priv_fault(adev, entry); 4986 return 0; 4987 } 4988 4989 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 4990 { 4991 const unsigned int gcr_cntl = 4992 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 4993 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 4994 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 4995 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 4996 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 4997 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 4998 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 4999 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5000 5001 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5002 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5003 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5004 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5005 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5006 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5007 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5008 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5009 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5010 } 5011 5012 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5013 { 5014 /* Header itself is a NOP packet */ 5015 if (num_nop == 1) { 5016 amdgpu_ring_write(ring, ring->funcs->nop); 5017 return; 5018 } 5019 5020 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5021 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5022 5023 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5024 amdgpu_ring_insert_nop(ring, num_nop - 1); 5025 } 5026 5027 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5028 { 5029 /* Emit the cleaner shader */ 5030 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5031 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5032 } 5033 5034 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5035 { 5036 struct amdgpu_device *adev = ip_block->adev; 5037 uint32_t i, j, k, reg, index = 0; 5038 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5039 5040 if (!adev->gfx.ip_dump_core) 5041 return; 5042 5043 for (i = 0; i < reg_count; i++) 5044 drm_printf(p, "%-50s \t 0x%08x\n", 5045 gc_reg_list_12_0[i].reg_name, 5046 adev->gfx.ip_dump_core[i]); 5047 5048 /* print compute queue registers for all instances */ 5049 if (!adev->gfx.ip_dump_compute_queues) 5050 return; 5051 5052 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5053 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5054 adev->gfx.mec.num_mec, 5055 adev->gfx.mec.num_pipe_per_mec, 5056 adev->gfx.mec.num_queue_per_pipe); 5057 5058 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5059 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5060 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5061 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5062 for (reg = 0; reg < reg_count; reg++) { 5063 drm_printf(p, "%-50s \t 0x%08x\n", 5064 gc_cp_reg_list_12[reg].reg_name, 5065 adev->gfx.ip_dump_compute_queues[index + reg]); 5066 } 5067 index += reg_count; 5068 } 5069 } 5070 } 5071 5072 /* print gfx queue registers for all instances */ 5073 if (!adev->gfx.ip_dump_gfx_queues) 5074 return; 5075 5076 index = 0; 5077 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5078 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5079 adev->gfx.me.num_me, 5080 adev->gfx.me.num_pipe_per_me, 5081 adev->gfx.me.num_queue_per_pipe); 5082 5083 for (i = 0; i < adev->gfx.me.num_me; i++) { 5084 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5085 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5086 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5087 for (reg = 0; reg < reg_count; reg++) { 5088 drm_printf(p, "%-50s \t 0x%08x\n", 5089 gc_gfx_queue_reg_list_12[reg].reg_name, 5090 adev->gfx.ip_dump_gfx_queues[index + reg]); 5091 } 5092 index += reg_count; 5093 } 5094 } 5095 } 5096 } 5097 5098 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5099 { 5100 struct amdgpu_device *adev = ip_block->adev; 5101 uint32_t i, j, k, reg, index = 0; 5102 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5103 5104 if (!adev->gfx.ip_dump_core) 5105 return; 5106 5107 amdgpu_gfx_off_ctrl(adev, false); 5108 for (i = 0; i < reg_count; i++) 5109 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5110 amdgpu_gfx_off_ctrl(adev, true); 5111 5112 /* dump compute queue registers for all instances */ 5113 if (!adev->gfx.ip_dump_compute_queues) 5114 return; 5115 5116 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5117 amdgpu_gfx_off_ctrl(adev, false); 5118 mutex_lock(&adev->srbm_mutex); 5119 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5120 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5121 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5122 /* ME0 is for GFX so start from 1 for CP */ 5123 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5124 for (reg = 0; reg < reg_count; reg++) { 5125 adev->gfx.ip_dump_compute_queues[index + reg] = 5126 RREG32(SOC15_REG_ENTRY_OFFSET( 5127 gc_cp_reg_list_12[reg])); 5128 } 5129 index += reg_count; 5130 } 5131 } 5132 } 5133 soc24_grbm_select(adev, 0, 0, 0, 0); 5134 mutex_unlock(&adev->srbm_mutex); 5135 amdgpu_gfx_off_ctrl(adev, true); 5136 5137 /* dump gfx queue registers for all instances */ 5138 if (!adev->gfx.ip_dump_gfx_queues) 5139 return; 5140 5141 index = 0; 5142 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5143 amdgpu_gfx_off_ctrl(adev, false); 5144 mutex_lock(&adev->srbm_mutex); 5145 for (i = 0; i < adev->gfx.me.num_me; i++) { 5146 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5147 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5148 soc24_grbm_select(adev, i, j, k, 0); 5149 5150 for (reg = 0; reg < reg_count; reg++) { 5151 adev->gfx.ip_dump_gfx_queues[index + reg] = 5152 RREG32(SOC15_REG_ENTRY_OFFSET( 5153 gc_gfx_queue_reg_list_12[reg])); 5154 } 5155 index += reg_count; 5156 } 5157 } 5158 } 5159 soc24_grbm_select(adev, 0, 0, 0, 0); 5160 mutex_unlock(&adev->srbm_mutex); 5161 amdgpu_gfx_off_ctrl(adev, true); 5162 } 5163 5164 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5165 { 5166 /* Disable the pipe reset until the CPFW fully support it.*/ 5167 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5168 return false; 5169 } 5170 5171 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5172 { 5173 struct amdgpu_device *adev = ring->adev; 5174 uint32_t reset_pipe = 0, clean_pipe = 0; 5175 int r; 5176 5177 if (!gfx_v12_pipe_reset_support(adev)) 5178 return -EOPNOTSUPP; 5179 5180 gfx_v12_0_set_safe_mode(adev, 0); 5181 mutex_lock(&adev->srbm_mutex); 5182 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5183 5184 switch (ring->pipe) { 5185 case 0: 5186 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5187 PFP_PIPE0_RESET, 1); 5188 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5189 ME_PIPE0_RESET, 1); 5190 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5191 PFP_PIPE0_RESET, 0); 5192 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5193 ME_PIPE0_RESET, 0); 5194 break; 5195 case 1: 5196 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5197 PFP_PIPE1_RESET, 1); 5198 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5199 ME_PIPE1_RESET, 1); 5200 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5201 PFP_PIPE1_RESET, 0); 5202 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5203 ME_PIPE1_RESET, 0); 5204 break; 5205 default: 5206 break; 5207 } 5208 5209 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5210 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5211 5212 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5213 RS64_FW_UC_START_ADDR_LO; 5214 soc24_grbm_select(adev, 0, 0, 0, 0); 5215 mutex_unlock(&adev->srbm_mutex); 5216 gfx_v12_0_unset_safe_mode(adev, 0); 5217 5218 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5219 r == 0 ? "successfully" : "failed"); 5220 /* Sometimes the ME start pc counter can't cache correctly, so the 5221 * PC check only as a reference and pipe reset result rely on the 5222 * later ring test. 5223 */ 5224 return 0; 5225 } 5226 5227 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5228 { 5229 struct amdgpu_device *adev = ring->adev; 5230 int r; 5231 5232 if (amdgpu_sriov_vf(adev)) 5233 return -EINVAL; 5234 5235 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5236 if (r) { 5237 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5238 r = gfx_v12_reset_gfx_pipe(ring); 5239 if (r) 5240 return r; 5241 } 5242 5243 r = gfx_v12_0_kgq_init_queue(ring, true); 5244 if (r) { 5245 dev_err(adev->dev, "failed to init kgq\n"); 5246 return r; 5247 } 5248 5249 r = amdgpu_mes_map_legacy_queue(adev, ring); 5250 if (r) { 5251 dev_err(adev->dev, "failed to remap kgq\n"); 5252 return r; 5253 } 5254 5255 return amdgpu_ring_test_ring(ring); 5256 } 5257 5258 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5259 { 5260 struct amdgpu_device *adev = ring->adev; 5261 int r; 5262 5263 if (amdgpu_sriov_vf(adev)) 5264 return -EINVAL; 5265 5266 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5267 if (r) { 5268 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5269 return r; 5270 } 5271 5272 r = gfx_v12_0_kcq_init_queue(ring, true); 5273 if (r) { 5274 dev_err(adev->dev, "failed to init kcq\n"); 5275 return r; 5276 } 5277 r = amdgpu_mes_map_legacy_queue(adev, ring); 5278 if (r) { 5279 dev_err(adev->dev, "failed to remap kcq\n"); 5280 return r; 5281 } 5282 5283 return amdgpu_ring_test_ring(ring); 5284 } 5285 5286 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5287 { 5288 amdgpu_gfx_profile_ring_begin_use(ring); 5289 5290 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5291 } 5292 5293 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5294 { 5295 amdgpu_gfx_profile_ring_end_use(ring); 5296 5297 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5298 } 5299 5300 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5301 .name = "gfx_v12_0", 5302 .early_init = gfx_v12_0_early_init, 5303 .late_init = gfx_v12_0_late_init, 5304 .sw_init = gfx_v12_0_sw_init, 5305 .sw_fini = gfx_v12_0_sw_fini, 5306 .hw_init = gfx_v12_0_hw_init, 5307 .hw_fini = gfx_v12_0_hw_fini, 5308 .suspend = gfx_v12_0_suspend, 5309 .resume = gfx_v12_0_resume, 5310 .is_idle = gfx_v12_0_is_idle, 5311 .wait_for_idle = gfx_v12_0_wait_for_idle, 5312 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5313 .set_powergating_state = gfx_v12_0_set_powergating_state, 5314 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5315 .dump_ip_state = gfx_v12_ip_dump, 5316 .print_ip_state = gfx_v12_ip_print, 5317 }; 5318 5319 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5320 .type = AMDGPU_RING_TYPE_GFX, 5321 .align_mask = 0xff, 5322 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5323 .support_64bit_ptrs = true, 5324 .secure_submission_supported = true, 5325 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5326 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5327 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5328 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5329 5 + /* COND_EXEC */ 5330 7 + /* PIPELINE_SYNC */ 5331 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5332 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5333 2 + /* VM_FLUSH */ 5334 8 + /* FENCE for VM_FLUSH */ 5335 5 + /* COND_EXEC */ 5336 7 + /* HDP_flush */ 5337 4 + /* VGT_flush */ 5338 31 + /* DE_META */ 5339 3 + /* CNTX_CTRL */ 5340 5 + /* HDP_INVL */ 5341 8 + 8 + /* FENCE x2 */ 5342 8 + /* gfx_v12_0_emit_mem_sync */ 5343 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5344 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5345 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5346 .emit_fence = gfx_v12_0_ring_emit_fence, 5347 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5348 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5349 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5350 .test_ring = gfx_v12_0_ring_test_ring, 5351 .test_ib = gfx_v12_0_ring_test_ib, 5352 .insert_nop = gfx_v12_ring_insert_nop, 5353 .pad_ib = amdgpu_ring_generic_pad_ib, 5354 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5355 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5356 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5357 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5358 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5359 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5360 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5361 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5362 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5363 .reset = gfx_v12_0_reset_kgq, 5364 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5365 .begin_use = gfx_v12_0_ring_begin_use, 5366 .end_use = gfx_v12_0_ring_end_use, 5367 }; 5368 5369 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5370 .type = AMDGPU_RING_TYPE_COMPUTE, 5371 .align_mask = 0xff, 5372 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5373 .support_64bit_ptrs = true, 5374 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5375 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5376 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5377 .emit_frame_size = 5378 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5379 5 + /* hdp invalidate */ 5380 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5381 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5382 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5383 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5384 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5385 8 + /* gfx_v12_0_emit_mem_sync */ 5386 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5387 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5388 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5389 .emit_fence = gfx_v12_0_ring_emit_fence, 5390 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5391 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5392 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5393 .test_ring = gfx_v12_0_ring_test_ring, 5394 .test_ib = gfx_v12_0_ring_test_ib, 5395 .insert_nop = gfx_v12_ring_insert_nop, 5396 .pad_ib = amdgpu_ring_generic_pad_ib, 5397 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5398 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5399 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5400 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5401 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5402 .reset = gfx_v12_0_reset_kcq, 5403 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5404 .begin_use = gfx_v12_0_ring_begin_use, 5405 .end_use = gfx_v12_0_ring_end_use, 5406 }; 5407 5408 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5409 .type = AMDGPU_RING_TYPE_KIQ, 5410 .align_mask = 0xff, 5411 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5412 .support_64bit_ptrs = true, 5413 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5414 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5415 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5416 .emit_frame_size = 5417 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5418 5 + /*hdp invalidate */ 5419 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5420 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5421 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5422 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5423 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5424 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5425 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5426 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5427 .test_ring = gfx_v12_0_ring_test_ring, 5428 .test_ib = gfx_v12_0_ring_test_ib, 5429 .insert_nop = amdgpu_ring_insert_nop, 5430 .pad_ib = amdgpu_ring_generic_pad_ib, 5431 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5432 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5433 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5434 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5435 }; 5436 5437 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5438 { 5439 int i; 5440 5441 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5442 5443 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5444 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5445 5446 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5447 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5448 } 5449 5450 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5451 .set = gfx_v12_0_set_eop_interrupt_state, 5452 .process = gfx_v12_0_eop_irq, 5453 }; 5454 5455 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5456 .set = gfx_v12_0_set_priv_reg_fault_state, 5457 .process = gfx_v12_0_priv_reg_irq, 5458 }; 5459 5460 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5461 .set = gfx_v12_0_set_bad_op_fault_state, 5462 .process = gfx_v12_0_bad_op_irq, 5463 }; 5464 5465 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5466 .set = gfx_v12_0_set_priv_inst_fault_state, 5467 .process = gfx_v12_0_priv_inst_irq, 5468 }; 5469 5470 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5471 { 5472 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5473 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5474 5475 adev->gfx.priv_reg_irq.num_types = 1; 5476 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5477 5478 adev->gfx.bad_op_irq.num_types = 1; 5479 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5480 5481 adev->gfx.priv_inst_irq.num_types = 1; 5482 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5483 } 5484 5485 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5486 { 5487 if (adev->flags & AMD_IS_APU) 5488 adev->gfx.imu.mode = MISSION_MODE; 5489 else 5490 adev->gfx.imu.mode = DEBUG_MODE; 5491 5492 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5493 } 5494 5495 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5496 { 5497 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5498 } 5499 5500 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5501 { 5502 /* set gfx eng mqd */ 5503 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5504 sizeof(struct v12_gfx_mqd); 5505 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5506 gfx_v12_0_gfx_mqd_init; 5507 /* set compute eng mqd */ 5508 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5509 sizeof(struct v12_compute_mqd); 5510 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5511 gfx_v12_0_compute_mqd_init; 5512 } 5513 5514 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5515 u32 bitmap) 5516 { 5517 u32 data; 5518 5519 if (!bitmap) 5520 return; 5521 5522 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5523 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5524 5525 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5526 } 5527 5528 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5529 { 5530 u32 data, wgp_bitmask; 5531 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5532 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5533 5534 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5535 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5536 5537 wgp_bitmask = 5538 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5539 5540 return (~data) & wgp_bitmask; 5541 } 5542 5543 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5544 { 5545 u32 wgp_idx, wgp_active_bitmap; 5546 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5547 5548 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5549 cu_active_bitmap = 0; 5550 5551 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5552 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5553 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5554 if (wgp_active_bitmap & (1 << wgp_idx)) 5555 cu_active_bitmap |= cu_bitmap_per_wgp; 5556 } 5557 5558 return cu_active_bitmap; 5559 } 5560 5561 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5562 struct amdgpu_cu_info *cu_info) 5563 { 5564 int i, j, k, counter, active_cu_number = 0; 5565 u32 mask, bitmap; 5566 unsigned disable_masks[8 * 2]; 5567 5568 if (!adev || !cu_info) 5569 return -EINVAL; 5570 5571 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5572 5573 mutex_lock(&adev->grbm_idx_mutex); 5574 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5575 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5576 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5577 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5578 continue; 5579 mask = 1; 5580 counter = 0; 5581 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5582 if (i < 8 && j < 2) 5583 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5584 adev, disable_masks[i * 2 + j]); 5585 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5586 5587 /** 5588 * GFX12 could support more than 4 SEs, while the bitmap 5589 * in cu_info struct is 4x4 and ioctl interface struct 5590 * drm_amdgpu_info_device should keep stable. 5591 * So we use last two columns of bitmap to store cu mask for 5592 * SEs 4 to 7, the layout of the bitmap is as below: 5593 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5594 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5595 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5596 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5597 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5598 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5599 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5600 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5601 */ 5602 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5603 5604 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5605 if (bitmap & mask) 5606 counter++; 5607 5608 mask <<= 1; 5609 } 5610 active_cu_number += counter; 5611 } 5612 } 5613 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5614 mutex_unlock(&adev->grbm_idx_mutex); 5615 5616 cu_info->number = active_cu_number; 5617 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5618 5619 return 0; 5620 } 5621 5622 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5623 .type = AMD_IP_BLOCK_TYPE_GFX, 5624 .major = 12, 5625 .minor = 0, 5626 .rev = 0, 5627 .funcs = &gfx_v12_0_ip_funcs, 5628 }; 5629