1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_0.h" 47 #include "nbif_v6_3_1.h" 48 #include "mes_v12_0.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 65 66 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 97 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 101 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 102 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 104 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 105 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 109 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 120 121 /* cp header registers */ 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 126 /* SE status registers */ 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 128 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 130 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 131 }; 132 133 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 134 /* compute registers */ 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 174 }; 175 176 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 177 /* gfx queue registers */ 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 203 }; 204 205 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 206 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 209 }; 210 211 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 212 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 213 }; 214 215 #define DEFAULT_SH_MEM_CONFIG \ 216 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 217 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 218 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 219 220 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 221 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 222 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 223 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 224 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 225 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 226 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 227 struct amdgpu_cu_info *cu_info); 228 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 229 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 230 u32 sh_num, u32 instance, int xcc_id); 231 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 232 233 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 234 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 235 uint32_t val); 236 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 237 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 238 uint16_t pasid, uint32_t flush_type, 239 bool all_hub, uint8_t dst_sel); 240 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 241 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 242 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 243 bool enable); 244 245 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 246 uint64_t queue_mask) 247 { 248 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 249 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 250 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 251 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 252 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 253 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 254 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 255 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 256 amdgpu_ring_write(kiq_ring, 0); 257 } 258 259 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 260 struct amdgpu_ring *ring) 261 { 262 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 263 uint64_t wptr_addr = ring->wptr_gpu_addr; 264 uint32_t me = 0, eng_sel = 0; 265 266 switch (ring->funcs->type) { 267 case AMDGPU_RING_TYPE_COMPUTE: 268 me = 1; 269 eng_sel = 0; 270 break; 271 case AMDGPU_RING_TYPE_GFX: 272 me = 0; 273 eng_sel = 4; 274 break; 275 case AMDGPU_RING_TYPE_MES: 276 me = 2; 277 eng_sel = 5; 278 break; 279 default: 280 WARN_ON(1); 281 } 282 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 284 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 285 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 286 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 287 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 288 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 289 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 290 PACKET3_MAP_QUEUES_ME((me)) | 291 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 292 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 293 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 294 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 295 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 296 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 297 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 298 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 299 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 300 } 301 302 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 303 struct amdgpu_ring *ring, 304 enum amdgpu_unmap_queues_action action, 305 u64 gpu_addr, u64 seq) 306 { 307 struct amdgpu_device *adev = kiq_ring->adev; 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 311 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 312 return; 313 } 314 315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 316 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 317 PACKET3_UNMAP_QUEUES_ACTION(action) | 318 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 319 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 320 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 321 amdgpu_ring_write(kiq_ring, 322 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 323 324 if (action == PREEMPT_QUEUES_NO_UNMAP) { 325 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 326 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 327 amdgpu_ring_write(kiq_ring, seq); 328 } else { 329 amdgpu_ring_write(kiq_ring, 0); 330 amdgpu_ring_write(kiq_ring, 0); 331 amdgpu_ring_write(kiq_ring, 0); 332 } 333 } 334 335 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 336 struct amdgpu_ring *ring, 337 u64 addr, u64 seq) 338 { 339 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 340 341 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 342 amdgpu_ring_write(kiq_ring, 343 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 344 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 345 PACKET3_QUERY_STATUS_COMMAND(2)); 346 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 347 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 348 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 349 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 350 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 351 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 352 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 353 } 354 355 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 356 uint16_t pasid, 357 uint32_t flush_type, 358 bool all_hub) 359 { 360 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 361 } 362 363 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 364 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 365 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 366 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 367 .kiq_query_status = gfx_v12_0_kiq_query_status, 368 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 369 .set_resources_size = 8, 370 .map_queues_size = 7, 371 .unmap_queues_size = 6, 372 .query_status_size = 7, 373 .invalidate_tlbs_size = 2, 374 }; 375 376 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 377 { 378 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 379 } 380 381 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 382 int mem_space, int opt, uint32_t addr0, 383 uint32_t addr1, uint32_t ref, 384 uint32_t mask, uint32_t inv) 385 { 386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 387 amdgpu_ring_write(ring, 388 /* memory (1) or register (0) */ 389 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 390 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 391 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 392 WAIT_REG_MEM_ENGINE(eng_sel))); 393 394 if (mem_space) 395 BUG_ON(addr0 & 0x3); /* Dword align */ 396 amdgpu_ring_write(ring, addr0); 397 amdgpu_ring_write(ring, addr1); 398 amdgpu_ring_write(ring, ref); 399 amdgpu_ring_write(ring, mask); 400 amdgpu_ring_write(ring, inv); /* poll interval */ 401 } 402 403 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 407 uint32_t tmp = 0; 408 unsigned i; 409 int r; 410 411 WREG32(scratch, 0xCAFEDEAD); 412 r = amdgpu_ring_alloc(ring, 5); 413 if (r) { 414 dev_err(adev->dev, 415 "amdgpu: cp failed to lock ring %d (%d).\n", 416 ring->idx, r); 417 return r; 418 } 419 420 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 421 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 422 } else { 423 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 424 amdgpu_ring_write(ring, scratch - 425 PACKET3_SET_UCONFIG_REG_START); 426 amdgpu_ring_write(ring, 0xDEADBEEF); 427 } 428 amdgpu_ring_commit(ring); 429 430 for (i = 0; i < adev->usec_timeout; i++) { 431 tmp = RREG32(scratch); 432 if (tmp == 0xDEADBEEF) 433 break; 434 if (amdgpu_emu_mode == 1) 435 msleep(1); 436 else 437 udelay(1); 438 } 439 440 if (i >= adev->usec_timeout) 441 r = -ETIMEDOUT; 442 return r; 443 } 444 445 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 struct amdgpu_ib ib; 449 struct dma_fence *f = NULL; 450 unsigned index; 451 uint64_t gpu_addr; 452 volatile uint32_t *cpu_ptr; 453 long r; 454 455 /* MES KIQ fw hasn't indirect buffer support for now */ 456 if (adev->enable_mes_kiq && 457 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 458 return 0; 459 460 memset(&ib, 0, sizeof(ib)); 461 462 if (ring->is_mes_queue) { 463 uint32_t padding, offset; 464 465 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 466 padding = amdgpu_mes_ctx_get_offs(ring, 467 AMDGPU_MES_CTX_PADDING_OFFS); 468 469 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 470 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 471 472 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 473 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 474 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 475 } else { 476 r = amdgpu_device_wb_get(adev, &index); 477 if (r) 478 return r; 479 480 gpu_addr = adev->wb.gpu_addr + (index * 4); 481 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 482 cpu_ptr = &adev->wb.wb[index]; 483 484 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 485 if (r) { 486 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 487 goto err1; 488 } 489 } 490 491 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 493 ib.ptr[2] = lower_32_bits(gpu_addr); 494 ib.ptr[3] = upper_32_bits(gpu_addr); 495 ib.ptr[4] = 0xDEADBEEF; 496 ib.length_dw = 5; 497 498 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 499 if (r) 500 goto err2; 501 502 r = dma_fence_wait_timeout(f, false, timeout); 503 if (r == 0) { 504 r = -ETIMEDOUT; 505 goto err2; 506 } else if (r < 0) { 507 goto err2; 508 } 509 510 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 511 r = 0; 512 else 513 r = -EINVAL; 514 err2: 515 if (!ring->is_mes_queue) 516 amdgpu_ib_free(&ib, NULL); 517 dma_fence_put(f); 518 err1: 519 if (!ring->is_mes_queue) 520 amdgpu_device_wb_free(adev, index); 521 return r; 522 } 523 524 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 525 { 526 amdgpu_ucode_release(&adev->gfx.pfp_fw); 527 amdgpu_ucode_release(&adev->gfx.me_fw); 528 amdgpu_ucode_release(&adev->gfx.rlc_fw); 529 amdgpu_ucode_release(&adev->gfx.mec_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 535 { 536 const struct psp_firmware_header_v1_0 *toc_hdr; 537 int err = 0; 538 539 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 540 AMDGPU_UCODE_REQUIRED, 541 "amdgpu/%s_toc.bin", ucode_prefix); 542 if (err) 543 goto out; 544 545 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 546 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 547 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 548 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 549 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 550 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 551 return 0; 552 out: 553 amdgpu_ucode_release(&adev->psp.toc_fw); 554 return err; 555 } 556 557 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 558 { 559 char ucode_prefix[15]; 560 int err; 561 const struct rlc_firmware_header_v2_0 *rlc_hdr; 562 uint16_t version_major; 563 uint16_t version_minor; 564 565 DRM_DEBUG("\n"); 566 567 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 568 569 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_pfp.bin", ucode_prefix); 572 if (err) 573 goto out; 574 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 576 577 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 578 AMDGPU_UCODE_REQUIRED, 579 "amdgpu/%s_me.bin", ucode_prefix); 580 if (err) 581 goto out; 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 583 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 584 585 if (!amdgpu_sriov_vf(adev)) { 586 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 587 AMDGPU_UCODE_REQUIRED, 588 "amdgpu/%s_rlc.bin", ucode_prefix); 589 if (err) 590 goto out; 591 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 592 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 593 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 594 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 595 if (err) 596 goto out; 597 } 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_mec.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 607 608 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 609 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 610 611 /* only one MEC for gfx 12 */ 612 adev->gfx.mec2_fw = NULL; 613 614 if (adev->gfx.imu.funcs) { 615 if (adev->gfx.imu.funcs->init_microcode) { 616 err = adev->gfx.imu.funcs->init_microcode(adev); 617 if (err) 618 dev_err(adev->dev, "Failed to load imu firmware!\n"); 619 } 620 } 621 622 out: 623 if (err) { 624 amdgpu_ucode_release(&adev->gfx.pfp_fw); 625 amdgpu_ucode_release(&adev->gfx.me_fw); 626 amdgpu_ucode_release(&adev->gfx.rlc_fw); 627 amdgpu_ucode_release(&adev->gfx.mec_fw); 628 } 629 630 return err; 631 } 632 633 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 634 { 635 u32 count = 0; 636 const struct cs_section_def *sect = NULL; 637 const struct cs_extent_def *ext = NULL; 638 639 count += 1; 640 641 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 642 if (sect->id == SECT_CONTEXT) { 643 for (ext = sect->section; ext->extent != NULL; ++ext) 644 count += 2 + ext->reg_count; 645 } else 646 return 0; 647 } 648 649 return count; 650 } 651 652 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 653 volatile u32 *buffer) 654 { 655 u32 count = 0, clustercount = 0, i; 656 const struct cs_section_def *sect = NULL; 657 const struct cs_extent_def *ext = NULL; 658 659 if (adev->gfx.rlc.cs_data == NULL) 660 return; 661 if (buffer == NULL) 662 return; 663 664 count += 1; 665 666 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 667 if (sect->id == SECT_CONTEXT) { 668 for (ext = sect->section; ext->extent != NULL; ++ext) { 669 clustercount++; 670 buffer[count++] = ext->reg_count; 671 buffer[count++] = ext->reg_index; 672 673 for (i = 0; i < ext->reg_count; i++) 674 buffer[count++] = cpu_to_le32(ext->extent[i]); 675 } 676 } else 677 return; 678 } 679 680 buffer[0] = clustercount; 681 } 682 683 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 684 { 685 /* clear state block */ 686 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 687 &adev->gfx.rlc.clear_state_gpu_addr, 688 (void **)&adev->gfx.rlc.cs_ptr); 689 690 /* jump table block */ 691 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 692 &adev->gfx.rlc.cp_table_gpu_addr, 693 (void **)&adev->gfx.rlc.cp_table_ptr); 694 } 695 696 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 697 { 698 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 699 700 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 701 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 702 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 703 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 704 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 705 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 706 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 707 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 708 adev->gfx.rlc.rlcg_reg_access_supported = true; 709 } 710 711 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 712 { 713 const struct cs_section_def *cs_data; 714 int r; 715 716 adev->gfx.rlc.cs_data = gfx12_cs_data; 717 718 cs_data = adev->gfx.rlc.cs_data; 719 720 if (cs_data) { 721 /* init clear state block */ 722 r = amdgpu_gfx_rlc_init_csb(adev); 723 if (r) 724 return r; 725 } 726 727 /* init spm vmid with 0xf */ 728 if (adev->gfx.rlc.funcs->update_spm_vmid) 729 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 730 731 return 0; 732 } 733 734 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 735 { 736 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 737 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 738 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 739 } 740 741 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 742 { 743 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 744 745 amdgpu_gfx_graphics_queue_acquire(adev); 746 } 747 748 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 749 { 750 int r; 751 u32 *hpd; 752 size_t mec_hpd_size; 753 754 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 755 756 /* take ownership of the relevant compute queues */ 757 amdgpu_gfx_compute_queue_acquire(adev); 758 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 759 760 if (mec_hpd_size) { 761 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 762 AMDGPU_GEM_DOMAIN_GTT, 763 &adev->gfx.mec.hpd_eop_obj, 764 &adev->gfx.mec.hpd_eop_gpu_addr, 765 (void **)&hpd); 766 if (r) { 767 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 768 gfx_v12_0_mec_fini(adev); 769 return r; 770 } 771 772 memset(hpd, 0, mec_hpd_size); 773 774 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 775 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 776 } 777 778 return 0; 779 } 780 781 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 782 { 783 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 784 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 785 (address << SQ_IND_INDEX__INDEX__SHIFT)); 786 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 787 } 788 789 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 790 uint32_t thread, uint32_t regno, 791 uint32_t num, uint32_t *out) 792 { 793 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 794 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 795 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 796 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 797 (SQ_IND_INDEX__AUTO_INCR_MASK)); 798 while (num--) 799 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 800 } 801 802 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 803 uint32_t xcc_id, 804 uint32_t simd, uint32_t wave, 805 uint32_t *dst, int *no_fields) 806 { 807 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 808 * field when performing a select_se_sh so it should be 809 * zero here */ 810 WARN_ON(simd != 0); 811 812 /* type 4 wave data */ 813 dst[(*no_fields)++] = 4; 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 837 } 838 839 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 840 uint32_t xcc_id, uint32_t simd, 841 uint32_t wave, uint32_t start, 842 uint32_t size, uint32_t *dst) 843 { 844 WARN_ON(simd != 0); 845 846 wave_read_regs( 847 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 848 dst); 849 } 850 851 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 852 uint32_t xcc_id, uint32_t simd, 853 uint32_t wave, uint32_t thread, 854 uint32_t start, uint32_t size, 855 uint32_t *dst) 856 { 857 wave_read_regs( 858 adev, wave, thread, 859 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 860 } 861 862 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 863 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 864 { 865 soc24_grbm_select(adev, me, pipe, q, vm); 866 } 867 868 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 869 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 870 .select_se_sh = &gfx_v12_0_select_se_sh, 871 .read_wave_data = &gfx_v12_0_read_wave_data, 872 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 873 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 874 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 875 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 876 }; 877 878 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 879 { 880 881 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 882 case IP_VERSION(12, 0, 0): 883 case IP_VERSION(12, 0, 1): 884 adev->gfx.config.max_hw_contexts = 8; 885 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 886 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 887 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 888 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 889 break; 890 default: 891 BUG(); 892 break; 893 } 894 895 return 0; 896 } 897 898 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 899 int me, int pipe, int queue) 900 { 901 int r; 902 struct amdgpu_ring *ring; 903 unsigned int irq_type; 904 905 ring = &adev->gfx.gfx_ring[ring_id]; 906 907 ring->me = me; 908 ring->pipe = pipe; 909 ring->queue = queue; 910 911 ring->ring_obj = NULL; 912 ring->use_doorbell = true; 913 914 if (!ring_id) 915 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 916 else 917 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 918 ring->vm_hub = AMDGPU_GFXHUB(0); 919 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 920 921 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 922 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 923 AMDGPU_RING_PRIO_DEFAULT, NULL); 924 if (r) 925 return r; 926 return 0; 927 } 928 929 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 930 int mec, int pipe, int queue) 931 { 932 int r; 933 unsigned irq_type; 934 struct amdgpu_ring *ring; 935 unsigned int hw_prio; 936 937 ring = &adev->gfx.compute_ring[ring_id]; 938 939 /* mec0 is me1 */ 940 ring->me = mec + 1; 941 ring->pipe = pipe; 942 ring->queue = queue; 943 944 ring->ring_obj = NULL; 945 ring->use_doorbell = true; 946 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 947 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 948 + (ring_id * GFX12_MEC_HPD_SIZE); 949 ring->vm_hub = AMDGPU_GFXHUB(0); 950 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 951 952 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 953 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 954 + ring->pipe; 955 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 956 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 957 /* type-2 packets are deprecated on MEC, use type-3 instead */ 958 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 959 hw_prio, NULL); 960 if (r) 961 return r; 962 963 return 0; 964 } 965 966 static struct { 967 SOC24_FIRMWARE_ID id; 968 unsigned int offset; 969 unsigned int size; 970 unsigned int size_x16; 971 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 972 973 #define RLC_TOC_OFFSET_DWUNIT 8 974 #define RLC_SIZE_MULTIPLE 1024 975 #define RLC_TOC_UMF_SIZE_inM 23ULL 976 #define RLC_TOC_FORMAT_API 165ULL 977 978 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 979 { 980 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 981 982 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 983 rlc_autoload_info[ucode->id].id = ucode->id; 984 rlc_autoload_info[ucode->id].offset = 985 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 986 rlc_autoload_info[ucode->id].size = 987 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 988 ucode->size * 4; 989 ucode++; 990 } 991 } 992 993 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 994 { 995 uint32_t total_size = 0; 996 SOC24_FIRMWARE_ID id; 997 998 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 999 1000 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1001 total_size += rlc_autoload_info[id].size; 1002 1003 /* In case the offset in rlc toc ucode is aligned */ 1004 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1005 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1006 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1007 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1008 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1009 1010 return total_size; 1011 } 1012 1013 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1014 { 1015 int r; 1016 uint32_t total_size; 1017 1018 total_size = gfx_v12_0_calc_toc_total_size(adev); 1019 1020 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1021 AMDGPU_GEM_DOMAIN_VRAM, 1022 &adev->gfx.rlc.rlc_autoload_bo, 1023 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1024 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1025 1026 if (r) { 1027 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1028 return r; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1035 SOC24_FIRMWARE_ID id, 1036 const void *fw_data, 1037 uint32_t fw_size) 1038 { 1039 uint32_t toc_offset; 1040 uint32_t toc_fw_size; 1041 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1042 1043 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1044 return; 1045 1046 toc_offset = rlc_autoload_info[id].offset; 1047 toc_fw_size = rlc_autoload_info[id].size; 1048 1049 if (fw_size == 0) 1050 fw_size = toc_fw_size; 1051 1052 if (fw_size > toc_fw_size) 1053 fw_size = toc_fw_size; 1054 1055 memcpy(ptr + toc_offset, fw_data, fw_size); 1056 1057 if (fw_size < toc_fw_size) 1058 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1059 } 1060 1061 static void 1062 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1063 { 1064 void *data; 1065 uint32_t size; 1066 uint32_t *toc_ptr; 1067 1068 data = adev->psp.toc.start_addr; 1069 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1070 1071 toc_ptr = (uint32_t *)data + size / 4 - 2; 1072 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1073 1074 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1075 data, size); 1076 } 1077 1078 static void 1079 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1080 { 1081 const __le32 *fw_data; 1082 uint32_t fw_size; 1083 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1084 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1085 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1086 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1087 uint16_t version_major, version_minor; 1088 1089 /* pfp ucode */ 1090 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1091 adev->gfx.pfp_fw->data; 1092 /* instruction */ 1093 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1094 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1095 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1096 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1097 fw_data, fw_size); 1098 /* data */ 1099 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1100 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1101 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1102 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1103 fw_data, fw_size); 1104 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1105 fw_data, fw_size); 1106 /* me ucode */ 1107 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1108 adev->gfx.me_fw->data; 1109 /* instruction */ 1110 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1111 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1112 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1113 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1114 fw_data, fw_size); 1115 /* data */ 1116 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1117 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1118 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1119 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1120 fw_data, fw_size); 1121 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1122 fw_data, fw_size); 1123 /* mec ucode */ 1124 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1125 adev->gfx.mec_fw->data; 1126 /* instruction */ 1127 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1128 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1129 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1130 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1131 fw_data, fw_size); 1132 /* data */ 1133 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1134 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1135 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1136 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1137 fw_data, fw_size); 1138 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1139 fw_data, fw_size); 1140 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1141 fw_data, fw_size); 1142 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1143 fw_data, fw_size); 1144 1145 /* rlc ucode */ 1146 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1147 adev->gfx.rlc_fw->data; 1148 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1149 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1150 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1151 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1152 fw_data, fw_size); 1153 1154 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1155 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1156 if (version_major == 2) { 1157 if (version_minor >= 1) { 1158 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1159 1160 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1161 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1162 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1164 fw_data, fw_size); 1165 1166 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1167 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1168 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1170 fw_data, fw_size); 1171 } 1172 if (version_minor >= 2) { 1173 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1174 1175 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1176 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1177 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1179 fw_data, fw_size); 1180 1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1182 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1183 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1185 fw_data, fw_size); 1186 } 1187 } 1188 } 1189 1190 static void 1191 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1192 { 1193 const __le32 *fw_data; 1194 uint32_t fw_size; 1195 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1196 1197 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1198 adev->sdma.instance[0].fw->data; 1199 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1200 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1201 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1202 1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1204 fw_data, fw_size); 1205 } 1206 1207 static void 1208 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1209 { 1210 const __le32 *fw_data; 1211 unsigned fw_size; 1212 const struct mes_firmware_header_v1_0 *mes_hdr; 1213 int pipe, ucode_id, data_id; 1214 1215 for (pipe = 0; pipe < 2; pipe++) { 1216 if (pipe == 0) { 1217 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1218 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1219 } else { 1220 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1221 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1222 } 1223 1224 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1225 adev->mes.fw[pipe]->data; 1226 1227 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1228 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1229 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1230 1231 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1232 1233 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1234 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1235 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1236 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1238 } 1239 } 1240 1241 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1242 { 1243 uint32_t rlc_g_offset, rlc_g_size; 1244 uint64_t gpu_addr; 1245 uint32_t data; 1246 1247 /* RLC autoload sequence 2: copy ucode */ 1248 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1250 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1251 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1252 1253 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1254 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1255 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1256 1257 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1258 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1259 1260 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1261 1262 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1263 /* RLC autoload sequence 3: load IMU fw */ 1264 if (adev->gfx.imu.funcs->load_microcode) 1265 adev->gfx.imu.funcs->load_microcode(adev); 1266 /* RLC autoload sequence 4 init IMU fw */ 1267 if (adev->gfx.imu.funcs->setup_imu) 1268 adev->gfx.imu.funcs->setup_imu(adev); 1269 if (adev->gfx.imu.funcs->start_imu) 1270 adev->gfx.imu.funcs->start_imu(adev); 1271 1272 /* RLC autoload sequence 5 disable gpa mode */ 1273 gfx_v12_0_disable_gpa_mode(adev); 1274 } else { 1275 /* unhalt rlc to start autoload without imu */ 1276 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1277 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1278 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1279 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1280 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1287 { 1288 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1289 uint32_t *ptr; 1290 uint32_t inst; 1291 1292 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1293 if (!ptr) { 1294 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1295 adev->gfx.ip_dump_core = NULL; 1296 } else { 1297 adev->gfx.ip_dump_core = ptr; 1298 } 1299 1300 /* Allocate memory for compute queue registers for all the instances */ 1301 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1302 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1303 adev->gfx.mec.num_queue_per_pipe; 1304 1305 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1306 if (!ptr) { 1307 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1308 adev->gfx.ip_dump_compute_queues = NULL; 1309 } else { 1310 adev->gfx.ip_dump_compute_queues = ptr; 1311 } 1312 1313 /* Allocate memory for gfx queue registers for all the instances */ 1314 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1315 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1316 adev->gfx.me.num_queue_per_pipe; 1317 1318 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1319 if (!ptr) { 1320 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1321 adev->gfx.ip_dump_gfx_queues = NULL; 1322 } else { 1323 adev->gfx.ip_dump_gfx_queues = ptr; 1324 } 1325 } 1326 1327 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1328 { 1329 int i, j, k, r, ring_id = 0; 1330 unsigned num_compute_rings; 1331 int xcc_id = 0; 1332 struct amdgpu_device *adev = ip_block->adev; 1333 1334 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1335 case IP_VERSION(12, 0, 0): 1336 case IP_VERSION(12, 0, 1): 1337 adev->gfx.me.num_me = 1; 1338 adev->gfx.me.num_pipe_per_me = 1; 1339 adev->gfx.me.num_queue_per_pipe = 1; 1340 adev->gfx.mec.num_mec = 2; 1341 adev->gfx.mec.num_pipe_per_mec = 2; 1342 adev->gfx.mec.num_queue_per_pipe = 4; 1343 break; 1344 default: 1345 adev->gfx.me.num_me = 1; 1346 adev->gfx.me.num_pipe_per_me = 1; 1347 adev->gfx.me.num_queue_per_pipe = 1; 1348 adev->gfx.mec.num_mec = 1; 1349 adev->gfx.mec.num_pipe_per_mec = 4; 1350 adev->gfx.mec.num_queue_per_pipe = 8; 1351 break; 1352 } 1353 1354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1355 default: 1356 adev->gfx.enable_cleaner_shader = false; 1357 break; 1358 } 1359 1360 /* recalculate compute rings to use based on hardware configuration */ 1361 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe) / 2; 1363 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1364 num_compute_rings); 1365 1366 /* EOP Event */ 1367 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1368 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1369 &adev->gfx.eop_irq); 1370 if (r) 1371 return r; 1372 1373 /* Bad opcode Event */ 1374 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1375 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1376 &adev->gfx.bad_op_irq); 1377 if (r) 1378 return r; 1379 1380 /* Privileged reg */ 1381 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1382 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1383 &adev->gfx.priv_reg_irq); 1384 if (r) 1385 return r; 1386 1387 /* Privileged inst */ 1388 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1389 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1390 &adev->gfx.priv_inst_irq); 1391 if (r) 1392 return r; 1393 1394 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1395 1396 gfx_v12_0_me_init(adev); 1397 1398 r = gfx_v12_0_rlc_init(adev); 1399 if (r) { 1400 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1401 return r; 1402 } 1403 1404 r = gfx_v12_0_mec_init(adev); 1405 if (r) { 1406 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1407 return r; 1408 } 1409 1410 /* set up the gfx ring */ 1411 for (i = 0; i < adev->gfx.me.num_me; i++) { 1412 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1413 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1414 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1415 continue; 1416 1417 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1418 i, k, j); 1419 if (r) 1420 return r; 1421 ring_id++; 1422 } 1423 } 1424 } 1425 1426 ring_id = 0; 1427 /* set up the compute queues - allocate horizontally across pipes */ 1428 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1429 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1430 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1431 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1432 0, i, k, j)) 1433 continue; 1434 1435 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1436 i, k, j); 1437 if (r) 1438 return r; 1439 1440 ring_id++; 1441 } 1442 } 1443 } 1444 1445 /* TODO: Add queue reset mask when FW fully supports it */ 1446 adev->gfx.gfx_supported_reset = 1447 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1448 adev->gfx.compute_supported_reset = 1449 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1450 1451 if (!adev->enable_mes_kiq) { 1452 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1453 if (r) { 1454 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1455 return r; 1456 } 1457 1458 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1459 if (r) 1460 return r; 1461 } 1462 1463 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1464 if (r) 1465 return r; 1466 1467 /* allocate visible FB for rlc auto-loading fw */ 1468 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1469 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1470 if (r) 1471 return r; 1472 } 1473 1474 r = gfx_v12_0_gpu_early_init(adev); 1475 if (r) 1476 return r; 1477 1478 gfx_v12_0_alloc_ip_dump(adev); 1479 1480 r = amdgpu_gfx_sysfs_init(adev); 1481 if (r) 1482 return r; 1483 1484 return 0; 1485 } 1486 1487 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1488 { 1489 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1490 &adev->gfx.pfp.pfp_fw_gpu_addr, 1491 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1492 1493 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1494 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1495 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1496 } 1497 1498 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1499 { 1500 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1501 &adev->gfx.me.me_fw_gpu_addr, 1502 (void **)&adev->gfx.me.me_fw_ptr); 1503 1504 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1505 &adev->gfx.me.me_fw_data_gpu_addr, 1506 (void **)&adev->gfx.me.me_fw_data_ptr); 1507 } 1508 1509 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1510 { 1511 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1512 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1513 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1514 } 1515 1516 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1517 { 1518 int i; 1519 struct amdgpu_device *adev = ip_block->adev; 1520 1521 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1522 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1523 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1524 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1525 1526 amdgpu_gfx_mqd_sw_fini(adev, 0); 1527 1528 if (!adev->enable_mes_kiq) { 1529 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1530 amdgpu_gfx_kiq_fini(adev, 0); 1531 } 1532 1533 gfx_v12_0_pfp_fini(adev); 1534 gfx_v12_0_me_fini(adev); 1535 gfx_v12_0_rlc_fini(adev); 1536 gfx_v12_0_mec_fini(adev); 1537 1538 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1539 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1540 1541 gfx_v12_0_free_microcode(adev); 1542 1543 amdgpu_gfx_sysfs_fini(adev); 1544 1545 kfree(adev->gfx.ip_dump_core); 1546 kfree(adev->gfx.ip_dump_compute_queues); 1547 kfree(adev->gfx.ip_dump_gfx_queues); 1548 1549 return 0; 1550 } 1551 1552 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1553 u32 sh_num, u32 instance, int xcc_id) 1554 { 1555 u32 data; 1556 1557 if (instance == 0xffffffff) 1558 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1559 INSTANCE_BROADCAST_WRITES, 1); 1560 else 1561 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1562 instance); 1563 1564 if (se_num == 0xffffffff) 1565 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1566 1); 1567 else 1568 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1569 1570 if (sh_num == 0xffffffff) 1571 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1572 1); 1573 else 1574 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1575 1576 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1577 } 1578 1579 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1580 { 1581 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1582 1583 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1584 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1585 GRBM_CC_GC_SA_UNIT_DISABLE, 1586 SA_DISABLE); 1587 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1588 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1589 GRBM_GC_USER_SA_UNIT_DISABLE, 1590 SA_DISABLE); 1591 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1592 adev->gfx.config.max_shader_engines); 1593 1594 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1595 } 1596 1597 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1598 { 1599 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1600 u32 rb_mask; 1601 1602 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1603 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1604 CC_RB_BACKEND_DISABLE, 1605 BACKEND_DISABLE); 1606 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1607 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1608 GC_USER_RB_BACKEND_DISABLE, 1609 BACKEND_DISABLE); 1610 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1611 adev->gfx.config.max_shader_engines); 1612 1613 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1614 } 1615 1616 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1617 { 1618 u32 rb_bitmap_width_per_sa; 1619 u32 max_sa; 1620 u32 active_sa_bitmap; 1621 u32 global_active_rb_bitmap; 1622 u32 active_rb_bitmap = 0; 1623 u32 i; 1624 1625 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1626 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1627 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1628 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1629 1630 /* generate active rb bitmap according to active sa bitmap */ 1631 max_sa = adev->gfx.config.max_shader_engines * 1632 adev->gfx.config.max_sh_per_se; 1633 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1634 adev->gfx.config.max_sh_per_se; 1635 for (i = 0; i < max_sa; i++) { 1636 if (active_sa_bitmap & (1 << i)) 1637 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1638 } 1639 1640 active_rb_bitmap |= global_active_rb_bitmap; 1641 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1642 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1643 } 1644 1645 #define LDS_APP_BASE 0x1 1646 #define SCRATCH_APP_BASE 0x2 1647 1648 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1649 { 1650 int i; 1651 uint32_t sh_mem_bases; 1652 uint32_t data; 1653 1654 /* 1655 * Configure apertures: 1656 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1657 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1658 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1659 */ 1660 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1661 SCRATCH_APP_BASE; 1662 1663 mutex_lock(&adev->srbm_mutex); 1664 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1665 soc24_grbm_select(adev, 0, 0, 0, i); 1666 /* CP and shaders */ 1667 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1668 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1669 1670 /* Enable trap for each kfd vmid. */ 1671 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1672 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1673 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1674 } 1675 soc24_grbm_select(adev, 0, 0, 0, 0); 1676 mutex_unlock(&adev->srbm_mutex); 1677 } 1678 1679 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1680 { 1681 /* TODO: harvest feature to be added later. */ 1682 } 1683 1684 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1685 { 1686 } 1687 1688 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1689 { 1690 u32 tmp; 1691 int i; 1692 1693 if (!amdgpu_sriov_vf(adev)) 1694 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1695 1696 gfx_v12_0_setup_rb(adev); 1697 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1698 gfx_v12_0_get_tcc_info(adev); 1699 adev->gfx.config.pa_sc_tile_steering_override = 0; 1700 1701 /* XXX SH_MEM regs */ 1702 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1703 mutex_lock(&adev->srbm_mutex); 1704 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1705 soc24_grbm_select(adev, 0, 0, 0, i); 1706 /* CP and shaders */ 1707 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1708 if (i != 0) { 1709 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1710 (adev->gmc.private_aperture_start >> 48)); 1711 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1712 (adev->gmc.shared_aperture_start >> 48)); 1713 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1714 } 1715 } 1716 soc24_grbm_select(adev, 0, 0, 0, 0); 1717 1718 mutex_unlock(&adev->srbm_mutex); 1719 1720 gfx_v12_0_init_compute_vmid(adev); 1721 } 1722 1723 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1724 int me, int pipe) 1725 { 1726 if (me != 0) 1727 return 0; 1728 1729 switch (pipe) { 1730 case 0: 1731 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1732 default: 1733 return 0; 1734 } 1735 } 1736 1737 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1738 int me, int pipe) 1739 { 1740 /* 1741 * amdgpu controls only the first MEC. That's why this function only 1742 * handles the setting of interrupts for this specific MEC. All other 1743 * pipes' interrupts are set by amdkfd. 1744 */ 1745 if (me != 1) 1746 return 0; 1747 1748 switch (pipe) { 1749 case 0: 1750 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1751 case 1: 1752 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1753 default: 1754 return 0; 1755 } 1756 } 1757 1758 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1759 bool enable) 1760 { 1761 u32 tmp, cp_int_cntl_reg; 1762 int i, j; 1763 1764 if (amdgpu_sriov_vf(adev)) 1765 return; 1766 1767 for (i = 0; i < adev->gfx.me.num_me; i++) { 1768 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1769 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1770 1771 if (cp_int_cntl_reg) { 1772 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1773 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1774 enable ? 1 : 0); 1775 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1776 enable ? 1 : 0); 1777 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1778 enable ? 1 : 0); 1779 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1780 enable ? 1 : 0); 1781 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1782 } 1783 } 1784 } 1785 } 1786 1787 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1788 { 1789 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1790 1791 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1792 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1793 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1794 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1795 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1796 1797 return 0; 1798 } 1799 1800 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1801 { 1802 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1803 1804 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1805 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1806 } 1807 1808 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1809 { 1810 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1811 udelay(50); 1812 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1813 udelay(50); 1814 } 1815 1816 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1817 bool enable) 1818 { 1819 uint32_t rlc_pg_cntl; 1820 1821 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1822 1823 if (!enable) { 1824 /* RLC_PG_CNTL[23] = 0 (default) 1825 * RLC will wait for handshake acks with SMU 1826 * GFXOFF will be enabled 1827 * RLC_PG_CNTL[23] = 1 1828 * RLC will not issue any message to SMU 1829 * hence no handshake between SMU & RLC 1830 * GFXOFF will be disabled 1831 */ 1832 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1833 } else 1834 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1835 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1836 } 1837 1838 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1839 { 1840 /* TODO: enable rlc & smu handshake until smu 1841 * and gfxoff feature works as expected */ 1842 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1843 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1844 1845 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1846 udelay(50); 1847 } 1848 1849 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1850 { 1851 uint32_t tmp; 1852 1853 /* enable Save Restore Machine */ 1854 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1855 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1856 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1857 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1858 } 1859 1860 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1861 { 1862 const struct rlc_firmware_header_v2_0 *hdr; 1863 const __le32 *fw_data; 1864 unsigned i, fw_size; 1865 1866 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1867 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1868 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1869 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1870 1871 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1872 RLCG_UCODE_LOADING_START_ADDRESS); 1873 1874 for (i = 0; i < fw_size; i++) 1875 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1876 le32_to_cpup(fw_data++)); 1877 1878 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1879 } 1880 1881 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1882 { 1883 const struct rlc_firmware_header_v2_2 *hdr; 1884 const __le32 *fw_data; 1885 unsigned i, fw_size; 1886 u32 tmp; 1887 1888 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1889 1890 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1891 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1892 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1893 1894 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1895 1896 for (i = 0; i < fw_size; i++) { 1897 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1898 msleep(1); 1899 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1900 le32_to_cpup(fw_data++)); 1901 } 1902 1903 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1904 1905 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1906 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1907 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1908 1909 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1910 for (i = 0; i < fw_size; i++) { 1911 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1912 msleep(1); 1913 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1914 le32_to_cpup(fw_data++)); 1915 } 1916 1917 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1918 1919 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1920 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1921 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1922 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1923 } 1924 1925 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1926 { 1927 const struct rlc_firmware_header_v2_0 *hdr; 1928 uint16_t version_major; 1929 uint16_t version_minor; 1930 1931 if (!adev->gfx.rlc_fw) 1932 return -EINVAL; 1933 1934 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1935 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1936 1937 version_major = le16_to_cpu(hdr->header.header_version_major); 1938 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1939 1940 if (version_major == 2) { 1941 gfx_v12_0_load_rlcg_microcode(adev); 1942 if (amdgpu_dpm == 1) { 1943 if (version_minor >= 2) 1944 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1945 } 1946 1947 return 0; 1948 } 1949 1950 return -EINVAL; 1951 } 1952 1953 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1954 { 1955 int r; 1956 1957 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1958 gfx_v12_0_init_csb(adev); 1959 1960 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1961 gfx_v12_0_rlc_enable_srm(adev); 1962 } else { 1963 if (amdgpu_sriov_vf(adev)) { 1964 gfx_v12_0_init_csb(adev); 1965 return 0; 1966 } 1967 1968 adev->gfx.rlc.funcs->stop(adev); 1969 1970 /* disable CG */ 1971 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1972 1973 /* disable PG */ 1974 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1975 1976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1977 /* legacy rlc firmware loading */ 1978 r = gfx_v12_0_rlc_load_microcode(adev); 1979 if (r) 1980 return r; 1981 } 1982 1983 gfx_v12_0_init_csb(adev); 1984 1985 adev->gfx.rlc.funcs->start(adev); 1986 } 1987 1988 return 0; 1989 } 1990 1991 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 1992 { 1993 const struct gfx_firmware_header_v2_0 *pfp_hdr; 1994 const struct gfx_firmware_header_v2_0 *me_hdr; 1995 const struct gfx_firmware_header_v2_0 *mec_hdr; 1996 uint32_t pipe_id, tmp; 1997 1998 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1999 adev->gfx.mec_fw->data; 2000 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2001 adev->gfx.me_fw->data; 2002 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2003 adev->gfx.pfp_fw->data; 2004 2005 /* config pfp program start addr */ 2006 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2007 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2008 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2009 (pfp_hdr->ucode_start_addr_hi << 30) | 2010 (pfp_hdr->ucode_start_addr_lo >> 2)); 2011 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2012 pfp_hdr->ucode_start_addr_hi >> 2); 2013 } 2014 soc24_grbm_select(adev, 0, 0, 0, 0); 2015 2016 /* reset pfp pipe */ 2017 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2018 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2019 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2020 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2021 2022 /* clear pfp pipe reset */ 2023 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2024 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2025 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2026 2027 /* config me program start addr */ 2028 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2029 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2030 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2031 (me_hdr->ucode_start_addr_hi << 30) | 2032 (me_hdr->ucode_start_addr_lo >> 2)); 2033 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2034 me_hdr->ucode_start_addr_hi>>2); 2035 } 2036 soc24_grbm_select(adev, 0, 0, 0, 0); 2037 2038 /* reset me pipe */ 2039 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2041 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2042 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2043 2044 /* clear me pipe reset */ 2045 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2046 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2047 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2048 2049 /* config mec program start addr */ 2050 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2051 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2052 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2053 mec_hdr->ucode_start_addr_lo >> 2 | 2054 mec_hdr->ucode_start_addr_hi << 30); 2055 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2056 mec_hdr->ucode_start_addr_hi >> 2); 2057 } 2058 soc24_grbm_select(adev, 0, 0, 0, 0); 2059 2060 /* reset mec pipe */ 2061 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2062 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2063 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2064 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2065 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2066 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2067 2068 /* clear mec pipe reset */ 2069 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2070 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2071 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2072 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2073 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2074 } 2075 2076 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2077 { 2078 const struct gfx_firmware_header_v2_0 *cp_hdr; 2079 unsigned pipe_id, tmp; 2080 2081 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2082 adev->gfx.pfp_fw->data; 2083 mutex_lock(&adev->srbm_mutex); 2084 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2085 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2086 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2087 (cp_hdr->ucode_start_addr_hi << 30) | 2088 (cp_hdr->ucode_start_addr_lo >> 2)); 2089 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2090 cp_hdr->ucode_start_addr_hi>>2); 2091 2092 /* 2093 * Program CP_ME_CNTL to reset given PIPE to take 2094 * effect of CP_PFP_PRGRM_CNTR_START. 2095 */ 2096 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2097 if (pipe_id == 0) 2098 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2099 PFP_PIPE0_RESET, 1); 2100 else 2101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2102 PFP_PIPE1_RESET, 1); 2103 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2104 2105 /* Clear pfp pipe0 reset bit. */ 2106 if (pipe_id == 0) 2107 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2108 PFP_PIPE0_RESET, 0); 2109 else 2110 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2111 PFP_PIPE1_RESET, 0); 2112 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2113 } 2114 soc24_grbm_select(adev, 0, 0, 0, 0); 2115 mutex_unlock(&adev->srbm_mutex); 2116 } 2117 2118 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2119 { 2120 const struct gfx_firmware_header_v2_0 *cp_hdr; 2121 unsigned pipe_id, tmp; 2122 2123 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2124 adev->gfx.me_fw->data; 2125 mutex_lock(&adev->srbm_mutex); 2126 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2127 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2128 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2129 (cp_hdr->ucode_start_addr_hi << 30) | 2130 (cp_hdr->ucode_start_addr_lo >> 2) ); 2131 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2132 cp_hdr->ucode_start_addr_hi>>2); 2133 2134 /* 2135 * Program CP_ME_CNTL to reset given PIPE to take 2136 * effect of CP_ME_PRGRM_CNTR_START. 2137 */ 2138 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2139 if (pipe_id == 0) 2140 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2141 ME_PIPE0_RESET, 1); 2142 else 2143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2144 ME_PIPE1_RESET, 1); 2145 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2146 2147 /* Clear pfp pipe0 reset bit. */ 2148 if (pipe_id == 0) 2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2150 ME_PIPE0_RESET, 0); 2151 else 2152 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2153 ME_PIPE1_RESET, 0); 2154 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2155 } 2156 soc24_grbm_select(adev, 0, 0, 0, 0); 2157 mutex_unlock(&adev->srbm_mutex); 2158 } 2159 2160 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2161 { 2162 const struct gfx_firmware_header_v2_0 *cp_hdr; 2163 unsigned pipe_id; 2164 2165 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2166 adev->gfx.mec_fw->data; 2167 mutex_lock(&adev->srbm_mutex); 2168 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2169 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2170 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2171 cp_hdr->ucode_start_addr_lo >> 2 | 2172 cp_hdr->ucode_start_addr_hi << 30); 2173 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2174 cp_hdr->ucode_start_addr_hi >> 2); 2175 } 2176 soc24_grbm_select(adev, 0, 0, 0, 0); 2177 mutex_unlock(&adev->srbm_mutex); 2178 } 2179 2180 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2181 { 2182 uint32_t cp_status; 2183 uint32_t bootload_status; 2184 int i; 2185 2186 for (i = 0; i < adev->usec_timeout; i++) { 2187 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2188 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2189 2190 if ((cp_status == 0) && 2191 (REG_GET_FIELD(bootload_status, 2192 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2193 break; 2194 } 2195 udelay(1); 2196 if (amdgpu_emu_mode) 2197 msleep(10); 2198 } 2199 2200 if (i >= adev->usec_timeout) { 2201 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2202 return -ETIMEDOUT; 2203 } 2204 2205 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2206 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2207 gfx_v12_0_set_me_ucode_start_addr(adev); 2208 gfx_v12_0_set_mec_ucode_start_addr(adev); 2209 } 2210 2211 return 0; 2212 } 2213 2214 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2215 { 2216 int i; 2217 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2218 2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2221 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2222 2223 for (i = 0; i < adev->usec_timeout; i++) { 2224 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2225 break; 2226 udelay(1); 2227 } 2228 2229 if (i >= adev->usec_timeout) 2230 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2231 2232 return 0; 2233 } 2234 2235 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2236 { 2237 int r; 2238 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2239 const __le32 *fw_ucode, *fw_data; 2240 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2241 uint32_t tmp; 2242 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2243 2244 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2245 adev->gfx.pfp_fw->data; 2246 2247 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2248 2249 /* instruction */ 2250 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2251 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2252 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2253 /* data */ 2254 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2255 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2256 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2257 2258 /* 64kb align */ 2259 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2260 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2261 &adev->gfx.pfp.pfp_fw_obj, 2262 &adev->gfx.pfp.pfp_fw_gpu_addr, 2263 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2264 if (r) { 2265 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2266 gfx_v12_0_pfp_fini(adev); 2267 return r; 2268 } 2269 2270 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2271 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2272 &adev->gfx.pfp.pfp_fw_data_obj, 2273 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2274 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2275 if (r) { 2276 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2277 gfx_v12_0_pfp_fini(adev); 2278 return r; 2279 } 2280 2281 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2282 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2283 2284 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2285 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2286 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2287 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2288 2289 if (amdgpu_emu_mode == 1) 2290 adev->hdp.funcs->flush_hdp(adev, NULL); 2291 2292 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2293 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2294 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2295 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2296 2297 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2298 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2299 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2300 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2301 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2302 2303 /* 2304 * Programming any of the CP_PFP_IC_BASE registers 2305 * forces invalidation of the ME L1 I$. Wait for the 2306 * invalidation complete 2307 */ 2308 for (i = 0; i < usec_timeout; i++) { 2309 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2310 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2311 INVALIDATE_CACHE_COMPLETE)) 2312 break; 2313 udelay(1); 2314 } 2315 2316 if (i >= usec_timeout) { 2317 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2318 return -EINVAL; 2319 } 2320 2321 /* Prime the L1 instruction caches */ 2322 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2323 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2324 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2325 /* Waiting for cache primed*/ 2326 for (i = 0; i < usec_timeout; i++) { 2327 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2328 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2329 ICACHE_PRIMED)) 2330 break; 2331 udelay(1); 2332 } 2333 2334 if (i >= usec_timeout) { 2335 dev_err(adev->dev, "failed to prime instruction cache\n"); 2336 return -EINVAL; 2337 } 2338 2339 mutex_lock(&adev->srbm_mutex); 2340 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2341 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2342 2343 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2344 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2345 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2346 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2347 } 2348 soc24_grbm_select(adev, 0, 0, 0, 0); 2349 mutex_unlock(&adev->srbm_mutex); 2350 2351 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2352 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2353 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2354 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2355 2356 /* Invalidate the data caches */ 2357 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2358 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2359 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2360 2361 for (i = 0; i < usec_timeout; i++) { 2362 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2363 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2364 INVALIDATE_DCACHE_COMPLETE)) 2365 break; 2366 udelay(1); 2367 } 2368 2369 if (i >= usec_timeout) { 2370 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2371 return -EINVAL; 2372 } 2373 2374 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2375 2376 return 0; 2377 } 2378 2379 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2380 { 2381 int r; 2382 const struct gfx_firmware_header_v2_0 *me_hdr; 2383 const __le32 *fw_ucode, *fw_data; 2384 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2385 uint32_t tmp; 2386 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2387 2388 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2389 adev->gfx.me_fw->data; 2390 2391 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2392 2393 /* instruction */ 2394 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2395 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2396 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2397 /* data */ 2398 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2399 le32_to_cpu(me_hdr->data_offset_bytes)); 2400 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2401 2402 /* 64kb align*/ 2403 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2404 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2405 &adev->gfx.me.me_fw_obj, 2406 &adev->gfx.me.me_fw_gpu_addr, 2407 (void **)&adev->gfx.me.me_fw_ptr); 2408 if (r) { 2409 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2410 gfx_v12_0_me_fini(adev); 2411 return r; 2412 } 2413 2414 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2415 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2416 &adev->gfx.me.me_fw_data_obj, 2417 &adev->gfx.me.me_fw_data_gpu_addr, 2418 (void **)&adev->gfx.me.me_fw_data_ptr); 2419 if (r) { 2420 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2421 gfx_v12_0_pfp_fini(adev); 2422 return r; 2423 } 2424 2425 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2426 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2427 2428 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2429 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2430 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2431 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2432 2433 if (amdgpu_emu_mode == 1) 2434 adev->hdp.funcs->flush_hdp(adev, NULL); 2435 2436 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2437 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2438 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2439 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2440 2441 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2442 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2443 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2444 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2445 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2446 2447 /* 2448 * Programming any of the CP_ME_IC_BASE registers 2449 * forces invalidation of the ME L1 I$. Wait for the 2450 * invalidation complete 2451 */ 2452 for (i = 0; i < usec_timeout; i++) { 2453 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2454 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2455 INVALIDATE_CACHE_COMPLETE)) 2456 break; 2457 udelay(1); 2458 } 2459 2460 if (i >= usec_timeout) { 2461 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2462 return -EINVAL; 2463 } 2464 2465 /* Prime the instruction caches */ 2466 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2467 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2468 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2469 2470 /* Waiting for instruction cache primed*/ 2471 for (i = 0; i < usec_timeout; i++) { 2472 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2473 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2474 ICACHE_PRIMED)) 2475 break; 2476 udelay(1); 2477 } 2478 2479 if (i >= usec_timeout) { 2480 dev_err(adev->dev, "failed to prime instruction cache\n"); 2481 return -EINVAL; 2482 } 2483 2484 mutex_lock(&adev->srbm_mutex); 2485 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2486 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2487 2488 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2489 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2490 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2491 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2492 } 2493 soc24_grbm_select(adev, 0, 0, 0, 0); 2494 mutex_unlock(&adev->srbm_mutex); 2495 2496 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2497 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2498 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2499 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2500 2501 /* Invalidate the data caches */ 2502 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2503 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2504 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2505 2506 for (i = 0; i < usec_timeout; i++) { 2507 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2508 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2509 INVALIDATE_DCACHE_COMPLETE)) 2510 break; 2511 udelay(1); 2512 } 2513 2514 if (i >= usec_timeout) { 2515 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2516 return -EINVAL; 2517 } 2518 2519 gfx_v12_0_set_me_ucode_start_addr(adev); 2520 2521 return 0; 2522 } 2523 2524 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2525 { 2526 int r; 2527 2528 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2529 return -EINVAL; 2530 2531 gfx_v12_0_cp_gfx_enable(adev, false); 2532 2533 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2534 if (r) { 2535 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2536 return r; 2537 } 2538 2539 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2540 if (r) { 2541 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2542 return r; 2543 } 2544 2545 return 0; 2546 } 2547 2548 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2549 { 2550 /* init the CP */ 2551 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2552 adev->gfx.config.max_hw_contexts - 1); 2553 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2554 2555 if (!amdgpu_async_gfx_ring) 2556 gfx_v12_0_cp_gfx_enable(adev, true); 2557 2558 return 0; 2559 } 2560 2561 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2562 CP_PIPE_ID pipe) 2563 { 2564 u32 tmp; 2565 2566 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2567 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2568 2569 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2570 } 2571 2572 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2573 struct amdgpu_ring *ring) 2574 { 2575 u32 tmp; 2576 2577 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2578 if (ring->use_doorbell) { 2579 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2580 DOORBELL_OFFSET, ring->doorbell_index); 2581 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2582 DOORBELL_EN, 1); 2583 } else { 2584 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2585 DOORBELL_EN, 0); 2586 } 2587 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2588 2589 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2590 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2591 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2592 2593 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2594 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2595 } 2596 2597 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2598 { 2599 struct amdgpu_ring *ring; 2600 u32 tmp; 2601 u32 rb_bufsz; 2602 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2603 u32 i; 2604 2605 /* Set the write pointer delay */ 2606 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2607 2608 /* set the RB to use vmid 0 */ 2609 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2610 2611 /* Init gfx ring 0 for pipe 0 */ 2612 mutex_lock(&adev->srbm_mutex); 2613 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2614 2615 /* Set ring buffer size */ 2616 ring = &adev->gfx.gfx_ring[0]; 2617 rb_bufsz = order_base_2(ring->ring_size / 8); 2618 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2619 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2620 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2621 2622 /* Initialize the ring buffer's write pointers */ 2623 ring->wptr = 0; 2624 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2625 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2626 2627 /* set the wb address whether it's enabled or not */ 2628 rptr_addr = ring->rptr_gpu_addr; 2629 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2630 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2631 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2632 2633 wptr_gpu_addr = ring->wptr_gpu_addr; 2634 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2635 lower_32_bits(wptr_gpu_addr)); 2636 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2637 upper_32_bits(wptr_gpu_addr)); 2638 2639 mdelay(1); 2640 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2641 2642 rb_addr = ring->gpu_addr >> 8; 2643 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2644 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2645 2646 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2647 2648 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2649 mutex_unlock(&adev->srbm_mutex); 2650 2651 /* Switch to pipe 0 */ 2652 mutex_lock(&adev->srbm_mutex); 2653 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2654 mutex_unlock(&adev->srbm_mutex); 2655 2656 /* start the ring */ 2657 gfx_v12_0_cp_gfx_start(adev); 2658 2659 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2660 ring = &adev->gfx.gfx_ring[i]; 2661 ring->sched.ready = true; 2662 } 2663 2664 return 0; 2665 } 2666 2667 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2668 { 2669 u32 data; 2670 2671 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2672 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2673 enable ? 0 : 1); 2674 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2675 enable ? 0 : 1); 2676 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2677 enable ? 0 : 1); 2678 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2679 enable ? 0 : 1); 2680 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2681 enable ? 0 : 1); 2682 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2683 enable ? 1 : 0); 2684 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2685 enable ? 1 : 0); 2686 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2687 enable ? 1 : 0); 2688 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2689 enable ? 1 : 0); 2690 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2691 enable ? 0 : 1); 2692 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2693 2694 adev->gfx.kiq[0].ring.sched.ready = enable; 2695 2696 udelay(50); 2697 } 2698 2699 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2700 { 2701 const struct gfx_firmware_header_v2_0 *mec_hdr; 2702 const __le32 *fw_ucode, *fw_data; 2703 u32 tmp, fw_ucode_size, fw_data_size; 2704 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2705 u32 *fw_ucode_ptr, *fw_data_ptr; 2706 int r; 2707 2708 if (!adev->gfx.mec_fw) 2709 return -EINVAL; 2710 2711 gfx_v12_0_cp_compute_enable(adev, false); 2712 2713 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2714 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2715 2716 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2717 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2718 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2719 2720 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2721 le32_to_cpu(mec_hdr->data_offset_bytes)); 2722 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2723 2724 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2725 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2726 &adev->gfx.mec.mec_fw_obj, 2727 &adev->gfx.mec.mec_fw_gpu_addr, 2728 (void **)&fw_ucode_ptr); 2729 if (r) { 2730 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2731 gfx_v12_0_mec_fini(adev); 2732 return r; 2733 } 2734 2735 r = amdgpu_bo_create_reserved(adev, 2736 ALIGN(fw_data_size, 64 * 1024) * 2737 adev->gfx.mec.num_pipe_per_mec, 2738 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2739 &adev->gfx.mec.mec_fw_data_obj, 2740 &adev->gfx.mec.mec_fw_data_gpu_addr, 2741 (void **)&fw_data_ptr); 2742 if (r) { 2743 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2744 gfx_v12_0_mec_fini(adev); 2745 return r; 2746 } 2747 2748 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2749 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2750 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2751 } 2752 2753 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2754 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2755 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2756 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2757 2758 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2759 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2760 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2761 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2762 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2763 2764 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2765 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2766 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2767 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2768 2769 mutex_lock(&adev->srbm_mutex); 2770 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2771 soc24_grbm_select(adev, 1, i, 0, 0); 2772 2773 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2774 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2775 i * ALIGN(fw_data_size, 64 * 1024))); 2776 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2777 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2778 i * ALIGN(fw_data_size, 64 * 1024))); 2779 2780 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2781 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2782 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2783 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2784 } 2785 mutex_unlock(&adev->srbm_mutex); 2786 soc24_grbm_select(adev, 0, 0, 0, 0); 2787 2788 /* Trigger an invalidation of the L1 instruction caches */ 2789 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2790 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2791 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2792 2793 /* Wait for invalidation complete */ 2794 for (i = 0; i < usec_timeout; i++) { 2795 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2796 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2797 INVALIDATE_DCACHE_COMPLETE)) 2798 break; 2799 udelay(1); 2800 } 2801 2802 if (i >= usec_timeout) { 2803 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2804 return -EINVAL; 2805 } 2806 2807 /* Trigger an invalidation of the L1 instruction caches */ 2808 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2809 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2810 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2811 2812 /* Wait for invalidation complete */ 2813 for (i = 0; i < usec_timeout; i++) { 2814 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2815 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2816 INVALIDATE_CACHE_COMPLETE)) 2817 break; 2818 udelay(1); 2819 } 2820 2821 if (i >= usec_timeout) { 2822 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2823 return -EINVAL; 2824 } 2825 2826 gfx_v12_0_set_mec_ucode_start_addr(adev); 2827 2828 return 0; 2829 } 2830 2831 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2832 { 2833 uint32_t tmp; 2834 struct amdgpu_device *adev = ring->adev; 2835 2836 /* tell RLC which is KIQ queue */ 2837 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2838 tmp &= 0xffffff00; 2839 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2840 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2841 } 2842 2843 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2844 { 2845 /* set graphics engine doorbell range */ 2846 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2847 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2848 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2849 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2850 2851 /* set compute engine doorbell range */ 2852 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2853 (adev->doorbell_index.kiq * 2) << 2); 2854 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2855 (adev->doorbell_index.userqueue_end * 2) << 2); 2856 } 2857 2858 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2859 struct amdgpu_mqd_prop *prop) 2860 { 2861 struct v12_gfx_mqd *mqd = m; 2862 uint64_t hqd_gpu_addr, wb_gpu_addr; 2863 uint32_t tmp; 2864 uint32_t rb_bufsz; 2865 2866 /* set up gfx hqd wptr */ 2867 mqd->cp_gfx_hqd_wptr = 0; 2868 mqd->cp_gfx_hqd_wptr_hi = 0; 2869 2870 /* set the pointer to the MQD */ 2871 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2872 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2873 2874 /* set up mqd control */ 2875 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2876 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2877 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2878 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2879 mqd->cp_gfx_mqd_control = tmp; 2880 2881 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2882 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2883 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2884 mqd->cp_gfx_hqd_vmid = 0; 2885 2886 /* set up default queue priority level 2887 * 0x0 = low priority, 0x1 = high priority */ 2888 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2889 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2890 mqd->cp_gfx_hqd_queue_priority = tmp; 2891 2892 /* set up time quantum */ 2893 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2894 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2895 mqd->cp_gfx_hqd_quantum = tmp; 2896 2897 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2898 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2899 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2900 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2901 2902 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2903 wb_gpu_addr = prop->rptr_gpu_addr; 2904 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2905 mqd->cp_gfx_hqd_rptr_addr_hi = 2906 upper_32_bits(wb_gpu_addr) & 0xffff; 2907 2908 /* set up rb_wptr_poll addr */ 2909 wb_gpu_addr = prop->wptr_gpu_addr; 2910 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2911 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2912 2913 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2914 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2915 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2916 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2917 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2918 #ifdef __BIG_ENDIAN 2919 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2920 #endif 2921 mqd->cp_gfx_hqd_cntl = tmp; 2922 2923 /* set up cp_doorbell_control */ 2924 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2925 if (prop->use_doorbell) { 2926 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2927 DOORBELL_OFFSET, prop->doorbell_index); 2928 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2929 DOORBELL_EN, 1); 2930 } else 2931 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2932 DOORBELL_EN, 0); 2933 mqd->cp_rb_doorbell_control = tmp; 2934 2935 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2936 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2937 2938 /* active the queue */ 2939 mqd->cp_gfx_hqd_active = 1; 2940 2941 return 0; 2942 } 2943 2944 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2945 { 2946 struct amdgpu_device *adev = ring->adev; 2947 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2948 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2949 2950 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2951 memset((void *)mqd, 0, sizeof(*mqd)); 2952 mutex_lock(&adev->srbm_mutex); 2953 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2954 amdgpu_ring_init_mqd(ring); 2955 soc24_grbm_select(adev, 0, 0, 0, 0); 2956 mutex_unlock(&adev->srbm_mutex); 2957 if (adev->gfx.me.mqd_backup[mqd_idx]) 2958 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2959 } else { 2960 /* restore mqd with the backup copy */ 2961 if (adev->gfx.me.mqd_backup[mqd_idx]) 2962 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2963 /* reset the ring */ 2964 ring->wptr = 0; 2965 *ring->wptr_cpu_addr = 0; 2966 amdgpu_ring_clear_ring(ring); 2967 } 2968 2969 return 0; 2970 } 2971 2972 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2973 { 2974 int r, i; 2975 struct amdgpu_ring *ring; 2976 2977 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2978 ring = &adev->gfx.gfx_ring[i]; 2979 2980 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2981 if (unlikely(r != 0)) 2982 goto done; 2983 2984 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2985 if (!r) { 2986 r = gfx_v12_0_kgq_init_queue(ring, false); 2987 amdgpu_bo_kunmap(ring->mqd_obj); 2988 ring->mqd_ptr = NULL; 2989 } 2990 amdgpu_bo_unreserve(ring->mqd_obj); 2991 if (r) 2992 goto done; 2993 } 2994 2995 r = amdgpu_gfx_enable_kgq(adev, 0); 2996 if (r) 2997 goto done; 2998 2999 r = gfx_v12_0_cp_gfx_start(adev); 3000 if (r) 3001 goto done; 3002 3003 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3004 ring = &adev->gfx.gfx_ring[i]; 3005 ring->sched.ready = true; 3006 } 3007 done: 3008 return r; 3009 } 3010 3011 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3012 struct amdgpu_mqd_prop *prop) 3013 { 3014 struct v12_compute_mqd *mqd = m; 3015 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3016 uint32_t tmp; 3017 3018 mqd->header = 0xC0310800; 3019 mqd->compute_pipelinestat_enable = 0x00000001; 3020 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3021 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3022 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3023 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3024 mqd->compute_misc_reserved = 0x00000007; 3025 3026 eop_base_addr = prop->eop_gpu_addr >> 8; 3027 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3028 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3029 3030 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3031 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3032 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3033 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3034 3035 mqd->cp_hqd_eop_control = tmp; 3036 3037 /* enable doorbell? */ 3038 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3039 3040 if (prop->use_doorbell) { 3041 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3042 DOORBELL_OFFSET, prop->doorbell_index); 3043 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3044 DOORBELL_EN, 1); 3045 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3046 DOORBELL_SOURCE, 0); 3047 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3048 DOORBELL_HIT, 0); 3049 } else { 3050 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3051 DOORBELL_EN, 0); 3052 } 3053 3054 mqd->cp_hqd_pq_doorbell_control = tmp; 3055 3056 /* disable the queue if it's active */ 3057 mqd->cp_hqd_dequeue_request = 0; 3058 mqd->cp_hqd_pq_rptr = 0; 3059 mqd->cp_hqd_pq_wptr_lo = 0; 3060 mqd->cp_hqd_pq_wptr_hi = 0; 3061 3062 /* set the pointer to the MQD */ 3063 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3064 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3065 3066 /* set MQD vmid to 0 */ 3067 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3068 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3069 mqd->cp_mqd_control = tmp; 3070 3071 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3072 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3073 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3074 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3075 3076 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3077 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3078 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3079 (order_base_2(prop->queue_size / 4) - 1)); 3080 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3081 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3082 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3083 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3084 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3085 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3086 mqd->cp_hqd_pq_control = tmp; 3087 3088 /* set the wb address whether it's enabled or not */ 3089 wb_gpu_addr = prop->rptr_gpu_addr; 3090 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3091 mqd->cp_hqd_pq_rptr_report_addr_hi = 3092 upper_32_bits(wb_gpu_addr) & 0xffff; 3093 3094 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3095 wb_gpu_addr = prop->wptr_gpu_addr; 3096 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3097 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3098 3099 tmp = 0; 3100 /* enable the doorbell if requested */ 3101 if (prop->use_doorbell) { 3102 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3104 DOORBELL_OFFSET, prop->doorbell_index); 3105 3106 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3107 DOORBELL_EN, 1); 3108 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3109 DOORBELL_SOURCE, 0); 3110 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3111 DOORBELL_HIT, 0); 3112 } 3113 3114 mqd->cp_hqd_pq_doorbell_control = tmp; 3115 3116 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3117 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3118 3119 /* set the vmid for the queue */ 3120 mqd->cp_hqd_vmid = 0; 3121 3122 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3123 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3124 mqd->cp_hqd_persistent_state = tmp; 3125 3126 /* set MIN_IB_AVAIL_SIZE */ 3127 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3128 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3129 mqd->cp_hqd_ib_control = tmp; 3130 3131 /* set static priority for a compute queue/ring */ 3132 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3133 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3134 3135 mqd->cp_hqd_active = prop->hqd_active; 3136 3137 return 0; 3138 } 3139 3140 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3141 { 3142 struct amdgpu_device *adev = ring->adev; 3143 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3144 int j; 3145 3146 /* inactivate the queue */ 3147 if (amdgpu_sriov_vf(adev)) 3148 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3149 3150 /* disable wptr polling */ 3151 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3152 3153 /* write the EOP addr */ 3154 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3155 mqd->cp_hqd_eop_base_addr_lo); 3156 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3157 mqd->cp_hqd_eop_base_addr_hi); 3158 3159 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3160 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3161 mqd->cp_hqd_eop_control); 3162 3163 /* enable doorbell? */ 3164 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3165 mqd->cp_hqd_pq_doorbell_control); 3166 3167 /* disable the queue if it's active */ 3168 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3169 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3170 for (j = 0; j < adev->usec_timeout; j++) { 3171 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3172 break; 3173 udelay(1); 3174 } 3175 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3176 mqd->cp_hqd_dequeue_request); 3177 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3178 mqd->cp_hqd_pq_rptr); 3179 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3180 mqd->cp_hqd_pq_wptr_lo); 3181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3182 mqd->cp_hqd_pq_wptr_hi); 3183 } 3184 3185 /* set the pointer to the MQD */ 3186 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3187 mqd->cp_mqd_base_addr_lo); 3188 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3189 mqd->cp_mqd_base_addr_hi); 3190 3191 /* set MQD vmid to 0 */ 3192 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3193 mqd->cp_mqd_control); 3194 3195 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3196 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3197 mqd->cp_hqd_pq_base_lo); 3198 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3199 mqd->cp_hqd_pq_base_hi); 3200 3201 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3202 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3203 mqd->cp_hqd_pq_control); 3204 3205 /* set the wb address whether it's enabled or not */ 3206 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3207 mqd->cp_hqd_pq_rptr_report_addr_lo); 3208 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3209 mqd->cp_hqd_pq_rptr_report_addr_hi); 3210 3211 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3212 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3213 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3214 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3215 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3216 3217 /* enable the doorbell if requested */ 3218 if (ring->use_doorbell) { 3219 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3220 (adev->doorbell_index.kiq * 2) << 2); 3221 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3222 (adev->doorbell_index.userqueue_end * 2) << 2); 3223 } 3224 3225 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3226 mqd->cp_hqd_pq_doorbell_control); 3227 3228 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3229 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3230 mqd->cp_hqd_pq_wptr_lo); 3231 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3232 mqd->cp_hqd_pq_wptr_hi); 3233 3234 /* set the vmid for the queue */ 3235 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3236 3237 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3238 mqd->cp_hqd_persistent_state); 3239 3240 /* activate the queue */ 3241 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3242 mqd->cp_hqd_active); 3243 3244 if (ring->use_doorbell) 3245 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3246 3247 return 0; 3248 } 3249 3250 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3251 { 3252 struct amdgpu_device *adev = ring->adev; 3253 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3254 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3255 3256 gfx_v12_0_kiq_setting(ring); 3257 3258 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3259 /* reset MQD to a clean status */ 3260 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3261 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3262 3263 /* reset ring buffer */ 3264 ring->wptr = 0; 3265 amdgpu_ring_clear_ring(ring); 3266 3267 mutex_lock(&adev->srbm_mutex); 3268 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3269 gfx_v12_0_kiq_init_register(ring); 3270 soc24_grbm_select(adev, 0, 0, 0, 0); 3271 mutex_unlock(&adev->srbm_mutex); 3272 } else { 3273 memset((void *)mqd, 0, sizeof(*mqd)); 3274 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3275 amdgpu_ring_clear_ring(ring); 3276 mutex_lock(&adev->srbm_mutex); 3277 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3278 amdgpu_ring_init_mqd(ring); 3279 gfx_v12_0_kiq_init_register(ring); 3280 soc24_grbm_select(adev, 0, 0, 0, 0); 3281 mutex_unlock(&adev->srbm_mutex); 3282 3283 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3284 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3285 } 3286 3287 return 0; 3288 } 3289 3290 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3291 { 3292 struct amdgpu_device *adev = ring->adev; 3293 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3294 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3295 3296 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3297 memset((void *)mqd, 0, sizeof(*mqd)); 3298 mutex_lock(&adev->srbm_mutex); 3299 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3300 amdgpu_ring_init_mqd(ring); 3301 soc24_grbm_select(adev, 0, 0, 0, 0); 3302 mutex_unlock(&adev->srbm_mutex); 3303 3304 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3305 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3306 } else { 3307 /* restore MQD to a clean status */ 3308 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3309 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3310 /* reset ring buffer */ 3311 ring->wptr = 0; 3312 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3313 amdgpu_ring_clear_ring(ring); 3314 } 3315 3316 return 0; 3317 } 3318 3319 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3320 { 3321 struct amdgpu_ring *ring; 3322 int r; 3323 3324 ring = &adev->gfx.kiq[0].ring; 3325 3326 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3327 if (unlikely(r != 0)) 3328 return r; 3329 3330 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3331 if (unlikely(r != 0)) { 3332 amdgpu_bo_unreserve(ring->mqd_obj); 3333 return r; 3334 } 3335 3336 gfx_v12_0_kiq_init_queue(ring); 3337 amdgpu_bo_kunmap(ring->mqd_obj); 3338 ring->mqd_ptr = NULL; 3339 amdgpu_bo_unreserve(ring->mqd_obj); 3340 ring->sched.ready = true; 3341 return 0; 3342 } 3343 3344 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3345 { 3346 struct amdgpu_ring *ring = NULL; 3347 int r = 0, i; 3348 3349 if (!amdgpu_async_gfx_ring) 3350 gfx_v12_0_cp_compute_enable(adev, true); 3351 3352 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3353 ring = &adev->gfx.compute_ring[i]; 3354 3355 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3356 if (unlikely(r != 0)) 3357 goto done; 3358 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3359 if (!r) { 3360 r = gfx_v12_0_kcq_init_queue(ring, false); 3361 amdgpu_bo_kunmap(ring->mqd_obj); 3362 ring->mqd_ptr = NULL; 3363 } 3364 amdgpu_bo_unreserve(ring->mqd_obj); 3365 if (r) 3366 goto done; 3367 } 3368 3369 r = amdgpu_gfx_enable_kcq(adev, 0); 3370 done: 3371 return r; 3372 } 3373 3374 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3375 { 3376 int r, i; 3377 struct amdgpu_ring *ring; 3378 3379 if (!(adev->flags & AMD_IS_APU)) 3380 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3381 3382 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3383 /* legacy firmware loading */ 3384 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3385 if (r) 3386 return r; 3387 3388 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3389 if (r) 3390 return r; 3391 } 3392 3393 gfx_v12_0_cp_set_doorbell_range(adev); 3394 3395 if (amdgpu_async_gfx_ring) { 3396 gfx_v12_0_cp_compute_enable(adev, true); 3397 gfx_v12_0_cp_gfx_enable(adev, true); 3398 } 3399 3400 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3401 r = amdgpu_mes_kiq_hw_init(adev); 3402 else 3403 r = gfx_v12_0_kiq_resume(adev); 3404 if (r) 3405 return r; 3406 3407 r = gfx_v12_0_kcq_resume(adev); 3408 if (r) 3409 return r; 3410 3411 if (!amdgpu_async_gfx_ring) { 3412 r = gfx_v12_0_cp_gfx_resume(adev); 3413 if (r) 3414 return r; 3415 } else { 3416 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3417 if (r) 3418 return r; 3419 } 3420 3421 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3422 ring = &adev->gfx.gfx_ring[i]; 3423 r = amdgpu_ring_test_helper(ring); 3424 if (r) 3425 return r; 3426 } 3427 3428 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3429 ring = &adev->gfx.compute_ring[i]; 3430 r = amdgpu_ring_test_helper(ring); 3431 if (r) 3432 return r; 3433 } 3434 3435 return 0; 3436 } 3437 3438 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3439 { 3440 gfx_v12_0_cp_gfx_enable(adev, enable); 3441 gfx_v12_0_cp_compute_enable(adev, enable); 3442 } 3443 3444 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3445 { 3446 int r; 3447 bool value; 3448 3449 r = adev->gfxhub.funcs->gart_enable(adev); 3450 if (r) 3451 return r; 3452 3453 adev->hdp.funcs->flush_hdp(adev, NULL); 3454 3455 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3456 false : true; 3457 3458 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3459 /* TODO investigate why this and the hdp flush above is needed, 3460 * are we missing a flush somewhere else? */ 3461 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3462 3463 return 0; 3464 } 3465 3466 static int get_gb_addr_config(struct amdgpu_device *adev) 3467 { 3468 u32 gb_addr_config; 3469 3470 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3471 if (gb_addr_config == 0) 3472 return -EINVAL; 3473 3474 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3475 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3476 3477 adev->gfx.config.gb_addr_config = gb_addr_config; 3478 3479 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3480 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3481 GB_ADDR_CONFIG, NUM_PIPES); 3482 3483 adev->gfx.config.max_tile_pipes = 3484 adev->gfx.config.gb_addr_config_fields.num_pipes; 3485 3486 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3487 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3488 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3489 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3490 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3491 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3492 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3493 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3494 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3495 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3496 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3497 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3498 3499 return 0; 3500 } 3501 3502 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3503 { 3504 uint32_t data; 3505 3506 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3507 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3508 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3509 3510 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3511 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3512 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3513 } 3514 3515 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3516 { 3517 if (amdgpu_sriov_vf(adev)) 3518 return; 3519 3520 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3521 case IP_VERSION(12, 0, 0): 3522 case IP_VERSION(12, 0, 1): 3523 soc15_program_register_sequence(adev, 3524 golden_settings_gc_12_0, 3525 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3526 3527 if (adev->rev_id == 0) 3528 soc15_program_register_sequence(adev, 3529 golden_settings_gc_12_0_rev0, 3530 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3531 break; 3532 default: 3533 break; 3534 } 3535 } 3536 3537 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3538 { 3539 int r; 3540 struct amdgpu_device *adev = ip_block->adev; 3541 3542 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3543 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3544 /* RLC autoload sequence 1: Program rlc ram */ 3545 if (adev->gfx.imu.funcs->program_rlc_ram) 3546 adev->gfx.imu.funcs->program_rlc_ram(adev); 3547 } 3548 /* rlc autoload firmware */ 3549 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3550 if (r) 3551 return r; 3552 } else { 3553 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3554 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3555 if (adev->gfx.imu.funcs->load_microcode) 3556 adev->gfx.imu.funcs->load_microcode(adev); 3557 if (adev->gfx.imu.funcs->setup_imu) 3558 adev->gfx.imu.funcs->setup_imu(adev); 3559 if (adev->gfx.imu.funcs->start_imu) 3560 adev->gfx.imu.funcs->start_imu(adev); 3561 } 3562 3563 /* disable gpa mode in backdoor loading */ 3564 gfx_v12_0_disable_gpa_mode(adev); 3565 } 3566 } 3567 3568 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3569 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3570 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3571 if (r) { 3572 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3573 return r; 3574 } 3575 } 3576 3577 if (!amdgpu_emu_mode) 3578 gfx_v12_0_init_golden_registers(adev); 3579 3580 adev->gfx.is_poweron = true; 3581 3582 if (get_gb_addr_config(adev)) 3583 DRM_WARN("Invalid gb_addr_config !\n"); 3584 3585 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3586 gfx_v12_0_config_gfx_rs64(adev); 3587 3588 r = gfx_v12_0_gfxhub_enable(adev); 3589 if (r) 3590 return r; 3591 3592 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3593 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3594 (amdgpu_dpm == 1)) { 3595 /** 3596 * For gfx 12, rlc firmware loading relies on smu firmware is 3597 * loaded firstly, so in direct type, it has to load smc ucode 3598 * here before rlc. 3599 */ 3600 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3601 if (r) 3602 return r; 3603 } 3604 3605 gfx_v12_0_constants_init(adev); 3606 3607 if (adev->nbio.funcs->gc_doorbell_init) 3608 adev->nbio.funcs->gc_doorbell_init(adev); 3609 3610 r = gfx_v12_0_rlc_resume(adev); 3611 if (r) 3612 return r; 3613 3614 /* 3615 * init golden registers and rlc resume may override some registers, 3616 * reconfig them here 3617 */ 3618 gfx_v12_0_tcp_harvest(adev); 3619 3620 r = gfx_v12_0_cp_resume(adev); 3621 if (r) 3622 return r; 3623 3624 return r; 3625 } 3626 3627 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3628 { 3629 struct amdgpu_device *adev = ip_block->adev; 3630 uint32_t tmp; 3631 3632 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3633 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3634 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3635 3636 if (!adev->no_hw_access) { 3637 if (amdgpu_async_gfx_ring) { 3638 if (amdgpu_gfx_disable_kgq(adev, 0)) 3639 DRM_ERROR("KGQ disable failed\n"); 3640 } 3641 3642 if (amdgpu_gfx_disable_kcq(adev, 0)) 3643 DRM_ERROR("KCQ disable failed\n"); 3644 3645 amdgpu_mes_kiq_hw_fini(adev); 3646 } 3647 3648 if (amdgpu_sriov_vf(adev)) { 3649 gfx_v12_0_cp_gfx_enable(adev, false); 3650 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3651 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3652 tmp &= 0xffffff00; 3653 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3654 3655 return 0; 3656 } 3657 gfx_v12_0_cp_enable(adev, false); 3658 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3659 3660 adev->gfxhub.funcs->gart_disable(adev); 3661 3662 adev->gfx.is_poweron = false; 3663 3664 return 0; 3665 } 3666 3667 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3668 { 3669 return gfx_v12_0_hw_fini(ip_block); 3670 } 3671 3672 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3673 { 3674 return gfx_v12_0_hw_init(ip_block); 3675 } 3676 3677 static bool gfx_v12_0_is_idle(void *handle) 3678 { 3679 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3680 3681 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3682 GRBM_STATUS, GUI_ACTIVE)) 3683 return false; 3684 else 3685 return true; 3686 } 3687 3688 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3689 { 3690 unsigned i; 3691 u32 tmp; 3692 struct amdgpu_device *adev = ip_block->adev; 3693 3694 for (i = 0; i < adev->usec_timeout; i++) { 3695 /* read MC_STATUS */ 3696 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3697 GRBM_STATUS__GUI_ACTIVE_MASK; 3698 3699 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3700 return 0; 3701 udelay(1); 3702 } 3703 return -ETIMEDOUT; 3704 } 3705 3706 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3707 { 3708 uint64_t clock = 0; 3709 3710 if (adev->smuio.funcs && 3711 adev->smuio.funcs->get_gpu_clock_counter) 3712 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3713 else 3714 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3715 3716 return clock; 3717 } 3718 3719 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3720 { 3721 struct amdgpu_device *adev = ip_block->adev; 3722 3723 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3724 3725 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3726 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3727 AMDGPU_MAX_COMPUTE_RINGS); 3728 3729 gfx_v12_0_set_kiq_pm4_funcs(adev); 3730 gfx_v12_0_set_ring_funcs(adev); 3731 gfx_v12_0_set_irq_funcs(adev); 3732 gfx_v12_0_set_rlc_funcs(adev); 3733 gfx_v12_0_set_mqd_funcs(adev); 3734 gfx_v12_0_set_imu_funcs(adev); 3735 3736 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3737 3738 return gfx_v12_0_init_microcode(adev); 3739 } 3740 3741 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3742 { 3743 struct amdgpu_device *adev = ip_block->adev; 3744 int r; 3745 3746 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3747 if (r) 3748 return r; 3749 3750 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3751 if (r) 3752 return r; 3753 3754 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3755 if (r) 3756 return r; 3757 3758 return 0; 3759 } 3760 3761 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3762 { 3763 uint32_t rlc_cntl; 3764 3765 /* if RLC is not enabled, do nothing */ 3766 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3767 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3768 } 3769 3770 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3771 int xcc_id) 3772 { 3773 uint32_t data; 3774 unsigned i; 3775 3776 data = RLC_SAFE_MODE__CMD_MASK; 3777 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3778 3779 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3780 3781 /* wait for RLC_SAFE_MODE */ 3782 for (i = 0; i < adev->usec_timeout; i++) { 3783 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3784 RLC_SAFE_MODE, CMD)) 3785 break; 3786 udelay(1); 3787 } 3788 } 3789 3790 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3791 int xcc_id) 3792 { 3793 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3794 } 3795 3796 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3797 bool enable) 3798 { 3799 uint32_t def, data; 3800 3801 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3802 return; 3803 3804 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3805 3806 if (enable) 3807 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3808 else 3809 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3810 3811 if (def != data) 3812 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3813 } 3814 3815 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3816 struct amdgpu_ring *ring, 3817 unsigned vmid) 3818 { 3819 u32 reg, data; 3820 3821 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3822 if (amdgpu_sriov_is_pp_one_vf(adev)) 3823 data = RREG32_NO_KIQ(reg); 3824 else 3825 data = RREG32(reg); 3826 3827 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3828 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3829 3830 if (amdgpu_sriov_is_pp_one_vf(adev)) 3831 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3832 else 3833 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3834 3835 if (ring 3836 && amdgpu_sriov_is_pp_one_vf(adev) 3837 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3838 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3839 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3840 amdgpu_ring_emit_wreg(ring, reg, data); 3841 } 3842 } 3843 3844 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3845 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3846 .set_safe_mode = gfx_v12_0_set_safe_mode, 3847 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3848 .init = gfx_v12_0_rlc_init, 3849 .get_csb_size = gfx_v12_0_get_csb_size, 3850 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3851 .resume = gfx_v12_0_rlc_resume, 3852 .stop = gfx_v12_0_rlc_stop, 3853 .reset = gfx_v12_0_rlc_reset, 3854 .start = gfx_v12_0_rlc_start, 3855 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3856 }; 3857 3858 #if 0 3859 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3860 { 3861 /* TODO */ 3862 } 3863 3864 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3865 { 3866 /* TODO */ 3867 } 3868 #endif 3869 3870 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3871 enum amd_powergating_state state) 3872 { 3873 struct amdgpu_device *adev = ip_block->adev; 3874 bool enable = (state == AMD_PG_STATE_GATE); 3875 3876 if (amdgpu_sriov_vf(adev)) 3877 return 0; 3878 3879 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3880 case IP_VERSION(12, 0, 0): 3881 case IP_VERSION(12, 0, 1): 3882 amdgpu_gfx_off_ctrl(adev, enable); 3883 break; 3884 default: 3885 break; 3886 } 3887 3888 return 0; 3889 } 3890 3891 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3892 bool enable) 3893 { 3894 uint32_t def, data; 3895 3896 if (!(adev->cg_flags & 3897 (AMD_CG_SUPPORT_GFX_CGCG | 3898 AMD_CG_SUPPORT_GFX_CGLS | 3899 AMD_CG_SUPPORT_GFX_3D_CGCG | 3900 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3901 return; 3902 3903 if (enable) { 3904 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3905 3906 /* unset CGCG override */ 3907 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3908 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3909 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3910 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3911 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3912 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3913 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3914 3915 /* update CGCG override bits */ 3916 if (def != data) 3917 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3918 3919 /* enable cgcg FSM(0x0000363F) */ 3920 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3921 3922 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3923 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3924 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3925 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3926 } 3927 3928 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3929 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3930 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3931 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3932 } 3933 3934 if (def != data) 3935 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3936 3937 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3938 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3939 3940 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3941 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3942 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3943 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3944 } 3945 3946 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3947 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3948 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3949 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3950 } 3951 3952 if (def != data) 3953 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3954 3955 /* set IDLE_POLL_COUNT(0x00900100) */ 3956 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3957 3958 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3959 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3960 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3961 3962 if (def != data) 3963 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3964 3965 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3966 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3967 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3968 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3969 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3970 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3971 3972 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3973 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3974 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3975 3976 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3977 if (adev->sdma.num_instances > 1) { 3978 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3979 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3980 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3981 } 3982 } else { 3983 /* Program RLC_CGCG_CGLS_CTRL */ 3984 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3985 3986 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3987 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3988 3989 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3990 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3991 3992 if (def != data) 3993 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3994 3995 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3996 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3997 3998 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 3999 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4000 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4001 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4002 4003 if (def != data) 4004 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4005 4006 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4007 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4008 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4009 4010 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4011 if (adev->sdma.num_instances > 1) { 4012 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4013 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4014 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4015 } 4016 } 4017 } 4018 4019 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4020 bool enable) 4021 { 4022 uint32_t data, def; 4023 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4024 return; 4025 4026 /* It is disabled by HW by default */ 4027 if (enable) { 4028 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4029 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4030 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4031 4032 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4033 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4034 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4035 4036 if (def != data) 4037 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4038 } 4039 } else { 4040 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4041 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4042 4043 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4044 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4045 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4046 4047 if (def != data) 4048 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4049 } 4050 } 4051 } 4052 4053 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4054 bool enable) 4055 { 4056 uint32_t def, data; 4057 4058 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4059 return; 4060 4061 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4062 4063 if (enable) 4064 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4065 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4066 else 4067 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4068 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4069 4070 if (def != data) 4071 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4072 } 4073 4074 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4075 bool enable) 4076 { 4077 uint32_t def, data; 4078 4079 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4080 return; 4081 4082 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4083 4084 if (enable) 4085 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4086 else 4087 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4088 4089 if (def != data) 4090 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4091 } 4092 4093 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4094 bool enable) 4095 { 4096 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4097 4098 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4099 4100 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4101 4102 gfx_v12_0_update_repeater_fgcg(adev, enable); 4103 4104 gfx_v12_0_update_sram_fgcg(adev, enable); 4105 4106 gfx_v12_0_update_perf_clk(adev, enable); 4107 4108 if (adev->cg_flags & 4109 (AMD_CG_SUPPORT_GFX_MGCG | 4110 AMD_CG_SUPPORT_GFX_CGLS | 4111 AMD_CG_SUPPORT_GFX_CGCG | 4112 AMD_CG_SUPPORT_GFX_3D_CGCG | 4113 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4114 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4115 4116 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4117 4118 return 0; 4119 } 4120 4121 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4122 enum amd_clockgating_state state) 4123 { 4124 struct amdgpu_device *adev = ip_block->adev; 4125 4126 if (amdgpu_sriov_vf(adev)) 4127 return 0; 4128 4129 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4130 case IP_VERSION(12, 0, 0): 4131 case IP_VERSION(12, 0, 1): 4132 gfx_v12_0_update_gfx_clock_gating(adev, 4133 state == AMD_CG_STATE_GATE); 4134 break; 4135 default: 4136 break; 4137 } 4138 4139 return 0; 4140 } 4141 4142 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 4143 { 4144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4145 int data; 4146 4147 /* AMD_CG_SUPPORT_GFX_MGCG */ 4148 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4149 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4150 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4151 4152 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4153 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4154 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4155 4156 /* AMD_CG_SUPPORT_GFX_FGCG */ 4157 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4158 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4159 4160 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4161 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4162 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4163 4164 /* AMD_CG_SUPPORT_GFX_CGCG */ 4165 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4166 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4167 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4168 4169 /* AMD_CG_SUPPORT_GFX_CGLS */ 4170 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4171 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4172 4173 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4174 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4175 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4176 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4177 4178 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4179 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4180 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4181 } 4182 4183 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4184 { 4185 /* gfx12 is 32bit rptr*/ 4186 return *(uint32_t *)ring->rptr_cpu_addr; 4187 } 4188 4189 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4190 { 4191 struct amdgpu_device *adev = ring->adev; 4192 u64 wptr; 4193 4194 /* XXX check if swapping is necessary on BE */ 4195 if (ring->use_doorbell) { 4196 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4197 } else { 4198 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4199 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4200 } 4201 4202 return wptr; 4203 } 4204 4205 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4206 { 4207 struct amdgpu_device *adev = ring->adev; 4208 uint32_t *wptr_saved; 4209 uint32_t *is_queue_unmap; 4210 uint64_t aggregated_db_index; 4211 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4212 uint64_t wptr_tmp; 4213 4214 if (ring->is_mes_queue) { 4215 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4216 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4217 sizeof(uint32_t)); 4218 aggregated_db_index = 4219 amdgpu_mes_get_aggregated_doorbell_index(adev, 4220 ring->hw_prio); 4221 4222 wptr_tmp = ring->wptr & ring->buf_mask; 4223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4224 *wptr_saved = wptr_tmp; 4225 /* assume doorbell always being used by mes mapped queue */ 4226 if (*is_queue_unmap) { 4227 WDOORBELL64(aggregated_db_index, wptr_tmp); 4228 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4229 } else { 4230 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4231 4232 if (*is_queue_unmap) 4233 WDOORBELL64(aggregated_db_index, wptr_tmp); 4234 } 4235 } else { 4236 if (ring->use_doorbell) { 4237 /* XXX check if swapping is necessary on BE */ 4238 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4239 ring->wptr); 4240 WDOORBELL64(ring->doorbell_index, ring->wptr); 4241 } else { 4242 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4243 lower_32_bits(ring->wptr)); 4244 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4245 upper_32_bits(ring->wptr)); 4246 } 4247 } 4248 } 4249 4250 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4251 { 4252 /* gfx12 hardware is 32bit rptr */ 4253 return *(uint32_t *)ring->rptr_cpu_addr; 4254 } 4255 4256 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4257 { 4258 u64 wptr; 4259 4260 /* XXX check if swapping is necessary on BE */ 4261 if (ring->use_doorbell) 4262 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4263 else 4264 BUG(); 4265 return wptr; 4266 } 4267 4268 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4269 { 4270 struct amdgpu_device *adev = ring->adev; 4271 uint32_t *wptr_saved; 4272 uint32_t *is_queue_unmap; 4273 uint64_t aggregated_db_index; 4274 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4275 uint64_t wptr_tmp; 4276 4277 if (ring->is_mes_queue) { 4278 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4279 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4280 sizeof(uint32_t)); 4281 aggregated_db_index = 4282 amdgpu_mes_get_aggregated_doorbell_index(adev, 4283 ring->hw_prio); 4284 4285 wptr_tmp = ring->wptr & ring->buf_mask; 4286 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4287 *wptr_saved = wptr_tmp; 4288 /* assume doorbell always used by mes mapped queue */ 4289 if (*is_queue_unmap) { 4290 WDOORBELL64(aggregated_db_index, wptr_tmp); 4291 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4292 } else { 4293 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4294 4295 if (*is_queue_unmap) 4296 WDOORBELL64(aggregated_db_index, wptr_tmp); 4297 } 4298 } else { 4299 /* XXX check if swapping is necessary on BE */ 4300 if (ring->use_doorbell) { 4301 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4302 ring->wptr); 4303 WDOORBELL64(ring->doorbell_index, ring->wptr); 4304 } else { 4305 BUG(); /* only DOORBELL method supported on gfx12 now */ 4306 } 4307 } 4308 } 4309 4310 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4311 { 4312 struct amdgpu_device *adev = ring->adev; 4313 u32 ref_and_mask, reg_mem_engine; 4314 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4315 4316 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4317 switch (ring->me) { 4318 case 1: 4319 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4320 break; 4321 case 2: 4322 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4323 break; 4324 default: 4325 return; 4326 } 4327 reg_mem_engine = 0; 4328 } else { 4329 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4330 reg_mem_engine = 1; /* pfp */ 4331 } 4332 4333 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4334 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4335 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4336 ref_and_mask, ref_and_mask, 0x20); 4337 } 4338 4339 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4340 struct amdgpu_job *job, 4341 struct amdgpu_ib *ib, 4342 uint32_t flags) 4343 { 4344 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4345 u32 header, control = 0; 4346 4347 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4348 4349 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4350 4351 control |= ib->length_dw | (vmid << 24); 4352 4353 if (ring->is_mes_queue) 4354 /* inherit vmid from mqd */ 4355 control |= 0x400000; 4356 4357 amdgpu_ring_write(ring, header); 4358 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4359 amdgpu_ring_write(ring, 4360 #ifdef __BIG_ENDIAN 4361 (2 << 0) | 4362 #endif 4363 lower_32_bits(ib->gpu_addr)); 4364 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4365 amdgpu_ring_write(ring, control); 4366 } 4367 4368 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4369 struct amdgpu_job *job, 4370 struct amdgpu_ib *ib, 4371 uint32_t flags) 4372 { 4373 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4374 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4375 4376 if (ring->is_mes_queue) 4377 /* inherit vmid from mqd */ 4378 control |= 0x40000000; 4379 4380 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4381 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4382 amdgpu_ring_write(ring, 4383 #ifdef __BIG_ENDIAN 4384 (2 << 0) | 4385 #endif 4386 lower_32_bits(ib->gpu_addr)); 4387 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4388 amdgpu_ring_write(ring, control); 4389 } 4390 4391 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4392 u64 seq, unsigned flags) 4393 { 4394 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4395 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4396 4397 /* RELEASE_MEM - flush caches, send int */ 4398 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4399 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4400 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4401 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4402 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4403 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4404 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4405 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4406 4407 /* 4408 * the address should be Qword aligned if 64bit write, Dword 4409 * aligned if only send 32bit data low (discard data high) 4410 */ 4411 if (write64bit) 4412 BUG_ON(addr & 0x7); 4413 else 4414 BUG_ON(addr & 0x3); 4415 amdgpu_ring_write(ring, lower_32_bits(addr)); 4416 amdgpu_ring_write(ring, upper_32_bits(addr)); 4417 amdgpu_ring_write(ring, lower_32_bits(seq)); 4418 amdgpu_ring_write(ring, upper_32_bits(seq)); 4419 amdgpu_ring_write(ring, ring->is_mes_queue ? 4420 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4421 } 4422 4423 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4424 { 4425 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4426 uint32_t seq = ring->fence_drv.sync_seq; 4427 uint64_t addr = ring->fence_drv.gpu_addr; 4428 4429 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4430 upper_32_bits(addr), seq, 0xffffffff, 4); 4431 } 4432 4433 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4434 uint16_t pasid, uint32_t flush_type, 4435 bool all_hub, uint8_t dst_sel) 4436 { 4437 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4438 amdgpu_ring_write(ring, 4439 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4440 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4441 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4442 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4443 } 4444 4445 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4446 unsigned vmid, uint64_t pd_addr) 4447 { 4448 if (ring->is_mes_queue) 4449 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4450 else 4451 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4452 4453 /* compute doesn't have PFP */ 4454 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4455 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4456 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4457 amdgpu_ring_write(ring, 0x0); 4458 } 4459 } 4460 4461 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4462 u64 seq, unsigned int flags) 4463 { 4464 struct amdgpu_device *adev = ring->adev; 4465 4466 /* we only allocate 32bit for each seq wb address */ 4467 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4468 4469 /* write fence seq to the "addr" */ 4470 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4471 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4472 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4473 amdgpu_ring_write(ring, lower_32_bits(addr)); 4474 amdgpu_ring_write(ring, upper_32_bits(addr)); 4475 amdgpu_ring_write(ring, lower_32_bits(seq)); 4476 4477 if (flags & AMDGPU_FENCE_FLAG_INT) { 4478 /* set register to trigger INT */ 4479 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4480 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4481 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4482 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4483 amdgpu_ring_write(ring, 0); 4484 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4485 } 4486 } 4487 4488 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4489 uint32_t flags) 4490 { 4491 uint32_t dw2 = 0; 4492 4493 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4494 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4495 /* set load_global_config & load_global_uconfig */ 4496 dw2 |= 0x8001; 4497 /* set load_cs_sh_regs */ 4498 dw2 |= 0x01000000; 4499 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4500 dw2 |= 0x10002; 4501 } 4502 4503 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4504 amdgpu_ring_write(ring, dw2); 4505 amdgpu_ring_write(ring, 0); 4506 } 4507 4508 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4509 uint64_t addr) 4510 { 4511 unsigned ret; 4512 4513 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4514 amdgpu_ring_write(ring, lower_32_bits(addr)); 4515 amdgpu_ring_write(ring, upper_32_bits(addr)); 4516 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4517 amdgpu_ring_write(ring, 0); 4518 ret = ring->wptr & ring->buf_mask; 4519 /* patch dummy value later */ 4520 amdgpu_ring_write(ring, 0); 4521 4522 return ret; 4523 } 4524 4525 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4526 { 4527 int i, r = 0; 4528 struct amdgpu_device *adev = ring->adev; 4529 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4530 struct amdgpu_ring *kiq_ring = &kiq->ring; 4531 unsigned long flags; 4532 4533 if (adev->enable_mes) 4534 return -EINVAL; 4535 4536 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4537 return -EINVAL; 4538 4539 spin_lock_irqsave(&kiq->ring_lock, flags); 4540 4541 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4542 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4543 return -ENOMEM; 4544 } 4545 4546 /* assert preemption condition */ 4547 amdgpu_ring_set_preempt_cond_exec(ring, false); 4548 4549 /* assert IB preemption, emit the trailing fence */ 4550 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4551 ring->trail_fence_gpu_addr, 4552 ++ring->trail_seq); 4553 amdgpu_ring_commit(kiq_ring); 4554 4555 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4556 4557 /* poll the trailing fence */ 4558 for (i = 0; i < adev->usec_timeout; i++) { 4559 if (ring->trail_seq == 4560 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4561 break; 4562 udelay(1); 4563 } 4564 4565 if (i >= adev->usec_timeout) { 4566 r = -EINVAL; 4567 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4568 } 4569 4570 /* deassert preemption condition */ 4571 amdgpu_ring_set_preempt_cond_exec(ring, true); 4572 return r; 4573 } 4574 4575 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4576 bool start, 4577 bool secure) 4578 { 4579 uint32_t v = secure ? FRAME_TMZ : 0; 4580 4581 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4582 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4583 } 4584 4585 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4586 uint32_t reg_val_offs) 4587 { 4588 struct amdgpu_device *adev = ring->adev; 4589 4590 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4591 amdgpu_ring_write(ring, 0 | /* src: register*/ 4592 (5 << 8) | /* dst: memory */ 4593 (1 << 20)); /* write confirm */ 4594 amdgpu_ring_write(ring, reg); 4595 amdgpu_ring_write(ring, 0); 4596 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4597 reg_val_offs * 4)); 4598 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4599 reg_val_offs * 4)); 4600 } 4601 4602 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4603 uint32_t reg, 4604 uint32_t val) 4605 { 4606 uint32_t cmd = 0; 4607 4608 switch (ring->funcs->type) { 4609 case AMDGPU_RING_TYPE_GFX: 4610 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4611 break; 4612 case AMDGPU_RING_TYPE_KIQ: 4613 cmd = (1 << 16); /* no inc addr */ 4614 break; 4615 default: 4616 cmd = WR_CONFIRM; 4617 break; 4618 } 4619 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4620 amdgpu_ring_write(ring, cmd); 4621 amdgpu_ring_write(ring, reg); 4622 amdgpu_ring_write(ring, 0); 4623 amdgpu_ring_write(ring, val); 4624 } 4625 4626 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4627 uint32_t val, uint32_t mask) 4628 { 4629 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4630 } 4631 4632 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4633 uint32_t reg0, uint32_t reg1, 4634 uint32_t ref, uint32_t mask) 4635 { 4636 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4637 4638 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4639 ref, mask, 0x20); 4640 } 4641 4642 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4643 unsigned vmid) 4644 { 4645 struct amdgpu_device *adev = ring->adev; 4646 uint32_t value = 0; 4647 4648 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4649 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4650 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4651 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4652 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4653 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4654 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4655 } 4656 4657 static void 4658 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4659 uint32_t me, uint32_t pipe, 4660 enum amdgpu_interrupt_state state) 4661 { 4662 uint32_t cp_int_cntl, cp_int_cntl_reg; 4663 4664 if (!me) { 4665 switch (pipe) { 4666 case 0: 4667 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4668 break; 4669 default: 4670 DRM_DEBUG("invalid pipe %d\n", pipe); 4671 return; 4672 } 4673 } else { 4674 DRM_DEBUG("invalid me %d\n", me); 4675 return; 4676 } 4677 4678 switch (state) { 4679 case AMDGPU_IRQ_STATE_DISABLE: 4680 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4681 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4682 TIME_STAMP_INT_ENABLE, 0); 4683 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4684 GENERIC0_INT_ENABLE, 0); 4685 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4686 break; 4687 case AMDGPU_IRQ_STATE_ENABLE: 4688 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4689 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4690 TIME_STAMP_INT_ENABLE, 1); 4691 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4692 GENERIC0_INT_ENABLE, 1); 4693 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4694 break; 4695 default: 4696 break; 4697 } 4698 } 4699 4700 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4701 int me, int pipe, 4702 enum amdgpu_interrupt_state state) 4703 { 4704 u32 mec_int_cntl, mec_int_cntl_reg; 4705 4706 /* 4707 * amdgpu controls only the first MEC. That's why this function only 4708 * handles the setting of interrupts for this specific MEC. All other 4709 * pipes' interrupts are set by amdkfd. 4710 */ 4711 4712 if (me == 1) { 4713 switch (pipe) { 4714 case 0: 4715 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4716 break; 4717 case 1: 4718 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4719 break; 4720 default: 4721 DRM_DEBUG("invalid pipe %d\n", pipe); 4722 return; 4723 } 4724 } else { 4725 DRM_DEBUG("invalid me %d\n", me); 4726 return; 4727 } 4728 4729 switch (state) { 4730 case AMDGPU_IRQ_STATE_DISABLE: 4731 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4732 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4733 TIME_STAMP_INT_ENABLE, 0); 4734 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4735 GENERIC0_INT_ENABLE, 0); 4736 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4737 break; 4738 case AMDGPU_IRQ_STATE_ENABLE: 4739 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4740 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4741 TIME_STAMP_INT_ENABLE, 1); 4742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4743 GENERIC0_INT_ENABLE, 1); 4744 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4745 break; 4746 default: 4747 break; 4748 } 4749 } 4750 4751 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4752 struct amdgpu_irq_src *src, 4753 unsigned type, 4754 enum amdgpu_interrupt_state state) 4755 { 4756 switch (type) { 4757 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4758 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4759 break; 4760 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4761 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4762 break; 4763 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4764 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4765 break; 4766 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4767 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4768 break; 4769 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4770 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4771 break; 4772 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4773 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4774 break; 4775 default: 4776 break; 4777 } 4778 return 0; 4779 } 4780 4781 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4782 struct amdgpu_irq_src *source, 4783 struct amdgpu_iv_entry *entry) 4784 { 4785 int i; 4786 u8 me_id, pipe_id, queue_id; 4787 struct amdgpu_ring *ring; 4788 uint32_t mes_queue_id = entry->src_data[0]; 4789 4790 DRM_DEBUG("IH: CP EOP\n"); 4791 4792 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4793 struct amdgpu_mes_queue *queue; 4794 4795 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4796 4797 spin_lock(&adev->mes.queue_id_lock); 4798 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4799 if (queue) { 4800 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4801 amdgpu_fence_process(queue->ring); 4802 } 4803 spin_unlock(&adev->mes.queue_id_lock); 4804 } else { 4805 me_id = (entry->ring_id & 0x0c) >> 2; 4806 pipe_id = (entry->ring_id & 0x03) >> 0; 4807 queue_id = (entry->ring_id & 0x70) >> 4; 4808 4809 switch (me_id) { 4810 case 0: 4811 if (pipe_id == 0) 4812 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4813 else 4814 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4815 break; 4816 case 1: 4817 case 2: 4818 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4819 ring = &adev->gfx.compute_ring[i]; 4820 /* Per-queue interrupt is supported for MEC starting from VI. 4821 * The interrupt can only be enabled/disabled per pipe instead 4822 * of per queue. 4823 */ 4824 if ((ring->me == me_id) && 4825 (ring->pipe == pipe_id) && 4826 (ring->queue == queue_id)) 4827 amdgpu_fence_process(ring); 4828 } 4829 break; 4830 } 4831 } 4832 4833 return 0; 4834 } 4835 4836 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4837 struct amdgpu_irq_src *source, 4838 unsigned int type, 4839 enum amdgpu_interrupt_state state) 4840 { 4841 u32 cp_int_cntl_reg, cp_int_cntl; 4842 int i, j; 4843 4844 switch (state) { 4845 case AMDGPU_IRQ_STATE_DISABLE: 4846 case AMDGPU_IRQ_STATE_ENABLE: 4847 for (i = 0; i < adev->gfx.me.num_me; i++) { 4848 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4849 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4850 4851 if (cp_int_cntl_reg) { 4852 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4853 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4854 PRIV_REG_INT_ENABLE, 4855 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4856 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4857 } 4858 } 4859 } 4860 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4861 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4862 /* MECs start at 1 */ 4863 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4864 4865 if (cp_int_cntl_reg) { 4866 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4867 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4868 PRIV_REG_INT_ENABLE, 4869 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4870 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4871 } 4872 } 4873 } 4874 break; 4875 default: 4876 break; 4877 } 4878 4879 return 0; 4880 } 4881 4882 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4883 struct amdgpu_irq_src *source, 4884 unsigned type, 4885 enum amdgpu_interrupt_state state) 4886 { 4887 u32 cp_int_cntl_reg, cp_int_cntl; 4888 int i, j; 4889 4890 switch (state) { 4891 case AMDGPU_IRQ_STATE_DISABLE: 4892 case AMDGPU_IRQ_STATE_ENABLE: 4893 for (i = 0; i < adev->gfx.me.num_me; i++) { 4894 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4895 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4896 4897 if (cp_int_cntl_reg) { 4898 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4899 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4900 OPCODE_ERROR_INT_ENABLE, 4901 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4902 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4903 } 4904 } 4905 } 4906 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4907 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4908 /* MECs start at 1 */ 4909 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4910 4911 if (cp_int_cntl_reg) { 4912 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4913 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4914 OPCODE_ERROR_INT_ENABLE, 4915 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4916 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4917 } 4918 } 4919 } 4920 break; 4921 default: 4922 break; 4923 } 4924 return 0; 4925 } 4926 4927 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4928 struct amdgpu_irq_src *source, 4929 unsigned int type, 4930 enum amdgpu_interrupt_state state) 4931 { 4932 u32 cp_int_cntl_reg, cp_int_cntl; 4933 int i, j; 4934 4935 switch (state) { 4936 case AMDGPU_IRQ_STATE_DISABLE: 4937 case AMDGPU_IRQ_STATE_ENABLE: 4938 for (i = 0; i < adev->gfx.me.num_me; i++) { 4939 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4940 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4941 4942 if (cp_int_cntl_reg) { 4943 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4944 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4945 PRIV_INSTR_INT_ENABLE, 4946 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4947 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4948 } 4949 } 4950 } 4951 break; 4952 default: 4953 break; 4954 } 4955 4956 return 0; 4957 } 4958 4959 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4960 struct amdgpu_iv_entry *entry) 4961 { 4962 u8 me_id, pipe_id, queue_id; 4963 struct amdgpu_ring *ring; 4964 int i; 4965 4966 me_id = (entry->ring_id & 0x0c) >> 2; 4967 pipe_id = (entry->ring_id & 0x03) >> 0; 4968 queue_id = (entry->ring_id & 0x70) >> 4; 4969 4970 switch (me_id) { 4971 case 0: 4972 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4973 ring = &adev->gfx.gfx_ring[i]; 4974 if (ring->me == me_id && ring->pipe == pipe_id && 4975 ring->queue == queue_id) 4976 drm_sched_fault(&ring->sched); 4977 } 4978 break; 4979 case 1: 4980 case 2: 4981 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4982 ring = &adev->gfx.compute_ring[i]; 4983 if (ring->me == me_id && ring->pipe == pipe_id && 4984 ring->queue == queue_id) 4985 drm_sched_fault(&ring->sched); 4986 } 4987 break; 4988 default: 4989 BUG(); 4990 break; 4991 } 4992 } 4993 4994 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 4995 struct amdgpu_irq_src *source, 4996 struct amdgpu_iv_entry *entry) 4997 { 4998 DRM_ERROR("Illegal register access in command stream\n"); 4999 gfx_v12_0_handle_priv_fault(adev, entry); 5000 return 0; 5001 } 5002 5003 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5004 struct amdgpu_irq_src *source, 5005 struct amdgpu_iv_entry *entry) 5006 { 5007 DRM_ERROR("Illegal opcode in command stream \n"); 5008 gfx_v12_0_handle_priv_fault(adev, entry); 5009 return 0; 5010 } 5011 5012 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5013 struct amdgpu_irq_src *source, 5014 struct amdgpu_iv_entry *entry) 5015 { 5016 DRM_ERROR("Illegal instruction in command stream\n"); 5017 gfx_v12_0_handle_priv_fault(adev, entry); 5018 return 0; 5019 } 5020 5021 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5022 { 5023 const unsigned int gcr_cntl = 5024 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5025 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5026 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5027 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5028 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5029 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5030 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5031 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5032 5033 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5034 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5035 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5036 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5037 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5038 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5039 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5040 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5041 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5042 } 5043 5044 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5045 { 5046 /* Header itself is a NOP packet */ 5047 if (num_nop == 1) { 5048 amdgpu_ring_write(ring, ring->funcs->nop); 5049 return; 5050 } 5051 5052 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5053 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5054 5055 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5056 amdgpu_ring_insert_nop(ring, num_nop - 1); 5057 } 5058 5059 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5060 { 5061 /* Emit the cleaner shader */ 5062 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5063 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5064 } 5065 5066 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5067 { 5068 struct amdgpu_device *adev = ip_block->adev; 5069 uint32_t i, j, k, reg, index = 0; 5070 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5071 5072 if (!adev->gfx.ip_dump_core) 5073 return; 5074 5075 for (i = 0; i < reg_count; i++) 5076 drm_printf(p, "%-50s \t 0x%08x\n", 5077 gc_reg_list_12_0[i].reg_name, 5078 adev->gfx.ip_dump_core[i]); 5079 5080 /* print compute queue registers for all instances */ 5081 if (!adev->gfx.ip_dump_compute_queues) 5082 return; 5083 5084 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5085 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5086 adev->gfx.mec.num_mec, 5087 adev->gfx.mec.num_pipe_per_mec, 5088 adev->gfx.mec.num_queue_per_pipe); 5089 5090 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5091 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5092 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5093 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5094 for (reg = 0; reg < reg_count; reg++) { 5095 drm_printf(p, "%-50s \t 0x%08x\n", 5096 gc_cp_reg_list_12[reg].reg_name, 5097 adev->gfx.ip_dump_compute_queues[index + reg]); 5098 } 5099 index += reg_count; 5100 } 5101 } 5102 } 5103 5104 /* print gfx queue registers for all instances */ 5105 if (!adev->gfx.ip_dump_gfx_queues) 5106 return; 5107 5108 index = 0; 5109 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5110 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5111 adev->gfx.me.num_me, 5112 adev->gfx.me.num_pipe_per_me, 5113 adev->gfx.me.num_queue_per_pipe); 5114 5115 for (i = 0; i < adev->gfx.me.num_me; i++) { 5116 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5117 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5118 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5119 for (reg = 0; reg < reg_count; reg++) { 5120 drm_printf(p, "%-50s \t 0x%08x\n", 5121 gc_gfx_queue_reg_list_12[reg].reg_name, 5122 adev->gfx.ip_dump_gfx_queues[index + reg]); 5123 } 5124 index += reg_count; 5125 } 5126 } 5127 } 5128 } 5129 5130 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5131 { 5132 struct amdgpu_device *adev = ip_block->adev; 5133 uint32_t i, j, k, reg, index = 0; 5134 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5135 5136 if (!adev->gfx.ip_dump_core) 5137 return; 5138 5139 amdgpu_gfx_off_ctrl(adev, false); 5140 for (i = 0; i < reg_count; i++) 5141 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5142 amdgpu_gfx_off_ctrl(adev, true); 5143 5144 /* dump compute queue registers for all instances */ 5145 if (!adev->gfx.ip_dump_compute_queues) 5146 return; 5147 5148 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5149 amdgpu_gfx_off_ctrl(adev, false); 5150 mutex_lock(&adev->srbm_mutex); 5151 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5152 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5153 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5154 /* ME0 is for GFX so start from 1 for CP */ 5155 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5156 for (reg = 0; reg < reg_count; reg++) { 5157 adev->gfx.ip_dump_compute_queues[index + reg] = 5158 RREG32(SOC15_REG_ENTRY_OFFSET( 5159 gc_cp_reg_list_12[reg])); 5160 } 5161 index += reg_count; 5162 } 5163 } 5164 } 5165 soc24_grbm_select(adev, 0, 0, 0, 0); 5166 mutex_unlock(&adev->srbm_mutex); 5167 amdgpu_gfx_off_ctrl(adev, true); 5168 5169 /* dump gfx queue registers for all instances */ 5170 if (!adev->gfx.ip_dump_gfx_queues) 5171 return; 5172 5173 index = 0; 5174 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5175 amdgpu_gfx_off_ctrl(adev, false); 5176 mutex_lock(&adev->srbm_mutex); 5177 for (i = 0; i < adev->gfx.me.num_me; i++) { 5178 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5179 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5180 soc24_grbm_select(adev, i, j, k, 0); 5181 5182 for (reg = 0; reg < reg_count; reg++) { 5183 adev->gfx.ip_dump_gfx_queues[index + reg] = 5184 RREG32(SOC15_REG_ENTRY_OFFSET( 5185 gc_gfx_queue_reg_list_12[reg])); 5186 } 5187 index += reg_count; 5188 } 5189 } 5190 } 5191 soc24_grbm_select(adev, 0, 0, 0, 0); 5192 mutex_unlock(&adev->srbm_mutex); 5193 amdgpu_gfx_off_ctrl(adev, true); 5194 } 5195 5196 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5197 { 5198 struct amdgpu_device *adev = ring->adev; 5199 int r; 5200 5201 if (amdgpu_sriov_vf(adev)) 5202 return -EINVAL; 5203 5204 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5205 if (r) { 5206 dev_err(adev->dev, "reset via MES failed %d\n", r); 5207 return r; 5208 } 5209 5210 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5211 if (unlikely(r != 0)) { 5212 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5213 return r; 5214 } 5215 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5216 if (!r) { 5217 r = gfx_v12_0_kgq_init_queue(ring, true); 5218 amdgpu_bo_kunmap(ring->mqd_obj); 5219 ring->mqd_ptr = NULL; 5220 } 5221 amdgpu_bo_unreserve(ring->mqd_obj); 5222 if (r) { 5223 DRM_ERROR("fail to unresv mqd_obj\n"); 5224 return r; 5225 } 5226 5227 r = amdgpu_mes_map_legacy_queue(adev, ring); 5228 if (r) { 5229 dev_err(adev->dev, "failed to remap kgq\n"); 5230 return r; 5231 } 5232 5233 return amdgpu_ring_test_ring(ring); 5234 } 5235 5236 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5237 { 5238 struct amdgpu_device *adev = ring->adev; 5239 int r; 5240 5241 if (amdgpu_sriov_vf(adev)) 5242 return -EINVAL; 5243 5244 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5245 if (r) { 5246 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5247 return r; 5248 } 5249 5250 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5251 if (unlikely(r != 0)) { 5252 DRM_ERROR("fail to resv mqd_obj\n"); 5253 return r; 5254 } 5255 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5256 if (!r) { 5257 r = gfx_v12_0_kcq_init_queue(ring, true); 5258 amdgpu_bo_kunmap(ring->mqd_obj); 5259 ring->mqd_ptr = NULL; 5260 } 5261 amdgpu_bo_unreserve(ring->mqd_obj); 5262 if (r) { 5263 DRM_ERROR("fail to unresv mqd_obj\n"); 5264 return r; 5265 } 5266 r = amdgpu_mes_map_legacy_queue(adev, ring); 5267 if (r) { 5268 dev_err(adev->dev, "failed to remap kcq\n"); 5269 return r; 5270 } 5271 5272 return amdgpu_ring_test_ring(ring); 5273 } 5274 5275 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5276 .name = "gfx_v12_0", 5277 .early_init = gfx_v12_0_early_init, 5278 .late_init = gfx_v12_0_late_init, 5279 .sw_init = gfx_v12_0_sw_init, 5280 .sw_fini = gfx_v12_0_sw_fini, 5281 .hw_init = gfx_v12_0_hw_init, 5282 .hw_fini = gfx_v12_0_hw_fini, 5283 .suspend = gfx_v12_0_suspend, 5284 .resume = gfx_v12_0_resume, 5285 .is_idle = gfx_v12_0_is_idle, 5286 .wait_for_idle = gfx_v12_0_wait_for_idle, 5287 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5288 .set_powergating_state = gfx_v12_0_set_powergating_state, 5289 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5290 .dump_ip_state = gfx_v12_ip_dump, 5291 .print_ip_state = gfx_v12_ip_print, 5292 }; 5293 5294 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5295 .type = AMDGPU_RING_TYPE_GFX, 5296 .align_mask = 0xff, 5297 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5298 .support_64bit_ptrs = true, 5299 .secure_submission_supported = true, 5300 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5301 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5302 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5303 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5304 5 + /* COND_EXEC */ 5305 7 + /* PIPELINE_SYNC */ 5306 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5307 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5308 2 + /* VM_FLUSH */ 5309 8 + /* FENCE for VM_FLUSH */ 5310 5 + /* COND_EXEC */ 5311 7 + /* HDP_flush */ 5312 4 + /* VGT_flush */ 5313 31 + /* DE_META */ 5314 3 + /* CNTX_CTRL */ 5315 5 + /* HDP_INVL */ 5316 8 + 8 + /* FENCE x2 */ 5317 8 + /* gfx_v12_0_emit_mem_sync */ 5318 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5319 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5320 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5321 .emit_fence = gfx_v12_0_ring_emit_fence, 5322 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5323 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5324 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5325 .test_ring = gfx_v12_0_ring_test_ring, 5326 .test_ib = gfx_v12_0_ring_test_ib, 5327 .insert_nop = gfx_v12_ring_insert_nop, 5328 .pad_ib = amdgpu_ring_generic_pad_ib, 5329 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5330 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5331 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5332 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5333 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5334 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5335 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5336 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5337 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5338 .reset = gfx_v12_0_reset_kgq, 5339 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5340 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5341 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5342 }; 5343 5344 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5345 .type = AMDGPU_RING_TYPE_COMPUTE, 5346 .align_mask = 0xff, 5347 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5348 .support_64bit_ptrs = true, 5349 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5350 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5351 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5352 .emit_frame_size = 5353 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5354 5 + /* hdp invalidate */ 5355 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5356 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5357 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5358 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5359 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5360 8 + /* gfx_v12_0_emit_mem_sync */ 5361 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5362 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5363 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5364 .emit_fence = gfx_v12_0_ring_emit_fence, 5365 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5366 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5367 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5368 .test_ring = gfx_v12_0_ring_test_ring, 5369 .test_ib = gfx_v12_0_ring_test_ib, 5370 .insert_nop = gfx_v12_ring_insert_nop, 5371 .pad_ib = amdgpu_ring_generic_pad_ib, 5372 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5373 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5374 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5375 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5376 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5377 .reset = gfx_v12_0_reset_kcq, 5378 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5379 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5380 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5381 }; 5382 5383 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5384 .type = AMDGPU_RING_TYPE_KIQ, 5385 .align_mask = 0xff, 5386 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5387 .support_64bit_ptrs = true, 5388 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5389 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5390 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5391 .emit_frame_size = 5392 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5393 5 + /*hdp invalidate */ 5394 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5395 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5396 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5397 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5398 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5399 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5400 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5401 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5402 .test_ring = gfx_v12_0_ring_test_ring, 5403 .test_ib = gfx_v12_0_ring_test_ib, 5404 .insert_nop = amdgpu_ring_insert_nop, 5405 .pad_ib = amdgpu_ring_generic_pad_ib, 5406 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5407 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5408 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5409 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5410 }; 5411 5412 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5413 { 5414 int i; 5415 5416 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5417 5418 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5419 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5420 5421 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5422 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5423 } 5424 5425 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5426 .set = gfx_v12_0_set_eop_interrupt_state, 5427 .process = gfx_v12_0_eop_irq, 5428 }; 5429 5430 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5431 .set = gfx_v12_0_set_priv_reg_fault_state, 5432 .process = gfx_v12_0_priv_reg_irq, 5433 }; 5434 5435 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5436 .set = gfx_v12_0_set_bad_op_fault_state, 5437 .process = gfx_v12_0_bad_op_irq, 5438 }; 5439 5440 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5441 .set = gfx_v12_0_set_priv_inst_fault_state, 5442 .process = gfx_v12_0_priv_inst_irq, 5443 }; 5444 5445 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5446 { 5447 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5448 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5449 5450 adev->gfx.priv_reg_irq.num_types = 1; 5451 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5452 5453 adev->gfx.bad_op_irq.num_types = 1; 5454 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5455 5456 adev->gfx.priv_inst_irq.num_types = 1; 5457 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5458 } 5459 5460 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5461 { 5462 if (adev->flags & AMD_IS_APU) 5463 adev->gfx.imu.mode = MISSION_MODE; 5464 else 5465 adev->gfx.imu.mode = DEBUG_MODE; 5466 5467 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5468 } 5469 5470 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5471 { 5472 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5473 } 5474 5475 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5476 { 5477 /* set gfx eng mqd */ 5478 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5479 sizeof(struct v12_gfx_mqd); 5480 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5481 gfx_v12_0_gfx_mqd_init; 5482 /* set compute eng mqd */ 5483 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5484 sizeof(struct v12_compute_mqd); 5485 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5486 gfx_v12_0_compute_mqd_init; 5487 } 5488 5489 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5490 u32 bitmap) 5491 { 5492 u32 data; 5493 5494 if (!bitmap) 5495 return; 5496 5497 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5498 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5499 5500 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5501 } 5502 5503 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5504 { 5505 u32 data, wgp_bitmask; 5506 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5507 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5508 5509 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5510 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5511 5512 wgp_bitmask = 5513 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5514 5515 return (~data) & wgp_bitmask; 5516 } 5517 5518 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5519 { 5520 u32 wgp_idx, wgp_active_bitmap; 5521 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5522 5523 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5524 cu_active_bitmap = 0; 5525 5526 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5527 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5528 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5529 if (wgp_active_bitmap & (1 << wgp_idx)) 5530 cu_active_bitmap |= cu_bitmap_per_wgp; 5531 } 5532 5533 return cu_active_bitmap; 5534 } 5535 5536 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5537 struct amdgpu_cu_info *cu_info) 5538 { 5539 int i, j, k, counter, active_cu_number = 0; 5540 u32 mask, bitmap; 5541 unsigned disable_masks[8 * 2]; 5542 5543 if (!adev || !cu_info) 5544 return -EINVAL; 5545 5546 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5547 5548 mutex_lock(&adev->grbm_idx_mutex); 5549 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5550 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5551 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5552 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5553 continue; 5554 mask = 1; 5555 counter = 0; 5556 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5557 if (i < 8 && j < 2) 5558 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5559 adev, disable_masks[i * 2 + j]); 5560 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5561 5562 /** 5563 * GFX12 could support more than 4 SEs, while the bitmap 5564 * in cu_info struct is 4x4 and ioctl interface struct 5565 * drm_amdgpu_info_device should keep stable. 5566 * So we use last two columns of bitmap to store cu mask for 5567 * SEs 4 to 7, the layout of the bitmap is as below: 5568 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5569 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5570 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5571 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5572 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5573 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5574 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5575 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5576 */ 5577 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5578 5579 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5580 if (bitmap & mask) 5581 counter++; 5582 5583 mask <<= 1; 5584 } 5585 active_cu_number += counter; 5586 } 5587 } 5588 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5589 mutex_unlock(&adev->grbm_idx_mutex); 5590 5591 cu_info->number = active_cu_number; 5592 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5593 5594 return 0; 5595 } 5596 5597 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5598 .type = AMD_IP_BLOCK_TYPE_GFX, 5599 .major = 12, 5600 .minor = 0, 5601 .rev = 0, 5602 .funcs = &gfx_v12_0_ip_funcs, 5603 }; 5604