1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 282 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 283 uint32_t val); 284 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 285 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 286 uint16_t pasid, uint32_t flush_type, 287 bool all_hub, uint8_t dst_sel); 288 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 291 bool enable); 292 293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 294 uint64_t queue_mask) 295 { 296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 304 amdgpu_ring_write(kiq_ring, 0); 305 } 306 307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 308 struct amdgpu_ring *ring) 309 { 310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 311 uint64_t wptr_addr = ring->wptr_gpu_addr; 312 uint32_t me = 0, eng_sel = 0; 313 314 switch (ring->funcs->type) { 315 case AMDGPU_RING_TYPE_COMPUTE: 316 me = 1; 317 eng_sel = 0; 318 break; 319 case AMDGPU_RING_TYPE_GFX: 320 me = 0; 321 eng_sel = 4; 322 break; 323 case AMDGPU_RING_TYPE_MES: 324 me = 2; 325 eng_sel = 5; 326 break; 327 default: 328 WARN_ON(1); 329 } 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 338 PACKET3_MAP_QUEUES_ME((me)) | 339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 348 } 349 350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 351 struct amdgpu_ring *ring, 352 enum amdgpu_unmap_queues_action action, 353 u64 gpu_addr, u64 seq) 354 { 355 struct amdgpu_device *adev = kiq_ring->adev; 356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 357 358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 360 return; 361 } 362 363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 365 PACKET3_UNMAP_QUEUES_ACTION(action) | 366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 369 amdgpu_ring_write(kiq_ring, 370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 371 372 if (action == PREEMPT_QUEUES_NO_UNMAP) { 373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, seq); 376 } else { 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 } 381 } 382 383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 384 struct amdgpu_ring *ring, 385 u64 addr, u64 seq) 386 { 387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 388 389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 390 amdgpu_ring_write(kiq_ring, 391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 393 PACKET3_QUERY_STATUS_COMMAND(2)); 394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 401 } 402 403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 404 uint16_t pasid, 405 uint32_t flush_type, 406 bool all_hub) 407 { 408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 409 } 410 411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 412 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 413 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 415 .kiq_query_status = gfx_v12_0_kiq_query_status, 416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 417 .set_resources_size = 8, 418 .map_queues_size = 7, 419 .unmap_queues_size = 6, 420 .query_status_size = 7, 421 .invalidate_tlbs_size = 2, 422 }; 423 424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 425 { 426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 427 } 428 429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 430 int mem_space, int opt, uint32_t addr0, 431 uint32_t addr1, uint32_t ref, 432 uint32_t mask, uint32_t inv) 433 { 434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 435 amdgpu_ring_write(ring, 436 /* memory (1) or register (0) */ 437 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 438 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 439 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 440 WAIT_REG_MEM_ENGINE(eng_sel))); 441 442 if (mem_space) 443 BUG_ON(addr0 & 0x3); /* Dword align */ 444 amdgpu_ring_write(ring, addr0); 445 amdgpu_ring_write(ring, addr1); 446 amdgpu_ring_write(ring, ref); 447 amdgpu_ring_write(ring, mask); 448 amdgpu_ring_write(ring, inv); /* poll interval */ 449 } 450 451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 455 uint32_t tmp = 0; 456 unsigned i; 457 int r; 458 459 WREG32(scratch, 0xCAFEDEAD); 460 r = amdgpu_ring_alloc(ring, 5); 461 if (r) { 462 dev_err(adev->dev, 463 "amdgpu: cp failed to lock ring %d (%d).\n", 464 ring->idx, r); 465 return r; 466 } 467 468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 470 } else { 471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 472 amdgpu_ring_write(ring, scratch - 473 PACKET3_SET_UCONFIG_REG_START); 474 amdgpu_ring_write(ring, 0xDEADBEEF); 475 } 476 amdgpu_ring_commit(ring); 477 478 for (i = 0; i < adev->usec_timeout; i++) { 479 tmp = RREG32(scratch); 480 if (tmp == 0xDEADBEEF) 481 break; 482 if (amdgpu_emu_mode == 1) 483 msleep(1); 484 else 485 udelay(1); 486 } 487 488 if (i >= adev->usec_timeout) 489 r = -ETIMEDOUT; 490 return r; 491 } 492 493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 494 { 495 struct amdgpu_device *adev = ring->adev; 496 struct amdgpu_ib ib; 497 struct dma_fence *f = NULL; 498 unsigned index; 499 uint64_t gpu_addr; 500 volatile uint32_t *cpu_ptr; 501 long r; 502 503 /* MES KIQ fw hasn't indirect buffer support for now */ 504 if (adev->enable_mes_kiq && 505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 506 return 0; 507 508 memset(&ib, 0, sizeof(ib)); 509 510 r = amdgpu_device_wb_get(adev, &index); 511 if (r) 512 return r; 513 514 gpu_addr = adev->wb.gpu_addr + (index * 4); 515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 516 cpu_ptr = &adev->wb.wb[index]; 517 518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 519 if (r) { 520 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 521 goto err1; 522 } 523 524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 526 ib.ptr[2] = lower_32_bits(gpu_addr); 527 ib.ptr[3] = upper_32_bits(gpu_addr); 528 ib.ptr[4] = 0xDEADBEEF; 529 ib.length_dw = 5; 530 531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 532 if (r) 533 goto err2; 534 535 r = dma_fence_wait_timeout(f, false, timeout); 536 if (r == 0) { 537 r = -ETIMEDOUT; 538 goto err2; 539 } else if (r < 0) { 540 goto err2; 541 } 542 543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 544 r = 0; 545 else 546 r = -EINVAL; 547 err2: 548 amdgpu_ib_free(&ib, NULL); 549 dma_fence_put(f); 550 err1: 551 amdgpu_device_wb_free(adev, index); 552 return r; 553 } 554 555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 556 { 557 amdgpu_ucode_release(&adev->gfx.pfp_fw); 558 amdgpu_ucode_release(&adev->gfx.me_fw); 559 amdgpu_ucode_release(&adev->gfx.rlc_fw); 560 amdgpu_ucode_release(&adev->gfx.mec_fw); 561 562 kfree(adev->gfx.rlc.register_list_format); 563 } 564 565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 566 { 567 const struct psp_firmware_header_v1_0 *toc_hdr; 568 int err = 0; 569 570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_toc.bin", ucode_prefix); 573 if (err) 574 goto out; 575 576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 582 return 0; 583 out: 584 amdgpu_ucode_release(&adev->psp.toc_fw); 585 return err; 586 } 587 588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 589 { 590 char ucode_prefix[30]; 591 int err; 592 const struct rlc_firmware_header_v2_0 *rlc_hdr; 593 uint16_t version_major; 594 uint16_t version_minor; 595 596 DRM_DEBUG("\n"); 597 598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 599 600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 601 AMDGPU_UCODE_REQUIRED, 602 "amdgpu/%s_pfp.bin", ucode_prefix); 603 if (err) 604 goto out; 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 607 608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 609 AMDGPU_UCODE_REQUIRED, 610 "amdgpu/%s_me.bin", ucode_prefix); 611 if (err) 612 goto out; 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 615 616 if (!amdgpu_sriov_vf(adev)) { 617 if (amdgpu_is_kicker_fw(adev)) 618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 619 AMDGPU_UCODE_REQUIRED, 620 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 621 else 622 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 623 AMDGPU_UCODE_REQUIRED, 624 "amdgpu/%s_rlc.bin", ucode_prefix); 625 if (err) 626 goto out; 627 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 628 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 629 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 630 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 631 if (err) 632 goto out; 633 } 634 635 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 636 AMDGPU_UCODE_REQUIRED, 637 "amdgpu/%s_mec.bin", ucode_prefix); 638 if (err) 639 goto out; 640 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 643 644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 645 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 646 647 /* only one MEC for gfx 12 */ 648 adev->gfx.mec2_fw = NULL; 649 650 if (adev->gfx.imu.funcs) { 651 if (adev->gfx.imu.funcs->init_microcode) { 652 err = adev->gfx.imu.funcs->init_microcode(adev); 653 if (err) 654 dev_err(adev->dev, "Failed to load imu firmware!\n"); 655 } 656 } 657 658 out: 659 if (err) { 660 amdgpu_ucode_release(&adev->gfx.pfp_fw); 661 amdgpu_ucode_release(&adev->gfx.me_fw); 662 amdgpu_ucode_release(&adev->gfx.rlc_fw); 663 amdgpu_ucode_release(&adev->gfx.mec_fw); 664 } 665 666 return err; 667 } 668 669 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 670 { 671 u32 count = 0; 672 const struct cs_section_def *sect = NULL; 673 const struct cs_extent_def *ext = NULL; 674 675 count += 1; 676 677 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 678 if (sect->id == SECT_CONTEXT) { 679 for (ext = sect->section; ext->extent != NULL; ++ext) 680 count += 2 + ext->reg_count; 681 } else 682 return 0; 683 } 684 685 return count; 686 } 687 688 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 689 volatile u32 *buffer) 690 { 691 u32 count = 0, clustercount = 0, i; 692 const struct cs_section_def *sect = NULL; 693 const struct cs_extent_def *ext = NULL; 694 695 if (adev->gfx.rlc.cs_data == NULL) 696 return; 697 if (buffer == NULL) 698 return; 699 700 count += 1; 701 702 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 703 if (sect->id == SECT_CONTEXT) { 704 for (ext = sect->section; ext->extent != NULL; ++ext) { 705 clustercount++; 706 buffer[count++] = ext->reg_count; 707 buffer[count++] = ext->reg_index; 708 709 for (i = 0; i < ext->reg_count; i++) 710 buffer[count++] = cpu_to_le32(ext->extent[i]); 711 } 712 } else 713 return; 714 } 715 716 buffer[0] = clustercount; 717 } 718 719 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 720 { 721 /* clear state block */ 722 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 723 &adev->gfx.rlc.clear_state_gpu_addr, 724 (void **)&adev->gfx.rlc.cs_ptr); 725 726 /* jump table block */ 727 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 728 &adev->gfx.rlc.cp_table_gpu_addr, 729 (void **)&adev->gfx.rlc.cp_table_ptr); 730 } 731 732 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 733 { 734 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 735 736 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 737 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 738 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 739 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 740 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 741 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 742 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 743 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 744 adev->gfx.rlc.rlcg_reg_access_supported = true; 745 } 746 747 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 748 { 749 const struct cs_section_def *cs_data; 750 int r; 751 752 adev->gfx.rlc.cs_data = gfx12_cs_data; 753 754 cs_data = adev->gfx.rlc.cs_data; 755 756 if (cs_data) { 757 /* init clear state block */ 758 r = amdgpu_gfx_rlc_init_csb(adev); 759 if (r) 760 return r; 761 } 762 763 /* init spm vmid with 0xf */ 764 if (adev->gfx.rlc.funcs->update_spm_vmid) 765 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 766 767 return 0; 768 } 769 770 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 771 { 772 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 774 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 775 } 776 777 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 778 { 779 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 780 781 amdgpu_gfx_graphics_queue_acquire(adev); 782 } 783 784 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 785 { 786 int r; 787 u32 *hpd; 788 size_t mec_hpd_size; 789 790 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 791 792 /* take ownership of the relevant compute queues */ 793 amdgpu_gfx_compute_queue_acquire(adev); 794 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 795 796 if (mec_hpd_size) { 797 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 798 AMDGPU_GEM_DOMAIN_GTT, 799 &adev->gfx.mec.hpd_eop_obj, 800 &adev->gfx.mec.hpd_eop_gpu_addr, 801 (void **)&hpd); 802 if (r) { 803 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 804 gfx_v12_0_mec_fini(adev); 805 return r; 806 } 807 808 memset(hpd, 0, mec_hpd_size); 809 810 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 811 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 812 } 813 814 return 0; 815 } 816 817 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 818 { 819 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 820 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 821 (address << SQ_IND_INDEX__INDEX__SHIFT)); 822 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 823 } 824 825 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 826 uint32_t thread, uint32_t regno, 827 uint32_t num, uint32_t *out) 828 { 829 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 830 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 831 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 832 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 833 (SQ_IND_INDEX__AUTO_INCR_MASK)); 834 while (num--) 835 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 836 } 837 838 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 839 uint32_t xcc_id, 840 uint32_t simd, uint32_t wave, 841 uint32_t *dst, int *no_fields) 842 { 843 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 844 * field when performing a select_se_sh so it should be 845 * zero here */ 846 WARN_ON(simd != 0); 847 848 /* type 4 wave data */ 849 dst[(*no_fields)++] = 4; 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 873 } 874 875 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 876 uint32_t xcc_id, uint32_t simd, 877 uint32_t wave, uint32_t start, 878 uint32_t size, uint32_t *dst) 879 { 880 WARN_ON(simd != 0); 881 882 wave_read_regs( 883 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 884 dst); 885 } 886 887 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 888 uint32_t xcc_id, uint32_t simd, 889 uint32_t wave, uint32_t thread, 890 uint32_t start, uint32_t size, 891 uint32_t *dst) 892 { 893 wave_read_regs( 894 adev, wave, thread, 895 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 896 } 897 898 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 899 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 900 { 901 soc24_grbm_select(adev, me, pipe, q, vm); 902 } 903 904 /* all sizes are in bytes */ 905 #define MQD_SHADOW_BASE_SIZE 73728 906 #define MQD_SHADOW_BASE_ALIGNMENT 256 907 #define MQD_FWWORKAREA_SIZE 484 908 #define MQD_FWWORKAREA_ALIGNMENT 256 909 910 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 911 struct amdgpu_gfx_shadow_info *shadow_info) 912 { 913 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 914 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 915 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 916 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 917 } 918 919 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 920 struct amdgpu_gfx_shadow_info *shadow_info, 921 bool skip_check) 922 { 923 if (adev->gfx.cp_gfx_shadow || skip_check) { 924 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 925 return 0; 926 } 927 928 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 929 return -EINVAL; 930 } 931 932 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 933 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 934 .select_se_sh = &gfx_v12_0_select_se_sh, 935 .read_wave_data = &gfx_v12_0_read_wave_data, 936 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 937 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 938 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 939 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 940 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 941 }; 942 943 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 944 { 945 946 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 947 case IP_VERSION(12, 0, 0): 948 case IP_VERSION(12, 0, 1): 949 adev->gfx.config.max_hw_contexts = 8; 950 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 951 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 952 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 953 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 954 break; 955 default: 956 BUG(); 957 break; 958 } 959 960 return 0; 961 } 962 963 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 964 int me, int pipe, int queue) 965 { 966 int r; 967 struct amdgpu_ring *ring; 968 unsigned int irq_type; 969 970 ring = &adev->gfx.gfx_ring[ring_id]; 971 972 ring->me = me; 973 ring->pipe = pipe; 974 ring->queue = queue; 975 976 ring->ring_obj = NULL; 977 ring->use_doorbell = true; 978 979 if (!ring_id) 980 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 981 else 982 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 983 ring->vm_hub = AMDGPU_GFXHUB(0); 984 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 985 986 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 987 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 988 AMDGPU_RING_PRIO_DEFAULT, NULL); 989 if (r) 990 return r; 991 return 0; 992 } 993 994 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 995 int mec, int pipe, int queue) 996 { 997 int r; 998 unsigned irq_type; 999 struct amdgpu_ring *ring; 1000 unsigned int hw_prio; 1001 1002 ring = &adev->gfx.compute_ring[ring_id]; 1003 1004 /* mec0 is me1 */ 1005 ring->me = mec + 1; 1006 ring->pipe = pipe; 1007 ring->queue = queue; 1008 1009 ring->ring_obj = NULL; 1010 ring->use_doorbell = true; 1011 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1012 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1013 + (ring_id * GFX12_MEC_HPD_SIZE); 1014 ring->vm_hub = AMDGPU_GFXHUB(0); 1015 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1016 1017 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1018 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1019 + ring->pipe; 1020 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1021 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1022 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1023 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1024 hw_prio, NULL); 1025 if (r) 1026 return r; 1027 1028 return 0; 1029 } 1030 1031 static struct { 1032 SOC24_FIRMWARE_ID id; 1033 unsigned int offset; 1034 unsigned int size; 1035 unsigned int size_x16; 1036 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1037 1038 #define RLC_TOC_OFFSET_DWUNIT 8 1039 #define RLC_SIZE_MULTIPLE 1024 1040 #define RLC_TOC_UMF_SIZE_inM 23ULL 1041 #define RLC_TOC_FORMAT_API 165ULL 1042 1043 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1044 { 1045 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1046 1047 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1048 rlc_autoload_info[ucode->id].id = ucode->id; 1049 rlc_autoload_info[ucode->id].offset = 1050 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1051 rlc_autoload_info[ucode->id].size = 1052 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1053 ucode->size * 4; 1054 ucode++; 1055 } 1056 } 1057 1058 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1059 { 1060 uint32_t total_size = 0; 1061 SOC24_FIRMWARE_ID id; 1062 1063 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1064 1065 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1066 total_size += rlc_autoload_info[id].size; 1067 1068 /* In case the offset in rlc toc ucode is aligned */ 1069 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1070 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1071 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1072 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1073 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1074 1075 return total_size; 1076 } 1077 1078 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1079 { 1080 int r; 1081 uint32_t total_size; 1082 1083 total_size = gfx_v12_0_calc_toc_total_size(adev); 1084 1085 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1086 AMDGPU_GEM_DOMAIN_VRAM, 1087 &adev->gfx.rlc.rlc_autoload_bo, 1088 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1089 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1090 1091 if (r) { 1092 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1093 return r; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1100 SOC24_FIRMWARE_ID id, 1101 const void *fw_data, 1102 uint32_t fw_size) 1103 { 1104 uint32_t toc_offset; 1105 uint32_t toc_fw_size; 1106 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1107 1108 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1109 return; 1110 1111 toc_offset = rlc_autoload_info[id].offset; 1112 toc_fw_size = rlc_autoload_info[id].size; 1113 1114 if (fw_size == 0) 1115 fw_size = toc_fw_size; 1116 1117 if (fw_size > toc_fw_size) 1118 fw_size = toc_fw_size; 1119 1120 memcpy(ptr + toc_offset, fw_data, fw_size); 1121 1122 if (fw_size < toc_fw_size) 1123 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1124 } 1125 1126 static void 1127 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1128 { 1129 void *data; 1130 uint32_t size; 1131 uint32_t *toc_ptr; 1132 1133 data = adev->psp.toc.start_addr; 1134 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1135 1136 toc_ptr = (uint32_t *)data + size / 4 - 2; 1137 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1138 1139 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1140 data, size); 1141 } 1142 1143 static void 1144 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1145 { 1146 const __le32 *fw_data; 1147 uint32_t fw_size; 1148 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1149 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1150 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1151 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1152 uint16_t version_major, version_minor; 1153 1154 /* pfp ucode */ 1155 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1156 adev->gfx.pfp_fw->data; 1157 /* instruction */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1162 fw_data, fw_size); 1163 /* data */ 1164 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1165 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1166 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1168 fw_data, fw_size); 1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1170 fw_data, fw_size); 1171 /* me ucode */ 1172 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1173 adev->gfx.me_fw->data; 1174 /* instruction */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1179 fw_data, fw_size); 1180 /* data */ 1181 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1182 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1183 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1185 fw_data, fw_size); 1186 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1187 fw_data, fw_size); 1188 /* mec ucode */ 1189 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1190 adev->gfx.mec_fw->data; 1191 /* instruction */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1196 fw_data, fw_size); 1197 /* data */ 1198 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1199 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1200 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1202 fw_data, fw_size); 1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1204 fw_data, fw_size); 1205 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1206 fw_data, fw_size); 1207 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1208 fw_data, fw_size); 1209 1210 /* rlc ucode */ 1211 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1212 adev->gfx.rlc_fw->data; 1213 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1214 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1215 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1217 fw_data, fw_size); 1218 1219 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1220 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1221 if (version_major == 2) { 1222 if (version_minor >= 1) { 1223 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1229 fw_data, fw_size); 1230 1231 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1232 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1233 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1234 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1235 fw_data, fw_size); 1236 } 1237 if (version_minor >= 2) { 1238 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1244 fw_data, fw_size); 1245 1246 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1247 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1248 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1250 fw_data, fw_size); 1251 } 1252 } 1253 } 1254 1255 static void 1256 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1257 { 1258 const __le32 *fw_data; 1259 uint32_t fw_size; 1260 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1261 1262 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1263 adev->sdma.instance[0].fw->data; 1264 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1265 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1266 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1267 1268 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1269 fw_data, fw_size); 1270 } 1271 1272 static void 1273 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1274 { 1275 const __le32 *fw_data; 1276 unsigned fw_size; 1277 const struct mes_firmware_header_v1_0 *mes_hdr; 1278 int pipe, ucode_id, data_id; 1279 1280 for (pipe = 0; pipe < 2; pipe++) { 1281 if (pipe == 0) { 1282 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1283 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1284 } else { 1285 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1286 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1287 } 1288 1289 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1290 adev->mes.fw[pipe]->data; 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1297 1298 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1299 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1300 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1301 1302 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1303 } 1304 } 1305 1306 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1307 { 1308 uint32_t rlc_g_offset, rlc_g_size; 1309 uint64_t gpu_addr; 1310 uint32_t data; 1311 1312 /* RLC autoload sequence 2: copy ucode */ 1313 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1314 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1315 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1316 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1317 1318 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1319 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1320 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1321 1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1323 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1324 1325 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1326 1327 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1328 /* RLC autoload sequence 3: load IMU fw */ 1329 if (adev->gfx.imu.funcs->load_microcode) 1330 adev->gfx.imu.funcs->load_microcode(adev); 1331 /* RLC autoload sequence 4 init IMU fw */ 1332 if (adev->gfx.imu.funcs->setup_imu) 1333 adev->gfx.imu.funcs->setup_imu(adev); 1334 if (adev->gfx.imu.funcs->start_imu) 1335 adev->gfx.imu.funcs->start_imu(adev); 1336 1337 /* RLC autoload sequence 5 disable gpa mode */ 1338 gfx_v12_0_disable_gpa_mode(adev); 1339 } else { 1340 /* unhalt rlc to start autoload without imu */ 1341 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1342 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1343 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1344 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1345 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1346 } 1347 1348 return 0; 1349 } 1350 1351 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1352 { 1353 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1354 uint32_t *ptr; 1355 uint32_t inst; 1356 1357 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1358 if (!ptr) { 1359 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1360 adev->gfx.ip_dump_core = NULL; 1361 } else { 1362 adev->gfx.ip_dump_core = ptr; 1363 } 1364 1365 /* Allocate memory for compute queue registers for all the instances */ 1366 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1367 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1368 adev->gfx.mec.num_queue_per_pipe; 1369 1370 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1371 if (!ptr) { 1372 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1373 adev->gfx.ip_dump_compute_queues = NULL; 1374 } else { 1375 adev->gfx.ip_dump_compute_queues = ptr; 1376 } 1377 1378 /* Allocate memory for gfx queue registers for all the instances */ 1379 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1380 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1381 adev->gfx.me.num_queue_per_pipe; 1382 1383 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1384 if (!ptr) { 1385 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1386 adev->gfx.ip_dump_gfx_queues = NULL; 1387 } else { 1388 adev->gfx.ip_dump_gfx_queues = ptr; 1389 } 1390 } 1391 1392 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1393 { 1394 int i, j, k, r, ring_id = 0; 1395 unsigned num_compute_rings; 1396 int xcc_id = 0; 1397 struct amdgpu_device *adev = ip_block->adev; 1398 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1399 1400 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1401 1402 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1403 case IP_VERSION(12, 0, 0): 1404 case IP_VERSION(12, 0, 1): 1405 adev->gfx.me.num_me = 1; 1406 adev->gfx.me.num_pipe_per_me = 1; 1407 adev->gfx.me.num_queue_per_pipe = 8; 1408 adev->gfx.mec.num_mec = 1; 1409 adev->gfx.mec.num_pipe_per_mec = 2; 1410 adev->gfx.mec.num_queue_per_pipe = 4; 1411 break; 1412 default: 1413 adev->gfx.me.num_me = 1; 1414 adev->gfx.me.num_pipe_per_me = 1; 1415 adev->gfx.me.num_queue_per_pipe = 1; 1416 adev->gfx.mec.num_mec = 1; 1417 adev->gfx.mec.num_pipe_per_mec = 4; 1418 adev->gfx.mec.num_queue_per_pipe = 8; 1419 break; 1420 } 1421 1422 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1423 case IP_VERSION(12, 0, 0): 1424 case IP_VERSION(12, 0, 1): 1425 if (!adev->gfx.disable_uq && 1426 adev->gfx.me_fw_version >= 2780 && 1427 adev->gfx.pfp_fw_version >= 2840 && 1428 adev->gfx.mec_fw_version >= 3050 && 1429 adev->mes.fw_version[0] >= 123) { 1430 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1431 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1432 } 1433 break; 1434 default: 1435 break; 1436 } 1437 1438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1439 case IP_VERSION(12, 0, 0): 1440 case IP_VERSION(12, 0, 1): 1441 if (adev->gfx.me_fw_version >= 2480 && 1442 adev->gfx.pfp_fw_version >= 2530 && 1443 adev->gfx.mec_fw_version >= 2680 && 1444 adev->mes.fw_version[0] >= 100) 1445 adev->gfx.enable_cleaner_shader = true; 1446 break; 1447 default: 1448 adev->gfx.enable_cleaner_shader = false; 1449 break; 1450 } 1451 1452 if (adev->gfx.num_compute_rings) { 1453 /* recalculate compute rings to use based on hardware configuration */ 1454 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1455 adev->gfx.mec.num_queue_per_pipe) / 2; 1456 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1457 num_compute_rings); 1458 } 1459 1460 /* EOP Event */ 1461 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1462 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1463 &adev->gfx.eop_irq); 1464 if (r) 1465 return r; 1466 1467 /* Bad opcode Event */ 1468 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1469 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1470 &adev->gfx.bad_op_irq); 1471 if (r) 1472 return r; 1473 1474 /* Privileged reg */ 1475 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1476 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1477 &adev->gfx.priv_reg_irq); 1478 if (r) 1479 return r; 1480 1481 /* Privileged inst */ 1482 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1483 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1484 &adev->gfx.priv_inst_irq); 1485 if (r) 1486 return r; 1487 1488 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1489 1490 gfx_v12_0_me_init(adev); 1491 1492 r = gfx_v12_0_rlc_init(adev); 1493 if (r) { 1494 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1495 return r; 1496 } 1497 1498 r = gfx_v12_0_mec_init(adev); 1499 if (r) { 1500 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1501 return r; 1502 } 1503 1504 if (adev->gfx.num_gfx_rings) { 1505 /* set up the gfx ring */ 1506 for (i = 0; i < adev->gfx.me.num_me; i++) { 1507 for (j = 0; j < num_queue_per_pipe; j++) { 1508 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1509 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1510 continue; 1511 1512 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1513 i, k, j); 1514 if (r) 1515 return r; 1516 ring_id++; 1517 } 1518 } 1519 } 1520 } 1521 1522 if (adev->gfx.num_compute_rings) { 1523 ring_id = 0; 1524 /* set up the compute queues - allocate horizontally across pipes */ 1525 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1526 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1527 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1528 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1529 0, i, k, j)) 1530 continue; 1531 1532 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1533 i, k, j); 1534 if (r) 1535 return r; 1536 1537 ring_id++; 1538 } 1539 } 1540 } 1541 } 1542 1543 adev->gfx.gfx_supported_reset = 1544 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1545 adev->gfx.compute_supported_reset = 1546 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1547 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1548 case IP_VERSION(12, 0, 0): 1549 case IP_VERSION(12, 0, 1): 1550 if ((adev->gfx.me_fw_version >= 2660) && 1551 (adev->gfx.mec_fw_version >= 2920) && 1552 !amdgpu_sriov_vf(adev)) { 1553 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1554 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1555 } 1556 break; 1557 default: 1558 break; 1559 } 1560 1561 if (!adev->enable_mes_kiq) { 1562 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1563 if (r) { 1564 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1565 return r; 1566 } 1567 1568 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1569 if (r) 1570 return r; 1571 } 1572 1573 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1574 if (r) 1575 return r; 1576 1577 /* allocate visible FB for rlc auto-loading fw */ 1578 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1579 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1580 if (r) 1581 return r; 1582 } 1583 1584 r = gfx_v12_0_gpu_early_init(adev); 1585 if (r) 1586 return r; 1587 1588 gfx_v12_0_alloc_ip_dump(adev); 1589 1590 r = amdgpu_gfx_sysfs_init(adev); 1591 if (r) 1592 return r; 1593 1594 return 0; 1595 } 1596 1597 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1598 { 1599 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1600 &adev->gfx.pfp.pfp_fw_gpu_addr, 1601 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1602 1603 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1604 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1605 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1606 } 1607 1608 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1609 { 1610 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1611 &adev->gfx.me.me_fw_gpu_addr, 1612 (void **)&adev->gfx.me.me_fw_ptr); 1613 1614 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1615 &adev->gfx.me.me_fw_data_gpu_addr, 1616 (void **)&adev->gfx.me.me_fw_data_ptr); 1617 } 1618 1619 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1620 { 1621 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1622 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1623 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1624 } 1625 1626 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1627 { 1628 int i; 1629 struct amdgpu_device *adev = ip_block->adev; 1630 1631 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1632 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1633 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1634 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1635 1636 amdgpu_gfx_mqd_sw_fini(adev, 0); 1637 1638 if (!adev->enable_mes_kiq) { 1639 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1640 amdgpu_gfx_kiq_fini(adev, 0); 1641 } 1642 1643 gfx_v12_0_pfp_fini(adev); 1644 gfx_v12_0_me_fini(adev); 1645 gfx_v12_0_rlc_fini(adev); 1646 gfx_v12_0_mec_fini(adev); 1647 1648 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1649 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1650 1651 gfx_v12_0_free_microcode(adev); 1652 1653 amdgpu_gfx_sysfs_fini(adev); 1654 1655 kfree(adev->gfx.ip_dump_core); 1656 kfree(adev->gfx.ip_dump_compute_queues); 1657 kfree(adev->gfx.ip_dump_gfx_queues); 1658 1659 return 0; 1660 } 1661 1662 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1663 u32 sh_num, u32 instance, int xcc_id) 1664 { 1665 u32 data; 1666 1667 if (instance == 0xffffffff) 1668 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1669 INSTANCE_BROADCAST_WRITES, 1); 1670 else 1671 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1672 instance); 1673 1674 if (se_num == 0xffffffff) 1675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1676 1); 1677 else 1678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1679 1680 if (sh_num == 0xffffffff) 1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1682 1); 1683 else 1684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1685 1686 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1687 } 1688 1689 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1690 { 1691 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1692 1693 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1694 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1695 GRBM_CC_GC_SA_UNIT_DISABLE, 1696 SA_DISABLE); 1697 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1698 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1699 GRBM_GC_USER_SA_UNIT_DISABLE, 1700 SA_DISABLE); 1701 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1702 adev->gfx.config.max_shader_engines); 1703 1704 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1705 } 1706 1707 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1708 { 1709 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1710 u32 rb_mask; 1711 1712 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1713 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1714 CC_RB_BACKEND_DISABLE, 1715 BACKEND_DISABLE); 1716 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1717 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1718 GC_USER_RB_BACKEND_DISABLE, 1719 BACKEND_DISABLE); 1720 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1721 adev->gfx.config.max_shader_engines); 1722 1723 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1724 } 1725 1726 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1727 { 1728 u32 rb_bitmap_per_sa; 1729 u32 rb_bitmap_width_per_sa; 1730 u32 max_sa; 1731 u32 active_sa_bitmap; 1732 u32 global_active_rb_bitmap; 1733 u32 active_rb_bitmap = 0; 1734 u32 i; 1735 1736 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1737 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1738 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1739 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1740 1741 /* generate active rb bitmap according to active sa bitmap */ 1742 max_sa = adev->gfx.config.max_shader_engines * 1743 adev->gfx.config.max_sh_per_se; 1744 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1745 adev->gfx.config.max_sh_per_se; 1746 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1747 1748 for (i = 0; i < max_sa; i++) { 1749 if (active_sa_bitmap & (1 << i)) 1750 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1751 } 1752 1753 active_rb_bitmap &= global_active_rb_bitmap; 1754 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1755 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1756 } 1757 1758 #define LDS_APP_BASE 0x1 1759 #define SCRATCH_APP_BASE 0x2 1760 1761 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1762 { 1763 int i; 1764 uint32_t sh_mem_bases; 1765 uint32_t data; 1766 1767 /* 1768 * Configure apertures: 1769 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1770 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1771 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1772 */ 1773 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1774 SCRATCH_APP_BASE; 1775 1776 mutex_lock(&adev->srbm_mutex); 1777 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1778 soc24_grbm_select(adev, 0, 0, 0, i); 1779 /* CP and shaders */ 1780 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1781 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1782 1783 /* Enable trap for each kfd vmid. */ 1784 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1785 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1786 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1787 } 1788 soc24_grbm_select(adev, 0, 0, 0, 0); 1789 mutex_unlock(&adev->srbm_mutex); 1790 } 1791 1792 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1793 { 1794 /* TODO: harvest feature to be added later. */ 1795 } 1796 1797 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1798 { 1799 } 1800 1801 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1802 { 1803 u32 tmp; 1804 int i; 1805 1806 if (!amdgpu_sriov_vf(adev)) 1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1808 1809 gfx_v12_0_setup_rb(adev); 1810 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1811 gfx_v12_0_get_tcc_info(adev); 1812 adev->gfx.config.pa_sc_tile_steering_override = 0; 1813 1814 /* XXX SH_MEM regs */ 1815 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1816 mutex_lock(&adev->srbm_mutex); 1817 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1818 soc24_grbm_select(adev, 0, 0, 0, i); 1819 /* CP and shaders */ 1820 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1821 if (i != 0) { 1822 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1823 (adev->gmc.private_aperture_start >> 48)); 1824 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1825 (adev->gmc.shared_aperture_start >> 48)); 1826 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1827 } 1828 } 1829 soc24_grbm_select(adev, 0, 0, 0, 0); 1830 1831 mutex_unlock(&adev->srbm_mutex); 1832 1833 gfx_v12_0_init_compute_vmid(adev); 1834 } 1835 1836 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1837 int me, int pipe) 1838 { 1839 if (me != 0) 1840 return 0; 1841 1842 switch (pipe) { 1843 case 0: 1844 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1845 default: 1846 return 0; 1847 } 1848 } 1849 1850 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1851 int me, int pipe) 1852 { 1853 /* 1854 * amdgpu controls only the first MEC. That's why this function only 1855 * handles the setting of interrupts for this specific MEC. All other 1856 * pipes' interrupts are set by amdkfd. 1857 */ 1858 if (me != 1) 1859 return 0; 1860 1861 switch (pipe) { 1862 case 0: 1863 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1864 case 1: 1865 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1866 default: 1867 return 0; 1868 } 1869 } 1870 1871 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1872 bool enable) 1873 { 1874 u32 tmp, cp_int_cntl_reg; 1875 int i, j; 1876 1877 if (amdgpu_sriov_vf(adev)) 1878 return; 1879 1880 for (i = 0; i < adev->gfx.me.num_me; i++) { 1881 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1882 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1883 1884 if (cp_int_cntl_reg) { 1885 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1887 enable ? 1 : 0); 1888 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1889 enable ? 1 : 0); 1890 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1891 enable ? 1 : 0); 1892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1893 enable ? 1 : 0); 1894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1895 } 1896 } 1897 } 1898 } 1899 1900 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1901 { 1902 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1903 1904 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1905 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1906 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1907 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1908 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1909 1910 return 0; 1911 } 1912 1913 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1914 { 1915 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1916 1917 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1918 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1919 } 1920 1921 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1922 { 1923 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1924 udelay(50); 1925 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1926 udelay(50); 1927 } 1928 1929 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1930 bool enable) 1931 { 1932 uint32_t rlc_pg_cntl; 1933 1934 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1935 1936 if (!enable) { 1937 /* RLC_PG_CNTL[23] = 0 (default) 1938 * RLC will wait for handshake acks with SMU 1939 * GFXOFF will be enabled 1940 * RLC_PG_CNTL[23] = 1 1941 * RLC will not issue any message to SMU 1942 * hence no handshake between SMU & RLC 1943 * GFXOFF will be disabled 1944 */ 1945 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1946 } else 1947 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1948 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1949 } 1950 1951 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1952 { 1953 /* TODO: enable rlc & smu handshake until smu 1954 * and gfxoff feature works as expected */ 1955 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1956 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1957 1958 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1959 udelay(50); 1960 } 1961 1962 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1963 { 1964 uint32_t tmp; 1965 1966 /* enable Save Restore Machine */ 1967 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1968 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1969 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1970 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1971 } 1972 1973 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1974 { 1975 const struct rlc_firmware_header_v2_0 *hdr; 1976 const __le32 *fw_data; 1977 unsigned i, fw_size; 1978 1979 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1980 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1981 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1982 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1983 1984 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1985 RLCG_UCODE_LOADING_START_ADDRESS); 1986 1987 for (i = 0; i < fw_size; i++) 1988 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1989 le32_to_cpup(fw_data++)); 1990 1991 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1992 } 1993 1994 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1995 { 1996 const struct rlc_firmware_header_v2_2 *hdr; 1997 const __le32 *fw_data; 1998 unsigned i, fw_size; 1999 u32 tmp; 2000 2001 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2002 2003 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2004 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2005 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2006 2007 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2008 2009 for (i = 0; i < fw_size; i++) { 2010 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2011 msleep(1); 2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2013 le32_to_cpup(fw_data++)); 2014 } 2015 2016 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2017 2018 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2019 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2020 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2021 2022 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2023 for (i = 0; i < fw_size; i++) { 2024 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2025 msleep(1); 2026 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2027 le32_to_cpup(fw_data++)); 2028 } 2029 2030 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2031 2032 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2033 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2034 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2035 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2036 } 2037 2038 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2039 { 2040 const struct rlc_firmware_header_v2_0 *hdr; 2041 uint16_t version_major; 2042 uint16_t version_minor; 2043 2044 if (!adev->gfx.rlc_fw) 2045 return -EINVAL; 2046 2047 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2048 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2049 2050 version_major = le16_to_cpu(hdr->header.header_version_major); 2051 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2052 2053 if (version_major == 2) { 2054 gfx_v12_0_load_rlcg_microcode(adev); 2055 if (amdgpu_dpm == 1) { 2056 if (version_minor >= 2) 2057 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2058 } 2059 2060 return 0; 2061 } 2062 2063 return -EINVAL; 2064 } 2065 2066 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2067 { 2068 int r; 2069 2070 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2071 gfx_v12_0_init_csb(adev); 2072 2073 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2074 gfx_v12_0_rlc_enable_srm(adev); 2075 } else { 2076 if (amdgpu_sriov_vf(adev)) { 2077 gfx_v12_0_init_csb(adev); 2078 return 0; 2079 } 2080 2081 adev->gfx.rlc.funcs->stop(adev); 2082 2083 /* disable CG */ 2084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2085 2086 /* disable PG */ 2087 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2088 2089 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2090 /* legacy rlc firmware loading */ 2091 r = gfx_v12_0_rlc_load_microcode(adev); 2092 if (r) 2093 return r; 2094 } 2095 2096 gfx_v12_0_init_csb(adev); 2097 2098 adev->gfx.rlc.funcs->start(adev); 2099 } 2100 2101 return 0; 2102 } 2103 2104 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2105 { 2106 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2107 const struct gfx_firmware_header_v2_0 *me_hdr; 2108 const struct gfx_firmware_header_v2_0 *mec_hdr; 2109 uint32_t pipe_id, tmp; 2110 2111 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2112 adev->gfx.mec_fw->data; 2113 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2114 adev->gfx.me_fw->data; 2115 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2116 adev->gfx.pfp_fw->data; 2117 2118 /* config pfp program start addr */ 2119 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2120 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2121 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2122 (pfp_hdr->ucode_start_addr_hi << 30) | 2123 (pfp_hdr->ucode_start_addr_lo >> 2)); 2124 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2125 pfp_hdr->ucode_start_addr_hi >> 2); 2126 } 2127 soc24_grbm_select(adev, 0, 0, 0, 0); 2128 2129 /* reset pfp pipe */ 2130 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2134 2135 /* clear pfp pipe reset */ 2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2139 2140 /* config me program start addr */ 2141 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2142 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2143 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2144 (me_hdr->ucode_start_addr_hi << 30) | 2145 (me_hdr->ucode_start_addr_lo >> 2)); 2146 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2147 me_hdr->ucode_start_addr_hi>>2); 2148 } 2149 soc24_grbm_select(adev, 0, 0, 0, 0); 2150 2151 /* reset me pipe */ 2152 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2155 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2156 2157 /* clear me pipe reset */ 2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2161 2162 /* config mec program start addr */ 2163 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2164 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2165 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2166 mec_hdr->ucode_start_addr_lo >> 2 | 2167 mec_hdr->ucode_start_addr_hi << 30); 2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2169 mec_hdr->ucode_start_addr_hi >> 2); 2170 } 2171 soc24_grbm_select(adev, 0, 0, 0, 0); 2172 2173 /* reset mec pipe */ 2174 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2178 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2179 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2180 2181 /* clear mec pipe reset */ 2182 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2184 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2185 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2186 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2187 } 2188 2189 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2190 { 2191 const struct gfx_firmware_header_v2_0 *cp_hdr; 2192 unsigned pipe_id, tmp; 2193 2194 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2195 adev->gfx.pfp_fw->data; 2196 mutex_lock(&adev->srbm_mutex); 2197 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2198 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2199 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2200 (cp_hdr->ucode_start_addr_hi << 30) | 2201 (cp_hdr->ucode_start_addr_lo >> 2)); 2202 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2203 cp_hdr->ucode_start_addr_hi>>2); 2204 2205 /* 2206 * Program CP_ME_CNTL to reset given PIPE to take 2207 * effect of CP_PFP_PRGRM_CNTR_START. 2208 */ 2209 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2210 if (pipe_id == 0) 2211 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2212 PFP_PIPE0_RESET, 1); 2213 else 2214 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2215 PFP_PIPE1_RESET, 1); 2216 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2217 2218 /* Clear pfp pipe0 reset bit. */ 2219 if (pipe_id == 0) 2220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2221 PFP_PIPE0_RESET, 0); 2222 else 2223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2224 PFP_PIPE1_RESET, 0); 2225 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2226 } 2227 soc24_grbm_select(adev, 0, 0, 0, 0); 2228 mutex_unlock(&adev->srbm_mutex); 2229 } 2230 2231 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2232 { 2233 const struct gfx_firmware_header_v2_0 *cp_hdr; 2234 unsigned pipe_id, tmp; 2235 2236 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2237 adev->gfx.me_fw->data; 2238 mutex_lock(&adev->srbm_mutex); 2239 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2240 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2241 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2242 (cp_hdr->ucode_start_addr_hi << 30) | 2243 (cp_hdr->ucode_start_addr_lo >> 2) ); 2244 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2245 cp_hdr->ucode_start_addr_hi>>2); 2246 2247 /* 2248 * Program CP_ME_CNTL to reset given PIPE to take 2249 * effect of CP_ME_PRGRM_CNTR_START. 2250 */ 2251 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2252 if (pipe_id == 0) 2253 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2254 ME_PIPE0_RESET, 1); 2255 else 2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2257 ME_PIPE1_RESET, 1); 2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2259 2260 /* Clear pfp pipe0 reset bit. */ 2261 if (pipe_id == 0) 2262 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2263 ME_PIPE0_RESET, 0); 2264 else 2265 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2266 ME_PIPE1_RESET, 0); 2267 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2268 } 2269 soc24_grbm_select(adev, 0, 0, 0, 0); 2270 mutex_unlock(&adev->srbm_mutex); 2271 } 2272 2273 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2274 { 2275 const struct gfx_firmware_header_v2_0 *cp_hdr; 2276 unsigned pipe_id; 2277 2278 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2279 adev->gfx.mec_fw->data; 2280 mutex_lock(&adev->srbm_mutex); 2281 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2282 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2283 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2284 cp_hdr->ucode_start_addr_lo >> 2 | 2285 cp_hdr->ucode_start_addr_hi << 30); 2286 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2287 cp_hdr->ucode_start_addr_hi >> 2); 2288 } 2289 soc24_grbm_select(adev, 0, 0, 0, 0); 2290 mutex_unlock(&adev->srbm_mutex); 2291 } 2292 2293 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2294 { 2295 uint32_t cp_status; 2296 uint32_t bootload_status; 2297 int i; 2298 2299 for (i = 0; i < adev->usec_timeout; i++) { 2300 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2301 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2302 2303 if ((cp_status == 0) && 2304 (REG_GET_FIELD(bootload_status, 2305 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2306 break; 2307 } 2308 udelay(1); 2309 if (amdgpu_emu_mode) 2310 msleep(10); 2311 } 2312 2313 if (i >= adev->usec_timeout) { 2314 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2315 return -ETIMEDOUT; 2316 } 2317 2318 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2319 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2320 gfx_v12_0_set_me_ucode_start_addr(adev); 2321 gfx_v12_0_set_mec_ucode_start_addr(adev); 2322 } 2323 2324 return 0; 2325 } 2326 2327 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2328 { 2329 int i; 2330 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2331 2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2334 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2335 2336 for (i = 0; i < adev->usec_timeout; i++) { 2337 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2338 break; 2339 udelay(1); 2340 } 2341 2342 if (i >= adev->usec_timeout) 2343 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2344 2345 return 0; 2346 } 2347 2348 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2349 { 2350 int r; 2351 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2352 const __le32 *fw_ucode, *fw_data; 2353 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2354 uint32_t tmp; 2355 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2356 2357 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2358 adev->gfx.pfp_fw->data; 2359 2360 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2361 2362 /* instruction */ 2363 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2364 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2365 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2366 /* data */ 2367 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2368 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2369 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2370 2371 /* 64kb align */ 2372 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2373 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2374 &adev->gfx.pfp.pfp_fw_obj, 2375 &adev->gfx.pfp.pfp_fw_gpu_addr, 2376 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2377 if (r) { 2378 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2379 gfx_v12_0_pfp_fini(adev); 2380 return r; 2381 } 2382 2383 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2384 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2385 &adev->gfx.pfp.pfp_fw_data_obj, 2386 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2387 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2388 if (r) { 2389 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2390 gfx_v12_0_pfp_fini(adev); 2391 return r; 2392 } 2393 2394 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2395 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2396 2397 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2398 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2399 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2400 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2401 2402 if (amdgpu_emu_mode == 1) 2403 amdgpu_device_flush_hdp(adev, NULL); 2404 2405 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2406 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2407 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2408 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2409 2410 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2411 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2412 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2413 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2414 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2415 2416 /* 2417 * Programming any of the CP_PFP_IC_BASE registers 2418 * forces invalidation of the ME L1 I$. Wait for the 2419 * invalidation complete 2420 */ 2421 for (i = 0; i < usec_timeout; i++) { 2422 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2423 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2424 INVALIDATE_CACHE_COMPLETE)) 2425 break; 2426 udelay(1); 2427 } 2428 2429 if (i >= usec_timeout) { 2430 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2431 return -EINVAL; 2432 } 2433 2434 /* Prime the L1 instruction caches */ 2435 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2436 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2437 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2438 /* Waiting for cache primed*/ 2439 for (i = 0; i < usec_timeout; i++) { 2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2441 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2442 ICACHE_PRIMED)) 2443 break; 2444 udelay(1); 2445 } 2446 2447 if (i >= usec_timeout) { 2448 dev_err(adev->dev, "failed to prime instruction cache\n"); 2449 return -EINVAL; 2450 } 2451 2452 mutex_lock(&adev->srbm_mutex); 2453 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2454 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2455 2456 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2457 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2458 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2459 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2460 } 2461 soc24_grbm_select(adev, 0, 0, 0, 0); 2462 mutex_unlock(&adev->srbm_mutex); 2463 2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2466 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2467 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2468 2469 /* Invalidate the data caches */ 2470 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2471 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2473 2474 for (i = 0; i < usec_timeout; i++) { 2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2476 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2477 INVALIDATE_DCACHE_COMPLETE)) 2478 break; 2479 udelay(1); 2480 } 2481 2482 if (i >= usec_timeout) { 2483 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2484 return -EINVAL; 2485 } 2486 2487 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2488 2489 return 0; 2490 } 2491 2492 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2493 { 2494 int r; 2495 const struct gfx_firmware_header_v2_0 *me_hdr; 2496 const __le32 *fw_ucode, *fw_data; 2497 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2498 uint32_t tmp; 2499 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2500 2501 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2502 adev->gfx.me_fw->data; 2503 2504 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2505 2506 /* instruction */ 2507 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2508 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2509 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2510 /* data */ 2511 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2512 le32_to_cpu(me_hdr->data_offset_bytes)); 2513 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2514 2515 /* 64kb align*/ 2516 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2517 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2518 &adev->gfx.me.me_fw_obj, 2519 &adev->gfx.me.me_fw_gpu_addr, 2520 (void **)&adev->gfx.me.me_fw_ptr); 2521 if (r) { 2522 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2523 gfx_v12_0_me_fini(adev); 2524 return r; 2525 } 2526 2527 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2528 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2529 &adev->gfx.me.me_fw_data_obj, 2530 &adev->gfx.me.me_fw_data_gpu_addr, 2531 (void **)&adev->gfx.me.me_fw_data_ptr); 2532 if (r) { 2533 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2534 gfx_v12_0_me_fini(adev); 2535 return r; 2536 } 2537 2538 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2539 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2540 2541 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2542 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2543 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2544 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2545 2546 if (amdgpu_emu_mode == 1) 2547 amdgpu_device_flush_hdp(adev, NULL); 2548 2549 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2550 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2551 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2552 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2553 2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2555 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2557 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2558 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2559 2560 /* 2561 * Programming any of the CP_ME_IC_BASE registers 2562 * forces invalidation of the ME L1 I$. Wait for the 2563 * invalidation complete 2564 */ 2565 for (i = 0; i < usec_timeout; i++) { 2566 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2567 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2568 INVALIDATE_CACHE_COMPLETE)) 2569 break; 2570 udelay(1); 2571 } 2572 2573 if (i >= usec_timeout) { 2574 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2575 return -EINVAL; 2576 } 2577 2578 /* Prime the instruction caches */ 2579 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2580 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2581 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2582 2583 /* Waiting for instruction cache primed*/ 2584 for (i = 0; i < usec_timeout; i++) { 2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2586 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2587 ICACHE_PRIMED)) 2588 break; 2589 udelay(1); 2590 } 2591 2592 if (i >= usec_timeout) { 2593 dev_err(adev->dev, "failed to prime instruction cache\n"); 2594 return -EINVAL; 2595 } 2596 2597 mutex_lock(&adev->srbm_mutex); 2598 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2599 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2600 2601 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2602 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2603 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2604 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2605 } 2606 soc24_grbm_select(adev, 0, 0, 0, 0); 2607 mutex_unlock(&adev->srbm_mutex); 2608 2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2611 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2612 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2613 2614 /* Invalidate the data caches */ 2615 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2616 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2618 2619 for (i = 0; i < usec_timeout; i++) { 2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2621 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2622 INVALIDATE_DCACHE_COMPLETE)) 2623 break; 2624 udelay(1); 2625 } 2626 2627 if (i >= usec_timeout) { 2628 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2629 return -EINVAL; 2630 } 2631 2632 gfx_v12_0_set_me_ucode_start_addr(adev); 2633 2634 return 0; 2635 } 2636 2637 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2638 { 2639 int r; 2640 2641 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2642 return -EINVAL; 2643 2644 gfx_v12_0_cp_gfx_enable(adev, false); 2645 2646 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2647 if (r) { 2648 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2649 return r; 2650 } 2651 2652 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2653 if (r) { 2654 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2655 return r; 2656 } 2657 2658 return 0; 2659 } 2660 2661 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2662 { 2663 /* init the CP */ 2664 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2665 adev->gfx.config.max_hw_contexts - 1); 2666 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2667 2668 if (!amdgpu_async_gfx_ring) 2669 gfx_v12_0_cp_gfx_enable(adev, true); 2670 2671 return 0; 2672 } 2673 2674 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2675 CP_PIPE_ID pipe) 2676 { 2677 u32 tmp; 2678 2679 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2680 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2681 2682 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2683 } 2684 2685 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2686 struct amdgpu_ring *ring) 2687 { 2688 u32 tmp; 2689 2690 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2691 if (ring->use_doorbell) { 2692 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2693 DOORBELL_OFFSET, ring->doorbell_index); 2694 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2695 DOORBELL_EN, 1); 2696 } else { 2697 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2698 DOORBELL_EN, 0); 2699 } 2700 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2701 2702 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2703 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2704 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2705 2706 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2707 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2708 } 2709 2710 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2711 { 2712 struct amdgpu_ring *ring; 2713 u32 tmp; 2714 u32 rb_bufsz; 2715 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2716 2717 /* Set the write pointer delay */ 2718 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2719 2720 /* set the RB to use vmid 0 */ 2721 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2722 2723 /* Init gfx ring 0 for pipe 0 */ 2724 mutex_lock(&adev->srbm_mutex); 2725 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2726 2727 /* Set ring buffer size */ 2728 ring = &adev->gfx.gfx_ring[0]; 2729 rb_bufsz = order_base_2(ring->ring_size / 8); 2730 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2731 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2732 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2733 2734 /* Initialize the ring buffer's write pointers */ 2735 ring->wptr = 0; 2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2737 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2738 2739 /* set the wb address whether it's enabled or not */ 2740 rptr_addr = ring->rptr_gpu_addr; 2741 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2742 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2743 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2744 2745 wptr_gpu_addr = ring->wptr_gpu_addr; 2746 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2747 lower_32_bits(wptr_gpu_addr)); 2748 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2749 upper_32_bits(wptr_gpu_addr)); 2750 2751 mdelay(1); 2752 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2753 2754 rb_addr = ring->gpu_addr >> 8; 2755 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2756 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2757 2758 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2759 2760 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2761 mutex_unlock(&adev->srbm_mutex); 2762 2763 /* Switch to pipe 0 */ 2764 mutex_lock(&adev->srbm_mutex); 2765 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2766 mutex_unlock(&adev->srbm_mutex); 2767 2768 /* start the ring */ 2769 gfx_v12_0_cp_gfx_start(adev); 2770 return 0; 2771 } 2772 2773 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2774 { 2775 u32 data; 2776 2777 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2779 enable ? 0 : 1); 2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2781 enable ? 0 : 1); 2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2783 enable ? 0 : 1); 2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2785 enable ? 0 : 1); 2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2787 enable ? 0 : 1); 2788 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2789 enable ? 1 : 0); 2790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2791 enable ? 1 : 0); 2792 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2793 enable ? 1 : 0); 2794 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2795 enable ? 1 : 0); 2796 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2797 enable ? 0 : 1); 2798 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2799 2800 adev->gfx.kiq[0].ring.sched.ready = enable; 2801 2802 udelay(50); 2803 } 2804 2805 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2806 { 2807 const struct gfx_firmware_header_v2_0 *mec_hdr; 2808 const __le32 *fw_ucode, *fw_data; 2809 u32 tmp, fw_ucode_size, fw_data_size; 2810 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2811 u32 *fw_ucode_ptr, *fw_data_ptr; 2812 int r; 2813 2814 if (!adev->gfx.mec_fw) 2815 return -EINVAL; 2816 2817 gfx_v12_0_cp_compute_enable(adev, false); 2818 2819 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2820 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2821 2822 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2823 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2824 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2825 2826 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2827 le32_to_cpu(mec_hdr->data_offset_bytes)); 2828 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2829 2830 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2831 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2832 &adev->gfx.mec.mec_fw_obj, 2833 &adev->gfx.mec.mec_fw_gpu_addr, 2834 (void **)&fw_ucode_ptr); 2835 if (r) { 2836 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2837 gfx_v12_0_mec_fini(adev); 2838 return r; 2839 } 2840 2841 r = amdgpu_bo_create_reserved(adev, 2842 ALIGN(fw_data_size, 64 * 1024) * 2843 adev->gfx.mec.num_pipe_per_mec, 2844 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2845 &adev->gfx.mec.mec_fw_data_obj, 2846 &adev->gfx.mec.mec_fw_data_gpu_addr, 2847 (void **)&fw_data_ptr); 2848 if (r) { 2849 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2850 gfx_v12_0_mec_fini(adev); 2851 return r; 2852 } 2853 2854 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2855 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2856 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2857 } 2858 2859 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2860 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2861 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2862 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2863 2864 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2865 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2866 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2867 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2868 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2869 2870 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2871 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2872 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2873 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2874 2875 mutex_lock(&adev->srbm_mutex); 2876 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2877 soc24_grbm_select(adev, 1, i, 0, 0); 2878 2879 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2880 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2881 i * ALIGN(fw_data_size, 64 * 1024))); 2882 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2883 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2884 i * ALIGN(fw_data_size, 64 * 1024))); 2885 2886 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2887 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2888 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2889 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2890 } 2891 mutex_unlock(&adev->srbm_mutex); 2892 soc24_grbm_select(adev, 0, 0, 0, 0); 2893 2894 /* Trigger an invalidation of the L1 instruction caches */ 2895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2896 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2897 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2898 2899 /* Wait for invalidation complete */ 2900 for (i = 0; i < usec_timeout; i++) { 2901 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2902 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2903 INVALIDATE_DCACHE_COMPLETE)) 2904 break; 2905 udelay(1); 2906 } 2907 2908 if (i >= usec_timeout) { 2909 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2910 return -EINVAL; 2911 } 2912 2913 /* Trigger an invalidation of the L1 instruction caches */ 2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2915 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2916 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2917 2918 /* Wait for invalidation complete */ 2919 for (i = 0; i < usec_timeout; i++) { 2920 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2921 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2922 INVALIDATE_CACHE_COMPLETE)) 2923 break; 2924 udelay(1); 2925 } 2926 2927 if (i >= usec_timeout) { 2928 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2929 return -EINVAL; 2930 } 2931 2932 gfx_v12_0_set_mec_ucode_start_addr(adev); 2933 2934 return 0; 2935 } 2936 2937 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2938 { 2939 uint32_t tmp; 2940 struct amdgpu_device *adev = ring->adev; 2941 2942 /* tell RLC which is KIQ queue */ 2943 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2944 tmp &= 0xffffff00; 2945 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2946 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2947 } 2948 2949 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2950 { 2951 /* set graphics engine doorbell range */ 2952 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2953 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2954 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2955 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2956 2957 /* set compute engine doorbell range */ 2958 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2959 (adev->doorbell_index.kiq * 2) << 2); 2960 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2961 (adev->doorbell_index.userqueue_end * 2) << 2); 2962 } 2963 2964 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2965 struct amdgpu_mqd_prop *prop) 2966 { 2967 struct v12_gfx_mqd *mqd = m; 2968 uint64_t hqd_gpu_addr, wb_gpu_addr; 2969 uint32_t tmp; 2970 uint32_t rb_bufsz; 2971 2972 /* set up gfx hqd wptr */ 2973 mqd->cp_gfx_hqd_wptr = 0; 2974 mqd->cp_gfx_hqd_wptr_hi = 0; 2975 2976 /* set the pointer to the MQD */ 2977 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2978 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2979 2980 /* set up mqd control */ 2981 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2982 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2983 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2984 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2985 mqd->cp_gfx_mqd_control = tmp; 2986 2987 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2988 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2990 mqd->cp_gfx_hqd_vmid = 0; 2991 2992 /* set up default queue priority level 2993 * 0x0 = low priority, 0x1 = high priority */ 2994 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2995 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2996 mqd->cp_gfx_hqd_queue_priority = tmp; 2997 2998 /* set up time quantum */ 2999 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3001 mqd->cp_gfx_hqd_quantum = tmp; 3002 3003 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3004 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3005 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3006 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3007 3008 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3009 wb_gpu_addr = prop->rptr_gpu_addr; 3010 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3011 mqd->cp_gfx_hqd_rptr_addr_hi = 3012 upper_32_bits(wb_gpu_addr) & 0xffff; 3013 3014 /* set up rb_wptr_poll addr */ 3015 wb_gpu_addr = prop->wptr_gpu_addr; 3016 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3017 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3018 3019 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3020 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3021 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3023 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3024 #ifdef __BIG_ENDIAN 3025 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3026 #endif 3027 if (prop->tmz_queue) 3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3029 if (!prop->kernel_queue) 3030 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3031 mqd->cp_gfx_hqd_cntl = tmp; 3032 3033 /* set up cp_doorbell_control */ 3034 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3035 if (prop->use_doorbell) { 3036 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3037 DOORBELL_OFFSET, prop->doorbell_index); 3038 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3039 DOORBELL_EN, 1); 3040 } else 3041 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3042 DOORBELL_EN, 0); 3043 mqd->cp_rb_doorbell_control = tmp; 3044 3045 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3046 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3047 3048 /* active the queue */ 3049 mqd->cp_gfx_hqd_active = 1; 3050 3051 /* set gfx UQ items */ 3052 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3053 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3054 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3055 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3056 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3057 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3058 3059 return 0; 3060 } 3061 3062 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3063 { 3064 struct amdgpu_device *adev = ring->adev; 3065 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3066 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3067 3068 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3069 memset((void *)mqd, 0, sizeof(*mqd)); 3070 mutex_lock(&adev->srbm_mutex); 3071 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3072 amdgpu_ring_init_mqd(ring); 3073 soc24_grbm_select(adev, 0, 0, 0, 0); 3074 mutex_unlock(&adev->srbm_mutex); 3075 if (adev->gfx.me.mqd_backup[mqd_idx]) 3076 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3077 } else { 3078 /* restore mqd with the backup copy */ 3079 if (adev->gfx.me.mqd_backup[mqd_idx]) 3080 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3081 /* reset the ring */ 3082 ring->wptr = 0; 3083 *ring->wptr_cpu_addr = 0; 3084 amdgpu_ring_clear_ring(ring); 3085 } 3086 3087 return 0; 3088 } 3089 3090 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3091 { 3092 int i, r; 3093 3094 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3095 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3096 if (r) 3097 return r; 3098 } 3099 3100 r = amdgpu_gfx_enable_kgq(adev, 0); 3101 if (r) 3102 return r; 3103 3104 return gfx_v12_0_cp_gfx_start(adev); 3105 } 3106 3107 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3108 struct amdgpu_mqd_prop *prop) 3109 { 3110 struct v12_compute_mqd *mqd = m; 3111 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3112 uint32_t tmp; 3113 3114 mqd->header = 0xC0310800; 3115 mqd->compute_pipelinestat_enable = 0x00000001; 3116 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3117 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3118 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3119 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3120 mqd->compute_misc_reserved = 0x00000007; 3121 3122 eop_base_addr = prop->eop_gpu_addr >> 8; 3123 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3124 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3125 3126 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3127 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3128 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3129 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3130 3131 mqd->cp_hqd_eop_control = tmp; 3132 3133 /* enable doorbell? */ 3134 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3135 3136 if (prop->use_doorbell) { 3137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3138 DOORBELL_OFFSET, prop->doorbell_index); 3139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3140 DOORBELL_EN, 1); 3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3142 DOORBELL_SOURCE, 0); 3143 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3144 DOORBELL_HIT, 0); 3145 } else { 3146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3147 DOORBELL_EN, 0); 3148 } 3149 3150 mqd->cp_hqd_pq_doorbell_control = tmp; 3151 3152 /* disable the queue if it's active */ 3153 mqd->cp_hqd_dequeue_request = 0; 3154 mqd->cp_hqd_pq_rptr = 0; 3155 mqd->cp_hqd_pq_wptr_lo = 0; 3156 mqd->cp_hqd_pq_wptr_hi = 0; 3157 3158 /* set the pointer to the MQD */ 3159 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3160 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3161 3162 /* set MQD vmid to 0 */ 3163 tmp = regCP_MQD_CONTROL_DEFAULT; 3164 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3165 mqd->cp_mqd_control = tmp; 3166 3167 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3168 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3169 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3170 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3171 3172 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3173 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3175 (order_base_2(prop->queue_size / 4) - 1)); 3176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3177 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3180 if (prop->kernel_queue) { 3181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3183 } 3184 if (prop->tmz_queue) 3185 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3186 mqd->cp_hqd_pq_control = tmp; 3187 3188 /* set the wb address whether it's enabled or not */ 3189 wb_gpu_addr = prop->rptr_gpu_addr; 3190 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3191 mqd->cp_hqd_pq_rptr_report_addr_hi = 3192 upper_32_bits(wb_gpu_addr) & 0xffff; 3193 3194 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3195 wb_gpu_addr = prop->wptr_gpu_addr; 3196 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3197 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3198 3199 tmp = 0; 3200 /* enable the doorbell if requested */ 3201 if (prop->use_doorbell) { 3202 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3203 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3204 DOORBELL_OFFSET, prop->doorbell_index); 3205 3206 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3207 DOORBELL_EN, 1); 3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3209 DOORBELL_SOURCE, 0); 3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3211 DOORBELL_HIT, 0); 3212 } 3213 3214 mqd->cp_hqd_pq_doorbell_control = tmp; 3215 3216 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3217 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3218 3219 /* set the vmid for the queue */ 3220 mqd->cp_hqd_vmid = 0; 3221 3222 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3223 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3224 mqd->cp_hqd_persistent_state = tmp; 3225 3226 /* set MIN_IB_AVAIL_SIZE */ 3227 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3228 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3229 mqd->cp_hqd_ib_control = tmp; 3230 3231 /* set static priority for a compute queue/ring */ 3232 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3233 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3234 3235 mqd->cp_hqd_active = prop->hqd_active; 3236 3237 /* set UQ fenceaddress */ 3238 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3239 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3240 3241 return 0; 3242 } 3243 3244 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3245 { 3246 struct amdgpu_device *adev = ring->adev; 3247 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3248 int j; 3249 3250 /* inactivate the queue */ 3251 if (amdgpu_sriov_vf(adev)) 3252 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3253 3254 /* disable wptr polling */ 3255 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3256 3257 /* write the EOP addr */ 3258 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3259 mqd->cp_hqd_eop_base_addr_lo); 3260 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3261 mqd->cp_hqd_eop_base_addr_hi); 3262 3263 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3264 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3265 mqd->cp_hqd_eop_control); 3266 3267 /* enable doorbell? */ 3268 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3269 mqd->cp_hqd_pq_doorbell_control); 3270 3271 /* disable the queue if it's active */ 3272 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3273 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3274 for (j = 0; j < adev->usec_timeout; j++) { 3275 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3276 break; 3277 udelay(1); 3278 } 3279 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3280 mqd->cp_hqd_dequeue_request); 3281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3282 mqd->cp_hqd_pq_rptr); 3283 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3284 mqd->cp_hqd_pq_wptr_lo); 3285 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3286 mqd->cp_hqd_pq_wptr_hi); 3287 } 3288 3289 /* set the pointer to the MQD */ 3290 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3291 mqd->cp_mqd_base_addr_lo); 3292 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3293 mqd->cp_mqd_base_addr_hi); 3294 3295 /* set MQD vmid to 0 */ 3296 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3297 mqd->cp_mqd_control); 3298 3299 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3300 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3301 mqd->cp_hqd_pq_base_lo); 3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3303 mqd->cp_hqd_pq_base_hi); 3304 3305 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3307 mqd->cp_hqd_pq_control); 3308 3309 /* set the wb address whether it's enabled or not */ 3310 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3311 mqd->cp_hqd_pq_rptr_report_addr_lo); 3312 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3313 mqd->cp_hqd_pq_rptr_report_addr_hi); 3314 3315 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3316 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3317 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3318 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3319 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3320 3321 /* enable the doorbell if requested */ 3322 if (ring->use_doorbell) { 3323 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3324 (adev->doorbell_index.kiq * 2) << 2); 3325 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3326 (adev->doorbell_index.userqueue_end * 2) << 2); 3327 } 3328 3329 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3330 mqd->cp_hqd_pq_doorbell_control); 3331 3332 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3333 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3334 mqd->cp_hqd_pq_wptr_lo); 3335 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3336 mqd->cp_hqd_pq_wptr_hi); 3337 3338 /* set the vmid for the queue */ 3339 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3340 3341 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3342 mqd->cp_hqd_persistent_state); 3343 3344 /* activate the queue */ 3345 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3346 mqd->cp_hqd_active); 3347 3348 if (ring->use_doorbell) 3349 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3350 3351 return 0; 3352 } 3353 3354 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3355 { 3356 struct amdgpu_device *adev = ring->adev; 3357 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3358 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3359 3360 gfx_v12_0_kiq_setting(ring); 3361 3362 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3363 /* reset MQD to a clean status */ 3364 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3365 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3366 3367 /* reset ring buffer */ 3368 ring->wptr = 0; 3369 amdgpu_ring_clear_ring(ring); 3370 3371 mutex_lock(&adev->srbm_mutex); 3372 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3373 gfx_v12_0_kiq_init_register(ring); 3374 soc24_grbm_select(adev, 0, 0, 0, 0); 3375 mutex_unlock(&adev->srbm_mutex); 3376 } else { 3377 memset((void *)mqd, 0, sizeof(*mqd)); 3378 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3379 amdgpu_ring_clear_ring(ring); 3380 mutex_lock(&adev->srbm_mutex); 3381 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3382 amdgpu_ring_init_mqd(ring); 3383 gfx_v12_0_kiq_init_register(ring); 3384 soc24_grbm_select(adev, 0, 0, 0, 0); 3385 mutex_unlock(&adev->srbm_mutex); 3386 3387 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3388 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3389 } 3390 3391 return 0; 3392 } 3393 3394 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3395 { 3396 struct amdgpu_device *adev = ring->adev; 3397 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3398 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3399 3400 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3401 memset((void *)mqd, 0, sizeof(*mqd)); 3402 mutex_lock(&adev->srbm_mutex); 3403 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3404 amdgpu_ring_init_mqd(ring); 3405 soc24_grbm_select(adev, 0, 0, 0, 0); 3406 mutex_unlock(&adev->srbm_mutex); 3407 3408 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3409 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3410 } else { 3411 /* restore MQD to a clean status */ 3412 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3413 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3414 /* reset ring buffer */ 3415 ring->wptr = 0; 3416 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3417 amdgpu_ring_clear_ring(ring); 3418 } 3419 3420 return 0; 3421 } 3422 3423 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3424 { 3425 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3426 adev->gfx.kiq[0].ring.sched.ready = true; 3427 return 0; 3428 } 3429 3430 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3431 { 3432 int i, r; 3433 3434 if (!amdgpu_async_gfx_ring) 3435 gfx_v12_0_cp_compute_enable(adev, true); 3436 3437 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3438 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3439 if (r) 3440 return r; 3441 } 3442 3443 return amdgpu_gfx_enable_kcq(adev, 0); 3444 } 3445 3446 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3447 { 3448 int r, i; 3449 struct amdgpu_ring *ring; 3450 3451 if (!(adev->flags & AMD_IS_APU)) 3452 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3453 3454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3455 /* legacy firmware loading */ 3456 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3457 if (r) 3458 return r; 3459 3460 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3461 if (r) 3462 return r; 3463 } 3464 3465 gfx_v12_0_cp_set_doorbell_range(adev); 3466 3467 if (amdgpu_async_gfx_ring) { 3468 gfx_v12_0_cp_compute_enable(adev, true); 3469 gfx_v12_0_cp_gfx_enable(adev, true); 3470 } 3471 3472 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3473 r = amdgpu_mes_kiq_hw_init(adev); 3474 else 3475 r = gfx_v12_0_kiq_resume(adev); 3476 if (r) 3477 return r; 3478 3479 r = gfx_v12_0_kcq_resume(adev); 3480 if (r) 3481 return r; 3482 3483 if (!amdgpu_async_gfx_ring) { 3484 r = gfx_v12_0_cp_gfx_resume(adev); 3485 if (r) 3486 return r; 3487 } else { 3488 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3489 if (r) 3490 return r; 3491 } 3492 3493 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3494 ring = &adev->gfx.gfx_ring[i]; 3495 r = amdgpu_ring_test_helper(ring); 3496 if (r) 3497 return r; 3498 } 3499 3500 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3501 ring = &adev->gfx.compute_ring[i]; 3502 r = amdgpu_ring_test_helper(ring); 3503 if (r) 3504 return r; 3505 } 3506 3507 return 0; 3508 } 3509 3510 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3511 { 3512 gfx_v12_0_cp_gfx_enable(adev, enable); 3513 gfx_v12_0_cp_compute_enable(adev, enable); 3514 } 3515 3516 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3517 { 3518 int r; 3519 bool value; 3520 3521 r = adev->gfxhub.funcs->gart_enable(adev); 3522 if (r) 3523 return r; 3524 3525 amdgpu_device_flush_hdp(adev, NULL); 3526 3527 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3528 false : true; 3529 3530 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3531 /* TODO investigate why this and the hdp flush above is needed, 3532 * are we missing a flush somewhere else? */ 3533 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3534 3535 return 0; 3536 } 3537 3538 static int get_gb_addr_config(struct amdgpu_device *adev) 3539 { 3540 u32 gb_addr_config; 3541 3542 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3543 if (gb_addr_config == 0) 3544 return -EINVAL; 3545 3546 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3547 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3548 3549 adev->gfx.config.gb_addr_config = gb_addr_config; 3550 3551 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3552 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3553 GB_ADDR_CONFIG, NUM_PIPES); 3554 3555 adev->gfx.config.max_tile_pipes = 3556 adev->gfx.config.gb_addr_config_fields.num_pipes; 3557 3558 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3559 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3560 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3561 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3562 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3563 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3564 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3565 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3566 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3567 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3568 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3569 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3570 3571 return 0; 3572 } 3573 3574 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3575 { 3576 uint32_t data; 3577 3578 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3579 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3580 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3581 3582 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3583 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3584 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3585 } 3586 3587 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3588 { 3589 if (amdgpu_sriov_vf(adev)) 3590 return; 3591 3592 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3593 case IP_VERSION(12, 0, 0): 3594 case IP_VERSION(12, 0, 1): 3595 soc15_program_register_sequence(adev, 3596 golden_settings_gc_12_0, 3597 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3598 3599 if (adev->rev_id == 0) 3600 soc15_program_register_sequence(adev, 3601 golden_settings_gc_12_0_rev0, 3602 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3603 break; 3604 default: 3605 break; 3606 } 3607 } 3608 3609 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3610 { 3611 int r; 3612 struct amdgpu_device *adev = ip_block->adev; 3613 3614 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3615 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3616 /* RLC autoload sequence 1: Program rlc ram */ 3617 if (adev->gfx.imu.funcs->program_rlc_ram) 3618 adev->gfx.imu.funcs->program_rlc_ram(adev); 3619 } 3620 /* rlc autoload firmware */ 3621 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3622 if (r) 3623 return r; 3624 } else { 3625 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3626 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3627 if (adev->gfx.imu.funcs->load_microcode) 3628 adev->gfx.imu.funcs->load_microcode(adev); 3629 if (adev->gfx.imu.funcs->setup_imu) 3630 adev->gfx.imu.funcs->setup_imu(adev); 3631 if (adev->gfx.imu.funcs->start_imu) 3632 adev->gfx.imu.funcs->start_imu(adev); 3633 } 3634 3635 /* disable gpa mode in backdoor loading */ 3636 gfx_v12_0_disable_gpa_mode(adev); 3637 } 3638 } 3639 3640 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3641 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3642 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3643 if (r) { 3644 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3645 return r; 3646 } 3647 } 3648 3649 if (!amdgpu_emu_mode) 3650 gfx_v12_0_init_golden_registers(adev); 3651 3652 adev->gfx.is_poweron = true; 3653 3654 if (get_gb_addr_config(adev)) 3655 DRM_WARN("Invalid gb_addr_config !\n"); 3656 3657 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3658 gfx_v12_0_config_gfx_rs64(adev); 3659 3660 r = gfx_v12_0_gfxhub_enable(adev); 3661 if (r) 3662 return r; 3663 3664 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3665 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3666 (amdgpu_dpm == 1)) { 3667 /** 3668 * For gfx 12, rlc firmware loading relies on smu firmware is 3669 * loaded firstly, so in direct type, it has to load smc ucode 3670 * here before rlc. 3671 */ 3672 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3673 if (r) 3674 return r; 3675 } 3676 3677 gfx_v12_0_constants_init(adev); 3678 3679 if (adev->nbio.funcs->gc_doorbell_init) 3680 adev->nbio.funcs->gc_doorbell_init(adev); 3681 3682 r = gfx_v12_0_rlc_resume(adev); 3683 if (r) 3684 return r; 3685 3686 /* 3687 * init golden registers and rlc resume may override some registers, 3688 * reconfig them here 3689 */ 3690 gfx_v12_0_tcp_harvest(adev); 3691 3692 r = gfx_v12_0_cp_resume(adev); 3693 if (r) 3694 return r; 3695 3696 return r; 3697 } 3698 3699 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3700 bool enable) 3701 { 3702 unsigned int irq_type; 3703 int m, p, r; 3704 3705 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3706 for (m = 0; m < adev->gfx.me.num_me; m++) { 3707 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3708 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3709 if (enable) 3710 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3711 irq_type); 3712 else 3713 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3714 irq_type); 3715 if (r) 3716 return r; 3717 } 3718 } 3719 } 3720 3721 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3722 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3723 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3724 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3725 + (m * adev->gfx.mec.num_pipe_per_mec) 3726 + p; 3727 if (enable) 3728 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3729 irq_type); 3730 else 3731 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3732 irq_type); 3733 if (r) 3734 return r; 3735 } 3736 } 3737 } 3738 3739 return 0; 3740 } 3741 3742 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3743 { 3744 struct amdgpu_device *adev = ip_block->adev; 3745 uint32_t tmp; 3746 3747 cancel_delayed_work_sync(&adev->gfx.idle_work); 3748 3749 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3750 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3751 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3752 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3753 3754 if (!adev->no_hw_access) { 3755 if (amdgpu_async_gfx_ring) { 3756 if (amdgpu_gfx_disable_kgq(adev, 0)) 3757 DRM_ERROR("KGQ disable failed\n"); 3758 } 3759 3760 if (amdgpu_gfx_disable_kcq(adev, 0)) 3761 DRM_ERROR("KCQ disable failed\n"); 3762 3763 amdgpu_mes_kiq_hw_fini(adev); 3764 } 3765 3766 if (amdgpu_sriov_vf(adev)) { 3767 gfx_v12_0_cp_gfx_enable(adev, false); 3768 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3769 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3770 tmp &= 0xffffff00; 3771 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3772 3773 return 0; 3774 } 3775 gfx_v12_0_cp_enable(adev, false); 3776 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3777 3778 adev->gfxhub.funcs->gart_disable(adev); 3779 3780 adev->gfx.is_poweron = false; 3781 3782 return 0; 3783 } 3784 3785 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3786 { 3787 return gfx_v12_0_hw_fini(ip_block); 3788 } 3789 3790 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3791 { 3792 return gfx_v12_0_hw_init(ip_block); 3793 } 3794 3795 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3796 { 3797 struct amdgpu_device *adev = ip_block->adev; 3798 3799 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3800 GRBM_STATUS, GUI_ACTIVE)) 3801 return false; 3802 else 3803 return true; 3804 } 3805 3806 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3807 { 3808 unsigned i; 3809 u32 tmp; 3810 struct amdgpu_device *adev = ip_block->adev; 3811 3812 for (i = 0; i < adev->usec_timeout; i++) { 3813 /* read MC_STATUS */ 3814 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3815 GRBM_STATUS__GUI_ACTIVE_MASK; 3816 3817 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3818 return 0; 3819 udelay(1); 3820 } 3821 return -ETIMEDOUT; 3822 } 3823 3824 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3825 { 3826 uint64_t clock = 0; 3827 3828 if (adev->smuio.funcs && 3829 adev->smuio.funcs->get_gpu_clock_counter) 3830 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3831 else 3832 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3833 3834 return clock; 3835 } 3836 3837 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3838 { 3839 struct amdgpu_device *adev = ip_block->adev; 3840 3841 switch (amdgpu_user_queue) { 3842 case -1: 3843 case 0: 3844 default: 3845 adev->gfx.disable_kq = false; 3846 adev->gfx.disable_uq = true; 3847 break; 3848 case 1: 3849 adev->gfx.disable_kq = false; 3850 adev->gfx.disable_uq = false; 3851 break; 3852 case 2: 3853 adev->gfx.disable_kq = true; 3854 adev->gfx.disable_uq = false; 3855 break; 3856 } 3857 3858 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3859 3860 if (adev->gfx.disable_kq) { 3861 adev->gfx.num_gfx_rings = 0; 3862 adev->gfx.num_compute_rings = 0; 3863 } else { 3864 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3865 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3866 AMDGPU_MAX_COMPUTE_RINGS); 3867 } 3868 3869 gfx_v12_0_set_kiq_pm4_funcs(adev); 3870 gfx_v12_0_set_ring_funcs(adev); 3871 gfx_v12_0_set_irq_funcs(adev); 3872 gfx_v12_0_set_rlc_funcs(adev); 3873 gfx_v12_0_set_mqd_funcs(adev); 3874 gfx_v12_0_set_imu_funcs(adev); 3875 3876 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3877 3878 return gfx_v12_0_init_microcode(adev); 3879 } 3880 3881 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3882 { 3883 struct amdgpu_device *adev = ip_block->adev; 3884 int r; 3885 3886 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3887 if (r) 3888 return r; 3889 3890 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3891 if (r) 3892 return r; 3893 3894 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3895 if (r) 3896 return r; 3897 3898 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3899 if (r) 3900 return r; 3901 3902 return 0; 3903 } 3904 3905 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3906 { 3907 uint32_t rlc_cntl; 3908 3909 /* if RLC is not enabled, do nothing */ 3910 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3911 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3912 } 3913 3914 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3915 int xcc_id) 3916 { 3917 uint32_t data; 3918 unsigned i; 3919 3920 data = RLC_SAFE_MODE__CMD_MASK; 3921 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3922 3923 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3924 3925 /* wait for RLC_SAFE_MODE */ 3926 for (i = 0; i < adev->usec_timeout; i++) { 3927 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3928 RLC_SAFE_MODE, CMD)) 3929 break; 3930 udelay(1); 3931 } 3932 } 3933 3934 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3935 int xcc_id) 3936 { 3937 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3938 } 3939 3940 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3941 bool enable) 3942 { 3943 uint32_t def, data; 3944 3945 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3946 return; 3947 3948 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3949 3950 if (enable) 3951 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3952 else 3953 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3954 3955 if (def != data) 3956 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3957 } 3958 3959 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3960 struct amdgpu_ring *ring, 3961 unsigned vmid) 3962 { 3963 u32 reg, data; 3964 3965 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3966 if (amdgpu_sriov_is_pp_one_vf(adev)) 3967 data = RREG32_NO_KIQ(reg); 3968 else 3969 data = RREG32(reg); 3970 3971 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3972 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3973 3974 if (amdgpu_sriov_is_pp_one_vf(adev)) 3975 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3976 else 3977 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3978 3979 if (ring 3980 && amdgpu_sriov_is_pp_one_vf(adev) 3981 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3982 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3983 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3984 amdgpu_ring_emit_wreg(ring, reg, data); 3985 } 3986 } 3987 3988 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3989 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3990 .set_safe_mode = gfx_v12_0_set_safe_mode, 3991 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3992 .init = gfx_v12_0_rlc_init, 3993 .get_csb_size = gfx_v12_0_get_csb_size, 3994 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3995 .resume = gfx_v12_0_rlc_resume, 3996 .stop = gfx_v12_0_rlc_stop, 3997 .reset = gfx_v12_0_rlc_reset, 3998 .start = gfx_v12_0_rlc_start, 3999 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4000 }; 4001 4002 #if 0 4003 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4004 { 4005 /* TODO */ 4006 } 4007 4008 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4009 { 4010 /* TODO */ 4011 } 4012 #endif 4013 4014 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4015 enum amd_powergating_state state) 4016 { 4017 struct amdgpu_device *adev = ip_block->adev; 4018 bool enable = (state == AMD_PG_STATE_GATE); 4019 4020 if (amdgpu_sriov_vf(adev)) 4021 return 0; 4022 4023 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4024 case IP_VERSION(12, 0, 0): 4025 case IP_VERSION(12, 0, 1): 4026 amdgpu_gfx_off_ctrl(adev, enable); 4027 break; 4028 default: 4029 break; 4030 } 4031 4032 return 0; 4033 } 4034 4035 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4036 bool enable) 4037 { 4038 uint32_t def, data; 4039 4040 if (!(adev->cg_flags & 4041 (AMD_CG_SUPPORT_GFX_CGCG | 4042 AMD_CG_SUPPORT_GFX_CGLS | 4043 AMD_CG_SUPPORT_GFX_3D_CGCG | 4044 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4045 return; 4046 4047 if (enable) { 4048 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4049 4050 /* unset CGCG override */ 4051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4052 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4053 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4054 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4055 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4056 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4057 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4058 4059 /* update CGCG override bits */ 4060 if (def != data) 4061 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4062 4063 /* enable cgcg FSM(0x0000363F) */ 4064 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4065 4066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4067 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4068 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4069 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4070 } 4071 4072 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4073 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4074 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4075 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4076 } 4077 4078 if (def != data) 4079 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4080 4081 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4082 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4083 4084 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4085 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4086 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4087 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4088 } 4089 4090 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4091 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4092 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4093 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4094 } 4095 4096 if (def != data) 4097 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4098 4099 /* set IDLE_POLL_COUNT(0x00900100) */ 4100 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4101 4102 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4103 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4104 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4105 4106 if (def != data) 4107 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4108 4109 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4110 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4111 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4112 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4113 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4114 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4115 4116 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4117 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4118 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4119 4120 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4121 if (adev->sdma.num_instances > 1) { 4122 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4123 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4124 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4125 } 4126 } else { 4127 /* Program RLC_CGCG_CGLS_CTRL */ 4128 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4129 4130 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4131 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4132 4133 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4134 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4135 4136 if (def != data) 4137 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4138 4139 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4140 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4141 4142 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4143 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4144 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4145 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4146 4147 if (def != data) 4148 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4149 } 4150 } 4151 4152 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4153 bool enable) 4154 { 4155 uint32_t data, def; 4156 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4157 return; 4158 4159 /* It is disabled by HW by default */ 4160 if (enable) { 4161 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4162 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4163 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4164 4165 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4166 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4167 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4168 4169 if (def != data) 4170 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4171 } 4172 } else { 4173 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4174 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4175 4176 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4177 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4178 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4179 4180 if (def != data) 4181 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4182 } 4183 } 4184 } 4185 4186 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4187 bool enable) 4188 { 4189 uint32_t def, data; 4190 4191 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4192 return; 4193 4194 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4195 4196 if (enable) 4197 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4198 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4199 else 4200 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4201 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4202 4203 if (def != data) 4204 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4205 } 4206 4207 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4208 bool enable) 4209 { 4210 uint32_t def, data; 4211 4212 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4213 return; 4214 4215 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4216 4217 if (enable) 4218 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4219 else 4220 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4221 4222 if (def != data) 4223 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4224 } 4225 4226 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4227 bool enable) 4228 { 4229 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4230 4231 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4232 4233 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4234 4235 gfx_v12_0_update_repeater_fgcg(adev, enable); 4236 4237 gfx_v12_0_update_sram_fgcg(adev, enable); 4238 4239 gfx_v12_0_update_perf_clk(adev, enable); 4240 4241 if (adev->cg_flags & 4242 (AMD_CG_SUPPORT_GFX_MGCG | 4243 AMD_CG_SUPPORT_GFX_CGLS | 4244 AMD_CG_SUPPORT_GFX_CGCG | 4245 AMD_CG_SUPPORT_GFX_3D_CGCG | 4246 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4247 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4248 4249 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4250 4251 return 0; 4252 } 4253 4254 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4255 enum amd_clockgating_state state) 4256 { 4257 struct amdgpu_device *adev = ip_block->adev; 4258 4259 if (amdgpu_sriov_vf(adev)) 4260 return 0; 4261 4262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4263 case IP_VERSION(12, 0, 0): 4264 case IP_VERSION(12, 0, 1): 4265 gfx_v12_0_update_gfx_clock_gating(adev, 4266 state == AMD_CG_STATE_GATE); 4267 break; 4268 default: 4269 break; 4270 } 4271 4272 return 0; 4273 } 4274 4275 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4276 { 4277 struct amdgpu_device *adev = ip_block->adev; 4278 int data; 4279 4280 /* AMD_CG_SUPPORT_GFX_MGCG */ 4281 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4282 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4283 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4284 4285 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4286 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4287 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4288 4289 /* AMD_CG_SUPPORT_GFX_FGCG */ 4290 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4291 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4292 4293 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4294 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4295 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4296 4297 /* AMD_CG_SUPPORT_GFX_CGCG */ 4298 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4299 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4300 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4301 4302 /* AMD_CG_SUPPORT_GFX_CGLS */ 4303 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4304 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4305 4306 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4307 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4308 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4309 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4310 4311 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4312 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4313 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4314 } 4315 4316 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4317 { 4318 /* gfx12 is 32bit rptr*/ 4319 return *(uint32_t *)ring->rptr_cpu_addr; 4320 } 4321 4322 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4323 { 4324 struct amdgpu_device *adev = ring->adev; 4325 u64 wptr; 4326 4327 /* XXX check if swapping is necessary on BE */ 4328 if (ring->use_doorbell) { 4329 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4330 } else { 4331 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4332 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4333 } 4334 4335 return wptr; 4336 } 4337 4338 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4339 { 4340 struct amdgpu_device *adev = ring->adev; 4341 4342 if (ring->use_doorbell) { 4343 /* XXX check if swapping is necessary on BE */ 4344 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4345 ring->wptr); 4346 WDOORBELL64(ring->doorbell_index, ring->wptr); 4347 } else { 4348 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4349 lower_32_bits(ring->wptr)); 4350 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4351 upper_32_bits(ring->wptr)); 4352 } 4353 } 4354 4355 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4356 { 4357 /* gfx12 hardware is 32bit rptr */ 4358 return *(uint32_t *)ring->rptr_cpu_addr; 4359 } 4360 4361 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4362 { 4363 u64 wptr; 4364 4365 /* XXX check if swapping is necessary on BE */ 4366 if (ring->use_doorbell) 4367 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4368 else 4369 BUG(); 4370 return wptr; 4371 } 4372 4373 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4374 { 4375 struct amdgpu_device *adev = ring->adev; 4376 4377 /* XXX check if swapping is necessary on BE */ 4378 if (ring->use_doorbell) { 4379 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4380 ring->wptr); 4381 WDOORBELL64(ring->doorbell_index, ring->wptr); 4382 } else { 4383 BUG(); /* only DOORBELL method supported on gfx12 now */ 4384 } 4385 } 4386 4387 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4388 { 4389 struct amdgpu_device *adev = ring->adev; 4390 u32 ref_and_mask, reg_mem_engine; 4391 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4392 4393 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4394 switch (ring->me) { 4395 case 1: 4396 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4397 break; 4398 case 2: 4399 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4400 break; 4401 default: 4402 return; 4403 } 4404 reg_mem_engine = 0; 4405 } else { 4406 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4407 reg_mem_engine = 1; /* pfp */ 4408 } 4409 4410 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4411 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4412 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4413 ref_and_mask, ref_and_mask, 0x20); 4414 } 4415 4416 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4417 struct amdgpu_job *job, 4418 struct amdgpu_ib *ib, 4419 uint32_t flags) 4420 { 4421 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4422 u32 header, control = 0; 4423 4424 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4425 4426 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4427 4428 control |= ib->length_dw | (vmid << 24); 4429 4430 amdgpu_ring_write(ring, header); 4431 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4432 amdgpu_ring_write(ring, 4433 #ifdef __BIG_ENDIAN 4434 (2 << 0) | 4435 #endif 4436 lower_32_bits(ib->gpu_addr)); 4437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4438 amdgpu_ring_write(ring, control); 4439 } 4440 4441 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4442 struct amdgpu_job *job, 4443 struct amdgpu_ib *ib, 4444 uint32_t flags) 4445 { 4446 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4447 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4448 4449 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4450 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4451 amdgpu_ring_write(ring, 4452 #ifdef __BIG_ENDIAN 4453 (2 << 0) | 4454 #endif 4455 lower_32_bits(ib->gpu_addr)); 4456 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4457 amdgpu_ring_write(ring, control); 4458 } 4459 4460 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4461 u64 seq, unsigned flags) 4462 { 4463 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4464 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4465 4466 /* RELEASE_MEM - flush caches, send int */ 4467 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4468 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4469 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4470 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4471 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4472 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4473 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4474 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4475 4476 /* 4477 * the address should be Qword aligned if 64bit write, Dword 4478 * aligned if only send 32bit data low (discard data high) 4479 */ 4480 if (write64bit) 4481 BUG_ON(addr & 0x7); 4482 else 4483 BUG_ON(addr & 0x3); 4484 amdgpu_ring_write(ring, lower_32_bits(addr)); 4485 amdgpu_ring_write(ring, upper_32_bits(addr)); 4486 amdgpu_ring_write(ring, lower_32_bits(seq)); 4487 amdgpu_ring_write(ring, upper_32_bits(seq)); 4488 amdgpu_ring_write(ring, 0); 4489 } 4490 4491 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4492 { 4493 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4494 uint32_t seq = ring->fence_drv.sync_seq; 4495 uint64_t addr = ring->fence_drv.gpu_addr; 4496 4497 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4498 upper_32_bits(addr), seq, 0xffffffff, 4); 4499 } 4500 4501 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4502 uint16_t pasid, uint32_t flush_type, 4503 bool all_hub, uint8_t dst_sel) 4504 { 4505 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4506 amdgpu_ring_write(ring, 4507 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4508 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4509 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4510 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4511 } 4512 4513 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4514 unsigned vmid, uint64_t pd_addr) 4515 { 4516 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4517 4518 /* compute doesn't have PFP */ 4519 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4520 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4521 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4522 amdgpu_ring_write(ring, 0x0); 4523 } 4524 } 4525 4526 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4527 u64 seq, unsigned int flags) 4528 { 4529 struct amdgpu_device *adev = ring->adev; 4530 4531 /* we only allocate 32bit for each seq wb address */ 4532 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4533 4534 /* write fence seq to the "addr" */ 4535 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4536 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4537 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4538 amdgpu_ring_write(ring, lower_32_bits(addr)); 4539 amdgpu_ring_write(ring, upper_32_bits(addr)); 4540 amdgpu_ring_write(ring, lower_32_bits(seq)); 4541 4542 if (flags & AMDGPU_FENCE_FLAG_INT) { 4543 /* set register to trigger INT */ 4544 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4545 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4546 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4547 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4548 amdgpu_ring_write(ring, 0); 4549 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4550 } 4551 } 4552 4553 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4554 uint32_t flags) 4555 { 4556 uint32_t dw2 = 0; 4557 4558 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4559 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4560 /* set load_global_config & load_global_uconfig */ 4561 dw2 |= 0x8001; 4562 /* set load_cs_sh_regs */ 4563 dw2 |= 0x01000000; 4564 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4565 dw2 |= 0x10002; 4566 } 4567 4568 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4569 amdgpu_ring_write(ring, dw2); 4570 amdgpu_ring_write(ring, 0); 4571 } 4572 4573 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4574 uint64_t addr) 4575 { 4576 unsigned ret; 4577 4578 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4579 amdgpu_ring_write(ring, lower_32_bits(addr)); 4580 amdgpu_ring_write(ring, upper_32_bits(addr)); 4581 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4582 amdgpu_ring_write(ring, 0); 4583 ret = ring->wptr & ring->buf_mask; 4584 /* patch dummy value later */ 4585 amdgpu_ring_write(ring, 0); 4586 4587 return ret; 4588 } 4589 4590 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4591 { 4592 int i, r = 0; 4593 struct amdgpu_device *adev = ring->adev; 4594 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4595 struct amdgpu_ring *kiq_ring = &kiq->ring; 4596 unsigned long flags; 4597 4598 if (adev->enable_mes) 4599 return -EINVAL; 4600 4601 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4602 return -EINVAL; 4603 4604 spin_lock_irqsave(&kiq->ring_lock, flags); 4605 4606 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4607 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4608 return -ENOMEM; 4609 } 4610 4611 /* assert preemption condition */ 4612 amdgpu_ring_set_preempt_cond_exec(ring, false); 4613 4614 /* assert IB preemption, emit the trailing fence */ 4615 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4616 ring->trail_fence_gpu_addr, 4617 ++ring->trail_seq); 4618 amdgpu_ring_commit(kiq_ring); 4619 4620 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4621 4622 /* poll the trailing fence */ 4623 for (i = 0; i < adev->usec_timeout; i++) { 4624 if (ring->trail_seq == 4625 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4626 break; 4627 udelay(1); 4628 } 4629 4630 if (i >= adev->usec_timeout) { 4631 r = -EINVAL; 4632 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4633 } 4634 4635 /* deassert preemption condition */ 4636 amdgpu_ring_set_preempt_cond_exec(ring, true); 4637 return r; 4638 } 4639 4640 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4641 bool start, 4642 bool secure) 4643 { 4644 uint32_t v = secure ? FRAME_TMZ : 0; 4645 4646 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4647 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4648 } 4649 4650 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4651 uint32_t reg_val_offs) 4652 { 4653 struct amdgpu_device *adev = ring->adev; 4654 4655 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4656 amdgpu_ring_write(ring, 0 | /* src: register*/ 4657 (5 << 8) | /* dst: memory */ 4658 (1 << 20)); /* write confirm */ 4659 amdgpu_ring_write(ring, reg); 4660 amdgpu_ring_write(ring, 0); 4661 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4662 reg_val_offs * 4)); 4663 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4664 reg_val_offs * 4)); 4665 } 4666 4667 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4668 uint32_t reg, 4669 uint32_t val) 4670 { 4671 uint32_t cmd = 0; 4672 4673 switch (ring->funcs->type) { 4674 case AMDGPU_RING_TYPE_GFX: 4675 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4676 break; 4677 case AMDGPU_RING_TYPE_KIQ: 4678 cmd = (1 << 16); /* no inc addr */ 4679 break; 4680 default: 4681 cmd = WR_CONFIRM; 4682 break; 4683 } 4684 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4685 amdgpu_ring_write(ring, cmd); 4686 amdgpu_ring_write(ring, reg); 4687 amdgpu_ring_write(ring, 0); 4688 amdgpu_ring_write(ring, val); 4689 } 4690 4691 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4692 uint32_t val, uint32_t mask) 4693 { 4694 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4695 } 4696 4697 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4698 uint32_t reg0, uint32_t reg1, 4699 uint32_t ref, uint32_t mask) 4700 { 4701 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4702 4703 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4704 ref, mask, 0x20); 4705 } 4706 4707 static void 4708 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4709 uint32_t me, uint32_t pipe, 4710 enum amdgpu_interrupt_state state) 4711 { 4712 uint32_t cp_int_cntl, cp_int_cntl_reg; 4713 4714 if (!me) { 4715 switch (pipe) { 4716 case 0: 4717 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4718 break; 4719 default: 4720 DRM_DEBUG("invalid pipe %d\n", pipe); 4721 return; 4722 } 4723 } else { 4724 DRM_DEBUG("invalid me %d\n", me); 4725 return; 4726 } 4727 4728 switch (state) { 4729 case AMDGPU_IRQ_STATE_DISABLE: 4730 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4731 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4732 TIME_STAMP_INT_ENABLE, 0); 4733 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4734 GENERIC0_INT_ENABLE, 0); 4735 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4736 break; 4737 case AMDGPU_IRQ_STATE_ENABLE: 4738 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4739 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4740 TIME_STAMP_INT_ENABLE, 1); 4741 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4742 GENERIC0_INT_ENABLE, 1); 4743 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4744 break; 4745 default: 4746 break; 4747 } 4748 } 4749 4750 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4751 int me, int pipe, 4752 enum amdgpu_interrupt_state state) 4753 { 4754 u32 mec_int_cntl, mec_int_cntl_reg; 4755 4756 /* 4757 * amdgpu controls only the first MEC. That's why this function only 4758 * handles the setting of interrupts for this specific MEC. All other 4759 * pipes' interrupts are set by amdkfd. 4760 */ 4761 4762 if (me == 1) { 4763 switch (pipe) { 4764 case 0: 4765 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4766 break; 4767 case 1: 4768 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4769 break; 4770 default: 4771 DRM_DEBUG("invalid pipe %d\n", pipe); 4772 return; 4773 } 4774 } else { 4775 DRM_DEBUG("invalid me %d\n", me); 4776 return; 4777 } 4778 4779 switch (state) { 4780 case AMDGPU_IRQ_STATE_DISABLE: 4781 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4782 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4783 TIME_STAMP_INT_ENABLE, 0); 4784 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4785 GENERIC0_INT_ENABLE, 0); 4786 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4787 break; 4788 case AMDGPU_IRQ_STATE_ENABLE: 4789 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4790 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4791 TIME_STAMP_INT_ENABLE, 1); 4792 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4793 GENERIC0_INT_ENABLE, 1); 4794 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4795 break; 4796 default: 4797 break; 4798 } 4799 } 4800 4801 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4802 struct amdgpu_irq_src *src, 4803 unsigned type, 4804 enum amdgpu_interrupt_state state) 4805 { 4806 switch (type) { 4807 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4808 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4809 break; 4810 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4811 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4812 break; 4813 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4814 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4815 break; 4816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4817 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4818 break; 4819 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4820 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4821 break; 4822 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4823 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4824 break; 4825 default: 4826 break; 4827 } 4828 return 0; 4829 } 4830 4831 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4832 struct amdgpu_irq_src *source, 4833 struct amdgpu_iv_entry *entry) 4834 { 4835 u32 doorbell_offset = entry->src_data[0]; 4836 u8 me_id, pipe_id, queue_id; 4837 struct amdgpu_ring *ring; 4838 int i; 4839 4840 DRM_DEBUG("IH: CP EOP\n"); 4841 4842 if (adev->enable_mes && doorbell_offset) { 4843 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4844 struct xarray *xa = &adev->userq_xa; 4845 unsigned long flags; 4846 4847 xa_lock_irqsave(xa, flags); 4848 fence_drv = xa_load(xa, doorbell_offset); 4849 if (fence_drv) 4850 amdgpu_userq_fence_driver_process(fence_drv); 4851 xa_unlock_irqrestore(xa, flags); 4852 } else { 4853 me_id = (entry->ring_id & 0x0c) >> 2; 4854 pipe_id = (entry->ring_id & 0x03) >> 0; 4855 queue_id = (entry->ring_id & 0x70) >> 4; 4856 4857 switch (me_id) { 4858 case 0: 4859 if (pipe_id == 0) 4860 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4861 else 4862 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4863 break; 4864 case 1: 4865 case 2: 4866 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4867 ring = &adev->gfx.compute_ring[i]; 4868 /* Per-queue interrupt is supported for MEC starting from VI. 4869 * The interrupt can only be enabled/disabled per pipe instead 4870 * of per queue. 4871 */ 4872 if ((ring->me == me_id) && 4873 (ring->pipe == pipe_id) && 4874 (ring->queue == queue_id)) 4875 amdgpu_fence_process(ring); 4876 } 4877 break; 4878 } 4879 } 4880 4881 return 0; 4882 } 4883 4884 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4885 struct amdgpu_irq_src *source, 4886 unsigned int type, 4887 enum amdgpu_interrupt_state state) 4888 { 4889 u32 cp_int_cntl_reg, cp_int_cntl; 4890 int i, j; 4891 4892 switch (state) { 4893 case AMDGPU_IRQ_STATE_DISABLE: 4894 case AMDGPU_IRQ_STATE_ENABLE: 4895 for (i = 0; i < adev->gfx.me.num_me; i++) { 4896 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4897 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4898 4899 if (cp_int_cntl_reg) { 4900 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4901 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4902 PRIV_REG_INT_ENABLE, 4903 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4904 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4905 } 4906 } 4907 } 4908 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4909 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4910 /* MECs start at 1 */ 4911 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4912 4913 if (cp_int_cntl_reg) { 4914 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4915 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4916 PRIV_REG_INT_ENABLE, 4917 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4918 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4919 } 4920 } 4921 } 4922 break; 4923 default: 4924 break; 4925 } 4926 4927 return 0; 4928 } 4929 4930 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4931 struct amdgpu_irq_src *source, 4932 unsigned type, 4933 enum amdgpu_interrupt_state state) 4934 { 4935 u32 cp_int_cntl_reg, cp_int_cntl; 4936 int i, j; 4937 4938 switch (state) { 4939 case AMDGPU_IRQ_STATE_DISABLE: 4940 case AMDGPU_IRQ_STATE_ENABLE: 4941 for (i = 0; i < adev->gfx.me.num_me; i++) { 4942 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4943 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4944 4945 if (cp_int_cntl_reg) { 4946 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4947 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4948 OPCODE_ERROR_INT_ENABLE, 4949 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4950 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4951 } 4952 } 4953 } 4954 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4955 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4956 /* MECs start at 1 */ 4957 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4958 4959 if (cp_int_cntl_reg) { 4960 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4961 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4962 OPCODE_ERROR_INT_ENABLE, 4963 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4964 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4965 } 4966 } 4967 } 4968 break; 4969 default: 4970 break; 4971 } 4972 return 0; 4973 } 4974 4975 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4976 struct amdgpu_irq_src *source, 4977 unsigned int type, 4978 enum amdgpu_interrupt_state state) 4979 { 4980 u32 cp_int_cntl_reg, cp_int_cntl; 4981 int i, j; 4982 4983 switch (state) { 4984 case AMDGPU_IRQ_STATE_DISABLE: 4985 case AMDGPU_IRQ_STATE_ENABLE: 4986 for (i = 0; i < adev->gfx.me.num_me; i++) { 4987 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4988 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4989 4990 if (cp_int_cntl_reg) { 4991 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4992 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4993 PRIV_INSTR_INT_ENABLE, 4994 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4995 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4996 } 4997 } 4998 } 4999 break; 5000 default: 5001 break; 5002 } 5003 5004 return 0; 5005 } 5006 5007 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5008 struct amdgpu_iv_entry *entry) 5009 { 5010 u8 me_id, pipe_id, queue_id; 5011 struct amdgpu_ring *ring; 5012 int i; 5013 5014 me_id = (entry->ring_id & 0x0c) >> 2; 5015 pipe_id = (entry->ring_id & 0x03) >> 0; 5016 queue_id = (entry->ring_id & 0x70) >> 4; 5017 5018 if (!adev->gfx.disable_kq) { 5019 switch (me_id) { 5020 case 0: 5021 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5022 ring = &adev->gfx.gfx_ring[i]; 5023 if (ring->me == me_id && ring->pipe == pipe_id && 5024 ring->queue == queue_id) 5025 drm_sched_fault(&ring->sched); 5026 } 5027 break; 5028 case 1: 5029 case 2: 5030 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5031 ring = &adev->gfx.compute_ring[i]; 5032 if (ring->me == me_id && ring->pipe == pipe_id && 5033 ring->queue == queue_id) 5034 drm_sched_fault(&ring->sched); 5035 } 5036 break; 5037 default: 5038 BUG(); 5039 break; 5040 } 5041 } 5042 } 5043 5044 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5045 struct amdgpu_irq_src *source, 5046 struct amdgpu_iv_entry *entry) 5047 { 5048 DRM_ERROR("Illegal register access in command stream\n"); 5049 gfx_v12_0_handle_priv_fault(adev, entry); 5050 return 0; 5051 } 5052 5053 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5054 struct amdgpu_irq_src *source, 5055 struct amdgpu_iv_entry *entry) 5056 { 5057 DRM_ERROR("Illegal opcode in command stream \n"); 5058 gfx_v12_0_handle_priv_fault(adev, entry); 5059 return 0; 5060 } 5061 5062 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5063 struct amdgpu_irq_src *source, 5064 struct amdgpu_iv_entry *entry) 5065 { 5066 DRM_ERROR("Illegal instruction in command stream\n"); 5067 gfx_v12_0_handle_priv_fault(adev, entry); 5068 return 0; 5069 } 5070 5071 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5072 { 5073 const unsigned int gcr_cntl = 5074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5079 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5080 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5081 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5082 5083 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5084 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5085 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5086 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5087 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5088 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5089 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5090 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5091 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5092 } 5093 5094 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5095 { 5096 /* Header itself is a NOP packet */ 5097 if (num_nop == 1) { 5098 amdgpu_ring_write(ring, ring->funcs->nop); 5099 return; 5100 } 5101 5102 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5103 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5104 5105 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5106 amdgpu_ring_insert_nop(ring, num_nop - 1); 5107 } 5108 5109 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5110 { 5111 /* Emit the cleaner shader */ 5112 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5113 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5114 } 5115 5116 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5117 { 5118 struct amdgpu_device *adev = ip_block->adev; 5119 uint32_t i, j, k, reg, index = 0; 5120 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5121 5122 if (!adev->gfx.ip_dump_core) 5123 return; 5124 5125 for (i = 0; i < reg_count; i++) 5126 drm_printf(p, "%-50s \t 0x%08x\n", 5127 gc_reg_list_12_0[i].reg_name, 5128 adev->gfx.ip_dump_core[i]); 5129 5130 /* print compute queue registers for all instances */ 5131 if (!adev->gfx.ip_dump_compute_queues) 5132 return; 5133 5134 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5135 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5136 adev->gfx.mec.num_mec, 5137 adev->gfx.mec.num_pipe_per_mec, 5138 adev->gfx.mec.num_queue_per_pipe); 5139 5140 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5141 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5142 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5143 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5144 for (reg = 0; reg < reg_count; reg++) { 5145 drm_printf(p, "%-50s \t 0x%08x\n", 5146 gc_cp_reg_list_12[reg].reg_name, 5147 adev->gfx.ip_dump_compute_queues[index + reg]); 5148 } 5149 index += reg_count; 5150 } 5151 } 5152 } 5153 5154 /* print gfx queue registers for all instances */ 5155 if (!adev->gfx.ip_dump_gfx_queues) 5156 return; 5157 5158 index = 0; 5159 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5160 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5161 adev->gfx.me.num_me, 5162 adev->gfx.me.num_pipe_per_me, 5163 adev->gfx.me.num_queue_per_pipe); 5164 5165 for (i = 0; i < adev->gfx.me.num_me; i++) { 5166 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5167 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5168 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5169 for (reg = 0; reg < reg_count; reg++) { 5170 drm_printf(p, "%-50s \t 0x%08x\n", 5171 gc_gfx_queue_reg_list_12[reg].reg_name, 5172 adev->gfx.ip_dump_gfx_queues[index + reg]); 5173 } 5174 index += reg_count; 5175 } 5176 } 5177 } 5178 } 5179 5180 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5181 { 5182 struct amdgpu_device *adev = ip_block->adev; 5183 uint32_t i, j, k, reg, index = 0; 5184 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5185 5186 if (!adev->gfx.ip_dump_core) 5187 return; 5188 5189 amdgpu_gfx_off_ctrl(adev, false); 5190 for (i = 0; i < reg_count; i++) 5191 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5192 amdgpu_gfx_off_ctrl(adev, true); 5193 5194 /* dump compute queue registers for all instances */ 5195 if (!adev->gfx.ip_dump_compute_queues) 5196 return; 5197 5198 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5199 amdgpu_gfx_off_ctrl(adev, false); 5200 mutex_lock(&adev->srbm_mutex); 5201 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5202 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5203 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5204 /* ME0 is for GFX so start from 1 for CP */ 5205 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5206 for (reg = 0; reg < reg_count; reg++) { 5207 adev->gfx.ip_dump_compute_queues[index + reg] = 5208 RREG32(SOC15_REG_ENTRY_OFFSET( 5209 gc_cp_reg_list_12[reg])); 5210 } 5211 index += reg_count; 5212 } 5213 } 5214 } 5215 soc24_grbm_select(adev, 0, 0, 0, 0); 5216 mutex_unlock(&adev->srbm_mutex); 5217 amdgpu_gfx_off_ctrl(adev, true); 5218 5219 /* dump gfx queue registers for all instances */ 5220 if (!adev->gfx.ip_dump_gfx_queues) 5221 return; 5222 5223 index = 0; 5224 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5225 amdgpu_gfx_off_ctrl(adev, false); 5226 mutex_lock(&adev->srbm_mutex); 5227 for (i = 0; i < adev->gfx.me.num_me; i++) { 5228 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5229 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5230 soc24_grbm_select(adev, i, j, k, 0); 5231 5232 for (reg = 0; reg < reg_count; reg++) { 5233 adev->gfx.ip_dump_gfx_queues[index + reg] = 5234 RREG32(SOC15_REG_ENTRY_OFFSET( 5235 gc_gfx_queue_reg_list_12[reg])); 5236 } 5237 index += reg_count; 5238 } 5239 } 5240 } 5241 soc24_grbm_select(adev, 0, 0, 0, 0); 5242 mutex_unlock(&adev->srbm_mutex); 5243 amdgpu_gfx_off_ctrl(adev, true); 5244 } 5245 5246 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5247 { 5248 /* Disable the pipe reset until the CPFW fully support it.*/ 5249 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5250 return false; 5251 } 5252 5253 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5254 { 5255 struct amdgpu_device *adev = ring->adev; 5256 uint32_t reset_pipe = 0, clean_pipe = 0; 5257 int r; 5258 5259 if (!gfx_v12_pipe_reset_support(adev)) 5260 return -EOPNOTSUPP; 5261 5262 gfx_v12_0_set_safe_mode(adev, 0); 5263 mutex_lock(&adev->srbm_mutex); 5264 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5265 5266 switch (ring->pipe) { 5267 case 0: 5268 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5269 PFP_PIPE0_RESET, 1); 5270 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5271 ME_PIPE0_RESET, 1); 5272 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5273 PFP_PIPE0_RESET, 0); 5274 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5275 ME_PIPE0_RESET, 0); 5276 break; 5277 case 1: 5278 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5279 PFP_PIPE1_RESET, 1); 5280 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5281 ME_PIPE1_RESET, 1); 5282 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5283 PFP_PIPE1_RESET, 0); 5284 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5285 ME_PIPE1_RESET, 0); 5286 break; 5287 default: 5288 break; 5289 } 5290 5291 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5292 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5293 5294 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5295 RS64_FW_UC_START_ADDR_LO; 5296 soc24_grbm_select(adev, 0, 0, 0, 0); 5297 mutex_unlock(&adev->srbm_mutex); 5298 gfx_v12_0_unset_safe_mode(adev, 0); 5299 5300 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5301 r == 0 ? "successfully" : "failed"); 5302 /* Sometimes the ME start pc counter can't cache correctly, so the 5303 * PC check only as a reference and pipe reset result rely on the 5304 * later ring test. 5305 */ 5306 return 0; 5307 } 5308 5309 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5310 unsigned int vmid, 5311 struct amdgpu_fence *timedout_fence) 5312 { 5313 struct amdgpu_device *adev = ring->adev; 5314 int r; 5315 5316 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5317 5318 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5319 if (r) { 5320 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5321 r = gfx_v12_reset_gfx_pipe(ring); 5322 if (r) 5323 return r; 5324 } 5325 5326 r = gfx_v12_0_kgq_init_queue(ring, true); 5327 if (r) { 5328 dev_err(adev->dev, "failed to init kgq\n"); 5329 return r; 5330 } 5331 5332 r = amdgpu_mes_map_legacy_queue(adev, ring); 5333 if (r) { 5334 dev_err(adev->dev, "failed to remap kgq\n"); 5335 return r; 5336 } 5337 5338 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5339 } 5340 5341 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5342 { 5343 struct amdgpu_device *adev = ring->adev; 5344 uint32_t reset_pipe = 0, clean_pipe = 0; 5345 int r = 0; 5346 5347 if (!gfx_v12_pipe_reset_support(adev)) 5348 return -EOPNOTSUPP; 5349 5350 gfx_v12_0_set_safe_mode(adev, 0); 5351 mutex_lock(&adev->srbm_mutex); 5352 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5353 5354 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5355 clean_pipe = reset_pipe; 5356 5357 if (adev->gfx.rs64_enable) { 5358 switch (ring->pipe) { 5359 case 0: 5360 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5361 MEC_PIPE0_RESET, 1); 5362 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5363 MEC_PIPE0_RESET, 0); 5364 break; 5365 case 1: 5366 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5367 MEC_PIPE1_RESET, 1); 5368 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5369 MEC_PIPE1_RESET, 0); 5370 break; 5371 case 2: 5372 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5373 MEC_PIPE2_RESET, 1); 5374 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5375 MEC_PIPE2_RESET, 0); 5376 break; 5377 case 3: 5378 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5379 MEC_PIPE3_RESET, 1); 5380 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5381 MEC_PIPE3_RESET, 0); 5382 break; 5383 default: 5384 break; 5385 } 5386 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5387 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5388 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5389 RS64_FW_UC_START_ADDR_LO; 5390 } else { 5391 switch (ring->pipe) { 5392 case 0: 5393 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5394 MEC_ME1_PIPE0_RESET, 1); 5395 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5396 MEC_ME1_PIPE0_RESET, 0); 5397 break; 5398 case 1: 5399 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5400 MEC_ME1_PIPE1_RESET, 1); 5401 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5402 MEC_ME1_PIPE1_RESET, 0); 5403 break; 5404 default: 5405 break; 5406 } 5407 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5408 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5409 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5410 * the driver won't run into the F32 mode. 5411 */ 5412 } 5413 5414 soc24_grbm_select(adev, 0, 0, 0, 0); 5415 mutex_unlock(&adev->srbm_mutex); 5416 gfx_v12_0_unset_safe_mode(adev, 0); 5417 5418 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5419 r == 0 ? "successfully" : "failed"); 5420 /* Need the ring test to verify the pipe reset result.*/ 5421 return 0; 5422 } 5423 5424 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5425 unsigned int vmid, 5426 struct amdgpu_fence *timedout_fence) 5427 { 5428 struct amdgpu_device *adev = ring->adev; 5429 int r; 5430 5431 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5432 5433 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5434 if (r) { 5435 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5436 r = gfx_v12_0_reset_compute_pipe(ring); 5437 if (r) 5438 return r; 5439 } 5440 5441 r = gfx_v12_0_kcq_init_queue(ring, true); 5442 if (r) { 5443 dev_err(adev->dev, "failed to init kcq\n"); 5444 return r; 5445 } 5446 r = amdgpu_mes_map_legacy_queue(adev, ring); 5447 if (r) { 5448 dev_err(adev->dev, "failed to remap kcq\n"); 5449 return r; 5450 } 5451 5452 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5453 } 5454 5455 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5456 { 5457 amdgpu_gfx_profile_ring_begin_use(ring); 5458 5459 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5460 } 5461 5462 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5463 { 5464 amdgpu_gfx_profile_ring_end_use(ring); 5465 5466 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5467 } 5468 5469 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5470 .name = "gfx_v12_0", 5471 .early_init = gfx_v12_0_early_init, 5472 .late_init = gfx_v12_0_late_init, 5473 .sw_init = gfx_v12_0_sw_init, 5474 .sw_fini = gfx_v12_0_sw_fini, 5475 .hw_init = gfx_v12_0_hw_init, 5476 .hw_fini = gfx_v12_0_hw_fini, 5477 .suspend = gfx_v12_0_suspend, 5478 .resume = gfx_v12_0_resume, 5479 .is_idle = gfx_v12_0_is_idle, 5480 .wait_for_idle = gfx_v12_0_wait_for_idle, 5481 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5482 .set_powergating_state = gfx_v12_0_set_powergating_state, 5483 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5484 .dump_ip_state = gfx_v12_ip_dump, 5485 .print_ip_state = gfx_v12_ip_print, 5486 }; 5487 5488 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5489 .type = AMDGPU_RING_TYPE_GFX, 5490 .align_mask = 0xff, 5491 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5492 .support_64bit_ptrs = true, 5493 .secure_submission_supported = true, 5494 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5495 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5496 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5497 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5498 5 + /* COND_EXEC */ 5499 7 + /* PIPELINE_SYNC */ 5500 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5501 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5502 2 + /* VM_FLUSH */ 5503 8 + /* FENCE for VM_FLUSH */ 5504 5 + /* COND_EXEC */ 5505 7 + /* HDP_flush */ 5506 4 + /* VGT_flush */ 5507 31 + /* DE_META */ 5508 3 + /* CNTX_CTRL */ 5509 5 + /* HDP_INVL */ 5510 8 + 8 + /* FENCE x2 */ 5511 8 + /* gfx_v12_0_emit_mem_sync */ 5512 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5513 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5514 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5515 .emit_fence = gfx_v12_0_ring_emit_fence, 5516 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5517 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5518 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5519 .test_ring = gfx_v12_0_ring_test_ring, 5520 .test_ib = gfx_v12_0_ring_test_ib, 5521 .insert_nop = gfx_v12_ring_insert_nop, 5522 .pad_ib = amdgpu_ring_generic_pad_ib, 5523 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5524 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5525 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5526 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5527 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5528 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5529 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5530 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5531 .reset = gfx_v12_0_reset_kgq, 5532 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5533 .begin_use = gfx_v12_0_ring_begin_use, 5534 .end_use = gfx_v12_0_ring_end_use, 5535 }; 5536 5537 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5538 .type = AMDGPU_RING_TYPE_COMPUTE, 5539 .align_mask = 0xff, 5540 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5541 .support_64bit_ptrs = true, 5542 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5543 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5544 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5545 .emit_frame_size = 5546 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5547 5 + /* hdp invalidate */ 5548 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5549 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5550 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5551 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5552 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5553 8 + /* gfx_v12_0_emit_mem_sync */ 5554 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5555 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5556 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5557 .emit_fence = gfx_v12_0_ring_emit_fence, 5558 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5559 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5560 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5561 .test_ring = gfx_v12_0_ring_test_ring, 5562 .test_ib = gfx_v12_0_ring_test_ib, 5563 .insert_nop = gfx_v12_ring_insert_nop, 5564 .pad_ib = amdgpu_ring_generic_pad_ib, 5565 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5566 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5567 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5568 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5569 .reset = gfx_v12_0_reset_kcq, 5570 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5571 .begin_use = gfx_v12_0_ring_begin_use, 5572 .end_use = gfx_v12_0_ring_end_use, 5573 }; 5574 5575 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5576 .type = AMDGPU_RING_TYPE_KIQ, 5577 .align_mask = 0xff, 5578 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5579 .support_64bit_ptrs = true, 5580 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5581 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5582 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5583 .emit_frame_size = 5584 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5585 5 + /*hdp invalidate */ 5586 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5587 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5588 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5589 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5590 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5591 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5592 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5593 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5594 .test_ring = gfx_v12_0_ring_test_ring, 5595 .test_ib = gfx_v12_0_ring_test_ib, 5596 .insert_nop = amdgpu_ring_insert_nop, 5597 .pad_ib = amdgpu_ring_generic_pad_ib, 5598 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5599 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5600 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5601 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5602 }; 5603 5604 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5605 { 5606 int i; 5607 5608 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5609 5610 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5611 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5612 5613 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5614 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5615 } 5616 5617 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5618 .set = gfx_v12_0_set_eop_interrupt_state, 5619 .process = gfx_v12_0_eop_irq, 5620 }; 5621 5622 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5623 .set = gfx_v12_0_set_priv_reg_fault_state, 5624 .process = gfx_v12_0_priv_reg_irq, 5625 }; 5626 5627 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5628 .set = gfx_v12_0_set_bad_op_fault_state, 5629 .process = gfx_v12_0_bad_op_irq, 5630 }; 5631 5632 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5633 .set = gfx_v12_0_set_priv_inst_fault_state, 5634 .process = gfx_v12_0_priv_inst_irq, 5635 }; 5636 5637 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5638 { 5639 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5640 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5641 5642 adev->gfx.priv_reg_irq.num_types = 1; 5643 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5644 5645 adev->gfx.bad_op_irq.num_types = 1; 5646 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5647 5648 adev->gfx.priv_inst_irq.num_types = 1; 5649 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5650 } 5651 5652 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5653 { 5654 if (adev->flags & AMD_IS_APU) 5655 adev->gfx.imu.mode = MISSION_MODE; 5656 else 5657 adev->gfx.imu.mode = DEBUG_MODE; 5658 5659 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5660 } 5661 5662 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5663 { 5664 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5665 } 5666 5667 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5668 { 5669 /* set gfx eng mqd */ 5670 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5671 sizeof(struct v12_gfx_mqd); 5672 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5673 gfx_v12_0_gfx_mqd_init; 5674 /* set compute eng mqd */ 5675 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5676 sizeof(struct v12_compute_mqd); 5677 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5678 gfx_v12_0_compute_mqd_init; 5679 } 5680 5681 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5682 u32 bitmap) 5683 { 5684 u32 data; 5685 5686 if (!bitmap) 5687 return; 5688 5689 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5690 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5691 5692 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5693 } 5694 5695 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5696 { 5697 u32 data, wgp_bitmask; 5698 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5699 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5700 5701 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5702 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5703 5704 wgp_bitmask = 5705 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5706 5707 return (~data) & wgp_bitmask; 5708 } 5709 5710 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5711 { 5712 u32 wgp_idx, wgp_active_bitmap; 5713 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5714 5715 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5716 cu_active_bitmap = 0; 5717 5718 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5719 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5720 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5721 if (wgp_active_bitmap & (1 << wgp_idx)) 5722 cu_active_bitmap |= cu_bitmap_per_wgp; 5723 } 5724 5725 return cu_active_bitmap; 5726 } 5727 5728 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5729 struct amdgpu_cu_info *cu_info) 5730 { 5731 int i, j, k, counter, active_cu_number = 0; 5732 u32 mask, bitmap; 5733 unsigned disable_masks[8 * 2]; 5734 5735 if (!adev || !cu_info) 5736 return -EINVAL; 5737 5738 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5739 5740 mutex_lock(&adev->grbm_idx_mutex); 5741 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5742 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5743 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5744 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5745 continue; 5746 mask = 1; 5747 counter = 0; 5748 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5749 if (i < 8 && j < 2) 5750 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5751 adev, disable_masks[i * 2 + j]); 5752 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5753 5754 /** 5755 * GFX12 could support more than 4 SEs, while the bitmap 5756 * in cu_info struct is 4x4 and ioctl interface struct 5757 * drm_amdgpu_info_device should keep stable. 5758 * So we use last two columns of bitmap to store cu mask for 5759 * SEs 4 to 7, the layout of the bitmap is as below: 5760 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5761 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5762 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5763 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5764 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5765 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5766 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5767 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5768 */ 5769 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5770 5771 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5772 if (bitmap & mask) 5773 counter++; 5774 5775 mask <<= 1; 5776 } 5777 active_cu_number += counter; 5778 } 5779 } 5780 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5781 mutex_unlock(&adev->grbm_idx_mutex); 5782 5783 cu_info->number = active_cu_number; 5784 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5785 5786 return 0; 5787 } 5788 5789 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5790 .type = AMD_IP_BLOCK_TYPE_GFX, 5791 .major = 12, 5792 .minor = 0, 5793 .rev = 0, 5794 .funcs = &gfx_v12_0_ip_funcs, 5795 }; 5796