1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 359 gpu_addr, seq, 0); 360 return; 361 } 362 363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 365 PACKET3_UNMAP_QUEUES_ACTION(action) | 366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 369 amdgpu_ring_write(kiq_ring, 370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 371 372 if (action == PREEMPT_QUEUES_NO_UNMAP) { 373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, seq); 376 } else { 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 } 381 } 382 383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 384 struct amdgpu_ring *ring, 385 u64 addr, u64 seq) 386 { 387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 388 389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 390 amdgpu_ring_write(kiq_ring, 391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 393 PACKET3_QUERY_STATUS_COMMAND(2)); 394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 401 } 402 403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 404 uint16_t pasid, 405 uint32_t flush_type, 406 bool all_hub) 407 { 408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 409 } 410 411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 412 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 413 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 415 .kiq_query_status = gfx_v12_0_kiq_query_status, 416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 417 .set_resources_size = 8, 418 .map_queues_size = 7, 419 .unmap_queues_size = 6, 420 .query_status_size = 7, 421 .invalidate_tlbs_size = 2, 422 }; 423 424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 425 { 426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 427 } 428 429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 430 int mem_space, int opt, uint32_t addr0, 431 uint32_t addr1, uint32_t ref, 432 uint32_t mask, uint32_t inv) 433 { 434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 435 amdgpu_ring_write(ring, 436 /* memory (1) or register (0) */ 437 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 438 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 439 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 440 WAIT_REG_MEM_ENGINE(eng_sel))); 441 442 if (mem_space) 443 WARN_ON(addr0 & 0x3); /* Dword align */ 444 amdgpu_ring_write(ring, addr0); 445 amdgpu_ring_write(ring, addr1); 446 amdgpu_ring_write(ring, ref); 447 amdgpu_ring_write(ring, mask); 448 amdgpu_ring_write(ring, inv); /* poll interval */ 449 } 450 451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 455 uint32_t tmp = 0; 456 unsigned i; 457 int r; 458 459 WREG32(scratch, 0xCAFEDEAD); 460 r = amdgpu_ring_alloc(ring, 5); 461 if (r) { 462 drm_err(adev_to_drm(adev), 463 "cp failed to lock ring %d (%d).\n", 464 ring->idx, r); 465 return r; 466 } 467 468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 470 } else { 471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 472 amdgpu_ring_write(ring, scratch - 473 PACKET3_SET_UCONFIG_REG_START); 474 amdgpu_ring_write(ring, 0xDEADBEEF); 475 } 476 amdgpu_ring_commit(ring); 477 478 for (i = 0; i < adev->usec_timeout; i++) { 479 tmp = RREG32(scratch); 480 if (tmp == 0xDEADBEEF) 481 break; 482 if (amdgpu_emu_mode == 1) 483 msleep(1); 484 else 485 udelay(1); 486 } 487 488 if (i >= adev->usec_timeout) 489 r = -ETIMEDOUT; 490 return r; 491 } 492 493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 494 { 495 struct amdgpu_device *adev = ring->adev; 496 struct amdgpu_ib ib; 497 struct dma_fence *f = NULL; 498 unsigned index; 499 uint64_t gpu_addr; 500 uint32_t *cpu_ptr; 501 long r; 502 503 /* MES KIQ fw hasn't indirect buffer support for now */ 504 if (adev->enable_mes_kiq && 505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 506 return 0; 507 508 memset(&ib, 0, sizeof(ib)); 509 510 r = amdgpu_device_wb_get(adev, &index); 511 if (r) 512 return r; 513 514 gpu_addr = adev->wb.gpu_addr + (index * 4); 515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 516 cpu_ptr = &adev->wb.wb[index]; 517 518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 519 if (r) { 520 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 521 goto err1; 522 } 523 524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 526 ib.ptr[2] = lower_32_bits(gpu_addr); 527 ib.ptr[3] = upper_32_bits(gpu_addr); 528 ib.ptr[4] = 0xDEADBEEF; 529 ib.length_dw = 5; 530 531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 532 if (r) 533 goto err2; 534 535 r = dma_fence_wait_timeout(f, false, timeout); 536 if (r == 0) { 537 r = -ETIMEDOUT; 538 goto err2; 539 } else if (r < 0) { 540 goto err2; 541 } 542 543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 544 r = 0; 545 else 546 r = -EINVAL; 547 err2: 548 amdgpu_ib_free(&ib, NULL); 549 dma_fence_put(f); 550 err1: 551 amdgpu_device_wb_free(adev, index); 552 return r; 553 } 554 555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 556 { 557 amdgpu_ucode_release(&adev->gfx.pfp_fw); 558 amdgpu_ucode_release(&adev->gfx.me_fw); 559 amdgpu_ucode_release(&adev->gfx.rlc_fw); 560 amdgpu_ucode_release(&adev->gfx.mec_fw); 561 562 kfree(adev->gfx.rlc.register_list_format); 563 } 564 565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 566 { 567 const struct psp_firmware_header_v1_0 *toc_hdr; 568 int err = 0; 569 570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_toc.bin", ucode_prefix); 573 if (err) 574 goto out; 575 576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 582 return 0; 583 out: 584 amdgpu_ucode_release(&adev->psp.toc_fw); 585 return err; 586 } 587 588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 589 { 590 char ucode_prefix[30]; 591 int err; 592 const struct rlc_firmware_header_v2_0 *rlc_hdr; 593 uint16_t version_major; 594 uint16_t version_minor; 595 596 DRM_DEBUG("\n"); 597 598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 599 600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 601 AMDGPU_UCODE_REQUIRED, 602 "amdgpu/%s_pfp.bin", ucode_prefix); 603 if (err) 604 goto out; 605 606 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 607 (union amdgpu_firmware_header *) 608 adev->gfx.pfp_fw->data, 2, 0); 609 if (adev->gfx.rs64_enable) 610 dev_dbg(adev->dev, "CP RS64 enable\n"); 611 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 614 615 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 616 AMDGPU_UCODE_REQUIRED, 617 "amdgpu/%s_me.bin", ucode_prefix); 618 if (err) 619 goto out; 620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 622 623 if (!amdgpu_sriov_vf(adev)) { 624 if (amdgpu_is_kicker_fw(adev)) 625 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 626 AMDGPU_UCODE_REQUIRED, 627 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 628 else 629 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_rlc.bin", ucode_prefix); 632 if (err) 633 goto out; 634 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 635 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 636 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 637 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 638 if (err) 639 goto out; 640 } 641 642 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 643 AMDGPU_UCODE_REQUIRED, 644 "amdgpu/%s_mec.bin", ucode_prefix); 645 if (err) 646 goto out; 647 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 648 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 649 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 650 651 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 652 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 653 654 /* only one MEC for gfx 12 */ 655 adev->gfx.mec2_fw = NULL; 656 657 if (adev->gfx.imu.funcs) { 658 if (adev->gfx.imu.funcs->init_microcode) { 659 err = adev->gfx.imu.funcs->init_microcode(adev); 660 if (err) 661 dev_err(adev->dev, "Failed to load imu firmware!\n"); 662 } 663 } 664 665 out: 666 if (err) { 667 amdgpu_ucode_release(&adev->gfx.pfp_fw); 668 amdgpu_ucode_release(&adev->gfx.me_fw); 669 amdgpu_ucode_release(&adev->gfx.rlc_fw); 670 amdgpu_ucode_release(&adev->gfx.mec_fw); 671 } 672 673 return err; 674 } 675 676 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 677 { 678 u32 count = 0; 679 const struct cs_section_def *sect = NULL; 680 const struct cs_extent_def *ext = NULL; 681 682 count += 1; 683 684 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 685 if (sect->id == SECT_CONTEXT) { 686 for (ext = sect->section; ext->extent != NULL; ++ext) 687 count += 2 + ext->reg_count; 688 } else 689 return 0; 690 } 691 692 return count; 693 } 694 695 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 696 { 697 u32 count = 0, clustercount = 0, i; 698 const struct cs_section_def *sect = NULL; 699 const struct cs_extent_def *ext = NULL; 700 701 if (adev->gfx.rlc.cs_data == NULL) 702 return; 703 if (buffer == NULL) 704 return; 705 706 count += 1; 707 708 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 709 if (sect->id == SECT_CONTEXT) { 710 for (ext = sect->section; ext->extent != NULL; ++ext) { 711 clustercount++; 712 buffer[count++] = ext->reg_count; 713 buffer[count++] = ext->reg_index; 714 715 for (i = 0; i < ext->reg_count; i++) 716 buffer[count++] = cpu_to_le32(ext->extent[i]); 717 } 718 } else 719 return; 720 } 721 722 buffer[0] = clustercount; 723 } 724 725 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 726 { 727 /* clear state block */ 728 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 729 &adev->gfx.rlc.clear_state_gpu_addr, 730 (void **)&adev->gfx.rlc.cs_ptr); 731 732 /* jump table block */ 733 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 734 &adev->gfx.rlc.cp_table_gpu_addr, 735 (void **)&adev->gfx.rlc.cp_table_ptr); 736 } 737 738 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 739 { 740 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 741 742 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 743 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 744 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 745 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 746 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 747 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 748 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 749 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 750 adev->gfx.rlc.rlcg_reg_access_supported = true; 751 } 752 753 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 754 { 755 const struct cs_section_def *cs_data; 756 int r; 757 758 adev->gfx.rlc.cs_data = gfx12_cs_data; 759 760 cs_data = adev->gfx.rlc.cs_data; 761 762 if (cs_data) { 763 /* init clear state block */ 764 r = amdgpu_gfx_rlc_init_csb(adev); 765 if (r) 766 return r; 767 } 768 769 /* init spm vmid with 0xf */ 770 if (adev->gfx.rlc.funcs->update_spm_vmid) 771 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 772 773 return 0; 774 } 775 776 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 777 { 778 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 779 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 780 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 781 } 782 783 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 784 { 785 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 786 787 amdgpu_gfx_graphics_queue_acquire(adev); 788 } 789 790 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 791 { 792 int r; 793 u32 *hpd; 794 size_t mec_hpd_size; 795 796 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 797 798 /* take ownership of the relevant compute queues */ 799 amdgpu_gfx_compute_queue_acquire(adev); 800 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 801 802 if (mec_hpd_size) { 803 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 804 AMDGPU_GEM_DOMAIN_GTT, 805 &adev->gfx.mec.hpd_eop_obj, 806 &adev->gfx.mec.hpd_eop_gpu_addr, 807 (void **)&hpd); 808 if (r) { 809 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 810 gfx_v12_0_mec_fini(adev); 811 return r; 812 } 813 814 memset(hpd, 0, mec_hpd_size); 815 816 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 817 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 818 } 819 820 return 0; 821 } 822 823 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 824 { 825 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 826 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 827 (address << SQ_IND_INDEX__INDEX__SHIFT)); 828 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 829 } 830 831 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 832 uint32_t thread, uint32_t regno, 833 uint32_t num, uint32_t *out) 834 { 835 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 836 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 837 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 838 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 839 (SQ_IND_INDEX__AUTO_INCR_MASK)); 840 while (num--) 841 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 842 } 843 844 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 845 uint32_t xcc_id, 846 uint32_t simd, uint32_t wave, 847 uint32_t *dst, int *no_fields) 848 { 849 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 850 * field when performing a select_se_sh so it should be 851 * zero here */ 852 WARN_ON(simd != 0); 853 854 /* type 4 wave data */ 855 dst[(*no_fields)++] = 4; 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 873 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 874 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 875 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 876 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 877 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 878 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 879 } 880 881 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t start, 884 uint32_t size, uint32_t *dst) 885 { 886 WARN_ON(simd != 0); 887 888 wave_read_regs( 889 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 890 dst); 891 } 892 893 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 894 uint32_t xcc_id, uint32_t simd, 895 uint32_t wave, uint32_t thread, 896 uint32_t start, uint32_t size, 897 uint32_t *dst) 898 { 899 wave_read_regs( 900 adev, wave, thread, 901 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 902 } 903 904 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 905 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 906 { 907 soc24_grbm_select(adev, me, pipe, q, vm); 908 } 909 910 /* all sizes are in bytes */ 911 #define MQD_SHADOW_BASE_SIZE 73728 912 #define MQD_SHADOW_BASE_ALIGNMENT 256 913 #define MQD_FWWORKAREA_SIZE 484 914 #define MQD_FWWORKAREA_ALIGNMENT 256 915 916 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 917 struct amdgpu_gfx_shadow_info *shadow_info) 918 { 919 /* for gfx */ 920 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 921 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 922 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 923 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 924 /* for compute */ 925 shadow_info->eop_size = GFX12_MEC_HPD_SIZE; 926 shadow_info->eop_alignment = 256; 927 } 928 929 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 930 struct amdgpu_gfx_shadow_info *shadow_info, 931 bool skip_check) 932 { 933 if (adev->gfx.cp_gfx_shadow || skip_check) { 934 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 935 return 0; 936 } 937 938 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 939 return -EINVAL; 940 } 941 942 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 943 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 944 .select_se_sh = &gfx_v12_0_select_se_sh, 945 .read_wave_data = &gfx_v12_0_read_wave_data, 946 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 947 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 948 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 949 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 950 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 951 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 952 }; 953 954 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 955 { 956 957 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 958 case IP_VERSION(12, 0, 0): 959 case IP_VERSION(12, 0, 1): 960 adev->gfx.config.max_hw_contexts = 8; 961 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 962 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 963 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 964 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 965 break; 966 default: 967 BUG(); 968 break; 969 } 970 971 return 0; 972 } 973 974 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 975 int me, int pipe, int queue) 976 { 977 int r; 978 struct amdgpu_ring *ring; 979 unsigned int irq_type; 980 981 ring = &adev->gfx.gfx_ring[ring_id]; 982 983 ring->me = me; 984 ring->pipe = pipe; 985 ring->queue = queue; 986 987 ring->ring_obj = NULL; 988 ring->use_doorbell = true; 989 990 if (!ring_id) 991 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 992 else 993 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 994 ring->vm_hub = AMDGPU_GFXHUB(0); 995 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 996 997 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 998 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 999 AMDGPU_RING_PRIO_DEFAULT, NULL); 1000 if (r) 1001 return r; 1002 return 0; 1003 } 1004 1005 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1006 int mec, int pipe, int queue) 1007 { 1008 int r; 1009 unsigned irq_type; 1010 struct amdgpu_ring *ring; 1011 unsigned int hw_prio; 1012 1013 ring = &adev->gfx.compute_ring[ring_id]; 1014 1015 /* mec0 is me1 */ 1016 ring->me = mec + 1; 1017 ring->pipe = pipe; 1018 ring->queue = queue; 1019 1020 ring->ring_obj = NULL; 1021 ring->use_doorbell = true; 1022 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1023 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1024 + (ring_id * GFX12_MEC_HPD_SIZE); 1025 ring->vm_hub = AMDGPU_GFXHUB(0); 1026 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1027 1028 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1029 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1030 + ring->pipe; 1031 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1032 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1033 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1035 hw_prio, NULL); 1036 if (r) 1037 return r; 1038 1039 return 0; 1040 } 1041 1042 static struct { 1043 SOC24_FIRMWARE_ID id; 1044 unsigned int offset; 1045 unsigned int size; 1046 unsigned int size_x16; 1047 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1048 1049 #define RLC_TOC_OFFSET_DWUNIT 8 1050 #define RLC_SIZE_MULTIPLE 1024 1051 #define RLC_TOC_UMF_SIZE_inM 23ULL 1052 #define RLC_TOC_FORMAT_API 165ULL 1053 1054 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1055 { 1056 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1057 1058 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1059 rlc_autoload_info[ucode->id].id = ucode->id; 1060 rlc_autoload_info[ucode->id].offset = 1061 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1062 rlc_autoload_info[ucode->id].size = 1063 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1064 ucode->size * 4; 1065 ucode++; 1066 } 1067 } 1068 1069 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1070 { 1071 uint32_t total_size = 0; 1072 SOC24_FIRMWARE_ID id; 1073 1074 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1075 1076 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1077 total_size += rlc_autoload_info[id].size; 1078 1079 /* In case the offset in rlc toc ucode is aligned */ 1080 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1081 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1082 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1083 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1084 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1085 1086 return total_size; 1087 } 1088 1089 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1090 { 1091 int r; 1092 uint32_t total_size; 1093 1094 total_size = gfx_v12_0_calc_toc_total_size(adev); 1095 1096 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1097 AMDGPU_GEM_DOMAIN_VRAM, 1098 &adev->gfx.rlc.rlc_autoload_bo, 1099 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1100 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1101 1102 if (r) { 1103 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1104 return r; 1105 } 1106 1107 return 0; 1108 } 1109 1110 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1111 SOC24_FIRMWARE_ID id, 1112 const void *fw_data, 1113 uint32_t fw_size) 1114 { 1115 uint32_t toc_offset; 1116 uint32_t toc_fw_size; 1117 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1118 1119 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1120 return; 1121 1122 toc_offset = rlc_autoload_info[id].offset; 1123 toc_fw_size = rlc_autoload_info[id].size; 1124 1125 if (fw_size == 0) 1126 fw_size = toc_fw_size; 1127 1128 if (fw_size > toc_fw_size) 1129 fw_size = toc_fw_size; 1130 1131 memcpy(ptr + toc_offset, fw_data, fw_size); 1132 1133 if (fw_size < toc_fw_size) 1134 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1139 { 1140 void *data; 1141 uint32_t size; 1142 uint32_t *toc_ptr; 1143 1144 data = adev->psp.toc.start_addr; 1145 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1146 1147 toc_ptr = (uint32_t *)data + size / 4 - 2; 1148 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1149 1150 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1151 data, size); 1152 } 1153 1154 static void 1155 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1156 { 1157 const __le32 *fw_data; 1158 uint32_t fw_size; 1159 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1160 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1161 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1162 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1163 uint16_t version_major, version_minor; 1164 1165 /* pfp ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.pfp_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1181 fw_data, fw_size); 1182 /* me ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.me_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1198 fw_data, fw_size); 1199 /* mec ucode */ 1200 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1201 adev->gfx.mec_fw->data; 1202 /* instruction */ 1203 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1204 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1205 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1206 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1207 fw_data, fw_size); 1208 /* data */ 1209 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1210 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1211 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1212 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1213 fw_data, fw_size); 1214 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1215 fw_data, fw_size); 1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1217 fw_data, fw_size); 1218 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1219 fw_data, fw_size); 1220 1221 /* rlc ucode */ 1222 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1223 adev->gfx.rlc_fw->data; 1224 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1225 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1226 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1227 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1228 fw_data, fw_size); 1229 1230 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1231 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1232 if (version_major == 2) { 1233 if (version_minor >= 1) { 1234 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1235 1236 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1237 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1238 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1239 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1240 fw_data, fw_size); 1241 1242 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1243 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1244 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1245 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1246 fw_data, fw_size); 1247 } 1248 if (version_minor >= 2) { 1249 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1250 1251 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1252 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1253 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1254 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1255 fw_data, fw_size); 1256 1257 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1258 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1259 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1260 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1261 fw_data, fw_size); 1262 } 1263 } 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 uint32_t fw_size; 1271 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1272 1273 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1274 adev->sdma.instance[0].fw->data; 1275 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1276 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1277 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1278 1279 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1280 fw_data, fw_size); 1281 } 1282 1283 static void 1284 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1285 { 1286 const __le32 *fw_data; 1287 unsigned fw_size; 1288 const struct mes_firmware_header_v1_0 *mes_hdr; 1289 int pipe, ucode_id, data_id; 1290 1291 for (pipe = 0; pipe < 2; pipe++) { 1292 if (pipe == 0) { 1293 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1294 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1295 } else { 1296 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1297 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1298 } 1299 1300 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1301 adev->mes.fw[pipe]->data; 1302 1303 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1304 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1305 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1306 1307 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1308 1309 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1310 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1311 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1312 1313 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1314 } 1315 } 1316 1317 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1318 { 1319 uint32_t rlc_g_offset, rlc_g_size; 1320 uint64_t gpu_addr; 1321 uint32_t data; 1322 1323 /* RLC autoload sequence 2: copy ucode */ 1324 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1325 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1326 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1327 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1328 1329 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1330 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1331 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1332 1333 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1334 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1335 1336 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1337 1338 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1339 /* RLC autoload sequence 3: load IMU fw */ 1340 if (adev->gfx.imu.funcs->load_microcode) 1341 adev->gfx.imu.funcs->load_microcode(adev); 1342 /* RLC autoload sequence 4 init IMU fw */ 1343 if (adev->gfx.imu.funcs->setup_imu) 1344 adev->gfx.imu.funcs->setup_imu(adev); 1345 if (adev->gfx.imu.funcs->start_imu) 1346 adev->gfx.imu.funcs->start_imu(adev); 1347 1348 /* RLC autoload sequence 5 disable gpa mode */ 1349 gfx_v12_0_disable_gpa_mode(adev); 1350 } else { 1351 /* unhalt rlc to start autoload without imu */ 1352 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1353 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1354 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1355 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1356 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1357 } 1358 1359 return 0; 1360 } 1361 1362 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1363 { 1364 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1365 uint32_t *ptr; 1366 uint32_t inst; 1367 1368 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1369 if (!ptr) { 1370 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1371 adev->gfx.ip_dump_core = NULL; 1372 } else { 1373 adev->gfx.ip_dump_core = ptr; 1374 } 1375 1376 /* Allocate memory for compute queue registers for all the instances */ 1377 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1378 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1379 adev->gfx.mec.num_queue_per_pipe; 1380 1381 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1382 if (!ptr) { 1383 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1384 adev->gfx.ip_dump_compute_queues = NULL; 1385 } else { 1386 adev->gfx.ip_dump_compute_queues = ptr; 1387 } 1388 1389 /* Allocate memory for gfx queue registers for all the instances */ 1390 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1391 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1392 adev->gfx.me.num_queue_per_pipe; 1393 1394 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1395 if (!ptr) { 1396 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1397 adev->gfx.ip_dump_gfx_queues = NULL; 1398 } else { 1399 adev->gfx.ip_dump_gfx_queues = ptr; 1400 } 1401 } 1402 1403 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1404 { 1405 int i, j, k, r, ring_id = 0; 1406 unsigned num_compute_rings; 1407 int xcc_id = 0; 1408 struct amdgpu_device *adev = ip_block->adev; 1409 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1410 1411 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1412 1413 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1414 case IP_VERSION(12, 0, 0): 1415 case IP_VERSION(12, 0, 1): 1416 adev->gfx.me.num_me = 1; 1417 adev->gfx.me.num_pipe_per_me = 1; 1418 adev->gfx.me.num_queue_per_pipe = 8; 1419 adev->gfx.mec.num_mec = 1; 1420 adev->gfx.mec.num_pipe_per_mec = 2; 1421 adev->gfx.mec.num_queue_per_pipe = 4; 1422 break; 1423 default: 1424 adev->gfx.me.num_me = 1; 1425 adev->gfx.me.num_pipe_per_me = 1; 1426 adev->gfx.me.num_queue_per_pipe = 1; 1427 adev->gfx.mec.num_mec = 1; 1428 adev->gfx.mec.num_pipe_per_mec = 4; 1429 adev->gfx.mec.num_queue_per_pipe = 8; 1430 break; 1431 } 1432 1433 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1434 case IP_VERSION(12, 0, 0): 1435 case IP_VERSION(12, 0, 1): 1436 if (!adev->gfx.disable_uq && 1437 adev->gfx.me_fw_version >= 2780 && 1438 adev->gfx.pfp_fw_version >= 2840 && 1439 adev->gfx.mec_fw_version >= 3050 && 1440 adev->mes.fw_version[0] >= 123) { 1441 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1442 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1443 } 1444 break; 1445 default: 1446 break; 1447 } 1448 1449 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1450 case IP_VERSION(12, 0, 0): 1451 case IP_VERSION(12, 0, 1): 1452 if (adev->gfx.me_fw_version >= 2480 && 1453 adev->gfx.pfp_fw_version >= 2530 && 1454 adev->gfx.mec_fw_version >= 2680 && 1455 adev->mes.fw_version[0] >= 100) 1456 adev->gfx.enable_cleaner_shader = true; 1457 break; 1458 default: 1459 adev->gfx.enable_cleaner_shader = false; 1460 break; 1461 } 1462 1463 if (adev->gfx.num_compute_rings) { 1464 /* recalculate compute rings to use based on hardware configuration */ 1465 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1466 adev->gfx.mec.num_queue_per_pipe) / 2; 1467 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1468 num_compute_rings); 1469 } 1470 1471 /* EOP Event */ 1472 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1473 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1474 &adev->gfx.eop_irq); 1475 if (r) 1476 return r; 1477 1478 /* Bad opcode Event */ 1479 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1480 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1481 &adev->gfx.bad_op_irq); 1482 if (r) 1483 return r; 1484 1485 /* Privileged reg */ 1486 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1487 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1488 &adev->gfx.priv_reg_irq); 1489 if (r) 1490 return r; 1491 1492 /* Privileged inst */ 1493 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1494 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1495 &adev->gfx.priv_inst_irq); 1496 if (r) 1497 return r; 1498 1499 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1500 1501 gfx_v12_0_me_init(adev); 1502 1503 r = gfx_v12_0_rlc_init(adev); 1504 if (r) { 1505 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1506 return r; 1507 } 1508 1509 r = gfx_v12_0_mec_init(adev); 1510 if (r) { 1511 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1512 return r; 1513 } 1514 1515 if (adev->gfx.num_gfx_rings) { 1516 /* set up the gfx ring */ 1517 for (i = 0; i < adev->gfx.me.num_me; i++) { 1518 for (j = 0; j < num_queue_per_pipe; j++) { 1519 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1520 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1521 continue; 1522 1523 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1524 i, k, j); 1525 if (r) 1526 return r; 1527 ring_id++; 1528 } 1529 } 1530 } 1531 } 1532 1533 if (adev->gfx.num_compute_rings) { 1534 ring_id = 0; 1535 /* set up the compute queues - allocate horizontally across pipes */ 1536 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1537 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1538 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1539 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1540 0, i, k, j)) 1541 continue; 1542 1543 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1544 i, k, j); 1545 if (r) 1546 return r; 1547 1548 ring_id++; 1549 } 1550 } 1551 } 1552 } 1553 1554 adev->gfx.gfx_supported_reset = 1555 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1556 adev->gfx.compute_supported_reset = 1557 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1558 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1559 case IP_VERSION(12, 0, 0): 1560 case IP_VERSION(12, 0, 1): 1561 if ((adev->gfx.me_fw_version >= 2660) && 1562 (adev->gfx.mec_fw_version >= 2920) && 1563 !amdgpu_sriov_vf(adev) && 1564 !adev->debug_disable_gpu_ring_reset) { 1565 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1566 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1567 } 1568 break; 1569 default: 1570 break; 1571 } 1572 1573 if (!adev->enable_mes_kiq) { 1574 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1575 if (r) { 1576 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1577 return r; 1578 } 1579 1580 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1581 if (r) 1582 return r; 1583 } 1584 1585 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1586 if (r) 1587 return r; 1588 1589 /* allocate visible FB for rlc auto-loading fw */ 1590 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1591 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1592 if (r) 1593 return r; 1594 } 1595 1596 r = gfx_v12_0_gpu_early_init(adev); 1597 if (r) 1598 return r; 1599 1600 gfx_v12_0_alloc_ip_dump(adev); 1601 1602 r = amdgpu_gfx_sysfs_init(adev); 1603 if (r) 1604 return r; 1605 1606 adev->gfx.me.use_mmio_for_reset = false; 1607 adev->gfx.mec.use_mmio_for_reset = true; 1608 1609 mutex_init(&adev->gfx.mec.reset_mutex); 1610 1611 return 0; 1612 } 1613 1614 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1615 { 1616 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1617 &adev->gfx.pfp.pfp_fw_gpu_addr, 1618 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1619 1620 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1621 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1622 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1623 } 1624 1625 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1626 { 1627 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1628 &adev->gfx.me.me_fw_gpu_addr, 1629 (void **)&adev->gfx.me.me_fw_ptr); 1630 1631 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1632 &adev->gfx.me.me_fw_data_gpu_addr, 1633 (void **)&adev->gfx.me.me_fw_data_ptr); 1634 } 1635 1636 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1637 { 1638 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1639 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1640 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1641 } 1642 1643 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1644 { 1645 int i; 1646 struct amdgpu_device *adev = ip_block->adev; 1647 1648 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1649 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1650 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1651 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1652 1653 amdgpu_gfx_mqd_sw_fini(adev, 0); 1654 1655 if (!adev->enable_mes_kiq) { 1656 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1657 amdgpu_gfx_kiq_fini(adev, 0); 1658 } 1659 1660 gfx_v12_0_pfp_fini(adev); 1661 gfx_v12_0_me_fini(adev); 1662 gfx_v12_0_rlc_fini(adev); 1663 gfx_v12_0_mec_fini(adev); 1664 1665 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1666 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1667 1668 gfx_v12_0_free_microcode(adev); 1669 1670 amdgpu_gfx_sysfs_fini(adev); 1671 1672 kfree(adev->gfx.ip_dump_core); 1673 kfree(adev->gfx.ip_dump_compute_queues); 1674 kfree(adev->gfx.ip_dump_gfx_queues); 1675 1676 return 0; 1677 } 1678 1679 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1680 u32 sh_num, u32 instance, int xcc_id) 1681 { 1682 u32 data; 1683 1684 if (instance == 0xffffffff) 1685 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1686 INSTANCE_BROADCAST_WRITES, 1); 1687 else 1688 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1689 instance); 1690 1691 if (se_num == 0xffffffff) 1692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1693 1); 1694 else 1695 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1696 1697 if (sh_num == 0xffffffff) 1698 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1699 1); 1700 else 1701 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1702 1703 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1704 } 1705 1706 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1707 { 1708 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1709 1710 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1711 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1712 GRBM_CC_GC_SA_UNIT_DISABLE, 1713 SA_DISABLE); 1714 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1715 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1716 GRBM_GC_USER_SA_UNIT_DISABLE, 1717 SA_DISABLE); 1718 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1719 adev->gfx.config.max_shader_engines); 1720 1721 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1722 } 1723 1724 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1725 { 1726 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1727 u32 rb_mask; 1728 1729 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1730 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1731 CC_RB_BACKEND_DISABLE, 1732 BACKEND_DISABLE); 1733 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1734 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1735 GC_USER_RB_BACKEND_DISABLE, 1736 BACKEND_DISABLE); 1737 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1738 adev->gfx.config.max_shader_engines); 1739 1740 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1741 } 1742 1743 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1744 { 1745 u32 rb_bitmap_per_sa; 1746 u32 rb_bitmap_width_per_sa; 1747 u32 max_sa; 1748 u32 active_sa_bitmap; 1749 u32 global_active_rb_bitmap; 1750 u32 active_rb_bitmap = 0; 1751 u32 i; 1752 1753 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1754 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1755 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1756 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1757 1758 /* generate active rb bitmap according to active sa bitmap */ 1759 max_sa = adev->gfx.config.max_shader_engines * 1760 adev->gfx.config.max_sh_per_se; 1761 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1762 adev->gfx.config.max_sh_per_se; 1763 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1764 1765 for (i = 0; i < max_sa; i++) { 1766 if (active_sa_bitmap & (1 << i)) 1767 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1768 } 1769 1770 active_rb_bitmap &= global_active_rb_bitmap; 1771 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1772 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1773 } 1774 1775 #define LDS_APP_BASE 0x1 1776 #define SCRATCH_APP_BASE 0x2 1777 1778 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1779 { 1780 int i; 1781 uint32_t sh_mem_bases; 1782 uint32_t data; 1783 1784 /* 1785 * Configure apertures: 1786 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1787 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1788 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1789 */ 1790 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1791 SCRATCH_APP_BASE; 1792 1793 mutex_lock(&adev->srbm_mutex); 1794 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1795 soc24_grbm_select(adev, 0, 0, 0, i); 1796 /* CP and shaders */ 1797 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1798 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1799 1800 /* Enable trap for each kfd vmid. */ 1801 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1802 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1803 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1804 } 1805 soc24_grbm_select(adev, 0, 0, 0, 0); 1806 mutex_unlock(&adev->srbm_mutex); 1807 } 1808 1809 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1810 { 1811 /* TODO: harvest feature to be added later. */ 1812 } 1813 1814 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1815 { 1816 } 1817 1818 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1819 { 1820 u32 tmp; 1821 int i; 1822 1823 if (!amdgpu_sriov_vf(adev)) 1824 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1825 1826 gfx_v12_0_setup_rb(adev); 1827 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1828 gfx_v12_0_get_tcc_info(adev); 1829 adev->gfx.config.pa_sc_tile_steering_override = 0; 1830 1831 /* XXX SH_MEM regs */ 1832 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1833 mutex_lock(&adev->srbm_mutex); 1834 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1835 soc24_grbm_select(adev, 0, 0, 0, i); 1836 /* CP and shaders */ 1837 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1838 if (i != 0) { 1839 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1840 (adev->gmc.private_aperture_start >> 48)); 1841 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1842 (adev->gmc.shared_aperture_start >> 48)); 1843 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1844 } 1845 } 1846 soc24_grbm_select(adev, 0, 0, 0, 0); 1847 1848 mutex_unlock(&adev->srbm_mutex); 1849 1850 gfx_v12_0_init_compute_vmid(adev); 1851 } 1852 1853 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1854 int me, int pipe) 1855 { 1856 if (me != 0) 1857 return 0; 1858 1859 switch (pipe) { 1860 case 0: 1861 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1862 default: 1863 return 0; 1864 } 1865 } 1866 1867 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1868 int me, int pipe) 1869 { 1870 /* 1871 * amdgpu controls only the first MEC. That's why this function only 1872 * handles the setting of interrupts for this specific MEC. All other 1873 * pipes' interrupts are set by amdkfd. 1874 */ 1875 if (me != 1) 1876 return 0; 1877 1878 switch (pipe) { 1879 case 0: 1880 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1881 case 1: 1882 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1883 default: 1884 return 0; 1885 } 1886 } 1887 1888 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1889 bool enable) 1890 { 1891 u32 tmp, cp_int_cntl_reg; 1892 int i, j; 1893 1894 if (amdgpu_sriov_vf(adev)) 1895 return; 1896 1897 for (i = 0; i < adev->gfx.me.num_me; i++) { 1898 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1899 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1900 1901 if (cp_int_cntl_reg) { 1902 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1903 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1904 enable ? 1 : 0); 1905 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1906 enable ? 1 : 0); 1907 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1908 enable ? 1 : 0); 1909 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1910 enable ? 1 : 0); 1911 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1912 } 1913 } 1914 } 1915 } 1916 1917 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1918 { 1919 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1920 1921 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1922 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1923 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1924 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1925 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1926 1927 return 0; 1928 } 1929 1930 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1931 { 1932 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1933 1934 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1935 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1936 } 1937 1938 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1939 { 1940 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1941 udelay(50); 1942 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1943 udelay(50); 1944 } 1945 1946 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1947 bool enable) 1948 { 1949 uint32_t rlc_pg_cntl; 1950 1951 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1952 1953 if (!enable) { 1954 /* RLC_PG_CNTL[23] = 0 (default) 1955 * RLC will wait for handshake acks with SMU 1956 * GFXOFF will be enabled 1957 * RLC_PG_CNTL[23] = 1 1958 * RLC will not issue any message to SMU 1959 * hence no handshake between SMU & RLC 1960 * GFXOFF will be disabled 1961 */ 1962 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1963 } else 1964 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1965 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1966 } 1967 1968 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1969 { 1970 /* TODO: enable rlc & smu handshake until smu 1971 * and gfxoff feature works as expected */ 1972 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1973 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1974 1975 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1976 udelay(50); 1977 } 1978 1979 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1980 { 1981 uint32_t tmp; 1982 1983 /* enable Save Restore Machine */ 1984 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1985 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1986 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1987 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1988 } 1989 1990 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1991 { 1992 const struct rlc_firmware_header_v2_0 *hdr; 1993 const __le32 *fw_data; 1994 unsigned i, fw_size; 1995 1996 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1997 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1998 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1999 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2000 2001 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2002 RLCG_UCODE_LOADING_START_ADDRESS); 2003 2004 for (i = 0; i < fw_size; i++) 2005 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2006 le32_to_cpup(fw_data++)); 2007 2008 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2009 } 2010 2011 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2012 { 2013 const struct rlc_firmware_header_v2_2 *hdr; 2014 const __le32 *fw_data; 2015 unsigned i, fw_size; 2016 u32 tmp; 2017 2018 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2019 2020 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2021 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2022 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2023 2024 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2025 2026 for (i = 0; i < fw_size; i++) { 2027 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2028 msleep(1); 2029 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2030 le32_to_cpup(fw_data++)); 2031 } 2032 2033 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2034 2035 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2036 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2037 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2038 2039 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2040 for (i = 0; i < fw_size; i++) { 2041 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2042 msleep(1); 2043 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2044 le32_to_cpup(fw_data++)); 2045 } 2046 2047 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2048 2049 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2050 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2051 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2052 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2053 } 2054 2055 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2056 { 2057 const struct rlc_firmware_header_v2_0 *hdr; 2058 uint16_t version_major; 2059 uint16_t version_minor; 2060 2061 if (!adev->gfx.rlc_fw) 2062 return -EINVAL; 2063 2064 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2065 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2066 2067 version_major = le16_to_cpu(hdr->header.header_version_major); 2068 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2069 2070 if (version_major == 2) { 2071 gfx_v12_0_load_rlcg_microcode(adev); 2072 if (amdgpu_dpm == 1) { 2073 if (version_minor >= 2) 2074 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2075 } 2076 2077 return 0; 2078 } 2079 2080 return -EINVAL; 2081 } 2082 2083 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2084 { 2085 int r; 2086 2087 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2088 gfx_v12_0_init_csb(adev); 2089 2090 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2091 gfx_v12_0_rlc_enable_srm(adev); 2092 } else { 2093 if (amdgpu_sriov_vf(adev)) { 2094 gfx_v12_0_init_csb(adev); 2095 return 0; 2096 } 2097 2098 adev->gfx.rlc.funcs->stop(adev); 2099 2100 /* disable CG */ 2101 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2102 2103 /* disable PG */ 2104 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2105 2106 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2107 /* legacy rlc firmware loading */ 2108 r = gfx_v12_0_rlc_load_microcode(adev); 2109 if (r) 2110 return r; 2111 } 2112 2113 gfx_v12_0_init_csb(adev); 2114 2115 adev->gfx.rlc.funcs->start(adev); 2116 } 2117 2118 return 0; 2119 } 2120 2121 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2122 { 2123 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2124 const struct gfx_firmware_header_v2_0 *me_hdr; 2125 const struct gfx_firmware_header_v2_0 *mec_hdr; 2126 uint32_t pipe_id, tmp; 2127 2128 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2129 adev->gfx.mec_fw->data; 2130 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2131 adev->gfx.me_fw->data; 2132 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2133 adev->gfx.pfp_fw->data; 2134 2135 /* config pfp program start addr */ 2136 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2137 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2138 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2139 (pfp_hdr->ucode_start_addr_hi << 30) | 2140 (pfp_hdr->ucode_start_addr_lo >> 2)); 2141 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2142 pfp_hdr->ucode_start_addr_hi >> 2); 2143 } 2144 soc24_grbm_select(adev, 0, 0, 0, 0); 2145 2146 /* reset pfp pipe */ 2147 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2150 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2151 2152 /* clear pfp pipe reset */ 2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2155 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2156 2157 /* config me program start addr */ 2158 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2159 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2160 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2161 (me_hdr->ucode_start_addr_hi << 30) | 2162 (me_hdr->ucode_start_addr_lo >> 2)); 2163 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2164 me_hdr->ucode_start_addr_hi>>2); 2165 } 2166 soc24_grbm_select(adev, 0, 0, 0, 0); 2167 2168 /* reset me pipe */ 2169 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2171 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2172 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2173 2174 /* clear me pipe reset */ 2175 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2176 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2177 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2178 2179 /* config mec program start addr */ 2180 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2181 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2182 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2183 mec_hdr->ucode_start_addr_lo >> 2 | 2184 mec_hdr->ucode_start_addr_hi << 30); 2185 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2186 mec_hdr->ucode_start_addr_hi >> 2); 2187 } 2188 soc24_grbm_select(adev, 0, 0, 0, 0); 2189 2190 /* reset mec pipe */ 2191 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2192 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2193 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2194 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2195 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2196 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2197 2198 /* clear mec pipe reset */ 2199 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2200 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2201 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2202 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2203 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2204 } 2205 2206 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2207 { 2208 const struct gfx_firmware_header_v2_0 *cp_hdr; 2209 unsigned pipe_id, tmp; 2210 2211 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2212 adev->gfx.pfp_fw->data; 2213 mutex_lock(&adev->srbm_mutex); 2214 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2215 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2216 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2217 (cp_hdr->ucode_start_addr_hi << 30) | 2218 (cp_hdr->ucode_start_addr_lo >> 2)); 2219 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2220 cp_hdr->ucode_start_addr_hi>>2); 2221 2222 /* 2223 * Program CP_ME_CNTL to reset given PIPE to take 2224 * effect of CP_PFP_PRGRM_CNTR_START. 2225 */ 2226 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2227 if (pipe_id == 0) 2228 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2229 PFP_PIPE0_RESET, 1); 2230 else 2231 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2232 PFP_PIPE1_RESET, 1); 2233 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2234 2235 /* Clear pfp pipe0 reset bit. */ 2236 if (pipe_id == 0) 2237 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2238 PFP_PIPE0_RESET, 0); 2239 else 2240 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2241 PFP_PIPE1_RESET, 0); 2242 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2243 } 2244 soc24_grbm_select(adev, 0, 0, 0, 0); 2245 mutex_unlock(&adev->srbm_mutex); 2246 } 2247 2248 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2249 { 2250 const struct gfx_firmware_header_v2_0 *cp_hdr; 2251 unsigned pipe_id, tmp; 2252 2253 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2254 adev->gfx.me_fw->data; 2255 mutex_lock(&adev->srbm_mutex); 2256 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2257 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2258 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2259 (cp_hdr->ucode_start_addr_hi << 30) | 2260 (cp_hdr->ucode_start_addr_lo >> 2) ); 2261 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2262 cp_hdr->ucode_start_addr_hi>>2); 2263 2264 /* 2265 * Program CP_ME_CNTL to reset given PIPE to take 2266 * effect of CP_ME_PRGRM_CNTR_START. 2267 */ 2268 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2269 if (pipe_id == 0) 2270 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2271 ME_PIPE0_RESET, 1); 2272 else 2273 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2274 ME_PIPE1_RESET, 1); 2275 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2276 2277 /* Clear pfp pipe0 reset bit. */ 2278 if (pipe_id == 0) 2279 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2280 ME_PIPE0_RESET, 0); 2281 else 2282 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2283 ME_PIPE1_RESET, 0); 2284 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2285 } 2286 soc24_grbm_select(adev, 0, 0, 0, 0); 2287 mutex_unlock(&adev->srbm_mutex); 2288 } 2289 2290 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2291 { 2292 const struct gfx_firmware_header_v2_0 *cp_hdr; 2293 unsigned pipe_id; 2294 2295 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2296 adev->gfx.mec_fw->data; 2297 mutex_lock(&adev->srbm_mutex); 2298 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2299 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2300 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2301 cp_hdr->ucode_start_addr_lo >> 2 | 2302 cp_hdr->ucode_start_addr_hi << 30); 2303 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2304 cp_hdr->ucode_start_addr_hi >> 2); 2305 } 2306 soc24_grbm_select(adev, 0, 0, 0, 0); 2307 mutex_unlock(&adev->srbm_mutex); 2308 } 2309 2310 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2311 { 2312 uint32_t cp_status; 2313 uint32_t bootload_status; 2314 int i; 2315 2316 for (i = 0; i < adev->usec_timeout; i++) { 2317 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2318 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2319 2320 if ((cp_status == 0) && 2321 (REG_GET_FIELD(bootload_status, 2322 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2323 break; 2324 } 2325 udelay(1); 2326 if (amdgpu_emu_mode) 2327 msleep(10); 2328 } 2329 2330 if (i >= adev->usec_timeout) { 2331 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2332 return -ETIMEDOUT; 2333 } 2334 2335 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2336 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2337 gfx_v12_0_set_me_ucode_start_addr(adev); 2338 gfx_v12_0_set_mec_ucode_start_addr(adev); 2339 } 2340 2341 return 0; 2342 } 2343 2344 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2345 { 2346 int i; 2347 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2348 2349 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2350 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2351 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2352 2353 for (i = 0; i < adev->usec_timeout; i++) { 2354 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2355 break; 2356 udelay(1); 2357 } 2358 2359 if (i >= adev->usec_timeout) 2360 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2361 2362 return 0; 2363 } 2364 2365 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2366 { 2367 int r; 2368 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2369 const __le32 *fw_ucode, *fw_data; 2370 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2371 uint32_t tmp; 2372 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2373 2374 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2375 adev->gfx.pfp_fw->data; 2376 2377 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2378 2379 /* instruction */ 2380 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2381 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2382 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2383 /* data */ 2384 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2385 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2386 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2387 2388 /* 64kb align */ 2389 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2390 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2391 &adev->gfx.pfp.pfp_fw_obj, 2392 &adev->gfx.pfp.pfp_fw_gpu_addr, 2393 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2394 if (r) { 2395 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2396 gfx_v12_0_pfp_fini(adev); 2397 return r; 2398 } 2399 2400 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2401 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2402 &adev->gfx.pfp.pfp_fw_data_obj, 2403 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2404 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2405 if (r) { 2406 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2407 gfx_v12_0_pfp_fini(adev); 2408 return r; 2409 } 2410 2411 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2412 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2413 2414 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2415 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2416 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2417 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2418 2419 if (amdgpu_emu_mode == 1) 2420 amdgpu_device_flush_hdp(adev, NULL); 2421 2422 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2423 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2424 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2425 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2426 2427 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2428 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2429 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2430 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2431 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2432 2433 /* 2434 * Programming any of the CP_PFP_IC_BASE registers 2435 * forces invalidation of the ME L1 I$. Wait for the 2436 * invalidation complete 2437 */ 2438 for (i = 0; i < usec_timeout; i++) { 2439 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2440 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2441 INVALIDATE_CACHE_COMPLETE)) 2442 break; 2443 udelay(1); 2444 } 2445 2446 if (i >= usec_timeout) { 2447 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2448 return -EINVAL; 2449 } 2450 2451 /* Prime the L1 instruction caches */ 2452 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2453 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2454 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2455 /* Waiting for cache primed*/ 2456 for (i = 0; i < usec_timeout; i++) { 2457 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2458 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2459 ICACHE_PRIMED)) 2460 break; 2461 udelay(1); 2462 } 2463 2464 if (i >= usec_timeout) { 2465 dev_err(adev->dev, "failed to prime instruction cache\n"); 2466 return -EINVAL; 2467 } 2468 2469 mutex_lock(&adev->srbm_mutex); 2470 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2471 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2472 2473 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2474 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2475 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2476 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2477 } 2478 soc24_grbm_select(adev, 0, 0, 0, 0); 2479 mutex_unlock(&adev->srbm_mutex); 2480 2481 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2482 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2483 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2484 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2485 2486 /* Invalidate the data caches */ 2487 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2488 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2489 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2490 2491 for (i = 0; i < usec_timeout; i++) { 2492 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2493 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2494 INVALIDATE_DCACHE_COMPLETE)) 2495 break; 2496 udelay(1); 2497 } 2498 2499 if (i >= usec_timeout) { 2500 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2501 return -EINVAL; 2502 } 2503 2504 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2505 2506 return 0; 2507 } 2508 2509 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2510 { 2511 int r; 2512 const struct gfx_firmware_header_v2_0 *me_hdr; 2513 const __le32 *fw_ucode, *fw_data; 2514 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2515 uint32_t tmp; 2516 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2517 2518 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2519 adev->gfx.me_fw->data; 2520 2521 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2522 2523 /* instruction */ 2524 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2525 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2526 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2527 /* data */ 2528 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2529 le32_to_cpu(me_hdr->data_offset_bytes)); 2530 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2531 2532 /* 64kb align*/ 2533 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2534 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2535 &adev->gfx.me.me_fw_obj, 2536 &adev->gfx.me.me_fw_gpu_addr, 2537 (void **)&adev->gfx.me.me_fw_ptr); 2538 if (r) { 2539 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2540 gfx_v12_0_me_fini(adev); 2541 return r; 2542 } 2543 2544 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2545 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2546 &adev->gfx.me.me_fw_data_obj, 2547 &adev->gfx.me.me_fw_data_gpu_addr, 2548 (void **)&adev->gfx.me.me_fw_data_ptr); 2549 if (r) { 2550 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2551 gfx_v12_0_me_fini(adev); 2552 return r; 2553 } 2554 2555 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2556 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2557 2558 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2559 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2560 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2561 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2562 2563 if (amdgpu_emu_mode == 1) 2564 amdgpu_device_flush_hdp(adev, NULL); 2565 2566 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2567 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2568 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2569 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2570 2571 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2572 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2573 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2574 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2575 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2576 2577 /* 2578 * Programming any of the CP_ME_IC_BASE registers 2579 * forces invalidation of the ME L1 I$. Wait for the 2580 * invalidation complete 2581 */ 2582 for (i = 0; i < usec_timeout; i++) { 2583 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2584 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2585 INVALIDATE_CACHE_COMPLETE)) 2586 break; 2587 udelay(1); 2588 } 2589 2590 if (i >= usec_timeout) { 2591 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2592 return -EINVAL; 2593 } 2594 2595 /* Prime the instruction caches */ 2596 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2597 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2598 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2599 2600 /* Waiting for instruction cache primed*/ 2601 for (i = 0; i < usec_timeout; i++) { 2602 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2603 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2604 ICACHE_PRIMED)) 2605 break; 2606 udelay(1); 2607 } 2608 2609 if (i >= usec_timeout) { 2610 dev_err(adev->dev, "failed to prime instruction cache\n"); 2611 return -EINVAL; 2612 } 2613 2614 mutex_lock(&adev->srbm_mutex); 2615 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2616 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2617 2618 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2619 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2620 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2621 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2622 } 2623 soc24_grbm_select(adev, 0, 0, 0, 0); 2624 mutex_unlock(&adev->srbm_mutex); 2625 2626 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2627 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2628 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2629 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2630 2631 /* Invalidate the data caches */ 2632 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2633 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2634 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2635 2636 for (i = 0; i < usec_timeout; i++) { 2637 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2638 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2639 INVALIDATE_DCACHE_COMPLETE)) 2640 break; 2641 udelay(1); 2642 } 2643 2644 if (i >= usec_timeout) { 2645 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2646 return -EINVAL; 2647 } 2648 2649 gfx_v12_0_set_me_ucode_start_addr(adev); 2650 2651 return 0; 2652 } 2653 2654 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2655 { 2656 int r; 2657 2658 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2659 return -EINVAL; 2660 2661 gfx_v12_0_cp_gfx_enable(adev, false); 2662 2663 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2664 if (r) { 2665 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2666 return r; 2667 } 2668 2669 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2670 if (r) { 2671 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2672 return r; 2673 } 2674 2675 return 0; 2676 } 2677 2678 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2679 { 2680 /* init the CP */ 2681 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2682 adev->gfx.config.max_hw_contexts - 1); 2683 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2684 2685 if (!amdgpu_async_gfx_ring) 2686 gfx_v12_0_cp_gfx_enable(adev, true); 2687 2688 return 0; 2689 } 2690 2691 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2692 CP_PIPE_ID pipe) 2693 { 2694 u32 tmp; 2695 2696 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2697 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2698 2699 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2700 } 2701 2702 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2703 struct amdgpu_ring *ring) 2704 { 2705 u32 tmp; 2706 2707 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2708 if (ring->use_doorbell) { 2709 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2710 DOORBELL_OFFSET, ring->doorbell_index); 2711 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2712 DOORBELL_EN, 1); 2713 } else { 2714 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2715 DOORBELL_EN, 0); 2716 } 2717 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2718 2719 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2720 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2721 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2722 2723 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2724 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2725 } 2726 2727 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2728 { 2729 struct amdgpu_ring *ring; 2730 u32 tmp; 2731 u32 rb_bufsz; 2732 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2733 2734 /* Set the write pointer delay */ 2735 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2736 2737 /* set the RB to use vmid 0 */ 2738 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2739 2740 /* Init gfx ring 0 for pipe 0 */ 2741 mutex_lock(&adev->srbm_mutex); 2742 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2743 2744 /* Set ring buffer size */ 2745 ring = &adev->gfx.gfx_ring[0]; 2746 rb_bufsz = order_base_2(ring->ring_size / 8); 2747 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2748 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2749 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2750 2751 /* Initialize the ring buffer's write pointers */ 2752 ring->wptr = 0; 2753 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2754 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2755 2756 /* set the wb address whether it's enabled or not */ 2757 rptr_addr = ring->rptr_gpu_addr; 2758 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2759 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2760 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2761 2762 wptr_gpu_addr = ring->wptr_gpu_addr; 2763 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2764 lower_32_bits(wptr_gpu_addr)); 2765 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2766 upper_32_bits(wptr_gpu_addr)); 2767 2768 mdelay(1); 2769 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2770 2771 rb_addr = ring->gpu_addr >> 8; 2772 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2773 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2774 2775 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2776 2777 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2778 mutex_unlock(&adev->srbm_mutex); 2779 2780 /* Switch to pipe 0 */ 2781 mutex_lock(&adev->srbm_mutex); 2782 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2783 mutex_unlock(&adev->srbm_mutex); 2784 2785 /* start the ring */ 2786 gfx_v12_0_cp_gfx_start(adev); 2787 return 0; 2788 } 2789 2790 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2791 { 2792 u32 data; 2793 2794 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2795 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2796 enable ? 0 : 1); 2797 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2798 enable ? 0 : 1); 2799 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2800 enable ? 0 : 1); 2801 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2802 enable ? 0 : 1); 2803 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2804 enable ? 0 : 1); 2805 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2806 enable ? 1 : 0); 2807 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2808 enable ? 1 : 0); 2809 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2810 enable ? 1 : 0); 2811 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2812 enable ? 1 : 0); 2813 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2814 enable ? 0 : 1); 2815 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2816 2817 adev->gfx.kiq[0].ring.sched.ready = enable; 2818 2819 udelay(50); 2820 } 2821 2822 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2823 { 2824 const struct gfx_firmware_header_v2_0 *mec_hdr; 2825 const __le32 *fw_ucode, *fw_data; 2826 u32 tmp, fw_ucode_size, fw_data_size; 2827 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2828 u32 *fw_ucode_ptr, *fw_data_ptr; 2829 int r; 2830 2831 if (!adev->gfx.mec_fw) 2832 return -EINVAL; 2833 2834 gfx_v12_0_cp_compute_enable(adev, false); 2835 2836 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2837 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2838 2839 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2840 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2841 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2842 2843 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2844 le32_to_cpu(mec_hdr->data_offset_bytes)); 2845 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2846 2847 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2848 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2849 &adev->gfx.mec.mec_fw_obj, 2850 &adev->gfx.mec.mec_fw_gpu_addr, 2851 (void **)&fw_ucode_ptr); 2852 if (r) { 2853 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2854 gfx_v12_0_mec_fini(adev); 2855 return r; 2856 } 2857 2858 r = amdgpu_bo_create_reserved(adev, 2859 ALIGN(fw_data_size, 64 * 1024) * 2860 adev->gfx.mec.num_pipe_per_mec, 2861 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2862 &adev->gfx.mec.mec_fw_data_obj, 2863 &adev->gfx.mec.mec_fw_data_gpu_addr, 2864 (void **)&fw_data_ptr); 2865 if (r) { 2866 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2867 gfx_v12_0_mec_fini(adev); 2868 return r; 2869 } 2870 2871 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2872 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2873 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2874 } 2875 2876 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2877 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2878 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2879 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2880 2881 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2882 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2883 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2884 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2885 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2886 2887 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2888 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2889 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2890 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2891 2892 mutex_lock(&adev->srbm_mutex); 2893 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2894 soc24_grbm_select(adev, 1, i, 0, 0); 2895 2896 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2897 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2898 i * ALIGN(fw_data_size, 64 * 1024))); 2899 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2900 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2901 i * ALIGN(fw_data_size, 64 * 1024))); 2902 2903 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2904 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2905 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2906 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2907 } 2908 mutex_unlock(&adev->srbm_mutex); 2909 soc24_grbm_select(adev, 0, 0, 0, 0); 2910 2911 /* Trigger an invalidation of the L1 instruction caches */ 2912 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2913 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2914 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2915 2916 /* Wait for invalidation complete */ 2917 for (i = 0; i < usec_timeout; i++) { 2918 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2919 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2920 INVALIDATE_DCACHE_COMPLETE)) 2921 break; 2922 udelay(1); 2923 } 2924 2925 if (i >= usec_timeout) { 2926 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2927 return -EINVAL; 2928 } 2929 2930 /* Trigger an invalidation of the L1 instruction caches */ 2931 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2932 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2933 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2934 2935 /* Wait for invalidation complete */ 2936 for (i = 0; i < usec_timeout; i++) { 2937 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2938 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2939 INVALIDATE_CACHE_COMPLETE)) 2940 break; 2941 udelay(1); 2942 } 2943 2944 if (i >= usec_timeout) { 2945 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2946 return -EINVAL; 2947 } 2948 2949 gfx_v12_0_set_mec_ucode_start_addr(adev); 2950 2951 return 0; 2952 } 2953 2954 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2955 { 2956 uint32_t tmp; 2957 struct amdgpu_device *adev = ring->adev; 2958 2959 /* tell RLC which is KIQ queue */ 2960 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2961 tmp &= 0xffffff00; 2962 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2963 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2964 } 2965 2966 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2967 { 2968 /* set graphics engine doorbell range */ 2969 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2970 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2971 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2972 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2973 2974 /* set compute engine doorbell range */ 2975 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2976 (adev->doorbell_index.kiq * 2) << 2); 2977 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2978 (adev->doorbell_index.userqueue_end * 2) << 2); 2979 } 2980 2981 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2982 struct amdgpu_mqd_prop *prop) 2983 { 2984 struct v12_gfx_mqd *mqd = m; 2985 uint64_t hqd_gpu_addr, wb_gpu_addr; 2986 uint32_t tmp; 2987 uint32_t rb_bufsz; 2988 2989 /* set up gfx hqd wptr */ 2990 mqd->cp_gfx_hqd_wptr = 0; 2991 mqd->cp_gfx_hqd_wptr_hi = 0; 2992 2993 /* set the pointer to the MQD */ 2994 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2995 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2996 2997 /* set up mqd control */ 2998 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2999 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3000 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3001 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3002 mqd->cp_gfx_mqd_control = tmp; 3003 3004 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3005 tmp = regCP_GFX_HQD_VMID_DEFAULT; 3006 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3007 mqd->cp_gfx_hqd_vmid = 0; 3008 3009 /* set up default queue priority level 3010 * 0x0 = low priority, 0x1 = high priority */ 3011 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 3012 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3013 mqd->cp_gfx_hqd_queue_priority = tmp; 3014 3015 /* set up time quantum */ 3016 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3017 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3018 mqd->cp_gfx_hqd_quantum = tmp; 3019 3020 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3021 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3022 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3023 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3024 3025 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3026 wb_gpu_addr = prop->rptr_gpu_addr; 3027 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3028 mqd->cp_gfx_hqd_rptr_addr_hi = 3029 upper_32_bits(wb_gpu_addr) & 0xffff; 3030 3031 /* set up rb_wptr_poll addr */ 3032 wb_gpu_addr = prop->wptr_gpu_addr; 3033 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3034 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3035 3036 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3037 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3038 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3039 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3040 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3041 #ifdef __BIG_ENDIAN 3042 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3043 #endif 3044 if (prop->tmz_queue) 3045 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3046 if (!prop->kernel_queue) 3047 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3048 mqd->cp_gfx_hqd_cntl = tmp; 3049 3050 /* set up cp_doorbell_control */ 3051 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3052 if (prop->use_doorbell) { 3053 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3054 DOORBELL_OFFSET, prop->doorbell_index); 3055 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3056 DOORBELL_EN, 1); 3057 } else 3058 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3059 DOORBELL_EN, 0); 3060 mqd->cp_rb_doorbell_control = tmp; 3061 3062 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3063 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3064 3065 /* active the queue */ 3066 mqd->cp_gfx_hqd_active = 1; 3067 3068 /* set gfx UQ items */ 3069 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3070 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3071 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3072 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3073 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3074 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3075 3076 return 0; 3077 } 3078 3079 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring) 3080 { 3081 struct amdgpu_device *adev = ring->adev; 3082 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3083 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3084 3085 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3086 memset((void *)mqd, 0, sizeof(*mqd)); 3087 mutex_lock(&adev->srbm_mutex); 3088 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3089 amdgpu_ring_init_mqd(ring); 3090 soc24_grbm_select(adev, 0, 0, 0, 0); 3091 mutex_unlock(&adev->srbm_mutex); 3092 if (adev->gfx.me.mqd_backup[mqd_idx]) 3093 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3094 } else { 3095 /* restore mqd with the backup copy */ 3096 if (adev->gfx.me.mqd_backup[mqd_idx]) 3097 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3098 /* reset the ring */ 3099 ring->wptr = 0; 3100 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3101 amdgpu_ring_clear_ring(ring); 3102 } 3103 3104 return 0; 3105 } 3106 3107 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3108 { 3109 int i, r; 3110 3111 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3112 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i]); 3113 if (r) 3114 return r; 3115 } 3116 3117 r = amdgpu_gfx_enable_kgq(adev, 0); 3118 if (r) 3119 return r; 3120 3121 return gfx_v12_0_cp_gfx_start(adev); 3122 } 3123 3124 static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 3125 struct v12_compute_mqd *mqd, 3126 struct amdgpu_mqd_prop *prop) 3127 { 3128 uint32_t se_mask[8] = {0}; 3129 uint32_t wa_mask; 3130 bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 3131 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 3132 3133 if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 3134 return; 3135 3136 if (has_wa_flag) { 3137 wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 3138 0xffff : 0xffffffff; 3139 mqd->compute_static_thread_mgmt_se0 = wa_mask; 3140 mqd->compute_static_thread_mgmt_se1 = wa_mask; 3141 mqd->compute_static_thread_mgmt_se2 = wa_mask; 3142 mqd->compute_static_thread_mgmt_se3 = wa_mask; 3143 return; 3144 } 3145 3146 amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 3147 prop->cu_mask_count, se_mask); 3148 3149 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 3150 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 3151 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 3152 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 3153 } 3154 3155 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3156 struct amdgpu_mqd_prop *prop) 3157 { 3158 struct v12_compute_mqd *mqd = m; 3159 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3160 uint32_t tmp; 3161 3162 mqd->header = 0xC0310800; 3163 mqd->compute_pipelinestat_enable = 0x00000001; 3164 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3165 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3166 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3167 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3168 mqd->compute_misc_reserved = 0x00000007; 3169 3170 eop_base_addr = prop->eop_gpu_addr >> 8; 3171 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3172 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3173 3174 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3175 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3176 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3177 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3178 3179 mqd->cp_hqd_eop_control = tmp; 3180 3181 /* enable doorbell? */ 3182 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3183 3184 if (prop->use_doorbell) { 3185 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3186 DOORBELL_OFFSET, prop->doorbell_index); 3187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3188 DOORBELL_EN, 1); 3189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3190 DOORBELL_SOURCE, 0); 3191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3192 DOORBELL_HIT, 0); 3193 } else { 3194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3195 DOORBELL_EN, 0); 3196 } 3197 3198 mqd->cp_hqd_pq_doorbell_control = tmp; 3199 3200 /* disable the queue if it's active */ 3201 mqd->cp_hqd_dequeue_request = 0; 3202 mqd->cp_hqd_pq_rptr = 0; 3203 mqd->cp_hqd_pq_wptr_lo = 0; 3204 mqd->cp_hqd_pq_wptr_hi = 0; 3205 3206 /* set the pointer to the MQD */ 3207 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3208 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3209 3210 /* set MQD vmid to 0 */ 3211 tmp = regCP_MQD_CONTROL_DEFAULT; 3212 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3213 mqd->cp_mqd_control = tmp; 3214 3215 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3216 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3217 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3218 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3219 3220 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3221 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3222 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3223 (order_base_2(prop->queue_size / 4) - 1)); 3224 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3225 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3226 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3227 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3228 if (prop->kernel_queue) { 3229 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3230 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3231 } 3232 if (prop->tmz_queue) 3233 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3234 mqd->cp_hqd_pq_control = tmp; 3235 3236 /* set the wb address whether it's enabled or not */ 3237 wb_gpu_addr = prop->rptr_gpu_addr; 3238 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3239 mqd->cp_hqd_pq_rptr_report_addr_hi = 3240 upper_32_bits(wb_gpu_addr) & 0xffff; 3241 3242 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3243 wb_gpu_addr = prop->wptr_gpu_addr; 3244 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3245 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3246 3247 tmp = 0; 3248 /* enable the doorbell if requested */ 3249 if (prop->use_doorbell) { 3250 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3251 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3252 DOORBELL_OFFSET, prop->doorbell_index); 3253 3254 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3255 DOORBELL_EN, 1); 3256 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3257 DOORBELL_SOURCE, 0); 3258 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3259 DOORBELL_HIT, 0); 3260 } 3261 3262 mqd->cp_hqd_pq_doorbell_control = tmp; 3263 3264 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3265 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3266 3267 /* set the vmid for the queue */ 3268 mqd->cp_hqd_vmid = 0; 3269 3270 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3271 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3272 mqd->cp_hqd_persistent_state = tmp; 3273 3274 /* set MIN_IB_AVAIL_SIZE */ 3275 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3276 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3277 mqd->cp_hqd_ib_control = tmp; 3278 3279 /* set static priority for a compute queue/ring */ 3280 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3281 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3282 3283 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 3284 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 3285 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 3286 mqd->cp_hqd_quantum = tmp; 3287 3288 mqd->cp_hqd_active = prop->hqd_active; 3289 3290 /* set UQ fenceaddress */ 3291 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3292 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3293 /* set CU mask */ 3294 gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); 3295 3296 return 0; 3297 } 3298 3299 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3300 { 3301 struct amdgpu_device *adev = ring->adev; 3302 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3303 int j; 3304 3305 /* inactivate the queue */ 3306 if (amdgpu_sriov_vf(adev)) 3307 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3308 3309 /* disable wptr polling */ 3310 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3311 3312 /* write the EOP addr */ 3313 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3314 mqd->cp_hqd_eop_base_addr_lo); 3315 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3316 mqd->cp_hqd_eop_base_addr_hi); 3317 3318 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3319 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3320 mqd->cp_hqd_eop_control); 3321 3322 /* enable doorbell? */ 3323 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3324 mqd->cp_hqd_pq_doorbell_control); 3325 3326 /* disable the queue if it's active */ 3327 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3328 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3329 for (j = 0; j < adev->usec_timeout; j++) { 3330 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3331 break; 3332 udelay(1); 3333 } 3334 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3335 mqd->cp_hqd_dequeue_request); 3336 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3337 mqd->cp_hqd_pq_rptr); 3338 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3339 mqd->cp_hqd_pq_wptr_lo); 3340 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3341 mqd->cp_hqd_pq_wptr_hi); 3342 } 3343 3344 /* set the pointer to the MQD */ 3345 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3346 mqd->cp_mqd_base_addr_lo); 3347 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3348 mqd->cp_mqd_base_addr_hi); 3349 3350 /* set MQD vmid to 0 */ 3351 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3352 mqd->cp_mqd_control); 3353 3354 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3355 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3356 mqd->cp_hqd_pq_base_lo); 3357 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3358 mqd->cp_hqd_pq_base_hi); 3359 3360 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3361 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3362 mqd->cp_hqd_pq_control); 3363 3364 /* set the wb address whether it's enabled or not */ 3365 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3366 mqd->cp_hqd_pq_rptr_report_addr_lo); 3367 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3368 mqd->cp_hqd_pq_rptr_report_addr_hi); 3369 3370 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3371 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3372 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3373 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3374 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3375 3376 /* enable the doorbell if requested */ 3377 if (ring->use_doorbell) { 3378 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3379 (adev->doorbell_index.kiq * 2) << 2); 3380 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3381 (adev->doorbell_index.userqueue_end * 2) << 2); 3382 } 3383 3384 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3385 mqd->cp_hqd_pq_doorbell_control); 3386 3387 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3388 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3389 mqd->cp_hqd_pq_wptr_lo); 3390 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3391 mqd->cp_hqd_pq_wptr_hi); 3392 3393 /* set the vmid for the queue */ 3394 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3395 3396 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3397 mqd->cp_hqd_persistent_state); 3398 3399 /* activate the queue */ 3400 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3401 mqd->cp_hqd_active); 3402 3403 if (ring->use_doorbell) 3404 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3405 3406 return 0; 3407 } 3408 3409 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3410 { 3411 struct amdgpu_device *adev = ring->adev; 3412 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3413 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3414 3415 gfx_v12_0_kiq_setting(ring); 3416 3417 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3418 /* reset MQD to a clean status */ 3419 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3420 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3421 3422 /* reset ring buffer */ 3423 ring->wptr = 0; 3424 amdgpu_ring_clear_ring(ring); 3425 3426 mutex_lock(&adev->srbm_mutex); 3427 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3428 gfx_v12_0_kiq_init_register(ring); 3429 soc24_grbm_select(adev, 0, 0, 0, 0); 3430 mutex_unlock(&adev->srbm_mutex); 3431 } else { 3432 memset((void *)mqd, 0, sizeof(*mqd)); 3433 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3434 amdgpu_ring_clear_ring(ring); 3435 mutex_lock(&adev->srbm_mutex); 3436 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3437 amdgpu_ring_init_mqd(ring); 3438 gfx_v12_0_kiq_init_register(ring); 3439 soc24_grbm_select(adev, 0, 0, 0, 0); 3440 mutex_unlock(&adev->srbm_mutex); 3441 3442 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3443 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3444 } 3445 3446 return 0; 3447 } 3448 3449 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring) 3450 { 3451 struct amdgpu_device *adev = ring->adev; 3452 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3453 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3454 3455 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3456 memset((void *)mqd, 0, sizeof(*mqd)); 3457 mutex_lock(&adev->srbm_mutex); 3458 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3459 amdgpu_ring_init_mqd(ring); 3460 soc24_grbm_select(adev, 0, 0, 0, 0); 3461 mutex_unlock(&adev->srbm_mutex); 3462 3463 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3464 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3465 } else { 3466 /* restore MQD to a clean status */ 3467 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3468 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3469 /* reset ring buffer */ 3470 ring->wptr = 0; 3471 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3472 amdgpu_ring_clear_ring(ring); 3473 } 3474 3475 return 0; 3476 } 3477 3478 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3479 { 3480 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3481 adev->gfx.kiq[0].ring.sched.ready = true; 3482 return 0; 3483 } 3484 3485 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3486 { 3487 int i, r; 3488 3489 if (!amdgpu_async_gfx_ring) 3490 gfx_v12_0_cp_compute_enable(adev, true); 3491 3492 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3493 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i]); 3494 if (r) 3495 return r; 3496 } 3497 3498 return amdgpu_gfx_enable_kcq(adev, 0); 3499 } 3500 3501 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3502 { 3503 int r, i; 3504 struct amdgpu_ring *ring; 3505 3506 if (!(adev->flags & AMD_IS_APU)) 3507 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3508 3509 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3510 /* legacy firmware loading */ 3511 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3512 if (r) 3513 return r; 3514 3515 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3516 if (r) 3517 return r; 3518 } 3519 3520 gfx_v12_0_cp_set_doorbell_range(adev); 3521 3522 if (amdgpu_async_gfx_ring) { 3523 gfx_v12_0_cp_compute_enable(adev, true); 3524 gfx_v12_0_cp_gfx_enable(adev, true); 3525 } 3526 3527 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3528 r = amdgpu_mes_kiq_hw_init(adev, 0); 3529 else 3530 r = gfx_v12_0_kiq_resume(adev); 3531 if (r) 3532 return r; 3533 3534 r = gfx_v12_0_kcq_resume(adev); 3535 if (r) 3536 return r; 3537 3538 if (!amdgpu_async_gfx_ring) { 3539 r = gfx_v12_0_cp_gfx_resume(adev); 3540 if (r) 3541 return r; 3542 } else { 3543 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3544 if (r) 3545 return r; 3546 } 3547 3548 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3549 ring = &adev->gfx.gfx_ring[i]; 3550 r = amdgpu_ring_test_helper(ring); 3551 if (r) 3552 return r; 3553 } 3554 3555 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3556 ring = &adev->gfx.compute_ring[i]; 3557 r = amdgpu_ring_test_helper(ring); 3558 if (r) 3559 return r; 3560 } 3561 3562 return 0; 3563 } 3564 3565 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3566 { 3567 gfx_v12_0_cp_gfx_enable(adev, enable); 3568 gfx_v12_0_cp_compute_enable(adev, enable); 3569 } 3570 3571 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3572 { 3573 int r; 3574 bool value; 3575 3576 r = adev->gfxhub.funcs->gart_enable(adev); 3577 if (r) 3578 return r; 3579 3580 amdgpu_device_flush_hdp(adev, NULL); 3581 3582 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3583 3584 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3585 /* TODO investigate why this and the hdp flush above is needed, 3586 * are we missing a flush somewhere else? */ 3587 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3588 3589 return 0; 3590 } 3591 3592 static int get_gb_addr_config(struct amdgpu_device *adev) 3593 { 3594 u32 gb_addr_config; 3595 3596 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3597 if (gb_addr_config == 0) 3598 return -EINVAL; 3599 3600 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3601 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3602 3603 adev->gfx.config.gb_addr_config = gb_addr_config; 3604 3605 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3606 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3607 GB_ADDR_CONFIG, NUM_PIPES); 3608 3609 adev->gfx.config.max_tile_pipes = 3610 adev->gfx.config.gb_addr_config_fields.num_pipes; 3611 3612 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3613 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3614 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3615 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3616 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3617 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3618 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3619 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3620 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3621 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3622 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3623 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3624 3625 return 0; 3626 } 3627 3628 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3629 { 3630 uint32_t data; 3631 3632 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3633 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3634 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3635 3636 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3637 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3638 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3639 } 3640 3641 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3642 { 3643 if (amdgpu_sriov_vf(adev)) 3644 return; 3645 3646 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3647 case IP_VERSION(12, 0, 0): 3648 case IP_VERSION(12, 0, 1): 3649 soc15_program_register_sequence(adev, 3650 golden_settings_gc_12_0, 3651 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3652 3653 if (adev->rev_id == 0) 3654 soc15_program_register_sequence(adev, 3655 golden_settings_gc_12_0_rev0, 3656 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3657 break; 3658 default: 3659 break; 3660 } 3661 } 3662 3663 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3664 bool enable) 3665 { 3666 unsigned int irq_type; 3667 int m, p, r; 3668 3669 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3670 for (m = 0; m < adev->gfx.me.num_me; m++) { 3671 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3672 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3673 if (enable) 3674 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3675 else 3676 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3677 if (r) { 3678 if (!enable) 3679 return r; 3680 goto err_gfx; 3681 } 3682 } 3683 } 3684 } 3685 3686 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3687 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3688 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3689 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3690 + (m * adev->gfx.mec.num_pipe_per_mec) 3691 + p; 3692 if (enable) 3693 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3694 else 3695 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3696 if (r) { 3697 if (!enable) 3698 return r; 3699 goto err_compute; 3700 } 3701 } 3702 } 3703 } 3704 3705 return 0; 3706 3707 err_compute: 3708 for (p--; p >= 0; p--) { 3709 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3710 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3711 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3712 } 3713 for (m--; m >= 0; m--) { 3714 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 3715 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3716 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3717 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3718 } 3719 } 3720 m = adev->gfx.me.num_me; 3721 err_gfx: 3722 for (p--; p >= 0; p--) { 3723 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3724 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3725 } 3726 for (m--; m >= 0; m--) { 3727 for (p = adev->gfx.me.num_pipe_per_me - 1; p >= 0; p--) { 3728 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3729 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3730 } 3731 } 3732 return r; 3733 } 3734 3735 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3736 { 3737 int r; 3738 struct amdgpu_device *adev = ip_block->adev; 3739 3740 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3741 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3742 /* RLC autoload sequence 1: Program rlc ram */ 3743 if (adev->gfx.imu.funcs->program_rlc_ram) 3744 adev->gfx.imu.funcs->program_rlc_ram(adev); 3745 } 3746 /* rlc autoload firmware */ 3747 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3748 if (r) 3749 return r; 3750 } else { 3751 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3752 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3753 if (adev->gfx.imu.funcs->load_microcode) 3754 adev->gfx.imu.funcs->load_microcode(adev); 3755 if (adev->gfx.imu.funcs->setup_imu) 3756 adev->gfx.imu.funcs->setup_imu(adev); 3757 if (adev->gfx.imu.funcs->start_imu) 3758 adev->gfx.imu.funcs->start_imu(adev); 3759 } 3760 3761 /* disable gpa mode in backdoor loading */ 3762 gfx_v12_0_disable_gpa_mode(adev); 3763 } 3764 } 3765 3766 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3767 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3768 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3769 if (r) { 3770 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3771 return r; 3772 } 3773 } 3774 3775 if (!amdgpu_emu_mode) 3776 gfx_v12_0_init_golden_registers(adev); 3777 3778 adev->gfx.is_poweron = true; 3779 3780 if (get_gb_addr_config(adev)) 3781 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 3782 3783 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3784 gfx_v12_0_config_gfx_rs64(adev); 3785 3786 r = gfx_v12_0_gfxhub_enable(adev); 3787 if (r) 3788 return r; 3789 3790 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3791 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3792 (amdgpu_dpm == 1)) { 3793 /** 3794 * For gfx 12, rlc firmware loading relies on smu firmware is 3795 * loaded firstly, so in direct type, it has to load smc ucode 3796 * here before rlc. 3797 */ 3798 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3799 if (r) 3800 return r; 3801 } 3802 3803 gfx_v12_0_constants_init(adev); 3804 3805 if (adev->nbio.funcs->gc_doorbell_init) 3806 adev->nbio.funcs->gc_doorbell_init(adev); 3807 3808 r = gfx_v12_0_rlc_resume(adev); 3809 if (r) 3810 return r; 3811 3812 /* 3813 * init golden registers and rlc resume may override some registers, 3814 * reconfig them here 3815 */ 3816 gfx_v12_0_tcp_harvest(adev); 3817 3818 r = gfx_v12_0_cp_resume(adev); 3819 if (r) 3820 return r; 3821 3822 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3823 if (r) 3824 return r; 3825 3826 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3827 if (r) 3828 goto err_priv_inst; 3829 3830 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3831 if (r) 3832 goto err_bad_op; 3833 3834 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3835 if (r) 3836 goto err_userq_eop; 3837 3838 return 0; 3839 3840 err_userq_eop: 3841 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3842 err_bad_op: 3843 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3844 err_priv_inst: 3845 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3846 return r; 3847 } 3848 3849 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3850 { 3851 struct amdgpu_device *adev = ip_block->adev; 3852 uint32_t tmp; 3853 3854 cancel_delayed_work_sync(&adev->gfx.idle_work); 3855 3856 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3857 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3858 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3859 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3860 3861 if (!adev->no_hw_access) { 3862 if (amdgpu_async_gfx_ring) { 3863 if (amdgpu_gfx_disable_kgq(adev, 0)) 3864 DRM_ERROR("KGQ disable failed\n"); 3865 } 3866 3867 if (amdgpu_gfx_disable_kcq(adev, 0)) 3868 DRM_ERROR("KCQ disable failed\n"); 3869 3870 amdgpu_mes_kiq_hw_fini(adev, 0); 3871 } 3872 3873 if (amdgpu_sriov_vf(adev)) { 3874 gfx_v12_0_cp_gfx_enable(adev, false); 3875 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3876 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3877 tmp &= 0xffffff00; 3878 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3879 3880 return 0; 3881 } 3882 gfx_v12_0_cp_enable(adev, false); 3883 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3884 3885 adev->gfxhub.funcs->gart_disable(adev); 3886 3887 adev->gfx.is_poweron = false; 3888 3889 return 0; 3890 } 3891 3892 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3893 { 3894 return gfx_v12_0_hw_fini(ip_block); 3895 } 3896 3897 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3898 { 3899 return gfx_v12_0_hw_init(ip_block); 3900 } 3901 3902 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3903 { 3904 struct amdgpu_device *adev = ip_block->adev; 3905 3906 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3907 GRBM_STATUS, GUI_ACTIVE)) 3908 return false; 3909 else 3910 return true; 3911 } 3912 3913 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3914 { 3915 unsigned i; 3916 u32 tmp; 3917 struct amdgpu_device *adev = ip_block->adev; 3918 3919 for (i = 0; i < adev->usec_timeout; i++) { 3920 /* read MC_STATUS */ 3921 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3922 GRBM_STATUS__GUI_ACTIVE_MASK; 3923 3924 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3925 return 0; 3926 udelay(1); 3927 } 3928 return -ETIMEDOUT; 3929 } 3930 3931 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3932 { 3933 uint64_t clock = 0; 3934 3935 if (adev->smuio.funcs && 3936 adev->smuio.funcs->get_gpu_clock_counter) 3937 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3938 else 3939 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3940 3941 return clock; 3942 } 3943 3944 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3945 { 3946 struct amdgpu_device *adev = ip_block->adev; 3947 3948 switch (amdgpu_user_queue) { 3949 case -1: 3950 case 0: 3951 default: 3952 adev->gfx.disable_kq = false; 3953 adev->gfx.disable_uq = true; 3954 break; 3955 case 1: 3956 adev->gfx.disable_kq = false; 3957 adev->gfx.disable_uq = false; 3958 break; 3959 case 2: 3960 adev->gfx.disable_kq = true; 3961 adev->gfx.disable_uq = false; 3962 break; 3963 } 3964 3965 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3966 3967 if (adev->gfx.disable_kq) { 3968 adev->gfx.num_gfx_rings = 0; 3969 adev->gfx.num_compute_rings = 0; 3970 } else { 3971 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3972 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3973 AMDGPU_MAX_COMPUTE_RINGS); 3974 } 3975 3976 gfx_v12_0_set_kiq_pm4_funcs(adev); 3977 gfx_v12_0_set_ring_funcs(adev); 3978 gfx_v12_0_set_irq_funcs(adev); 3979 gfx_v12_0_set_rlc_funcs(adev); 3980 gfx_v12_0_set_mqd_funcs(adev); 3981 gfx_v12_0_set_imu_funcs(adev); 3982 3983 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3984 3985 amdgpu_init_rlc_reg_funcs(adev); 3986 3987 return gfx_v12_0_init_microcode(adev); 3988 } 3989 3990 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3991 { 3992 uint32_t rlc_cntl; 3993 3994 /* if RLC is not enabled, do nothing */ 3995 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3996 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3997 } 3998 3999 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 4000 int xcc_id) 4001 { 4002 uint32_t data; 4003 unsigned i; 4004 4005 data = RLC_SAFE_MODE__CMD_MASK; 4006 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4007 4008 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4009 4010 /* wait for RLC_SAFE_MODE */ 4011 for (i = 0; i < adev->usec_timeout; i++) { 4012 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4013 RLC_SAFE_MODE, CMD)) 4014 break; 4015 udelay(1); 4016 } 4017 } 4018 4019 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 4020 int xcc_id) 4021 { 4022 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4023 } 4024 4025 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 4026 bool enable) 4027 { 4028 uint32_t def, data; 4029 4030 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4031 return; 4032 4033 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4034 4035 if (enable) 4036 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4037 else 4038 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4039 4040 if (def != data) 4041 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4042 } 4043 4044 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 4045 int xcc_id, 4046 struct amdgpu_ring *ring, 4047 unsigned vmid) 4048 { 4049 u32 reg, data; 4050 4051 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4052 if (amdgpu_sriov_is_pp_one_vf(adev)) 4053 data = RREG32_NO_KIQ(reg); 4054 else 4055 data = RREG32(reg); 4056 4057 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4058 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4059 4060 if (amdgpu_sriov_is_pp_one_vf(adev)) 4061 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 4062 else 4063 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 4064 4065 if (ring 4066 && amdgpu_sriov_is_pp_one_vf(adev) 4067 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 4068 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 4069 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4070 amdgpu_ring_emit_wreg(ring, reg, data); 4071 } 4072 } 4073 4074 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 4075 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 4076 .set_safe_mode = gfx_v12_0_set_safe_mode, 4077 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 4078 .init = gfx_v12_0_rlc_init, 4079 .get_csb_size = gfx_v12_0_get_csb_size, 4080 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 4081 .resume = gfx_v12_0_rlc_resume, 4082 .stop = gfx_v12_0_rlc_stop, 4083 .reset = gfx_v12_0_rlc_reset, 4084 .start = gfx_v12_0_rlc_start, 4085 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4086 }; 4087 4088 #if 0 4089 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4090 { 4091 /* TODO */ 4092 } 4093 4094 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4095 { 4096 /* TODO */ 4097 } 4098 #endif 4099 4100 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4101 enum amd_powergating_state state) 4102 { 4103 struct amdgpu_device *adev = ip_block->adev; 4104 bool enable = (state == AMD_PG_STATE_GATE); 4105 4106 if (amdgpu_sriov_vf(adev)) 4107 return 0; 4108 4109 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4110 case IP_VERSION(12, 0, 0): 4111 case IP_VERSION(12, 0, 1): 4112 amdgpu_gfx_off_ctrl(adev, enable); 4113 break; 4114 default: 4115 break; 4116 } 4117 4118 return 0; 4119 } 4120 4121 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4122 bool enable) 4123 { 4124 uint32_t def, data; 4125 4126 if (!(adev->cg_flags & 4127 (AMD_CG_SUPPORT_GFX_CGCG | 4128 AMD_CG_SUPPORT_GFX_CGLS | 4129 AMD_CG_SUPPORT_GFX_3D_CGCG | 4130 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4131 return; 4132 4133 if (enable) { 4134 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4135 4136 /* unset CGCG override */ 4137 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4138 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4139 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4140 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4141 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4142 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4143 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4144 4145 /* update CGCG override bits */ 4146 if (def != data) 4147 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4148 4149 /* enable cgcg FSM(0x0000363F) */ 4150 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4151 4152 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4153 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4154 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4155 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4156 } 4157 4158 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4159 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4160 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4161 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4162 } 4163 4164 if (def != data) 4165 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4166 4167 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4168 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4169 4170 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4171 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4172 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4173 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4174 } 4175 4176 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4177 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4178 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4179 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4180 } 4181 4182 if (def != data) 4183 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4184 4185 /* set IDLE_POLL_COUNT(0x00900100) */ 4186 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4187 4188 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4189 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4190 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4191 4192 if (def != data) 4193 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4194 4195 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4196 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4197 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4198 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4199 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4200 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4201 4202 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4203 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4204 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4205 4206 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4207 if (adev->sdma.num_instances > 1) { 4208 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4209 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4210 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4211 } 4212 } else { 4213 /* Program RLC_CGCG_CGLS_CTRL */ 4214 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4215 4216 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4217 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4218 4219 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4220 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4221 4222 if (def != data) 4223 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4224 4225 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4226 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4227 4228 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4229 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4230 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4231 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4232 4233 if (def != data) 4234 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4235 } 4236 } 4237 4238 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4239 bool enable) 4240 { 4241 uint32_t data, def; 4242 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4243 return; 4244 4245 /* It is disabled by HW by default */ 4246 if (enable) { 4247 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4248 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4249 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4250 4251 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4252 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4253 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4254 4255 if (def != data) 4256 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4257 } 4258 } else { 4259 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4260 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4261 4262 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4263 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4264 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4265 4266 if (def != data) 4267 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4268 } 4269 } 4270 } 4271 4272 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4273 bool enable) 4274 { 4275 uint32_t def, data; 4276 4277 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4278 return; 4279 4280 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4281 4282 if (enable) 4283 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4284 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4285 else 4286 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4287 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4288 4289 if (def != data) 4290 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4291 } 4292 4293 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4294 bool enable) 4295 { 4296 uint32_t def, data; 4297 4298 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4299 return; 4300 4301 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4302 4303 if (enable) 4304 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4305 else 4306 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4307 4308 if (def != data) 4309 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4310 } 4311 4312 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4313 bool enable) 4314 { 4315 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4316 4317 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4318 4319 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4320 4321 gfx_v12_0_update_repeater_fgcg(adev, enable); 4322 4323 gfx_v12_0_update_sram_fgcg(adev, enable); 4324 4325 gfx_v12_0_update_perf_clk(adev, enable); 4326 4327 if (adev->cg_flags & 4328 (AMD_CG_SUPPORT_GFX_MGCG | 4329 AMD_CG_SUPPORT_GFX_CGLS | 4330 AMD_CG_SUPPORT_GFX_CGCG | 4331 AMD_CG_SUPPORT_GFX_3D_CGCG | 4332 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4333 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4334 4335 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4336 4337 return 0; 4338 } 4339 4340 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4341 enum amd_clockgating_state state) 4342 { 4343 struct amdgpu_device *adev = ip_block->adev; 4344 4345 if (amdgpu_sriov_vf(adev)) 4346 return 0; 4347 4348 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4349 case IP_VERSION(12, 0, 0): 4350 case IP_VERSION(12, 0, 1): 4351 gfx_v12_0_update_gfx_clock_gating(adev, 4352 state == AMD_CG_STATE_GATE); 4353 break; 4354 default: 4355 break; 4356 } 4357 4358 return 0; 4359 } 4360 4361 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4362 { 4363 struct amdgpu_device *adev = ip_block->adev; 4364 int data; 4365 4366 /* AMD_CG_SUPPORT_GFX_MGCG */ 4367 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4368 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4369 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4370 4371 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4372 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4373 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4374 4375 /* AMD_CG_SUPPORT_GFX_FGCG */ 4376 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4377 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4378 4379 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4380 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4381 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4382 4383 /* AMD_CG_SUPPORT_GFX_CGCG */ 4384 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4385 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4386 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4387 4388 /* AMD_CG_SUPPORT_GFX_CGLS */ 4389 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4390 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4391 4392 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4393 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4394 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4395 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4396 4397 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4398 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4399 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4400 } 4401 4402 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4403 { 4404 /* gfx12 is 32bit rptr*/ 4405 return *(uint32_t *)ring->rptr_cpu_addr; 4406 } 4407 4408 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4409 { 4410 struct amdgpu_device *adev = ring->adev; 4411 u64 wptr; 4412 4413 /* XXX check if swapping is necessary on BE */ 4414 if (ring->use_doorbell) { 4415 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4416 } else { 4417 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4418 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4419 } 4420 4421 return wptr; 4422 } 4423 4424 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4425 { 4426 struct amdgpu_device *adev = ring->adev; 4427 4428 if (ring->use_doorbell) { 4429 /* XXX check if swapping is necessary on BE */ 4430 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4431 ring->wptr); 4432 WDOORBELL64(ring->doorbell_index, ring->wptr); 4433 } else { 4434 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4435 lower_32_bits(ring->wptr)); 4436 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4437 upper_32_bits(ring->wptr)); 4438 } 4439 } 4440 4441 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4442 { 4443 /* gfx12 hardware is 32bit rptr */ 4444 return *(uint32_t *)ring->rptr_cpu_addr; 4445 } 4446 4447 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4448 { 4449 u64 wptr; 4450 4451 /* XXX check if swapping is necessary on BE */ 4452 if (ring->use_doorbell) 4453 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4454 else 4455 BUG(); 4456 return wptr; 4457 } 4458 4459 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4460 { 4461 struct amdgpu_device *adev = ring->adev; 4462 4463 /* XXX check if swapping is necessary on BE */ 4464 if (ring->use_doorbell) { 4465 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4466 ring->wptr); 4467 WDOORBELL64(ring->doorbell_index, ring->wptr); 4468 } else { 4469 BUG(); /* only DOORBELL method supported on gfx12 now */ 4470 } 4471 } 4472 4473 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4474 { 4475 struct amdgpu_device *adev = ring->adev; 4476 u32 ref_and_mask, reg_mem_engine; 4477 4478 if (!adev->gfx.funcs->get_hdp_flush_mask) { 4479 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 4480 return; 4481 } 4482 4483 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 4484 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4485 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4486 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4487 ref_and_mask, ref_and_mask, 0x20); 4488 } 4489 4490 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4491 struct amdgpu_job *job, 4492 struct amdgpu_ib *ib, 4493 uint32_t flags) 4494 { 4495 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4496 u32 header, control = 0; 4497 4498 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4499 4500 control |= ib->length_dw | (vmid << 24); 4501 4502 amdgpu_ring_write(ring, header); 4503 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4504 amdgpu_ring_write(ring, 4505 #ifdef __BIG_ENDIAN 4506 (2 << 0) | 4507 #endif 4508 lower_32_bits(ib->gpu_addr)); 4509 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4510 amdgpu_ring_write(ring, control); 4511 } 4512 4513 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4514 struct amdgpu_job *job, 4515 struct amdgpu_ib *ib, 4516 uint32_t flags) 4517 { 4518 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4519 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4520 4521 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4522 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4523 amdgpu_ring_write(ring, 4524 #ifdef __BIG_ENDIAN 4525 (2 << 0) | 4526 #endif 4527 lower_32_bits(ib->gpu_addr)); 4528 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4529 amdgpu_ring_write(ring, control); 4530 } 4531 4532 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4533 u64 seq, unsigned flags) 4534 { 4535 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4536 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4537 4538 /* RELEASE_MEM - flush caches, send int */ 4539 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4540 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4541 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4542 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4543 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4544 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4545 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4546 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4547 4548 /* 4549 * the address should be Qword aligned if 64bit write, Dword 4550 * aligned if only send 32bit data low (discard data high) 4551 */ 4552 if (write64bit) 4553 WARN_ON(addr & 0x7); 4554 else 4555 WARN_ON(addr & 0x3); 4556 amdgpu_ring_write(ring, lower_32_bits(addr)); 4557 amdgpu_ring_write(ring, upper_32_bits(addr)); 4558 amdgpu_ring_write(ring, lower_32_bits(seq)); 4559 amdgpu_ring_write(ring, upper_32_bits(seq)); 4560 amdgpu_ring_write(ring, 0); 4561 } 4562 4563 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4564 { 4565 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4566 uint32_t seq = ring->fence_drv.sync_seq; 4567 uint64_t addr = ring->fence_drv.gpu_addr; 4568 4569 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4570 upper_32_bits(addr), seq, 0xffffffff, 4); 4571 } 4572 4573 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4574 uint16_t pasid, uint32_t flush_type, 4575 bool all_hub, uint8_t dst_sel) 4576 { 4577 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4578 amdgpu_ring_write(ring, 4579 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4580 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4581 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4582 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4583 } 4584 4585 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4586 unsigned vmid, uint64_t pd_addr) 4587 { 4588 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4589 4590 /* compute doesn't have PFP */ 4591 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4592 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4593 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4594 amdgpu_ring_write(ring, 0x0); 4595 } 4596 } 4597 4598 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4599 u64 seq, unsigned int flags) 4600 { 4601 struct amdgpu_device *adev = ring->adev; 4602 4603 /* write fence seq to the "addr" */ 4604 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4605 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4606 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4607 amdgpu_ring_write(ring, lower_32_bits(addr)); 4608 amdgpu_ring_write(ring, upper_32_bits(addr)); 4609 amdgpu_ring_write(ring, lower_32_bits(seq)); 4610 4611 if (flags & AMDGPU_FENCE_FLAG_INT) { 4612 /* set register to trigger INT */ 4613 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4614 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4615 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4616 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4617 amdgpu_ring_write(ring, 0); 4618 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4619 } 4620 } 4621 4622 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4623 uint32_t flags) 4624 { 4625 uint32_t dw2 = 0; 4626 4627 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4628 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4629 /* set load_global_config & load_global_uconfig */ 4630 dw2 |= 0x8001; 4631 /* set load_cs_sh_regs */ 4632 dw2 |= 0x01000000; 4633 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4634 dw2 |= 0x10002; 4635 } 4636 4637 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4638 amdgpu_ring_write(ring, dw2); 4639 amdgpu_ring_write(ring, 0); 4640 } 4641 4642 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4643 uint64_t addr) 4644 { 4645 unsigned ret; 4646 4647 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4648 amdgpu_ring_write(ring, lower_32_bits(addr)); 4649 amdgpu_ring_write(ring, upper_32_bits(addr)); 4650 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4651 amdgpu_ring_write(ring, 0); 4652 ret = ring->wptr & ring->buf_mask; 4653 /* patch dummy value later */ 4654 amdgpu_ring_write(ring, 0); 4655 4656 return ret; 4657 } 4658 4659 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4660 uint32_t reg_val_offs) 4661 { 4662 struct amdgpu_device *adev = ring->adev; 4663 4664 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4665 amdgpu_ring_write(ring, 0 | /* src: register*/ 4666 (5 << 8) | /* dst: memory */ 4667 (1 << 20)); /* write confirm */ 4668 amdgpu_ring_write(ring, reg); 4669 amdgpu_ring_write(ring, 0); 4670 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4671 reg_val_offs * 4)); 4672 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4673 reg_val_offs * 4)); 4674 } 4675 4676 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4677 uint32_t reg, 4678 uint32_t val) 4679 { 4680 uint32_t cmd = 0; 4681 4682 switch (ring->funcs->type) { 4683 case AMDGPU_RING_TYPE_GFX: 4684 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4685 break; 4686 case AMDGPU_RING_TYPE_KIQ: 4687 cmd = (1 << 16); /* no inc addr */ 4688 break; 4689 default: 4690 cmd = WR_CONFIRM; 4691 break; 4692 } 4693 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4694 amdgpu_ring_write(ring, cmd); 4695 amdgpu_ring_write(ring, reg); 4696 amdgpu_ring_write(ring, 0); 4697 amdgpu_ring_write(ring, val); 4698 } 4699 4700 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4701 uint32_t val, uint32_t mask) 4702 { 4703 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4704 } 4705 4706 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4707 uint32_t reg0, uint32_t reg1, 4708 uint32_t ref, uint32_t mask) 4709 { 4710 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4711 4712 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4713 ref, mask, 0x20); 4714 } 4715 4716 static void 4717 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4718 uint32_t me, uint32_t pipe, 4719 enum amdgpu_interrupt_state state) 4720 { 4721 uint32_t cp_int_cntl, cp_int_cntl_reg; 4722 4723 if (!me) { 4724 switch (pipe) { 4725 case 0: 4726 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4727 break; 4728 default: 4729 DRM_DEBUG("invalid pipe %d\n", pipe); 4730 return; 4731 } 4732 } else { 4733 DRM_DEBUG("invalid me %d\n", me); 4734 return; 4735 } 4736 4737 switch (state) { 4738 case AMDGPU_IRQ_STATE_DISABLE: 4739 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4740 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4741 TIME_STAMP_INT_ENABLE, 0); 4742 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4743 GENERIC0_INT_ENABLE, 0); 4744 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4745 break; 4746 case AMDGPU_IRQ_STATE_ENABLE: 4747 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4748 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4749 TIME_STAMP_INT_ENABLE, 1); 4750 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4751 GENERIC0_INT_ENABLE, 1); 4752 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4753 break; 4754 default: 4755 break; 4756 } 4757 } 4758 4759 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4760 int me, int pipe, 4761 enum amdgpu_interrupt_state state) 4762 { 4763 u32 mec_int_cntl, mec_int_cntl_reg; 4764 4765 /* 4766 * amdgpu controls only the first MEC. That's why this function only 4767 * handles the setting of interrupts for this specific MEC. All other 4768 * pipes' interrupts are set by amdkfd. 4769 */ 4770 4771 if (me == 1) { 4772 switch (pipe) { 4773 case 0: 4774 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4775 break; 4776 case 1: 4777 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4778 break; 4779 default: 4780 DRM_DEBUG("invalid pipe %d\n", pipe); 4781 return; 4782 } 4783 } else { 4784 DRM_DEBUG("invalid me %d\n", me); 4785 return; 4786 } 4787 4788 switch (state) { 4789 case AMDGPU_IRQ_STATE_DISABLE: 4790 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4791 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4792 TIME_STAMP_INT_ENABLE, 0); 4793 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4794 GENERIC0_INT_ENABLE, 0); 4795 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4796 break; 4797 case AMDGPU_IRQ_STATE_ENABLE: 4798 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4799 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4800 TIME_STAMP_INT_ENABLE, 1); 4801 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4802 GENERIC0_INT_ENABLE, 1); 4803 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4804 break; 4805 default: 4806 break; 4807 } 4808 } 4809 4810 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4811 struct amdgpu_irq_src *src, 4812 unsigned type, 4813 enum amdgpu_interrupt_state state) 4814 { 4815 switch (type) { 4816 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4817 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4818 break; 4819 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4820 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4821 break; 4822 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4823 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4824 break; 4825 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4826 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4827 break; 4828 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4829 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4830 break; 4831 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4832 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4833 break; 4834 default: 4835 break; 4836 } 4837 return 0; 4838 } 4839 4840 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4841 struct amdgpu_irq_src *source, 4842 struct amdgpu_iv_entry *entry) 4843 { 4844 u32 doorbell_offset = entry->src_data[0]; 4845 4846 DRM_DEBUG("IH: CP EOP\n"); 4847 4848 if (!adev->gfx.disable_kq) { 4849 u8 me_id = (entry->ring_id & 0x0c) >> 2; 4850 u8 pipe_id = (entry->ring_id & 0x03) >> 0; 4851 u8 queue_id = (entry->ring_id & 0x70) >> 4; 4852 struct amdgpu_ring *ring; 4853 int i; 4854 4855 switch (me_id) { 4856 case 0: 4857 /* 4858 * MES splits gfx HQDs per (me,pipe): KGQ owns queue=0, 4859 * userq gfx owns queue>=1 (see amdgpu_mes_get_hqd_mask). 4860 * Require a strict (me,pipe,queue) match so userq gfx 4861 * EOPs fall through to amdgpu_userq_process_fence_irq(). 4862 */ 4863 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4864 ring = &adev->gfx.gfx_ring[i]; 4865 if ((ring->me == me_id) && 4866 (ring->pipe == pipe_id) && 4867 (ring->queue == queue_id)) { 4868 amdgpu_fence_process(ring); 4869 return 0; 4870 } 4871 } 4872 break; 4873 case 1: 4874 case 2: 4875 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4876 ring = &adev->gfx.compute_ring[i]; 4877 /* Per-queue interrupt is supported for MEC starting from VI. 4878 * The interrupt can only be enabled/disabled per pipe instead 4879 * of per queue. 4880 */ 4881 if ((ring->me == me_id) && 4882 (ring->pipe == pipe_id) && 4883 (ring->queue == queue_id)) { 4884 amdgpu_fence_process(ring); 4885 return 0; 4886 } 4887 } 4888 break; 4889 default: 4890 break; 4891 } 4892 } 4893 4894 if (adev->enable_mes && doorbell_offset) 4895 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 4896 4897 return 0; 4898 } 4899 4900 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4901 struct amdgpu_irq_src *source, 4902 unsigned int type, 4903 enum amdgpu_interrupt_state state) 4904 { 4905 u32 cp_int_cntl_reg, cp_int_cntl; 4906 int i, j; 4907 4908 switch (state) { 4909 case AMDGPU_IRQ_STATE_DISABLE: 4910 case AMDGPU_IRQ_STATE_ENABLE: 4911 for (i = 0; i < adev->gfx.me.num_me; i++) { 4912 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4913 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4914 4915 if (cp_int_cntl_reg) { 4916 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4917 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4918 PRIV_REG_INT_ENABLE, 4919 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4920 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4921 } 4922 } 4923 } 4924 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4925 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4926 /* MECs start at 1 */ 4927 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4928 4929 if (cp_int_cntl_reg) { 4930 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4931 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4932 PRIV_REG_INT_ENABLE, 4933 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4934 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4935 } 4936 } 4937 } 4938 break; 4939 default: 4940 break; 4941 } 4942 4943 return 0; 4944 } 4945 4946 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4947 struct amdgpu_irq_src *source, 4948 unsigned type, 4949 enum amdgpu_interrupt_state state) 4950 { 4951 u32 cp_int_cntl_reg, cp_int_cntl; 4952 int i, j; 4953 4954 switch (state) { 4955 case AMDGPU_IRQ_STATE_DISABLE: 4956 case AMDGPU_IRQ_STATE_ENABLE: 4957 for (i = 0; i < adev->gfx.me.num_me; i++) { 4958 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4959 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4960 4961 if (cp_int_cntl_reg) { 4962 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4963 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4964 OPCODE_ERROR_INT_ENABLE, 4965 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4966 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4967 } 4968 } 4969 } 4970 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4971 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4972 /* MECs start at 1 */ 4973 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4974 4975 if (cp_int_cntl_reg) { 4976 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4977 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4978 OPCODE_ERROR_INT_ENABLE, 4979 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4980 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4981 } 4982 } 4983 } 4984 break; 4985 default: 4986 break; 4987 } 4988 return 0; 4989 } 4990 4991 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4992 struct amdgpu_irq_src *source, 4993 unsigned int type, 4994 enum amdgpu_interrupt_state state) 4995 { 4996 u32 cp_int_cntl_reg, cp_int_cntl; 4997 int i, j; 4998 4999 switch (state) { 5000 case AMDGPU_IRQ_STATE_DISABLE: 5001 case AMDGPU_IRQ_STATE_ENABLE: 5002 for (i = 0; i < adev->gfx.me.num_me; i++) { 5003 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5004 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 5005 5006 if (cp_int_cntl_reg) { 5007 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5008 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5009 PRIV_INSTR_INT_ENABLE, 5010 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5011 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5012 } 5013 } 5014 } 5015 break; 5016 default: 5017 break; 5018 } 5019 5020 return 0; 5021 } 5022 5023 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5024 struct amdgpu_iv_entry *entry) 5025 { 5026 u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK; 5027 5028 /* 5029 * Try KQ first by ring_id; UQ as fallback. KCQ and UQ never share 5030 * a HW slot (compute_hqd_mask contract). 5031 */ 5032 if (!adev->gfx.disable_kq) { 5033 u8 me_id, pipe_id, queue_id; 5034 struct amdgpu_ring *ring; 5035 int i; 5036 5037 me_id = (entry->ring_id & 0x0c) >> 2; 5038 pipe_id = (entry->ring_id & 0x03) >> 0; 5039 queue_id = (entry->ring_id & 0x70) >> 4; 5040 5041 switch (me_id) { 5042 case 0: 5043 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5044 ring = &adev->gfx.gfx_ring[i]; 5045 if (ring->me == me_id && ring->pipe == pipe_id && 5046 ring->queue == queue_id) { 5047 drm_sched_fault(&ring->sched); 5048 return; 5049 } 5050 } 5051 break; 5052 case 1: 5053 case 2: 5054 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5055 ring = &adev->gfx.compute_ring[i]; 5056 if (ring->me == me_id && ring->pipe == pipe_id && 5057 ring->queue == queue_id) { 5058 drm_sched_fault(&ring->sched); 5059 return; 5060 } 5061 } 5062 break; 5063 default: 5064 BUG(); 5065 break; 5066 } 5067 } 5068 5069 /* No KQ matched: HW slot is a MES-scheduled user queue. */ 5070 if (adev->enable_mes && doorbell_offset) 5071 amdgpu_userq_process_reset_irq(adev, entry->pasid, 5072 doorbell_offset); 5073 } 5074 5075 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5076 struct amdgpu_irq_src *source, 5077 struct amdgpu_iv_entry *entry) 5078 { 5079 DRM_ERROR("Illegal register access in command stream\n"); 5080 gfx_v12_0_handle_priv_fault(adev, entry); 5081 return 0; 5082 } 5083 5084 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5085 struct amdgpu_irq_src *source, 5086 struct amdgpu_iv_entry *entry) 5087 { 5088 DRM_ERROR("Illegal opcode in command stream\n"); 5089 gfx_v12_0_handle_priv_fault(adev, entry); 5090 return 0; 5091 } 5092 5093 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5094 struct amdgpu_irq_src *source, 5095 struct amdgpu_iv_entry *entry) 5096 { 5097 DRM_ERROR("Illegal instruction in command stream\n"); 5098 gfx_v12_0_handle_priv_fault(adev, entry); 5099 return 0; 5100 } 5101 5102 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5103 { 5104 const unsigned int gcr_cntl = 5105 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5106 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5107 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5108 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5109 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5110 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5111 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5112 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5113 5114 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5115 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5116 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5117 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5118 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5119 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5120 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5121 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5122 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5123 } 5124 5125 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5126 { 5127 /* Header itself is a NOP packet */ 5128 if (num_nop == 1) { 5129 amdgpu_ring_write(ring, ring->funcs->nop); 5130 return; 5131 } 5132 5133 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5134 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5135 5136 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5137 amdgpu_ring_insert_nop(ring, num_nop - 1); 5138 } 5139 5140 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5141 { 5142 /* Emit the cleaner shader */ 5143 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5144 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5145 } 5146 5147 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5148 { 5149 struct amdgpu_device *adev = ip_block->adev; 5150 uint32_t i, j, k, reg, index = 0; 5151 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5152 5153 if (!adev->gfx.ip_dump_core) 5154 return; 5155 5156 for (i = 0; i < reg_count; i++) 5157 drm_printf(p, "%-50s \t 0x%08x\n", 5158 gc_reg_list_12_0[i].reg_name, 5159 adev->gfx.ip_dump_core[i]); 5160 5161 /* print compute queue registers for all instances */ 5162 if (!adev->gfx.ip_dump_compute_queues) 5163 return; 5164 5165 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5166 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5167 adev->gfx.mec.num_mec, 5168 adev->gfx.mec.num_pipe_per_mec, 5169 adev->gfx.mec.num_queue_per_pipe); 5170 5171 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5172 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5173 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5174 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5175 for (reg = 0; reg < reg_count; reg++) { 5176 drm_printf(p, "%-50s \t 0x%08x\n", 5177 gc_cp_reg_list_12[reg].reg_name, 5178 adev->gfx.ip_dump_compute_queues[index + reg]); 5179 } 5180 index += reg_count; 5181 } 5182 } 5183 } 5184 5185 /* print gfx queue registers for all instances */ 5186 if (!adev->gfx.ip_dump_gfx_queues) 5187 return; 5188 5189 index = 0; 5190 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5191 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5192 adev->gfx.me.num_me, 5193 adev->gfx.me.num_pipe_per_me, 5194 adev->gfx.me.num_queue_per_pipe); 5195 5196 for (i = 0; i < adev->gfx.me.num_me; i++) { 5197 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5198 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5199 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5200 for (reg = 0; reg < reg_count; reg++) { 5201 drm_printf(p, "%-50s \t 0x%08x\n", 5202 gc_gfx_queue_reg_list_12[reg].reg_name, 5203 adev->gfx.ip_dump_gfx_queues[index + reg]); 5204 } 5205 index += reg_count; 5206 } 5207 } 5208 } 5209 } 5210 5211 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5212 { 5213 struct amdgpu_device *adev = ip_block->adev; 5214 uint32_t i, j, k, reg, index = 0; 5215 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5216 5217 if (!adev->gfx.ip_dump_core) 5218 return; 5219 5220 amdgpu_gfx_off_ctrl(adev, false); 5221 for (i = 0; i < reg_count; i++) 5222 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5223 amdgpu_gfx_off_ctrl(adev, true); 5224 5225 /* dump compute queue registers for all instances */ 5226 if (!adev->gfx.ip_dump_compute_queues) 5227 return; 5228 5229 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5230 amdgpu_gfx_off_ctrl(adev, false); 5231 mutex_lock(&adev->srbm_mutex); 5232 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5233 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5234 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5235 /* ME0 is for GFX so start from 1 for CP */ 5236 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5237 for (reg = 0; reg < reg_count; reg++) { 5238 adev->gfx.ip_dump_compute_queues[index + reg] = 5239 RREG32(SOC15_REG_ENTRY_OFFSET( 5240 gc_cp_reg_list_12[reg])); 5241 } 5242 index += reg_count; 5243 } 5244 } 5245 } 5246 soc24_grbm_select(adev, 0, 0, 0, 0); 5247 mutex_unlock(&adev->srbm_mutex); 5248 amdgpu_gfx_off_ctrl(adev, true); 5249 5250 /* dump gfx queue registers for all instances */ 5251 if (!adev->gfx.ip_dump_gfx_queues) 5252 return; 5253 5254 index = 0; 5255 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5256 amdgpu_gfx_off_ctrl(adev, false); 5257 mutex_lock(&adev->srbm_mutex); 5258 for (i = 0; i < adev->gfx.me.num_me; i++) { 5259 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5260 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5261 soc24_grbm_select(adev, i, j, k, 0); 5262 5263 for (reg = 0; reg < reg_count; reg++) { 5264 adev->gfx.ip_dump_gfx_queues[index + reg] = 5265 RREG32(SOC15_REG_ENTRY_OFFSET( 5266 gc_gfx_queue_reg_list_12[reg])); 5267 } 5268 index += reg_count; 5269 } 5270 } 5271 } 5272 soc24_grbm_select(adev, 0, 0, 0, 0); 5273 mutex_unlock(&adev->srbm_mutex); 5274 amdgpu_gfx_off_ctrl(adev, true); 5275 } 5276 5277 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5278 unsigned int vmid, 5279 struct amdgpu_fence *timedout_fence) 5280 { 5281 struct amdgpu_device *adev = ring->adev; 5282 bool use_mmio = adev->gfx.me.use_mmio_for_reset; 5283 5284 return amdgpu_gfx_mes_reset_queue(ring, vmid, timedout_fence, use_mmio); 5285 } 5286 5287 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5288 unsigned int vmid, 5289 struct amdgpu_fence *timedout_fence) 5290 { 5291 struct amdgpu_device *adev = ring->adev; 5292 5293 return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); 5294 } 5295 5296 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5297 { 5298 amdgpu_gfx_profile_ring_begin_use(ring); 5299 5300 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5301 } 5302 5303 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5304 { 5305 amdgpu_gfx_profile_ring_end_use(ring); 5306 5307 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5308 } 5309 5310 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5311 .name = "gfx_v12_0", 5312 .early_init = gfx_v12_0_early_init, 5313 .sw_init = gfx_v12_0_sw_init, 5314 .sw_fini = gfx_v12_0_sw_fini, 5315 .hw_init = gfx_v12_0_hw_init, 5316 .hw_fini = gfx_v12_0_hw_fini, 5317 .suspend = gfx_v12_0_suspend, 5318 .resume = gfx_v12_0_resume, 5319 .is_idle = gfx_v12_0_is_idle, 5320 .wait_for_idle = gfx_v12_0_wait_for_idle, 5321 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5322 .set_powergating_state = gfx_v12_0_set_powergating_state, 5323 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5324 .dump_ip_state = gfx_v12_ip_dump, 5325 .print_ip_state = gfx_v12_ip_print, 5326 }; 5327 5328 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5329 .type = AMDGPU_RING_TYPE_GFX, 5330 .align_mask = 0xff, 5331 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5332 .support_64bit_ptrs = true, 5333 .secure_submission_supported = true, 5334 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5335 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5336 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5337 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5338 5 + /* COND_EXEC */ 5339 7 + /* PIPELINE_SYNC */ 5340 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5341 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5342 2 + /* VM_FLUSH */ 5343 8 + /* FENCE for VM_FLUSH */ 5344 5 + /* COND_EXEC */ 5345 7 + /* HDP_flush */ 5346 4 + /* VGT_flush */ 5347 31 + /* DE_META */ 5348 3 + /* CNTX_CTRL */ 5349 5 + /* HDP_INVL */ 5350 8 + 8 + /* FENCE x2 */ 5351 8 + /* gfx_v12_0_emit_mem_sync */ 5352 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5353 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5354 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5355 .emit_fence = gfx_v12_0_ring_emit_fence, 5356 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5357 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5358 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5359 .test_ring = gfx_v12_0_ring_test_ring, 5360 .test_ib = gfx_v12_0_ring_test_ib, 5361 .insert_nop = gfx_v12_ring_insert_nop, 5362 .pad_ib = amdgpu_ring_generic_pad_ib, 5363 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5364 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5365 .preempt_ib = amdgpu_gfx_ring_preempt_ib, 5366 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5367 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5368 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5369 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5370 .reset = gfx_v12_0_reset_kgq, 5371 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5372 .begin_use = gfx_v12_0_ring_begin_use, 5373 .end_use = gfx_v12_0_ring_end_use, 5374 }; 5375 5376 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5377 .type = AMDGPU_RING_TYPE_COMPUTE, 5378 .align_mask = 0xff, 5379 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5380 .support_64bit_ptrs = true, 5381 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5382 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5383 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5384 .emit_frame_size = 5385 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5386 5 + /* hdp invalidate */ 5387 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5388 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5389 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5390 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5391 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5392 8 + /* gfx_v12_0_emit_mem_sync */ 5393 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5394 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5395 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5396 .emit_fence = gfx_v12_0_ring_emit_fence, 5397 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5398 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5399 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5400 .test_ring = gfx_v12_0_ring_test_ring, 5401 .test_ib = gfx_v12_0_ring_test_ib, 5402 .insert_nop = gfx_v12_ring_insert_nop, 5403 .pad_ib = amdgpu_ring_generic_pad_ib, 5404 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5405 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5406 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5407 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5408 .reset = gfx_v12_0_reset_kcq, 5409 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5410 .begin_use = gfx_v12_0_ring_begin_use, 5411 .end_use = gfx_v12_0_ring_end_use, 5412 }; 5413 5414 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5415 .type = AMDGPU_RING_TYPE_KIQ, 5416 .align_mask = 0xff, 5417 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5418 .support_64bit_ptrs = true, 5419 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5420 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5421 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5422 .emit_frame_size = 5423 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5424 5 + /*hdp invalidate */ 5425 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5426 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5427 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5428 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5429 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5430 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5431 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5432 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5433 .test_ring = gfx_v12_0_ring_test_ring, 5434 .test_ib = gfx_v12_0_ring_test_ib, 5435 .insert_nop = amdgpu_ring_insert_nop, 5436 .pad_ib = amdgpu_ring_generic_pad_ib, 5437 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5438 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5439 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5440 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5441 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5442 }; 5443 5444 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5445 { 5446 int i; 5447 5448 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5449 5450 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5451 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5452 5453 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5454 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5455 } 5456 5457 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5458 .set = gfx_v12_0_set_eop_interrupt_state, 5459 .process = gfx_v12_0_eop_irq, 5460 }; 5461 5462 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5463 .set = gfx_v12_0_set_priv_reg_fault_state, 5464 .process = gfx_v12_0_priv_reg_irq, 5465 }; 5466 5467 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5468 .set = gfx_v12_0_set_bad_op_fault_state, 5469 .process = gfx_v12_0_bad_op_irq, 5470 }; 5471 5472 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5473 .set = gfx_v12_0_set_priv_inst_fault_state, 5474 .process = gfx_v12_0_priv_inst_irq, 5475 }; 5476 5477 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5478 { 5479 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5480 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5481 5482 adev->gfx.priv_reg_irq.num_types = 1; 5483 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5484 5485 adev->gfx.bad_op_irq.num_types = 1; 5486 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5487 5488 adev->gfx.priv_inst_irq.num_types = 1; 5489 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5490 } 5491 5492 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5493 { 5494 if (adev->flags & AMD_IS_APU) 5495 adev->gfx.imu.mode = MISSION_MODE; 5496 else 5497 adev->gfx.imu.mode = DEBUG_MODE; 5498 5499 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5500 } 5501 5502 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5503 { 5504 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5505 } 5506 5507 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5508 { 5509 /* set gfx eng mqd */ 5510 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5511 sizeof(struct v12_gfx_mqd); 5512 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5513 gfx_v12_0_gfx_mqd_init; 5514 /* set compute eng mqd */ 5515 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5516 sizeof(struct v12_compute_mqd); 5517 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5518 gfx_v12_0_compute_mqd_init; 5519 } 5520 5521 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5522 u32 bitmap) 5523 { 5524 u32 data; 5525 5526 if (!bitmap) 5527 return; 5528 5529 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5530 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5531 5532 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5533 } 5534 5535 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5536 { 5537 u32 data, wgp_bitmask; 5538 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5539 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5540 5541 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5542 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5543 5544 wgp_bitmask = 5545 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5546 5547 return (~data) & wgp_bitmask; 5548 } 5549 5550 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5551 { 5552 u32 wgp_idx, wgp_active_bitmap; 5553 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5554 5555 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5556 cu_active_bitmap = 0; 5557 5558 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5559 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5560 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5561 if (wgp_active_bitmap & (1 << wgp_idx)) 5562 cu_active_bitmap |= cu_bitmap_per_wgp; 5563 } 5564 5565 return cu_active_bitmap; 5566 } 5567 5568 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5569 struct amdgpu_cu_info *cu_info) 5570 { 5571 int i, j, k, counter, active_cu_number = 0; 5572 u32 mask, bitmap; 5573 unsigned disable_masks[8 * 2]; 5574 5575 if (!adev || !cu_info) 5576 return -EINVAL; 5577 5578 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 5579 5580 mutex_lock(&adev->grbm_idx_mutex); 5581 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5582 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5583 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5584 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5585 continue; 5586 mask = 1; 5587 counter = 0; 5588 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5589 if (i < 8 && j < 2) 5590 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5591 adev, disable_masks[i * 2 + j]); 5592 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5593 5594 /** 5595 * GFX12 could support more than 4 SEs, while the bitmap 5596 * in cu_info struct is 4x4 and ioctl interface struct 5597 * drm_amdgpu_info_device should keep stable. 5598 * So we use last two columns of bitmap to store cu mask for 5599 * SEs 4 to 7, the layout of the bitmap is as below: 5600 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5601 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5602 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5603 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5604 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5605 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5606 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5607 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5608 */ 5609 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5610 5611 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5612 if (bitmap & mask) 5613 counter++; 5614 5615 mask <<= 1; 5616 } 5617 active_cu_number += counter; 5618 } 5619 } 5620 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5621 mutex_unlock(&adev->grbm_idx_mutex); 5622 5623 cu_info->number = active_cu_number; 5624 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5625 5626 return 0; 5627 } 5628 5629 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5630 .type = AMD_IP_BLOCK_TYPE_GFX, 5631 .major = 12, 5632 .minor = 0, 5633 .rev = 0, 5634 .funcs = &gfx_v12_0_ip_funcs, 5635 }; 5636