1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 83 84 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 120 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 121 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 124 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 138 /* cp header registers */ 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 /* SE status registers */ 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 152 }; 153 154 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 155 /* compute registers */ 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 195 /* cp header registers */ 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 }; 205 206 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 207 /* gfx queue registers */ 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 233 /* cp header registers */ 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 }; 251 252 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 256 }; 257 258 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 260 }; 261 262 #define DEFAULT_SH_MEM_CONFIG \ 263 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 264 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 265 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 266 267 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 268 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 273 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 274 struct amdgpu_cu_info *cu_info); 275 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 276 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 277 u32 sh_num, u32 instance, int xcc_id); 278 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 279 280 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 359 return; 360 } 361 362 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 363 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 364 PACKET3_UNMAP_QUEUES_ACTION(action) | 365 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 366 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 367 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 368 amdgpu_ring_write(kiq_ring, 369 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 370 371 if (action == PREEMPT_QUEUES_NO_UNMAP) { 372 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 373 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, seq); 375 } else { 376 amdgpu_ring_write(kiq_ring, 0); 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 } 380 } 381 382 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 383 struct amdgpu_ring *ring, 384 u64 addr, u64 seq) 385 { 386 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 387 388 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 389 amdgpu_ring_write(kiq_ring, 390 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 391 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 392 PACKET3_QUERY_STATUS_COMMAND(2)); 393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 394 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 395 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 396 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 397 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 400 } 401 402 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 403 uint16_t pasid, 404 uint32_t flush_type, 405 bool all_hub) 406 { 407 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 408 } 409 410 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 411 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 412 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 413 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 414 .kiq_query_status = gfx_v12_0_kiq_query_status, 415 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 416 .set_resources_size = 8, 417 .map_queues_size = 7, 418 .unmap_queues_size = 6, 419 .query_status_size = 7, 420 .invalidate_tlbs_size = 2, 421 }; 422 423 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 424 { 425 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 426 } 427 428 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 429 int mem_space, int opt, uint32_t addr0, 430 uint32_t addr1, uint32_t ref, 431 uint32_t mask, uint32_t inv) 432 { 433 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 434 amdgpu_ring_write(ring, 435 /* memory (1) or register (0) */ 436 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 437 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 438 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 439 WAIT_REG_MEM_ENGINE(eng_sel))); 440 441 if (mem_space) 442 BUG_ON(addr0 & 0x3); /* Dword align */ 443 amdgpu_ring_write(ring, addr0); 444 amdgpu_ring_write(ring, addr1); 445 amdgpu_ring_write(ring, ref); 446 amdgpu_ring_write(ring, mask); 447 amdgpu_ring_write(ring, inv); /* poll interval */ 448 } 449 450 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 454 uint32_t tmp = 0; 455 unsigned i; 456 int r; 457 458 WREG32(scratch, 0xCAFEDEAD); 459 r = amdgpu_ring_alloc(ring, 5); 460 if (r) { 461 dev_err(adev->dev, 462 "amdgpu: cp failed to lock ring %d (%d).\n", 463 ring->idx, r); 464 return r; 465 } 466 467 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 468 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 469 } else { 470 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 471 amdgpu_ring_write(ring, scratch - 472 PACKET3_SET_UCONFIG_REG_START); 473 amdgpu_ring_write(ring, 0xDEADBEEF); 474 } 475 amdgpu_ring_commit(ring); 476 477 for (i = 0; i < adev->usec_timeout; i++) { 478 tmp = RREG32(scratch); 479 if (tmp == 0xDEADBEEF) 480 break; 481 if (amdgpu_emu_mode == 1) 482 msleep(1); 483 else 484 udelay(1); 485 } 486 487 if (i >= adev->usec_timeout) 488 r = -ETIMEDOUT; 489 return r; 490 } 491 492 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 struct amdgpu_ib ib; 496 struct dma_fence *f = NULL; 497 unsigned index; 498 uint64_t gpu_addr; 499 volatile uint32_t *cpu_ptr; 500 long r; 501 502 /* MES KIQ fw hasn't indirect buffer support for now */ 503 if (adev->enable_mes_kiq && 504 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 505 return 0; 506 507 memset(&ib, 0, sizeof(ib)); 508 509 r = amdgpu_device_wb_get(adev, &index); 510 if (r) 511 return r; 512 513 gpu_addr = adev->wb.gpu_addr + (index * 4); 514 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 515 cpu_ptr = &adev->wb.wb[index]; 516 517 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 518 if (r) { 519 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 520 goto err1; 521 } 522 523 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 524 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 525 ib.ptr[2] = lower_32_bits(gpu_addr); 526 ib.ptr[3] = upper_32_bits(gpu_addr); 527 ib.ptr[4] = 0xDEADBEEF; 528 ib.length_dw = 5; 529 530 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 531 if (r) 532 goto err2; 533 534 r = dma_fence_wait_timeout(f, false, timeout); 535 if (r == 0) { 536 r = -ETIMEDOUT; 537 goto err2; 538 } else if (r < 0) { 539 goto err2; 540 } 541 542 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 543 r = 0; 544 else 545 r = -EINVAL; 546 err2: 547 amdgpu_ib_free(&ib, NULL); 548 dma_fence_put(f); 549 err1: 550 amdgpu_device_wb_free(adev, index); 551 return r; 552 } 553 554 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 555 { 556 amdgpu_ucode_release(&adev->gfx.pfp_fw); 557 amdgpu_ucode_release(&adev->gfx.me_fw); 558 amdgpu_ucode_release(&adev->gfx.rlc_fw); 559 amdgpu_ucode_release(&adev->gfx.mec_fw); 560 561 kfree(adev->gfx.rlc.register_list_format); 562 } 563 564 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 565 { 566 const struct psp_firmware_header_v1_0 *toc_hdr; 567 int err = 0; 568 569 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_toc.bin", ucode_prefix); 572 if (err) 573 goto out; 574 575 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 576 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 577 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 578 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 579 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 580 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 581 return 0; 582 out: 583 amdgpu_ucode_release(&adev->psp.toc_fw); 584 return err; 585 } 586 587 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int err; 591 const struct rlc_firmware_header_v2_0 *rlc_hdr; 592 uint16_t version_major; 593 uint16_t version_minor; 594 595 DRM_DEBUG("\n"); 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_pfp.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 606 607 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 608 AMDGPU_UCODE_REQUIRED, 609 "amdgpu/%s_me.bin", ucode_prefix); 610 if (err) 611 goto out; 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 614 615 if (!amdgpu_sriov_vf(adev)) { 616 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 617 AMDGPU_UCODE_REQUIRED, 618 "amdgpu/%s_rlc.bin", ucode_prefix); 619 if (err) 620 goto out; 621 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 622 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 623 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 624 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 625 if (err) 626 goto out; 627 } 628 629 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_mec.bin", ucode_prefix); 632 if (err) 633 goto out; 634 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 635 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 636 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 637 638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 639 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 640 641 /* only one MEC for gfx 12 */ 642 adev->gfx.mec2_fw = NULL; 643 644 if (adev->gfx.imu.funcs) { 645 if (adev->gfx.imu.funcs->init_microcode) { 646 err = adev->gfx.imu.funcs->init_microcode(adev); 647 if (err) 648 dev_err(adev->dev, "Failed to load imu firmware!\n"); 649 } 650 } 651 652 out: 653 if (err) { 654 amdgpu_ucode_release(&adev->gfx.pfp_fw); 655 amdgpu_ucode_release(&adev->gfx.me_fw); 656 amdgpu_ucode_release(&adev->gfx.rlc_fw); 657 amdgpu_ucode_release(&adev->gfx.mec_fw); 658 } 659 660 return err; 661 } 662 663 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 664 { 665 u32 count = 0; 666 const struct cs_section_def *sect = NULL; 667 const struct cs_extent_def *ext = NULL; 668 669 count += 1; 670 671 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 672 if (sect->id == SECT_CONTEXT) { 673 for (ext = sect->section; ext->extent != NULL; ++ext) 674 count += 2 + ext->reg_count; 675 } else 676 return 0; 677 } 678 679 return count; 680 } 681 682 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 683 volatile u32 *buffer) 684 { 685 u32 count = 0, clustercount = 0, i; 686 const struct cs_section_def *sect = NULL; 687 const struct cs_extent_def *ext = NULL; 688 689 if (adev->gfx.rlc.cs_data == NULL) 690 return; 691 if (buffer == NULL) 692 return; 693 694 count += 1; 695 696 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 697 if (sect->id == SECT_CONTEXT) { 698 for (ext = sect->section; ext->extent != NULL; ++ext) { 699 clustercount++; 700 buffer[count++] = ext->reg_count; 701 buffer[count++] = ext->reg_index; 702 703 for (i = 0; i < ext->reg_count; i++) 704 buffer[count++] = cpu_to_le32(ext->extent[i]); 705 } 706 } else 707 return; 708 } 709 710 buffer[0] = clustercount; 711 } 712 713 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 714 { 715 /* clear state block */ 716 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 717 &adev->gfx.rlc.clear_state_gpu_addr, 718 (void **)&adev->gfx.rlc.cs_ptr); 719 720 /* jump table block */ 721 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 722 &adev->gfx.rlc.cp_table_gpu_addr, 723 (void **)&adev->gfx.rlc.cp_table_ptr); 724 } 725 726 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 727 { 728 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 729 730 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 731 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 732 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 733 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 734 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 735 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 736 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 737 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 738 adev->gfx.rlc.rlcg_reg_access_supported = true; 739 } 740 741 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 742 { 743 const struct cs_section_def *cs_data; 744 int r; 745 746 adev->gfx.rlc.cs_data = gfx12_cs_data; 747 748 cs_data = adev->gfx.rlc.cs_data; 749 750 if (cs_data) { 751 /* init clear state block */ 752 r = amdgpu_gfx_rlc_init_csb(adev); 753 if (r) 754 return r; 755 } 756 757 /* init spm vmid with 0xf */ 758 if (adev->gfx.rlc.funcs->update_spm_vmid) 759 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 760 761 return 0; 762 } 763 764 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 765 { 766 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 767 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 768 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 769 } 770 771 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 772 { 773 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 774 775 amdgpu_gfx_graphics_queue_acquire(adev); 776 } 777 778 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 779 { 780 int r; 781 u32 *hpd; 782 size_t mec_hpd_size; 783 784 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 785 786 /* take ownership of the relevant compute queues */ 787 amdgpu_gfx_compute_queue_acquire(adev); 788 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 789 790 if (mec_hpd_size) { 791 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 792 AMDGPU_GEM_DOMAIN_GTT, 793 &adev->gfx.mec.hpd_eop_obj, 794 &adev->gfx.mec.hpd_eop_gpu_addr, 795 (void **)&hpd); 796 if (r) { 797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 798 gfx_v12_0_mec_fini(adev); 799 return r; 800 } 801 802 memset(hpd, 0, mec_hpd_size); 803 804 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 805 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 806 } 807 808 return 0; 809 } 810 811 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 812 { 813 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 814 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 815 (address << SQ_IND_INDEX__INDEX__SHIFT)); 816 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 817 } 818 819 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 820 uint32_t thread, uint32_t regno, 821 uint32_t num, uint32_t *out) 822 { 823 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 824 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 825 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 826 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 827 (SQ_IND_INDEX__AUTO_INCR_MASK)); 828 while (num--) 829 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 830 } 831 832 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 833 uint32_t xcc_id, 834 uint32_t simd, uint32_t wave, 835 uint32_t *dst, int *no_fields) 836 { 837 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 838 * field when performing a select_se_sh so it should be 839 * zero here */ 840 WARN_ON(simd != 0); 841 842 /* type 4 wave data */ 843 dst[(*no_fields)++] = 4; 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 867 } 868 869 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 870 uint32_t xcc_id, uint32_t simd, 871 uint32_t wave, uint32_t start, 872 uint32_t size, uint32_t *dst) 873 { 874 WARN_ON(simd != 0); 875 876 wave_read_regs( 877 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 878 dst); 879 } 880 881 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t thread, 884 uint32_t start, uint32_t size, 885 uint32_t *dst) 886 { 887 wave_read_regs( 888 adev, wave, thread, 889 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 890 } 891 892 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 893 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 894 { 895 soc24_grbm_select(adev, me, pipe, q, vm); 896 } 897 898 /* all sizes are in bytes */ 899 #define MQD_SHADOW_BASE_SIZE 73728 900 #define MQD_SHADOW_BASE_ALIGNMENT 256 901 #define MQD_FWWORKAREA_SIZE 484 902 #define MQD_FWWORKAREA_ALIGNMENT 256 903 904 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 905 struct amdgpu_gfx_shadow_info *shadow_info) 906 { 907 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 908 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 909 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 910 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 911 } 912 913 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 914 struct amdgpu_gfx_shadow_info *shadow_info, 915 bool skip_check) 916 { 917 if (adev->gfx.cp_gfx_shadow || skip_check) { 918 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 919 return 0; 920 } 921 922 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 923 return -EINVAL; 924 } 925 926 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 927 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 928 .select_se_sh = &gfx_v12_0_select_se_sh, 929 .read_wave_data = &gfx_v12_0_read_wave_data, 930 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 931 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 932 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 933 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 934 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 935 }; 936 937 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 938 { 939 940 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 941 case IP_VERSION(12, 0, 0): 942 case IP_VERSION(12, 0, 1): 943 adev->gfx.config.max_hw_contexts = 8; 944 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 945 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 946 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 947 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 948 break; 949 default: 950 BUG(); 951 break; 952 } 953 954 return 0; 955 } 956 957 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 958 int me, int pipe, int queue) 959 { 960 int r; 961 struct amdgpu_ring *ring; 962 unsigned int irq_type; 963 964 ring = &adev->gfx.gfx_ring[ring_id]; 965 966 ring->me = me; 967 ring->pipe = pipe; 968 ring->queue = queue; 969 970 ring->ring_obj = NULL; 971 ring->use_doorbell = true; 972 973 if (!ring_id) 974 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 975 else 976 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 977 ring->vm_hub = AMDGPU_GFXHUB(0); 978 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 979 980 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 981 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 if (r) 984 return r; 985 return 0; 986 } 987 988 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 989 int mec, int pipe, int queue) 990 { 991 int r; 992 unsigned irq_type; 993 struct amdgpu_ring *ring; 994 unsigned int hw_prio; 995 996 ring = &adev->gfx.compute_ring[ring_id]; 997 998 /* mec0 is me1 */ 999 ring->me = mec + 1; 1000 ring->pipe = pipe; 1001 ring->queue = queue; 1002 1003 ring->ring_obj = NULL; 1004 ring->use_doorbell = true; 1005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1007 + (ring_id * GFX12_MEC_HPD_SIZE); 1008 ring->vm_hub = AMDGPU_GFXHUB(0); 1009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1010 1011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1013 + ring->pipe; 1014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1015 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1017 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1018 hw_prio, NULL); 1019 if (r) 1020 return r; 1021 1022 return 0; 1023 } 1024 1025 static struct { 1026 SOC24_FIRMWARE_ID id; 1027 unsigned int offset; 1028 unsigned int size; 1029 unsigned int size_x16; 1030 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1031 1032 #define RLC_TOC_OFFSET_DWUNIT 8 1033 #define RLC_SIZE_MULTIPLE 1024 1034 #define RLC_TOC_UMF_SIZE_inM 23ULL 1035 #define RLC_TOC_FORMAT_API 165ULL 1036 1037 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1038 { 1039 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1040 1041 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1042 rlc_autoload_info[ucode->id].id = ucode->id; 1043 rlc_autoload_info[ucode->id].offset = 1044 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1045 rlc_autoload_info[ucode->id].size = 1046 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1047 ucode->size * 4; 1048 ucode++; 1049 } 1050 } 1051 1052 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1053 { 1054 uint32_t total_size = 0; 1055 SOC24_FIRMWARE_ID id; 1056 1057 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1058 1059 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1060 total_size += rlc_autoload_info[id].size; 1061 1062 /* In case the offset in rlc toc ucode is aligned */ 1063 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1064 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1065 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1066 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1067 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1068 1069 return total_size; 1070 } 1071 1072 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1073 { 1074 int r; 1075 uint32_t total_size; 1076 1077 total_size = gfx_v12_0_calc_toc_total_size(adev); 1078 1079 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1080 AMDGPU_GEM_DOMAIN_VRAM, 1081 &adev->gfx.rlc.rlc_autoload_bo, 1082 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1083 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1084 1085 if (r) { 1086 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1087 return r; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1094 SOC24_FIRMWARE_ID id, 1095 const void *fw_data, 1096 uint32_t fw_size) 1097 { 1098 uint32_t toc_offset; 1099 uint32_t toc_fw_size; 1100 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1101 1102 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1103 return; 1104 1105 toc_offset = rlc_autoload_info[id].offset; 1106 toc_fw_size = rlc_autoload_info[id].size; 1107 1108 if (fw_size == 0) 1109 fw_size = toc_fw_size; 1110 1111 if (fw_size > toc_fw_size) 1112 fw_size = toc_fw_size; 1113 1114 memcpy(ptr + toc_offset, fw_data, fw_size); 1115 1116 if (fw_size < toc_fw_size) 1117 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1118 } 1119 1120 static void 1121 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1122 { 1123 void *data; 1124 uint32_t size; 1125 uint32_t *toc_ptr; 1126 1127 data = adev->psp.toc.start_addr; 1128 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1129 1130 toc_ptr = (uint32_t *)data + size / 4 - 2; 1131 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1132 1133 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1134 data, size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1139 { 1140 const __le32 *fw_data; 1141 uint32_t fw_size; 1142 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1143 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1144 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1145 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1146 uint16_t version_major, version_minor; 1147 1148 /* pfp ucode */ 1149 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1150 adev->gfx.pfp_fw->data; 1151 /* instruction */ 1152 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1153 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1154 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1155 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1156 fw_data, fw_size); 1157 /* data */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1162 fw_data, fw_size); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1164 fw_data, fw_size); 1165 /* me ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.me_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1181 fw_data, fw_size); 1182 /* mec ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.mec_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1198 fw_data, fw_size); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1200 fw_data, fw_size); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1202 fw_data, fw_size); 1203 1204 /* rlc ucode */ 1205 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1206 adev->gfx.rlc_fw->data; 1207 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1208 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1209 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1210 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1211 fw_data, fw_size); 1212 1213 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1214 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1215 if (version_major == 2) { 1216 if (version_minor >= 1) { 1217 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1218 1219 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1220 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1221 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1222 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1223 fw_data, fw_size); 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1229 fw_data, fw_size); 1230 } 1231 if (version_minor >= 2) { 1232 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1233 1234 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1235 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1236 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1238 fw_data, fw_size); 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1244 fw_data, fw_size); 1245 } 1246 } 1247 } 1248 1249 static void 1250 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1251 { 1252 const __le32 *fw_data; 1253 uint32_t fw_size; 1254 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1255 1256 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1257 adev->sdma.instance[0].fw->data; 1258 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1259 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1260 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1261 1262 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1263 fw_data, fw_size); 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 unsigned fw_size; 1271 const struct mes_firmware_header_v1_0 *mes_hdr; 1272 int pipe, ucode_id, data_id; 1273 1274 for (pipe = 0; pipe < 2; pipe++) { 1275 if (pipe == 0) { 1276 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1277 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1278 } else { 1279 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1280 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1281 } 1282 1283 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1284 adev->mes.fw[pipe]->data; 1285 1286 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1287 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1288 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1289 1290 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1297 } 1298 } 1299 1300 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1301 { 1302 uint32_t rlc_g_offset, rlc_g_size; 1303 uint64_t gpu_addr; 1304 uint32_t data; 1305 1306 /* RLC autoload sequence 2: copy ucode */ 1307 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1308 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1309 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1310 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1311 1312 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1313 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1314 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1315 1316 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1317 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1318 1319 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1320 1321 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1322 /* RLC autoload sequence 3: load IMU fw */ 1323 if (adev->gfx.imu.funcs->load_microcode) 1324 adev->gfx.imu.funcs->load_microcode(adev); 1325 /* RLC autoload sequence 4 init IMU fw */ 1326 if (adev->gfx.imu.funcs->setup_imu) 1327 adev->gfx.imu.funcs->setup_imu(adev); 1328 if (adev->gfx.imu.funcs->start_imu) 1329 adev->gfx.imu.funcs->start_imu(adev); 1330 1331 /* RLC autoload sequence 5 disable gpa mode */ 1332 gfx_v12_0_disable_gpa_mode(adev); 1333 } else { 1334 /* unhalt rlc to start autoload without imu */ 1335 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1336 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1337 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1338 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1339 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1346 { 1347 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1348 uint32_t *ptr; 1349 uint32_t inst; 1350 1351 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1352 if (!ptr) { 1353 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1354 adev->gfx.ip_dump_core = NULL; 1355 } else { 1356 adev->gfx.ip_dump_core = ptr; 1357 } 1358 1359 /* Allocate memory for compute queue registers for all the instances */ 1360 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1361 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe; 1363 1364 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1365 if (!ptr) { 1366 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1367 adev->gfx.ip_dump_compute_queues = NULL; 1368 } else { 1369 adev->gfx.ip_dump_compute_queues = ptr; 1370 } 1371 1372 /* Allocate memory for gfx queue registers for all the instances */ 1373 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1374 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1375 adev->gfx.me.num_queue_per_pipe; 1376 1377 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1378 if (!ptr) { 1379 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1380 adev->gfx.ip_dump_gfx_queues = NULL; 1381 } else { 1382 adev->gfx.ip_dump_gfx_queues = ptr; 1383 } 1384 } 1385 1386 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1387 { 1388 int i, j, k, r, ring_id = 0; 1389 unsigned num_compute_rings; 1390 int xcc_id = 0; 1391 struct amdgpu_device *adev = ip_block->adev; 1392 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1393 1394 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1395 1396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1397 case IP_VERSION(12, 0, 0): 1398 case IP_VERSION(12, 0, 1): 1399 adev->gfx.me.num_me = 1; 1400 adev->gfx.me.num_pipe_per_me = 1; 1401 adev->gfx.me.num_queue_per_pipe = 8; 1402 adev->gfx.mec.num_mec = 1; 1403 adev->gfx.mec.num_pipe_per_mec = 2; 1404 adev->gfx.mec.num_queue_per_pipe = 4; 1405 break; 1406 default: 1407 adev->gfx.me.num_me = 1; 1408 adev->gfx.me.num_pipe_per_me = 1; 1409 adev->gfx.me.num_queue_per_pipe = 1; 1410 adev->gfx.mec.num_mec = 1; 1411 adev->gfx.mec.num_pipe_per_mec = 4; 1412 adev->gfx.mec.num_queue_per_pipe = 8; 1413 break; 1414 } 1415 1416 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1417 case IP_VERSION(12, 0, 0): 1418 case IP_VERSION(12, 0, 1): 1419 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ 1420 /* add firmware version checks here */ 1421 if (0) { 1422 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1423 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1424 } 1425 #endif 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1432 case IP_VERSION(12, 0, 0): 1433 case IP_VERSION(12, 0, 1): 1434 if (adev->gfx.me_fw_version >= 2480 && 1435 adev->gfx.pfp_fw_version >= 2530 && 1436 adev->gfx.mec_fw_version >= 2680 && 1437 adev->mes.fw_version[0] >= 100) 1438 adev->gfx.enable_cleaner_shader = true; 1439 break; 1440 default: 1441 adev->gfx.enable_cleaner_shader = false; 1442 break; 1443 } 1444 1445 if (adev->gfx.num_compute_rings) { 1446 /* recalculate compute rings to use based on hardware configuration */ 1447 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1448 adev->gfx.mec.num_queue_per_pipe) / 2; 1449 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1450 num_compute_rings); 1451 } 1452 1453 /* EOP Event */ 1454 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1455 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1456 &adev->gfx.eop_irq); 1457 if (r) 1458 return r; 1459 1460 /* Bad opcode Event */ 1461 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1462 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1463 &adev->gfx.bad_op_irq); 1464 if (r) 1465 return r; 1466 1467 /* Privileged reg */ 1468 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1469 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1470 &adev->gfx.priv_reg_irq); 1471 if (r) 1472 return r; 1473 1474 /* Privileged inst */ 1475 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1476 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1477 &adev->gfx.priv_inst_irq); 1478 if (r) 1479 return r; 1480 1481 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1482 1483 gfx_v12_0_me_init(adev); 1484 1485 r = gfx_v12_0_rlc_init(adev); 1486 if (r) { 1487 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1488 return r; 1489 } 1490 1491 r = gfx_v12_0_mec_init(adev); 1492 if (r) { 1493 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1494 return r; 1495 } 1496 1497 if (adev->gfx.num_gfx_rings) { 1498 /* set up the gfx ring */ 1499 for (i = 0; i < adev->gfx.me.num_me; i++) { 1500 for (j = 0; j < num_queue_per_pipe; j++) { 1501 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1502 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1503 continue; 1504 1505 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1506 i, k, j); 1507 if (r) 1508 return r; 1509 ring_id++; 1510 } 1511 } 1512 } 1513 } 1514 1515 if (adev->gfx.num_compute_rings) { 1516 ring_id = 0; 1517 /* set up the compute queues - allocate horizontally across pipes */ 1518 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1519 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1520 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1521 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1522 0, i, k, j)) 1523 continue; 1524 1525 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1526 i, k, j); 1527 if (r) 1528 return r; 1529 1530 ring_id++; 1531 } 1532 } 1533 } 1534 } 1535 1536 adev->gfx.gfx_supported_reset = 1537 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1538 adev->gfx.compute_supported_reset = 1539 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1540 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1541 case IP_VERSION(12, 0, 0): 1542 case IP_VERSION(12, 0, 1): 1543 if ((adev->gfx.me_fw_version >= 2660) && 1544 (adev->gfx.mec_fw_version >= 2920)) { 1545 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1546 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1547 } 1548 } 1549 1550 if (!adev->enable_mes_kiq) { 1551 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1552 if (r) { 1553 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1554 return r; 1555 } 1556 1557 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1558 if (r) 1559 return r; 1560 } 1561 1562 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1563 if (r) 1564 return r; 1565 1566 /* allocate visible FB for rlc auto-loading fw */ 1567 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1568 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1569 if (r) 1570 return r; 1571 } 1572 1573 r = gfx_v12_0_gpu_early_init(adev); 1574 if (r) 1575 return r; 1576 1577 gfx_v12_0_alloc_ip_dump(adev); 1578 1579 r = amdgpu_gfx_sysfs_init(adev); 1580 if (r) 1581 return r; 1582 1583 return 0; 1584 } 1585 1586 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1587 { 1588 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1589 &adev->gfx.pfp.pfp_fw_gpu_addr, 1590 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1591 1592 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1593 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1594 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1595 } 1596 1597 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1598 { 1599 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1600 &adev->gfx.me.me_fw_gpu_addr, 1601 (void **)&adev->gfx.me.me_fw_ptr); 1602 1603 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1604 &adev->gfx.me.me_fw_data_gpu_addr, 1605 (void **)&adev->gfx.me.me_fw_data_ptr); 1606 } 1607 1608 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1609 { 1610 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1611 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1612 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1613 } 1614 1615 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1616 { 1617 int i; 1618 struct amdgpu_device *adev = ip_block->adev; 1619 1620 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1621 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1622 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1623 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1624 1625 amdgpu_gfx_mqd_sw_fini(adev, 0); 1626 1627 if (!adev->enable_mes_kiq) { 1628 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1629 amdgpu_gfx_kiq_fini(adev, 0); 1630 } 1631 1632 gfx_v12_0_pfp_fini(adev); 1633 gfx_v12_0_me_fini(adev); 1634 gfx_v12_0_rlc_fini(adev); 1635 gfx_v12_0_mec_fini(adev); 1636 1637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1638 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1639 1640 gfx_v12_0_free_microcode(adev); 1641 1642 amdgpu_gfx_sysfs_fini(adev); 1643 1644 kfree(adev->gfx.ip_dump_core); 1645 kfree(adev->gfx.ip_dump_compute_queues); 1646 kfree(adev->gfx.ip_dump_gfx_queues); 1647 1648 return 0; 1649 } 1650 1651 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1652 u32 sh_num, u32 instance, int xcc_id) 1653 { 1654 u32 data; 1655 1656 if (instance == 0xffffffff) 1657 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1658 INSTANCE_BROADCAST_WRITES, 1); 1659 else 1660 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1661 instance); 1662 1663 if (se_num == 0xffffffff) 1664 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1665 1); 1666 else 1667 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1668 1669 if (sh_num == 0xffffffff) 1670 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1671 1); 1672 else 1673 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1674 1675 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1676 } 1677 1678 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1679 { 1680 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1681 1682 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1683 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1684 GRBM_CC_GC_SA_UNIT_DISABLE, 1685 SA_DISABLE); 1686 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1687 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1688 GRBM_GC_USER_SA_UNIT_DISABLE, 1689 SA_DISABLE); 1690 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1691 adev->gfx.config.max_shader_engines); 1692 1693 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1694 } 1695 1696 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1697 { 1698 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1699 u32 rb_mask; 1700 1701 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1702 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1703 CC_RB_BACKEND_DISABLE, 1704 BACKEND_DISABLE); 1705 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1706 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1707 GC_USER_RB_BACKEND_DISABLE, 1708 BACKEND_DISABLE); 1709 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1710 adev->gfx.config.max_shader_engines); 1711 1712 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1713 } 1714 1715 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1716 { 1717 u32 rb_bitmap_per_sa; 1718 u32 rb_bitmap_width_per_sa; 1719 u32 max_sa; 1720 u32 active_sa_bitmap; 1721 u32 global_active_rb_bitmap; 1722 u32 active_rb_bitmap = 0; 1723 u32 i; 1724 1725 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1726 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1727 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1728 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1729 1730 /* generate active rb bitmap according to active sa bitmap */ 1731 max_sa = adev->gfx.config.max_shader_engines * 1732 adev->gfx.config.max_sh_per_se; 1733 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1734 adev->gfx.config.max_sh_per_se; 1735 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1736 1737 for (i = 0; i < max_sa; i++) { 1738 if (active_sa_bitmap & (1 << i)) 1739 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1740 } 1741 1742 active_rb_bitmap &= global_active_rb_bitmap; 1743 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1744 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1745 } 1746 1747 #define LDS_APP_BASE 0x1 1748 #define SCRATCH_APP_BASE 0x2 1749 1750 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1751 { 1752 int i; 1753 uint32_t sh_mem_bases; 1754 uint32_t data; 1755 1756 /* 1757 * Configure apertures: 1758 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1759 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1760 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1761 */ 1762 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1763 SCRATCH_APP_BASE; 1764 1765 mutex_lock(&adev->srbm_mutex); 1766 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1767 soc24_grbm_select(adev, 0, 0, 0, i); 1768 /* CP and shaders */ 1769 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1770 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1771 1772 /* Enable trap for each kfd vmid. */ 1773 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1774 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1775 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1776 } 1777 soc24_grbm_select(adev, 0, 0, 0, 0); 1778 mutex_unlock(&adev->srbm_mutex); 1779 } 1780 1781 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1782 { 1783 /* TODO: harvest feature to be added later. */ 1784 } 1785 1786 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1787 { 1788 } 1789 1790 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1791 { 1792 u32 tmp; 1793 int i; 1794 1795 if (!amdgpu_sriov_vf(adev)) 1796 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1797 1798 gfx_v12_0_setup_rb(adev); 1799 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1800 gfx_v12_0_get_tcc_info(adev); 1801 adev->gfx.config.pa_sc_tile_steering_override = 0; 1802 1803 /* XXX SH_MEM regs */ 1804 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1805 mutex_lock(&adev->srbm_mutex); 1806 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1807 soc24_grbm_select(adev, 0, 0, 0, i); 1808 /* CP and shaders */ 1809 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1810 if (i != 0) { 1811 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1812 (adev->gmc.private_aperture_start >> 48)); 1813 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1814 (adev->gmc.shared_aperture_start >> 48)); 1815 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1816 } 1817 } 1818 soc24_grbm_select(adev, 0, 0, 0, 0); 1819 1820 mutex_unlock(&adev->srbm_mutex); 1821 1822 gfx_v12_0_init_compute_vmid(adev); 1823 } 1824 1825 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1826 int me, int pipe) 1827 { 1828 if (me != 0) 1829 return 0; 1830 1831 switch (pipe) { 1832 case 0: 1833 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1834 default: 1835 return 0; 1836 } 1837 } 1838 1839 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1840 int me, int pipe) 1841 { 1842 /* 1843 * amdgpu controls only the first MEC. That's why this function only 1844 * handles the setting of interrupts for this specific MEC. All other 1845 * pipes' interrupts are set by amdkfd. 1846 */ 1847 if (me != 1) 1848 return 0; 1849 1850 switch (pipe) { 1851 case 0: 1852 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1853 case 1: 1854 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1855 default: 1856 return 0; 1857 } 1858 } 1859 1860 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1861 bool enable) 1862 { 1863 u32 tmp, cp_int_cntl_reg; 1864 int i, j; 1865 1866 if (amdgpu_sriov_vf(adev)) 1867 return; 1868 1869 for (i = 0; i < adev->gfx.me.num_me; i++) { 1870 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1871 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1872 1873 if (cp_int_cntl_reg) { 1874 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1875 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1876 enable ? 1 : 0); 1877 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1878 enable ? 1 : 0); 1879 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1880 enable ? 1 : 0); 1881 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1882 enable ? 1 : 0); 1883 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1884 } 1885 } 1886 } 1887 } 1888 1889 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1890 { 1891 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1892 1893 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1894 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1895 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1896 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1897 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1898 1899 return 0; 1900 } 1901 1902 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1903 { 1904 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1905 1906 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1907 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1908 } 1909 1910 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1911 { 1912 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1913 udelay(50); 1914 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1915 udelay(50); 1916 } 1917 1918 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1919 bool enable) 1920 { 1921 uint32_t rlc_pg_cntl; 1922 1923 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1924 1925 if (!enable) { 1926 /* RLC_PG_CNTL[23] = 0 (default) 1927 * RLC will wait for handshake acks with SMU 1928 * GFXOFF will be enabled 1929 * RLC_PG_CNTL[23] = 1 1930 * RLC will not issue any message to SMU 1931 * hence no handshake between SMU & RLC 1932 * GFXOFF will be disabled 1933 */ 1934 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1935 } else 1936 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1937 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1938 } 1939 1940 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1941 { 1942 /* TODO: enable rlc & smu handshake until smu 1943 * and gfxoff feature works as expected */ 1944 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1945 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1946 1947 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1948 udelay(50); 1949 } 1950 1951 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1952 { 1953 uint32_t tmp; 1954 1955 /* enable Save Restore Machine */ 1956 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1957 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1958 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1959 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1960 } 1961 1962 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1963 { 1964 const struct rlc_firmware_header_v2_0 *hdr; 1965 const __le32 *fw_data; 1966 unsigned i, fw_size; 1967 1968 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1969 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1970 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1971 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1972 1973 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1974 RLCG_UCODE_LOADING_START_ADDRESS); 1975 1976 for (i = 0; i < fw_size; i++) 1977 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1978 le32_to_cpup(fw_data++)); 1979 1980 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1981 } 1982 1983 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1984 { 1985 const struct rlc_firmware_header_v2_2 *hdr; 1986 const __le32 *fw_data; 1987 unsigned i, fw_size; 1988 u32 tmp; 1989 1990 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1991 1992 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1993 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1994 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1995 1996 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1997 1998 for (i = 0; i < fw_size; i++) { 1999 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2000 msleep(1); 2001 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2002 le32_to_cpup(fw_data++)); 2003 } 2004 2005 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2006 2007 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2008 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2009 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2010 2011 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2012 for (i = 0; i < fw_size; i++) { 2013 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2014 msleep(1); 2015 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2016 le32_to_cpup(fw_data++)); 2017 } 2018 2019 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2020 2021 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2022 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2023 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2024 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2025 } 2026 2027 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2028 { 2029 const struct rlc_firmware_header_v2_0 *hdr; 2030 uint16_t version_major; 2031 uint16_t version_minor; 2032 2033 if (!adev->gfx.rlc_fw) 2034 return -EINVAL; 2035 2036 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2037 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2038 2039 version_major = le16_to_cpu(hdr->header.header_version_major); 2040 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2041 2042 if (version_major == 2) { 2043 gfx_v12_0_load_rlcg_microcode(adev); 2044 if (amdgpu_dpm == 1) { 2045 if (version_minor >= 2) 2046 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2047 } 2048 2049 return 0; 2050 } 2051 2052 return -EINVAL; 2053 } 2054 2055 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2056 { 2057 int r; 2058 2059 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2060 gfx_v12_0_init_csb(adev); 2061 2062 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2063 gfx_v12_0_rlc_enable_srm(adev); 2064 } else { 2065 if (amdgpu_sriov_vf(adev)) { 2066 gfx_v12_0_init_csb(adev); 2067 return 0; 2068 } 2069 2070 adev->gfx.rlc.funcs->stop(adev); 2071 2072 /* disable CG */ 2073 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2074 2075 /* disable PG */ 2076 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2077 2078 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2079 /* legacy rlc firmware loading */ 2080 r = gfx_v12_0_rlc_load_microcode(adev); 2081 if (r) 2082 return r; 2083 } 2084 2085 gfx_v12_0_init_csb(adev); 2086 2087 adev->gfx.rlc.funcs->start(adev); 2088 } 2089 2090 return 0; 2091 } 2092 2093 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2094 { 2095 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2096 const struct gfx_firmware_header_v2_0 *me_hdr; 2097 const struct gfx_firmware_header_v2_0 *mec_hdr; 2098 uint32_t pipe_id, tmp; 2099 2100 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2101 adev->gfx.mec_fw->data; 2102 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2103 adev->gfx.me_fw->data; 2104 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2105 adev->gfx.pfp_fw->data; 2106 2107 /* config pfp program start addr */ 2108 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2109 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2110 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2111 (pfp_hdr->ucode_start_addr_hi << 30) | 2112 (pfp_hdr->ucode_start_addr_lo >> 2)); 2113 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2114 pfp_hdr->ucode_start_addr_hi >> 2); 2115 } 2116 soc24_grbm_select(adev, 0, 0, 0, 0); 2117 2118 /* reset pfp pipe */ 2119 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2120 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2121 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2122 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2123 2124 /* clear pfp pipe reset */ 2125 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2127 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2128 2129 /* config me program start addr */ 2130 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2131 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2132 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2133 (me_hdr->ucode_start_addr_hi << 30) | 2134 (me_hdr->ucode_start_addr_lo >> 2)); 2135 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2136 me_hdr->ucode_start_addr_hi>>2); 2137 } 2138 soc24_grbm_select(adev, 0, 0, 0, 0); 2139 2140 /* reset me pipe */ 2141 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2144 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2145 2146 /* clear me pipe reset */ 2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2150 2151 /* config mec program start addr */ 2152 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2153 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2154 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2155 mec_hdr->ucode_start_addr_lo >> 2 | 2156 mec_hdr->ucode_start_addr_hi << 30); 2157 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2158 mec_hdr->ucode_start_addr_hi >> 2); 2159 } 2160 soc24_grbm_select(adev, 0, 0, 0, 0); 2161 2162 /* reset mec pipe */ 2163 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2164 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2165 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2166 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2167 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2169 2170 /* clear mec pipe reset */ 2171 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2172 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2173 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2174 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2175 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2176 } 2177 2178 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2179 { 2180 const struct gfx_firmware_header_v2_0 *cp_hdr; 2181 unsigned pipe_id, tmp; 2182 2183 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2184 adev->gfx.pfp_fw->data; 2185 mutex_lock(&adev->srbm_mutex); 2186 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2187 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2188 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2189 (cp_hdr->ucode_start_addr_hi << 30) | 2190 (cp_hdr->ucode_start_addr_lo >> 2)); 2191 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2192 cp_hdr->ucode_start_addr_hi>>2); 2193 2194 /* 2195 * Program CP_ME_CNTL to reset given PIPE to take 2196 * effect of CP_PFP_PRGRM_CNTR_START. 2197 */ 2198 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2199 if (pipe_id == 0) 2200 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2201 PFP_PIPE0_RESET, 1); 2202 else 2203 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2204 PFP_PIPE1_RESET, 1); 2205 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2206 2207 /* Clear pfp pipe0 reset bit. */ 2208 if (pipe_id == 0) 2209 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2210 PFP_PIPE0_RESET, 0); 2211 else 2212 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2213 PFP_PIPE1_RESET, 0); 2214 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2215 } 2216 soc24_grbm_select(adev, 0, 0, 0, 0); 2217 mutex_unlock(&adev->srbm_mutex); 2218 } 2219 2220 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2221 { 2222 const struct gfx_firmware_header_v2_0 *cp_hdr; 2223 unsigned pipe_id, tmp; 2224 2225 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2226 adev->gfx.me_fw->data; 2227 mutex_lock(&adev->srbm_mutex); 2228 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2229 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2230 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2231 (cp_hdr->ucode_start_addr_hi << 30) | 2232 (cp_hdr->ucode_start_addr_lo >> 2) ); 2233 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2234 cp_hdr->ucode_start_addr_hi>>2); 2235 2236 /* 2237 * Program CP_ME_CNTL to reset given PIPE to take 2238 * effect of CP_ME_PRGRM_CNTR_START. 2239 */ 2240 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2241 if (pipe_id == 0) 2242 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2243 ME_PIPE0_RESET, 1); 2244 else 2245 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2246 ME_PIPE1_RESET, 1); 2247 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2248 2249 /* Clear pfp pipe0 reset bit. */ 2250 if (pipe_id == 0) 2251 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2252 ME_PIPE0_RESET, 0); 2253 else 2254 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2255 ME_PIPE1_RESET, 0); 2256 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2257 } 2258 soc24_grbm_select(adev, 0, 0, 0, 0); 2259 mutex_unlock(&adev->srbm_mutex); 2260 } 2261 2262 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2263 { 2264 const struct gfx_firmware_header_v2_0 *cp_hdr; 2265 unsigned pipe_id; 2266 2267 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2268 adev->gfx.mec_fw->data; 2269 mutex_lock(&adev->srbm_mutex); 2270 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2271 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2272 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2273 cp_hdr->ucode_start_addr_lo >> 2 | 2274 cp_hdr->ucode_start_addr_hi << 30); 2275 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2276 cp_hdr->ucode_start_addr_hi >> 2); 2277 } 2278 soc24_grbm_select(adev, 0, 0, 0, 0); 2279 mutex_unlock(&adev->srbm_mutex); 2280 } 2281 2282 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2283 { 2284 uint32_t cp_status; 2285 uint32_t bootload_status; 2286 int i; 2287 2288 for (i = 0; i < adev->usec_timeout; i++) { 2289 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2290 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2291 2292 if ((cp_status == 0) && 2293 (REG_GET_FIELD(bootload_status, 2294 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2295 break; 2296 } 2297 udelay(1); 2298 if (amdgpu_emu_mode) 2299 msleep(10); 2300 } 2301 2302 if (i >= adev->usec_timeout) { 2303 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2304 return -ETIMEDOUT; 2305 } 2306 2307 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2308 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2309 gfx_v12_0_set_me_ucode_start_addr(adev); 2310 gfx_v12_0_set_mec_ucode_start_addr(adev); 2311 } 2312 2313 return 0; 2314 } 2315 2316 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2317 { 2318 int i; 2319 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2320 2321 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2322 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2323 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2324 2325 for (i = 0; i < adev->usec_timeout; i++) { 2326 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2327 break; 2328 udelay(1); 2329 } 2330 2331 if (i >= adev->usec_timeout) 2332 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2333 2334 return 0; 2335 } 2336 2337 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2338 { 2339 int r; 2340 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2341 const __le32 *fw_ucode, *fw_data; 2342 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2343 uint32_t tmp; 2344 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2345 2346 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2347 adev->gfx.pfp_fw->data; 2348 2349 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2350 2351 /* instruction */ 2352 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2353 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2354 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2355 /* data */ 2356 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2357 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2358 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2359 2360 /* 64kb align */ 2361 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2362 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2363 &adev->gfx.pfp.pfp_fw_obj, 2364 &adev->gfx.pfp.pfp_fw_gpu_addr, 2365 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2366 if (r) { 2367 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2368 gfx_v12_0_pfp_fini(adev); 2369 return r; 2370 } 2371 2372 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2373 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2374 &adev->gfx.pfp.pfp_fw_data_obj, 2375 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2376 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2377 if (r) { 2378 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2379 gfx_v12_0_pfp_fini(adev); 2380 return r; 2381 } 2382 2383 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2384 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2385 2386 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2387 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2388 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2389 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2390 2391 if (amdgpu_emu_mode == 1) 2392 adev->hdp.funcs->flush_hdp(adev, NULL); 2393 2394 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2395 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2396 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2397 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2398 2399 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2400 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2401 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2402 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2403 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2404 2405 /* 2406 * Programming any of the CP_PFP_IC_BASE registers 2407 * forces invalidation of the ME L1 I$. Wait for the 2408 * invalidation complete 2409 */ 2410 for (i = 0; i < usec_timeout; i++) { 2411 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2412 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2413 INVALIDATE_CACHE_COMPLETE)) 2414 break; 2415 udelay(1); 2416 } 2417 2418 if (i >= usec_timeout) { 2419 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2420 return -EINVAL; 2421 } 2422 2423 /* Prime the L1 instruction caches */ 2424 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2425 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2426 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2427 /* Waiting for cache primed*/ 2428 for (i = 0; i < usec_timeout; i++) { 2429 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2430 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2431 ICACHE_PRIMED)) 2432 break; 2433 udelay(1); 2434 } 2435 2436 if (i >= usec_timeout) { 2437 dev_err(adev->dev, "failed to prime instruction cache\n"); 2438 return -EINVAL; 2439 } 2440 2441 mutex_lock(&adev->srbm_mutex); 2442 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2443 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2444 2445 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2446 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2447 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2448 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2449 } 2450 soc24_grbm_select(adev, 0, 0, 0, 0); 2451 mutex_unlock(&adev->srbm_mutex); 2452 2453 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2454 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2455 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2456 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2457 2458 /* Invalidate the data caches */ 2459 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2460 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2461 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2462 2463 for (i = 0; i < usec_timeout; i++) { 2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2465 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2466 INVALIDATE_DCACHE_COMPLETE)) 2467 break; 2468 udelay(1); 2469 } 2470 2471 if (i >= usec_timeout) { 2472 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2473 return -EINVAL; 2474 } 2475 2476 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2477 2478 return 0; 2479 } 2480 2481 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2482 { 2483 int r; 2484 const struct gfx_firmware_header_v2_0 *me_hdr; 2485 const __le32 *fw_ucode, *fw_data; 2486 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2487 uint32_t tmp; 2488 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2489 2490 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2491 adev->gfx.me_fw->data; 2492 2493 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2494 2495 /* instruction */ 2496 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2497 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2498 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2499 /* data */ 2500 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2501 le32_to_cpu(me_hdr->data_offset_bytes)); 2502 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2503 2504 /* 64kb align*/ 2505 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2506 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2507 &adev->gfx.me.me_fw_obj, 2508 &adev->gfx.me.me_fw_gpu_addr, 2509 (void **)&adev->gfx.me.me_fw_ptr); 2510 if (r) { 2511 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2512 gfx_v12_0_me_fini(adev); 2513 return r; 2514 } 2515 2516 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2517 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2518 &adev->gfx.me.me_fw_data_obj, 2519 &adev->gfx.me.me_fw_data_gpu_addr, 2520 (void **)&adev->gfx.me.me_fw_data_ptr); 2521 if (r) { 2522 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2523 gfx_v12_0_me_fini(adev); 2524 return r; 2525 } 2526 2527 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2528 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2529 2530 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2531 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2532 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2533 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2534 2535 if (amdgpu_emu_mode == 1) 2536 adev->hdp.funcs->flush_hdp(adev, NULL); 2537 2538 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2539 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2540 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2541 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2542 2543 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2544 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2545 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2546 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2547 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2548 2549 /* 2550 * Programming any of the CP_ME_IC_BASE registers 2551 * forces invalidation of the ME L1 I$. Wait for the 2552 * invalidation complete 2553 */ 2554 for (i = 0; i < usec_timeout; i++) { 2555 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2556 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2557 INVALIDATE_CACHE_COMPLETE)) 2558 break; 2559 udelay(1); 2560 } 2561 2562 if (i >= usec_timeout) { 2563 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2564 return -EINVAL; 2565 } 2566 2567 /* Prime the instruction caches */ 2568 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2569 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2570 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2571 2572 /* Waiting for instruction cache primed*/ 2573 for (i = 0; i < usec_timeout; i++) { 2574 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2575 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2576 ICACHE_PRIMED)) 2577 break; 2578 udelay(1); 2579 } 2580 2581 if (i >= usec_timeout) { 2582 dev_err(adev->dev, "failed to prime instruction cache\n"); 2583 return -EINVAL; 2584 } 2585 2586 mutex_lock(&adev->srbm_mutex); 2587 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2588 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2589 2590 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2591 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2592 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2593 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2594 } 2595 soc24_grbm_select(adev, 0, 0, 0, 0); 2596 mutex_unlock(&adev->srbm_mutex); 2597 2598 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2599 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2600 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2601 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2602 2603 /* Invalidate the data caches */ 2604 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2605 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2607 2608 for (i = 0; i < usec_timeout; i++) { 2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2610 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2611 INVALIDATE_DCACHE_COMPLETE)) 2612 break; 2613 udelay(1); 2614 } 2615 2616 if (i >= usec_timeout) { 2617 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2618 return -EINVAL; 2619 } 2620 2621 gfx_v12_0_set_me_ucode_start_addr(adev); 2622 2623 return 0; 2624 } 2625 2626 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2627 { 2628 int r; 2629 2630 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2631 return -EINVAL; 2632 2633 gfx_v12_0_cp_gfx_enable(adev, false); 2634 2635 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2636 if (r) { 2637 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2638 return r; 2639 } 2640 2641 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2642 if (r) { 2643 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2644 return r; 2645 } 2646 2647 return 0; 2648 } 2649 2650 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2651 { 2652 /* init the CP */ 2653 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2654 adev->gfx.config.max_hw_contexts - 1); 2655 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2656 2657 if (!amdgpu_async_gfx_ring) 2658 gfx_v12_0_cp_gfx_enable(adev, true); 2659 2660 return 0; 2661 } 2662 2663 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2664 CP_PIPE_ID pipe) 2665 { 2666 u32 tmp; 2667 2668 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2669 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2670 2671 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2672 } 2673 2674 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2675 struct amdgpu_ring *ring) 2676 { 2677 u32 tmp; 2678 2679 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2680 if (ring->use_doorbell) { 2681 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2682 DOORBELL_OFFSET, ring->doorbell_index); 2683 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2684 DOORBELL_EN, 1); 2685 } else { 2686 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2687 DOORBELL_EN, 0); 2688 } 2689 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2690 2691 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2692 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2693 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2694 2695 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2696 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2697 } 2698 2699 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2700 { 2701 struct amdgpu_ring *ring; 2702 u32 tmp; 2703 u32 rb_bufsz; 2704 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2705 2706 /* Set the write pointer delay */ 2707 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2708 2709 /* set the RB to use vmid 0 */ 2710 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2711 2712 /* Init gfx ring 0 for pipe 0 */ 2713 mutex_lock(&adev->srbm_mutex); 2714 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2715 2716 /* Set ring buffer size */ 2717 ring = &adev->gfx.gfx_ring[0]; 2718 rb_bufsz = order_base_2(ring->ring_size / 8); 2719 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2720 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2721 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2722 2723 /* Initialize the ring buffer's write pointers */ 2724 ring->wptr = 0; 2725 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2726 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2727 2728 /* set the wb address whether it's enabled or not */ 2729 rptr_addr = ring->rptr_gpu_addr; 2730 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2731 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2732 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2733 2734 wptr_gpu_addr = ring->wptr_gpu_addr; 2735 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2736 lower_32_bits(wptr_gpu_addr)); 2737 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2738 upper_32_bits(wptr_gpu_addr)); 2739 2740 mdelay(1); 2741 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2742 2743 rb_addr = ring->gpu_addr >> 8; 2744 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2745 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2746 2747 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2748 2749 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2750 mutex_unlock(&adev->srbm_mutex); 2751 2752 /* Switch to pipe 0 */ 2753 mutex_lock(&adev->srbm_mutex); 2754 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2755 mutex_unlock(&adev->srbm_mutex); 2756 2757 /* start the ring */ 2758 gfx_v12_0_cp_gfx_start(adev); 2759 return 0; 2760 } 2761 2762 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2763 { 2764 u32 data; 2765 2766 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2767 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2768 enable ? 0 : 1); 2769 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2770 enable ? 0 : 1); 2771 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2772 enable ? 0 : 1); 2773 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2774 enable ? 0 : 1); 2775 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2776 enable ? 0 : 1); 2777 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2778 enable ? 1 : 0); 2779 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2780 enable ? 1 : 0); 2781 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2782 enable ? 1 : 0); 2783 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2784 enable ? 1 : 0); 2785 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2786 enable ? 0 : 1); 2787 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2788 2789 adev->gfx.kiq[0].ring.sched.ready = enable; 2790 2791 udelay(50); 2792 } 2793 2794 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2795 { 2796 const struct gfx_firmware_header_v2_0 *mec_hdr; 2797 const __le32 *fw_ucode, *fw_data; 2798 u32 tmp, fw_ucode_size, fw_data_size; 2799 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2800 u32 *fw_ucode_ptr, *fw_data_ptr; 2801 int r; 2802 2803 if (!adev->gfx.mec_fw) 2804 return -EINVAL; 2805 2806 gfx_v12_0_cp_compute_enable(adev, false); 2807 2808 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2809 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2810 2811 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2812 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2813 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2814 2815 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2816 le32_to_cpu(mec_hdr->data_offset_bytes)); 2817 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2818 2819 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2820 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2821 &adev->gfx.mec.mec_fw_obj, 2822 &adev->gfx.mec.mec_fw_gpu_addr, 2823 (void **)&fw_ucode_ptr); 2824 if (r) { 2825 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2826 gfx_v12_0_mec_fini(adev); 2827 return r; 2828 } 2829 2830 r = amdgpu_bo_create_reserved(adev, 2831 ALIGN(fw_data_size, 64 * 1024) * 2832 adev->gfx.mec.num_pipe_per_mec, 2833 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2834 &adev->gfx.mec.mec_fw_data_obj, 2835 &adev->gfx.mec.mec_fw_data_gpu_addr, 2836 (void **)&fw_data_ptr); 2837 if (r) { 2838 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2839 gfx_v12_0_mec_fini(adev); 2840 return r; 2841 } 2842 2843 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2844 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2845 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2846 } 2847 2848 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2849 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2850 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2851 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2852 2853 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2854 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2855 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2856 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2857 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2858 2859 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2860 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2861 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2862 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2863 2864 mutex_lock(&adev->srbm_mutex); 2865 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2866 soc24_grbm_select(adev, 1, i, 0, 0); 2867 2868 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2869 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2870 i * ALIGN(fw_data_size, 64 * 1024))); 2871 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2872 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2873 i * ALIGN(fw_data_size, 64 * 1024))); 2874 2875 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2876 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2877 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2878 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2879 } 2880 mutex_unlock(&adev->srbm_mutex); 2881 soc24_grbm_select(adev, 0, 0, 0, 0); 2882 2883 /* Trigger an invalidation of the L1 instruction caches */ 2884 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2885 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2886 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2887 2888 /* Wait for invalidation complete */ 2889 for (i = 0; i < usec_timeout; i++) { 2890 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2891 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2892 INVALIDATE_DCACHE_COMPLETE)) 2893 break; 2894 udelay(1); 2895 } 2896 2897 if (i >= usec_timeout) { 2898 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2899 return -EINVAL; 2900 } 2901 2902 /* Trigger an invalidation of the L1 instruction caches */ 2903 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2904 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2905 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2906 2907 /* Wait for invalidation complete */ 2908 for (i = 0; i < usec_timeout; i++) { 2909 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2910 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2911 INVALIDATE_CACHE_COMPLETE)) 2912 break; 2913 udelay(1); 2914 } 2915 2916 if (i >= usec_timeout) { 2917 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2918 return -EINVAL; 2919 } 2920 2921 gfx_v12_0_set_mec_ucode_start_addr(adev); 2922 2923 return 0; 2924 } 2925 2926 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2927 { 2928 uint32_t tmp; 2929 struct amdgpu_device *adev = ring->adev; 2930 2931 /* tell RLC which is KIQ queue */ 2932 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2933 tmp &= 0xffffff00; 2934 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2935 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2936 } 2937 2938 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2939 { 2940 /* set graphics engine doorbell range */ 2941 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2942 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2943 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2944 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2945 2946 /* set compute engine doorbell range */ 2947 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2948 (adev->doorbell_index.kiq * 2) << 2); 2949 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2950 (adev->doorbell_index.userqueue_end * 2) << 2); 2951 } 2952 2953 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2954 struct amdgpu_mqd_prop *prop) 2955 { 2956 struct v12_gfx_mqd *mqd = m; 2957 uint64_t hqd_gpu_addr, wb_gpu_addr; 2958 uint32_t tmp; 2959 uint32_t rb_bufsz; 2960 2961 /* set up gfx hqd wptr */ 2962 mqd->cp_gfx_hqd_wptr = 0; 2963 mqd->cp_gfx_hqd_wptr_hi = 0; 2964 2965 /* set the pointer to the MQD */ 2966 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2967 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2968 2969 /* set up mqd control */ 2970 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2971 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2972 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2973 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2974 mqd->cp_gfx_mqd_control = tmp; 2975 2976 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2977 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2978 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2979 mqd->cp_gfx_hqd_vmid = 0; 2980 2981 /* set up default queue priority level 2982 * 0x0 = low priority, 0x1 = high priority */ 2983 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2984 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2985 mqd->cp_gfx_hqd_queue_priority = tmp; 2986 2987 /* set up time quantum */ 2988 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2990 mqd->cp_gfx_hqd_quantum = tmp; 2991 2992 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2993 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2994 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2995 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2996 2997 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2998 wb_gpu_addr = prop->rptr_gpu_addr; 2999 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3000 mqd->cp_gfx_hqd_rptr_addr_hi = 3001 upper_32_bits(wb_gpu_addr) & 0xffff; 3002 3003 /* set up rb_wptr_poll addr */ 3004 wb_gpu_addr = prop->wptr_gpu_addr; 3005 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3006 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3007 3008 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3009 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3010 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3011 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3012 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3013 #ifdef __BIG_ENDIAN 3014 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3015 #endif 3016 mqd->cp_gfx_hqd_cntl = tmp; 3017 3018 /* set up cp_doorbell_control */ 3019 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3020 if (prop->use_doorbell) { 3021 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3022 DOORBELL_OFFSET, prop->doorbell_index); 3023 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3024 DOORBELL_EN, 1); 3025 } else 3026 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3027 DOORBELL_EN, 0); 3028 mqd->cp_rb_doorbell_control = tmp; 3029 3030 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3031 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3032 3033 /* active the queue */ 3034 mqd->cp_gfx_hqd_active = 1; 3035 3036 /* set gfx UQ items */ 3037 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3038 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3039 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3040 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3041 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3042 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3043 3044 return 0; 3045 } 3046 3047 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3048 { 3049 struct amdgpu_device *adev = ring->adev; 3050 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3051 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3052 3053 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3054 memset((void *)mqd, 0, sizeof(*mqd)); 3055 mutex_lock(&adev->srbm_mutex); 3056 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3057 amdgpu_ring_init_mqd(ring); 3058 soc24_grbm_select(adev, 0, 0, 0, 0); 3059 mutex_unlock(&adev->srbm_mutex); 3060 if (adev->gfx.me.mqd_backup[mqd_idx]) 3061 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3062 } else { 3063 /* restore mqd with the backup copy */ 3064 if (adev->gfx.me.mqd_backup[mqd_idx]) 3065 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3066 /* reset the ring */ 3067 ring->wptr = 0; 3068 *ring->wptr_cpu_addr = 0; 3069 amdgpu_ring_clear_ring(ring); 3070 } 3071 3072 return 0; 3073 } 3074 3075 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3076 { 3077 int i, r; 3078 3079 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3080 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3081 if (r) 3082 return r; 3083 } 3084 3085 r = amdgpu_gfx_enable_kgq(adev, 0); 3086 if (r) 3087 return r; 3088 3089 return gfx_v12_0_cp_gfx_start(adev); 3090 } 3091 3092 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3093 struct amdgpu_mqd_prop *prop) 3094 { 3095 struct v12_compute_mqd *mqd = m; 3096 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3097 uint32_t tmp; 3098 3099 mqd->header = 0xC0310800; 3100 mqd->compute_pipelinestat_enable = 0x00000001; 3101 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3102 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3103 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3104 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3105 mqd->compute_misc_reserved = 0x00000007; 3106 3107 eop_base_addr = prop->eop_gpu_addr >> 8; 3108 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3109 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3110 3111 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3112 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3113 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3114 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3115 3116 mqd->cp_hqd_eop_control = tmp; 3117 3118 /* enable doorbell? */ 3119 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3120 3121 if (prop->use_doorbell) { 3122 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3123 DOORBELL_OFFSET, prop->doorbell_index); 3124 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3125 DOORBELL_EN, 1); 3126 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3127 DOORBELL_SOURCE, 0); 3128 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3129 DOORBELL_HIT, 0); 3130 } else { 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_EN, 0); 3133 } 3134 3135 mqd->cp_hqd_pq_doorbell_control = tmp; 3136 3137 /* disable the queue if it's active */ 3138 mqd->cp_hqd_dequeue_request = 0; 3139 mqd->cp_hqd_pq_rptr = 0; 3140 mqd->cp_hqd_pq_wptr_lo = 0; 3141 mqd->cp_hqd_pq_wptr_hi = 0; 3142 3143 /* set the pointer to the MQD */ 3144 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3145 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3146 3147 /* set MQD vmid to 0 */ 3148 tmp = regCP_MQD_CONTROL_DEFAULT; 3149 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3150 mqd->cp_mqd_control = tmp; 3151 3152 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3153 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3154 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3155 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3156 3157 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3158 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3159 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3160 (order_base_2(prop->queue_size / 4) - 1)); 3161 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3162 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3163 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3165 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3167 mqd->cp_hqd_pq_control = tmp; 3168 3169 /* set the wb address whether it's enabled or not */ 3170 wb_gpu_addr = prop->rptr_gpu_addr; 3171 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3172 mqd->cp_hqd_pq_rptr_report_addr_hi = 3173 upper_32_bits(wb_gpu_addr) & 0xffff; 3174 3175 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3176 wb_gpu_addr = prop->wptr_gpu_addr; 3177 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3178 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3179 3180 tmp = 0; 3181 /* enable the doorbell if requested */ 3182 if (prop->use_doorbell) { 3183 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3185 DOORBELL_OFFSET, prop->doorbell_index); 3186 3187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3188 DOORBELL_EN, 1); 3189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3190 DOORBELL_SOURCE, 0); 3191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3192 DOORBELL_HIT, 0); 3193 } 3194 3195 mqd->cp_hqd_pq_doorbell_control = tmp; 3196 3197 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3198 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3199 3200 /* set the vmid for the queue */ 3201 mqd->cp_hqd_vmid = 0; 3202 3203 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3204 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3205 mqd->cp_hqd_persistent_state = tmp; 3206 3207 /* set MIN_IB_AVAIL_SIZE */ 3208 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3209 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3210 mqd->cp_hqd_ib_control = tmp; 3211 3212 /* set static priority for a compute queue/ring */ 3213 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3214 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3215 3216 mqd->cp_hqd_active = prop->hqd_active; 3217 3218 /* set UQ fenceaddress */ 3219 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3220 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3221 3222 return 0; 3223 } 3224 3225 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3226 { 3227 struct amdgpu_device *adev = ring->adev; 3228 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3229 int j; 3230 3231 /* inactivate the queue */ 3232 if (amdgpu_sriov_vf(adev)) 3233 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3234 3235 /* disable wptr polling */ 3236 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3237 3238 /* write the EOP addr */ 3239 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3240 mqd->cp_hqd_eop_base_addr_lo); 3241 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3242 mqd->cp_hqd_eop_base_addr_hi); 3243 3244 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3245 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3246 mqd->cp_hqd_eop_control); 3247 3248 /* enable doorbell? */ 3249 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3250 mqd->cp_hqd_pq_doorbell_control); 3251 3252 /* disable the queue if it's active */ 3253 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3254 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3255 for (j = 0; j < adev->usec_timeout; j++) { 3256 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3257 break; 3258 udelay(1); 3259 } 3260 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3261 mqd->cp_hqd_dequeue_request); 3262 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3263 mqd->cp_hqd_pq_rptr); 3264 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3265 mqd->cp_hqd_pq_wptr_lo); 3266 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3267 mqd->cp_hqd_pq_wptr_hi); 3268 } 3269 3270 /* set the pointer to the MQD */ 3271 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3272 mqd->cp_mqd_base_addr_lo); 3273 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3274 mqd->cp_mqd_base_addr_hi); 3275 3276 /* set MQD vmid to 0 */ 3277 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3278 mqd->cp_mqd_control); 3279 3280 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3282 mqd->cp_hqd_pq_base_lo); 3283 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3284 mqd->cp_hqd_pq_base_hi); 3285 3286 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3287 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3288 mqd->cp_hqd_pq_control); 3289 3290 /* set the wb address whether it's enabled or not */ 3291 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3292 mqd->cp_hqd_pq_rptr_report_addr_lo); 3293 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3294 mqd->cp_hqd_pq_rptr_report_addr_hi); 3295 3296 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3297 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3298 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3299 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3300 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3301 3302 /* enable the doorbell if requested */ 3303 if (ring->use_doorbell) { 3304 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3305 (adev->doorbell_index.kiq * 2) << 2); 3306 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3307 (adev->doorbell_index.userqueue_end * 2) << 2); 3308 } 3309 3310 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3311 mqd->cp_hqd_pq_doorbell_control); 3312 3313 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3314 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3315 mqd->cp_hqd_pq_wptr_lo); 3316 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3317 mqd->cp_hqd_pq_wptr_hi); 3318 3319 /* set the vmid for the queue */ 3320 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3321 3322 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3323 mqd->cp_hqd_persistent_state); 3324 3325 /* activate the queue */ 3326 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3327 mqd->cp_hqd_active); 3328 3329 if (ring->use_doorbell) 3330 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3331 3332 return 0; 3333 } 3334 3335 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3336 { 3337 struct amdgpu_device *adev = ring->adev; 3338 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3339 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3340 3341 gfx_v12_0_kiq_setting(ring); 3342 3343 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3344 /* reset MQD to a clean status */ 3345 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3346 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3347 3348 /* reset ring buffer */ 3349 ring->wptr = 0; 3350 amdgpu_ring_clear_ring(ring); 3351 3352 mutex_lock(&adev->srbm_mutex); 3353 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3354 gfx_v12_0_kiq_init_register(ring); 3355 soc24_grbm_select(adev, 0, 0, 0, 0); 3356 mutex_unlock(&adev->srbm_mutex); 3357 } else { 3358 memset((void *)mqd, 0, sizeof(*mqd)); 3359 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3360 amdgpu_ring_clear_ring(ring); 3361 mutex_lock(&adev->srbm_mutex); 3362 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3363 amdgpu_ring_init_mqd(ring); 3364 gfx_v12_0_kiq_init_register(ring); 3365 soc24_grbm_select(adev, 0, 0, 0, 0); 3366 mutex_unlock(&adev->srbm_mutex); 3367 3368 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3369 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3370 } 3371 3372 return 0; 3373 } 3374 3375 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3376 { 3377 struct amdgpu_device *adev = ring->adev; 3378 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3379 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3380 3381 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3382 memset((void *)mqd, 0, sizeof(*mqd)); 3383 mutex_lock(&adev->srbm_mutex); 3384 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3385 amdgpu_ring_init_mqd(ring); 3386 soc24_grbm_select(adev, 0, 0, 0, 0); 3387 mutex_unlock(&adev->srbm_mutex); 3388 3389 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3390 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3391 } else { 3392 /* restore MQD to a clean status */ 3393 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3394 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3395 /* reset ring buffer */ 3396 ring->wptr = 0; 3397 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3398 amdgpu_ring_clear_ring(ring); 3399 } 3400 3401 return 0; 3402 } 3403 3404 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3405 { 3406 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3407 adev->gfx.kiq[0].ring.sched.ready = true; 3408 return 0; 3409 } 3410 3411 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3412 { 3413 int i, r; 3414 3415 if (!amdgpu_async_gfx_ring) 3416 gfx_v12_0_cp_compute_enable(adev, true); 3417 3418 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3419 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3420 if (r) 3421 return r; 3422 } 3423 3424 return amdgpu_gfx_enable_kcq(adev, 0); 3425 } 3426 3427 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3428 { 3429 int r, i; 3430 struct amdgpu_ring *ring; 3431 3432 if (!(adev->flags & AMD_IS_APU)) 3433 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3434 3435 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3436 /* legacy firmware loading */ 3437 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3438 if (r) 3439 return r; 3440 3441 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3442 if (r) 3443 return r; 3444 } 3445 3446 gfx_v12_0_cp_set_doorbell_range(adev); 3447 3448 if (amdgpu_async_gfx_ring) { 3449 gfx_v12_0_cp_compute_enable(adev, true); 3450 gfx_v12_0_cp_gfx_enable(adev, true); 3451 } 3452 3453 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3454 r = amdgpu_mes_kiq_hw_init(adev); 3455 else 3456 r = gfx_v12_0_kiq_resume(adev); 3457 if (r) 3458 return r; 3459 3460 r = gfx_v12_0_kcq_resume(adev); 3461 if (r) 3462 return r; 3463 3464 if (!amdgpu_async_gfx_ring) { 3465 r = gfx_v12_0_cp_gfx_resume(adev); 3466 if (r) 3467 return r; 3468 } else { 3469 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3470 if (r) 3471 return r; 3472 } 3473 3474 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3475 ring = &adev->gfx.gfx_ring[i]; 3476 r = amdgpu_ring_test_helper(ring); 3477 if (r) 3478 return r; 3479 } 3480 3481 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3482 ring = &adev->gfx.compute_ring[i]; 3483 r = amdgpu_ring_test_helper(ring); 3484 if (r) 3485 return r; 3486 } 3487 3488 return 0; 3489 } 3490 3491 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3492 { 3493 gfx_v12_0_cp_gfx_enable(adev, enable); 3494 gfx_v12_0_cp_compute_enable(adev, enable); 3495 } 3496 3497 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3498 { 3499 int r; 3500 bool value; 3501 3502 r = adev->gfxhub.funcs->gart_enable(adev); 3503 if (r) 3504 return r; 3505 3506 adev->hdp.funcs->flush_hdp(adev, NULL); 3507 3508 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3509 false : true; 3510 3511 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3512 /* TODO investigate why this and the hdp flush above is needed, 3513 * are we missing a flush somewhere else? */ 3514 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3515 3516 return 0; 3517 } 3518 3519 static int get_gb_addr_config(struct amdgpu_device *adev) 3520 { 3521 u32 gb_addr_config; 3522 3523 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3524 if (gb_addr_config == 0) 3525 return -EINVAL; 3526 3527 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3528 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3529 3530 adev->gfx.config.gb_addr_config = gb_addr_config; 3531 3532 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3533 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3534 GB_ADDR_CONFIG, NUM_PIPES); 3535 3536 adev->gfx.config.max_tile_pipes = 3537 adev->gfx.config.gb_addr_config_fields.num_pipes; 3538 3539 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3540 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3541 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3542 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3543 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3544 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3545 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3546 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3547 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3548 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3549 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3550 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3551 3552 return 0; 3553 } 3554 3555 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3556 { 3557 uint32_t data; 3558 3559 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3560 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3561 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3562 3563 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3564 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3565 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3566 } 3567 3568 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3569 { 3570 if (amdgpu_sriov_vf(adev)) 3571 return; 3572 3573 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3574 case IP_VERSION(12, 0, 0): 3575 case IP_VERSION(12, 0, 1): 3576 soc15_program_register_sequence(adev, 3577 golden_settings_gc_12_0, 3578 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3579 3580 if (adev->rev_id == 0) 3581 soc15_program_register_sequence(adev, 3582 golden_settings_gc_12_0_rev0, 3583 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3584 break; 3585 default: 3586 break; 3587 } 3588 } 3589 3590 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3591 { 3592 int r; 3593 struct amdgpu_device *adev = ip_block->adev; 3594 3595 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3596 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3597 /* RLC autoload sequence 1: Program rlc ram */ 3598 if (adev->gfx.imu.funcs->program_rlc_ram) 3599 adev->gfx.imu.funcs->program_rlc_ram(adev); 3600 } 3601 /* rlc autoload firmware */ 3602 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3603 if (r) 3604 return r; 3605 } else { 3606 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3607 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3608 if (adev->gfx.imu.funcs->load_microcode) 3609 adev->gfx.imu.funcs->load_microcode(adev); 3610 if (adev->gfx.imu.funcs->setup_imu) 3611 adev->gfx.imu.funcs->setup_imu(adev); 3612 if (adev->gfx.imu.funcs->start_imu) 3613 adev->gfx.imu.funcs->start_imu(adev); 3614 } 3615 3616 /* disable gpa mode in backdoor loading */ 3617 gfx_v12_0_disable_gpa_mode(adev); 3618 } 3619 } 3620 3621 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3622 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3623 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3624 if (r) { 3625 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3626 return r; 3627 } 3628 } 3629 3630 if (!amdgpu_emu_mode) 3631 gfx_v12_0_init_golden_registers(adev); 3632 3633 adev->gfx.is_poweron = true; 3634 3635 if (get_gb_addr_config(adev)) 3636 DRM_WARN("Invalid gb_addr_config !\n"); 3637 3638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3639 gfx_v12_0_config_gfx_rs64(adev); 3640 3641 r = gfx_v12_0_gfxhub_enable(adev); 3642 if (r) 3643 return r; 3644 3645 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3646 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3647 (amdgpu_dpm == 1)) { 3648 /** 3649 * For gfx 12, rlc firmware loading relies on smu firmware is 3650 * loaded firstly, so in direct type, it has to load smc ucode 3651 * here before rlc. 3652 */ 3653 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3654 if (r) 3655 return r; 3656 } 3657 3658 gfx_v12_0_constants_init(adev); 3659 3660 if (adev->nbio.funcs->gc_doorbell_init) 3661 adev->nbio.funcs->gc_doorbell_init(adev); 3662 3663 r = gfx_v12_0_rlc_resume(adev); 3664 if (r) 3665 return r; 3666 3667 /* 3668 * init golden registers and rlc resume may override some registers, 3669 * reconfig them here 3670 */ 3671 gfx_v12_0_tcp_harvest(adev); 3672 3673 r = gfx_v12_0_cp_resume(adev); 3674 if (r) 3675 return r; 3676 3677 return r; 3678 } 3679 3680 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3681 bool enable) 3682 { 3683 if (adev->gfx.disable_kq) { 3684 unsigned int irq_type; 3685 int m, p, r; 3686 3687 for (m = 0; m < adev->gfx.me.num_me; m++) { 3688 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3689 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3690 if (enable) 3691 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3692 irq_type); 3693 else 3694 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3695 irq_type); 3696 if (r) 3697 return r; 3698 } 3699 } 3700 3701 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3702 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3703 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3704 + (m * adev->gfx.mec.num_pipe_per_mec) 3705 + p; 3706 if (enable) 3707 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3708 irq_type); 3709 else 3710 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3711 irq_type); 3712 if (r) 3713 return r; 3714 } 3715 } 3716 } 3717 return 0; 3718 } 3719 3720 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3721 { 3722 struct amdgpu_device *adev = ip_block->adev; 3723 uint32_t tmp; 3724 3725 cancel_delayed_work_sync(&adev->gfx.idle_work); 3726 3727 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3728 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3729 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3730 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3731 3732 if (!adev->no_hw_access) { 3733 if (amdgpu_async_gfx_ring) { 3734 if (amdgpu_gfx_disable_kgq(adev, 0)) 3735 DRM_ERROR("KGQ disable failed\n"); 3736 } 3737 3738 if (amdgpu_gfx_disable_kcq(adev, 0)) 3739 DRM_ERROR("KCQ disable failed\n"); 3740 3741 amdgpu_mes_kiq_hw_fini(adev); 3742 } 3743 3744 if (amdgpu_sriov_vf(adev)) { 3745 gfx_v12_0_cp_gfx_enable(adev, false); 3746 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3747 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3748 tmp &= 0xffffff00; 3749 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3750 3751 return 0; 3752 } 3753 gfx_v12_0_cp_enable(adev, false); 3754 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3755 3756 adev->gfxhub.funcs->gart_disable(adev); 3757 3758 adev->gfx.is_poweron = false; 3759 3760 return 0; 3761 } 3762 3763 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3764 { 3765 return gfx_v12_0_hw_fini(ip_block); 3766 } 3767 3768 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3769 { 3770 return gfx_v12_0_hw_init(ip_block); 3771 } 3772 3773 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3774 { 3775 struct amdgpu_device *adev = ip_block->adev; 3776 3777 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3778 GRBM_STATUS, GUI_ACTIVE)) 3779 return false; 3780 else 3781 return true; 3782 } 3783 3784 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3785 { 3786 unsigned i; 3787 u32 tmp; 3788 struct amdgpu_device *adev = ip_block->adev; 3789 3790 for (i = 0; i < adev->usec_timeout; i++) { 3791 /* read MC_STATUS */ 3792 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3793 GRBM_STATUS__GUI_ACTIVE_MASK; 3794 3795 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3796 return 0; 3797 udelay(1); 3798 } 3799 return -ETIMEDOUT; 3800 } 3801 3802 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3803 { 3804 uint64_t clock = 0; 3805 3806 if (adev->smuio.funcs && 3807 adev->smuio.funcs->get_gpu_clock_counter) 3808 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3809 else 3810 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3811 3812 return clock; 3813 } 3814 3815 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3816 { 3817 struct amdgpu_device *adev = ip_block->adev; 3818 3819 if (amdgpu_disable_kq == 1) 3820 adev->gfx.disable_kq = true; 3821 3822 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3823 3824 if (adev->gfx.disable_kq) { 3825 adev->gfx.num_gfx_rings = 0; 3826 adev->gfx.num_compute_rings = 0; 3827 } else { 3828 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3829 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3830 AMDGPU_MAX_COMPUTE_RINGS); 3831 } 3832 3833 gfx_v12_0_set_kiq_pm4_funcs(adev); 3834 gfx_v12_0_set_ring_funcs(adev); 3835 gfx_v12_0_set_irq_funcs(adev); 3836 gfx_v12_0_set_rlc_funcs(adev); 3837 gfx_v12_0_set_mqd_funcs(adev); 3838 gfx_v12_0_set_imu_funcs(adev); 3839 3840 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3841 3842 return gfx_v12_0_init_microcode(adev); 3843 } 3844 3845 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3846 { 3847 struct amdgpu_device *adev = ip_block->adev; 3848 int r; 3849 3850 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3851 if (r) 3852 return r; 3853 3854 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3855 if (r) 3856 return r; 3857 3858 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3859 if (r) 3860 return r; 3861 3862 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3863 if (r) 3864 return r; 3865 3866 return 0; 3867 } 3868 3869 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3870 { 3871 uint32_t rlc_cntl; 3872 3873 /* if RLC is not enabled, do nothing */ 3874 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3875 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3876 } 3877 3878 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3879 int xcc_id) 3880 { 3881 uint32_t data; 3882 unsigned i; 3883 3884 data = RLC_SAFE_MODE__CMD_MASK; 3885 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3886 3887 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3888 3889 /* wait for RLC_SAFE_MODE */ 3890 for (i = 0; i < adev->usec_timeout; i++) { 3891 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3892 RLC_SAFE_MODE, CMD)) 3893 break; 3894 udelay(1); 3895 } 3896 } 3897 3898 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3899 int xcc_id) 3900 { 3901 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3902 } 3903 3904 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3905 bool enable) 3906 { 3907 uint32_t def, data; 3908 3909 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3910 return; 3911 3912 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3913 3914 if (enable) 3915 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3916 else 3917 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3918 3919 if (def != data) 3920 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3921 } 3922 3923 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3924 struct amdgpu_ring *ring, 3925 unsigned vmid) 3926 { 3927 u32 reg, data; 3928 3929 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3930 if (amdgpu_sriov_is_pp_one_vf(adev)) 3931 data = RREG32_NO_KIQ(reg); 3932 else 3933 data = RREG32(reg); 3934 3935 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3936 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3937 3938 if (amdgpu_sriov_is_pp_one_vf(adev)) 3939 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3940 else 3941 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3942 3943 if (ring 3944 && amdgpu_sriov_is_pp_one_vf(adev) 3945 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3946 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3947 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3948 amdgpu_ring_emit_wreg(ring, reg, data); 3949 } 3950 } 3951 3952 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3953 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3954 .set_safe_mode = gfx_v12_0_set_safe_mode, 3955 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3956 .init = gfx_v12_0_rlc_init, 3957 .get_csb_size = gfx_v12_0_get_csb_size, 3958 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3959 .resume = gfx_v12_0_rlc_resume, 3960 .stop = gfx_v12_0_rlc_stop, 3961 .reset = gfx_v12_0_rlc_reset, 3962 .start = gfx_v12_0_rlc_start, 3963 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3964 }; 3965 3966 #if 0 3967 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3968 { 3969 /* TODO */ 3970 } 3971 3972 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3973 { 3974 /* TODO */ 3975 } 3976 #endif 3977 3978 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3979 enum amd_powergating_state state) 3980 { 3981 struct amdgpu_device *adev = ip_block->adev; 3982 bool enable = (state == AMD_PG_STATE_GATE); 3983 3984 if (amdgpu_sriov_vf(adev)) 3985 return 0; 3986 3987 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3988 case IP_VERSION(12, 0, 0): 3989 case IP_VERSION(12, 0, 1): 3990 amdgpu_gfx_off_ctrl(adev, enable); 3991 break; 3992 default: 3993 break; 3994 } 3995 3996 return 0; 3997 } 3998 3999 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4000 bool enable) 4001 { 4002 uint32_t def, data; 4003 4004 if (!(adev->cg_flags & 4005 (AMD_CG_SUPPORT_GFX_CGCG | 4006 AMD_CG_SUPPORT_GFX_CGLS | 4007 AMD_CG_SUPPORT_GFX_3D_CGCG | 4008 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4009 return; 4010 4011 if (enable) { 4012 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4013 4014 /* unset CGCG override */ 4015 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4016 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4017 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4018 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4019 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4020 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4021 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4022 4023 /* update CGCG override bits */ 4024 if (def != data) 4025 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4026 4027 /* enable cgcg FSM(0x0000363F) */ 4028 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4029 4030 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4031 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4032 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4033 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4034 } 4035 4036 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4037 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4038 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4039 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4040 } 4041 4042 if (def != data) 4043 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4044 4045 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4046 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4047 4048 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4049 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4050 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4051 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4052 } 4053 4054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4055 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4056 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4057 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4058 } 4059 4060 if (def != data) 4061 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4062 4063 /* set IDLE_POLL_COUNT(0x00900100) */ 4064 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4065 4066 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4067 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4068 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4069 4070 if (def != data) 4071 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4072 4073 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4074 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4075 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4076 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4077 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4078 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4079 4080 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4081 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4082 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4083 4084 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4085 if (adev->sdma.num_instances > 1) { 4086 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4087 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4088 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4089 } 4090 } else { 4091 /* Program RLC_CGCG_CGLS_CTRL */ 4092 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4093 4094 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4095 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4096 4097 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4098 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4099 4100 if (def != data) 4101 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4102 4103 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4104 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4105 4106 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4107 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4108 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4109 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4110 4111 if (def != data) 4112 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4113 } 4114 } 4115 4116 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4117 bool enable) 4118 { 4119 uint32_t data, def; 4120 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4121 return; 4122 4123 /* It is disabled by HW by default */ 4124 if (enable) { 4125 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4126 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4127 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4128 4129 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4130 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4131 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4132 4133 if (def != data) 4134 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4135 } 4136 } else { 4137 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4138 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4139 4140 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4141 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4142 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4143 4144 if (def != data) 4145 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4146 } 4147 } 4148 } 4149 4150 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4151 bool enable) 4152 { 4153 uint32_t def, data; 4154 4155 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4156 return; 4157 4158 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4159 4160 if (enable) 4161 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4162 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4163 else 4164 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4165 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4166 4167 if (def != data) 4168 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4169 } 4170 4171 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4172 bool enable) 4173 { 4174 uint32_t def, data; 4175 4176 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4177 return; 4178 4179 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4180 4181 if (enable) 4182 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4183 else 4184 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4185 4186 if (def != data) 4187 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4188 } 4189 4190 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4191 bool enable) 4192 { 4193 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4194 4195 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4196 4197 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4198 4199 gfx_v12_0_update_repeater_fgcg(adev, enable); 4200 4201 gfx_v12_0_update_sram_fgcg(adev, enable); 4202 4203 gfx_v12_0_update_perf_clk(adev, enable); 4204 4205 if (adev->cg_flags & 4206 (AMD_CG_SUPPORT_GFX_MGCG | 4207 AMD_CG_SUPPORT_GFX_CGLS | 4208 AMD_CG_SUPPORT_GFX_CGCG | 4209 AMD_CG_SUPPORT_GFX_3D_CGCG | 4210 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4211 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4212 4213 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4214 4215 return 0; 4216 } 4217 4218 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4219 enum amd_clockgating_state state) 4220 { 4221 struct amdgpu_device *adev = ip_block->adev; 4222 4223 if (amdgpu_sriov_vf(adev)) 4224 return 0; 4225 4226 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4227 case IP_VERSION(12, 0, 0): 4228 case IP_VERSION(12, 0, 1): 4229 gfx_v12_0_update_gfx_clock_gating(adev, 4230 state == AMD_CG_STATE_GATE); 4231 break; 4232 default: 4233 break; 4234 } 4235 4236 return 0; 4237 } 4238 4239 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4240 { 4241 struct amdgpu_device *adev = ip_block->adev; 4242 int data; 4243 4244 /* AMD_CG_SUPPORT_GFX_MGCG */ 4245 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4246 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4247 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4248 4249 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4250 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4251 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4252 4253 /* AMD_CG_SUPPORT_GFX_FGCG */ 4254 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4255 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4256 4257 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4258 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4259 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4260 4261 /* AMD_CG_SUPPORT_GFX_CGCG */ 4262 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4263 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4264 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4265 4266 /* AMD_CG_SUPPORT_GFX_CGLS */ 4267 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4268 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4269 4270 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4271 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4272 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4273 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4274 4275 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4276 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4277 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4278 } 4279 4280 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4281 { 4282 /* gfx12 is 32bit rptr*/ 4283 return *(uint32_t *)ring->rptr_cpu_addr; 4284 } 4285 4286 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4287 { 4288 struct amdgpu_device *adev = ring->adev; 4289 u64 wptr; 4290 4291 /* XXX check if swapping is necessary on BE */ 4292 if (ring->use_doorbell) { 4293 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4294 } else { 4295 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4296 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4297 } 4298 4299 return wptr; 4300 } 4301 4302 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4303 { 4304 struct amdgpu_device *adev = ring->adev; 4305 4306 if (ring->use_doorbell) { 4307 /* XXX check if swapping is necessary on BE */ 4308 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4309 ring->wptr); 4310 WDOORBELL64(ring->doorbell_index, ring->wptr); 4311 } else { 4312 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4313 lower_32_bits(ring->wptr)); 4314 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4315 upper_32_bits(ring->wptr)); 4316 } 4317 } 4318 4319 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4320 { 4321 /* gfx12 hardware is 32bit rptr */ 4322 return *(uint32_t *)ring->rptr_cpu_addr; 4323 } 4324 4325 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4326 { 4327 u64 wptr; 4328 4329 /* XXX check if swapping is necessary on BE */ 4330 if (ring->use_doorbell) 4331 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4332 else 4333 BUG(); 4334 return wptr; 4335 } 4336 4337 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4338 { 4339 struct amdgpu_device *adev = ring->adev; 4340 4341 /* XXX check if swapping is necessary on BE */ 4342 if (ring->use_doorbell) { 4343 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4344 ring->wptr); 4345 WDOORBELL64(ring->doorbell_index, ring->wptr); 4346 } else { 4347 BUG(); /* only DOORBELL method supported on gfx12 now */ 4348 } 4349 } 4350 4351 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4352 { 4353 struct amdgpu_device *adev = ring->adev; 4354 u32 ref_and_mask, reg_mem_engine; 4355 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4356 4357 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4358 switch (ring->me) { 4359 case 1: 4360 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4361 break; 4362 case 2: 4363 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4364 break; 4365 default: 4366 return; 4367 } 4368 reg_mem_engine = 0; 4369 } else { 4370 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4371 reg_mem_engine = 1; /* pfp */ 4372 } 4373 4374 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4375 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4376 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4377 ref_and_mask, ref_and_mask, 0x20); 4378 } 4379 4380 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4381 struct amdgpu_job *job, 4382 struct amdgpu_ib *ib, 4383 uint32_t flags) 4384 { 4385 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4386 u32 header, control = 0; 4387 4388 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4389 4390 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4391 4392 control |= ib->length_dw | (vmid << 24); 4393 4394 amdgpu_ring_write(ring, header); 4395 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4396 amdgpu_ring_write(ring, 4397 #ifdef __BIG_ENDIAN 4398 (2 << 0) | 4399 #endif 4400 lower_32_bits(ib->gpu_addr)); 4401 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4402 amdgpu_ring_write(ring, control); 4403 } 4404 4405 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4406 struct amdgpu_job *job, 4407 struct amdgpu_ib *ib, 4408 uint32_t flags) 4409 { 4410 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4411 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4412 4413 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4414 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4415 amdgpu_ring_write(ring, 4416 #ifdef __BIG_ENDIAN 4417 (2 << 0) | 4418 #endif 4419 lower_32_bits(ib->gpu_addr)); 4420 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4421 amdgpu_ring_write(ring, control); 4422 } 4423 4424 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4425 u64 seq, unsigned flags) 4426 { 4427 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4428 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4429 4430 /* RELEASE_MEM - flush caches, send int */ 4431 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4432 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4433 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4434 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4435 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4436 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4437 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4438 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4439 4440 /* 4441 * the address should be Qword aligned if 64bit write, Dword 4442 * aligned if only send 32bit data low (discard data high) 4443 */ 4444 if (write64bit) 4445 BUG_ON(addr & 0x7); 4446 else 4447 BUG_ON(addr & 0x3); 4448 amdgpu_ring_write(ring, lower_32_bits(addr)); 4449 amdgpu_ring_write(ring, upper_32_bits(addr)); 4450 amdgpu_ring_write(ring, lower_32_bits(seq)); 4451 amdgpu_ring_write(ring, upper_32_bits(seq)); 4452 amdgpu_ring_write(ring, 0); 4453 } 4454 4455 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4456 { 4457 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4458 uint32_t seq = ring->fence_drv.sync_seq; 4459 uint64_t addr = ring->fence_drv.gpu_addr; 4460 4461 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4462 upper_32_bits(addr), seq, 0xffffffff, 4); 4463 } 4464 4465 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4466 uint16_t pasid, uint32_t flush_type, 4467 bool all_hub, uint8_t dst_sel) 4468 { 4469 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4470 amdgpu_ring_write(ring, 4471 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4472 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4473 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4474 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4475 } 4476 4477 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4478 unsigned vmid, uint64_t pd_addr) 4479 { 4480 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4481 4482 /* compute doesn't have PFP */ 4483 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4484 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4485 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4486 amdgpu_ring_write(ring, 0x0); 4487 } 4488 } 4489 4490 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4491 u64 seq, unsigned int flags) 4492 { 4493 struct amdgpu_device *adev = ring->adev; 4494 4495 /* we only allocate 32bit for each seq wb address */ 4496 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4497 4498 /* write fence seq to the "addr" */ 4499 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4500 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4501 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4502 amdgpu_ring_write(ring, lower_32_bits(addr)); 4503 amdgpu_ring_write(ring, upper_32_bits(addr)); 4504 amdgpu_ring_write(ring, lower_32_bits(seq)); 4505 4506 if (flags & AMDGPU_FENCE_FLAG_INT) { 4507 /* set register to trigger INT */ 4508 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4509 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4510 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4511 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4512 amdgpu_ring_write(ring, 0); 4513 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4514 } 4515 } 4516 4517 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4518 uint32_t flags) 4519 { 4520 uint32_t dw2 = 0; 4521 4522 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4523 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4524 /* set load_global_config & load_global_uconfig */ 4525 dw2 |= 0x8001; 4526 /* set load_cs_sh_regs */ 4527 dw2 |= 0x01000000; 4528 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4529 dw2 |= 0x10002; 4530 } 4531 4532 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4533 amdgpu_ring_write(ring, dw2); 4534 amdgpu_ring_write(ring, 0); 4535 } 4536 4537 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4538 uint64_t addr) 4539 { 4540 unsigned ret; 4541 4542 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4543 amdgpu_ring_write(ring, lower_32_bits(addr)); 4544 amdgpu_ring_write(ring, upper_32_bits(addr)); 4545 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4546 amdgpu_ring_write(ring, 0); 4547 ret = ring->wptr & ring->buf_mask; 4548 /* patch dummy value later */ 4549 amdgpu_ring_write(ring, 0); 4550 4551 return ret; 4552 } 4553 4554 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4555 { 4556 int i, r = 0; 4557 struct amdgpu_device *adev = ring->adev; 4558 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4559 struct amdgpu_ring *kiq_ring = &kiq->ring; 4560 unsigned long flags; 4561 4562 if (adev->enable_mes) 4563 return -EINVAL; 4564 4565 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4566 return -EINVAL; 4567 4568 spin_lock_irqsave(&kiq->ring_lock, flags); 4569 4570 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4571 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4572 return -ENOMEM; 4573 } 4574 4575 /* assert preemption condition */ 4576 amdgpu_ring_set_preempt_cond_exec(ring, false); 4577 4578 /* assert IB preemption, emit the trailing fence */ 4579 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4580 ring->trail_fence_gpu_addr, 4581 ++ring->trail_seq); 4582 amdgpu_ring_commit(kiq_ring); 4583 4584 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4585 4586 /* poll the trailing fence */ 4587 for (i = 0; i < adev->usec_timeout; i++) { 4588 if (ring->trail_seq == 4589 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4590 break; 4591 udelay(1); 4592 } 4593 4594 if (i >= adev->usec_timeout) { 4595 r = -EINVAL; 4596 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4597 } 4598 4599 /* deassert preemption condition */ 4600 amdgpu_ring_set_preempt_cond_exec(ring, true); 4601 return r; 4602 } 4603 4604 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4605 bool start, 4606 bool secure) 4607 { 4608 uint32_t v = secure ? FRAME_TMZ : 0; 4609 4610 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4611 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4612 } 4613 4614 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4615 uint32_t reg_val_offs) 4616 { 4617 struct amdgpu_device *adev = ring->adev; 4618 4619 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4620 amdgpu_ring_write(ring, 0 | /* src: register*/ 4621 (5 << 8) | /* dst: memory */ 4622 (1 << 20)); /* write confirm */ 4623 amdgpu_ring_write(ring, reg); 4624 amdgpu_ring_write(ring, 0); 4625 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4626 reg_val_offs * 4)); 4627 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4628 reg_val_offs * 4)); 4629 } 4630 4631 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4632 uint32_t reg, 4633 uint32_t val) 4634 { 4635 uint32_t cmd = 0; 4636 4637 switch (ring->funcs->type) { 4638 case AMDGPU_RING_TYPE_GFX: 4639 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4640 break; 4641 case AMDGPU_RING_TYPE_KIQ: 4642 cmd = (1 << 16); /* no inc addr */ 4643 break; 4644 default: 4645 cmd = WR_CONFIRM; 4646 break; 4647 } 4648 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4649 amdgpu_ring_write(ring, cmd); 4650 amdgpu_ring_write(ring, reg); 4651 amdgpu_ring_write(ring, 0); 4652 amdgpu_ring_write(ring, val); 4653 } 4654 4655 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4656 uint32_t val, uint32_t mask) 4657 { 4658 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4659 } 4660 4661 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4662 uint32_t reg0, uint32_t reg1, 4663 uint32_t ref, uint32_t mask) 4664 { 4665 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4666 4667 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4668 ref, mask, 0x20); 4669 } 4670 4671 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4672 unsigned vmid) 4673 { 4674 struct amdgpu_device *adev = ring->adev; 4675 uint32_t value = 0; 4676 4677 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4678 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4679 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4680 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4681 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4682 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4683 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4684 } 4685 4686 static void 4687 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4688 uint32_t me, uint32_t pipe, 4689 enum amdgpu_interrupt_state state) 4690 { 4691 uint32_t cp_int_cntl, cp_int_cntl_reg; 4692 4693 if (!me) { 4694 switch (pipe) { 4695 case 0: 4696 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4697 break; 4698 default: 4699 DRM_DEBUG("invalid pipe %d\n", pipe); 4700 return; 4701 } 4702 } else { 4703 DRM_DEBUG("invalid me %d\n", me); 4704 return; 4705 } 4706 4707 switch (state) { 4708 case AMDGPU_IRQ_STATE_DISABLE: 4709 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4710 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4711 TIME_STAMP_INT_ENABLE, 0); 4712 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4713 GENERIC0_INT_ENABLE, 0); 4714 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4715 break; 4716 case AMDGPU_IRQ_STATE_ENABLE: 4717 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4718 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4719 TIME_STAMP_INT_ENABLE, 1); 4720 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4721 GENERIC0_INT_ENABLE, 1); 4722 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4723 break; 4724 default: 4725 break; 4726 } 4727 } 4728 4729 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4730 int me, int pipe, 4731 enum amdgpu_interrupt_state state) 4732 { 4733 u32 mec_int_cntl, mec_int_cntl_reg; 4734 4735 /* 4736 * amdgpu controls only the first MEC. That's why this function only 4737 * handles the setting of interrupts for this specific MEC. All other 4738 * pipes' interrupts are set by amdkfd. 4739 */ 4740 4741 if (me == 1) { 4742 switch (pipe) { 4743 case 0: 4744 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4745 break; 4746 case 1: 4747 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4748 break; 4749 default: 4750 DRM_DEBUG("invalid pipe %d\n", pipe); 4751 return; 4752 } 4753 } else { 4754 DRM_DEBUG("invalid me %d\n", me); 4755 return; 4756 } 4757 4758 switch (state) { 4759 case AMDGPU_IRQ_STATE_DISABLE: 4760 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4761 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4762 TIME_STAMP_INT_ENABLE, 0); 4763 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4764 GENERIC0_INT_ENABLE, 0); 4765 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4766 break; 4767 case AMDGPU_IRQ_STATE_ENABLE: 4768 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4769 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4770 TIME_STAMP_INT_ENABLE, 1); 4771 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4772 GENERIC0_INT_ENABLE, 1); 4773 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4774 break; 4775 default: 4776 break; 4777 } 4778 } 4779 4780 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4781 struct amdgpu_irq_src *src, 4782 unsigned type, 4783 enum amdgpu_interrupt_state state) 4784 { 4785 switch (type) { 4786 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4787 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4788 break; 4789 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4790 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4791 break; 4792 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4793 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4794 break; 4795 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4796 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4797 break; 4798 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4799 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4800 break; 4801 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4802 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4803 break; 4804 default: 4805 break; 4806 } 4807 return 0; 4808 } 4809 4810 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4811 struct amdgpu_irq_src *source, 4812 struct amdgpu_iv_entry *entry) 4813 { 4814 u32 doorbell_offset = entry->src_data[0]; 4815 u8 me_id, pipe_id, queue_id; 4816 struct amdgpu_ring *ring; 4817 int i; 4818 4819 DRM_DEBUG("IH: CP EOP\n"); 4820 4821 if (adev->enable_mes && doorbell_offset) { 4822 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4823 struct xarray *xa = &adev->userq_xa; 4824 unsigned long flags; 4825 4826 xa_lock_irqsave(xa, flags); 4827 fence_drv = xa_load(xa, doorbell_offset); 4828 if (fence_drv) 4829 amdgpu_userq_fence_driver_process(fence_drv); 4830 xa_unlock_irqrestore(xa, flags); 4831 } else { 4832 me_id = (entry->ring_id & 0x0c) >> 2; 4833 pipe_id = (entry->ring_id & 0x03) >> 0; 4834 queue_id = (entry->ring_id & 0x70) >> 4; 4835 4836 switch (me_id) { 4837 case 0: 4838 if (pipe_id == 0) 4839 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4840 else 4841 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4842 break; 4843 case 1: 4844 case 2: 4845 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4846 ring = &adev->gfx.compute_ring[i]; 4847 /* Per-queue interrupt is supported for MEC starting from VI. 4848 * The interrupt can only be enabled/disabled per pipe instead 4849 * of per queue. 4850 */ 4851 if ((ring->me == me_id) && 4852 (ring->pipe == pipe_id) && 4853 (ring->queue == queue_id)) 4854 amdgpu_fence_process(ring); 4855 } 4856 break; 4857 } 4858 } 4859 4860 return 0; 4861 } 4862 4863 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4864 struct amdgpu_irq_src *source, 4865 unsigned int type, 4866 enum amdgpu_interrupt_state state) 4867 { 4868 u32 cp_int_cntl_reg, cp_int_cntl; 4869 int i, j; 4870 4871 switch (state) { 4872 case AMDGPU_IRQ_STATE_DISABLE: 4873 case AMDGPU_IRQ_STATE_ENABLE: 4874 for (i = 0; i < adev->gfx.me.num_me; i++) { 4875 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4876 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4877 4878 if (cp_int_cntl_reg) { 4879 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4880 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4881 PRIV_REG_INT_ENABLE, 4882 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4883 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4884 } 4885 } 4886 } 4887 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4888 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4889 /* MECs start at 1 */ 4890 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4891 4892 if (cp_int_cntl_reg) { 4893 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4894 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4895 PRIV_REG_INT_ENABLE, 4896 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4897 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4898 } 4899 } 4900 } 4901 break; 4902 default: 4903 break; 4904 } 4905 4906 return 0; 4907 } 4908 4909 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4910 struct amdgpu_irq_src *source, 4911 unsigned type, 4912 enum amdgpu_interrupt_state state) 4913 { 4914 u32 cp_int_cntl_reg, cp_int_cntl; 4915 int i, j; 4916 4917 switch (state) { 4918 case AMDGPU_IRQ_STATE_DISABLE: 4919 case AMDGPU_IRQ_STATE_ENABLE: 4920 for (i = 0; i < adev->gfx.me.num_me; i++) { 4921 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4922 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4923 4924 if (cp_int_cntl_reg) { 4925 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4926 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4927 OPCODE_ERROR_INT_ENABLE, 4928 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4929 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4930 } 4931 } 4932 } 4933 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4934 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4935 /* MECs start at 1 */ 4936 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4937 4938 if (cp_int_cntl_reg) { 4939 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4940 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4941 OPCODE_ERROR_INT_ENABLE, 4942 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4943 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4944 } 4945 } 4946 } 4947 break; 4948 default: 4949 break; 4950 } 4951 return 0; 4952 } 4953 4954 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4955 struct amdgpu_irq_src *source, 4956 unsigned int type, 4957 enum amdgpu_interrupt_state state) 4958 { 4959 u32 cp_int_cntl_reg, cp_int_cntl; 4960 int i, j; 4961 4962 switch (state) { 4963 case AMDGPU_IRQ_STATE_DISABLE: 4964 case AMDGPU_IRQ_STATE_ENABLE: 4965 for (i = 0; i < adev->gfx.me.num_me; i++) { 4966 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4967 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4968 4969 if (cp_int_cntl_reg) { 4970 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4971 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4972 PRIV_INSTR_INT_ENABLE, 4973 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4974 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4975 } 4976 } 4977 } 4978 break; 4979 default: 4980 break; 4981 } 4982 4983 return 0; 4984 } 4985 4986 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4987 struct amdgpu_iv_entry *entry) 4988 { 4989 u8 me_id, pipe_id, queue_id; 4990 struct amdgpu_ring *ring; 4991 int i; 4992 4993 me_id = (entry->ring_id & 0x0c) >> 2; 4994 pipe_id = (entry->ring_id & 0x03) >> 0; 4995 queue_id = (entry->ring_id & 0x70) >> 4; 4996 4997 if (!adev->gfx.disable_kq) { 4998 switch (me_id) { 4999 case 0: 5000 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5001 ring = &adev->gfx.gfx_ring[i]; 5002 if (ring->me == me_id && ring->pipe == pipe_id && 5003 ring->queue == queue_id) 5004 drm_sched_fault(&ring->sched); 5005 } 5006 break; 5007 case 1: 5008 case 2: 5009 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5010 ring = &adev->gfx.compute_ring[i]; 5011 if (ring->me == me_id && ring->pipe == pipe_id && 5012 ring->queue == queue_id) 5013 drm_sched_fault(&ring->sched); 5014 } 5015 break; 5016 default: 5017 BUG(); 5018 break; 5019 } 5020 } 5021 } 5022 5023 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5024 struct amdgpu_irq_src *source, 5025 struct amdgpu_iv_entry *entry) 5026 { 5027 DRM_ERROR("Illegal register access in command stream\n"); 5028 gfx_v12_0_handle_priv_fault(adev, entry); 5029 return 0; 5030 } 5031 5032 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5033 struct amdgpu_irq_src *source, 5034 struct amdgpu_iv_entry *entry) 5035 { 5036 DRM_ERROR("Illegal opcode in command stream \n"); 5037 gfx_v12_0_handle_priv_fault(adev, entry); 5038 return 0; 5039 } 5040 5041 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5042 struct amdgpu_irq_src *source, 5043 struct amdgpu_iv_entry *entry) 5044 { 5045 DRM_ERROR("Illegal instruction in command stream\n"); 5046 gfx_v12_0_handle_priv_fault(adev, entry); 5047 return 0; 5048 } 5049 5050 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5051 { 5052 const unsigned int gcr_cntl = 5053 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5054 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5055 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5056 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5057 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5058 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5059 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5060 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5061 5062 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5063 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5064 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5065 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5066 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5067 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5068 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5069 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5070 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5071 } 5072 5073 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5074 { 5075 /* Header itself is a NOP packet */ 5076 if (num_nop == 1) { 5077 amdgpu_ring_write(ring, ring->funcs->nop); 5078 return; 5079 } 5080 5081 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5082 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5083 5084 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5085 amdgpu_ring_insert_nop(ring, num_nop - 1); 5086 } 5087 5088 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5089 { 5090 /* Emit the cleaner shader */ 5091 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5092 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5093 } 5094 5095 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5096 { 5097 struct amdgpu_device *adev = ip_block->adev; 5098 uint32_t i, j, k, reg, index = 0; 5099 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5100 5101 if (!adev->gfx.ip_dump_core) 5102 return; 5103 5104 for (i = 0; i < reg_count; i++) 5105 drm_printf(p, "%-50s \t 0x%08x\n", 5106 gc_reg_list_12_0[i].reg_name, 5107 adev->gfx.ip_dump_core[i]); 5108 5109 /* print compute queue registers for all instances */ 5110 if (!adev->gfx.ip_dump_compute_queues) 5111 return; 5112 5113 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5114 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5115 adev->gfx.mec.num_mec, 5116 adev->gfx.mec.num_pipe_per_mec, 5117 adev->gfx.mec.num_queue_per_pipe); 5118 5119 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5120 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5121 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5122 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5123 for (reg = 0; reg < reg_count; reg++) { 5124 drm_printf(p, "%-50s \t 0x%08x\n", 5125 gc_cp_reg_list_12[reg].reg_name, 5126 adev->gfx.ip_dump_compute_queues[index + reg]); 5127 } 5128 index += reg_count; 5129 } 5130 } 5131 } 5132 5133 /* print gfx queue registers for all instances */ 5134 if (!adev->gfx.ip_dump_gfx_queues) 5135 return; 5136 5137 index = 0; 5138 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5139 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5140 adev->gfx.me.num_me, 5141 adev->gfx.me.num_pipe_per_me, 5142 adev->gfx.me.num_queue_per_pipe); 5143 5144 for (i = 0; i < adev->gfx.me.num_me; i++) { 5145 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5146 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5147 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5148 for (reg = 0; reg < reg_count; reg++) { 5149 drm_printf(p, "%-50s \t 0x%08x\n", 5150 gc_gfx_queue_reg_list_12[reg].reg_name, 5151 adev->gfx.ip_dump_gfx_queues[index + reg]); 5152 } 5153 index += reg_count; 5154 } 5155 } 5156 } 5157 } 5158 5159 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5160 { 5161 struct amdgpu_device *adev = ip_block->adev; 5162 uint32_t i, j, k, reg, index = 0; 5163 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5164 5165 if (!adev->gfx.ip_dump_core) 5166 return; 5167 5168 amdgpu_gfx_off_ctrl(adev, false); 5169 for (i = 0; i < reg_count; i++) 5170 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5171 amdgpu_gfx_off_ctrl(adev, true); 5172 5173 /* dump compute queue registers for all instances */ 5174 if (!adev->gfx.ip_dump_compute_queues) 5175 return; 5176 5177 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5178 amdgpu_gfx_off_ctrl(adev, false); 5179 mutex_lock(&adev->srbm_mutex); 5180 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5181 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5182 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5183 /* ME0 is for GFX so start from 1 for CP */ 5184 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5185 for (reg = 0; reg < reg_count; reg++) { 5186 adev->gfx.ip_dump_compute_queues[index + reg] = 5187 RREG32(SOC15_REG_ENTRY_OFFSET( 5188 gc_cp_reg_list_12[reg])); 5189 } 5190 index += reg_count; 5191 } 5192 } 5193 } 5194 soc24_grbm_select(adev, 0, 0, 0, 0); 5195 mutex_unlock(&adev->srbm_mutex); 5196 amdgpu_gfx_off_ctrl(adev, true); 5197 5198 /* dump gfx queue registers for all instances */ 5199 if (!adev->gfx.ip_dump_gfx_queues) 5200 return; 5201 5202 index = 0; 5203 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5204 amdgpu_gfx_off_ctrl(adev, false); 5205 mutex_lock(&adev->srbm_mutex); 5206 for (i = 0; i < adev->gfx.me.num_me; i++) { 5207 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5208 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5209 soc24_grbm_select(adev, i, j, k, 0); 5210 5211 for (reg = 0; reg < reg_count; reg++) { 5212 adev->gfx.ip_dump_gfx_queues[index + reg] = 5213 RREG32(SOC15_REG_ENTRY_OFFSET( 5214 gc_gfx_queue_reg_list_12[reg])); 5215 } 5216 index += reg_count; 5217 } 5218 } 5219 } 5220 soc24_grbm_select(adev, 0, 0, 0, 0); 5221 mutex_unlock(&adev->srbm_mutex); 5222 amdgpu_gfx_off_ctrl(adev, true); 5223 } 5224 5225 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5226 { 5227 /* Disable the pipe reset until the CPFW fully support it.*/ 5228 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5229 return false; 5230 } 5231 5232 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5233 { 5234 struct amdgpu_device *adev = ring->adev; 5235 uint32_t reset_pipe = 0, clean_pipe = 0; 5236 int r; 5237 5238 if (!gfx_v12_pipe_reset_support(adev)) 5239 return -EOPNOTSUPP; 5240 5241 gfx_v12_0_set_safe_mode(adev, 0); 5242 mutex_lock(&adev->srbm_mutex); 5243 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5244 5245 switch (ring->pipe) { 5246 case 0: 5247 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5248 PFP_PIPE0_RESET, 1); 5249 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5250 ME_PIPE0_RESET, 1); 5251 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5252 PFP_PIPE0_RESET, 0); 5253 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5254 ME_PIPE0_RESET, 0); 5255 break; 5256 case 1: 5257 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5258 PFP_PIPE1_RESET, 1); 5259 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5260 ME_PIPE1_RESET, 1); 5261 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5262 PFP_PIPE1_RESET, 0); 5263 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5264 ME_PIPE1_RESET, 0); 5265 break; 5266 default: 5267 break; 5268 } 5269 5270 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5271 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5272 5273 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5274 RS64_FW_UC_START_ADDR_LO; 5275 soc24_grbm_select(adev, 0, 0, 0, 0); 5276 mutex_unlock(&adev->srbm_mutex); 5277 gfx_v12_0_unset_safe_mode(adev, 0); 5278 5279 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5280 r == 0 ? "successfully" : "failed"); 5281 /* Sometimes the ME start pc counter can't cache correctly, so the 5282 * PC check only as a reference and pipe reset result rely on the 5283 * later ring test. 5284 */ 5285 return 0; 5286 } 5287 5288 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5289 { 5290 struct amdgpu_device *adev = ring->adev; 5291 int r; 5292 5293 if (amdgpu_sriov_vf(adev)) 5294 return -EINVAL; 5295 5296 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5297 if (r) { 5298 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5299 r = gfx_v12_reset_gfx_pipe(ring); 5300 if (r) 5301 return r; 5302 } 5303 5304 r = gfx_v12_0_kgq_init_queue(ring, true); 5305 if (r) { 5306 dev_err(adev->dev, "failed to init kgq\n"); 5307 return r; 5308 } 5309 5310 r = amdgpu_mes_map_legacy_queue(adev, ring); 5311 if (r) { 5312 dev_err(adev->dev, "failed to remap kgq\n"); 5313 return r; 5314 } 5315 5316 return amdgpu_ring_test_ring(ring); 5317 } 5318 5319 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5320 { 5321 struct amdgpu_device *adev = ring->adev; 5322 uint32_t reset_pipe = 0, clean_pipe = 0; 5323 int r = 0; 5324 5325 if (!gfx_v12_pipe_reset_support(adev)) 5326 return -EOPNOTSUPP; 5327 5328 gfx_v12_0_set_safe_mode(adev, 0); 5329 mutex_lock(&adev->srbm_mutex); 5330 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5331 5332 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5333 clean_pipe = reset_pipe; 5334 5335 if (adev->gfx.rs64_enable) { 5336 switch (ring->pipe) { 5337 case 0: 5338 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5339 MEC_PIPE0_RESET, 1); 5340 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5341 MEC_PIPE0_RESET, 0); 5342 break; 5343 case 1: 5344 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5345 MEC_PIPE1_RESET, 1); 5346 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5347 MEC_PIPE1_RESET, 0); 5348 break; 5349 case 2: 5350 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5351 MEC_PIPE2_RESET, 1); 5352 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5353 MEC_PIPE2_RESET, 0); 5354 break; 5355 case 3: 5356 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5357 MEC_PIPE3_RESET, 1); 5358 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5359 MEC_PIPE3_RESET, 0); 5360 break; 5361 default: 5362 break; 5363 } 5364 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5365 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5366 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5367 RS64_FW_UC_START_ADDR_LO; 5368 } else { 5369 switch (ring->pipe) { 5370 case 0: 5371 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5372 MEC_ME1_PIPE0_RESET, 1); 5373 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5374 MEC_ME1_PIPE0_RESET, 0); 5375 break; 5376 case 1: 5377 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5378 MEC_ME1_PIPE1_RESET, 1); 5379 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5380 MEC_ME1_PIPE1_RESET, 0); 5381 break; 5382 default: 5383 break; 5384 } 5385 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5386 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5387 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5388 * the driver won't run into the F32 mode. 5389 */ 5390 } 5391 5392 soc24_grbm_select(adev, 0, 0, 0, 0); 5393 mutex_unlock(&adev->srbm_mutex); 5394 gfx_v12_0_unset_safe_mode(adev, 0); 5395 5396 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5397 r == 0 ? "successfully" : "failed"); 5398 /* Need the ring test to verify the pipe reset result.*/ 5399 return 0; 5400 } 5401 5402 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5403 { 5404 struct amdgpu_device *adev = ring->adev; 5405 int r; 5406 5407 if (amdgpu_sriov_vf(adev)) 5408 return -EINVAL; 5409 5410 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5411 if (r) { 5412 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5413 r = gfx_v12_0_reset_compute_pipe(ring); 5414 if (r) 5415 return r; 5416 } 5417 5418 r = gfx_v12_0_kcq_init_queue(ring, true); 5419 if (r) { 5420 dev_err(adev->dev, "failed to init kcq\n"); 5421 return r; 5422 } 5423 r = amdgpu_mes_map_legacy_queue(adev, ring); 5424 if (r) { 5425 dev_err(adev->dev, "failed to remap kcq\n"); 5426 return r; 5427 } 5428 5429 return amdgpu_ring_test_ring(ring); 5430 } 5431 5432 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5433 { 5434 amdgpu_gfx_profile_ring_begin_use(ring); 5435 5436 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5437 } 5438 5439 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5440 { 5441 amdgpu_gfx_profile_ring_end_use(ring); 5442 5443 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5444 } 5445 5446 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5447 .name = "gfx_v12_0", 5448 .early_init = gfx_v12_0_early_init, 5449 .late_init = gfx_v12_0_late_init, 5450 .sw_init = gfx_v12_0_sw_init, 5451 .sw_fini = gfx_v12_0_sw_fini, 5452 .hw_init = gfx_v12_0_hw_init, 5453 .hw_fini = gfx_v12_0_hw_fini, 5454 .suspend = gfx_v12_0_suspend, 5455 .resume = gfx_v12_0_resume, 5456 .is_idle = gfx_v12_0_is_idle, 5457 .wait_for_idle = gfx_v12_0_wait_for_idle, 5458 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5459 .set_powergating_state = gfx_v12_0_set_powergating_state, 5460 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5461 .dump_ip_state = gfx_v12_ip_dump, 5462 .print_ip_state = gfx_v12_ip_print, 5463 }; 5464 5465 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5466 .type = AMDGPU_RING_TYPE_GFX, 5467 .align_mask = 0xff, 5468 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5469 .support_64bit_ptrs = true, 5470 .secure_submission_supported = true, 5471 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5472 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5473 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5474 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5475 5 + /* COND_EXEC */ 5476 7 + /* PIPELINE_SYNC */ 5477 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5478 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5479 2 + /* VM_FLUSH */ 5480 8 + /* FENCE for VM_FLUSH */ 5481 5 + /* COND_EXEC */ 5482 7 + /* HDP_flush */ 5483 4 + /* VGT_flush */ 5484 31 + /* DE_META */ 5485 3 + /* CNTX_CTRL */ 5486 5 + /* HDP_INVL */ 5487 8 + 8 + /* FENCE x2 */ 5488 8 + /* gfx_v12_0_emit_mem_sync */ 5489 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5490 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5491 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5492 .emit_fence = gfx_v12_0_ring_emit_fence, 5493 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5494 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5495 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5496 .test_ring = gfx_v12_0_ring_test_ring, 5497 .test_ib = gfx_v12_0_ring_test_ib, 5498 .insert_nop = gfx_v12_ring_insert_nop, 5499 .pad_ib = amdgpu_ring_generic_pad_ib, 5500 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5501 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5502 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5503 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5504 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5505 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5506 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5507 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5508 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5509 .reset = gfx_v12_0_reset_kgq, 5510 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5511 .begin_use = gfx_v12_0_ring_begin_use, 5512 .end_use = gfx_v12_0_ring_end_use, 5513 }; 5514 5515 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5516 .type = AMDGPU_RING_TYPE_COMPUTE, 5517 .align_mask = 0xff, 5518 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5519 .support_64bit_ptrs = true, 5520 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5521 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5522 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5523 .emit_frame_size = 5524 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5525 5 + /* hdp invalidate */ 5526 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5527 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5528 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5529 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5530 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5531 8 + /* gfx_v12_0_emit_mem_sync */ 5532 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5533 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5534 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5535 .emit_fence = gfx_v12_0_ring_emit_fence, 5536 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5537 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5538 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5539 .test_ring = gfx_v12_0_ring_test_ring, 5540 .test_ib = gfx_v12_0_ring_test_ib, 5541 .insert_nop = gfx_v12_ring_insert_nop, 5542 .pad_ib = amdgpu_ring_generic_pad_ib, 5543 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5544 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5545 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5546 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5547 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5548 .reset = gfx_v12_0_reset_kcq, 5549 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5550 .begin_use = gfx_v12_0_ring_begin_use, 5551 .end_use = gfx_v12_0_ring_end_use, 5552 }; 5553 5554 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5555 .type = AMDGPU_RING_TYPE_KIQ, 5556 .align_mask = 0xff, 5557 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5558 .support_64bit_ptrs = true, 5559 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5560 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5561 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5562 .emit_frame_size = 5563 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5564 5 + /*hdp invalidate */ 5565 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5566 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5567 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5568 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5569 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5570 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5571 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5572 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5573 .test_ring = gfx_v12_0_ring_test_ring, 5574 .test_ib = gfx_v12_0_ring_test_ib, 5575 .insert_nop = amdgpu_ring_insert_nop, 5576 .pad_ib = amdgpu_ring_generic_pad_ib, 5577 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5578 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5579 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5580 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5581 }; 5582 5583 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5584 { 5585 int i; 5586 5587 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5588 5589 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5590 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5591 5592 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5593 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5594 } 5595 5596 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5597 .set = gfx_v12_0_set_eop_interrupt_state, 5598 .process = gfx_v12_0_eop_irq, 5599 }; 5600 5601 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5602 .set = gfx_v12_0_set_priv_reg_fault_state, 5603 .process = gfx_v12_0_priv_reg_irq, 5604 }; 5605 5606 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5607 .set = gfx_v12_0_set_bad_op_fault_state, 5608 .process = gfx_v12_0_bad_op_irq, 5609 }; 5610 5611 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5612 .set = gfx_v12_0_set_priv_inst_fault_state, 5613 .process = gfx_v12_0_priv_inst_irq, 5614 }; 5615 5616 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5617 { 5618 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5619 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5620 5621 adev->gfx.priv_reg_irq.num_types = 1; 5622 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5623 5624 adev->gfx.bad_op_irq.num_types = 1; 5625 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5626 5627 adev->gfx.priv_inst_irq.num_types = 1; 5628 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5629 } 5630 5631 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5632 { 5633 if (adev->flags & AMD_IS_APU) 5634 adev->gfx.imu.mode = MISSION_MODE; 5635 else 5636 adev->gfx.imu.mode = DEBUG_MODE; 5637 5638 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5639 } 5640 5641 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5642 { 5643 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5644 } 5645 5646 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5647 { 5648 /* set gfx eng mqd */ 5649 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5650 sizeof(struct v12_gfx_mqd); 5651 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5652 gfx_v12_0_gfx_mqd_init; 5653 /* set compute eng mqd */ 5654 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5655 sizeof(struct v12_compute_mqd); 5656 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5657 gfx_v12_0_compute_mqd_init; 5658 } 5659 5660 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5661 u32 bitmap) 5662 { 5663 u32 data; 5664 5665 if (!bitmap) 5666 return; 5667 5668 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5669 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5670 5671 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5672 } 5673 5674 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5675 { 5676 u32 data, wgp_bitmask; 5677 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5678 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5679 5680 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5681 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5682 5683 wgp_bitmask = 5684 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5685 5686 return (~data) & wgp_bitmask; 5687 } 5688 5689 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5690 { 5691 u32 wgp_idx, wgp_active_bitmap; 5692 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5693 5694 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5695 cu_active_bitmap = 0; 5696 5697 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5698 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5699 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5700 if (wgp_active_bitmap & (1 << wgp_idx)) 5701 cu_active_bitmap |= cu_bitmap_per_wgp; 5702 } 5703 5704 return cu_active_bitmap; 5705 } 5706 5707 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5708 struct amdgpu_cu_info *cu_info) 5709 { 5710 int i, j, k, counter, active_cu_number = 0; 5711 u32 mask, bitmap; 5712 unsigned disable_masks[8 * 2]; 5713 5714 if (!adev || !cu_info) 5715 return -EINVAL; 5716 5717 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5718 5719 mutex_lock(&adev->grbm_idx_mutex); 5720 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5721 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5722 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5723 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5724 continue; 5725 mask = 1; 5726 counter = 0; 5727 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5728 if (i < 8 && j < 2) 5729 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5730 adev, disable_masks[i * 2 + j]); 5731 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5732 5733 /** 5734 * GFX12 could support more than 4 SEs, while the bitmap 5735 * in cu_info struct is 4x4 and ioctl interface struct 5736 * drm_amdgpu_info_device should keep stable. 5737 * So we use last two columns of bitmap to store cu mask for 5738 * SEs 4 to 7, the layout of the bitmap is as below: 5739 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5740 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5741 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5742 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5743 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5744 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5745 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5746 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5747 */ 5748 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5749 5750 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5751 if (bitmap & mask) 5752 counter++; 5753 5754 mask <<= 1; 5755 } 5756 active_cu_number += counter; 5757 } 5758 } 5759 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5760 mutex_unlock(&adev->grbm_idx_mutex); 5761 5762 cu_info->number = active_cu_number; 5763 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5764 5765 return 0; 5766 } 5767 5768 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5769 .type = AMD_IP_BLOCK_TYPE_GFX, 5770 .major = 12, 5771 .minor = 0, 5772 .rev = 0, 5773 .funcs = &gfx_v12_0_ip_funcs, 5774 }; 5775