1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_0.h" 47 #include "nbif_v6_3_1.h" 48 #include "mes_v12_0.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 65 66 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 97 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 101 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 102 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 104 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 105 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 109 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 120 121 /* cp header registers */ 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 126 /* SE status registers */ 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 128 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 130 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 131 }; 132 133 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 134 /* compute registers */ 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 174 }; 175 176 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 177 /* gfx queue registers */ 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 203 }; 204 205 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 206 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 209 }; 210 211 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 212 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 213 }; 214 215 #define DEFAULT_SH_MEM_CONFIG \ 216 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 217 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 218 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 219 220 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 221 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 222 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 223 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 224 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 225 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 226 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 227 struct amdgpu_cu_info *cu_info); 228 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 229 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 230 u32 sh_num, u32 instance, int xcc_id); 231 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 232 233 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 234 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 235 uint32_t val); 236 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 237 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 238 uint16_t pasid, uint32_t flush_type, 239 bool all_hub, uint8_t dst_sel); 240 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 241 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 242 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 243 bool enable); 244 245 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 246 uint64_t queue_mask) 247 { 248 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 249 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 250 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 251 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 252 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 253 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 254 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 255 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 256 amdgpu_ring_write(kiq_ring, 0); 257 } 258 259 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 260 struct amdgpu_ring *ring) 261 { 262 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 263 uint64_t wptr_addr = ring->wptr_gpu_addr; 264 uint32_t me = 0, eng_sel = 0; 265 266 switch (ring->funcs->type) { 267 case AMDGPU_RING_TYPE_COMPUTE: 268 me = 1; 269 eng_sel = 0; 270 break; 271 case AMDGPU_RING_TYPE_GFX: 272 me = 0; 273 eng_sel = 4; 274 break; 275 case AMDGPU_RING_TYPE_MES: 276 me = 2; 277 eng_sel = 5; 278 break; 279 default: 280 WARN_ON(1); 281 } 282 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 284 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 285 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 286 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 287 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 288 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 289 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 290 PACKET3_MAP_QUEUES_ME((me)) | 291 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 292 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 293 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 294 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 295 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 296 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 297 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 298 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 299 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 300 } 301 302 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 303 struct amdgpu_ring *ring, 304 enum amdgpu_unmap_queues_action action, 305 u64 gpu_addr, u64 seq) 306 { 307 struct amdgpu_device *adev = kiq_ring->adev; 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 311 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 312 return; 313 } 314 315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 316 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 317 PACKET3_UNMAP_QUEUES_ACTION(action) | 318 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 319 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 320 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 321 amdgpu_ring_write(kiq_ring, 322 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 323 324 if (action == PREEMPT_QUEUES_NO_UNMAP) { 325 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 326 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 327 amdgpu_ring_write(kiq_ring, seq); 328 } else { 329 amdgpu_ring_write(kiq_ring, 0); 330 amdgpu_ring_write(kiq_ring, 0); 331 amdgpu_ring_write(kiq_ring, 0); 332 } 333 } 334 335 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 336 struct amdgpu_ring *ring, 337 u64 addr, u64 seq) 338 { 339 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 340 341 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 342 amdgpu_ring_write(kiq_ring, 343 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 344 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 345 PACKET3_QUERY_STATUS_COMMAND(2)); 346 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 347 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 348 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 349 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 350 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 351 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 352 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 353 } 354 355 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 356 uint16_t pasid, 357 uint32_t flush_type, 358 bool all_hub) 359 { 360 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 361 } 362 363 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 364 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 365 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 366 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 367 .kiq_query_status = gfx_v12_0_kiq_query_status, 368 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 369 .set_resources_size = 8, 370 .map_queues_size = 7, 371 .unmap_queues_size = 6, 372 .query_status_size = 7, 373 .invalidate_tlbs_size = 2, 374 }; 375 376 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 377 { 378 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 379 } 380 381 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 382 int mem_space, int opt, uint32_t addr0, 383 uint32_t addr1, uint32_t ref, 384 uint32_t mask, uint32_t inv) 385 { 386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 387 amdgpu_ring_write(ring, 388 /* memory (1) or register (0) */ 389 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 390 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 391 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 392 WAIT_REG_MEM_ENGINE(eng_sel))); 393 394 if (mem_space) 395 BUG_ON(addr0 & 0x3); /* Dword align */ 396 amdgpu_ring_write(ring, addr0); 397 amdgpu_ring_write(ring, addr1); 398 amdgpu_ring_write(ring, ref); 399 amdgpu_ring_write(ring, mask); 400 amdgpu_ring_write(ring, inv); /* poll interval */ 401 } 402 403 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 407 uint32_t tmp = 0; 408 unsigned i; 409 int r; 410 411 WREG32(scratch, 0xCAFEDEAD); 412 r = amdgpu_ring_alloc(ring, 5); 413 if (r) { 414 dev_err(adev->dev, 415 "amdgpu: cp failed to lock ring %d (%d).\n", 416 ring->idx, r); 417 return r; 418 } 419 420 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 421 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 422 } else { 423 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 424 amdgpu_ring_write(ring, scratch - 425 PACKET3_SET_UCONFIG_REG_START); 426 amdgpu_ring_write(ring, 0xDEADBEEF); 427 } 428 amdgpu_ring_commit(ring); 429 430 for (i = 0; i < adev->usec_timeout; i++) { 431 tmp = RREG32(scratch); 432 if (tmp == 0xDEADBEEF) 433 break; 434 if (amdgpu_emu_mode == 1) 435 msleep(1); 436 else 437 udelay(1); 438 } 439 440 if (i >= adev->usec_timeout) 441 r = -ETIMEDOUT; 442 return r; 443 } 444 445 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 struct amdgpu_ib ib; 449 struct dma_fence *f = NULL; 450 unsigned index; 451 uint64_t gpu_addr; 452 volatile uint32_t *cpu_ptr; 453 long r; 454 455 /* MES KIQ fw hasn't indirect buffer support for now */ 456 if (adev->enable_mes_kiq && 457 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 458 return 0; 459 460 memset(&ib, 0, sizeof(ib)); 461 462 if (ring->is_mes_queue) { 463 uint32_t padding, offset; 464 465 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 466 padding = amdgpu_mes_ctx_get_offs(ring, 467 AMDGPU_MES_CTX_PADDING_OFFS); 468 469 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 470 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 471 472 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 473 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 474 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 475 } else { 476 r = amdgpu_device_wb_get(adev, &index); 477 if (r) 478 return r; 479 480 gpu_addr = adev->wb.gpu_addr + (index * 4); 481 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 482 cpu_ptr = &adev->wb.wb[index]; 483 484 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 485 if (r) { 486 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 487 goto err1; 488 } 489 } 490 491 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 493 ib.ptr[2] = lower_32_bits(gpu_addr); 494 ib.ptr[3] = upper_32_bits(gpu_addr); 495 ib.ptr[4] = 0xDEADBEEF; 496 ib.length_dw = 5; 497 498 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 499 if (r) 500 goto err2; 501 502 r = dma_fence_wait_timeout(f, false, timeout); 503 if (r == 0) { 504 r = -ETIMEDOUT; 505 goto err2; 506 } else if (r < 0) { 507 goto err2; 508 } 509 510 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 511 r = 0; 512 else 513 r = -EINVAL; 514 err2: 515 if (!ring->is_mes_queue) 516 amdgpu_ib_free(adev, &ib, NULL); 517 dma_fence_put(f); 518 err1: 519 if (!ring->is_mes_queue) 520 amdgpu_device_wb_free(adev, index); 521 return r; 522 } 523 524 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 525 { 526 amdgpu_ucode_release(&adev->gfx.pfp_fw); 527 amdgpu_ucode_release(&adev->gfx.me_fw); 528 amdgpu_ucode_release(&adev->gfx.rlc_fw); 529 amdgpu_ucode_release(&adev->gfx.mec_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 535 { 536 const struct psp_firmware_header_v1_0 *toc_hdr; 537 int err = 0; 538 539 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 540 "amdgpu/%s_toc.bin", ucode_prefix); 541 if (err) 542 goto out; 543 544 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 545 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 546 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 547 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 548 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 549 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 550 return 0; 551 out: 552 amdgpu_ucode_release(&adev->psp.toc_fw); 553 return err; 554 } 555 556 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 557 { 558 char ucode_prefix[15]; 559 int err; 560 const struct rlc_firmware_header_v2_0 *rlc_hdr; 561 uint16_t version_major; 562 uint16_t version_minor; 563 564 DRM_DEBUG("\n"); 565 566 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 567 568 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 569 "amdgpu/%s_pfp.bin", ucode_prefix); 570 if (err) 571 goto out; 572 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 573 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 574 575 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 576 "amdgpu/%s_me.bin", ucode_prefix); 577 if (err) 578 goto out; 579 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 581 582 if (!amdgpu_sriov_vf(adev)) { 583 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 584 "amdgpu/%s_rlc.bin", ucode_prefix); 585 if (err) 586 goto out; 587 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 588 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 589 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 590 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 591 if (err) 592 goto out; 593 } 594 595 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 596 "amdgpu/%s_mec.bin", ucode_prefix); 597 if (err) 598 goto out; 599 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 600 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 601 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 602 603 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 604 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 605 606 /* only one MEC for gfx 12 */ 607 adev->gfx.mec2_fw = NULL; 608 609 if (adev->gfx.imu.funcs) { 610 if (adev->gfx.imu.funcs->init_microcode) { 611 err = adev->gfx.imu.funcs->init_microcode(adev); 612 if (err) 613 dev_err(adev->dev, "Failed to load imu firmware!\n"); 614 } 615 } 616 617 out: 618 if (err) { 619 amdgpu_ucode_release(&adev->gfx.pfp_fw); 620 amdgpu_ucode_release(&adev->gfx.me_fw); 621 amdgpu_ucode_release(&adev->gfx.rlc_fw); 622 amdgpu_ucode_release(&adev->gfx.mec_fw); 623 } 624 625 return err; 626 } 627 628 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 629 { 630 u32 count = 0; 631 const struct cs_section_def *sect = NULL; 632 const struct cs_extent_def *ext = NULL; 633 634 count += 1; 635 636 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 637 if (sect->id == SECT_CONTEXT) { 638 for (ext = sect->section; ext->extent != NULL; ++ext) 639 count += 2 + ext->reg_count; 640 } else 641 return 0; 642 } 643 644 return count; 645 } 646 647 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 648 volatile u32 *buffer) 649 { 650 u32 count = 0, clustercount = 0, i; 651 const struct cs_section_def *sect = NULL; 652 const struct cs_extent_def *ext = NULL; 653 654 if (adev->gfx.rlc.cs_data == NULL) 655 return; 656 if (buffer == NULL) 657 return; 658 659 count += 1; 660 661 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 662 if (sect->id == SECT_CONTEXT) { 663 for (ext = sect->section; ext->extent != NULL; ++ext) { 664 clustercount++; 665 buffer[count++] = ext->reg_count; 666 buffer[count++] = ext->reg_index; 667 668 for (i = 0; i < ext->reg_count; i++) 669 buffer[count++] = cpu_to_le32(ext->extent[i]); 670 } 671 } else 672 return; 673 } 674 675 buffer[0] = clustercount; 676 } 677 678 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 679 { 680 /* clear state block */ 681 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 682 &adev->gfx.rlc.clear_state_gpu_addr, 683 (void **)&adev->gfx.rlc.cs_ptr); 684 685 /* jump table block */ 686 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 687 &adev->gfx.rlc.cp_table_gpu_addr, 688 (void **)&adev->gfx.rlc.cp_table_ptr); 689 } 690 691 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 692 { 693 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 694 695 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 696 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 697 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 698 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 699 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 700 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 701 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 702 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 703 adev->gfx.rlc.rlcg_reg_access_supported = true; 704 } 705 706 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 707 { 708 const struct cs_section_def *cs_data; 709 int r; 710 711 adev->gfx.rlc.cs_data = gfx12_cs_data; 712 713 cs_data = adev->gfx.rlc.cs_data; 714 715 if (cs_data) { 716 /* init clear state block */ 717 r = amdgpu_gfx_rlc_init_csb(adev); 718 if (r) 719 return r; 720 } 721 722 /* init spm vmid with 0xf */ 723 if (adev->gfx.rlc.funcs->update_spm_vmid) 724 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 725 726 return 0; 727 } 728 729 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 730 { 731 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 732 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 733 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 734 } 735 736 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 737 { 738 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 739 740 amdgpu_gfx_graphics_queue_acquire(adev); 741 } 742 743 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 744 { 745 int r; 746 u32 *hpd; 747 size_t mec_hpd_size; 748 749 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 750 751 /* take ownership of the relevant compute queues */ 752 amdgpu_gfx_compute_queue_acquire(adev); 753 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 754 755 if (mec_hpd_size) { 756 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 757 AMDGPU_GEM_DOMAIN_GTT, 758 &adev->gfx.mec.hpd_eop_obj, 759 &adev->gfx.mec.hpd_eop_gpu_addr, 760 (void **)&hpd); 761 if (r) { 762 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 763 gfx_v12_0_mec_fini(adev); 764 return r; 765 } 766 767 memset(hpd, 0, mec_hpd_size); 768 769 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 770 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 771 } 772 773 return 0; 774 } 775 776 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 777 { 778 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 779 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 780 (address << SQ_IND_INDEX__INDEX__SHIFT)); 781 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 782 } 783 784 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 785 uint32_t thread, uint32_t regno, 786 uint32_t num, uint32_t *out) 787 { 788 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 789 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 790 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 791 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 792 (SQ_IND_INDEX__AUTO_INCR_MASK)); 793 while (num--) 794 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 795 } 796 797 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 798 uint32_t xcc_id, 799 uint32_t simd, uint32_t wave, 800 uint32_t *dst, int *no_fields) 801 { 802 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 803 * field when performing a select_se_sh so it should be 804 * zero here */ 805 WARN_ON(simd != 0); 806 807 /* type 4 wave data */ 808 dst[(*no_fields)++] = 4; 809 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 810 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 811 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 812 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 832 } 833 834 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 835 uint32_t xcc_id, uint32_t simd, 836 uint32_t wave, uint32_t start, 837 uint32_t size, uint32_t *dst) 838 { 839 WARN_ON(simd != 0); 840 841 wave_read_regs( 842 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 843 dst); 844 } 845 846 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 847 uint32_t xcc_id, uint32_t simd, 848 uint32_t wave, uint32_t thread, 849 uint32_t start, uint32_t size, 850 uint32_t *dst) 851 { 852 wave_read_regs( 853 adev, wave, thread, 854 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 855 } 856 857 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 858 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 859 { 860 soc24_grbm_select(adev, me, pipe, q, vm); 861 } 862 863 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 864 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 865 .select_se_sh = &gfx_v12_0_select_se_sh, 866 .read_wave_data = &gfx_v12_0_read_wave_data, 867 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 868 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 869 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 870 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 871 }; 872 873 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 874 { 875 876 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 877 case IP_VERSION(12, 0, 0): 878 case IP_VERSION(12, 0, 1): 879 adev->gfx.config.max_hw_contexts = 8; 880 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 881 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 882 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 883 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 884 break; 885 default: 886 BUG(); 887 break; 888 } 889 890 return 0; 891 } 892 893 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 894 int me, int pipe, int queue) 895 { 896 int r; 897 struct amdgpu_ring *ring; 898 unsigned int irq_type; 899 900 ring = &adev->gfx.gfx_ring[ring_id]; 901 902 ring->me = me; 903 ring->pipe = pipe; 904 ring->queue = queue; 905 906 ring->ring_obj = NULL; 907 ring->use_doorbell = true; 908 909 if (!ring_id) 910 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 911 else 912 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 913 ring->vm_hub = AMDGPU_GFXHUB(0); 914 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 915 916 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 917 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 918 AMDGPU_RING_PRIO_DEFAULT, NULL); 919 if (r) 920 return r; 921 return 0; 922 } 923 924 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 925 int mec, int pipe, int queue) 926 { 927 int r; 928 unsigned irq_type; 929 struct amdgpu_ring *ring; 930 unsigned int hw_prio; 931 932 ring = &adev->gfx.compute_ring[ring_id]; 933 934 /* mec0 is me1 */ 935 ring->me = mec + 1; 936 ring->pipe = pipe; 937 ring->queue = queue; 938 939 ring->ring_obj = NULL; 940 ring->use_doorbell = true; 941 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 942 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 943 + (ring_id * GFX12_MEC_HPD_SIZE); 944 ring->vm_hub = AMDGPU_GFXHUB(0); 945 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 946 947 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 948 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 949 + ring->pipe; 950 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 951 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 952 /* type-2 packets are deprecated on MEC, use type-3 instead */ 953 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 954 hw_prio, NULL); 955 if (r) 956 return r; 957 958 return 0; 959 } 960 961 static struct { 962 SOC24_FIRMWARE_ID id; 963 unsigned int offset; 964 unsigned int size; 965 unsigned int size_x16; 966 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 967 968 #define RLC_TOC_OFFSET_DWUNIT 8 969 #define RLC_SIZE_MULTIPLE 1024 970 #define RLC_TOC_UMF_SIZE_inM 23ULL 971 #define RLC_TOC_FORMAT_API 165ULL 972 973 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 974 { 975 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 976 977 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 978 rlc_autoload_info[ucode->id].id = ucode->id; 979 rlc_autoload_info[ucode->id].offset = 980 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 981 rlc_autoload_info[ucode->id].size = 982 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 983 ucode->size * 4; 984 ucode++; 985 } 986 } 987 988 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 989 { 990 uint32_t total_size = 0; 991 SOC24_FIRMWARE_ID id; 992 993 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 994 995 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 996 total_size += rlc_autoload_info[id].size; 997 998 /* In case the offset in rlc toc ucode is aligned */ 999 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1000 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1001 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1002 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1003 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1004 1005 return total_size; 1006 } 1007 1008 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1009 { 1010 int r; 1011 uint32_t total_size; 1012 1013 total_size = gfx_v12_0_calc_toc_total_size(adev); 1014 1015 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1016 AMDGPU_GEM_DOMAIN_VRAM, 1017 &adev->gfx.rlc.rlc_autoload_bo, 1018 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1019 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1020 1021 if (r) { 1022 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1023 return r; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1030 SOC24_FIRMWARE_ID id, 1031 const void *fw_data, 1032 uint32_t fw_size) 1033 { 1034 uint32_t toc_offset; 1035 uint32_t toc_fw_size; 1036 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1037 1038 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1039 return; 1040 1041 toc_offset = rlc_autoload_info[id].offset; 1042 toc_fw_size = rlc_autoload_info[id].size; 1043 1044 if (fw_size == 0) 1045 fw_size = toc_fw_size; 1046 1047 if (fw_size > toc_fw_size) 1048 fw_size = toc_fw_size; 1049 1050 memcpy(ptr + toc_offset, fw_data, fw_size); 1051 1052 if (fw_size < toc_fw_size) 1053 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1054 } 1055 1056 static void 1057 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1058 { 1059 void *data; 1060 uint32_t size; 1061 uint32_t *toc_ptr; 1062 1063 data = adev->psp.toc.start_addr; 1064 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1065 1066 toc_ptr = (uint32_t *)data + size / 4 - 2; 1067 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1068 1069 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1070 data, size); 1071 } 1072 1073 static void 1074 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1075 { 1076 const __le32 *fw_data; 1077 uint32_t fw_size; 1078 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1079 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1080 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1081 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1082 uint16_t version_major, version_minor; 1083 1084 /* pfp ucode */ 1085 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1086 adev->gfx.pfp_fw->data; 1087 /* instruction */ 1088 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1089 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1090 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1091 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1092 fw_data, fw_size); 1093 /* data */ 1094 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1095 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1096 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1097 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1098 fw_data, fw_size); 1099 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1100 fw_data, fw_size); 1101 /* me ucode */ 1102 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1103 adev->gfx.me_fw->data; 1104 /* instruction */ 1105 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1106 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1107 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1108 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1109 fw_data, fw_size); 1110 /* data */ 1111 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1112 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1113 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1114 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1115 fw_data, fw_size); 1116 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1117 fw_data, fw_size); 1118 /* mec ucode */ 1119 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1120 adev->gfx.mec_fw->data; 1121 /* instruction */ 1122 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1123 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1124 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1125 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1126 fw_data, fw_size); 1127 /* data */ 1128 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1129 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1130 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1131 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1132 fw_data, fw_size); 1133 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1134 fw_data, fw_size); 1135 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1136 fw_data, fw_size); 1137 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1138 fw_data, fw_size); 1139 1140 /* rlc ucode */ 1141 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1142 adev->gfx.rlc_fw->data; 1143 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1144 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1145 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1146 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1147 fw_data, fw_size); 1148 1149 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1150 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1151 if (version_major == 2) { 1152 if (version_minor >= 1) { 1153 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1154 1155 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1156 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1157 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1158 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1159 fw_data, fw_size); 1160 1161 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1162 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1163 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1164 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1165 fw_data, fw_size); 1166 } 1167 if (version_minor >= 2) { 1168 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1169 1170 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1171 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1172 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1173 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1174 fw_data, fw_size); 1175 1176 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1177 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1178 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1179 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1180 fw_data, fw_size); 1181 } 1182 } 1183 } 1184 1185 static void 1186 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1187 { 1188 const __le32 *fw_data; 1189 uint32_t fw_size; 1190 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1191 1192 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1193 adev->sdma.instance[0].fw->data; 1194 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1195 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1196 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1197 1198 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1199 fw_data, fw_size); 1200 } 1201 1202 static void 1203 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1204 { 1205 const __le32 *fw_data; 1206 unsigned fw_size; 1207 const struct mes_firmware_header_v1_0 *mes_hdr; 1208 int pipe, ucode_id, data_id; 1209 1210 for (pipe = 0; pipe < 2; pipe++) { 1211 if (pipe == 0) { 1212 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1213 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1214 } else { 1215 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1216 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1217 } 1218 1219 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1220 adev->mes.fw[pipe]->data; 1221 1222 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1223 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1224 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1225 1226 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1227 1228 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1229 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1230 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1231 1232 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1233 } 1234 } 1235 1236 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1237 { 1238 uint32_t rlc_g_offset, rlc_g_size; 1239 uint64_t gpu_addr; 1240 uint32_t data; 1241 1242 /* RLC autoload sequence 2: copy ucode */ 1243 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1244 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1245 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1246 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1247 1248 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1249 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1250 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1251 1252 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1253 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1254 1255 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1256 1257 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1258 /* RLC autoload sequence 3: load IMU fw */ 1259 if (adev->gfx.imu.funcs->load_microcode) 1260 adev->gfx.imu.funcs->load_microcode(adev); 1261 /* RLC autoload sequence 4 init IMU fw */ 1262 if (adev->gfx.imu.funcs->setup_imu) 1263 adev->gfx.imu.funcs->setup_imu(adev); 1264 if (adev->gfx.imu.funcs->start_imu) 1265 adev->gfx.imu.funcs->start_imu(adev); 1266 1267 /* RLC autoload sequence 5 disable gpa mode */ 1268 gfx_v12_0_disable_gpa_mode(adev); 1269 } else { 1270 /* unhalt rlc to start autoload without imu */ 1271 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1272 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1273 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1274 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1275 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1276 } 1277 1278 return 0; 1279 } 1280 1281 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1282 { 1283 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1284 uint32_t *ptr; 1285 uint32_t inst; 1286 1287 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1288 if (!ptr) { 1289 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1290 adev->gfx.ip_dump_core = NULL; 1291 } else { 1292 adev->gfx.ip_dump_core = ptr; 1293 } 1294 1295 /* Allocate memory for compute queue registers for all the instances */ 1296 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1297 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1298 adev->gfx.mec.num_queue_per_pipe; 1299 1300 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1301 if (!ptr) { 1302 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1303 adev->gfx.ip_dump_compute_queues = NULL; 1304 } else { 1305 adev->gfx.ip_dump_compute_queues = ptr; 1306 } 1307 1308 /* Allocate memory for gfx queue registers for all the instances */ 1309 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1310 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1311 adev->gfx.me.num_queue_per_pipe; 1312 1313 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1314 if (!ptr) { 1315 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1316 adev->gfx.ip_dump_gfx_queues = NULL; 1317 } else { 1318 adev->gfx.ip_dump_gfx_queues = ptr; 1319 } 1320 } 1321 1322 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1323 { 1324 int i, j, k, r, ring_id = 0; 1325 unsigned num_compute_rings; 1326 int xcc_id = 0; 1327 struct amdgpu_device *adev = ip_block->adev; 1328 1329 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1330 case IP_VERSION(12, 0, 0): 1331 case IP_VERSION(12, 0, 1): 1332 adev->gfx.me.num_me = 1; 1333 adev->gfx.me.num_pipe_per_me = 1; 1334 adev->gfx.me.num_queue_per_pipe = 1; 1335 adev->gfx.mec.num_mec = 2; 1336 adev->gfx.mec.num_pipe_per_mec = 2; 1337 adev->gfx.mec.num_queue_per_pipe = 4; 1338 break; 1339 default: 1340 adev->gfx.me.num_me = 1; 1341 adev->gfx.me.num_pipe_per_me = 1; 1342 adev->gfx.me.num_queue_per_pipe = 1; 1343 adev->gfx.mec.num_mec = 1; 1344 adev->gfx.mec.num_pipe_per_mec = 4; 1345 adev->gfx.mec.num_queue_per_pipe = 8; 1346 break; 1347 } 1348 1349 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1350 default: 1351 adev->gfx.enable_cleaner_shader = false; 1352 break; 1353 } 1354 1355 /* recalculate compute rings to use based on hardware configuration */ 1356 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1357 adev->gfx.mec.num_queue_per_pipe) / 2; 1358 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1359 num_compute_rings); 1360 1361 /* EOP Event */ 1362 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1363 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1364 &adev->gfx.eop_irq); 1365 if (r) 1366 return r; 1367 1368 /* Bad opcode Event */ 1369 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1370 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1371 &adev->gfx.bad_op_irq); 1372 if (r) 1373 return r; 1374 1375 /* Privileged reg */ 1376 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1377 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1378 &adev->gfx.priv_reg_irq); 1379 if (r) 1380 return r; 1381 1382 /* Privileged inst */ 1383 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1384 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1385 &adev->gfx.priv_inst_irq); 1386 if (r) 1387 return r; 1388 1389 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1390 1391 gfx_v12_0_me_init(adev); 1392 1393 r = gfx_v12_0_rlc_init(adev); 1394 if (r) { 1395 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1396 return r; 1397 } 1398 1399 r = gfx_v12_0_mec_init(adev); 1400 if (r) { 1401 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1402 return r; 1403 } 1404 1405 /* set up the gfx ring */ 1406 for (i = 0; i < adev->gfx.me.num_me; i++) { 1407 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1408 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1409 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1410 continue; 1411 1412 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1413 i, k, j); 1414 if (r) 1415 return r; 1416 ring_id++; 1417 } 1418 } 1419 } 1420 1421 ring_id = 0; 1422 /* set up the compute queues - allocate horizontally across pipes */ 1423 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1424 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1425 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1426 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1427 0, i, k, j)) 1428 continue; 1429 1430 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1431 i, k, j); 1432 if (r) 1433 return r; 1434 1435 ring_id++; 1436 } 1437 } 1438 } 1439 1440 /* TODO: Add queue reset mask when FW fully supports it */ 1441 adev->gfx.gfx_supported_reset = 1442 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1443 adev->gfx.compute_supported_reset = 1444 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1445 1446 if (!adev->enable_mes_kiq) { 1447 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1448 if (r) { 1449 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1450 return r; 1451 } 1452 1453 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1454 if (r) 1455 return r; 1456 } 1457 1458 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1459 if (r) 1460 return r; 1461 1462 /* allocate visible FB for rlc auto-loading fw */ 1463 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1464 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1465 if (r) 1466 return r; 1467 } 1468 1469 r = gfx_v12_0_gpu_early_init(adev); 1470 if (r) 1471 return r; 1472 1473 gfx_v12_0_alloc_ip_dump(adev); 1474 1475 r = amdgpu_gfx_sysfs_init(adev); 1476 if (r) 1477 return r; 1478 1479 return 0; 1480 } 1481 1482 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1483 { 1484 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1485 &adev->gfx.pfp.pfp_fw_gpu_addr, 1486 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1487 1488 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1489 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1490 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1491 } 1492 1493 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1494 { 1495 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1496 &adev->gfx.me.me_fw_gpu_addr, 1497 (void **)&adev->gfx.me.me_fw_ptr); 1498 1499 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1500 &adev->gfx.me.me_fw_data_gpu_addr, 1501 (void **)&adev->gfx.me.me_fw_data_ptr); 1502 } 1503 1504 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1505 { 1506 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1507 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1508 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1509 } 1510 1511 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1512 { 1513 int i; 1514 struct amdgpu_device *adev = ip_block->adev; 1515 1516 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1517 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1518 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1519 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1520 1521 amdgpu_gfx_mqd_sw_fini(adev, 0); 1522 1523 if (!adev->enable_mes_kiq) { 1524 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1525 amdgpu_gfx_kiq_fini(adev, 0); 1526 } 1527 1528 gfx_v12_0_pfp_fini(adev); 1529 gfx_v12_0_me_fini(adev); 1530 gfx_v12_0_rlc_fini(adev); 1531 gfx_v12_0_mec_fini(adev); 1532 1533 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1534 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1535 1536 gfx_v12_0_free_microcode(adev); 1537 1538 amdgpu_gfx_sysfs_fini(adev); 1539 1540 kfree(adev->gfx.ip_dump_core); 1541 kfree(adev->gfx.ip_dump_compute_queues); 1542 kfree(adev->gfx.ip_dump_gfx_queues); 1543 1544 return 0; 1545 } 1546 1547 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1548 u32 sh_num, u32 instance, int xcc_id) 1549 { 1550 u32 data; 1551 1552 if (instance == 0xffffffff) 1553 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1554 INSTANCE_BROADCAST_WRITES, 1); 1555 else 1556 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1557 instance); 1558 1559 if (se_num == 0xffffffff) 1560 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1561 1); 1562 else 1563 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1564 1565 if (sh_num == 0xffffffff) 1566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1567 1); 1568 else 1569 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1570 1571 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1572 } 1573 1574 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1575 { 1576 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1577 1578 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1579 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1580 GRBM_CC_GC_SA_UNIT_DISABLE, 1581 SA_DISABLE); 1582 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1583 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1584 GRBM_GC_USER_SA_UNIT_DISABLE, 1585 SA_DISABLE); 1586 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1587 adev->gfx.config.max_shader_engines); 1588 1589 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1590 } 1591 1592 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1593 { 1594 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1595 u32 rb_mask; 1596 1597 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1598 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1599 CC_RB_BACKEND_DISABLE, 1600 BACKEND_DISABLE); 1601 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1602 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1603 GC_USER_RB_BACKEND_DISABLE, 1604 BACKEND_DISABLE); 1605 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1606 adev->gfx.config.max_shader_engines); 1607 1608 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1609 } 1610 1611 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1612 { 1613 u32 rb_bitmap_width_per_sa; 1614 u32 max_sa; 1615 u32 active_sa_bitmap; 1616 u32 global_active_rb_bitmap; 1617 u32 active_rb_bitmap = 0; 1618 u32 i; 1619 1620 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1621 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1622 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1623 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1624 1625 /* generate active rb bitmap according to active sa bitmap */ 1626 max_sa = adev->gfx.config.max_shader_engines * 1627 adev->gfx.config.max_sh_per_se; 1628 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1629 adev->gfx.config.max_sh_per_se; 1630 for (i = 0; i < max_sa; i++) { 1631 if (active_sa_bitmap & (1 << i)) 1632 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1633 } 1634 1635 active_rb_bitmap |= global_active_rb_bitmap; 1636 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1637 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1638 } 1639 1640 #define LDS_APP_BASE 0x1 1641 #define SCRATCH_APP_BASE 0x2 1642 1643 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1644 { 1645 int i; 1646 uint32_t sh_mem_bases; 1647 uint32_t data; 1648 1649 /* 1650 * Configure apertures: 1651 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1652 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1653 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1654 */ 1655 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1656 SCRATCH_APP_BASE; 1657 1658 mutex_lock(&adev->srbm_mutex); 1659 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1660 soc24_grbm_select(adev, 0, 0, 0, i); 1661 /* CP and shaders */ 1662 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1663 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1664 1665 /* Enable trap for each kfd vmid. */ 1666 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1667 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1668 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1669 } 1670 soc24_grbm_select(adev, 0, 0, 0, 0); 1671 mutex_unlock(&adev->srbm_mutex); 1672 } 1673 1674 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1675 { 1676 /* TODO: harvest feature to be added later. */ 1677 } 1678 1679 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1680 { 1681 } 1682 1683 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1684 { 1685 u32 tmp; 1686 int i; 1687 1688 if (!amdgpu_sriov_vf(adev)) 1689 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1690 1691 gfx_v12_0_setup_rb(adev); 1692 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1693 gfx_v12_0_get_tcc_info(adev); 1694 adev->gfx.config.pa_sc_tile_steering_override = 0; 1695 1696 /* XXX SH_MEM regs */ 1697 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1698 mutex_lock(&adev->srbm_mutex); 1699 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1700 soc24_grbm_select(adev, 0, 0, 0, i); 1701 /* CP and shaders */ 1702 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1703 if (i != 0) { 1704 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1705 (adev->gmc.private_aperture_start >> 48)); 1706 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1707 (adev->gmc.shared_aperture_start >> 48)); 1708 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1709 } 1710 } 1711 soc24_grbm_select(adev, 0, 0, 0, 0); 1712 1713 mutex_unlock(&adev->srbm_mutex); 1714 1715 gfx_v12_0_init_compute_vmid(adev); 1716 } 1717 1718 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1719 int me, int pipe) 1720 { 1721 if (me != 0) 1722 return 0; 1723 1724 switch (pipe) { 1725 case 0: 1726 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1727 default: 1728 return 0; 1729 } 1730 } 1731 1732 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1733 int me, int pipe) 1734 { 1735 /* 1736 * amdgpu controls only the first MEC. That's why this function only 1737 * handles the setting of interrupts for this specific MEC. All other 1738 * pipes' interrupts are set by amdkfd. 1739 */ 1740 if (me != 1) 1741 return 0; 1742 1743 switch (pipe) { 1744 case 0: 1745 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1746 case 1: 1747 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1748 default: 1749 return 0; 1750 } 1751 } 1752 1753 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1754 bool enable) 1755 { 1756 u32 tmp, cp_int_cntl_reg; 1757 int i, j; 1758 1759 if (amdgpu_sriov_vf(adev)) 1760 return; 1761 1762 for (i = 0; i < adev->gfx.me.num_me; i++) { 1763 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1764 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1765 1766 if (cp_int_cntl_reg) { 1767 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1768 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1769 enable ? 1 : 0); 1770 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1771 enable ? 1 : 0); 1772 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1773 enable ? 1 : 0); 1774 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1775 enable ? 1 : 0); 1776 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1777 } 1778 } 1779 } 1780 } 1781 1782 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1783 { 1784 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1785 1786 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1787 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1788 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1789 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1790 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1791 1792 return 0; 1793 } 1794 1795 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1796 { 1797 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1798 1799 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1800 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1801 } 1802 1803 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1804 { 1805 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1806 udelay(50); 1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1808 udelay(50); 1809 } 1810 1811 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1812 bool enable) 1813 { 1814 uint32_t rlc_pg_cntl; 1815 1816 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1817 1818 if (!enable) { 1819 /* RLC_PG_CNTL[23] = 0 (default) 1820 * RLC will wait for handshake acks with SMU 1821 * GFXOFF will be enabled 1822 * RLC_PG_CNTL[23] = 1 1823 * RLC will not issue any message to SMU 1824 * hence no handshake between SMU & RLC 1825 * GFXOFF will be disabled 1826 */ 1827 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1828 } else 1829 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1830 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1831 } 1832 1833 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1834 { 1835 /* TODO: enable rlc & smu handshake until smu 1836 * and gfxoff feature works as expected */ 1837 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1838 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1839 1840 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1841 udelay(50); 1842 } 1843 1844 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1845 { 1846 uint32_t tmp; 1847 1848 /* enable Save Restore Machine */ 1849 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1850 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1851 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1852 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1853 } 1854 1855 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1856 { 1857 const struct rlc_firmware_header_v2_0 *hdr; 1858 const __le32 *fw_data; 1859 unsigned i, fw_size; 1860 1861 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1862 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1863 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1864 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1865 1866 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1867 RLCG_UCODE_LOADING_START_ADDRESS); 1868 1869 for (i = 0; i < fw_size; i++) 1870 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1871 le32_to_cpup(fw_data++)); 1872 1873 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1874 } 1875 1876 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1877 { 1878 const struct rlc_firmware_header_v2_2 *hdr; 1879 const __le32 *fw_data; 1880 unsigned i, fw_size; 1881 u32 tmp; 1882 1883 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1884 1885 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1886 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1887 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1888 1889 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1890 1891 for (i = 0; i < fw_size; i++) { 1892 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1893 msleep(1); 1894 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1895 le32_to_cpup(fw_data++)); 1896 } 1897 1898 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1899 1900 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1901 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1902 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1903 1904 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1905 for (i = 0; i < fw_size; i++) { 1906 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1907 msleep(1); 1908 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1909 le32_to_cpup(fw_data++)); 1910 } 1911 1912 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1913 1914 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1915 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1916 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1917 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1918 } 1919 1920 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1921 { 1922 const struct rlc_firmware_header_v2_0 *hdr; 1923 uint16_t version_major; 1924 uint16_t version_minor; 1925 1926 if (!adev->gfx.rlc_fw) 1927 return -EINVAL; 1928 1929 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1930 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1931 1932 version_major = le16_to_cpu(hdr->header.header_version_major); 1933 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1934 1935 if (version_major == 2) { 1936 gfx_v12_0_load_rlcg_microcode(adev); 1937 if (amdgpu_dpm == 1) { 1938 if (version_minor >= 2) 1939 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1940 } 1941 1942 return 0; 1943 } 1944 1945 return -EINVAL; 1946 } 1947 1948 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1949 { 1950 int r; 1951 1952 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1953 gfx_v12_0_init_csb(adev); 1954 1955 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1956 gfx_v12_0_rlc_enable_srm(adev); 1957 } else { 1958 if (amdgpu_sriov_vf(adev)) { 1959 gfx_v12_0_init_csb(adev); 1960 return 0; 1961 } 1962 1963 adev->gfx.rlc.funcs->stop(adev); 1964 1965 /* disable CG */ 1966 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1967 1968 /* disable PG */ 1969 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1970 1971 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1972 /* legacy rlc firmware loading */ 1973 r = gfx_v12_0_rlc_load_microcode(adev); 1974 if (r) 1975 return r; 1976 } 1977 1978 gfx_v12_0_init_csb(adev); 1979 1980 adev->gfx.rlc.funcs->start(adev); 1981 } 1982 1983 return 0; 1984 } 1985 1986 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 1987 { 1988 const struct gfx_firmware_header_v2_0 *pfp_hdr; 1989 const struct gfx_firmware_header_v2_0 *me_hdr; 1990 const struct gfx_firmware_header_v2_0 *mec_hdr; 1991 uint32_t pipe_id, tmp; 1992 1993 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1994 adev->gfx.mec_fw->data; 1995 me_hdr = (const struct gfx_firmware_header_v2_0 *) 1996 adev->gfx.me_fw->data; 1997 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 1998 adev->gfx.pfp_fw->data; 1999 2000 /* config pfp program start addr */ 2001 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2002 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2003 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2004 (pfp_hdr->ucode_start_addr_hi << 30) | 2005 (pfp_hdr->ucode_start_addr_lo >> 2)); 2006 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2007 pfp_hdr->ucode_start_addr_hi >> 2); 2008 } 2009 soc24_grbm_select(adev, 0, 0, 0, 0); 2010 2011 /* reset pfp pipe */ 2012 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2013 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2014 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2015 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2016 2017 /* clear pfp pipe reset */ 2018 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2019 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2020 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2021 2022 /* config me program start addr */ 2023 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2024 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2025 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2026 (me_hdr->ucode_start_addr_hi << 30) | 2027 (me_hdr->ucode_start_addr_lo >> 2)); 2028 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2029 me_hdr->ucode_start_addr_hi>>2); 2030 } 2031 soc24_grbm_select(adev, 0, 0, 0, 0); 2032 2033 /* reset me pipe */ 2034 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2035 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2036 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2037 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2038 2039 /* clear me pipe reset */ 2040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2041 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2042 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2043 2044 /* config mec program start addr */ 2045 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2046 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2047 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2048 mec_hdr->ucode_start_addr_lo >> 2 | 2049 mec_hdr->ucode_start_addr_hi << 30); 2050 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2051 mec_hdr->ucode_start_addr_hi >> 2); 2052 } 2053 soc24_grbm_select(adev, 0, 0, 0, 0); 2054 2055 /* reset mec pipe */ 2056 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2057 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2058 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2059 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2060 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2061 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2062 2063 /* clear mec pipe reset */ 2064 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2065 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2066 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2067 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2068 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2069 } 2070 2071 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2072 { 2073 const struct gfx_firmware_header_v2_0 *cp_hdr; 2074 unsigned pipe_id, tmp; 2075 2076 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2077 adev->gfx.pfp_fw->data; 2078 mutex_lock(&adev->srbm_mutex); 2079 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2080 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2081 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2082 (cp_hdr->ucode_start_addr_hi << 30) | 2083 (cp_hdr->ucode_start_addr_lo >> 2)); 2084 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2085 cp_hdr->ucode_start_addr_hi>>2); 2086 2087 /* 2088 * Program CP_ME_CNTL to reset given PIPE to take 2089 * effect of CP_PFP_PRGRM_CNTR_START. 2090 */ 2091 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2092 if (pipe_id == 0) 2093 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2094 PFP_PIPE0_RESET, 1); 2095 else 2096 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2097 PFP_PIPE1_RESET, 1); 2098 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2099 2100 /* Clear pfp pipe0 reset bit. */ 2101 if (pipe_id == 0) 2102 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2103 PFP_PIPE0_RESET, 0); 2104 else 2105 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2106 PFP_PIPE1_RESET, 0); 2107 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2108 } 2109 soc24_grbm_select(adev, 0, 0, 0, 0); 2110 mutex_unlock(&adev->srbm_mutex); 2111 } 2112 2113 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2114 { 2115 const struct gfx_firmware_header_v2_0 *cp_hdr; 2116 unsigned pipe_id, tmp; 2117 2118 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2119 adev->gfx.me_fw->data; 2120 mutex_lock(&adev->srbm_mutex); 2121 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2122 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2123 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2124 (cp_hdr->ucode_start_addr_hi << 30) | 2125 (cp_hdr->ucode_start_addr_lo >> 2) ); 2126 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2127 cp_hdr->ucode_start_addr_hi>>2); 2128 2129 /* 2130 * Program CP_ME_CNTL to reset given PIPE to take 2131 * effect of CP_ME_PRGRM_CNTR_START. 2132 */ 2133 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2134 if (pipe_id == 0) 2135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2136 ME_PIPE0_RESET, 1); 2137 else 2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2139 ME_PIPE1_RESET, 1); 2140 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2141 2142 /* Clear pfp pipe0 reset bit. */ 2143 if (pipe_id == 0) 2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2145 ME_PIPE0_RESET, 0); 2146 else 2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2148 ME_PIPE1_RESET, 0); 2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2150 } 2151 soc24_grbm_select(adev, 0, 0, 0, 0); 2152 mutex_unlock(&adev->srbm_mutex); 2153 } 2154 2155 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2156 { 2157 const struct gfx_firmware_header_v2_0 *cp_hdr; 2158 unsigned pipe_id; 2159 2160 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2161 adev->gfx.mec_fw->data; 2162 mutex_lock(&adev->srbm_mutex); 2163 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2164 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2165 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2166 cp_hdr->ucode_start_addr_lo >> 2 | 2167 cp_hdr->ucode_start_addr_hi << 30); 2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2169 cp_hdr->ucode_start_addr_hi >> 2); 2170 } 2171 soc24_grbm_select(adev, 0, 0, 0, 0); 2172 mutex_unlock(&adev->srbm_mutex); 2173 } 2174 2175 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2176 { 2177 uint32_t cp_status; 2178 uint32_t bootload_status; 2179 int i; 2180 2181 for (i = 0; i < adev->usec_timeout; i++) { 2182 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2183 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2184 2185 if ((cp_status == 0) && 2186 (REG_GET_FIELD(bootload_status, 2187 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2188 break; 2189 } 2190 udelay(1); 2191 if (amdgpu_emu_mode) 2192 msleep(10); 2193 } 2194 2195 if (i >= adev->usec_timeout) { 2196 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2197 return -ETIMEDOUT; 2198 } 2199 2200 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2201 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2202 gfx_v12_0_set_me_ucode_start_addr(adev); 2203 gfx_v12_0_set_mec_ucode_start_addr(adev); 2204 } 2205 2206 return 0; 2207 } 2208 2209 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2210 { 2211 int i; 2212 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2213 2214 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2215 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2216 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2217 2218 for (i = 0; i < adev->usec_timeout; i++) { 2219 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2220 break; 2221 udelay(1); 2222 } 2223 2224 if (i >= adev->usec_timeout) 2225 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2226 2227 return 0; 2228 } 2229 2230 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2231 { 2232 int r; 2233 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2234 const __le32 *fw_ucode, *fw_data; 2235 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2236 uint32_t tmp; 2237 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2238 2239 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2240 adev->gfx.pfp_fw->data; 2241 2242 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2243 2244 /* instruction */ 2245 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2246 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2247 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2248 /* data */ 2249 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2250 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2251 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2252 2253 /* 64kb align */ 2254 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2255 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2256 &adev->gfx.pfp.pfp_fw_obj, 2257 &adev->gfx.pfp.pfp_fw_gpu_addr, 2258 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2259 if (r) { 2260 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2261 gfx_v12_0_pfp_fini(adev); 2262 return r; 2263 } 2264 2265 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2266 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2267 &adev->gfx.pfp.pfp_fw_data_obj, 2268 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2269 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2270 if (r) { 2271 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2272 gfx_v12_0_pfp_fini(adev); 2273 return r; 2274 } 2275 2276 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2277 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2278 2279 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2280 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2281 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2282 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2283 2284 if (amdgpu_emu_mode == 1) 2285 adev->hdp.funcs->flush_hdp(adev, NULL); 2286 2287 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2288 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2289 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2290 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2291 2292 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2293 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2294 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2295 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2296 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2297 2298 /* 2299 * Programming any of the CP_PFP_IC_BASE registers 2300 * forces invalidation of the ME L1 I$. Wait for the 2301 * invalidation complete 2302 */ 2303 for (i = 0; i < usec_timeout; i++) { 2304 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2305 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2306 INVALIDATE_CACHE_COMPLETE)) 2307 break; 2308 udelay(1); 2309 } 2310 2311 if (i >= usec_timeout) { 2312 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2313 return -EINVAL; 2314 } 2315 2316 /* Prime the L1 instruction caches */ 2317 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2318 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2319 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2320 /* Waiting for cache primed*/ 2321 for (i = 0; i < usec_timeout; i++) { 2322 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2323 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2324 ICACHE_PRIMED)) 2325 break; 2326 udelay(1); 2327 } 2328 2329 if (i >= usec_timeout) { 2330 dev_err(adev->dev, "failed to prime instruction cache\n"); 2331 return -EINVAL; 2332 } 2333 2334 mutex_lock(&adev->srbm_mutex); 2335 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2336 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2337 2338 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2339 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2340 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2341 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2342 } 2343 soc24_grbm_select(adev, 0, 0, 0, 0); 2344 mutex_unlock(&adev->srbm_mutex); 2345 2346 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2347 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2348 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2349 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2350 2351 /* Invalidate the data caches */ 2352 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2353 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2354 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2355 2356 for (i = 0; i < usec_timeout; i++) { 2357 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2358 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2359 INVALIDATE_DCACHE_COMPLETE)) 2360 break; 2361 udelay(1); 2362 } 2363 2364 if (i >= usec_timeout) { 2365 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2366 return -EINVAL; 2367 } 2368 2369 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2370 2371 return 0; 2372 } 2373 2374 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2375 { 2376 int r; 2377 const struct gfx_firmware_header_v2_0 *me_hdr; 2378 const __le32 *fw_ucode, *fw_data; 2379 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2380 uint32_t tmp; 2381 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2382 2383 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2384 adev->gfx.me_fw->data; 2385 2386 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2387 2388 /* instruction */ 2389 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2390 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2391 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2392 /* data */ 2393 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2394 le32_to_cpu(me_hdr->data_offset_bytes)); 2395 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2396 2397 /* 64kb align*/ 2398 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2399 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2400 &adev->gfx.me.me_fw_obj, 2401 &adev->gfx.me.me_fw_gpu_addr, 2402 (void **)&adev->gfx.me.me_fw_ptr); 2403 if (r) { 2404 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2405 gfx_v12_0_me_fini(adev); 2406 return r; 2407 } 2408 2409 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2410 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2411 &adev->gfx.me.me_fw_data_obj, 2412 &adev->gfx.me.me_fw_data_gpu_addr, 2413 (void **)&adev->gfx.me.me_fw_data_ptr); 2414 if (r) { 2415 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2416 gfx_v12_0_pfp_fini(adev); 2417 return r; 2418 } 2419 2420 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2421 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2422 2423 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2424 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2425 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2426 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2427 2428 if (amdgpu_emu_mode == 1) 2429 adev->hdp.funcs->flush_hdp(adev, NULL); 2430 2431 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2432 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2433 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2434 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2435 2436 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2437 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2438 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2439 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2440 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2441 2442 /* 2443 * Programming any of the CP_ME_IC_BASE registers 2444 * forces invalidation of the ME L1 I$. Wait for the 2445 * invalidation complete 2446 */ 2447 for (i = 0; i < usec_timeout; i++) { 2448 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2449 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2450 INVALIDATE_CACHE_COMPLETE)) 2451 break; 2452 udelay(1); 2453 } 2454 2455 if (i >= usec_timeout) { 2456 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2457 return -EINVAL; 2458 } 2459 2460 /* Prime the instruction caches */ 2461 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2462 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2463 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2464 2465 /* Waiting for instruction cache primed*/ 2466 for (i = 0; i < usec_timeout; i++) { 2467 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2468 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2469 ICACHE_PRIMED)) 2470 break; 2471 udelay(1); 2472 } 2473 2474 if (i >= usec_timeout) { 2475 dev_err(adev->dev, "failed to prime instruction cache\n"); 2476 return -EINVAL; 2477 } 2478 2479 mutex_lock(&adev->srbm_mutex); 2480 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2481 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2482 2483 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2484 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2485 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2486 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2487 } 2488 soc24_grbm_select(adev, 0, 0, 0, 0); 2489 mutex_unlock(&adev->srbm_mutex); 2490 2491 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2492 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2493 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2494 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2495 2496 /* Invalidate the data caches */ 2497 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2498 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2499 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2500 2501 for (i = 0; i < usec_timeout; i++) { 2502 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2503 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2504 INVALIDATE_DCACHE_COMPLETE)) 2505 break; 2506 udelay(1); 2507 } 2508 2509 if (i >= usec_timeout) { 2510 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2511 return -EINVAL; 2512 } 2513 2514 gfx_v12_0_set_me_ucode_start_addr(adev); 2515 2516 return 0; 2517 } 2518 2519 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2520 { 2521 int r; 2522 2523 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2524 return -EINVAL; 2525 2526 gfx_v12_0_cp_gfx_enable(adev, false); 2527 2528 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2529 if (r) { 2530 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2531 return r; 2532 } 2533 2534 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2535 if (r) { 2536 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2537 return r; 2538 } 2539 2540 return 0; 2541 } 2542 2543 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2544 { 2545 /* init the CP */ 2546 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2547 adev->gfx.config.max_hw_contexts - 1); 2548 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2549 2550 if (!amdgpu_async_gfx_ring) 2551 gfx_v12_0_cp_gfx_enable(adev, true); 2552 2553 return 0; 2554 } 2555 2556 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2557 CP_PIPE_ID pipe) 2558 { 2559 u32 tmp; 2560 2561 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2562 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2563 2564 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2565 } 2566 2567 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2568 struct amdgpu_ring *ring) 2569 { 2570 u32 tmp; 2571 2572 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2573 if (ring->use_doorbell) { 2574 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2575 DOORBELL_OFFSET, ring->doorbell_index); 2576 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2577 DOORBELL_EN, 1); 2578 } else { 2579 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2580 DOORBELL_EN, 0); 2581 } 2582 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2583 2584 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2585 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2586 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2587 2588 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2589 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2590 } 2591 2592 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2593 { 2594 struct amdgpu_ring *ring; 2595 u32 tmp; 2596 u32 rb_bufsz; 2597 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2598 u32 i; 2599 2600 /* Set the write pointer delay */ 2601 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2602 2603 /* set the RB to use vmid 0 */ 2604 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2605 2606 /* Init gfx ring 0 for pipe 0 */ 2607 mutex_lock(&adev->srbm_mutex); 2608 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2609 2610 /* Set ring buffer size */ 2611 ring = &adev->gfx.gfx_ring[0]; 2612 rb_bufsz = order_base_2(ring->ring_size / 8); 2613 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2614 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2615 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2616 2617 /* Initialize the ring buffer's write pointers */ 2618 ring->wptr = 0; 2619 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2620 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2621 2622 /* set the wb address whether it's enabled or not */ 2623 rptr_addr = ring->rptr_gpu_addr; 2624 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2625 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2626 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2627 2628 wptr_gpu_addr = ring->wptr_gpu_addr; 2629 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2630 lower_32_bits(wptr_gpu_addr)); 2631 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2632 upper_32_bits(wptr_gpu_addr)); 2633 2634 mdelay(1); 2635 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2636 2637 rb_addr = ring->gpu_addr >> 8; 2638 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2639 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2640 2641 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2642 2643 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2644 mutex_unlock(&adev->srbm_mutex); 2645 2646 /* Switch to pipe 0 */ 2647 mutex_lock(&adev->srbm_mutex); 2648 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2649 mutex_unlock(&adev->srbm_mutex); 2650 2651 /* start the ring */ 2652 gfx_v12_0_cp_gfx_start(adev); 2653 2654 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2655 ring = &adev->gfx.gfx_ring[i]; 2656 ring->sched.ready = true; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2663 { 2664 u32 data; 2665 2666 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2667 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2668 enable ? 0 : 1); 2669 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2670 enable ? 0 : 1); 2671 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2672 enable ? 0 : 1); 2673 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2674 enable ? 0 : 1); 2675 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2676 enable ? 0 : 1); 2677 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2678 enable ? 1 : 0); 2679 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2680 enable ? 1 : 0); 2681 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2682 enable ? 1 : 0); 2683 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2684 enable ? 1 : 0); 2685 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2686 enable ? 0 : 1); 2687 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2688 2689 adev->gfx.kiq[0].ring.sched.ready = enable; 2690 2691 udelay(50); 2692 } 2693 2694 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2695 { 2696 const struct gfx_firmware_header_v2_0 *mec_hdr; 2697 const __le32 *fw_ucode, *fw_data; 2698 u32 tmp, fw_ucode_size, fw_data_size; 2699 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2700 u32 *fw_ucode_ptr, *fw_data_ptr; 2701 int r; 2702 2703 if (!adev->gfx.mec_fw) 2704 return -EINVAL; 2705 2706 gfx_v12_0_cp_compute_enable(adev, false); 2707 2708 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2709 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2710 2711 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2712 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2713 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2714 2715 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2716 le32_to_cpu(mec_hdr->data_offset_bytes)); 2717 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2718 2719 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2720 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2721 &adev->gfx.mec.mec_fw_obj, 2722 &adev->gfx.mec.mec_fw_gpu_addr, 2723 (void **)&fw_ucode_ptr); 2724 if (r) { 2725 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2726 gfx_v12_0_mec_fini(adev); 2727 return r; 2728 } 2729 2730 r = amdgpu_bo_create_reserved(adev, 2731 ALIGN(fw_data_size, 64 * 1024) * 2732 adev->gfx.mec.num_pipe_per_mec, 2733 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2734 &adev->gfx.mec.mec_fw_data_obj, 2735 &adev->gfx.mec.mec_fw_data_gpu_addr, 2736 (void **)&fw_data_ptr); 2737 if (r) { 2738 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2739 gfx_v12_0_mec_fini(adev); 2740 return r; 2741 } 2742 2743 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2744 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2745 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2746 } 2747 2748 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2749 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2750 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2751 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2752 2753 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2754 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2755 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2756 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2757 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2758 2759 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2760 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2761 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2762 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2763 2764 mutex_lock(&adev->srbm_mutex); 2765 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2766 soc24_grbm_select(adev, 1, i, 0, 0); 2767 2768 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2769 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2770 i * ALIGN(fw_data_size, 64 * 1024))); 2771 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2772 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2773 i * ALIGN(fw_data_size, 64 * 1024))); 2774 2775 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2776 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2777 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2778 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2779 } 2780 mutex_unlock(&adev->srbm_mutex); 2781 soc24_grbm_select(adev, 0, 0, 0, 0); 2782 2783 /* Trigger an invalidation of the L1 instruction caches */ 2784 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2785 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2786 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2787 2788 /* Wait for invalidation complete */ 2789 for (i = 0; i < usec_timeout; i++) { 2790 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2791 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2792 INVALIDATE_DCACHE_COMPLETE)) 2793 break; 2794 udelay(1); 2795 } 2796 2797 if (i >= usec_timeout) { 2798 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2799 return -EINVAL; 2800 } 2801 2802 /* Trigger an invalidation of the L1 instruction caches */ 2803 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2804 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2805 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2806 2807 /* Wait for invalidation complete */ 2808 for (i = 0; i < usec_timeout; i++) { 2809 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2810 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2811 INVALIDATE_CACHE_COMPLETE)) 2812 break; 2813 udelay(1); 2814 } 2815 2816 if (i >= usec_timeout) { 2817 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2818 return -EINVAL; 2819 } 2820 2821 gfx_v12_0_set_mec_ucode_start_addr(adev); 2822 2823 return 0; 2824 } 2825 2826 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2827 { 2828 uint32_t tmp; 2829 struct amdgpu_device *adev = ring->adev; 2830 2831 /* tell RLC which is KIQ queue */ 2832 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2833 tmp &= 0xffffff00; 2834 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2835 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 2836 tmp |= 0x80; 2837 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 2838 } 2839 2840 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2841 { 2842 /* set graphics engine doorbell range */ 2843 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2844 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2845 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2846 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2847 2848 /* set compute engine doorbell range */ 2849 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2850 (adev->doorbell_index.kiq * 2) << 2); 2851 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2852 (adev->doorbell_index.userqueue_end * 2) << 2); 2853 } 2854 2855 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2856 struct amdgpu_mqd_prop *prop) 2857 { 2858 struct v12_gfx_mqd *mqd = m; 2859 uint64_t hqd_gpu_addr, wb_gpu_addr; 2860 uint32_t tmp; 2861 uint32_t rb_bufsz; 2862 2863 /* set up gfx hqd wptr */ 2864 mqd->cp_gfx_hqd_wptr = 0; 2865 mqd->cp_gfx_hqd_wptr_hi = 0; 2866 2867 /* set the pointer to the MQD */ 2868 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2869 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2870 2871 /* set up mqd control */ 2872 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2873 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2874 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2875 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2876 mqd->cp_gfx_mqd_control = tmp; 2877 2878 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2879 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2880 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2881 mqd->cp_gfx_hqd_vmid = 0; 2882 2883 /* set up default queue priority level 2884 * 0x0 = low priority, 0x1 = high priority */ 2885 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2886 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2887 mqd->cp_gfx_hqd_queue_priority = tmp; 2888 2889 /* set up time quantum */ 2890 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2891 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2892 mqd->cp_gfx_hqd_quantum = tmp; 2893 2894 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2895 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2896 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2897 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2898 2899 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2900 wb_gpu_addr = prop->rptr_gpu_addr; 2901 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2902 mqd->cp_gfx_hqd_rptr_addr_hi = 2903 upper_32_bits(wb_gpu_addr) & 0xffff; 2904 2905 /* set up rb_wptr_poll addr */ 2906 wb_gpu_addr = prop->wptr_gpu_addr; 2907 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2908 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2909 2910 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2911 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2912 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2914 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2915 #ifdef __BIG_ENDIAN 2916 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2917 #endif 2918 mqd->cp_gfx_hqd_cntl = tmp; 2919 2920 /* set up cp_doorbell_control */ 2921 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2922 if (prop->use_doorbell) { 2923 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2924 DOORBELL_OFFSET, prop->doorbell_index); 2925 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2926 DOORBELL_EN, 1); 2927 } else 2928 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2929 DOORBELL_EN, 0); 2930 mqd->cp_rb_doorbell_control = tmp; 2931 2932 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2933 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2934 2935 /* active the queue */ 2936 mqd->cp_gfx_hqd_active = 1; 2937 2938 return 0; 2939 } 2940 2941 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2942 { 2943 struct amdgpu_device *adev = ring->adev; 2944 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2945 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2946 2947 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2948 memset((void *)mqd, 0, sizeof(*mqd)); 2949 mutex_lock(&adev->srbm_mutex); 2950 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2951 amdgpu_ring_init_mqd(ring); 2952 soc24_grbm_select(adev, 0, 0, 0, 0); 2953 mutex_unlock(&adev->srbm_mutex); 2954 if (adev->gfx.me.mqd_backup[mqd_idx]) 2955 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2956 } else { 2957 /* restore mqd with the backup copy */ 2958 if (adev->gfx.me.mqd_backup[mqd_idx]) 2959 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2960 /* reset the ring */ 2961 ring->wptr = 0; 2962 *ring->wptr_cpu_addr = 0; 2963 amdgpu_ring_clear_ring(ring); 2964 } 2965 2966 return 0; 2967 } 2968 2969 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2970 { 2971 int r, i; 2972 struct amdgpu_ring *ring; 2973 2974 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2975 ring = &adev->gfx.gfx_ring[i]; 2976 2977 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2978 if (unlikely(r != 0)) 2979 goto done; 2980 2981 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2982 if (!r) { 2983 r = gfx_v12_0_kgq_init_queue(ring, false); 2984 amdgpu_bo_kunmap(ring->mqd_obj); 2985 ring->mqd_ptr = NULL; 2986 } 2987 amdgpu_bo_unreserve(ring->mqd_obj); 2988 if (r) 2989 goto done; 2990 } 2991 2992 r = amdgpu_gfx_enable_kgq(adev, 0); 2993 if (r) 2994 goto done; 2995 2996 r = gfx_v12_0_cp_gfx_start(adev); 2997 if (r) 2998 goto done; 2999 3000 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3001 ring = &adev->gfx.gfx_ring[i]; 3002 ring->sched.ready = true; 3003 } 3004 done: 3005 return r; 3006 } 3007 3008 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3009 struct amdgpu_mqd_prop *prop) 3010 { 3011 struct v12_compute_mqd *mqd = m; 3012 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3013 uint32_t tmp; 3014 3015 mqd->header = 0xC0310800; 3016 mqd->compute_pipelinestat_enable = 0x00000001; 3017 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3018 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3019 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3020 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3021 mqd->compute_misc_reserved = 0x00000007; 3022 3023 eop_base_addr = prop->eop_gpu_addr >> 8; 3024 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3025 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3026 3027 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3028 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3029 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3030 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3031 3032 mqd->cp_hqd_eop_control = tmp; 3033 3034 /* enable doorbell? */ 3035 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3036 3037 if (prop->use_doorbell) { 3038 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3039 DOORBELL_OFFSET, prop->doorbell_index); 3040 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3041 DOORBELL_EN, 1); 3042 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3043 DOORBELL_SOURCE, 0); 3044 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3045 DOORBELL_HIT, 0); 3046 } else { 3047 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3048 DOORBELL_EN, 0); 3049 } 3050 3051 mqd->cp_hqd_pq_doorbell_control = tmp; 3052 3053 /* disable the queue if it's active */ 3054 mqd->cp_hqd_dequeue_request = 0; 3055 mqd->cp_hqd_pq_rptr = 0; 3056 mqd->cp_hqd_pq_wptr_lo = 0; 3057 mqd->cp_hqd_pq_wptr_hi = 0; 3058 3059 /* set the pointer to the MQD */ 3060 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3061 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3062 3063 /* set MQD vmid to 0 */ 3064 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3065 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3066 mqd->cp_mqd_control = tmp; 3067 3068 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3069 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3070 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3071 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3072 3073 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3074 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3075 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3076 (order_base_2(prop->queue_size / 4) - 1)); 3077 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3078 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3079 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3080 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3081 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3082 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3083 mqd->cp_hqd_pq_control = tmp; 3084 3085 /* set the wb address whether it's enabled or not */ 3086 wb_gpu_addr = prop->rptr_gpu_addr; 3087 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3088 mqd->cp_hqd_pq_rptr_report_addr_hi = 3089 upper_32_bits(wb_gpu_addr) & 0xffff; 3090 3091 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3092 wb_gpu_addr = prop->wptr_gpu_addr; 3093 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3094 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3095 3096 tmp = 0; 3097 /* enable the doorbell if requested */ 3098 if (prop->use_doorbell) { 3099 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3101 DOORBELL_OFFSET, prop->doorbell_index); 3102 3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3104 DOORBELL_EN, 1); 3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3106 DOORBELL_SOURCE, 0); 3107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3108 DOORBELL_HIT, 0); 3109 } 3110 3111 mqd->cp_hqd_pq_doorbell_control = tmp; 3112 3113 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3114 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3115 3116 /* set the vmid for the queue */ 3117 mqd->cp_hqd_vmid = 0; 3118 3119 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3120 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3121 mqd->cp_hqd_persistent_state = tmp; 3122 3123 /* set MIN_IB_AVAIL_SIZE */ 3124 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3125 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3126 mqd->cp_hqd_ib_control = tmp; 3127 3128 /* set static priority for a compute queue/ring */ 3129 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3130 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3131 3132 mqd->cp_hqd_active = prop->hqd_active; 3133 3134 return 0; 3135 } 3136 3137 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3138 { 3139 struct amdgpu_device *adev = ring->adev; 3140 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3141 int j; 3142 3143 /* inactivate the queue */ 3144 if (amdgpu_sriov_vf(adev)) 3145 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3146 3147 /* disable wptr polling */ 3148 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3149 3150 /* write the EOP addr */ 3151 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3152 mqd->cp_hqd_eop_base_addr_lo); 3153 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3154 mqd->cp_hqd_eop_base_addr_hi); 3155 3156 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3157 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3158 mqd->cp_hqd_eop_control); 3159 3160 /* enable doorbell? */ 3161 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3162 mqd->cp_hqd_pq_doorbell_control); 3163 3164 /* disable the queue if it's active */ 3165 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3166 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3167 for (j = 0; j < adev->usec_timeout; j++) { 3168 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3169 break; 3170 udelay(1); 3171 } 3172 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3173 mqd->cp_hqd_dequeue_request); 3174 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3175 mqd->cp_hqd_pq_rptr); 3176 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3177 mqd->cp_hqd_pq_wptr_lo); 3178 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3179 mqd->cp_hqd_pq_wptr_hi); 3180 } 3181 3182 /* set the pointer to the MQD */ 3183 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3184 mqd->cp_mqd_base_addr_lo); 3185 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3186 mqd->cp_mqd_base_addr_hi); 3187 3188 /* set MQD vmid to 0 */ 3189 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3190 mqd->cp_mqd_control); 3191 3192 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3193 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3194 mqd->cp_hqd_pq_base_lo); 3195 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3196 mqd->cp_hqd_pq_base_hi); 3197 3198 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3199 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3200 mqd->cp_hqd_pq_control); 3201 3202 /* set the wb address whether it's enabled or not */ 3203 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3204 mqd->cp_hqd_pq_rptr_report_addr_lo); 3205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3206 mqd->cp_hqd_pq_rptr_report_addr_hi); 3207 3208 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3209 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3210 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3211 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3212 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3213 3214 /* enable the doorbell if requested */ 3215 if (ring->use_doorbell) { 3216 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3217 (adev->doorbell_index.kiq * 2) << 2); 3218 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3219 (adev->doorbell_index.userqueue_end * 2) << 2); 3220 } 3221 3222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3223 mqd->cp_hqd_pq_doorbell_control); 3224 3225 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3226 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3227 mqd->cp_hqd_pq_wptr_lo); 3228 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3229 mqd->cp_hqd_pq_wptr_hi); 3230 3231 /* set the vmid for the queue */ 3232 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3233 3234 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3235 mqd->cp_hqd_persistent_state); 3236 3237 /* activate the queue */ 3238 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3239 mqd->cp_hqd_active); 3240 3241 if (ring->use_doorbell) 3242 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3243 3244 return 0; 3245 } 3246 3247 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3248 { 3249 struct amdgpu_device *adev = ring->adev; 3250 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3251 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3252 3253 gfx_v12_0_kiq_setting(ring); 3254 3255 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3256 /* reset MQD to a clean status */ 3257 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3258 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3259 3260 /* reset ring buffer */ 3261 ring->wptr = 0; 3262 amdgpu_ring_clear_ring(ring); 3263 3264 mutex_lock(&adev->srbm_mutex); 3265 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3266 gfx_v12_0_kiq_init_register(ring); 3267 soc24_grbm_select(adev, 0, 0, 0, 0); 3268 mutex_unlock(&adev->srbm_mutex); 3269 } else { 3270 memset((void *)mqd, 0, sizeof(*mqd)); 3271 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3272 amdgpu_ring_clear_ring(ring); 3273 mutex_lock(&adev->srbm_mutex); 3274 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3275 amdgpu_ring_init_mqd(ring); 3276 gfx_v12_0_kiq_init_register(ring); 3277 soc24_grbm_select(adev, 0, 0, 0, 0); 3278 mutex_unlock(&adev->srbm_mutex); 3279 3280 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3281 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3282 } 3283 3284 return 0; 3285 } 3286 3287 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3288 { 3289 struct amdgpu_device *adev = ring->adev; 3290 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3291 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3292 3293 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3294 memset((void *)mqd, 0, sizeof(*mqd)); 3295 mutex_lock(&adev->srbm_mutex); 3296 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3297 amdgpu_ring_init_mqd(ring); 3298 soc24_grbm_select(adev, 0, 0, 0, 0); 3299 mutex_unlock(&adev->srbm_mutex); 3300 3301 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3302 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3303 } else { 3304 /* restore MQD to a clean status */ 3305 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3306 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3307 /* reset ring buffer */ 3308 ring->wptr = 0; 3309 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3310 amdgpu_ring_clear_ring(ring); 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3317 { 3318 struct amdgpu_ring *ring; 3319 int r; 3320 3321 ring = &adev->gfx.kiq[0].ring; 3322 3323 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3324 if (unlikely(r != 0)) 3325 return r; 3326 3327 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3328 if (unlikely(r != 0)) { 3329 amdgpu_bo_unreserve(ring->mqd_obj); 3330 return r; 3331 } 3332 3333 gfx_v12_0_kiq_init_queue(ring); 3334 amdgpu_bo_kunmap(ring->mqd_obj); 3335 ring->mqd_ptr = NULL; 3336 amdgpu_bo_unreserve(ring->mqd_obj); 3337 ring->sched.ready = true; 3338 return 0; 3339 } 3340 3341 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3342 { 3343 struct amdgpu_ring *ring = NULL; 3344 int r = 0, i; 3345 3346 if (!amdgpu_async_gfx_ring) 3347 gfx_v12_0_cp_compute_enable(adev, true); 3348 3349 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3350 ring = &adev->gfx.compute_ring[i]; 3351 3352 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3353 if (unlikely(r != 0)) 3354 goto done; 3355 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3356 if (!r) { 3357 r = gfx_v12_0_kcq_init_queue(ring, false); 3358 amdgpu_bo_kunmap(ring->mqd_obj); 3359 ring->mqd_ptr = NULL; 3360 } 3361 amdgpu_bo_unreserve(ring->mqd_obj); 3362 if (r) 3363 goto done; 3364 } 3365 3366 r = amdgpu_gfx_enable_kcq(adev, 0); 3367 done: 3368 return r; 3369 } 3370 3371 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3372 { 3373 int r, i; 3374 struct amdgpu_ring *ring; 3375 3376 if (!(adev->flags & AMD_IS_APU)) 3377 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3378 3379 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3380 /* legacy firmware loading */ 3381 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3382 if (r) 3383 return r; 3384 3385 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3386 if (r) 3387 return r; 3388 } 3389 3390 gfx_v12_0_cp_set_doorbell_range(adev); 3391 3392 if (amdgpu_async_gfx_ring) { 3393 gfx_v12_0_cp_compute_enable(adev, true); 3394 gfx_v12_0_cp_gfx_enable(adev, true); 3395 } 3396 3397 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3398 r = amdgpu_mes_kiq_hw_init(adev); 3399 else 3400 r = gfx_v12_0_kiq_resume(adev); 3401 if (r) 3402 return r; 3403 3404 r = gfx_v12_0_kcq_resume(adev); 3405 if (r) 3406 return r; 3407 3408 if (!amdgpu_async_gfx_ring) { 3409 r = gfx_v12_0_cp_gfx_resume(adev); 3410 if (r) 3411 return r; 3412 } else { 3413 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3414 if (r) 3415 return r; 3416 } 3417 3418 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3419 ring = &adev->gfx.gfx_ring[i]; 3420 r = amdgpu_ring_test_helper(ring); 3421 if (r) 3422 return r; 3423 } 3424 3425 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3426 ring = &adev->gfx.compute_ring[i]; 3427 r = amdgpu_ring_test_helper(ring); 3428 if (r) 3429 return r; 3430 } 3431 3432 return 0; 3433 } 3434 3435 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3436 { 3437 gfx_v12_0_cp_gfx_enable(adev, enable); 3438 gfx_v12_0_cp_compute_enable(adev, enable); 3439 } 3440 3441 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3442 { 3443 int r; 3444 bool value; 3445 3446 r = adev->gfxhub.funcs->gart_enable(adev); 3447 if (r) 3448 return r; 3449 3450 adev->hdp.funcs->flush_hdp(adev, NULL); 3451 3452 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3453 false : true; 3454 3455 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3456 /* TODO investigate why this and the hdp flush above is needed, 3457 * are we missing a flush somewhere else? */ 3458 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3459 3460 return 0; 3461 } 3462 3463 static int get_gb_addr_config(struct amdgpu_device *adev) 3464 { 3465 u32 gb_addr_config; 3466 3467 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3468 if (gb_addr_config == 0) 3469 return -EINVAL; 3470 3471 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3472 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3473 3474 adev->gfx.config.gb_addr_config = gb_addr_config; 3475 3476 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3477 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3478 GB_ADDR_CONFIG, NUM_PIPES); 3479 3480 adev->gfx.config.max_tile_pipes = 3481 adev->gfx.config.gb_addr_config_fields.num_pipes; 3482 3483 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3484 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3485 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3486 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3487 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3488 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3489 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3490 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3491 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3492 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3493 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3494 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3495 3496 return 0; 3497 } 3498 3499 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3500 { 3501 uint32_t data; 3502 3503 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3504 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3505 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3506 3507 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3508 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3509 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3510 } 3511 3512 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3513 { 3514 if (amdgpu_sriov_vf(adev)) 3515 return; 3516 3517 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3518 case IP_VERSION(12, 0, 0): 3519 case IP_VERSION(12, 0, 1): 3520 soc15_program_register_sequence(adev, 3521 golden_settings_gc_12_0, 3522 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3523 3524 if (adev->rev_id == 0) 3525 soc15_program_register_sequence(adev, 3526 golden_settings_gc_12_0_rev0, 3527 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3528 break; 3529 default: 3530 break; 3531 } 3532 } 3533 3534 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3535 { 3536 int r; 3537 struct amdgpu_device *adev = ip_block->adev; 3538 3539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3540 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3541 /* RLC autoload sequence 1: Program rlc ram */ 3542 if (adev->gfx.imu.funcs->program_rlc_ram) 3543 adev->gfx.imu.funcs->program_rlc_ram(adev); 3544 } 3545 /* rlc autoload firmware */ 3546 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3547 if (r) 3548 return r; 3549 } else { 3550 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3551 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3552 if (adev->gfx.imu.funcs->load_microcode) 3553 adev->gfx.imu.funcs->load_microcode(adev); 3554 if (adev->gfx.imu.funcs->setup_imu) 3555 adev->gfx.imu.funcs->setup_imu(adev); 3556 if (adev->gfx.imu.funcs->start_imu) 3557 adev->gfx.imu.funcs->start_imu(adev); 3558 } 3559 3560 /* disable gpa mode in backdoor loading */ 3561 gfx_v12_0_disable_gpa_mode(adev); 3562 } 3563 } 3564 3565 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3566 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3567 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3568 if (r) { 3569 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3570 return r; 3571 } 3572 } 3573 3574 if (!amdgpu_emu_mode) 3575 gfx_v12_0_init_golden_registers(adev); 3576 3577 adev->gfx.is_poweron = true; 3578 3579 if (get_gb_addr_config(adev)) 3580 DRM_WARN("Invalid gb_addr_config !\n"); 3581 3582 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3583 gfx_v12_0_config_gfx_rs64(adev); 3584 3585 r = gfx_v12_0_gfxhub_enable(adev); 3586 if (r) 3587 return r; 3588 3589 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3590 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3591 (amdgpu_dpm == 1)) { 3592 /** 3593 * For gfx 12, rlc firmware loading relies on smu firmware is 3594 * loaded firstly, so in direct type, it has to load smc ucode 3595 * here before rlc. 3596 */ 3597 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3598 if (r) 3599 return r; 3600 } 3601 3602 gfx_v12_0_constants_init(adev); 3603 3604 if (adev->nbio.funcs->gc_doorbell_init) 3605 adev->nbio.funcs->gc_doorbell_init(adev); 3606 3607 r = gfx_v12_0_rlc_resume(adev); 3608 if (r) 3609 return r; 3610 3611 /* 3612 * init golden registers and rlc resume may override some registers, 3613 * reconfig them here 3614 */ 3615 gfx_v12_0_tcp_harvest(adev); 3616 3617 r = gfx_v12_0_cp_resume(adev); 3618 if (r) 3619 return r; 3620 3621 return r; 3622 } 3623 3624 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3625 { 3626 struct amdgpu_device *adev = ip_block->adev; 3627 uint32_t tmp; 3628 3629 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3630 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3631 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3632 3633 if (!adev->no_hw_access) { 3634 if (amdgpu_async_gfx_ring) { 3635 if (amdgpu_gfx_disable_kgq(adev, 0)) 3636 DRM_ERROR("KGQ disable failed\n"); 3637 } 3638 3639 if (amdgpu_gfx_disable_kcq(adev, 0)) 3640 DRM_ERROR("KCQ disable failed\n"); 3641 3642 amdgpu_mes_kiq_hw_fini(adev); 3643 } 3644 3645 if (amdgpu_sriov_vf(adev)) { 3646 gfx_v12_0_cp_gfx_enable(adev, false); 3647 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3648 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3649 tmp &= 0xffffff00; 3650 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3651 3652 return 0; 3653 } 3654 gfx_v12_0_cp_enable(adev, false); 3655 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3656 3657 adev->gfxhub.funcs->gart_disable(adev); 3658 3659 adev->gfx.is_poweron = false; 3660 3661 return 0; 3662 } 3663 3664 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3665 { 3666 return gfx_v12_0_hw_fini(ip_block); 3667 } 3668 3669 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3670 { 3671 return gfx_v12_0_hw_init(ip_block); 3672 } 3673 3674 static bool gfx_v12_0_is_idle(void *handle) 3675 { 3676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3677 3678 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3679 GRBM_STATUS, GUI_ACTIVE)) 3680 return false; 3681 else 3682 return true; 3683 } 3684 3685 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3686 { 3687 unsigned i; 3688 u32 tmp; 3689 struct amdgpu_device *adev = ip_block->adev; 3690 3691 for (i = 0; i < adev->usec_timeout; i++) { 3692 /* read MC_STATUS */ 3693 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3694 GRBM_STATUS__GUI_ACTIVE_MASK; 3695 3696 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3697 return 0; 3698 udelay(1); 3699 } 3700 return -ETIMEDOUT; 3701 } 3702 3703 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3704 { 3705 uint64_t clock = 0; 3706 3707 if (adev->smuio.funcs && 3708 adev->smuio.funcs->get_gpu_clock_counter) 3709 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3710 else 3711 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3712 3713 return clock; 3714 } 3715 3716 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3717 { 3718 struct amdgpu_device *adev = ip_block->adev; 3719 3720 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3721 3722 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3723 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3724 AMDGPU_MAX_COMPUTE_RINGS); 3725 3726 gfx_v12_0_set_kiq_pm4_funcs(adev); 3727 gfx_v12_0_set_ring_funcs(adev); 3728 gfx_v12_0_set_irq_funcs(adev); 3729 gfx_v12_0_set_rlc_funcs(adev); 3730 gfx_v12_0_set_mqd_funcs(adev); 3731 gfx_v12_0_set_imu_funcs(adev); 3732 3733 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3734 3735 return gfx_v12_0_init_microcode(adev); 3736 } 3737 3738 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3739 { 3740 struct amdgpu_device *adev = ip_block->adev; 3741 int r; 3742 3743 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3744 if (r) 3745 return r; 3746 3747 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3748 if (r) 3749 return r; 3750 3751 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3752 if (r) 3753 return r; 3754 3755 return 0; 3756 } 3757 3758 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3759 { 3760 uint32_t rlc_cntl; 3761 3762 /* if RLC is not enabled, do nothing */ 3763 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3764 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3765 } 3766 3767 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3768 int xcc_id) 3769 { 3770 uint32_t data; 3771 unsigned i; 3772 3773 data = RLC_SAFE_MODE__CMD_MASK; 3774 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3775 3776 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3777 3778 /* wait for RLC_SAFE_MODE */ 3779 for (i = 0; i < adev->usec_timeout; i++) { 3780 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3781 RLC_SAFE_MODE, CMD)) 3782 break; 3783 udelay(1); 3784 } 3785 } 3786 3787 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3788 int xcc_id) 3789 { 3790 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3791 } 3792 3793 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3794 bool enable) 3795 { 3796 uint32_t def, data; 3797 3798 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3799 return; 3800 3801 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3802 3803 if (enable) 3804 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3805 else 3806 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3807 3808 if (def != data) 3809 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3810 } 3811 3812 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3813 struct amdgpu_ring *ring, 3814 unsigned vmid) 3815 { 3816 u32 reg, data; 3817 3818 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3819 if (amdgpu_sriov_is_pp_one_vf(adev)) 3820 data = RREG32_NO_KIQ(reg); 3821 else 3822 data = RREG32(reg); 3823 3824 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3825 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3826 3827 if (amdgpu_sriov_is_pp_one_vf(adev)) 3828 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3829 else 3830 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3831 3832 if (ring 3833 && amdgpu_sriov_is_pp_one_vf(adev) 3834 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3835 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3836 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3837 amdgpu_ring_emit_wreg(ring, reg, data); 3838 } 3839 } 3840 3841 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3842 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3843 .set_safe_mode = gfx_v12_0_set_safe_mode, 3844 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3845 .init = gfx_v12_0_rlc_init, 3846 .get_csb_size = gfx_v12_0_get_csb_size, 3847 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3848 .resume = gfx_v12_0_rlc_resume, 3849 .stop = gfx_v12_0_rlc_stop, 3850 .reset = gfx_v12_0_rlc_reset, 3851 .start = gfx_v12_0_rlc_start, 3852 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3853 }; 3854 3855 #if 0 3856 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3857 { 3858 /* TODO */ 3859 } 3860 3861 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3862 { 3863 /* TODO */ 3864 } 3865 #endif 3866 3867 static int gfx_v12_0_set_powergating_state(void *handle, 3868 enum amd_powergating_state state) 3869 { 3870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3871 bool enable = (state == AMD_PG_STATE_GATE); 3872 3873 if (amdgpu_sriov_vf(adev)) 3874 return 0; 3875 3876 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3877 case IP_VERSION(12, 0, 0): 3878 case IP_VERSION(12, 0, 1): 3879 amdgpu_gfx_off_ctrl(adev, enable); 3880 break; 3881 default: 3882 break; 3883 } 3884 3885 return 0; 3886 } 3887 3888 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3889 bool enable) 3890 { 3891 uint32_t def, data; 3892 3893 if (!(adev->cg_flags & 3894 (AMD_CG_SUPPORT_GFX_CGCG | 3895 AMD_CG_SUPPORT_GFX_CGLS | 3896 AMD_CG_SUPPORT_GFX_3D_CGCG | 3897 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3898 return; 3899 3900 if (enable) { 3901 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3902 3903 /* unset CGCG override */ 3904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3905 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3906 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3907 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3908 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3909 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3910 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3911 3912 /* update CGCG override bits */ 3913 if (def != data) 3914 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3915 3916 /* enable cgcg FSM(0x0000363F) */ 3917 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3918 3919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3920 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3921 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3922 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3923 } 3924 3925 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3926 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3927 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3928 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3929 } 3930 3931 if (def != data) 3932 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3933 3934 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3935 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3936 3937 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3938 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3939 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3940 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3941 } 3942 3943 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3944 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3945 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3946 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3947 } 3948 3949 if (def != data) 3950 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3951 3952 /* set IDLE_POLL_COUNT(0x00900100) */ 3953 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3954 3955 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3956 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3957 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3958 3959 if (def != data) 3960 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3961 3962 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3963 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3964 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3965 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3966 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3967 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3968 3969 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3970 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3971 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3972 3973 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3974 if (adev->sdma.num_instances > 1) { 3975 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3976 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3977 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3978 } 3979 } else { 3980 /* Program RLC_CGCG_CGLS_CTRL */ 3981 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3982 3983 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3984 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3985 3986 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3987 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3988 3989 if (def != data) 3990 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3991 3992 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3993 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3994 3995 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 3996 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3997 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3998 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3999 4000 if (def != data) 4001 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4002 4003 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4004 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4005 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4006 4007 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4008 if (adev->sdma.num_instances > 1) { 4009 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4010 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4011 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4012 } 4013 } 4014 } 4015 4016 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4017 bool enable) 4018 { 4019 uint32_t data, def; 4020 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4021 return; 4022 4023 /* It is disabled by HW by default */ 4024 if (enable) { 4025 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4026 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4027 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4028 4029 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4030 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4031 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4032 4033 if (def != data) 4034 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4035 } 4036 } else { 4037 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4038 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4039 4040 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4041 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4042 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4043 4044 if (def != data) 4045 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4046 } 4047 } 4048 } 4049 4050 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4051 bool enable) 4052 { 4053 uint32_t def, data; 4054 4055 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4056 return; 4057 4058 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4059 4060 if (enable) 4061 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4062 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4063 else 4064 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4065 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4066 4067 if (def != data) 4068 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4069 } 4070 4071 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4072 bool enable) 4073 { 4074 uint32_t def, data; 4075 4076 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4077 return; 4078 4079 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4080 4081 if (enable) 4082 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4083 else 4084 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4085 4086 if (def != data) 4087 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4088 } 4089 4090 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4091 bool enable) 4092 { 4093 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4094 4095 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4096 4097 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4098 4099 gfx_v12_0_update_repeater_fgcg(adev, enable); 4100 4101 gfx_v12_0_update_sram_fgcg(adev, enable); 4102 4103 gfx_v12_0_update_perf_clk(adev, enable); 4104 4105 if (adev->cg_flags & 4106 (AMD_CG_SUPPORT_GFX_MGCG | 4107 AMD_CG_SUPPORT_GFX_CGLS | 4108 AMD_CG_SUPPORT_GFX_CGCG | 4109 AMD_CG_SUPPORT_GFX_3D_CGCG | 4110 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4111 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4112 4113 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4114 4115 return 0; 4116 } 4117 4118 static int gfx_v12_0_set_clockgating_state(void *handle, 4119 enum amd_clockgating_state state) 4120 { 4121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4122 4123 if (amdgpu_sriov_vf(adev)) 4124 return 0; 4125 4126 switch (adev->ip_versions[GC_HWIP][0]) { 4127 case IP_VERSION(12, 0, 0): 4128 case IP_VERSION(12, 0, 1): 4129 gfx_v12_0_update_gfx_clock_gating(adev, 4130 state == AMD_CG_STATE_GATE); 4131 break; 4132 default: 4133 break; 4134 } 4135 4136 return 0; 4137 } 4138 4139 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 4140 { 4141 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4142 int data; 4143 4144 /* AMD_CG_SUPPORT_GFX_MGCG */ 4145 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4146 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4147 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4148 4149 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4150 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4151 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4152 4153 /* AMD_CG_SUPPORT_GFX_FGCG */ 4154 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4155 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4156 4157 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4158 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4159 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4160 4161 /* AMD_CG_SUPPORT_GFX_CGCG */ 4162 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4163 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4164 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4165 4166 /* AMD_CG_SUPPORT_GFX_CGLS */ 4167 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4168 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4169 4170 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4171 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4172 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4173 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4174 4175 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4176 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4177 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4178 } 4179 4180 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4181 { 4182 /* gfx12 is 32bit rptr*/ 4183 return *(uint32_t *)ring->rptr_cpu_addr; 4184 } 4185 4186 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4187 { 4188 struct amdgpu_device *adev = ring->adev; 4189 u64 wptr; 4190 4191 /* XXX check if swapping is necessary on BE */ 4192 if (ring->use_doorbell) { 4193 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4194 } else { 4195 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4196 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4197 } 4198 4199 return wptr; 4200 } 4201 4202 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4203 { 4204 struct amdgpu_device *adev = ring->adev; 4205 uint32_t *wptr_saved; 4206 uint32_t *is_queue_unmap; 4207 uint64_t aggregated_db_index; 4208 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4209 uint64_t wptr_tmp; 4210 4211 if (ring->is_mes_queue) { 4212 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4213 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4214 sizeof(uint32_t)); 4215 aggregated_db_index = 4216 amdgpu_mes_get_aggregated_doorbell_index(adev, 4217 ring->hw_prio); 4218 4219 wptr_tmp = ring->wptr & ring->buf_mask; 4220 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4221 *wptr_saved = wptr_tmp; 4222 /* assume doorbell always being used by mes mapped queue */ 4223 if (*is_queue_unmap) { 4224 WDOORBELL64(aggregated_db_index, wptr_tmp); 4225 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4226 } else { 4227 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4228 4229 if (*is_queue_unmap) 4230 WDOORBELL64(aggregated_db_index, wptr_tmp); 4231 } 4232 } else { 4233 if (ring->use_doorbell) { 4234 /* XXX check if swapping is necessary on BE */ 4235 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4236 ring->wptr); 4237 WDOORBELL64(ring->doorbell_index, ring->wptr); 4238 } else { 4239 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4240 lower_32_bits(ring->wptr)); 4241 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4242 upper_32_bits(ring->wptr)); 4243 } 4244 } 4245 } 4246 4247 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4248 { 4249 /* gfx12 hardware is 32bit rptr */ 4250 return *(uint32_t *)ring->rptr_cpu_addr; 4251 } 4252 4253 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4254 { 4255 u64 wptr; 4256 4257 /* XXX check if swapping is necessary on BE */ 4258 if (ring->use_doorbell) 4259 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4260 else 4261 BUG(); 4262 return wptr; 4263 } 4264 4265 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4266 { 4267 struct amdgpu_device *adev = ring->adev; 4268 uint32_t *wptr_saved; 4269 uint32_t *is_queue_unmap; 4270 uint64_t aggregated_db_index; 4271 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4272 uint64_t wptr_tmp; 4273 4274 if (ring->is_mes_queue) { 4275 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4276 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4277 sizeof(uint32_t)); 4278 aggregated_db_index = 4279 amdgpu_mes_get_aggregated_doorbell_index(adev, 4280 ring->hw_prio); 4281 4282 wptr_tmp = ring->wptr & ring->buf_mask; 4283 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4284 *wptr_saved = wptr_tmp; 4285 /* assume doorbell always used by mes mapped queue */ 4286 if (*is_queue_unmap) { 4287 WDOORBELL64(aggregated_db_index, wptr_tmp); 4288 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4289 } else { 4290 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4291 4292 if (*is_queue_unmap) 4293 WDOORBELL64(aggregated_db_index, wptr_tmp); 4294 } 4295 } else { 4296 /* XXX check if swapping is necessary on BE */ 4297 if (ring->use_doorbell) { 4298 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4299 ring->wptr); 4300 WDOORBELL64(ring->doorbell_index, ring->wptr); 4301 } else { 4302 BUG(); /* only DOORBELL method supported on gfx12 now */ 4303 } 4304 } 4305 } 4306 4307 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4308 { 4309 struct amdgpu_device *adev = ring->adev; 4310 u32 ref_and_mask, reg_mem_engine; 4311 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4312 4313 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4314 switch (ring->me) { 4315 case 1: 4316 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4317 break; 4318 case 2: 4319 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4320 break; 4321 default: 4322 return; 4323 } 4324 reg_mem_engine = 0; 4325 } else { 4326 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4327 reg_mem_engine = 1; /* pfp */ 4328 } 4329 4330 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4331 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4332 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4333 ref_and_mask, ref_and_mask, 0x20); 4334 } 4335 4336 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4337 struct amdgpu_job *job, 4338 struct amdgpu_ib *ib, 4339 uint32_t flags) 4340 { 4341 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4342 u32 header, control = 0; 4343 4344 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4345 4346 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4347 4348 control |= ib->length_dw | (vmid << 24); 4349 4350 if (ring->is_mes_queue) 4351 /* inherit vmid from mqd */ 4352 control |= 0x400000; 4353 4354 amdgpu_ring_write(ring, header); 4355 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4356 amdgpu_ring_write(ring, 4357 #ifdef __BIG_ENDIAN 4358 (2 << 0) | 4359 #endif 4360 lower_32_bits(ib->gpu_addr)); 4361 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4362 amdgpu_ring_write(ring, control); 4363 } 4364 4365 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4366 struct amdgpu_job *job, 4367 struct amdgpu_ib *ib, 4368 uint32_t flags) 4369 { 4370 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4371 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4372 4373 if (ring->is_mes_queue) 4374 /* inherit vmid from mqd */ 4375 control |= 0x40000000; 4376 4377 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4378 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4379 amdgpu_ring_write(ring, 4380 #ifdef __BIG_ENDIAN 4381 (2 << 0) | 4382 #endif 4383 lower_32_bits(ib->gpu_addr)); 4384 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4385 amdgpu_ring_write(ring, control); 4386 } 4387 4388 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4389 u64 seq, unsigned flags) 4390 { 4391 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4392 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4393 4394 /* RELEASE_MEM - flush caches, send int */ 4395 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4396 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4397 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4398 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4399 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4400 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4401 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4402 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4403 4404 /* 4405 * the address should be Qword aligned if 64bit write, Dword 4406 * aligned if only send 32bit data low (discard data high) 4407 */ 4408 if (write64bit) 4409 BUG_ON(addr & 0x7); 4410 else 4411 BUG_ON(addr & 0x3); 4412 amdgpu_ring_write(ring, lower_32_bits(addr)); 4413 amdgpu_ring_write(ring, upper_32_bits(addr)); 4414 amdgpu_ring_write(ring, lower_32_bits(seq)); 4415 amdgpu_ring_write(ring, upper_32_bits(seq)); 4416 amdgpu_ring_write(ring, ring->is_mes_queue ? 4417 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4418 } 4419 4420 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4421 { 4422 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4423 uint32_t seq = ring->fence_drv.sync_seq; 4424 uint64_t addr = ring->fence_drv.gpu_addr; 4425 4426 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4427 upper_32_bits(addr), seq, 0xffffffff, 4); 4428 } 4429 4430 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4431 uint16_t pasid, uint32_t flush_type, 4432 bool all_hub, uint8_t dst_sel) 4433 { 4434 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4435 amdgpu_ring_write(ring, 4436 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4437 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4438 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4439 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4440 } 4441 4442 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4443 unsigned vmid, uint64_t pd_addr) 4444 { 4445 if (ring->is_mes_queue) 4446 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4447 else 4448 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4449 4450 /* compute doesn't have PFP */ 4451 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4452 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4453 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4454 amdgpu_ring_write(ring, 0x0); 4455 } 4456 } 4457 4458 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4459 u64 seq, unsigned int flags) 4460 { 4461 struct amdgpu_device *adev = ring->adev; 4462 4463 /* we only allocate 32bit for each seq wb address */ 4464 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4465 4466 /* write fence seq to the "addr" */ 4467 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4468 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4469 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4470 amdgpu_ring_write(ring, lower_32_bits(addr)); 4471 amdgpu_ring_write(ring, upper_32_bits(addr)); 4472 amdgpu_ring_write(ring, lower_32_bits(seq)); 4473 4474 if (flags & AMDGPU_FENCE_FLAG_INT) { 4475 /* set register to trigger INT */ 4476 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4477 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4478 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4479 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4480 amdgpu_ring_write(ring, 0); 4481 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4482 } 4483 } 4484 4485 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4486 uint32_t flags) 4487 { 4488 uint32_t dw2 = 0; 4489 4490 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4491 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4492 /* set load_global_config & load_global_uconfig */ 4493 dw2 |= 0x8001; 4494 /* set load_cs_sh_regs */ 4495 dw2 |= 0x01000000; 4496 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4497 dw2 |= 0x10002; 4498 } 4499 4500 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4501 amdgpu_ring_write(ring, dw2); 4502 amdgpu_ring_write(ring, 0); 4503 } 4504 4505 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4506 uint64_t addr) 4507 { 4508 unsigned ret; 4509 4510 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4511 amdgpu_ring_write(ring, lower_32_bits(addr)); 4512 amdgpu_ring_write(ring, upper_32_bits(addr)); 4513 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4514 amdgpu_ring_write(ring, 0); 4515 ret = ring->wptr & ring->buf_mask; 4516 /* patch dummy value later */ 4517 amdgpu_ring_write(ring, 0); 4518 4519 return ret; 4520 } 4521 4522 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4523 { 4524 int i, r = 0; 4525 struct amdgpu_device *adev = ring->adev; 4526 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4527 struct amdgpu_ring *kiq_ring = &kiq->ring; 4528 unsigned long flags; 4529 4530 if (adev->enable_mes) 4531 return -EINVAL; 4532 4533 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4534 return -EINVAL; 4535 4536 spin_lock_irqsave(&kiq->ring_lock, flags); 4537 4538 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4539 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4540 return -ENOMEM; 4541 } 4542 4543 /* assert preemption condition */ 4544 amdgpu_ring_set_preempt_cond_exec(ring, false); 4545 4546 /* assert IB preemption, emit the trailing fence */ 4547 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4548 ring->trail_fence_gpu_addr, 4549 ++ring->trail_seq); 4550 amdgpu_ring_commit(kiq_ring); 4551 4552 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4553 4554 /* poll the trailing fence */ 4555 for (i = 0; i < adev->usec_timeout; i++) { 4556 if (ring->trail_seq == 4557 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4558 break; 4559 udelay(1); 4560 } 4561 4562 if (i >= adev->usec_timeout) { 4563 r = -EINVAL; 4564 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4565 } 4566 4567 /* deassert preemption condition */ 4568 amdgpu_ring_set_preempt_cond_exec(ring, true); 4569 return r; 4570 } 4571 4572 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4573 bool start, 4574 bool secure) 4575 { 4576 uint32_t v = secure ? FRAME_TMZ : 0; 4577 4578 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4579 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4580 } 4581 4582 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4583 uint32_t reg_val_offs) 4584 { 4585 struct amdgpu_device *adev = ring->adev; 4586 4587 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4588 amdgpu_ring_write(ring, 0 | /* src: register*/ 4589 (5 << 8) | /* dst: memory */ 4590 (1 << 20)); /* write confirm */ 4591 amdgpu_ring_write(ring, reg); 4592 amdgpu_ring_write(ring, 0); 4593 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4594 reg_val_offs * 4)); 4595 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4596 reg_val_offs * 4)); 4597 } 4598 4599 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4600 uint32_t reg, 4601 uint32_t val) 4602 { 4603 uint32_t cmd = 0; 4604 4605 switch (ring->funcs->type) { 4606 case AMDGPU_RING_TYPE_GFX: 4607 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4608 break; 4609 case AMDGPU_RING_TYPE_KIQ: 4610 cmd = (1 << 16); /* no inc addr */ 4611 break; 4612 default: 4613 cmd = WR_CONFIRM; 4614 break; 4615 } 4616 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4617 amdgpu_ring_write(ring, cmd); 4618 amdgpu_ring_write(ring, reg); 4619 amdgpu_ring_write(ring, 0); 4620 amdgpu_ring_write(ring, val); 4621 } 4622 4623 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4624 uint32_t val, uint32_t mask) 4625 { 4626 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4627 } 4628 4629 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4630 uint32_t reg0, uint32_t reg1, 4631 uint32_t ref, uint32_t mask) 4632 { 4633 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4634 4635 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4636 ref, mask, 0x20); 4637 } 4638 4639 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4640 unsigned vmid) 4641 { 4642 struct amdgpu_device *adev = ring->adev; 4643 uint32_t value = 0; 4644 4645 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4646 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4647 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4648 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4649 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4650 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4651 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4652 } 4653 4654 static void 4655 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4656 uint32_t me, uint32_t pipe, 4657 enum amdgpu_interrupt_state state) 4658 { 4659 uint32_t cp_int_cntl, cp_int_cntl_reg; 4660 4661 if (!me) { 4662 switch (pipe) { 4663 case 0: 4664 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4665 break; 4666 default: 4667 DRM_DEBUG("invalid pipe %d\n", pipe); 4668 return; 4669 } 4670 } else { 4671 DRM_DEBUG("invalid me %d\n", me); 4672 return; 4673 } 4674 4675 switch (state) { 4676 case AMDGPU_IRQ_STATE_DISABLE: 4677 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4678 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4679 TIME_STAMP_INT_ENABLE, 0); 4680 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4681 GENERIC0_INT_ENABLE, 0); 4682 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4683 break; 4684 case AMDGPU_IRQ_STATE_ENABLE: 4685 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4686 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4687 TIME_STAMP_INT_ENABLE, 1); 4688 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4689 GENERIC0_INT_ENABLE, 1); 4690 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4691 break; 4692 default: 4693 break; 4694 } 4695 } 4696 4697 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4698 int me, int pipe, 4699 enum amdgpu_interrupt_state state) 4700 { 4701 u32 mec_int_cntl, mec_int_cntl_reg; 4702 4703 /* 4704 * amdgpu controls only the first MEC. That's why this function only 4705 * handles the setting of interrupts for this specific MEC. All other 4706 * pipes' interrupts are set by amdkfd. 4707 */ 4708 4709 if (me == 1) { 4710 switch (pipe) { 4711 case 0: 4712 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4713 break; 4714 case 1: 4715 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4716 break; 4717 default: 4718 DRM_DEBUG("invalid pipe %d\n", pipe); 4719 return; 4720 } 4721 } else { 4722 DRM_DEBUG("invalid me %d\n", me); 4723 return; 4724 } 4725 4726 switch (state) { 4727 case AMDGPU_IRQ_STATE_DISABLE: 4728 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4730 TIME_STAMP_INT_ENABLE, 0); 4731 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4732 GENERIC0_INT_ENABLE, 0); 4733 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4734 break; 4735 case AMDGPU_IRQ_STATE_ENABLE: 4736 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4737 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4738 TIME_STAMP_INT_ENABLE, 1); 4739 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4740 GENERIC0_INT_ENABLE, 1); 4741 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4742 break; 4743 default: 4744 break; 4745 } 4746 } 4747 4748 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4749 struct amdgpu_irq_src *src, 4750 unsigned type, 4751 enum amdgpu_interrupt_state state) 4752 { 4753 switch (type) { 4754 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4755 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4756 break; 4757 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4758 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4759 break; 4760 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4761 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4762 break; 4763 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4764 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4765 break; 4766 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4767 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4768 break; 4769 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4770 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4771 break; 4772 default: 4773 break; 4774 } 4775 return 0; 4776 } 4777 4778 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4779 struct amdgpu_irq_src *source, 4780 struct amdgpu_iv_entry *entry) 4781 { 4782 int i; 4783 u8 me_id, pipe_id, queue_id; 4784 struct amdgpu_ring *ring; 4785 uint32_t mes_queue_id = entry->src_data[0]; 4786 4787 DRM_DEBUG("IH: CP EOP\n"); 4788 4789 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4790 struct amdgpu_mes_queue *queue; 4791 4792 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4793 4794 spin_lock(&adev->mes.queue_id_lock); 4795 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4796 if (queue) { 4797 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4798 amdgpu_fence_process(queue->ring); 4799 } 4800 spin_unlock(&adev->mes.queue_id_lock); 4801 } else { 4802 me_id = (entry->ring_id & 0x0c) >> 2; 4803 pipe_id = (entry->ring_id & 0x03) >> 0; 4804 queue_id = (entry->ring_id & 0x70) >> 4; 4805 4806 switch (me_id) { 4807 case 0: 4808 if (pipe_id == 0) 4809 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4810 else 4811 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4812 break; 4813 case 1: 4814 case 2: 4815 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4816 ring = &adev->gfx.compute_ring[i]; 4817 /* Per-queue interrupt is supported for MEC starting from VI. 4818 * The interrupt can only be enabled/disabled per pipe instead 4819 * of per queue. 4820 */ 4821 if ((ring->me == me_id) && 4822 (ring->pipe == pipe_id) && 4823 (ring->queue == queue_id)) 4824 amdgpu_fence_process(ring); 4825 } 4826 break; 4827 } 4828 } 4829 4830 return 0; 4831 } 4832 4833 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4834 struct amdgpu_irq_src *source, 4835 unsigned int type, 4836 enum amdgpu_interrupt_state state) 4837 { 4838 u32 cp_int_cntl_reg, cp_int_cntl; 4839 int i, j; 4840 4841 switch (state) { 4842 case AMDGPU_IRQ_STATE_DISABLE: 4843 case AMDGPU_IRQ_STATE_ENABLE: 4844 for (i = 0; i < adev->gfx.me.num_me; i++) { 4845 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4846 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4847 4848 if (cp_int_cntl_reg) { 4849 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4850 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4851 PRIV_REG_INT_ENABLE, 4852 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4853 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4854 } 4855 } 4856 } 4857 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4858 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4859 /* MECs start at 1 */ 4860 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4861 4862 if (cp_int_cntl_reg) { 4863 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4864 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4865 PRIV_REG_INT_ENABLE, 4866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4867 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4868 } 4869 } 4870 } 4871 break; 4872 default: 4873 break; 4874 } 4875 4876 return 0; 4877 } 4878 4879 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4880 struct amdgpu_irq_src *source, 4881 unsigned type, 4882 enum amdgpu_interrupt_state state) 4883 { 4884 u32 cp_int_cntl_reg, cp_int_cntl; 4885 int i, j; 4886 4887 switch (state) { 4888 case AMDGPU_IRQ_STATE_DISABLE: 4889 case AMDGPU_IRQ_STATE_ENABLE: 4890 for (i = 0; i < adev->gfx.me.num_me; i++) { 4891 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4892 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4893 4894 if (cp_int_cntl_reg) { 4895 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4897 OPCODE_ERROR_INT_ENABLE, 4898 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4900 } 4901 } 4902 } 4903 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4904 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4905 /* MECs start at 1 */ 4906 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4907 4908 if (cp_int_cntl_reg) { 4909 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4910 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4911 OPCODE_ERROR_INT_ENABLE, 4912 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4913 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4914 } 4915 } 4916 } 4917 break; 4918 default: 4919 break; 4920 } 4921 return 0; 4922 } 4923 4924 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4925 struct amdgpu_irq_src *source, 4926 unsigned int type, 4927 enum amdgpu_interrupt_state state) 4928 { 4929 u32 cp_int_cntl_reg, cp_int_cntl; 4930 int i, j; 4931 4932 switch (state) { 4933 case AMDGPU_IRQ_STATE_DISABLE: 4934 case AMDGPU_IRQ_STATE_ENABLE: 4935 for (i = 0; i < adev->gfx.me.num_me; i++) { 4936 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4937 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4938 4939 if (cp_int_cntl_reg) { 4940 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4941 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4942 PRIV_INSTR_INT_ENABLE, 4943 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4944 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4945 } 4946 } 4947 } 4948 break; 4949 default: 4950 break; 4951 } 4952 4953 return 0; 4954 } 4955 4956 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4957 struct amdgpu_iv_entry *entry) 4958 { 4959 u8 me_id, pipe_id, queue_id; 4960 struct amdgpu_ring *ring; 4961 int i; 4962 4963 me_id = (entry->ring_id & 0x0c) >> 2; 4964 pipe_id = (entry->ring_id & 0x03) >> 0; 4965 queue_id = (entry->ring_id & 0x70) >> 4; 4966 4967 switch (me_id) { 4968 case 0: 4969 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4970 ring = &adev->gfx.gfx_ring[i]; 4971 if (ring->me == me_id && ring->pipe == pipe_id && 4972 ring->queue == queue_id) 4973 drm_sched_fault(&ring->sched); 4974 } 4975 break; 4976 case 1: 4977 case 2: 4978 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4979 ring = &adev->gfx.compute_ring[i]; 4980 if (ring->me == me_id && ring->pipe == pipe_id && 4981 ring->queue == queue_id) 4982 drm_sched_fault(&ring->sched); 4983 } 4984 break; 4985 default: 4986 BUG(); 4987 break; 4988 } 4989 } 4990 4991 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 4992 struct amdgpu_irq_src *source, 4993 struct amdgpu_iv_entry *entry) 4994 { 4995 DRM_ERROR("Illegal register access in command stream\n"); 4996 gfx_v12_0_handle_priv_fault(adev, entry); 4997 return 0; 4998 } 4999 5000 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5001 struct amdgpu_irq_src *source, 5002 struct amdgpu_iv_entry *entry) 5003 { 5004 DRM_ERROR("Illegal opcode in command stream \n"); 5005 gfx_v12_0_handle_priv_fault(adev, entry); 5006 return 0; 5007 } 5008 5009 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5010 struct amdgpu_irq_src *source, 5011 struct amdgpu_iv_entry *entry) 5012 { 5013 DRM_ERROR("Illegal instruction in command stream\n"); 5014 gfx_v12_0_handle_priv_fault(adev, entry); 5015 return 0; 5016 } 5017 5018 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5019 { 5020 const unsigned int gcr_cntl = 5021 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5022 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5023 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5024 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5025 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5026 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5027 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5028 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5029 5030 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5031 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5032 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5033 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5034 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5035 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5036 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5037 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5038 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5039 } 5040 5041 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5042 { 5043 /* Header itself is a NOP packet */ 5044 if (num_nop == 1) { 5045 amdgpu_ring_write(ring, ring->funcs->nop); 5046 return; 5047 } 5048 5049 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5050 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5051 5052 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5053 amdgpu_ring_insert_nop(ring, num_nop - 1); 5054 } 5055 5056 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5057 { 5058 /* Emit the cleaner shader */ 5059 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5060 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5061 } 5062 5063 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5064 { 5065 struct amdgpu_device *adev = ip_block->adev; 5066 uint32_t i, j, k, reg, index = 0; 5067 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5068 5069 if (!adev->gfx.ip_dump_core) 5070 return; 5071 5072 for (i = 0; i < reg_count; i++) 5073 drm_printf(p, "%-50s \t 0x%08x\n", 5074 gc_reg_list_12_0[i].reg_name, 5075 adev->gfx.ip_dump_core[i]); 5076 5077 /* print compute queue registers for all instances */ 5078 if (!adev->gfx.ip_dump_compute_queues) 5079 return; 5080 5081 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5082 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5083 adev->gfx.mec.num_mec, 5084 adev->gfx.mec.num_pipe_per_mec, 5085 adev->gfx.mec.num_queue_per_pipe); 5086 5087 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5088 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5089 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5090 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5091 for (reg = 0; reg < reg_count; reg++) { 5092 drm_printf(p, "%-50s \t 0x%08x\n", 5093 gc_cp_reg_list_12[reg].reg_name, 5094 adev->gfx.ip_dump_compute_queues[index + reg]); 5095 } 5096 index += reg_count; 5097 } 5098 } 5099 } 5100 5101 /* print gfx queue registers for all instances */ 5102 if (!adev->gfx.ip_dump_gfx_queues) 5103 return; 5104 5105 index = 0; 5106 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5107 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5108 adev->gfx.me.num_me, 5109 adev->gfx.me.num_pipe_per_me, 5110 adev->gfx.me.num_queue_per_pipe); 5111 5112 for (i = 0; i < adev->gfx.me.num_me; i++) { 5113 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5114 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5115 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5116 for (reg = 0; reg < reg_count; reg++) { 5117 drm_printf(p, "%-50s \t 0x%08x\n", 5118 gc_gfx_queue_reg_list_12[reg].reg_name, 5119 adev->gfx.ip_dump_gfx_queues[index + reg]); 5120 } 5121 index += reg_count; 5122 } 5123 } 5124 } 5125 } 5126 5127 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5128 { 5129 struct amdgpu_device *adev = ip_block->adev; 5130 uint32_t i, j, k, reg, index = 0; 5131 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5132 5133 if (!adev->gfx.ip_dump_core) 5134 return; 5135 5136 amdgpu_gfx_off_ctrl(adev, false); 5137 for (i = 0; i < reg_count; i++) 5138 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5139 amdgpu_gfx_off_ctrl(adev, true); 5140 5141 /* dump compute queue registers for all instances */ 5142 if (!adev->gfx.ip_dump_compute_queues) 5143 return; 5144 5145 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5146 amdgpu_gfx_off_ctrl(adev, false); 5147 mutex_lock(&adev->srbm_mutex); 5148 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5149 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5150 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5151 /* ME0 is for GFX so start from 1 for CP */ 5152 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5153 for (reg = 0; reg < reg_count; reg++) { 5154 adev->gfx.ip_dump_compute_queues[index + reg] = 5155 RREG32(SOC15_REG_ENTRY_OFFSET( 5156 gc_cp_reg_list_12[reg])); 5157 } 5158 index += reg_count; 5159 } 5160 } 5161 } 5162 soc24_grbm_select(adev, 0, 0, 0, 0); 5163 mutex_unlock(&adev->srbm_mutex); 5164 amdgpu_gfx_off_ctrl(adev, true); 5165 5166 /* dump gfx queue registers for all instances */ 5167 if (!adev->gfx.ip_dump_gfx_queues) 5168 return; 5169 5170 index = 0; 5171 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5172 amdgpu_gfx_off_ctrl(adev, false); 5173 mutex_lock(&adev->srbm_mutex); 5174 for (i = 0; i < adev->gfx.me.num_me; i++) { 5175 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5176 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5177 soc24_grbm_select(adev, i, j, k, 0); 5178 5179 for (reg = 0; reg < reg_count; reg++) { 5180 adev->gfx.ip_dump_gfx_queues[index + reg] = 5181 RREG32(SOC15_REG_ENTRY_OFFSET( 5182 gc_gfx_queue_reg_list_12[reg])); 5183 } 5184 index += reg_count; 5185 } 5186 } 5187 } 5188 soc24_grbm_select(adev, 0, 0, 0, 0); 5189 mutex_unlock(&adev->srbm_mutex); 5190 amdgpu_gfx_off_ctrl(adev, true); 5191 } 5192 5193 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5194 { 5195 struct amdgpu_device *adev = ring->adev; 5196 int r; 5197 5198 if (amdgpu_sriov_vf(adev)) 5199 return -EINVAL; 5200 5201 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5202 if (r) { 5203 dev_err(adev->dev, "reset via MES failed %d\n", r); 5204 return r; 5205 } 5206 5207 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5208 if (unlikely(r != 0)) { 5209 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5210 return r; 5211 } 5212 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5213 if (!r) { 5214 r = gfx_v12_0_kgq_init_queue(ring, true); 5215 amdgpu_bo_kunmap(ring->mqd_obj); 5216 ring->mqd_ptr = NULL; 5217 } 5218 amdgpu_bo_unreserve(ring->mqd_obj); 5219 if (r) { 5220 DRM_ERROR("fail to unresv mqd_obj\n"); 5221 return r; 5222 } 5223 5224 r = amdgpu_mes_map_legacy_queue(adev, ring); 5225 if (r) { 5226 dev_err(adev->dev, "failed to remap kgq\n"); 5227 return r; 5228 } 5229 5230 return amdgpu_ring_test_ring(ring); 5231 } 5232 5233 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5234 { 5235 struct amdgpu_device *adev = ring->adev; 5236 int r, i; 5237 5238 if (amdgpu_sriov_vf(adev)) 5239 return -EINVAL; 5240 5241 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5242 mutex_lock(&adev->srbm_mutex); 5243 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5244 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 5245 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 5246 for (i = 0; i < adev->usec_timeout; i++) { 5247 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 5248 break; 5249 udelay(1); 5250 } 5251 soc24_grbm_select(adev, 0, 0, 0, 0); 5252 mutex_unlock(&adev->srbm_mutex); 5253 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5254 5255 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5256 if (unlikely(r != 0)) { 5257 DRM_ERROR("fail to resv mqd_obj\n"); 5258 return r; 5259 } 5260 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5261 if (!r) { 5262 r = gfx_v12_0_kcq_init_queue(ring, true); 5263 amdgpu_bo_kunmap(ring->mqd_obj); 5264 ring->mqd_ptr = NULL; 5265 } 5266 amdgpu_bo_unreserve(ring->mqd_obj); 5267 if (r) { 5268 DRM_ERROR("fail to unresv mqd_obj\n"); 5269 return r; 5270 } 5271 r = amdgpu_mes_map_legacy_queue(adev, ring); 5272 if (r) { 5273 dev_err(adev->dev, "failed to remap kcq\n"); 5274 return r; 5275 } 5276 5277 return amdgpu_ring_test_ring(ring); 5278 } 5279 5280 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5281 .name = "gfx_v12_0", 5282 .early_init = gfx_v12_0_early_init, 5283 .late_init = gfx_v12_0_late_init, 5284 .sw_init = gfx_v12_0_sw_init, 5285 .sw_fini = gfx_v12_0_sw_fini, 5286 .hw_init = gfx_v12_0_hw_init, 5287 .hw_fini = gfx_v12_0_hw_fini, 5288 .suspend = gfx_v12_0_suspend, 5289 .resume = gfx_v12_0_resume, 5290 .is_idle = gfx_v12_0_is_idle, 5291 .wait_for_idle = gfx_v12_0_wait_for_idle, 5292 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5293 .set_powergating_state = gfx_v12_0_set_powergating_state, 5294 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5295 .dump_ip_state = gfx_v12_ip_dump, 5296 .print_ip_state = gfx_v12_ip_print, 5297 }; 5298 5299 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5300 .type = AMDGPU_RING_TYPE_GFX, 5301 .align_mask = 0xff, 5302 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5303 .support_64bit_ptrs = true, 5304 .secure_submission_supported = true, 5305 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5306 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5307 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5308 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5309 5 + /* COND_EXEC */ 5310 7 + /* PIPELINE_SYNC */ 5311 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5312 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5313 2 + /* VM_FLUSH */ 5314 8 + /* FENCE for VM_FLUSH */ 5315 5 + /* COND_EXEC */ 5316 7 + /* HDP_flush */ 5317 4 + /* VGT_flush */ 5318 31 + /* DE_META */ 5319 3 + /* CNTX_CTRL */ 5320 5 + /* HDP_INVL */ 5321 8 + 8 + /* FENCE x2 */ 5322 8 + /* gfx_v12_0_emit_mem_sync */ 5323 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5324 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5325 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5326 .emit_fence = gfx_v12_0_ring_emit_fence, 5327 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5328 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5329 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5330 .test_ring = gfx_v12_0_ring_test_ring, 5331 .test_ib = gfx_v12_0_ring_test_ib, 5332 .insert_nop = gfx_v12_ring_insert_nop, 5333 .pad_ib = amdgpu_ring_generic_pad_ib, 5334 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5335 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5336 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5337 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5338 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5339 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5340 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5341 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5342 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5343 .reset = gfx_v12_0_reset_kgq, 5344 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5345 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5346 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5347 }; 5348 5349 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5350 .type = AMDGPU_RING_TYPE_COMPUTE, 5351 .align_mask = 0xff, 5352 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5353 .support_64bit_ptrs = true, 5354 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5355 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5356 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5357 .emit_frame_size = 5358 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5359 5 + /* hdp invalidate */ 5360 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5361 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5362 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5363 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5364 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5365 8 + /* gfx_v12_0_emit_mem_sync */ 5366 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5367 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5368 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5369 .emit_fence = gfx_v12_0_ring_emit_fence, 5370 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5371 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5372 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5373 .test_ring = gfx_v12_0_ring_test_ring, 5374 .test_ib = gfx_v12_0_ring_test_ib, 5375 .insert_nop = gfx_v12_ring_insert_nop, 5376 .pad_ib = amdgpu_ring_generic_pad_ib, 5377 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5378 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5379 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5380 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5381 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5382 .reset = gfx_v12_0_reset_kcq, 5383 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5384 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 5385 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 5386 }; 5387 5388 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5389 .type = AMDGPU_RING_TYPE_KIQ, 5390 .align_mask = 0xff, 5391 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5392 .support_64bit_ptrs = true, 5393 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5394 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5395 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5396 .emit_frame_size = 5397 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5398 5 + /*hdp invalidate */ 5399 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5400 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5401 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5402 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5403 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5404 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5405 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5406 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5407 .test_ring = gfx_v12_0_ring_test_ring, 5408 .test_ib = gfx_v12_0_ring_test_ib, 5409 .insert_nop = amdgpu_ring_insert_nop, 5410 .pad_ib = amdgpu_ring_generic_pad_ib, 5411 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5412 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5413 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5414 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5415 }; 5416 5417 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5418 { 5419 int i; 5420 5421 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5422 5423 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5424 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5425 5426 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5427 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5428 } 5429 5430 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5431 .set = gfx_v12_0_set_eop_interrupt_state, 5432 .process = gfx_v12_0_eop_irq, 5433 }; 5434 5435 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5436 .set = gfx_v12_0_set_priv_reg_fault_state, 5437 .process = gfx_v12_0_priv_reg_irq, 5438 }; 5439 5440 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5441 .set = gfx_v12_0_set_bad_op_fault_state, 5442 .process = gfx_v12_0_bad_op_irq, 5443 }; 5444 5445 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5446 .set = gfx_v12_0_set_priv_inst_fault_state, 5447 .process = gfx_v12_0_priv_inst_irq, 5448 }; 5449 5450 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5451 { 5452 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5453 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5454 5455 adev->gfx.priv_reg_irq.num_types = 1; 5456 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5457 5458 adev->gfx.bad_op_irq.num_types = 1; 5459 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5460 5461 adev->gfx.priv_inst_irq.num_types = 1; 5462 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5463 } 5464 5465 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5466 { 5467 if (adev->flags & AMD_IS_APU) 5468 adev->gfx.imu.mode = MISSION_MODE; 5469 else 5470 adev->gfx.imu.mode = DEBUG_MODE; 5471 5472 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5473 } 5474 5475 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5476 { 5477 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5478 } 5479 5480 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5481 { 5482 /* set gfx eng mqd */ 5483 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5484 sizeof(struct v12_gfx_mqd); 5485 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5486 gfx_v12_0_gfx_mqd_init; 5487 /* set compute eng mqd */ 5488 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5489 sizeof(struct v12_compute_mqd); 5490 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5491 gfx_v12_0_compute_mqd_init; 5492 } 5493 5494 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5495 u32 bitmap) 5496 { 5497 u32 data; 5498 5499 if (!bitmap) 5500 return; 5501 5502 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5503 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5504 5505 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5506 } 5507 5508 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5509 { 5510 u32 data, wgp_bitmask; 5511 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5512 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5513 5514 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5515 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5516 5517 wgp_bitmask = 5518 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5519 5520 return (~data) & wgp_bitmask; 5521 } 5522 5523 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5524 { 5525 u32 wgp_idx, wgp_active_bitmap; 5526 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5527 5528 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5529 cu_active_bitmap = 0; 5530 5531 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5532 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5533 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5534 if (wgp_active_bitmap & (1 << wgp_idx)) 5535 cu_active_bitmap |= cu_bitmap_per_wgp; 5536 } 5537 5538 return cu_active_bitmap; 5539 } 5540 5541 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5542 struct amdgpu_cu_info *cu_info) 5543 { 5544 int i, j, k, counter, active_cu_number = 0; 5545 u32 mask, bitmap; 5546 unsigned disable_masks[8 * 2]; 5547 5548 if (!adev || !cu_info) 5549 return -EINVAL; 5550 5551 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5552 5553 mutex_lock(&adev->grbm_idx_mutex); 5554 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5555 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5556 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5557 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5558 continue; 5559 mask = 1; 5560 counter = 0; 5561 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5562 if (i < 8 && j < 2) 5563 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5564 adev, disable_masks[i * 2 + j]); 5565 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5566 5567 /** 5568 * GFX12 could support more than 4 SEs, while the bitmap 5569 * in cu_info struct is 4x4 and ioctl interface struct 5570 * drm_amdgpu_info_device should keep stable. 5571 * So we use last two columns of bitmap to store cu mask for 5572 * SEs 4 to 7, the layout of the bitmap is as below: 5573 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5574 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5575 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5576 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5577 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5578 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5579 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5580 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5581 */ 5582 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5583 5584 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5585 if (bitmap & mask) 5586 counter++; 5587 5588 mask <<= 1; 5589 } 5590 active_cu_number += counter; 5591 } 5592 } 5593 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5594 mutex_unlock(&adev->grbm_idx_mutex); 5595 5596 cu_info->number = active_cu_number; 5597 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5598 5599 return 0; 5600 } 5601 5602 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5603 .type = AMD_IP_BLOCK_TYPE_GFX, 5604 .major = 12, 5605 .minor = 0, 5606 .rev = 0, 5607 .funcs = &gfx_v12_0_ip_funcs, 5608 }; 5609