1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 83 84 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 120 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 121 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 124 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 138 /* cp header registers */ 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 /* SE status registers */ 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 152 }; 153 154 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 155 /* compute registers */ 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 195 /* cp header registers */ 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 }; 205 206 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 207 /* gfx queue registers */ 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 233 /* cp header registers */ 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 }; 251 252 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 256 }; 257 258 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 260 }; 261 262 #define DEFAULT_SH_MEM_CONFIG \ 263 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 264 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 265 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 266 267 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 268 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 273 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 274 struct amdgpu_cu_info *cu_info); 275 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 276 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 277 u32 sh_num, u32 instance, int xcc_id); 278 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 279 280 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 359 return; 360 } 361 362 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 363 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 364 PACKET3_UNMAP_QUEUES_ACTION(action) | 365 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 366 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 367 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 368 amdgpu_ring_write(kiq_ring, 369 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 370 371 if (action == PREEMPT_QUEUES_NO_UNMAP) { 372 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 373 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, seq); 375 } else { 376 amdgpu_ring_write(kiq_ring, 0); 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 } 380 } 381 382 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 383 struct amdgpu_ring *ring, 384 u64 addr, u64 seq) 385 { 386 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 387 388 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 389 amdgpu_ring_write(kiq_ring, 390 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 391 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 392 PACKET3_QUERY_STATUS_COMMAND(2)); 393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 394 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 395 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 396 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 397 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 400 } 401 402 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 403 uint16_t pasid, 404 uint32_t flush_type, 405 bool all_hub) 406 { 407 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 408 } 409 410 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 411 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 412 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 413 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 414 .kiq_query_status = gfx_v12_0_kiq_query_status, 415 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 416 .set_resources_size = 8, 417 .map_queues_size = 7, 418 .unmap_queues_size = 6, 419 .query_status_size = 7, 420 .invalidate_tlbs_size = 2, 421 }; 422 423 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 424 { 425 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 426 } 427 428 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 429 int mem_space, int opt, uint32_t addr0, 430 uint32_t addr1, uint32_t ref, 431 uint32_t mask, uint32_t inv) 432 { 433 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 434 amdgpu_ring_write(ring, 435 /* memory (1) or register (0) */ 436 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 437 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 438 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 439 WAIT_REG_MEM_ENGINE(eng_sel))); 440 441 if (mem_space) 442 BUG_ON(addr0 & 0x3); /* Dword align */ 443 amdgpu_ring_write(ring, addr0); 444 amdgpu_ring_write(ring, addr1); 445 amdgpu_ring_write(ring, ref); 446 amdgpu_ring_write(ring, mask); 447 amdgpu_ring_write(ring, inv); /* poll interval */ 448 } 449 450 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 454 uint32_t tmp = 0; 455 unsigned i; 456 int r; 457 458 WREG32(scratch, 0xCAFEDEAD); 459 r = amdgpu_ring_alloc(ring, 5); 460 if (r) { 461 dev_err(adev->dev, 462 "amdgpu: cp failed to lock ring %d (%d).\n", 463 ring->idx, r); 464 return r; 465 } 466 467 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 468 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 469 } else { 470 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 471 amdgpu_ring_write(ring, scratch - 472 PACKET3_SET_UCONFIG_REG_START); 473 amdgpu_ring_write(ring, 0xDEADBEEF); 474 } 475 amdgpu_ring_commit(ring); 476 477 for (i = 0; i < adev->usec_timeout; i++) { 478 tmp = RREG32(scratch); 479 if (tmp == 0xDEADBEEF) 480 break; 481 if (amdgpu_emu_mode == 1) 482 msleep(1); 483 else 484 udelay(1); 485 } 486 487 if (i >= adev->usec_timeout) 488 r = -ETIMEDOUT; 489 return r; 490 } 491 492 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 struct amdgpu_ib ib; 496 struct dma_fence *f = NULL; 497 unsigned index; 498 uint64_t gpu_addr; 499 volatile uint32_t *cpu_ptr; 500 long r; 501 502 /* MES KIQ fw hasn't indirect buffer support for now */ 503 if (adev->enable_mes_kiq && 504 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 505 return 0; 506 507 memset(&ib, 0, sizeof(ib)); 508 509 r = amdgpu_device_wb_get(adev, &index); 510 if (r) 511 return r; 512 513 gpu_addr = adev->wb.gpu_addr + (index * 4); 514 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 515 cpu_ptr = &adev->wb.wb[index]; 516 517 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 518 if (r) { 519 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 520 goto err1; 521 } 522 523 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 524 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 525 ib.ptr[2] = lower_32_bits(gpu_addr); 526 ib.ptr[3] = upper_32_bits(gpu_addr); 527 ib.ptr[4] = 0xDEADBEEF; 528 ib.length_dw = 5; 529 530 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 531 if (r) 532 goto err2; 533 534 r = dma_fence_wait_timeout(f, false, timeout); 535 if (r == 0) { 536 r = -ETIMEDOUT; 537 goto err2; 538 } else if (r < 0) { 539 goto err2; 540 } 541 542 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 543 r = 0; 544 else 545 r = -EINVAL; 546 err2: 547 amdgpu_ib_free(&ib, NULL); 548 dma_fence_put(f); 549 err1: 550 amdgpu_device_wb_free(adev, index); 551 return r; 552 } 553 554 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 555 { 556 amdgpu_ucode_release(&adev->gfx.pfp_fw); 557 amdgpu_ucode_release(&adev->gfx.me_fw); 558 amdgpu_ucode_release(&adev->gfx.rlc_fw); 559 amdgpu_ucode_release(&adev->gfx.mec_fw); 560 561 kfree(adev->gfx.rlc.register_list_format); 562 } 563 564 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 565 { 566 const struct psp_firmware_header_v1_0 *toc_hdr; 567 int err = 0; 568 569 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_toc.bin", ucode_prefix); 572 if (err) 573 goto out; 574 575 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 576 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 577 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 578 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 579 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 580 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 581 return 0; 582 out: 583 amdgpu_ucode_release(&adev->psp.toc_fw); 584 return err; 585 } 586 587 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int err; 591 const struct rlc_firmware_header_v2_0 *rlc_hdr; 592 uint16_t version_major; 593 uint16_t version_minor; 594 595 DRM_DEBUG("\n"); 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_pfp.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 606 607 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 608 AMDGPU_UCODE_REQUIRED, 609 "amdgpu/%s_me.bin", ucode_prefix); 610 if (err) 611 goto out; 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 614 615 if (!amdgpu_sriov_vf(adev)) { 616 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 617 AMDGPU_UCODE_REQUIRED, 618 "amdgpu/%s_rlc.bin", ucode_prefix); 619 if (err) 620 goto out; 621 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 622 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 623 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 624 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 625 if (err) 626 goto out; 627 } 628 629 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_mec.bin", ucode_prefix); 632 if (err) 633 goto out; 634 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 635 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 636 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 637 638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 639 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 640 641 /* only one MEC for gfx 12 */ 642 adev->gfx.mec2_fw = NULL; 643 644 if (adev->gfx.imu.funcs) { 645 if (adev->gfx.imu.funcs->init_microcode) { 646 err = adev->gfx.imu.funcs->init_microcode(adev); 647 if (err) 648 dev_err(adev->dev, "Failed to load imu firmware!\n"); 649 } 650 } 651 652 out: 653 if (err) { 654 amdgpu_ucode_release(&adev->gfx.pfp_fw); 655 amdgpu_ucode_release(&adev->gfx.me_fw); 656 amdgpu_ucode_release(&adev->gfx.rlc_fw); 657 amdgpu_ucode_release(&adev->gfx.mec_fw); 658 } 659 660 return err; 661 } 662 663 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 664 { 665 u32 count = 0; 666 const struct cs_section_def *sect = NULL; 667 const struct cs_extent_def *ext = NULL; 668 669 count += 1; 670 671 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 672 if (sect->id == SECT_CONTEXT) { 673 for (ext = sect->section; ext->extent != NULL; ++ext) 674 count += 2 + ext->reg_count; 675 } else 676 return 0; 677 } 678 679 return count; 680 } 681 682 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 683 volatile u32 *buffer) 684 { 685 u32 count = 0, clustercount = 0, i; 686 const struct cs_section_def *sect = NULL; 687 const struct cs_extent_def *ext = NULL; 688 689 if (adev->gfx.rlc.cs_data == NULL) 690 return; 691 if (buffer == NULL) 692 return; 693 694 count += 1; 695 696 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 697 if (sect->id == SECT_CONTEXT) { 698 for (ext = sect->section; ext->extent != NULL; ++ext) { 699 clustercount++; 700 buffer[count++] = ext->reg_count; 701 buffer[count++] = ext->reg_index; 702 703 for (i = 0; i < ext->reg_count; i++) 704 buffer[count++] = cpu_to_le32(ext->extent[i]); 705 } 706 } else 707 return; 708 } 709 710 buffer[0] = clustercount; 711 } 712 713 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 714 { 715 /* clear state block */ 716 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 717 &adev->gfx.rlc.clear_state_gpu_addr, 718 (void **)&adev->gfx.rlc.cs_ptr); 719 720 /* jump table block */ 721 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 722 &adev->gfx.rlc.cp_table_gpu_addr, 723 (void **)&adev->gfx.rlc.cp_table_ptr); 724 } 725 726 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 727 { 728 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 729 730 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 731 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 732 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 733 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 734 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 735 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 736 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 737 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 738 adev->gfx.rlc.rlcg_reg_access_supported = true; 739 } 740 741 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 742 { 743 const struct cs_section_def *cs_data; 744 int r; 745 746 adev->gfx.rlc.cs_data = gfx12_cs_data; 747 748 cs_data = adev->gfx.rlc.cs_data; 749 750 if (cs_data) { 751 /* init clear state block */ 752 r = amdgpu_gfx_rlc_init_csb(adev); 753 if (r) 754 return r; 755 } 756 757 /* init spm vmid with 0xf */ 758 if (adev->gfx.rlc.funcs->update_spm_vmid) 759 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 760 761 return 0; 762 } 763 764 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 765 { 766 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 767 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 768 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 769 } 770 771 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 772 { 773 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 774 775 amdgpu_gfx_graphics_queue_acquire(adev); 776 } 777 778 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 779 { 780 int r; 781 u32 *hpd; 782 size_t mec_hpd_size; 783 784 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 785 786 /* take ownership of the relevant compute queues */ 787 amdgpu_gfx_compute_queue_acquire(adev); 788 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 789 790 if (mec_hpd_size) { 791 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 792 AMDGPU_GEM_DOMAIN_GTT, 793 &adev->gfx.mec.hpd_eop_obj, 794 &adev->gfx.mec.hpd_eop_gpu_addr, 795 (void **)&hpd); 796 if (r) { 797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 798 gfx_v12_0_mec_fini(adev); 799 return r; 800 } 801 802 memset(hpd, 0, mec_hpd_size); 803 804 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 805 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 806 } 807 808 return 0; 809 } 810 811 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 812 { 813 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 814 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 815 (address << SQ_IND_INDEX__INDEX__SHIFT)); 816 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 817 } 818 819 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 820 uint32_t thread, uint32_t regno, 821 uint32_t num, uint32_t *out) 822 { 823 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 824 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 825 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 826 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 827 (SQ_IND_INDEX__AUTO_INCR_MASK)); 828 while (num--) 829 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 830 } 831 832 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 833 uint32_t xcc_id, 834 uint32_t simd, uint32_t wave, 835 uint32_t *dst, int *no_fields) 836 { 837 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 838 * field when performing a select_se_sh so it should be 839 * zero here */ 840 WARN_ON(simd != 0); 841 842 /* type 4 wave data */ 843 dst[(*no_fields)++] = 4; 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 867 } 868 869 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 870 uint32_t xcc_id, uint32_t simd, 871 uint32_t wave, uint32_t start, 872 uint32_t size, uint32_t *dst) 873 { 874 WARN_ON(simd != 0); 875 876 wave_read_regs( 877 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 878 dst); 879 } 880 881 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t thread, 884 uint32_t start, uint32_t size, 885 uint32_t *dst) 886 { 887 wave_read_regs( 888 adev, wave, thread, 889 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 890 } 891 892 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 893 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 894 { 895 soc24_grbm_select(adev, me, pipe, q, vm); 896 } 897 898 /* all sizes are in bytes */ 899 #define MQD_SHADOW_BASE_SIZE 73728 900 #define MQD_SHADOW_BASE_ALIGNMENT 256 901 #define MQD_FWWORKAREA_SIZE 484 902 #define MQD_FWWORKAREA_ALIGNMENT 256 903 904 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 905 struct amdgpu_gfx_shadow_info *shadow_info) 906 { 907 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 908 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 909 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 910 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 911 } 912 913 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 914 struct amdgpu_gfx_shadow_info *shadow_info, 915 bool skip_check) 916 { 917 if (adev->gfx.cp_gfx_shadow || skip_check) { 918 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 919 return 0; 920 } 921 922 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 923 return -EINVAL; 924 } 925 926 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 927 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 928 .select_se_sh = &gfx_v12_0_select_se_sh, 929 .read_wave_data = &gfx_v12_0_read_wave_data, 930 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 931 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 932 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 933 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 934 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 935 }; 936 937 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 938 { 939 940 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 941 case IP_VERSION(12, 0, 0): 942 case IP_VERSION(12, 0, 1): 943 adev->gfx.config.max_hw_contexts = 8; 944 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 945 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 946 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 947 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 948 break; 949 default: 950 BUG(); 951 break; 952 } 953 954 return 0; 955 } 956 957 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 958 int me, int pipe, int queue) 959 { 960 int r; 961 struct amdgpu_ring *ring; 962 unsigned int irq_type; 963 964 ring = &adev->gfx.gfx_ring[ring_id]; 965 966 ring->me = me; 967 ring->pipe = pipe; 968 ring->queue = queue; 969 970 ring->ring_obj = NULL; 971 ring->use_doorbell = true; 972 973 if (!ring_id) 974 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 975 else 976 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 977 ring->vm_hub = AMDGPU_GFXHUB(0); 978 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 979 980 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 981 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 if (r) 984 return r; 985 return 0; 986 } 987 988 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 989 int mec, int pipe, int queue) 990 { 991 int r; 992 unsigned irq_type; 993 struct amdgpu_ring *ring; 994 unsigned int hw_prio; 995 996 ring = &adev->gfx.compute_ring[ring_id]; 997 998 /* mec0 is me1 */ 999 ring->me = mec + 1; 1000 ring->pipe = pipe; 1001 ring->queue = queue; 1002 1003 ring->ring_obj = NULL; 1004 ring->use_doorbell = true; 1005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1007 + (ring_id * GFX12_MEC_HPD_SIZE); 1008 ring->vm_hub = AMDGPU_GFXHUB(0); 1009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1010 1011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1013 + ring->pipe; 1014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1015 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1017 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1018 hw_prio, NULL); 1019 if (r) 1020 return r; 1021 1022 return 0; 1023 } 1024 1025 static struct { 1026 SOC24_FIRMWARE_ID id; 1027 unsigned int offset; 1028 unsigned int size; 1029 unsigned int size_x16; 1030 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1031 1032 #define RLC_TOC_OFFSET_DWUNIT 8 1033 #define RLC_SIZE_MULTIPLE 1024 1034 #define RLC_TOC_UMF_SIZE_inM 23ULL 1035 #define RLC_TOC_FORMAT_API 165ULL 1036 1037 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1038 { 1039 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1040 1041 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1042 rlc_autoload_info[ucode->id].id = ucode->id; 1043 rlc_autoload_info[ucode->id].offset = 1044 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1045 rlc_autoload_info[ucode->id].size = 1046 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1047 ucode->size * 4; 1048 ucode++; 1049 } 1050 } 1051 1052 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1053 { 1054 uint32_t total_size = 0; 1055 SOC24_FIRMWARE_ID id; 1056 1057 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1058 1059 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1060 total_size += rlc_autoload_info[id].size; 1061 1062 /* In case the offset in rlc toc ucode is aligned */ 1063 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1064 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1065 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1066 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1067 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1068 1069 return total_size; 1070 } 1071 1072 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1073 { 1074 int r; 1075 uint32_t total_size; 1076 1077 total_size = gfx_v12_0_calc_toc_total_size(adev); 1078 1079 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1080 AMDGPU_GEM_DOMAIN_VRAM, 1081 &adev->gfx.rlc.rlc_autoload_bo, 1082 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1083 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1084 1085 if (r) { 1086 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1087 return r; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1094 SOC24_FIRMWARE_ID id, 1095 const void *fw_data, 1096 uint32_t fw_size) 1097 { 1098 uint32_t toc_offset; 1099 uint32_t toc_fw_size; 1100 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1101 1102 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1103 return; 1104 1105 toc_offset = rlc_autoload_info[id].offset; 1106 toc_fw_size = rlc_autoload_info[id].size; 1107 1108 if (fw_size == 0) 1109 fw_size = toc_fw_size; 1110 1111 if (fw_size > toc_fw_size) 1112 fw_size = toc_fw_size; 1113 1114 memcpy(ptr + toc_offset, fw_data, fw_size); 1115 1116 if (fw_size < toc_fw_size) 1117 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1118 } 1119 1120 static void 1121 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1122 { 1123 void *data; 1124 uint32_t size; 1125 uint32_t *toc_ptr; 1126 1127 data = adev->psp.toc.start_addr; 1128 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1129 1130 toc_ptr = (uint32_t *)data + size / 4 - 2; 1131 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1132 1133 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1134 data, size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1139 { 1140 const __le32 *fw_data; 1141 uint32_t fw_size; 1142 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1143 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1144 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1145 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1146 uint16_t version_major, version_minor; 1147 1148 /* pfp ucode */ 1149 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1150 adev->gfx.pfp_fw->data; 1151 /* instruction */ 1152 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1153 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1154 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1155 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1156 fw_data, fw_size); 1157 /* data */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1162 fw_data, fw_size); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1164 fw_data, fw_size); 1165 /* me ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.me_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1181 fw_data, fw_size); 1182 /* mec ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.mec_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1198 fw_data, fw_size); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1200 fw_data, fw_size); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1202 fw_data, fw_size); 1203 1204 /* rlc ucode */ 1205 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1206 adev->gfx.rlc_fw->data; 1207 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1208 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1209 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1210 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1211 fw_data, fw_size); 1212 1213 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1214 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1215 if (version_major == 2) { 1216 if (version_minor >= 1) { 1217 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1218 1219 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1220 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1221 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1222 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1223 fw_data, fw_size); 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1229 fw_data, fw_size); 1230 } 1231 if (version_minor >= 2) { 1232 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1233 1234 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1235 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1236 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1238 fw_data, fw_size); 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1244 fw_data, fw_size); 1245 } 1246 } 1247 } 1248 1249 static void 1250 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1251 { 1252 const __le32 *fw_data; 1253 uint32_t fw_size; 1254 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1255 1256 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1257 adev->sdma.instance[0].fw->data; 1258 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1259 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1260 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1261 1262 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1263 fw_data, fw_size); 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 unsigned fw_size; 1271 const struct mes_firmware_header_v1_0 *mes_hdr; 1272 int pipe, ucode_id, data_id; 1273 1274 for (pipe = 0; pipe < 2; pipe++) { 1275 if (pipe == 0) { 1276 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1277 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1278 } else { 1279 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1280 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1281 } 1282 1283 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1284 adev->mes.fw[pipe]->data; 1285 1286 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1287 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1288 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1289 1290 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1297 } 1298 } 1299 1300 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1301 { 1302 uint32_t rlc_g_offset, rlc_g_size; 1303 uint64_t gpu_addr; 1304 uint32_t data; 1305 1306 /* RLC autoload sequence 2: copy ucode */ 1307 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1308 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1309 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1310 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1311 1312 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1313 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1314 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1315 1316 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1317 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1318 1319 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1320 1321 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1322 /* RLC autoload sequence 3: load IMU fw */ 1323 if (adev->gfx.imu.funcs->load_microcode) 1324 adev->gfx.imu.funcs->load_microcode(adev); 1325 /* RLC autoload sequence 4 init IMU fw */ 1326 if (adev->gfx.imu.funcs->setup_imu) 1327 adev->gfx.imu.funcs->setup_imu(adev); 1328 if (adev->gfx.imu.funcs->start_imu) 1329 adev->gfx.imu.funcs->start_imu(adev); 1330 1331 /* RLC autoload sequence 5 disable gpa mode */ 1332 gfx_v12_0_disable_gpa_mode(adev); 1333 } else { 1334 /* unhalt rlc to start autoload without imu */ 1335 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1336 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1337 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1338 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1339 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1346 { 1347 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1348 uint32_t *ptr; 1349 uint32_t inst; 1350 1351 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1352 if (!ptr) { 1353 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1354 adev->gfx.ip_dump_core = NULL; 1355 } else { 1356 adev->gfx.ip_dump_core = ptr; 1357 } 1358 1359 /* Allocate memory for compute queue registers for all the instances */ 1360 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1361 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe; 1363 1364 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1365 if (!ptr) { 1366 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1367 adev->gfx.ip_dump_compute_queues = NULL; 1368 } else { 1369 adev->gfx.ip_dump_compute_queues = ptr; 1370 } 1371 1372 /* Allocate memory for gfx queue registers for all the instances */ 1373 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1374 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1375 adev->gfx.me.num_queue_per_pipe; 1376 1377 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1378 if (!ptr) { 1379 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1380 adev->gfx.ip_dump_gfx_queues = NULL; 1381 } else { 1382 adev->gfx.ip_dump_gfx_queues = ptr; 1383 } 1384 } 1385 1386 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1387 { 1388 int i, j, k, r, ring_id = 0; 1389 unsigned num_compute_rings; 1390 int xcc_id = 0; 1391 struct amdgpu_device *adev = ip_block->adev; 1392 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1393 1394 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1395 1396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1397 case IP_VERSION(12, 0, 0): 1398 case IP_VERSION(12, 0, 1): 1399 adev->gfx.me.num_me = 1; 1400 adev->gfx.me.num_pipe_per_me = 1; 1401 adev->gfx.me.num_queue_per_pipe = 8; 1402 adev->gfx.mec.num_mec = 1; 1403 adev->gfx.mec.num_pipe_per_mec = 2; 1404 adev->gfx.mec.num_queue_per_pipe = 4; 1405 break; 1406 default: 1407 adev->gfx.me.num_me = 1; 1408 adev->gfx.me.num_pipe_per_me = 1; 1409 adev->gfx.me.num_queue_per_pipe = 1; 1410 adev->gfx.mec.num_mec = 1; 1411 adev->gfx.mec.num_pipe_per_mec = 4; 1412 adev->gfx.mec.num_queue_per_pipe = 8; 1413 break; 1414 } 1415 1416 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1417 case IP_VERSION(12, 0, 0): 1418 case IP_VERSION(12, 0, 1): 1419 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ 1420 if (!adev->gfx.disable_uq && 1421 adev->gfx.me_fw_version >= 2780 && 1422 adev->gfx.pfp_fw_version >= 2840 && 1423 adev->gfx.mec_fw_version >= 3050 && 1424 adev->mes.fw_version[0] >= 123) { 1425 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1426 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1427 } 1428 #endif 1429 break; 1430 default: 1431 break; 1432 } 1433 1434 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1435 case IP_VERSION(12, 0, 0): 1436 case IP_VERSION(12, 0, 1): 1437 if (adev->gfx.me_fw_version >= 2480 && 1438 adev->gfx.pfp_fw_version >= 2530 && 1439 adev->gfx.mec_fw_version >= 2680 && 1440 adev->mes.fw_version[0] >= 100) 1441 adev->gfx.enable_cleaner_shader = true; 1442 break; 1443 default: 1444 adev->gfx.enable_cleaner_shader = false; 1445 break; 1446 } 1447 1448 if (adev->gfx.num_compute_rings) { 1449 /* recalculate compute rings to use based on hardware configuration */ 1450 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1451 adev->gfx.mec.num_queue_per_pipe) / 2; 1452 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1453 num_compute_rings); 1454 } 1455 1456 /* EOP Event */ 1457 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1458 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1459 &adev->gfx.eop_irq); 1460 if (r) 1461 return r; 1462 1463 /* Bad opcode Event */ 1464 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1465 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1466 &adev->gfx.bad_op_irq); 1467 if (r) 1468 return r; 1469 1470 /* Privileged reg */ 1471 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1472 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1473 &adev->gfx.priv_reg_irq); 1474 if (r) 1475 return r; 1476 1477 /* Privileged inst */ 1478 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1479 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1480 &adev->gfx.priv_inst_irq); 1481 if (r) 1482 return r; 1483 1484 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1485 1486 gfx_v12_0_me_init(adev); 1487 1488 r = gfx_v12_0_rlc_init(adev); 1489 if (r) { 1490 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1491 return r; 1492 } 1493 1494 r = gfx_v12_0_mec_init(adev); 1495 if (r) { 1496 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1497 return r; 1498 } 1499 1500 if (adev->gfx.num_gfx_rings) { 1501 /* set up the gfx ring */ 1502 for (i = 0; i < adev->gfx.me.num_me; i++) { 1503 for (j = 0; j < num_queue_per_pipe; j++) { 1504 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1505 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1506 continue; 1507 1508 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1509 i, k, j); 1510 if (r) 1511 return r; 1512 ring_id++; 1513 } 1514 } 1515 } 1516 } 1517 1518 if (adev->gfx.num_compute_rings) { 1519 ring_id = 0; 1520 /* set up the compute queues - allocate horizontally across pipes */ 1521 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1522 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1523 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1524 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1525 0, i, k, j)) 1526 continue; 1527 1528 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1529 i, k, j); 1530 if (r) 1531 return r; 1532 1533 ring_id++; 1534 } 1535 } 1536 } 1537 } 1538 1539 adev->gfx.gfx_supported_reset = 1540 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1541 adev->gfx.compute_supported_reset = 1542 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1543 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1544 case IP_VERSION(12, 0, 0): 1545 case IP_VERSION(12, 0, 1): 1546 if ((adev->gfx.me_fw_version >= 2660) && 1547 (adev->gfx.mec_fw_version >= 2920)) { 1548 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1549 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1550 } 1551 } 1552 1553 if (!adev->enable_mes_kiq) { 1554 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1555 if (r) { 1556 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1557 return r; 1558 } 1559 1560 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1561 if (r) 1562 return r; 1563 } 1564 1565 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1566 if (r) 1567 return r; 1568 1569 /* allocate visible FB for rlc auto-loading fw */ 1570 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1571 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1572 if (r) 1573 return r; 1574 } 1575 1576 r = gfx_v12_0_gpu_early_init(adev); 1577 if (r) 1578 return r; 1579 1580 gfx_v12_0_alloc_ip_dump(adev); 1581 1582 r = amdgpu_gfx_sysfs_init(adev); 1583 if (r) 1584 return r; 1585 1586 return 0; 1587 } 1588 1589 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1590 { 1591 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1592 &adev->gfx.pfp.pfp_fw_gpu_addr, 1593 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1594 1595 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1596 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1597 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1598 } 1599 1600 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1601 { 1602 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1603 &adev->gfx.me.me_fw_gpu_addr, 1604 (void **)&adev->gfx.me.me_fw_ptr); 1605 1606 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1607 &adev->gfx.me.me_fw_data_gpu_addr, 1608 (void **)&adev->gfx.me.me_fw_data_ptr); 1609 } 1610 1611 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1612 { 1613 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1614 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1615 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1616 } 1617 1618 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1619 { 1620 int i; 1621 struct amdgpu_device *adev = ip_block->adev; 1622 1623 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1624 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1625 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1626 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1627 1628 amdgpu_gfx_mqd_sw_fini(adev, 0); 1629 1630 if (!adev->enable_mes_kiq) { 1631 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1632 amdgpu_gfx_kiq_fini(adev, 0); 1633 } 1634 1635 gfx_v12_0_pfp_fini(adev); 1636 gfx_v12_0_me_fini(adev); 1637 gfx_v12_0_rlc_fini(adev); 1638 gfx_v12_0_mec_fini(adev); 1639 1640 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1641 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1642 1643 gfx_v12_0_free_microcode(adev); 1644 1645 amdgpu_gfx_sysfs_fini(adev); 1646 1647 kfree(adev->gfx.ip_dump_core); 1648 kfree(adev->gfx.ip_dump_compute_queues); 1649 kfree(adev->gfx.ip_dump_gfx_queues); 1650 1651 return 0; 1652 } 1653 1654 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1655 u32 sh_num, u32 instance, int xcc_id) 1656 { 1657 u32 data; 1658 1659 if (instance == 0xffffffff) 1660 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1661 INSTANCE_BROADCAST_WRITES, 1); 1662 else 1663 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1664 instance); 1665 1666 if (se_num == 0xffffffff) 1667 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1668 1); 1669 else 1670 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1671 1672 if (sh_num == 0xffffffff) 1673 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1674 1); 1675 else 1676 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1677 1678 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1679 } 1680 1681 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1682 { 1683 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1684 1685 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1686 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1687 GRBM_CC_GC_SA_UNIT_DISABLE, 1688 SA_DISABLE); 1689 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1690 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1691 GRBM_GC_USER_SA_UNIT_DISABLE, 1692 SA_DISABLE); 1693 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1694 adev->gfx.config.max_shader_engines); 1695 1696 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1697 } 1698 1699 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1700 { 1701 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1702 u32 rb_mask; 1703 1704 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1705 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1706 CC_RB_BACKEND_DISABLE, 1707 BACKEND_DISABLE); 1708 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1709 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1710 GC_USER_RB_BACKEND_DISABLE, 1711 BACKEND_DISABLE); 1712 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1713 adev->gfx.config.max_shader_engines); 1714 1715 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1716 } 1717 1718 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1719 { 1720 u32 rb_bitmap_per_sa; 1721 u32 rb_bitmap_width_per_sa; 1722 u32 max_sa; 1723 u32 active_sa_bitmap; 1724 u32 global_active_rb_bitmap; 1725 u32 active_rb_bitmap = 0; 1726 u32 i; 1727 1728 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1729 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1730 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1731 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1732 1733 /* generate active rb bitmap according to active sa bitmap */ 1734 max_sa = adev->gfx.config.max_shader_engines * 1735 adev->gfx.config.max_sh_per_se; 1736 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1737 adev->gfx.config.max_sh_per_se; 1738 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1739 1740 for (i = 0; i < max_sa; i++) { 1741 if (active_sa_bitmap & (1 << i)) 1742 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1743 } 1744 1745 active_rb_bitmap &= global_active_rb_bitmap; 1746 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1747 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1748 } 1749 1750 #define LDS_APP_BASE 0x1 1751 #define SCRATCH_APP_BASE 0x2 1752 1753 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1754 { 1755 int i; 1756 uint32_t sh_mem_bases; 1757 uint32_t data; 1758 1759 /* 1760 * Configure apertures: 1761 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1762 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1763 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1764 */ 1765 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1766 SCRATCH_APP_BASE; 1767 1768 mutex_lock(&adev->srbm_mutex); 1769 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1770 soc24_grbm_select(adev, 0, 0, 0, i); 1771 /* CP and shaders */ 1772 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1773 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1774 1775 /* Enable trap for each kfd vmid. */ 1776 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1777 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1778 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1779 } 1780 soc24_grbm_select(adev, 0, 0, 0, 0); 1781 mutex_unlock(&adev->srbm_mutex); 1782 } 1783 1784 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1785 { 1786 /* TODO: harvest feature to be added later. */ 1787 } 1788 1789 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1790 { 1791 } 1792 1793 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1794 { 1795 u32 tmp; 1796 int i; 1797 1798 if (!amdgpu_sriov_vf(adev)) 1799 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1800 1801 gfx_v12_0_setup_rb(adev); 1802 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1803 gfx_v12_0_get_tcc_info(adev); 1804 adev->gfx.config.pa_sc_tile_steering_override = 0; 1805 1806 /* XXX SH_MEM regs */ 1807 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1808 mutex_lock(&adev->srbm_mutex); 1809 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1810 soc24_grbm_select(adev, 0, 0, 0, i); 1811 /* CP and shaders */ 1812 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1813 if (i != 0) { 1814 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1815 (adev->gmc.private_aperture_start >> 48)); 1816 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1817 (adev->gmc.shared_aperture_start >> 48)); 1818 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1819 } 1820 } 1821 soc24_grbm_select(adev, 0, 0, 0, 0); 1822 1823 mutex_unlock(&adev->srbm_mutex); 1824 1825 gfx_v12_0_init_compute_vmid(adev); 1826 } 1827 1828 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1829 int me, int pipe) 1830 { 1831 if (me != 0) 1832 return 0; 1833 1834 switch (pipe) { 1835 case 0: 1836 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1837 default: 1838 return 0; 1839 } 1840 } 1841 1842 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1843 int me, int pipe) 1844 { 1845 /* 1846 * amdgpu controls only the first MEC. That's why this function only 1847 * handles the setting of interrupts for this specific MEC. All other 1848 * pipes' interrupts are set by amdkfd. 1849 */ 1850 if (me != 1) 1851 return 0; 1852 1853 switch (pipe) { 1854 case 0: 1855 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1856 case 1: 1857 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1858 default: 1859 return 0; 1860 } 1861 } 1862 1863 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1864 bool enable) 1865 { 1866 u32 tmp, cp_int_cntl_reg; 1867 int i, j; 1868 1869 if (amdgpu_sriov_vf(adev)) 1870 return; 1871 1872 for (i = 0; i < adev->gfx.me.num_me; i++) { 1873 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1874 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1875 1876 if (cp_int_cntl_reg) { 1877 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1878 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1879 enable ? 1 : 0); 1880 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1881 enable ? 1 : 0); 1882 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1883 enable ? 1 : 0); 1884 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1885 enable ? 1 : 0); 1886 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1887 } 1888 } 1889 } 1890 } 1891 1892 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1893 { 1894 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1895 1896 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1897 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1898 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1899 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1900 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1901 1902 return 0; 1903 } 1904 1905 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1906 { 1907 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1908 1909 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1910 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1911 } 1912 1913 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1914 { 1915 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1916 udelay(50); 1917 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1918 udelay(50); 1919 } 1920 1921 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1922 bool enable) 1923 { 1924 uint32_t rlc_pg_cntl; 1925 1926 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1927 1928 if (!enable) { 1929 /* RLC_PG_CNTL[23] = 0 (default) 1930 * RLC will wait for handshake acks with SMU 1931 * GFXOFF will be enabled 1932 * RLC_PG_CNTL[23] = 1 1933 * RLC will not issue any message to SMU 1934 * hence no handshake between SMU & RLC 1935 * GFXOFF will be disabled 1936 */ 1937 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1938 } else 1939 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1940 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1941 } 1942 1943 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1944 { 1945 /* TODO: enable rlc & smu handshake until smu 1946 * and gfxoff feature works as expected */ 1947 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1948 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1949 1950 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1951 udelay(50); 1952 } 1953 1954 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1955 { 1956 uint32_t tmp; 1957 1958 /* enable Save Restore Machine */ 1959 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1960 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1961 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1962 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1963 } 1964 1965 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1966 { 1967 const struct rlc_firmware_header_v2_0 *hdr; 1968 const __le32 *fw_data; 1969 unsigned i, fw_size; 1970 1971 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1972 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1973 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1974 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1975 1976 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1977 RLCG_UCODE_LOADING_START_ADDRESS); 1978 1979 for (i = 0; i < fw_size; i++) 1980 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1981 le32_to_cpup(fw_data++)); 1982 1983 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1984 } 1985 1986 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1987 { 1988 const struct rlc_firmware_header_v2_2 *hdr; 1989 const __le32 *fw_data; 1990 unsigned i, fw_size; 1991 u32 tmp; 1992 1993 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1994 1995 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1996 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1997 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1998 1999 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2000 2001 for (i = 0; i < fw_size; i++) { 2002 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2003 msleep(1); 2004 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2005 le32_to_cpup(fw_data++)); 2006 } 2007 2008 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2009 2010 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2011 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2012 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2013 2014 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2015 for (i = 0; i < fw_size; i++) { 2016 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2017 msleep(1); 2018 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2019 le32_to_cpup(fw_data++)); 2020 } 2021 2022 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2023 2024 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2025 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2026 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2027 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2028 } 2029 2030 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2031 { 2032 const struct rlc_firmware_header_v2_0 *hdr; 2033 uint16_t version_major; 2034 uint16_t version_minor; 2035 2036 if (!adev->gfx.rlc_fw) 2037 return -EINVAL; 2038 2039 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2040 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2041 2042 version_major = le16_to_cpu(hdr->header.header_version_major); 2043 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2044 2045 if (version_major == 2) { 2046 gfx_v12_0_load_rlcg_microcode(adev); 2047 if (amdgpu_dpm == 1) { 2048 if (version_minor >= 2) 2049 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2050 } 2051 2052 return 0; 2053 } 2054 2055 return -EINVAL; 2056 } 2057 2058 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2059 { 2060 int r; 2061 2062 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2063 gfx_v12_0_init_csb(adev); 2064 2065 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2066 gfx_v12_0_rlc_enable_srm(adev); 2067 } else { 2068 if (amdgpu_sriov_vf(adev)) { 2069 gfx_v12_0_init_csb(adev); 2070 return 0; 2071 } 2072 2073 adev->gfx.rlc.funcs->stop(adev); 2074 2075 /* disable CG */ 2076 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2077 2078 /* disable PG */ 2079 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2080 2081 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2082 /* legacy rlc firmware loading */ 2083 r = gfx_v12_0_rlc_load_microcode(adev); 2084 if (r) 2085 return r; 2086 } 2087 2088 gfx_v12_0_init_csb(adev); 2089 2090 adev->gfx.rlc.funcs->start(adev); 2091 } 2092 2093 return 0; 2094 } 2095 2096 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2097 { 2098 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2099 const struct gfx_firmware_header_v2_0 *me_hdr; 2100 const struct gfx_firmware_header_v2_0 *mec_hdr; 2101 uint32_t pipe_id, tmp; 2102 2103 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2104 adev->gfx.mec_fw->data; 2105 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2106 adev->gfx.me_fw->data; 2107 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2108 adev->gfx.pfp_fw->data; 2109 2110 /* config pfp program start addr */ 2111 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2112 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2113 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2114 (pfp_hdr->ucode_start_addr_hi << 30) | 2115 (pfp_hdr->ucode_start_addr_lo >> 2)); 2116 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2117 pfp_hdr->ucode_start_addr_hi >> 2); 2118 } 2119 soc24_grbm_select(adev, 0, 0, 0, 0); 2120 2121 /* reset pfp pipe */ 2122 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2123 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2124 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2125 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2126 2127 /* clear pfp pipe reset */ 2128 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2129 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2130 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2131 2132 /* config me program start addr */ 2133 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2134 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2135 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2136 (me_hdr->ucode_start_addr_hi << 30) | 2137 (me_hdr->ucode_start_addr_lo >> 2)); 2138 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2139 me_hdr->ucode_start_addr_hi>>2); 2140 } 2141 soc24_grbm_select(adev, 0, 0, 0, 0); 2142 2143 /* reset me pipe */ 2144 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2145 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2146 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2147 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2148 2149 /* clear me pipe reset */ 2150 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2151 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2152 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2153 2154 /* config mec program start addr */ 2155 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2156 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2157 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2158 mec_hdr->ucode_start_addr_lo >> 2 | 2159 mec_hdr->ucode_start_addr_hi << 30); 2160 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2161 mec_hdr->ucode_start_addr_hi >> 2); 2162 } 2163 soc24_grbm_select(adev, 0, 0, 0, 0); 2164 2165 /* reset mec pipe */ 2166 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2167 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2168 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2169 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2170 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2171 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2172 2173 /* clear mec pipe reset */ 2174 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2178 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2179 } 2180 2181 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2182 { 2183 const struct gfx_firmware_header_v2_0 *cp_hdr; 2184 unsigned pipe_id, tmp; 2185 2186 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2187 adev->gfx.pfp_fw->data; 2188 mutex_lock(&adev->srbm_mutex); 2189 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2190 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2191 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2192 (cp_hdr->ucode_start_addr_hi << 30) | 2193 (cp_hdr->ucode_start_addr_lo >> 2)); 2194 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2195 cp_hdr->ucode_start_addr_hi>>2); 2196 2197 /* 2198 * Program CP_ME_CNTL to reset given PIPE to take 2199 * effect of CP_PFP_PRGRM_CNTR_START. 2200 */ 2201 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2202 if (pipe_id == 0) 2203 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2204 PFP_PIPE0_RESET, 1); 2205 else 2206 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2207 PFP_PIPE1_RESET, 1); 2208 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2209 2210 /* Clear pfp pipe0 reset bit. */ 2211 if (pipe_id == 0) 2212 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2213 PFP_PIPE0_RESET, 0); 2214 else 2215 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2216 PFP_PIPE1_RESET, 0); 2217 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2218 } 2219 soc24_grbm_select(adev, 0, 0, 0, 0); 2220 mutex_unlock(&adev->srbm_mutex); 2221 } 2222 2223 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2224 { 2225 const struct gfx_firmware_header_v2_0 *cp_hdr; 2226 unsigned pipe_id, tmp; 2227 2228 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2229 adev->gfx.me_fw->data; 2230 mutex_lock(&adev->srbm_mutex); 2231 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2232 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2233 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2234 (cp_hdr->ucode_start_addr_hi << 30) | 2235 (cp_hdr->ucode_start_addr_lo >> 2) ); 2236 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2237 cp_hdr->ucode_start_addr_hi>>2); 2238 2239 /* 2240 * Program CP_ME_CNTL to reset given PIPE to take 2241 * effect of CP_ME_PRGRM_CNTR_START. 2242 */ 2243 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2244 if (pipe_id == 0) 2245 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2246 ME_PIPE0_RESET, 1); 2247 else 2248 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2249 ME_PIPE1_RESET, 1); 2250 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2251 2252 /* Clear pfp pipe0 reset bit. */ 2253 if (pipe_id == 0) 2254 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2255 ME_PIPE0_RESET, 0); 2256 else 2257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2258 ME_PIPE1_RESET, 0); 2259 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2260 } 2261 soc24_grbm_select(adev, 0, 0, 0, 0); 2262 mutex_unlock(&adev->srbm_mutex); 2263 } 2264 2265 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2266 { 2267 const struct gfx_firmware_header_v2_0 *cp_hdr; 2268 unsigned pipe_id; 2269 2270 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2271 adev->gfx.mec_fw->data; 2272 mutex_lock(&adev->srbm_mutex); 2273 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2274 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2275 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2276 cp_hdr->ucode_start_addr_lo >> 2 | 2277 cp_hdr->ucode_start_addr_hi << 30); 2278 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2279 cp_hdr->ucode_start_addr_hi >> 2); 2280 } 2281 soc24_grbm_select(adev, 0, 0, 0, 0); 2282 mutex_unlock(&adev->srbm_mutex); 2283 } 2284 2285 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2286 { 2287 uint32_t cp_status; 2288 uint32_t bootload_status; 2289 int i; 2290 2291 for (i = 0; i < adev->usec_timeout; i++) { 2292 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2293 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2294 2295 if ((cp_status == 0) && 2296 (REG_GET_FIELD(bootload_status, 2297 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2298 break; 2299 } 2300 udelay(1); 2301 if (amdgpu_emu_mode) 2302 msleep(10); 2303 } 2304 2305 if (i >= adev->usec_timeout) { 2306 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2307 return -ETIMEDOUT; 2308 } 2309 2310 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2311 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2312 gfx_v12_0_set_me_ucode_start_addr(adev); 2313 gfx_v12_0_set_mec_ucode_start_addr(adev); 2314 } 2315 2316 return 0; 2317 } 2318 2319 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2320 { 2321 int i; 2322 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2323 2324 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2325 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2326 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2327 2328 for (i = 0; i < adev->usec_timeout; i++) { 2329 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2330 break; 2331 udelay(1); 2332 } 2333 2334 if (i >= adev->usec_timeout) 2335 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2336 2337 return 0; 2338 } 2339 2340 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2341 { 2342 int r; 2343 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2344 const __le32 *fw_ucode, *fw_data; 2345 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2346 uint32_t tmp; 2347 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2348 2349 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2350 adev->gfx.pfp_fw->data; 2351 2352 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2353 2354 /* instruction */ 2355 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2356 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2357 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2358 /* data */ 2359 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2360 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2361 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2362 2363 /* 64kb align */ 2364 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2365 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2366 &adev->gfx.pfp.pfp_fw_obj, 2367 &adev->gfx.pfp.pfp_fw_gpu_addr, 2368 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2369 if (r) { 2370 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2371 gfx_v12_0_pfp_fini(adev); 2372 return r; 2373 } 2374 2375 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2376 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2377 &adev->gfx.pfp.pfp_fw_data_obj, 2378 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2379 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2380 if (r) { 2381 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2382 gfx_v12_0_pfp_fini(adev); 2383 return r; 2384 } 2385 2386 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2387 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2388 2389 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2390 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2391 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2392 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2393 2394 if (amdgpu_emu_mode == 1) 2395 amdgpu_device_flush_hdp(adev, NULL); 2396 2397 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2398 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2399 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2400 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2401 2402 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2403 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2404 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2405 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2406 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2407 2408 /* 2409 * Programming any of the CP_PFP_IC_BASE registers 2410 * forces invalidation of the ME L1 I$. Wait for the 2411 * invalidation complete 2412 */ 2413 for (i = 0; i < usec_timeout; i++) { 2414 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2415 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2416 INVALIDATE_CACHE_COMPLETE)) 2417 break; 2418 udelay(1); 2419 } 2420 2421 if (i >= usec_timeout) { 2422 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2423 return -EINVAL; 2424 } 2425 2426 /* Prime the L1 instruction caches */ 2427 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2428 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2429 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2430 /* Waiting for cache primed*/ 2431 for (i = 0; i < usec_timeout; i++) { 2432 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2433 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2434 ICACHE_PRIMED)) 2435 break; 2436 udelay(1); 2437 } 2438 2439 if (i >= usec_timeout) { 2440 dev_err(adev->dev, "failed to prime instruction cache\n"); 2441 return -EINVAL; 2442 } 2443 2444 mutex_lock(&adev->srbm_mutex); 2445 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2446 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2447 2448 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2449 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2450 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2451 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2452 } 2453 soc24_grbm_select(adev, 0, 0, 0, 0); 2454 mutex_unlock(&adev->srbm_mutex); 2455 2456 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2457 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2458 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2459 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2460 2461 /* Invalidate the data caches */ 2462 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2463 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2464 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2465 2466 for (i = 0; i < usec_timeout; i++) { 2467 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2468 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2469 INVALIDATE_DCACHE_COMPLETE)) 2470 break; 2471 udelay(1); 2472 } 2473 2474 if (i >= usec_timeout) { 2475 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2476 return -EINVAL; 2477 } 2478 2479 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2480 2481 return 0; 2482 } 2483 2484 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2485 { 2486 int r; 2487 const struct gfx_firmware_header_v2_0 *me_hdr; 2488 const __le32 *fw_ucode, *fw_data; 2489 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2490 uint32_t tmp; 2491 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2492 2493 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2494 adev->gfx.me_fw->data; 2495 2496 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2497 2498 /* instruction */ 2499 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2500 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2501 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2502 /* data */ 2503 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2504 le32_to_cpu(me_hdr->data_offset_bytes)); 2505 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2506 2507 /* 64kb align*/ 2508 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2509 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2510 &adev->gfx.me.me_fw_obj, 2511 &adev->gfx.me.me_fw_gpu_addr, 2512 (void **)&adev->gfx.me.me_fw_ptr); 2513 if (r) { 2514 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2515 gfx_v12_0_me_fini(adev); 2516 return r; 2517 } 2518 2519 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2520 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2521 &adev->gfx.me.me_fw_data_obj, 2522 &adev->gfx.me.me_fw_data_gpu_addr, 2523 (void **)&adev->gfx.me.me_fw_data_ptr); 2524 if (r) { 2525 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2526 gfx_v12_0_me_fini(adev); 2527 return r; 2528 } 2529 2530 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2531 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2532 2533 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2534 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2535 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2536 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2537 2538 if (amdgpu_emu_mode == 1) 2539 amdgpu_device_flush_hdp(adev, NULL); 2540 2541 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2542 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2543 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2544 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2545 2546 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2547 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2548 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2549 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2550 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2551 2552 /* 2553 * Programming any of the CP_ME_IC_BASE registers 2554 * forces invalidation of the ME L1 I$. Wait for the 2555 * invalidation complete 2556 */ 2557 for (i = 0; i < usec_timeout; i++) { 2558 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2559 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2560 INVALIDATE_CACHE_COMPLETE)) 2561 break; 2562 udelay(1); 2563 } 2564 2565 if (i >= usec_timeout) { 2566 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2567 return -EINVAL; 2568 } 2569 2570 /* Prime the instruction caches */ 2571 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2572 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2573 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2574 2575 /* Waiting for instruction cache primed*/ 2576 for (i = 0; i < usec_timeout; i++) { 2577 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2578 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2579 ICACHE_PRIMED)) 2580 break; 2581 udelay(1); 2582 } 2583 2584 if (i >= usec_timeout) { 2585 dev_err(adev->dev, "failed to prime instruction cache\n"); 2586 return -EINVAL; 2587 } 2588 2589 mutex_lock(&adev->srbm_mutex); 2590 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2591 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2592 2593 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2594 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2595 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2596 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2597 } 2598 soc24_grbm_select(adev, 0, 0, 0, 0); 2599 mutex_unlock(&adev->srbm_mutex); 2600 2601 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2602 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2603 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2604 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2605 2606 /* Invalidate the data caches */ 2607 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2608 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2609 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2610 2611 for (i = 0; i < usec_timeout; i++) { 2612 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2613 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2614 INVALIDATE_DCACHE_COMPLETE)) 2615 break; 2616 udelay(1); 2617 } 2618 2619 if (i >= usec_timeout) { 2620 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2621 return -EINVAL; 2622 } 2623 2624 gfx_v12_0_set_me_ucode_start_addr(adev); 2625 2626 return 0; 2627 } 2628 2629 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2630 { 2631 int r; 2632 2633 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2634 return -EINVAL; 2635 2636 gfx_v12_0_cp_gfx_enable(adev, false); 2637 2638 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2639 if (r) { 2640 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2641 return r; 2642 } 2643 2644 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2645 if (r) { 2646 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2647 return r; 2648 } 2649 2650 return 0; 2651 } 2652 2653 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2654 { 2655 /* init the CP */ 2656 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2657 adev->gfx.config.max_hw_contexts - 1); 2658 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2659 2660 if (!amdgpu_async_gfx_ring) 2661 gfx_v12_0_cp_gfx_enable(adev, true); 2662 2663 return 0; 2664 } 2665 2666 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2667 CP_PIPE_ID pipe) 2668 { 2669 u32 tmp; 2670 2671 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2672 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2673 2674 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2675 } 2676 2677 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2678 struct amdgpu_ring *ring) 2679 { 2680 u32 tmp; 2681 2682 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2683 if (ring->use_doorbell) { 2684 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2685 DOORBELL_OFFSET, ring->doorbell_index); 2686 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2687 DOORBELL_EN, 1); 2688 } else { 2689 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2690 DOORBELL_EN, 0); 2691 } 2692 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2693 2694 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2695 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2696 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2697 2698 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2699 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2700 } 2701 2702 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2703 { 2704 struct amdgpu_ring *ring; 2705 u32 tmp; 2706 u32 rb_bufsz; 2707 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2708 2709 /* Set the write pointer delay */ 2710 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2711 2712 /* set the RB to use vmid 0 */ 2713 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2714 2715 /* Init gfx ring 0 for pipe 0 */ 2716 mutex_lock(&adev->srbm_mutex); 2717 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2718 2719 /* Set ring buffer size */ 2720 ring = &adev->gfx.gfx_ring[0]; 2721 rb_bufsz = order_base_2(ring->ring_size / 8); 2722 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2723 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2724 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2725 2726 /* Initialize the ring buffer's write pointers */ 2727 ring->wptr = 0; 2728 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2729 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2730 2731 /* set the wb address whether it's enabled or not */ 2732 rptr_addr = ring->rptr_gpu_addr; 2733 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2734 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2735 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2736 2737 wptr_gpu_addr = ring->wptr_gpu_addr; 2738 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2739 lower_32_bits(wptr_gpu_addr)); 2740 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2741 upper_32_bits(wptr_gpu_addr)); 2742 2743 mdelay(1); 2744 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2745 2746 rb_addr = ring->gpu_addr >> 8; 2747 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2748 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2749 2750 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2751 2752 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2753 mutex_unlock(&adev->srbm_mutex); 2754 2755 /* Switch to pipe 0 */ 2756 mutex_lock(&adev->srbm_mutex); 2757 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2758 mutex_unlock(&adev->srbm_mutex); 2759 2760 /* start the ring */ 2761 gfx_v12_0_cp_gfx_start(adev); 2762 return 0; 2763 } 2764 2765 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2766 { 2767 u32 data; 2768 2769 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2770 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2771 enable ? 0 : 1); 2772 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2773 enable ? 0 : 1); 2774 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2775 enable ? 0 : 1); 2776 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2777 enable ? 0 : 1); 2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2779 enable ? 0 : 1); 2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2781 enable ? 1 : 0); 2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2783 enable ? 1 : 0); 2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2785 enable ? 1 : 0); 2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2787 enable ? 1 : 0); 2788 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2789 enable ? 0 : 1); 2790 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2791 2792 adev->gfx.kiq[0].ring.sched.ready = enable; 2793 2794 udelay(50); 2795 } 2796 2797 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2798 { 2799 const struct gfx_firmware_header_v2_0 *mec_hdr; 2800 const __le32 *fw_ucode, *fw_data; 2801 u32 tmp, fw_ucode_size, fw_data_size; 2802 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2803 u32 *fw_ucode_ptr, *fw_data_ptr; 2804 int r; 2805 2806 if (!adev->gfx.mec_fw) 2807 return -EINVAL; 2808 2809 gfx_v12_0_cp_compute_enable(adev, false); 2810 2811 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2812 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2813 2814 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2815 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2816 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2817 2818 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2819 le32_to_cpu(mec_hdr->data_offset_bytes)); 2820 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2821 2822 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2823 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2824 &adev->gfx.mec.mec_fw_obj, 2825 &adev->gfx.mec.mec_fw_gpu_addr, 2826 (void **)&fw_ucode_ptr); 2827 if (r) { 2828 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2829 gfx_v12_0_mec_fini(adev); 2830 return r; 2831 } 2832 2833 r = amdgpu_bo_create_reserved(adev, 2834 ALIGN(fw_data_size, 64 * 1024) * 2835 adev->gfx.mec.num_pipe_per_mec, 2836 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2837 &adev->gfx.mec.mec_fw_data_obj, 2838 &adev->gfx.mec.mec_fw_data_gpu_addr, 2839 (void **)&fw_data_ptr); 2840 if (r) { 2841 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2842 gfx_v12_0_mec_fini(adev); 2843 return r; 2844 } 2845 2846 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2847 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2848 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2849 } 2850 2851 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2852 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2853 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2854 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2855 2856 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2857 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2858 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2859 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2860 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2861 2862 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2863 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2864 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2865 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2866 2867 mutex_lock(&adev->srbm_mutex); 2868 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2869 soc24_grbm_select(adev, 1, i, 0, 0); 2870 2871 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2872 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2873 i * ALIGN(fw_data_size, 64 * 1024))); 2874 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2875 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2876 i * ALIGN(fw_data_size, 64 * 1024))); 2877 2878 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2879 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2880 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2881 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2882 } 2883 mutex_unlock(&adev->srbm_mutex); 2884 soc24_grbm_select(adev, 0, 0, 0, 0); 2885 2886 /* Trigger an invalidation of the L1 instruction caches */ 2887 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2888 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2889 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2890 2891 /* Wait for invalidation complete */ 2892 for (i = 0; i < usec_timeout; i++) { 2893 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2894 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2895 INVALIDATE_DCACHE_COMPLETE)) 2896 break; 2897 udelay(1); 2898 } 2899 2900 if (i >= usec_timeout) { 2901 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2902 return -EINVAL; 2903 } 2904 2905 /* Trigger an invalidation of the L1 instruction caches */ 2906 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2907 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2908 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2909 2910 /* Wait for invalidation complete */ 2911 for (i = 0; i < usec_timeout; i++) { 2912 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2913 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2914 INVALIDATE_CACHE_COMPLETE)) 2915 break; 2916 udelay(1); 2917 } 2918 2919 if (i >= usec_timeout) { 2920 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2921 return -EINVAL; 2922 } 2923 2924 gfx_v12_0_set_mec_ucode_start_addr(adev); 2925 2926 return 0; 2927 } 2928 2929 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2930 { 2931 uint32_t tmp; 2932 struct amdgpu_device *adev = ring->adev; 2933 2934 /* tell RLC which is KIQ queue */ 2935 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2936 tmp &= 0xffffff00; 2937 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2938 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2939 } 2940 2941 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2942 { 2943 /* set graphics engine doorbell range */ 2944 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2945 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2946 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2947 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2948 2949 /* set compute engine doorbell range */ 2950 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2951 (adev->doorbell_index.kiq * 2) << 2); 2952 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2953 (adev->doorbell_index.userqueue_end * 2) << 2); 2954 } 2955 2956 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2957 struct amdgpu_mqd_prop *prop) 2958 { 2959 struct v12_gfx_mqd *mqd = m; 2960 uint64_t hqd_gpu_addr, wb_gpu_addr; 2961 uint32_t tmp; 2962 uint32_t rb_bufsz; 2963 2964 /* set up gfx hqd wptr */ 2965 mqd->cp_gfx_hqd_wptr = 0; 2966 mqd->cp_gfx_hqd_wptr_hi = 0; 2967 2968 /* set the pointer to the MQD */ 2969 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2970 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2971 2972 /* set up mqd control */ 2973 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2974 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2975 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2976 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2977 mqd->cp_gfx_mqd_control = tmp; 2978 2979 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2980 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2981 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2982 mqd->cp_gfx_hqd_vmid = 0; 2983 2984 /* set up default queue priority level 2985 * 0x0 = low priority, 0x1 = high priority */ 2986 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2987 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2988 mqd->cp_gfx_hqd_queue_priority = tmp; 2989 2990 /* set up time quantum */ 2991 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2992 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2993 mqd->cp_gfx_hqd_quantum = tmp; 2994 2995 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2996 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2997 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2998 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2999 3000 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3001 wb_gpu_addr = prop->rptr_gpu_addr; 3002 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3003 mqd->cp_gfx_hqd_rptr_addr_hi = 3004 upper_32_bits(wb_gpu_addr) & 0xffff; 3005 3006 /* set up rb_wptr_poll addr */ 3007 wb_gpu_addr = prop->wptr_gpu_addr; 3008 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3009 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3010 3011 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3012 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3013 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3014 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3015 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3016 #ifdef __BIG_ENDIAN 3017 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3018 #endif 3019 if (prop->tmz_queue) 3020 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3021 mqd->cp_gfx_hqd_cntl = tmp; 3022 3023 /* set up cp_doorbell_control */ 3024 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3025 if (prop->use_doorbell) { 3026 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3027 DOORBELL_OFFSET, prop->doorbell_index); 3028 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3029 DOORBELL_EN, 1); 3030 } else 3031 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3032 DOORBELL_EN, 0); 3033 mqd->cp_rb_doorbell_control = tmp; 3034 3035 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3036 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3037 3038 /* active the queue */ 3039 mqd->cp_gfx_hqd_active = 1; 3040 3041 /* set gfx UQ items */ 3042 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3043 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3044 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3045 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3046 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3047 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3048 3049 return 0; 3050 } 3051 3052 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3053 { 3054 struct amdgpu_device *adev = ring->adev; 3055 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3056 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3057 3058 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3059 memset((void *)mqd, 0, sizeof(*mqd)); 3060 mutex_lock(&adev->srbm_mutex); 3061 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3062 amdgpu_ring_init_mqd(ring); 3063 soc24_grbm_select(adev, 0, 0, 0, 0); 3064 mutex_unlock(&adev->srbm_mutex); 3065 if (adev->gfx.me.mqd_backup[mqd_idx]) 3066 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3067 } else { 3068 /* restore mqd with the backup copy */ 3069 if (adev->gfx.me.mqd_backup[mqd_idx]) 3070 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3071 /* reset the ring */ 3072 ring->wptr = 0; 3073 *ring->wptr_cpu_addr = 0; 3074 amdgpu_ring_clear_ring(ring); 3075 } 3076 3077 return 0; 3078 } 3079 3080 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3081 { 3082 int i, r; 3083 3084 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3085 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3086 if (r) 3087 return r; 3088 } 3089 3090 r = amdgpu_gfx_enable_kgq(adev, 0); 3091 if (r) 3092 return r; 3093 3094 return gfx_v12_0_cp_gfx_start(adev); 3095 } 3096 3097 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3098 struct amdgpu_mqd_prop *prop) 3099 { 3100 struct v12_compute_mqd *mqd = m; 3101 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3102 uint32_t tmp; 3103 3104 mqd->header = 0xC0310800; 3105 mqd->compute_pipelinestat_enable = 0x00000001; 3106 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3107 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3108 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3109 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3110 mqd->compute_misc_reserved = 0x00000007; 3111 3112 eop_base_addr = prop->eop_gpu_addr >> 8; 3113 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3114 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3115 3116 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3117 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3118 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3119 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3120 3121 mqd->cp_hqd_eop_control = tmp; 3122 3123 /* enable doorbell? */ 3124 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3125 3126 if (prop->use_doorbell) { 3127 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3128 DOORBELL_OFFSET, prop->doorbell_index); 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3130 DOORBELL_EN, 1); 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_SOURCE, 0); 3133 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3134 DOORBELL_HIT, 0); 3135 } else { 3136 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3137 DOORBELL_EN, 0); 3138 } 3139 3140 mqd->cp_hqd_pq_doorbell_control = tmp; 3141 3142 /* disable the queue if it's active */ 3143 mqd->cp_hqd_dequeue_request = 0; 3144 mqd->cp_hqd_pq_rptr = 0; 3145 mqd->cp_hqd_pq_wptr_lo = 0; 3146 mqd->cp_hqd_pq_wptr_hi = 0; 3147 3148 /* set the pointer to the MQD */ 3149 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3150 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3151 3152 /* set MQD vmid to 0 */ 3153 tmp = regCP_MQD_CONTROL_DEFAULT; 3154 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3155 mqd->cp_mqd_control = tmp; 3156 3157 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3158 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3159 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3160 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3161 3162 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3163 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3165 (order_base_2(prop->queue_size / 4) - 1)); 3166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3167 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3168 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3169 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3170 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3171 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3172 if (prop->tmz_queue) 3173 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3174 mqd->cp_hqd_pq_control = tmp; 3175 3176 /* set the wb address whether it's enabled or not */ 3177 wb_gpu_addr = prop->rptr_gpu_addr; 3178 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3179 mqd->cp_hqd_pq_rptr_report_addr_hi = 3180 upper_32_bits(wb_gpu_addr) & 0xffff; 3181 3182 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3183 wb_gpu_addr = prop->wptr_gpu_addr; 3184 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3185 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3186 3187 tmp = 0; 3188 /* enable the doorbell if requested */ 3189 if (prop->use_doorbell) { 3190 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3192 DOORBELL_OFFSET, prop->doorbell_index); 3193 3194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3195 DOORBELL_EN, 1); 3196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3197 DOORBELL_SOURCE, 0); 3198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3199 DOORBELL_HIT, 0); 3200 } 3201 3202 mqd->cp_hqd_pq_doorbell_control = tmp; 3203 3204 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3205 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3206 3207 /* set the vmid for the queue */ 3208 mqd->cp_hqd_vmid = 0; 3209 3210 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3211 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3212 mqd->cp_hqd_persistent_state = tmp; 3213 3214 /* set MIN_IB_AVAIL_SIZE */ 3215 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3216 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3217 mqd->cp_hqd_ib_control = tmp; 3218 3219 /* set static priority for a compute queue/ring */ 3220 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3221 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3222 3223 mqd->cp_hqd_active = prop->hqd_active; 3224 3225 /* set UQ fenceaddress */ 3226 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3227 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3228 3229 return 0; 3230 } 3231 3232 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3233 { 3234 struct amdgpu_device *adev = ring->adev; 3235 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3236 int j; 3237 3238 /* inactivate the queue */ 3239 if (amdgpu_sriov_vf(adev)) 3240 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3241 3242 /* disable wptr polling */ 3243 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3244 3245 /* write the EOP addr */ 3246 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3247 mqd->cp_hqd_eop_base_addr_lo); 3248 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3249 mqd->cp_hqd_eop_base_addr_hi); 3250 3251 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3252 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3253 mqd->cp_hqd_eop_control); 3254 3255 /* enable doorbell? */ 3256 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3257 mqd->cp_hqd_pq_doorbell_control); 3258 3259 /* disable the queue if it's active */ 3260 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3261 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3262 for (j = 0; j < adev->usec_timeout; j++) { 3263 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3264 break; 3265 udelay(1); 3266 } 3267 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3268 mqd->cp_hqd_dequeue_request); 3269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3270 mqd->cp_hqd_pq_rptr); 3271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3272 mqd->cp_hqd_pq_wptr_lo); 3273 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3274 mqd->cp_hqd_pq_wptr_hi); 3275 } 3276 3277 /* set the pointer to the MQD */ 3278 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3279 mqd->cp_mqd_base_addr_lo); 3280 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3281 mqd->cp_mqd_base_addr_hi); 3282 3283 /* set MQD vmid to 0 */ 3284 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3285 mqd->cp_mqd_control); 3286 3287 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3288 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3289 mqd->cp_hqd_pq_base_lo); 3290 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3291 mqd->cp_hqd_pq_base_hi); 3292 3293 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3294 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3295 mqd->cp_hqd_pq_control); 3296 3297 /* set the wb address whether it's enabled or not */ 3298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3299 mqd->cp_hqd_pq_rptr_report_addr_lo); 3300 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3301 mqd->cp_hqd_pq_rptr_report_addr_hi); 3302 3303 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3304 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3305 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3307 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3308 3309 /* enable the doorbell if requested */ 3310 if (ring->use_doorbell) { 3311 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3312 (adev->doorbell_index.kiq * 2) << 2); 3313 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3314 (adev->doorbell_index.userqueue_end * 2) << 2); 3315 } 3316 3317 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3318 mqd->cp_hqd_pq_doorbell_control); 3319 3320 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3321 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3322 mqd->cp_hqd_pq_wptr_lo); 3323 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3324 mqd->cp_hqd_pq_wptr_hi); 3325 3326 /* set the vmid for the queue */ 3327 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3328 3329 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3330 mqd->cp_hqd_persistent_state); 3331 3332 /* activate the queue */ 3333 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3334 mqd->cp_hqd_active); 3335 3336 if (ring->use_doorbell) 3337 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3338 3339 return 0; 3340 } 3341 3342 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3343 { 3344 struct amdgpu_device *adev = ring->adev; 3345 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3346 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3347 3348 gfx_v12_0_kiq_setting(ring); 3349 3350 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3351 /* reset MQD to a clean status */ 3352 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3353 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3354 3355 /* reset ring buffer */ 3356 ring->wptr = 0; 3357 amdgpu_ring_clear_ring(ring); 3358 3359 mutex_lock(&adev->srbm_mutex); 3360 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3361 gfx_v12_0_kiq_init_register(ring); 3362 soc24_grbm_select(adev, 0, 0, 0, 0); 3363 mutex_unlock(&adev->srbm_mutex); 3364 } else { 3365 memset((void *)mqd, 0, sizeof(*mqd)); 3366 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3367 amdgpu_ring_clear_ring(ring); 3368 mutex_lock(&adev->srbm_mutex); 3369 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3370 amdgpu_ring_init_mqd(ring); 3371 gfx_v12_0_kiq_init_register(ring); 3372 soc24_grbm_select(adev, 0, 0, 0, 0); 3373 mutex_unlock(&adev->srbm_mutex); 3374 3375 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3376 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3377 } 3378 3379 return 0; 3380 } 3381 3382 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3383 { 3384 struct amdgpu_device *adev = ring->adev; 3385 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3386 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3387 3388 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3389 memset((void *)mqd, 0, sizeof(*mqd)); 3390 mutex_lock(&adev->srbm_mutex); 3391 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3392 amdgpu_ring_init_mqd(ring); 3393 soc24_grbm_select(adev, 0, 0, 0, 0); 3394 mutex_unlock(&adev->srbm_mutex); 3395 3396 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3397 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3398 } else { 3399 /* restore MQD to a clean status */ 3400 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3401 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3402 /* reset ring buffer */ 3403 ring->wptr = 0; 3404 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3405 amdgpu_ring_clear_ring(ring); 3406 } 3407 3408 return 0; 3409 } 3410 3411 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3412 { 3413 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3414 adev->gfx.kiq[0].ring.sched.ready = true; 3415 return 0; 3416 } 3417 3418 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3419 { 3420 int i, r; 3421 3422 if (!amdgpu_async_gfx_ring) 3423 gfx_v12_0_cp_compute_enable(adev, true); 3424 3425 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3426 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3427 if (r) 3428 return r; 3429 } 3430 3431 return amdgpu_gfx_enable_kcq(adev, 0); 3432 } 3433 3434 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3435 { 3436 int r, i; 3437 struct amdgpu_ring *ring; 3438 3439 if (!(adev->flags & AMD_IS_APU)) 3440 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3441 3442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3443 /* legacy firmware loading */ 3444 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3445 if (r) 3446 return r; 3447 3448 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3449 if (r) 3450 return r; 3451 } 3452 3453 gfx_v12_0_cp_set_doorbell_range(adev); 3454 3455 if (amdgpu_async_gfx_ring) { 3456 gfx_v12_0_cp_compute_enable(adev, true); 3457 gfx_v12_0_cp_gfx_enable(adev, true); 3458 } 3459 3460 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3461 r = amdgpu_mes_kiq_hw_init(adev); 3462 else 3463 r = gfx_v12_0_kiq_resume(adev); 3464 if (r) 3465 return r; 3466 3467 r = gfx_v12_0_kcq_resume(adev); 3468 if (r) 3469 return r; 3470 3471 if (!amdgpu_async_gfx_ring) { 3472 r = gfx_v12_0_cp_gfx_resume(adev); 3473 if (r) 3474 return r; 3475 } else { 3476 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3477 if (r) 3478 return r; 3479 } 3480 3481 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3482 ring = &adev->gfx.gfx_ring[i]; 3483 r = amdgpu_ring_test_helper(ring); 3484 if (r) 3485 return r; 3486 } 3487 3488 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3489 ring = &adev->gfx.compute_ring[i]; 3490 r = amdgpu_ring_test_helper(ring); 3491 if (r) 3492 return r; 3493 } 3494 3495 return 0; 3496 } 3497 3498 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3499 { 3500 gfx_v12_0_cp_gfx_enable(adev, enable); 3501 gfx_v12_0_cp_compute_enable(adev, enable); 3502 } 3503 3504 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3505 { 3506 int r; 3507 bool value; 3508 3509 r = adev->gfxhub.funcs->gart_enable(adev); 3510 if (r) 3511 return r; 3512 3513 amdgpu_device_flush_hdp(adev, NULL); 3514 3515 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3516 false : true; 3517 3518 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3519 /* TODO investigate why this and the hdp flush above is needed, 3520 * are we missing a flush somewhere else? */ 3521 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3522 3523 return 0; 3524 } 3525 3526 static int get_gb_addr_config(struct amdgpu_device *adev) 3527 { 3528 u32 gb_addr_config; 3529 3530 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3531 if (gb_addr_config == 0) 3532 return -EINVAL; 3533 3534 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3535 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3536 3537 adev->gfx.config.gb_addr_config = gb_addr_config; 3538 3539 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3540 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3541 GB_ADDR_CONFIG, NUM_PIPES); 3542 3543 adev->gfx.config.max_tile_pipes = 3544 adev->gfx.config.gb_addr_config_fields.num_pipes; 3545 3546 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3547 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3548 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3549 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3550 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3551 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3552 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3553 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3554 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3555 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3556 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3557 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3558 3559 return 0; 3560 } 3561 3562 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3563 { 3564 uint32_t data; 3565 3566 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3567 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3568 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3569 3570 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3571 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3572 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3573 } 3574 3575 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3576 { 3577 if (amdgpu_sriov_vf(adev)) 3578 return; 3579 3580 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3581 case IP_VERSION(12, 0, 0): 3582 case IP_VERSION(12, 0, 1): 3583 soc15_program_register_sequence(adev, 3584 golden_settings_gc_12_0, 3585 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3586 3587 if (adev->rev_id == 0) 3588 soc15_program_register_sequence(adev, 3589 golden_settings_gc_12_0_rev0, 3590 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3591 break; 3592 default: 3593 break; 3594 } 3595 } 3596 3597 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3598 { 3599 int r; 3600 struct amdgpu_device *adev = ip_block->adev; 3601 3602 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3603 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3604 /* RLC autoload sequence 1: Program rlc ram */ 3605 if (adev->gfx.imu.funcs->program_rlc_ram) 3606 adev->gfx.imu.funcs->program_rlc_ram(adev); 3607 } 3608 /* rlc autoload firmware */ 3609 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3610 if (r) 3611 return r; 3612 } else { 3613 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3614 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3615 if (adev->gfx.imu.funcs->load_microcode) 3616 adev->gfx.imu.funcs->load_microcode(adev); 3617 if (adev->gfx.imu.funcs->setup_imu) 3618 adev->gfx.imu.funcs->setup_imu(adev); 3619 if (adev->gfx.imu.funcs->start_imu) 3620 adev->gfx.imu.funcs->start_imu(adev); 3621 } 3622 3623 /* disable gpa mode in backdoor loading */ 3624 gfx_v12_0_disable_gpa_mode(adev); 3625 } 3626 } 3627 3628 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3629 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3630 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3631 if (r) { 3632 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3633 return r; 3634 } 3635 } 3636 3637 if (!amdgpu_emu_mode) 3638 gfx_v12_0_init_golden_registers(adev); 3639 3640 adev->gfx.is_poweron = true; 3641 3642 if (get_gb_addr_config(adev)) 3643 DRM_WARN("Invalid gb_addr_config !\n"); 3644 3645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3646 gfx_v12_0_config_gfx_rs64(adev); 3647 3648 r = gfx_v12_0_gfxhub_enable(adev); 3649 if (r) 3650 return r; 3651 3652 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3653 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3654 (amdgpu_dpm == 1)) { 3655 /** 3656 * For gfx 12, rlc firmware loading relies on smu firmware is 3657 * loaded firstly, so in direct type, it has to load smc ucode 3658 * here before rlc. 3659 */ 3660 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3661 if (r) 3662 return r; 3663 } 3664 3665 gfx_v12_0_constants_init(adev); 3666 3667 if (adev->nbio.funcs->gc_doorbell_init) 3668 adev->nbio.funcs->gc_doorbell_init(adev); 3669 3670 r = gfx_v12_0_rlc_resume(adev); 3671 if (r) 3672 return r; 3673 3674 /* 3675 * init golden registers and rlc resume may override some registers, 3676 * reconfig them here 3677 */ 3678 gfx_v12_0_tcp_harvest(adev); 3679 3680 r = gfx_v12_0_cp_resume(adev); 3681 if (r) 3682 return r; 3683 3684 return r; 3685 } 3686 3687 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3688 bool enable) 3689 { 3690 unsigned int irq_type; 3691 int m, p, r; 3692 3693 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3694 for (m = 0; m < adev->gfx.me.num_me; m++) { 3695 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3696 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3697 if (enable) 3698 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3699 irq_type); 3700 else 3701 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3702 irq_type); 3703 if (r) 3704 return r; 3705 } 3706 } 3707 } 3708 3709 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3710 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3711 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3712 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3713 + (m * adev->gfx.mec.num_pipe_per_mec) 3714 + p; 3715 if (enable) 3716 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3717 irq_type); 3718 else 3719 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3720 irq_type); 3721 if (r) 3722 return r; 3723 } 3724 } 3725 } 3726 3727 return 0; 3728 } 3729 3730 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3731 { 3732 struct amdgpu_device *adev = ip_block->adev; 3733 uint32_t tmp; 3734 3735 cancel_delayed_work_sync(&adev->gfx.idle_work); 3736 3737 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3738 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3739 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3740 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3741 3742 if (!adev->no_hw_access) { 3743 if (amdgpu_async_gfx_ring) { 3744 if (amdgpu_gfx_disable_kgq(adev, 0)) 3745 DRM_ERROR("KGQ disable failed\n"); 3746 } 3747 3748 if (amdgpu_gfx_disable_kcq(adev, 0)) 3749 DRM_ERROR("KCQ disable failed\n"); 3750 3751 amdgpu_mes_kiq_hw_fini(adev); 3752 } 3753 3754 if (amdgpu_sriov_vf(adev)) { 3755 gfx_v12_0_cp_gfx_enable(adev, false); 3756 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3757 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3758 tmp &= 0xffffff00; 3759 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3760 3761 return 0; 3762 } 3763 gfx_v12_0_cp_enable(adev, false); 3764 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3765 3766 adev->gfxhub.funcs->gart_disable(adev); 3767 3768 adev->gfx.is_poweron = false; 3769 3770 return 0; 3771 } 3772 3773 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3774 { 3775 return gfx_v12_0_hw_fini(ip_block); 3776 } 3777 3778 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3779 { 3780 return gfx_v12_0_hw_init(ip_block); 3781 } 3782 3783 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3784 { 3785 struct amdgpu_device *adev = ip_block->adev; 3786 3787 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3788 GRBM_STATUS, GUI_ACTIVE)) 3789 return false; 3790 else 3791 return true; 3792 } 3793 3794 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3795 { 3796 unsigned i; 3797 u32 tmp; 3798 struct amdgpu_device *adev = ip_block->adev; 3799 3800 for (i = 0; i < adev->usec_timeout; i++) { 3801 /* read MC_STATUS */ 3802 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3803 GRBM_STATUS__GUI_ACTIVE_MASK; 3804 3805 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3806 return 0; 3807 udelay(1); 3808 } 3809 return -ETIMEDOUT; 3810 } 3811 3812 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3813 { 3814 uint64_t clock = 0; 3815 3816 if (adev->smuio.funcs && 3817 adev->smuio.funcs->get_gpu_clock_counter) 3818 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3819 else 3820 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3821 3822 return clock; 3823 } 3824 3825 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3826 { 3827 struct amdgpu_device *adev = ip_block->adev; 3828 3829 switch (amdgpu_user_queue) { 3830 case -1: 3831 case 0: 3832 default: 3833 adev->gfx.disable_kq = false; 3834 adev->gfx.disable_uq = true; 3835 break; 3836 case 1: 3837 adev->gfx.disable_kq = false; 3838 adev->gfx.disable_uq = false; 3839 break; 3840 case 2: 3841 adev->gfx.disable_kq = true; 3842 adev->gfx.disable_uq = false; 3843 break; 3844 } 3845 3846 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3847 3848 if (adev->gfx.disable_kq) { 3849 adev->gfx.num_gfx_rings = 0; 3850 adev->gfx.num_compute_rings = 0; 3851 } else { 3852 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3853 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3854 AMDGPU_MAX_COMPUTE_RINGS); 3855 } 3856 3857 gfx_v12_0_set_kiq_pm4_funcs(adev); 3858 gfx_v12_0_set_ring_funcs(adev); 3859 gfx_v12_0_set_irq_funcs(adev); 3860 gfx_v12_0_set_rlc_funcs(adev); 3861 gfx_v12_0_set_mqd_funcs(adev); 3862 gfx_v12_0_set_imu_funcs(adev); 3863 3864 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3865 3866 return gfx_v12_0_init_microcode(adev); 3867 } 3868 3869 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3870 { 3871 struct amdgpu_device *adev = ip_block->adev; 3872 int r; 3873 3874 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3875 if (r) 3876 return r; 3877 3878 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3879 if (r) 3880 return r; 3881 3882 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3883 if (r) 3884 return r; 3885 3886 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3887 if (r) 3888 return r; 3889 3890 return 0; 3891 } 3892 3893 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3894 { 3895 uint32_t rlc_cntl; 3896 3897 /* if RLC is not enabled, do nothing */ 3898 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3899 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3900 } 3901 3902 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3903 int xcc_id) 3904 { 3905 uint32_t data; 3906 unsigned i; 3907 3908 data = RLC_SAFE_MODE__CMD_MASK; 3909 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3910 3911 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3912 3913 /* wait for RLC_SAFE_MODE */ 3914 for (i = 0; i < adev->usec_timeout; i++) { 3915 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3916 RLC_SAFE_MODE, CMD)) 3917 break; 3918 udelay(1); 3919 } 3920 } 3921 3922 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3923 int xcc_id) 3924 { 3925 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3926 } 3927 3928 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3929 bool enable) 3930 { 3931 uint32_t def, data; 3932 3933 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3934 return; 3935 3936 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3937 3938 if (enable) 3939 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3940 else 3941 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3942 3943 if (def != data) 3944 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3945 } 3946 3947 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3948 struct amdgpu_ring *ring, 3949 unsigned vmid) 3950 { 3951 u32 reg, data; 3952 3953 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3954 if (amdgpu_sriov_is_pp_one_vf(adev)) 3955 data = RREG32_NO_KIQ(reg); 3956 else 3957 data = RREG32(reg); 3958 3959 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3960 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3961 3962 if (amdgpu_sriov_is_pp_one_vf(adev)) 3963 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3964 else 3965 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3966 3967 if (ring 3968 && amdgpu_sriov_is_pp_one_vf(adev) 3969 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3970 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3971 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3972 amdgpu_ring_emit_wreg(ring, reg, data); 3973 } 3974 } 3975 3976 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3977 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3978 .set_safe_mode = gfx_v12_0_set_safe_mode, 3979 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3980 .init = gfx_v12_0_rlc_init, 3981 .get_csb_size = gfx_v12_0_get_csb_size, 3982 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3983 .resume = gfx_v12_0_rlc_resume, 3984 .stop = gfx_v12_0_rlc_stop, 3985 .reset = gfx_v12_0_rlc_reset, 3986 .start = gfx_v12_0_rlc_start, 3987 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3988 }; 3989 3990 #if 0 3991 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3992 { 3993 /* TODO */ 3994 } 3995 3996 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3997 { 3998 /* TODO */ 3999 } 4000 #endif 4001 4002 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4003 enum amd_powergating_state state) 4004 { 4005 struct amdgpu_device *adev = ip_block->adev; 4006 bool enable = (state == AMD_PG_STATE_GATE); 4007 4008 if (amdgpu_sriov_vf(adev)) 4009 return 0; 4010 4011 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4012 case IP_VERSION(12, 0, 0): 4013 case IP_VERSION(12, 0, 1): 4014 amdgpu_gfx_off_ctrl(adev, enable); 4015 break; 4016 default: 4017 break; 4018 } 4019 4020 return 0; 4021 } 4022 4023 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4024 bool enable) 4025 { 4026 uint32_t def, data; 4027 4028 if (!(adev->cg_flags & 4029 (AMD_CG_SUPPORT_GFX_CGCG | 4030 AMD_CG_SUPPORT_GFX_CGLS | 4031 AMD_CG_SUPPORT_GFX_3D_CGCG | 4032 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4033 return; 4034 4035 if (enable) { 4036 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4037 4038 /* unset CGCG override */ 4039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4040 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4041 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4042 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4043 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4044 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4045 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4046 4047 /* update CGCG override bits */ 4048 if (def != data) 4049 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4050 4051 /* enable cgcg FSM(0x0000363F) */ 4052 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4053 4054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4055 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4056 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4057 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4058 } 4059 4060 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4061 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4062 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4063 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4064 } 4065 4066 if (def != data) 4067 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4068 4069 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4070 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4071 4072 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4073 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4074 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4075 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4076 } 4077 4078 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4079 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4080 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4081 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4082 } 4083 4084 if (def != data) 4085 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4086 4087 /* set IDLE_POLL_COUNT(0x00900100) */ 4088 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4089 4090 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4091 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4092 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4093 4094 if (def != data) 4095 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4096 4097 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4098 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4099 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4100 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4101 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4102 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4103 4104 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4105 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4106 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4107 4108 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4109 if (adev->sdma.num_instances > 1) { 4110 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4111 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4112 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4113 } 4114 } else { 4115 /* Program RLC_CGCG_CGLS_CTRL */ 4116 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4117 4118 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4119 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4120 4121 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4122 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4123 4124 if (def != data) 4125 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4126 4127 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4128 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4129 4130 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4131 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4132 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4133 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4134 4135 if (def != data) 4136 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4137 } 4138 } 4139 4140 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4141 bool enable) 4142 { 4143 uint32_t data, def; 4144 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4145 return; 4146 4147 /* It is disabled by HW by default */ 4148 if (enable) { 4149 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4150 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4151 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4152 4153 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4154 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4155 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4156 4157 if (def != data) 4158 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4159 } 4160 } else { 4161 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4162 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4163 4164 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4165 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4166 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4167 4168 if (def != data) 4169 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4170 } 4171 } 4172 } 4173 4174 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4175 bool enable) 4176 { 4177 uint32_t def, data; 4178 4179 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4180 return; 4181 4182 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4183 4184 if (enable) 4185 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4186 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4187 else 4188 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4189 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4190 4191 if (def != data) 4192 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4193 } 4194 4195 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4196 bool enable) 4197 { 4198 uint32_t def, data; 4199 4200 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4201 return; 4202 4203 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4204 4205 if (enable) 4206 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4207 else 4208 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4209 4210 if (def != data) 4211 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4212 } 4213 4214 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4215 bool enable) 4216 { 4217 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4218 4219 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4220 4221 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4222 4223 gfx_v12_0_update_repeater_fgcg(adev, enable); 4224 4225 gfx_v12_0_update_sram_fgcg(adev, enable); 4226 4227 gfx_v12_0_update_perf_clk(adev, enable); 4228 4229 if (adev->cg_flags & 4230 (AMD_CG_SUPPORT_GFX_MGCG | 4231 AMD_CG_SUPPORT_GFX_CGLS | 4232 AMD_CG_SUPPORT_GFX_CGCG | 4233 AMD_CG_SUPPORT_GFX_3D_CGCG | 4234 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4235 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4236 4237 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4238 4239 return 0; 4240 } 4241 4242 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4243 enum amd_clockgating_state state) 4244 { 4245 struct amdgpu_device *adev = ip_block->adev; 4246 4247 if (amdgpu_sriov_vf(adev)) 4248 return 0; 4249 4250 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4251 case IP_VERSION(12, 0, 0): 4252 case IP_VERSION(12, 0, 1): 4253 gfx_v12_0_update_gfx_clock_gating(adev, 4254 state == AMD_CG_STATE_GATE); 4255 break; 4256 default: 4257 break; 4258 } 4259 4260 return 0; 4261 } 4262 4263 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4264 { 4265 struct amdgpu_device *adev = ip_block->adev; 4266 int data; 4267 4268 /* AMD_CG_SUPPORT_GFX_MGCG */ 4269 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4270 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4271 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4272 4273 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4274 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4275 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4276 4277 /* AMD_CG_SUPPORT_GFX_FGCG */ 4278 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4279 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4280 4281 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4282 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4283 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4284 4285 /* AMD_CG_SUPPORT_GFX_CGCG */ 4286 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4287 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4288 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4289 4290 /* AMD_CG_SUPPORT_GFX_CGLS */ 4291 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4292 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4293 4294 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4295 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4296 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4297 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4298 4299 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4300 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4301 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4302 } 4303 4304 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4305 { 4306 /* gfx12 is 32bit rptr*/ 4307 return *(uint32_t *)ring->rptr_cpu_addr; 4308 } 4309 4310 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4311 { 4312 struct amdgpu_device *adev = ring->adev; 4313 u64 wptr; 4314 4315 /* XXX check if swapping is necessary on BE */ 4316 if (ring->use_doorbell) { 4317 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4318 } else { 4319 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4320 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4321 } 4322 4323 return wptr; 4324 } 4325 4326 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4327 { 4328 struct amdgpu_device *adev = ring->adev; 4329 4330 if (ring->use_doorbell) { 4331 /* XXX check if swapping is necessary on BE */ 4332 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4333 ring->wptr); 4334 WDOORBELL64(ring->doorbell_index, ring->wptr); 4335 } else { 4336 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4337 lower_32_bits(ring->wptr)); 4338 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4339 upper_32_bits(ring->wptr)); 4340 } 4341 } 4342 4343 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4344 { 4345 /* gfx12 hardware is 32bit rptr */ 4346 return *(uint32_t *)ring->rptr_cpu_addr; 4347 } 4348 4349 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4350 { 4351 u64 wptr; 4352 4353 /* XXX check if swapping is necessary on BE */ 4354 if (ring->use_doorbell) 4355 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4356 else 4357 BUG(); 4358 return wptr; 4359 } 4360 4361 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4362 { 4363 struct amdgpu_device *adev = ring->adev; 4364 4365 /* XXX check if swapping is necessary on BE */ 4366 if (ring->use_doorbell) { 4367 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4368 ring->wptr); 4369 WDOORBELL64(ring->doorbell_index, ring->wptr); 4370 } else { 4371 BUG(); /* only DOORBELL method supported on gfx12 now */ 4372 } 4373 } 4374 4375 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4376 { 4377 struct amdgpu_device *adev = ring->adev; 4378 u32 ref_and_mask, reg_mem_engine; 4379 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4380 4381 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4382 switch (ring->me) { 4383 case 1: 4384 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4385 break; 4386 case 2: 4387 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4388 break; 4389 default: 4390 return; 4391 } 4392 reg_mem_engine = 0; 4393 } else { 4394 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4395 reg_mem_engine = 1; /* pfp */ 4396 } 4397 4398 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4399 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4400 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4401 ref_and_mask, ref_and_mask, 0x20); 4402 } 4403 4404 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4405 struct amdgpu_job *job, 4406 struct amdgpu_ib *ib, 4407 uint32_t flags) 4408 { 4409 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4410 u32 header, control = 0; 4411 4412 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4413 4414 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4415 4416 control |= ib->length_dw | (vmid << 24); 4417 4418 amdgpu_ring_write(ring, header); 4419 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4420 amdgpu_ring_write(ring, 4421 #ifdef __BIG_ENDIAN 4422 (2 << 0) | 4423 #endif 4424 lower_32_bits(ib->gpu_addr)); 4425 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4426 amdgpu_ring_write(ring, control); 4427 } 4428 4429 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4430 struct amdgpu_job *job, 4431 struct amdgpu_ib *ib, 4432 uint32_t flags) 4433 { 4434 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4435 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4436 4437 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4438 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4439 amdgpu_ring_write(ring, 4440 #ifdef __BIG_ENDIAN 4441 (2 << 0) | 4442 #endif 4443 lower_32_bits(ib->gpu_addr)); 4444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4445 amdgpu_ring_write(ring, control); 4446 } 4447 4448 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4449 u64 seq, unsigned flags) 4450 { 4451 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4452 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4453 4454 /* RELEASE_MEM - flush caches, send int */ 4455 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4456 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4457 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4458 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4459 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4460 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4461 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4462 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4463 4464 /* 4465 * the address should be Qword aligned if 64bit write, Dword 4466 * aligned if only send 32bit data low (discard data high) 4467 */ 4468 if (write64bit) 4469 BUG_ON(addr & 0x7); 4470 else 4471 BUG_ON(addr & 0x3); 4472 amdgpu_ring_write(ring, lower_32_bits(addr)); 4473 amdgpu_ring_write(ring, upper_32_bits(addr)); 4474 amdgpu_ring_write(ring, lower_32_bits(seq)); 4475 amdgpu_ring_write(ring, upper_32_bits(seq)); 4476 amdgpu_ring_write(ring, 0); 4477 } 4478 4479 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4480 { 4481 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4482 uint32_t seq = ring->fence_drv.sync_seq; 4483 uint64_t addr = ring->fence_drv.gpu_addr; 4484 4485 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4486 upper_32_bits(addr), seq, 0xffffffff, 4); 4487 } 4488 4489 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4490 uint16_t pasid, uint32_t flush_type, 4491 bool all_hub, uint8_t dst_sel) 4492 { 4493 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4494 amdgpu_ring_write(ring, 4495 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4496 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4497 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4498 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4499 } 4500 4501 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4502 unsigned vmid, uint64_t pd_addr) 4503 { 4504 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4505 4506 /* compute doesn't have PFP */ 4507 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4508 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4509 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4510 amdgpu_ring_write(ring, 0x0); 4511 } 4512 } 4513 4514 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4515 u64 seq, unsigned int flags) 4516 { 4517 struct amdgpu_device *adev = ring->adev; 4518 4519 /* we only allocate 32bit for each seq wb address */ 4520 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4521 4522 /* write fence seq to the "addr" */ 4523 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4524 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4525 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4526 amdgpu_ring_write(ring, lower_32_bits(addr)); 4527 amdgpu_ring_write(ring, upper_32_bits(addr)); 4528 amdgpu_ring_write(ring, lower_32_bits(seq)); 4529 4530 if (flags & AMDGPU_FENCE_FLAG_INT) { 4531 /* set register to trigger INT */ 4532 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4533 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4534 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4535 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4536 amdgpu_ring_write(ring, 0); 4537 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4538 } 4539 } 4540 4541 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4542 uint32_t flags) 4543 { 4544 uint32_t dw2 = 0; 4545 4546 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4547 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4548 /* set load_global_config & load_global_uconfig */ 4549 dw2 |= 0x8001; 4550 /* set load_cs_sh_regs */ 4551 dw2 |= 0x01000000; 4552 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4553 dw2 |= 0x10002; 4554 } 4555 4556 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4557 amdgpu_ring_write(ring, dw2); 4558 amdgpu_ring_write(ring, 0); 4559 } 4560 4561 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4562 uint64_t addr) 4563 { 4564 unsigned ret; 4565 4566 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4567 amdgpu_ring_write(ring, lower_32_bits(addr)); 4568 amdgpu_ring_write(ring, upper_32_bits(addr)); 4569 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4570 amdgpu_ring_write(ring, 0); 4571 ret = ring->wptr & ring->buf_mask; 4572 /* patch dummy value later */ 4573 amdgpu_ring_write(ring, 0); 4574 4575 return ret; 4576 } 4577 4578 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4579 { 4580 int i, r = 0; 4581 struct amdgpu_device *adev = ring->adev; 4582 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4583 struct amdgpu_ring *kiq_ring = &kiq->ring; 4584 unsigned long flags; 4585 4586 if (adev->enable_mes) 4587 return -EINVAL; 4588 4589 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4590 return -EINVAL; 4591 4592 spin_lock_irqsave(&kiq->ring_lock, flags); 4593 4594 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4595 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4596 return -ENOMEM; 4597 } 4598 4599 /* assert preemption condition */ 4600 amdgpu_ring_set_preempt_cond_exec(ring, false); 4601 4602 /* assert IB preemption, emit the trailing fence */ 4603 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4604 ring->trail_fence_gpu_addr, 4605 ++ring->trail_seq); 4606 amdgpu_ring_commit(kiq_ring); 4607 4608 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4609 4610 /* poll the trailing fence */ 4611 for (i = 0; i < adev->usec_timeout; i++) { 4612 if (ring->trail_seq == 4613 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4614 break; 4615 udelay(1); 4616 } 4617 4618 if (i >= adev->usec_timeout) { 4619 r = -EINVAL; 4620 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4621 } 4622 4623 /* deassert preemption condition */ 4624 amdgpu_ring_set_preempt_cond_exec(ring, true); 4625 return r; 4626 } 4627 4628 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4629 bool start, 4630 bool secure) 4631 { 4632 uint32_t v = secure ? FRAME_TMZ : 0; 4633 4634 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4635 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4636 } 4637 4638 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4639 uint32_t reg_val_offs) 4640 { 4641 struct amdgpu_device *adev = ring->adev; 4642 4643 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4644 amdgpu_ring_write(ring, 0 | /* src: register*/ 4645 (5 << 8) | /* dst: memory */ 4646 (1 << 20)); /* write confirm */ 4647 amdgpu_ring_write(ring, reg); 4648 amdgpu_ring_write(ring, 0); 4649 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4650 reg_val_offs * 4)); 4651 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4652 reg_val_offs * 4)); 4653 } 4654 4655 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4656 uint32_t reg, 4657 uint32_t val) 4658 { 4659 uint32_t cmd = 0; 4660 4661 switch (ring->funcs->type) { 4662 case AMDGPU_RING_TYPE_GFX: 4663 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4664 break; 4665 case AMDGPU_RING_TYPE_KIQ: 4666 cmd = (1 << 16); /* no inc addr */ 4667 break; 4668 default: 4669 cmd = WR_CONFIRM; 4670 break; 4671 } 4672 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4673 amdgpu_ring_write(ring, cmd); 4674 amdgpu_ring_write(ring, reg); 4675 amdgpu_ring_write(ring, 0); 4676 amdgpu_ring_write(ring, val); 4677 } 4678 4679 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4680 uint32_t val, uint32_t mask) 4681 { 4682 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4683 } 4684 4685 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4686 uint32_t reg0, uint32_t reg1, 4687 uint32_t ref, uint32_t mask) 4688 { 4689 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4690 4691 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4692 ref, mask, 0x20); 4693 } 4694 4695 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4696 unsigned vmid) 4697 { 4698 struct amdgpu_device *adev = ring->adev; 4699 uint32_t value = 0; 4700 4701 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4702 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4703 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4704 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4705 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4706 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4707 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4708 } 4709 4710 static void 4711 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4712 uint32_t me, uint32_t pipe, 4713 enum amdgpu_interrupt_state state) 4714 { 4715 uint32_t cp_int_cntl, cp_int_cntl_reg; 4716 4717 if (!me) { 4718 switch (pipe) { 4719 case 0: 4720 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4721 break; 4722 default: 4723 DRM_DEBUG("invalid pipe %d\n", pipe); 4724 return; 4725 } 4726 } else { 4727 DRM_DEBUG("invalid me %d\n", me); 4728 return; 4729 } 4730 4731 switch (state) { 4732 case AMDGPU_IRQ_STATE_DISABLE: 4733 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4734 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4735 TIME_STAMP_INT_ENABLE, 0); 4736 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4737 GENERIC0_INT_ENABLE, 0); 4738 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4739 break; 4740 case AMDGPU_IRQ_STATE_ENABLE: 4741 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4742 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4743 TIME_STAMP_INT_ENABLE, 1); 4744 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4745 GENERIC0_INT_ENABLE, 1); 4746 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4747 break; 4748 default: 4749 break; 4750 } 4751 } 4752 4753 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4754 int me, int pipe, 4755 enum amdgpu_interrupt_state state) 4756 { 4757 u32 mec_int_cntl, mec_int_cntl_reg; 4758 4759 /* 4760 * amdgpu controls only the first MEC. That's why this function only 4761 * handles the setting of interrupts for this specific MEC. All other 4762 * pipes' interrupts are set by amdkfd. 4763 */ 4764 4765 if (me == 1) { 4766 switch (pipe) { 4767 case 0: 4768 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4769 break; 4770 case 1: 4771 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4772 break; 4773 default: 4774 DRM_DEBUG("invalid pipe %d\n", pipe); 4775 return; 4776 } 4777 } else { 4778 DRM_DEBUG("invalid me %d\n", me); 4779 return; 4780 } 4781 4782 switch (state) { 4783 case AMDGPU_IRQ_STATE_DISABLE: 4784 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4785 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4786 TIME_STAMP_INT_ENABLE, 0); 4787 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4788 GENERIC0_INT_ENABLE, 0); 4789 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4790 break; 4791 case AMDGPU_IRQ_STATE_ENABLE: 4792 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4793 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4794 TIME_STAMP_INT_ENABLE, 1); 4795 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4796 GENERIC0_INT_ENABLE, 1); 4797 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4798 break; 4799 default: 4800 break; 4801 } 4802 } 4803 4804 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4805 struct amdgpu_irq_src *src, 4806 unsigned type, 4807 enum amdgpu_interrupt_state state) 4808 { 4809 switch (type) { 4810 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4811 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4812 break; 4813 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4814 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4815 break; 4816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4817 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4818 break; 4819 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4820 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4821 break; 4822 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4823 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4824 break; 4825 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4826 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4827 break; 4828 default: 4829 break; 4830 } 4831 return 0; 4832 } 4833 4834 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4835 struct amdgpu_irq_src *source, 4836 struct amdgpu_iv_entry *entry) 4837 { 4838 u32 doorbell_offset = entry->src_data[0]; 4839 u8 me_id, pipe_id, queue_id; 4840 struct amdgpu_ring *ring; 4841 int i; 4842 4843 DRM_DEBUG("IH: CP EOP\n"); 4844 4845 if (adev->enable_mes && doorbell_offset) { 4846 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4847 struct xarray *xa = &adev->userq_xa; 4848 unsigned long flags; 4849 4850 xa_lock_irqsave(xa, flags); 4851 fence_drv = xa_load(xa, doorbell_offset); 4852 if (fence_drv) 4853 amdgpu_userq_fence_driver_process(fence_drv); 4854 xa_unlock_irqrestore(xa, flags); 4855 } else { 4856 me_id = (entry->ring_id & 0x0c) >> 2; 4857 pipe_id = (entry->ring_id & 0x03) >> 0; 4858 queue_id = (entry->ring_id & 0x70) >> 4; 4859 4860 switch (me_id) { 4861 case 0: 4862 if (pipe_id == 0) 4863 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4864 else 4865 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4866 break; 4867 case 1: 4868 case 2: 4869 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4870 ring = &adev->gfx.compute_ring[i]; 4871 /* Per-queue interrupt is supported for MEC starting from VI. 4872 * The interrupt can only be enabled/disabled per pipe instead 4873 * of per queue. 4874 */ 4875 if ((ring->me == me_id) && 4876 (ring->pipe == pipe_id) && 4877 (ring->queue == queue_id)) 4878 amdgpu_fence_process(ring); 4879 } 4880 break; 4881 } 4882 } 4883 4884 return 0; 4885 } 4886 4887 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4888 struct amdgpu_irq_src *source, 4889 unsigned int type, 4890 enum amdgpu_interrupt_state state) 4891 { 4892 u32 cp_int_cntl_reg, cp_int_cntl; 4893 int i, j; 4894 4895 switch (state) { 4896 case AMDGPU_IRQ_STATE_DISABLE: 4897 case AMDGPU_IRQ_STATE_ENABLE: 4898 for (i = 0; i < adev->gfx.me.num_me; i++) { 4899 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4900 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4901 4902 if (cp_int_cntl_reg) { 4903 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4904 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4905 PRIV_REG_INT_ENABLE, 4906 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4907 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4908 } 4909 } 4910 } 4911 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4912 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4913 /* MECs start at 1 */ 4914 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4915 4916 if (cp_int_cntl_reg) { 4917 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4918 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4919 PRIV_REG_INT_ENABLE, 4920 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4921 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4922 } 4923 } 4924 } 4925 break; 4926 default: 4927 break; 4928 } 4929 4930 return 0; 4931 } 4932 4933 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4934 struct amdgpu_irq_src *source, 4935 unsigned type, 4936 enum amdgpu_interrupt_state state) 4937 { 4938 u32 cp_int_cntl_reg, cp_int_cntl; 4939 int i, j; 4940 4941 switch (state) { 4942 case AMDGPU_IRQ_STATE_DISABLE: 4943 case AMDGPU_IRQ_STATE_ENABLE: 4944 for (i = 0; i < adev->gfx.me.num_me; i++) { 4945 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4946 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4947 4948 if (cp_int_cntl_reg) { 4949 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4950 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4951 OPCODE_ERROR_INT_ENABLE, 4952 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4953 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4954 } 4955 } 4956 } 4957 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4958 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4959 /* MECs start at 1 */ 4960 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4961 4962 if (cp_int_cntl_reg) { 4963 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4964 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4965 OPCODE_ERROR_INT_ENABLE, 4966 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4967 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4968 } 4969 } 4970 } 4971 break; 4972 default: 4973 break; 4974 } 4975 return 0; 4976 } 4977 4978 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4979 struct amdgpu_irq_src *source, 4980 unsigned int type, 4981 enum amdgpu_interrupt_state state) 4982 { 4983 u32 cp_int_cntl_reg, cp_int_cntl; 4984 int i, j; 4985 4986 switch (state) { 4987 case AMDGPU_IRQ_STATE_DISABLE: 4988 case AMDGPU_IRQ_STATE_ENABLE: 4989 for (i = 0; i < adev->gfx.me.num_me; i++) { 4990 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4991 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4992 4993 if (cp_int_cntl_reg) { 4994 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4995 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4996 PRIV_INSTR_INT_ENABLE, 4997 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4998 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4999 } 5000 } 5001 } 5002 break; 5003 default: 5004 break; 5005 } 5006 5007 return 0; 5008 } 5009 5010 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5011 struct amdgpu_iv_entry *entry) 5012 { 5013 u8 me_id, pipe_id, queue_id; 5014 struct amdgpu_ring *ring; 5015 int i; 5016 5017 me_id = (entry->ring_id & 0x0c) >> 2; 5018 pipe_id = (entry->ring_id & 0x03) >> 0; 5019 queue_id = (entry->ring_id & 0x70) >> 4; 5020 5021 if (!adev->gfx.disable_kq) { 5022 switch (me_id) { 5023 case 0: 5024 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5025 ring = &adev->gfx.gfx_ring[i]; 5026 if (ring->me == me_id && ring->pipe == pipe_id && 5027 ring->queue == queue_id) 5028 drm_sched_fault(&ring->sched); 5029 } 5030 break; 5031 case 1: 5032 case 2: 5033 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5034 ring = &adev->gfx.compute_ring[i]; 5035 if (ring->me == me_id && ring->pipe == pipe_id && 5036 ring->queue == queue_id) 5037 drm_sched_fault(&ring->sched); 5038 } 5039 break; 5040 default: 5041 BUG(); 5042 break; 5043 } 5044 } 5045 } 5046 5047 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5048 struct amdgpu_irq_src *source, 5049 struct amdgpu_iv_entry *entry) 5050 { 5051 DRM_ERROR("Illegal register access in command stream\n"); 5052 gfx_v12_0_handle_priv_fault(adev, entry); 5053 return 0; 5054 } 5055 5056 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5057 struct amdgpu_irq_src *source, 5058 struct amdgpu_iv_entry *entry) 5059 { 5060 DRM_ERROR("Illegal opcode in command stream \n"); 5061 gfx_v12_0_handle_priv_fault(adev, entry); 5062 return 0; 5063 } 5064 5065 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5066 struct amdgpu_irq_src *source, 5067 struct amdgpu_iv_entry *entry) 5068 { 5069 DRM_ERROR("Illegal instruction in command stream\n"); 5070 gfx_v12_0_handle_priv_fault(adev, entry); 5071 return 0; 5072 } 5073 5074 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5075 { 5076 const unsigned int gcr_cntl = 5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5079 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5080 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5081 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5082 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5083 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5084 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5085 5086 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5087 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5088 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5089 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5090 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5091 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5092 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5093 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5094 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5095 } 5096 5097 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5098 { 5099 /* Header itself is a NOP packet */ 5100 if (num_nop == 1) { 5101 amdgpu_ring_write(ring, ring->funcs->nop); 5102 return; 5103 } 5104 5105 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5106 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5107 5108 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5109 amdgpu_ring_insert_nop(ring, num_nop - 1); 5110 } 5111 5112 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5113 { 5114 /* Emit the cleaner shader */ 5115 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5116 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5117 } 5118 5119 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5120 { 5121 struct amdgpu_device *adev = ip_block->adev; 5122 uint32_t i, j, k, reg, index = 0; 5123 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5124 5125 if (!adev->gfx.ip_dump_core) 5126 return; 5127 5128 for (i = 0; i < reg_count; i++) 5129 drm_printf(p, "%-50s \t 0x%08x\n", 5130 gc_reg_list_12_0[i].reg_name, 5131 adev->gfx.ip_dump_core[i]); 5132 5133 /* print compute queue registers for all instances */ 5134 if (!adev->gfx.ip_dump_compute_queues) 5135 return; 5136 5137 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5138 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5139 adev->gfx.mec.num_mec, 5140 adev->gfx.mec.num_pipe_per_mec, 5141 adev->gfx.mec.num_queue_per_pipe); 5142 5143 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5144 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5145 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5146 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5147 for (reg = 0; reg < reg_count; reg++) { 5148 drm_printf(p, "%-50s \t 0x%08x\n", 5149 gc_cp_reg_list_12[reg].reg_name, 5150 adev->gfx.ip_dump_compute_queues[index + reg]); 5151 } 5152 index += reg_count; 5153 } 5154 } 5155 } 5156 5157 /* print gfx queue registers for all instances */ 5158 if (!adev->gfx.ip_dump_gfx_queues) 5159 return; 5160 5161 index = 0; 5162 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5163 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5164 adev->gfx.me.num_me, 5165 adev->gfx.me.num_pipe_per_me, 5166 adev->gfx.me.num_queue_per_pipe); 5167 5168 for (i = 0; i < adev->gfx.me.num_me; i++) { 5169 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5170 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5171 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5172 for (reg = 0; reg < reg_count; reg++) { 5173 drm_printf(p, "%-50s \t 0x%08x\n", 5174 gc_gfx_queue_reg_list_12[reg].reg_name, 5175 adev->gfx.ip_dump_gfx_queues[index + reg]); 5176 } 5177 index += reg_count; 5178 } 5179 } 5180 } 5181 } 5182 5183 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5184 { 5185 struct amdgpu_device *adev = ip_block->adev; 5186 uint32_t i, j, k, reg, index = 0; 5187 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5188 5189 if (!adev->gfx.ip_dump_core) 5190 return; 5191 5192 amdgpu_gfx_off_ctrl(adev, false); 5193 for (i = 0; i < reg_count; i++) 5194 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5195 amdgpu_gfx_off_ctrl(adev, true); 5196 5197 /* dump compute queue registers for all instances */ 5198 if (!adev->gfx.ip_dump_compute_queues) 5199 return; 5200 5201 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5202 amdgpu_gfx_off_ctrl(adev, false); 5203 mutex_lock(&adev->srbm_mutex); 5204 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5205 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5206 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5207 /* ME0 is for GFX so start from 1 for CP */ 5208 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5209 for (reg = 0; reg < reg_count; reg++) { 5210 adev->gfx.ip_dump_compute_queues[index + reg] = 5211 RREG32(SOC15_REG_ENTRY_OFFSET( 5212 gc_cp_reg_list_12[reg])); 5213 } 5214 index += reg_count; 5215 } 5216 } 5217 } 5218 soc24_grbm_select(adev, 0, 0, 0, 0); 5219 mutex_unlock(&adev->srbm_mutex); 5220 amdgpu_gfx_off_ctrl(adev, true); 5221 5222 /* dump gfx queue registers for all instances */ 5223 if (!adev->gfx.ip_dump_gfx_queues) 5224 return; 5225 5226 index = 0; 5227 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5228 amdgpu_gfx_off_ctrl(adev, false); 5229 mutex_lock(&adev->srbm_mutex); 5230 for (i = 0; i < adev->gfx.me.num_me; i++) { 5231 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5232 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5233 soc24_grbm_select(adev, i, j, k, 0); 5234 5235 for (reg = 0; reg < reg_count; reg++) { 5236 adev->gfx.ip_dump_gfx_queues[index + reg] = 5237 RREG32(SOC15_REG_ENTRY_OFFSET( 5238 gc_gfx_queue_reg_list_12[reg])); 5239 } 5240 index += reg_count; 5241 } 5242 } 5243 } 5244 soc24_grbm_select(adev, 0, 0, 0, 0); 5245 mutex_unlock(&adev->srbm_mutex); 5246 amdgpu_gfx_off_ctrl(adev, true); 5247 } 5248 5249 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5250 { 5251 /* Disable the pipe reset until the CPFW fully support it.*/ 5252 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5253 return false; 5254 } 5255 5256 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5257 { 5258 struct amdgpu_device *adev = ring->adev; 5259 uint32_t reset_pipe = 0, clean_pipe = 0; 5260 int r; 5261 5262 if (!gfx_v12_pipe_reset_support(adev)) 5263 return -EOPNOTSUPP; 5264 5265 gfx_v12_0_set_safe_mode(adev, 0); 5266 mutex_lock(&adev->srbm_mutex); 5267 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5268 5269 switch (ring->pipe) { 5270 case 0: 5271 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5272 PFP_PIPE0_RESET, 1); 5273 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5274 ME_PIPE0_RESET, 1); 5275 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5276 PFP_PIPE0_RESET, 0); 5277 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5278 ME_PIPE0_RESET, 0); 5279 break; 5280 case 1: 5281 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5282 PFP_PIPE1_RESET, 1); 5283 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5284 ME_PIPE1_RESET, 1); 5285 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5286 PFP_PIPE1_RESET, 0); 5287 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5288 ME_PIPE1_RESET, 0); 5289 break; 5290 default: 5291 break; 5292 } 5293 5294 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5295 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5296 5297 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5298 RS64_FW_UC_START_ADDR_LO; 5299 soc24_grbm_select(adev, 0, 0, 0, 0); 5300 mutex_unlock(&adev->srbm_mutex); 5301 gfx_v12_0_unset_safe_mode(adev, 0); 5302 5303 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5304 r == 0 ? "successfully" : "failed"); 5305 /* Sometimes the ME start pc counter can't cache correctly, so the 5306 * PC check only as a reference and pipe reset result rely on the 5307 * later ring test. 5308 */ 5309 return 0; 5310 } 5311 5312 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5313 { 5314 struct amdgpu_device *adev = ring->adev; 5315 int r; 5316 5317 if (amdgpu_sriov_vf(adev)) 5318 return -EINVAL; 5319 5320 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5321 if (r) { 5322 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5323 r = gfx_v12_reset_gfx_pipe(ring); 5324 if (r) 5325 return r; 5326 } 5327 5328 r = gfx_v12_0_kgq_init_queue(ring, true); 5329 if (r) { 5330 dev_err(adev->dev, "failed to init kgq\n"); 5331 return r; 5332 } 5333 5334 r = amdgpu_mes_map_legacy_queue(adev, ring); 5335 if (r) { 5336 dev_err(adev->dev, "failed to remap kgq\n"); 5337 return r; 5338 } 5339 5340 return amdgpu_ring_test_ring(ring); 5341 } 5342 5343 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5344 { 5345 struct amdgpu_device *adev = ring->adev; 5346 uint32_t reset_pipe = 0, clean_pipe = 0; 5347 int r = 0; 5348 5349 if (!gfx_v12_pipe_reset_support(adev)) 5350 return -EOPNOTSUPP; 5351 5352 gfx_v12_0_set_safe_mode(adev, 0); 5353 mutex_lock(&adev->srbm_mutex); 5354 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5355 5356 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5357 clean_pipe = reset_pipe; 5358 5359 if (adev->gfx.rs64_enable) { 5360 switch (ring->pipe) { 5361 case 0: 5362 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5363 MEC_PIPE0_RESET, 1); 5364 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5365 MEC_PIPE0_RESET, 0); 5366 break; 5367 case 1: 5368 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5369 MEC_PIPE1_RESET, 1); 5370 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5371 MEC_PIPE1_RESET, 0); 5372 break; 5373 case 2: 5374 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5375 MEC_PIPE2_RESET, 1); 5376 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5377 MEC_PIPE2_RESET, 0); 5378 break; 5379 case 3: 5380 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5381 MEC_PIPE3_RESET, 1); 5382 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5383 MEC_PIPE3_RESET, 0); 5384 break; 5385 default: 5386 break; 5387 } 5388 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5389 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5390 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5391 RS64_FW_UC_START_ADDR_LO; 5392 } else { 5393 switch (ring->pipe) { 5394 case 0: 5395 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5396 MEC_ME1_PIPE0_RESET, 1); 5397 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5398 MEC_ME1_PIPE0_RESET, 0); 5399 break; 5400 case 1: 5401 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5402 MEC_ME1_PIPE1_RESET, 1); 5403 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5404 MEC_ME1_PIPE1_RESET, 0); 5405 break; 5406 default: 5407 break; 5408 } 5409 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5410 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5411 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5412 * the driver won't run into the F32 mode. 5413 */ 5414 } 5415 5416 soc24_grbm_select(adev, 0, 0, 0, 0); 5417 mutex_unlock(&adev->srbm_mutex); 5418 gfx_v12_0_unset_safe_mode(adev, 0); 5419 5420 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5421 r == 0 ? "successfully" : "failed"); 5422 /* Need the ring test to verify the pipe reset result.*/ 5423 return 0; 5424 } 5425 5426 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5427 { 5428 struct amdgpu_device *adev = ring->adev; 5429 int r; 5430 5431 if (amdgpu_sriov_vf(adev)) 5432 return -EINVAL; 5433 5434 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5435 if (r) { 5436 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5437 r = gfx_v12_0_reset_compute_pipe(ring); 5438 if (r) 5439 return r; 5440 } 5441 5442 r = gfx_v12_0_kcq_init_queue(ring, true); 5443 if (r) { 5444 dev_err(adev->dev, "failed to init kcq\n"); 5445 return r; 5446 } 5447 r = amdgpu_mes_map_legacy_queue(adev, ring); 5448 if (r) { 5449 dev_err(adev->dev, "failed to remap kcq\n"); 5450 return r; 5451 } 5452 5453 return amdgpu_ring_test_ring(ring); 5454 } 5455 5456 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5457 { 5458 amdgpu_gfx_profile_ring_begin_use(ring); 5459 5460 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5461 } 5462 5463 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5464 { 5465 amdgpu_gfx_profile_ring_end_use(ring); 5466 5467 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5468 } 5469 5470 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5471 .name = "gfx_v12_0", 5472 .early_init = gfx_v12_0_early_init, 5473 .late_init = gfx_v12_0_late_init, 5474 .sw_init = gfx_v12_0_sw_init, 5475 .sw_fini = gfx_v12_0_sw_fini, 5476 .hw_init = gfx_v12_0_hw_init, 5477 .hw_fini = gfx_v12_0_hw_fini, 5478 .suspend = gfx_v12_0_suspend, 5479 .resume = gfx_v12_0_resume, 5480 .is_idle = gfx_v12_0_is_idle, 5481 .wait_for_idle = gfx_v12_0_wait_for_idle, 5482 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5483 .set_powergating_state = gfx_v12_0_set_powergating_state, 5484 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5485 .dump_ip_state = gfx_v12_ip_dump, 5486 .print_ip_state = gfx_v12_ip_print, 5487 }; 5488 5489 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5490 .type = AMDGPU_RING_TYPE_GFX, 5491 .align_mask = 0xff, 5492 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5493 .support_64bit_ptrs = true, 5494 .secure_submission_supported = true, 5495 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5496 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5497 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5498 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5499 5 + /* COND_EXEC */ 5500 7 + /* PIPELINE_SYNC */ 5501 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5502 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5503 2 + /* VM_FLUSH */ 5504 8 + /* FENCE for VM_FLUSH */ 5505 5 + /* COND_EXEC */ 5506 7 + /* HDP_flush */ 5507 4 + /* VGT_flush */ 5508 31 + /* DE_META */ 5509 3 + /* CNTX_CTRL */ 5510 5 + /* HDP_INVL */ 5511 8 + 8 + /* FENCE x2 */ 5512 8 + /* gfx_v12_0_emit_mem_sync */ 5513 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5514 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5515 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5516 .emit_fence = gfx_v12_0_ring_emit_fence, 5517 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5518 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5519 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5520 .test_ring = gfx_v12_0_ring_test_ring, 5521 .test_ib = gfx_v12_0_ring_test_ib, 5522 .insert_nop = gfx_v12_ring_insert_nop, 5523 .pad_ib = amdgpu_ring_generic_pad_ib, 5524 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5525 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5526 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5527 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5528 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5529 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5530 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5531 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5532 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5533 .reset = gfx_v12_0_reset_kgq, 5534 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5535 .begin_use = gfx_v12_0_ring_begin_use, 5536 .end_use = gfx_v12_0_ring_end_use, 5537 }; 5538 5539 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5540 .type = AMDGPU_RING_TYPE_COMPUTE, 5541 .align_mask = 0xff, 5542 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5543 .support_64bit_ptrs = true, 5544 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5545 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5546 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5547 .emit_frame_size = 5548 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5549 5 + /* hdp invalidate */ 5550 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5551 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5552 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5553 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5554 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5555 8 + /* gfx_v12_0_emit_mem_sync */ 5556 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5557 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5558 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5559 .emit_fence = gfx_v12_0_ring_emit_fence, 5560 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5561 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5562 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5563 .test_ring = gfx_v12_0_ring_test_ring, 5564 .test_ib = gfx_v12_0_ring_test_ib, 5565 .insert_nop = gfx_v12_ring_insert_nop, 5566 .pad_ib = amdgpu_ring_generic_pad_ib, 5567 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5568 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5569 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5570 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5571 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5572 .reset = gfx_v12_0_reset_kcq, 5573 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5574 .begin_use = gfx_v12_0_ring_begin_use, 5575 .end_use = gfx_v12_0_ring_end_use, 5576 }; 5577 5578 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5579 .type = AMDGPU_RING_TYPE_KIQ, 5580 .align_mask = 0xff, 5581 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5582 .support_64bit_ptrs = true, 5583 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5584 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5585 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5586 .emit_frame_size = 5587 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5588 5 + /*hdp invalidate */ 5589 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5590 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5591 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5592 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5593 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5594 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5595 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5596 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5597 .test_ring = gfx_v12_0_ring_test_ring, 5598 .test_ib = gfx_v12_0_ring_test_ib, 5599 .insert_nop = amdgpu_ring_insert_nop, 5600 .pad_ib = amdgpu_ring_generic_pad_ib, 5601 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5602 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5603 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5604 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5605 }; 5606 5607 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5608 { 5609 int i; 5610 5611 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5612 5613 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5614 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5615 5616 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5617 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5618 } 5619 5620 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5621 .set = gfx_v12_0_set_eop_interrupt_state, 5622 .process = gfx_v12_0_eop_irq, 5623 }; 5624 5625 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5626 .set = gfx_v12_0_set_priv_reg_fault_state, 5627 .process = gfx_v12_0_priv_reg_irq, 5628 }; 5629 5630 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5631 .set = gfx_v12_0_set_bad_op_fault_state, 5632 .process = gfx_v12_0_bad_op_irq, 5633 }; 5634 5635 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5636 .set = gfx_v12_0_set_priv_inst_fault_state, 5637 .process = gfx_v12_0_priv_inst_irq, 5638 }; 5639 5640 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5641 { 5642 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5643 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5644 5645 adev->gfx.priv_reg_irq.num_types = 1; 5646 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5647 5648 adev->gfx.bad_op_irq.num_types = 1; 5649 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5650 5651 adev->gfx.priv_inst_irq.num_types = 1; 5652 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5653 } 5654 5655 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5656 { 5657 if (adev->flags & AMD_IS_APU) 5658 adev->gfx.imu.mode = MISSION_MODE; 5659 else 5660 adev->gfx.imu.mode = DEBUG_MODE; 5661 5662 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5663 } 5664 5665 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5666 { 5667 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5668 } 5669 5670 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5671 { 5672 /* set gfx eng mqd */ 5673 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5674 sizeof(struct v12_gfx_mqd); 5675 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5676 gfx_v12_0_gfx_mqd_init; 5677 /* set compute eng mqd */ 5678 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5679 sizeof(struct v12_compute_mqd); 5680 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5681 gfx_v12_0_compute_mqd_init; 5682 } 5683 5684 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5685 u32 bitmap) 5686 { 5687 u32 data; 5688 5689 if (!bitmap) 5690 return; 5691 5692 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5693 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5694 5695 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5696 } 5697 5698 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5699 { 5700 u32 data, wgp_bitmask; 5701 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5702 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5703 5704 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5705 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5706 5707 wgp_bitmask = 5708 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5709 5710 return (~data) & wgp_bitmask; 5711 } 5712 5713 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5714 { 5715 u32 wgp_idx, wgp_active_bitmap; 5716 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5717 5718 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5719 cu_active_bitmap = 0; 5720 5721 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5722 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5723 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5724 if (wgp_active_bitmap & (1 << wgp_idx)) 5725 cu_active_bitmap |= cu_bitmap_per_wgp; 5726 } 5727 5728 return cu_active_bitmap; 5729 } 5730 5731 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5732 struct amdgpu_cu_info *cu_info) 5733 { 5734 int i, j, k, counter, active_cu_number = 0; 5735 u32 mask, bitmap; 5736 unsigned disable_masks[8 * 2]; 5737 5738 if (!adev || !cu_info) 5739 return -EINVAL; 5740 5741 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5742 5743 mutex_lock(&adev->grbm_idx_mutex); 5744 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5745 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5746 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5747 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5748 continue; 5749 mask = 1; 5750 counter = 0; 5751 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5752 if (i < 8 && j < 2) 5753 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5754 adev, disable_masks[i * 2 + j]); 5755 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5756 5757 /** 5758 * GFX12 could support more than 4 SEs, while the bitmap 5759 * in cu_info struct is 4x4 and ioctl interface struct 5760 * drm_amdgpu_info_device should keep stable. 5761 * So we use last two columns of bitmap to store cu mask for 5762 * SEs 4 to 7, the layout of the bitmap is as below: 5763 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5764 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5765 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5766 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5767 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5768 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5769 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5770 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5771 */ 5772 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5773 5774 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5775 if (bitmap & mask) 5776 counter++; 5777 5778 mask <<= 1; 5779 } 5780 active_cu_number += counter; 5781 } 5782 } 5783 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5784 mutex_unlock(&adev->grbm_idx_mutex); 5785 5786 cu_info->number = active_cu_number; 5787 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5788 5789 return 0; 5790 } 5791 5792 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5793 .type = AMD_IP_BLOCK_TYPE_GFX, 5794 .major = 12, 5795 .minor = 0, 5796 .rev = 0, 5797 .funcs = &gfx_v12_0_ip_funcs, 5798 }; 5799