1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 359 gpu_addr, seq, 0); 360 return; 361 } 362 363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 365 PACKET3_UNMAP_QUEUES_ACTION(action) | 366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 369 amdgpu_ring_write(kiq_ring, 370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 371 372 if (action == PREEMPT_QUEUES_NO_UNMAP) { 373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, seq); 376 } else { 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 } 381 } 382 383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 384 struct amdgpu_ring *ring, 385 u64 addr, u64 seq) 386 { 387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 388 389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 390 amdgpu_ring_write(kiq_ring, 391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 393 PACKET3_QUERY_STATUS_COMMAND(2)); 394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 401 } 402 403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 404 uint16_t pasid, 405 uint32_t flush_type, 406 bool all_hub) 407 { 408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 409 } 410 411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 412 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 413 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 415 .kiq_query_status = gfx_v12_0_kiq_query_status, 416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 417 .set_resources_size = 8, 418 .map_queues_size = 7, 419 .unmap_queues_size = 6, 420 .query_status_size = 7, 421 .invalidate_tlbs_size = 2, 422 }; 423 424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 425 { 426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 427 } 428 429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 430 int mem_space, int opt, uint32_t addr0, 431 uint32_t addr1, uint32_t ref, 432 uint32_t mask, uint32_t inv) 433 { 434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 435 amdgpu_ring_write(ring, 436 /* memory (1) or register (0) */ 437 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 438 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 439 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 440 WAIT_REG_MEM_ENGINE(eng_sel))); 441 442 if (mem_space) 443 WARN_ON(addr0 & 0x3); /* Dword align */ 444 amdgpu_ring_write(ring, addr0); 445 amdgpu_ring_write(ring, addr1); 446 amdgpu_ring_write(ring, ref); 447 amdgpu_ring_write(ring, mask); 448 amdgpu_ring_write(ring, inv); /* poll interval */ 449 } 450 451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 455 uint32_t tmp = 0; 456 unsigned i; 457 int r; 458 459 WREG32(scratch, 0xCAFEDEAD); 460 r = amdgpu_ring_alloc(ring, 5); 461 if (r) { 462 drm_err(adev_to_drm(adev), 463 "cp failed to lock ring %d (%d).\n", 464 ring->idx, r); 465 return r; 466 } 467 468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 470 } else { 471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 472 amdgpu_ring_write(ring, scratch - 473 PACKET3_SET_UCONFIG_REG_START); 474 amdgpu_ring_write(ring, 0xDEADBEEF); 475 } 476 amdgpu_ring_commit(ring); 477 478 for (i = 0; i < adev->usec_timeout; i++) { 479 tmp = RREG32(scratch); 480 if (tmp == 0xDEADBEEF) 481 break; 482 if (amdgpu_emu_mode == 1) 483 msleep(1); 484 else 485 udelay(1); 486 } 487 488 if (i >= adev->usec_timeout) 489 r = -ETIMEDOUT; 490 return r; 491 } 492 493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 494 { 495 struct amdgpu_device *adev = ring->adev; 496 struct amdgpu_ib ib; 497 struct dma_fence *f = NULL; 498 unsigned index; 499 uint64_t gpu_addr; 500 uint32_t *cpu_ptr; 501 long r; 502 503 /* MES KIQ fw hasn't indirect buffer support for now */ 504 if (adev->enable_mes_kiq && 505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 506 return 0; 507 508 memset(&ib, 0, sizeof(ib)); 509 510 r = amdgpu_wb_get(adev, &index); 511 if (r) 512 return r; 513 514 gpu_addr = adev->wb.gpu_addr + (index * 4); 515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 516 cpu_ptr = &adev->wb.wb[index]; 517 518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 519 if (r) { 520 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 521 goto err1; 522 } 523 524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 526 ib.ptr[2] = lower_32_bits(gpu_addr); 527 ib.ptr[3] = upper_32_bits(gpu_addr); 528 ib.ptr[4] = 0xDEADBEEF; 529 ib.length_dw = 5; 530 531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 532 if (r) 533 goto err2; 534 535 r = dma_fence_wait_timeout(f, false, timeout); 536 if (r == 0) { 537 r = -ETIMEDOUT; 538 goto err2; 539 } else if (r < 0) { 540 goto err2; 541 } 542 543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 544 r = 0; 545 else 546 r = -EINVAL; 547 err2: 548 amdgpu_ib_free(&ib, NULL); 549 dma_fence_put(f); 550 err1: 551 amdgpu_wb_free(adev, index); 552 return r; 553 } 554 555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 556 { 557 amdgpu_ucode_release(&adev->gfx.pfp_fw); 558 amdgpu_ucode_release(&adev->gfx.me_fw); 559 amdgpu_ucode_release(&adev->gfx.rlc_fw); 560 amdgpu_ucode_release(&adev->gfx.mec_fw); 561 562 kfree(adev->gfx.rlc.register_list_format); 563 } 564 565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 566 { 567 const struct psp_firmware_header_v1_0 *toc_hdr; 568 int err = 0; 569 570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_toc.bin", ucode_prefix); 573 if (err) 574 goto out; 575 576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 582 return 0; 583 out: 584 amdgpu_ucode_release(&adev->psp.toc_fw); 585 return err; 586 } 587 588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 589 { 590 char ucode_prefix[30]; 591 int err; 592 const struct rlc_firmware_header_v2_0 *rlc_hdr; 593 uint16_t version_major; 594 uint16_t version_minor; 595 596 DRM_DEBUG("\n"); 597 598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 599 600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 601 AMDGPU_UCODE_REQUIRED, 602 "amdgpu/%s_pfp.bin", ucode_prefix); 603 if (err) 604 goto out; 605 606 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 607 (union amdgpu_firmware_header *) 608 adev->gfx.pfp_fw->data, 2, 0); 609 if (adev->gfx.rs64_enable) 610 dev_dbg(adev->dev, "CP RS64 enable\n"); 611 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 614 615 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 616 AMDGPU_UCODE_REQUIRED, 617 "amdgpu/%s_me.bin", ucode_prefix); 618 if (err) 619 goto out; 620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 622 623 if (!amdgpu_sriov_vf(adev)) { 624 if (amdgpu_is_kicker_fw(adev)) 625 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 626 AMDGPU_UCODE_REQUIRED, 627 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 628 else 629 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_rlc.bin", ucode_prefix); 632 if (err) 633 goto out; 634 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 635 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 636 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 637 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 638 if (err) 639 goto out; 640 } 641 642 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 643 AMDGPU_UCODE_REQUIRED, 644 "amdgpu/%s_mec.bin", ucode_prefix); 645 if (err) 646 goto out; 647 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 648 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 649 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 650 651 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 652 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 653 654 /* only one MEC for gfx 12 */ 655 adev->gfx.mec2_fw = NULL; 656 657 if (adev->gfx.imu.funcs) { 658 if (adev->gfx.imu.funcs->init_microcode) { 659 err = adev->gfx.imu.funcs->init_microcode(adev); 660 if (err) 661 dev_err(adev->dev, "Failed to load imu firmware!\n"); 662 } 663 } 664 665 out: 666 if (err) { 667 amdgpu_ucode_release(&adev->gfx.pfp_fw); 668 amdgpu_ucode_release(&adev->gfx.me_fw); 669 amdgpu_ucode_release(&adev->gfx.rlc_fw); 670 amdgpu_ucode_release(&adev->gfx.mec_fw); 671 } 672 673 return err; 674 } 675 676 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 677 { 678 u32 count = 0; 679 const struct cs_section_def *sect = NULL; 680 const struct cs_extent_def *ext = NULL; 681 682 count += 1; 683 684 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 685 if (sect->id == SECT_CONTEXT) { 686 for (ext = sect->section; ext->extent != NULL; ++ext) 687 count += 2 + ext->reg_count; 688 } else 689 return 0; 690 } 691 692 return count; 693 } 694 695 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 696 { 697 u32 count = 0, clustercount = 0, i; 698 const struct cs_section_def *sect = NULL; 699 const struct cs_extent_def *ext = NULL; 700 701 if (adev->gfx.rlc.cs_data == NULL) 702 return; 703 if (buffer == NULL) 704 return; 705 706 count += 1; 707 708 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 709 if (sect->id == SECT_CONTEXT) { 710 for (ext = sect->section; ext->extent != NULL; ++ext) { 711 clustercount++; 712 buffer[count++] = ext->reg_count; 713 buffer[count++] = ext->reg_index; 714 715 for (i = 0; i < ext->reg_count; i++) 716 buffer[count++] = cpu_to_le32(ext->extent[i]); 717 } 718 } else 719 return; 720 } 721 722 buffer[0] = clustercount; 723 } 724 725 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 726 { 727 /* clear state block */ 728 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 729 &adev->gfx.rlc.clear_state_gpu_addr, 730 (void **)&adev->gfx.rlc.cs_ptr); 731 732 /* jump table block */ 733 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 734 &adev->gfx.rlc.cp_table_gpu_addr, 735 (void **)&adev->gfx.rlc.cp_table_ptr); 736 } 737 738 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 739 { 740 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 741 742 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 743 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 744 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 745 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 746 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 747 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 748 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 749 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 750 adev->gfx.rlc.rlcg_reg_access_supported = true; 751 } 752 753 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 754 { 755 const struct cs_section_def *cs_data; 756 int r; 757 758 adev->gfx.rlc.cs_data = gfx12_cs_data; 759 760 cs_data = adev->gfx.rlc.cs_data; 761 762 if (cs_data) { 763 /* init clear state block */ 764 r = amdgpu_gfx_rlc_init_csb(adev); 765 if (r) 766 return r; 767 } 768 769 /* init spm vmid with 0xf */ 770 if (adev->gfx.rlc.funcs->update_spm_vmid) 771 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 772 773 return 0; 774 } 775 776 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 777 { 778 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 779 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 780 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 781 } 782 783 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 784 { 785 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 786 787 amdgpu_gfx_graphics_queue_acquire(adev); 788 } 789 790 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 791 { 792 int r; 793 u32 *hpd; 794 size_t mec_hpd_size; 795 796 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 797 798 /* take ownership of the relevant compute queues */ 799 amdgpu_gfx_compute_queue_acquire(adev); 800 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 801 802 if (mec_hpd_size) { 803 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 804 AMDGPU_GEM_DOMAIN_GTT, 805 &adev->gfx.mec.hpd_eop_obj, 806 &adev->gfx.mec.hpd_eop_gpu_addr, 807 (void **)&hpd); 808 if (r) { 809 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 810 gfx_v12_0_mec_fini(adev); 811 return r; 812 } 813 814 memset(hpd, 0, mec_hpd_size); 815 816 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 817 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 818 } 819 820 return 0; 821 } 822 823 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 824 { 825 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 826 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 827 (address << SQ_IND_INDEX__INDEX__SHIFT)); 828 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 829 } 830 831 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 832 uint32_t thread, uint32_t regno, 833 uint32_t num, uint32_t *out) 834 { 835 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 836 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 837 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 838 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 839 (SQ_IND_INDEX__AUTO_INCR_MASK)); 840 while (num--) 841 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 842 } 843 844 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 845 uint32_t xcc_id, 846 uint32_t simd, uint32_t wave, 847 uint32_t *dst, int *no_fields) 848 { 849 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 850 * field when performing a select_se_sh so it should be 851 * zero here */ 852 WARN_ON(simd != 0); 853 854 /* type 4 wave data */ 855 dst[(*no_fields)++] = 4; 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 873 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 874 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 875 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 876 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 877 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 878 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 879 } 880 881 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t start, 884 uint32_t size, uint32_t *dst) 885 { 886 WARN_ON(simd != 0); 887 888 wave_read_regs( 889 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 890 dst); 891 } 892 893 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 894 uint32_t xcc_id, uint32_t simd, 895 uint32_t wave, uint32_t thread, 896 uint32_t start, uint32_t size, 897 uint32_t *dst) 898 { 899 wave_read_regs( 900 adev, wave, thread, 901 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 902 } 903 904 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 905 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 906 { 907 soc24_grbm_select(adev, me, pipe, q, vm); 908 } 909 910 /* all sizes are in bytes */ 911 #define MQD_SHADOW_BASE_SIZE 73728 912 #define MQD_SHADOW_BASE_ALIGNMENT 256 913 #define MQD_FWWORKAREA_SIZE 484 914 #define MQD_FWWORKAREA_ALIGNMENT 256 915 916 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 917 struct amdgpu_gfx_shadow_info *shadow_info) 918 { 919 /* for gfx */ 920 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 921 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 922 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 923 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 924 /* for compute */ 925 shadow_info->eop_size = GFX12_MEC_HPD_SIZE; 926 shadow_info->eop_alignment = 256; 927 } 928 929 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 930 struct amdgpu_gfx_shadow_info *shadow_info, 931 bool skip_check) 932 { 933 if (adev->gfx.cp_gfx_shadow || skip_check) { 934 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 935 return 0; 936 } 937 938 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 939 return -EINVAL; 940 } 941 942 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 943 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 944 .select_se_sh = &gfx_v12_0_select_se_sh, 945 .read_wave_data = &gfx_v12_0_read_wave_data, 946 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 947 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 948 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 949 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 950 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 951 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 952 }; 953 954 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 955 { 956 957 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 958 case IP_VERSION(12, 0, 0): 959 case IP_VERSION(12, 0, 1): 960 adev->gfx.config.max_hw_contexts = 8; 961 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 962 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 963 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 964 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 965 break; 966 default: 967 BUG(); 968 break; 969 } 970 971 return 0; 972 } 973 974 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 975 int me, int pipe, int queue) 976 { 977 int r; 978 struct amdgpu_ring *ring; 979 unsigned int irq_type; 980 981 ring = &adev->gfx.gfx_ring[ring_id]; 982 983 ring->me = me; 984 ring->pipe = pipe; 985 ring->queue = queue; 986 987 ring->ring_obj = NULL; 988 ring->use_doorbell = true; 989 990 if (!ring_id) 991 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 992 else 993 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 994 ring->vm_hub = AMDGPU_GFXHUB(0); 995 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 996 997 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 998 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 999 AMDGPU_RING_PRIO_DEFAULT, NULL); 1000 if (r) 1001 return r; 1002 return 0; 1003 } 1004 1005 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1006 int mec, int pipe, int queue) 1007 { 1008 int r; 1009 unsigned irq_type; 1010 struct amdgpu_ring *ring; 1011 unsigned int hw_prio; 1012 1013 ring = &adev->gfx.compute_ring[ring_id]; 1014 1015 /* mec0 is me1 */ 1016 ring->me = mec + 1; 1017 ring->pipe = pipe; 1018 ring->queue = queue; 1019 1020 ring->ring_obj = NULL; 1021 ring->use_doorbell = true; 1022 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1023 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1024 + (ring_id * GFX12_MEC_HPD_SIZE); 1025 ring->vm_hub = AMDGPU_GFXHUB(0); 1026 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1027 1028 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1029 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1030 + ring->pipe; 1031 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1032 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1033 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1035 hw_prio, NULL); 1036 if (r) 1037 return r; 1038 1039 return 0; 1040 } 1041 1042 static struct { 1043 SOC24_FIRMWARE_ID id; 1044 unsigned int offset; 1045 unsigned int size; 1046 unsigned int size_x16; 1047 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1048 1049 #define RLC_TOC_OFFSET_DWUNIT 8 1050 #define RLC_SIZE_MULTIPLE 1024 1051 #define RLC_TOC_UMF_SIZE_inM 23ULL 1052 #define RLC_TOC_FORMAT_API 165ULL 1053 1054 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1055 { 1056 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1057 1058 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1059 rlc_autoload_info[ucode->id].id = ucode->id; 1060 rlc_autoload_info[ucode->id].offset = 1061 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1062 rlc_autoload_info[ucode->id].size = 1063 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1064 ucode->size * 4; 1065 ucode++; 1066 } 1067 } 1068 1069 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1070 { 1071 uint32_t total_size = 0; 1072 SOC24_FIRMWARE_ID id; 1073 1074 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1075 1076 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1077 total_size += rlc_autoload_info[id].size; 1078 1079 /* In case the offset in rlc toc ucode is aligned */ 1080 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1081 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1082 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1083 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1084 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1085 1086 return total_size; 1087 } 1088 1089 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1090 { 1091 int r; 1092 uint32_t total_size; 1093 1094 total_size = gfx_v12_0_calc_toc_total_size(adev); 1095 1096 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1097 AMDGPU_GEM_DOMAIN_VRAM, 1098 &adev->gfx.rlc.rlc_autoload_bo, 1099 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1100 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1101 1102 if (r) { 1103 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1104 return r; 1105 } 1106 1107 return 0; 1108 } 1109 1110 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1111 SOC24_FIRMWARE_ID id, 1112 const void *fw_data, 1113 uint32_t fw_size) 1114 { 1115 uint32_t toc_offset; 1116 uint32_t toc_fw_size; 1117 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1118 1119 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1120 return; 1121 1122 toc_offset = rlc_autoload_info[id].offset; 1123 toc_fw_size = rlc_autoload_info[id].size; 1124 1125 if (fw_size == 0) 1126 fw_size = toc_fw_size; 1127 1128 if (fw_size > toc_fw_size) 1129 fw_size = toc_fw_size; 1130 1131 memcpy(ptr + toc_offset, fw_data, fw_size); 1132 1133 if (fw_size < toc_fw_size) 1134 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1139 { 1140 void *data; 1141 uint32_t size; 1142 uint32_t *toc_ptr; 1143 1144 data = adev->psp.toc.start_addr; 1145 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1146 1147 toc_ptr = (uint32_t *)data + size / 4 - 2; 1148 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1149 1150 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1151 data, size); 1152 } 1153 1154 static void 1155 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1156 { 1157 const __le32 *fw_data; 1158 uint32_t fw_size; 1159 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1160 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1161 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1162 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1163 uint16_t version_major, version_minor; 1164 1165 /* pfp ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.pfp_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1181 fw_data, fw_size); 1182 /* me ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.me_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1198 fw_data, fw_size); 1199 /* mec ucode */ 1200 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1201 adev->gfx.mec_fw->data; 1202 /* instruction */ 1203 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1204 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1205 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1206 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1207 fw_data, fw_size); 1208 /* data */ 1209 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1210 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1211 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1212 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1213 fw_data, fw_size); 1214 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1215 fw_data, fw_size); 1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1217 fw_data, fw_size); 1218 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1219 fw_data, fw_size); 1220 1221 /* rlc ucode */ 1222 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1223 adev->gfx.rlc_fw->data; 1224 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1225 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1226 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1227 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1228 fw_data, fw_size); 1229 1230 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1231 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1232 if (version_major == 2) { 1233 if (version_minor >= 1) { 1234 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1235 1236 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1237 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1238 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1239 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1240 fw_data, fw_size); 1241 1242 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1243 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1244 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1245 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1246 fw_data, fw_size); 1247 } 1248 if (version_minor >= 2) { 1249 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1250 1251 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1252 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1253 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1254 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1255 fw_data, fw_size); 1256 1257 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1258 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1259 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1260 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1261 fw_data, fw_size); 1262 } 1263 } 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 uint32_t fw_size; 1271 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1272 1273 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1274 adev->sdma.instance[0].fw->data; 1275 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1276 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1277 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1278 1279 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1280 fw_data, fw_size); 1281 } 1282 1283 static void 1284 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1285 { 1286 const __le32 *fw_data; 1287 unsigned fw_size; 1288 const struct mes_firmware_header_v1_0 *mes_hdr; 1289 int pipe, ucode_id, data_id; 1290 1291 for (pipe = 0; pipe < 2; pipe++) { 1292 if (pipe == 0) { 1293 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1294 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1295 } else { 1296 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1297 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1298 } 1299 1300 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1301 adev->mes.fw[pipe]->data; 1302 1303 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1304 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1305 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1306 1307 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1308 1309 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1310 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1311 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1312 1313 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1314 } 1315 } 1316 1317 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1318 { 1319 uint32_t rlc_g_offset, rlc_g_size; 1320 uint64_t gpu_addr; 1321 uint32_t data; 1322 1323 /* RLC autoload sequence 2: copy ucode */ 1324 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1325 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1326 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1327 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1328 1329 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1330 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1331 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1332 1333 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1334 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1335 1336 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1337 1338 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1339 /* RLC autoload sequence 3: load IMU fw */ 1340 if (adev->gfx.imu.funcs->load_microcode) 1341 adev->gfx.imu.funcs->load_microcode(adev); 1342 /* RLC autoload sequence 4 init IMU fw */ 1343 if (adev->gfx.imu.funcs->setup_imu) 1344 adev->gfx.imu.funcs->setup_imu(adev); 1345 if (adev->gfx.imu.funcs->start_imu) 1346 adev->gfx.imu.funcs->start_imu(adev); 1347 1348 /* RLC autoload sequence 5 disable gpa mode */ 1349 gfx_v12_0_disable_gpa_mode(adev); 1350 } else { 1351 /* unhalt rlc to start autoload without imu */ 1352 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1353 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1354 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1355 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1356 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1357 } 1358 1359 return 0; 1360 } 1361 1362 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1363 { 1364 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1365 uint32_t *ptr; 1366 uint32_t inst; 1367 1368 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1369 if (!ptr) { 1370 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1371 adev->gfx.ip_dump_core = NULL; 1372 } else { 1373 adev->gfx.ip_dump_core = ptr; 1374 } 1375 1376 /* Allocate memory for compute queue registers for all the instances */ 1377 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1378 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1379 adev->gfx.mec.num_queue_per_pipe; 1380 1381 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1382 if (!ptr) { 1383 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1384 adev->gfx.ip_dump_compute_queues = NULL; 1385 } else { 1386 adev->gfx.ip_dump_compute_queues = ptr; 1387 } 1388 1389 /* Allocate memory for gfx queue registers for all the instances */ 1390 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1391 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1392 adev->gfx.me.num_queue_per_pipe; 1393 1394 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1395 if (!ptr) { 1396 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1397 adev->gfx.ip_dump_gfx_queues = NULL; 1398 } else { 1399 adev->gfx.ip_dump_gfx_queues = ptr; 1400 } 1401 } 1402 1403 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1404 { 1405 int i, j, k, r, ring_id = 0; 1406 unsigned num_compute_rings; 1407 int xcc_id = 0; 1408 struct amdgpu_device *adev = ip_block->adev; 1409 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1410 1411 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1412 1413 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1414 case IP_VERSION(12, 0, 0): 1415 case IP_VERSION(12, 0, 1): 1416 adev->gfx.me.num_me = 1; 1417 adev->gfx.me.num_pipe_per_me = 1; 1418 adev->gfx.me.num_queue_per_pipe = 8; 1419 adev->gfx.mec.num_mec = 1; 1420 adev->gfx.mec.num_pipe_per_mec = 2; 1421 adev->gfx.mec.num_queue_per_pipe = 4; 1422 break; 1423 default: 1424 adev->gfx.me.num_me = 1; 1425 adev->gfx.me.num_pipe_per_me = 1; 1426 adev->gfx.me.num_queue_per_pipe = 1; 1427 adev->gfx.mec.num_mec = 1; 1428 adev->gfx.mec.num_pipe_per_mec = 4; 1429 adev->gfx.mec.num_queue_per_pipe = 8; 1430 break; 1431 } 1432 1433 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1434 case IP_VERSION(12, 0, 0): 1435 case IP_VERSION(12, 0, 1): 1436 if (!adev->gfx.disable_uq && 1437 adev->gfx.me_fw_version >= 2780 && 1438 adev->gfx.pfp_fw_version >= 2840 && 1439 adev->gfx.mec_fw_version >= 3050 && 1440 adev->mes.fw_version[0] >= 123) { 1441 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1442 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1443 } 1444 break; 1445 default: 1446 break; 1447 } 1448 1449 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1450 case IP_VERSION(12, 0, 0): 1451 case IP_VERSION(12, 0, 1): 1452 if (adev->gfx.me_fw_version >= 2480 && 1453 adev->gfx.pfp_fw_version >= 2530 && 1454 adev->gfx.mec_fw_version >= 2680 && 1455 adev->mes.fw_version[0] >= 100) 1456 adev->gfx.enable_cleaner_shader = true; 1457 break; 1458 default: 1459 adev->gfx.enable_cleaner_shader = false; 1460 break; 1461 } 1462 1463 if (adev->gfx.num_compute_rings) { 1464 /* recalculate compute rings to use based on hardware configuration */ 1465 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1466 adev->gfx.mec.num_queue_per_pipe) / 2; 1467 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1468 num_compute_rings); 1469 } 1470 1471 /* EOP Event */ 1472 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1473 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1474 &adev->gfx.eop_irq); 1475 if (r) 1476 return r; 1477 1478 /* Bad opcode Event */ 1479 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1480 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1481 &adev->gfx.bad_op_irq); 1482 if (r) 1483 return r; 1484 1485 /* Privileged reg */ 1486 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1487 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1488 &adev->gfx.priv_reg_irq); 1489 if (r) 1490 return r; 1491 1492 /* Privileged inst */ 1493 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1494 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1495 &adev->gfx.priv_inst_irq); 1496 if (r) 1497 return r; 1498 1499 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1500 1501 gfx_v12_0_me_init(adev); 1502 1503 r = gfx_v12_0_rlc_init(adev); 1504 if (r) { 1505 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1506 return r; 1507 } 1508 1509 r = gfx_v12_0_mec_init(adev); 1510 if (r) { 1511 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1512 return r; 1513 } 1514 1515 if (adev->gfx.num_gfx_rings) { 1516 /* set up the gfx ring */ 1517 for (i = 0; i < adev->gfx.me.num_me; i++) { 1518 for (j = 0; j < num_queue_per_pipe; j++) { 1519 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1520 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1521 continue; 1522 1523 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1524 i, k, j); 1525 if (r) 1526 return r; 1527 ring_id++; 1528 } 1529 } 1530 } 1531 } 1532 1533 if (adev->gfx.num_compute_rings) { 1534 ring_id = 0; 1535 /* set up the compute queues - allocate horizontally across pipes */ 1536 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1537 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1538 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1539 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1540 0, i, k, j)) 1541 continue; 1542 1543 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1544 i, k, j); 1545 if (r) 1546 return r; 1547 1548 ring_id++; 1549 } 1550 } 1551 } 1552 } 1553 1554 adev->gfx.gfx_supported_reset = 1555 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1556 adev->gfx.compute_supported_reset = 1557 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1558 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1559 case IP_VERSION(12, 0, 0): 1560 case IP_VERSION(12, 0, 1): 1561 if ((adev->gfx.me_fw_version >= 2660) && 1562 (adev->gfx.mec_fw_version >= 2920) && 1563 !amdgpu_sriov_vf(adev) && 1564 !adev->debug_disable_gpu_ring_reset) { 1565 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1566 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1567 } 1568 break; 1569 default: 1570 break; 1571 } 1572 1573 if (!adev->enable_mes_kiq) { 1574 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1575 if (r) { 1576 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1577 return r; 1578 } 1579 1580 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1581 if (r) 1582 return r; 1583 } 1584 1585 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1586 if (r) 1587 return r; 1588 1589 /* allocate visible FB for rlc auto-loading fw */ 1590 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1591 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1592 if (r) 1593 return r; 1594 } 1595 1596 r = gfx_v12_0_gpu_early_init(adev); 1597 if (r) 1598 return r; 1599 1600 r = amdgpu_gfx_sysfs_init(adev); 1601 if (r) 1602 return r; 1603 1604 gfx_v12_0_alloc_ip_dump(adev); 1605 1606 adev->gfx.me.use_mmio_for_reset = false; 1607 adev->gfx.mec.use_mmio_for_reset = true; 1608 1609 mutex_init(&adev->gfx.mec.reset_mutex); 1610 1611 return 0; 1612 } 1613 1614 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1615 { 1616 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1617 &adev->gfx.pfp.pfp_fw_gpu_addr, 1618 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1619 1620 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1621 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1622 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1623 } 1624 1625 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1626 { 1627 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1628 &adev->gfx.me.me_fw_gpu_addr, 1629 (void **)&adev->gfx.me.me_fw_ptr); 1630 1631 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1632 &adev->gfx.me.me_fw_data_gpu_addr, 1633 (void **)&adev->gfx.me.me_fw_data_ptr); 1634 } 1635 1636 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1637 { 1638 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1639 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1640 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1641 } 1642 1643 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1644 { 1645 int i; 1646 struct amdgpu_device *adev = ip_block->adev; 1647 1648 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1649 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1650 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1651 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1652 1653 amdgpu_gfx_mqd_sw_fini(adev, 0); 1654 1655 if (!adev->enable_mes_kiq) { 1656 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1657 amdgpu_gfx_kiq_fini(adev, 0); 1658 } 1659 1660 gfx_v12_0_pfp_fini(adev); 1661 gfx_v12_0_me_fini(adev); 1662 gfx_v12_0_rlc_fini(adev); 1663 gfx_v12_0_mec_fini(adev); 1664 1665 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1666 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1667 1668 gfx_v12_0_free_microcode(adev); 1669 1670 amdgpu_gfx_sysfs_fini(adev); 1671 1672 kfree(adev->gfx.ip_dump_core); 1673 kfree(adev->gfx.ip_dump_compute_queues); 1674 kfree(adev->gfx.ip_dump_gfx_queues); 1675 1676 return 0; 1677 } 1678 1679 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1680 u32 sh_num, u32 instance, int xcc_id) 1681 { 1682 u32 data; 1683 1684 if (instance == 0xffffffff) 1685 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1686 INSTANCE_BROADCAST_WRITES, 1); 1687 else 1688 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1689 instance); 1690 1691 if (se_num == 0xffffffff) 1692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1693 1); 1694 else 1695 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1696 1697 if (sh_num == 0xffffffff) 1698 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1699 1); 1700 else 1701 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1702 1703 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1704 } 1705 1706 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1707 { 1708 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1709 1710 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1711 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1712 GRBM_CC_GC_SA_UNIT_DISABLE, 1713 SA_DISABLE); 1714 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1715 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1716 GRBM_GC_USER_SA_UNIT_DISABLE, 1717 SA_DISABLE); 1718 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1719 adev->gfx.config.max_shader_engines); 1720 1721 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1722 } 1723 1724 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1725 { 1726 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1727 u32 rb_mask; 1728 1729 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1730 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1731 CC_RB_BACKEND_DISABLE, 1732 BACKEND_DISABLE); 1733 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1734 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1735 GC_USER_RB_BACKEND_DISABLE, 1736 BACKEND_DISABLE); 1737 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1738 adev->gfx.config.max_shader_engines); 1739 1740 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1741 } 1742 1743 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1744 { 1745 u32 rb_bitmap_per_sa; 1746 u32 rb_bitmap_width_per_sa; 1747 u32 max_sa; 1748 u32 active_sa_bitmap; 1749 u32 global_active_rb_bitmap; 1750 u32 active_rb_bitmap = 0; 1751 u32 i; 1752 1753 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1754 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1755 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1756 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1757 1758 /* generate active rb bitmap according to active sa bitmap */ 1759 max_sa = adev->gfx.config.max_shader_engines * 1760 adev->gfx.config.max_sh_per_se; 1761 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1762 adev->gfx.config.max_sh_per_se; 1763 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1764 1765 for (i = 0; i < max_sa; i++) { 1766 if (active_sa_bitmap & (1 << i)) 1767 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1768 } 1769 1770 active_rb_bitmap &= global_active_rb_bitmap; 1771 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1772 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1773 } 1774 1775 #define LDS_APP_BASE 0x1 1776 #define SCRATCH_APP_BASE 0x2 1777 1778 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1779 { 1780 int i; 1781 uint32_t sh_mem_bases; 1782 uint32_t data; 1783 1784 /* 1785 * Configure apertures: 1786 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1787 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1788 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1789 */ 1790 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1791 SCRATCH_APP_BASE; 1792 1793 mutex_lock(&adev->srbm_mutex); 1794 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1795 soc24_grbm_select(adev, 0, 0, 0, i); 1796 /* CP and shaders */ 1797 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1798 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1799 1800 /* Enable trap for each kfd vmid. */ 1801 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1802 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1803 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1804 } 1805 soc24_grbm_select(adev, 0, 0, 0, 0); 1806 mutex_unlock(&adev->srbm_mutex); 1807 } 1808 1809 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1810 { 1811 /* TODO: harvest feature to be added later. */ 1812 } 1813 1814 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1815 { 1816 } 1817 1818 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1819 { 1820 u32 tmp; 1821 int i; 1822 1823 if (!amdgpu_sriov_vf(adev)) 1824 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1825 1826 gfx_v12_0_setup_rb(adev); 1827 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1828 gfx_v12_0_get_tcc_info(adev); 1829 adev->gfx.config.pa_sc_tile_steering_override = 0; 1830 /* Program DB_RING_CONTROL for multiple GFX pipes 1831 * Default power up value is 1. 1832 * Possible values: 1833 * 0 - split occlusion counters between gfx pipes 1834 * 1 - all occlusion counters to pipe 0 1835 * 2 - all occlusion counters to pipe 1 1836 */ 1837 WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, 1838 (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); 1839 1840 /* XXX SH_MEM regs */ 1841 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1842 mutex_lock(&adev->srbm_mutex); 1843 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1844 soc24_grbm_select(adev, 0, 0, 0, i); 1845 /* CP and shaders */ 1846 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1847 if (i != 0) { 1848 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1849 (adev->gmc.private_aperture_start >> 48)); 1850 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1851 (adev->gmc.shared_aperture_start >> 48)); 1852 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1853 } 1854 } 1855 soc24_grbm_select(adev, 0, 0, 0, 0); 1856 1857 mutex_unlock(&adev->srbm_mutex); 1858 1859 gfx_v12_0_init_compute_vmid(adev); 1860 } 1861 1862 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1863 int me, int pipe) 1864 { 1865 if (me != 0) 1866 return 0; 1867 1868 switch (pipe) { 1869 case 0: 1870 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1871 default: 1872 return 0; 1873 } 1874 } 1875 1876 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1877 int me, int pipe) 1878 { 1879 /* 1880 * amdgpu controls only the first MEC. That's why this function only 1881 * handles the setting of interrupts for this specific MEC. All other 1882 * pipes' interrupts are set by amdkfd. 1883 */ 1884 if (me != 1) 1885 return 0; 1886 1887 switch (pipe) { 1888 case 0: 1889 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1890 case 1: 1891 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1892 default: 1893 return 0; 1894 } 1895 } 1896 1897 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1898 bool enable) 1899 { 1900 u32 tmp, cp_int_cntl_reg; 1901 int i, j; 1902 1903 if (amdgpu_sriov_vf(adev)) 1904 return; 1905 1906 for (i = 0; i < adev->gfx.me.num_me; i++) { 1907 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1908 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1909 1910 if (cp_int_cntl_reg) { 1911 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1912 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1913 enable ? 1 : 0); 1914 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1915 enable ? 1 : 0); 1916 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1917 enable ? 1 : 0); 1918 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1919 enable ? 1 : 0); 1920 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1921 } 1922 } 1923 } 1924 } 1925 1926 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1927 { 1928 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1929 1930 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1931 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1932 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1933 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1934 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1935 1936 return 0; 1937 } 1938 1939 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1940 { 1941 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1942 1943 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1944 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1945 } 1946 1947 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1948 { 1949 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1950 udelay(50); 1951 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1952 udelay(50); 1953 } 1954 1955 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1956 bool enable) 1957 { 1958 uint32_t rlc_pg_cntl; 1959 1960 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1961 1962 if (!enable) { 1963 /* RLC_PG_CNTL[23] = 0 (default) 1964 * RLC will wait for handshake acks with SMU 1965 * GFXOFF will be enabled 1966 * RLC_PG_CNTL[23] = 1 1967 * RLC will not issue any message to SMU 1968 * hence no handshake between SMU & RLC 1969 * GFXOFF will be disabled 1970 */ 1971 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1972 } else 1973 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1974 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1975 } 1976 1977 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1978 { 1979 /* TODO: enable rlc & smu handshake until smu 1980 * and gfxoff feature works as expected */ 1981 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1982 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1983 1984 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1985 udelay(50); 1986 } 1987 1988 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1989 { 1990 uint32_t tmp; 1991 1992 /* enable Save Restore Machine */ 1993 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1994 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1995 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1996 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1997 } 1998 1999 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 2000 { 2001 const struct rlc_firmware_header_v2_0 *hdr; 2002 const __le32 *fw_data; 2003 unsigned i, fw_size; 2004 2005 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2006 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2007 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2008 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2009 2010 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2011 RLCG_UCODE_LOADING_START_ADDRESS); 2012 2013 for (i = 0; i < fw_size; i++) 2014 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2015 le32_to_cpup(fw_data++)); 2016 2017 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2018 } 2019 2020 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2021 { 2022 const struct rlc_firmware_header_v2_2 *hdr; 2023 const __le32 *fw_data; 2024 unsigned i, fw_size; 2025 u32 tmp; 2026 2027 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2028 2029 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2030 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2031 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2032 2033 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2034 2035 for (i = 0; i < fw_size; i++) { 2036 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2037 msleep(1); 2038 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2039 le32_to_cpup(fw_data++)); 2040 } 2041 2042 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2043 2044 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2045 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2046 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2047 2048 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2049 for (i = 0; i < fw_size; i++) { 2050 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2051 msleep(1); 2052 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2053 le32_to_cpup(fw_data++)); 2054 } 2055 2056 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2057 2058 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2059 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2060 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2061 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2062 } 2063 2064 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2065 { 2066 const struct rlc_firmware_header_v2_0 *hdr; 2067 uint16_t version_major; 2068 uint16_t version_minor; 2069 2070 if (!adev->gfx.rlc_fw) 2071 return -EINVAL; 2072 2073 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2074 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2075 2076 version_major = le16_to_cpu(hdr->header.header_version_major); 2077 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2078 2079 if (version_major == 2) { 2080 gfx_v12_0_load_rlcg_microcode(adev); 2081 if (amdgpu_dpm == 1) { 2082 if (version_minor >= 2) 2083 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2084 } 2085 2086 return 0; 2087 } 2088 2089 return -EINVAL; 2090 } 2091 2092 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2093 { 2094 int r; 2095 2096 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2097 gfx_v12_0_init_csb(adev); 2098 2099 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2100 gfx_v12_0_rlc_enable_srm(adev); 2101 } else { 2102 if (amdgpu_sriov_vf(adev)) { 2103 gfx_v12_0_init_csb(adev); 2104 return 0; 2105 } 2106 2107 adev->gfx.rlc.funcs->stop(adev); 2108 2109 /* disable CG */ 2110 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2111 2112 /* disable PG */ 2113 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2114 2115 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2116 /* legacy rlc firmware loading */ 2117 r = gfx_v12_0_rlc_load_microcode(adev); 2118 if (r) 2119 return r; 2120 } 2121 2122 gfx_v12_0_init_csb(adev); 2123 2124 adev->gfx.rlc.funcs->start(adev); 2125 } 2126 2127 return 0; 2128 } 2129 2130 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2131 { 2132 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2133 const struct gfx_firmware_header_v2_0 *me_hdr; 2134 const struct gfx_firmware_header_v2_0 *mec_hdr; 2135 uint32_t pipe_id, tmp; 2136 2137 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2138 adev->gfx.mec_fw->data; 2139 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2140 adev->gfx.me_fw->data; 2141 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2142 adev->gfx.pfp_fw->data; 2143 2144 /* config pfp program start addr */ 2145 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2146 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2147 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2148 (pfp_hdr->ucode_start_addr_hi << 30) | 2149 (pfp_hdr->ucode_start_addr_lo >> 2)); 2150 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2151 pfp_hdr->ucode_start_addr_hi >> 2); 2152 } 2153 soc24_grbm_select(adev, 0, 0, 0, 0); 2154 2155 /* reset pfp pipe */ 2156 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2157 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2159 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2160 2161 /* clear pfp pipe reset */ 2162 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2163 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2164 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2165 2166 /* config me program start addr */ 2167 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2168 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2169 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2170 (me_hdr->ucode_start_addr_hi << 30) | 2171 (me_hdr->ucode_start_addr_lo >> 2)); 2172 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2173 me_hdr->ucode_start_addr_hi>>2); 2174 } 2175 soc24_grbm_select(adev, 0, 0, 0, 0); 2176 2177 /* reset me pipe */ 2178 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2179 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2180 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2181 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2182 2183 /* clear me pipe reset */ 2184 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2185 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2186 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2187 2188 /* config mec program start addr */ 2189 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2190 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2192 mec_hdr->ucode_start_addr_lo >> 2 | 2193 mec_hdr->ucode_start_addr_hi << 30); 2194 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2195 mec_hdr->ucode_start_addr_hi >> 2); 2196 } 2197 soc24_grbm_select(adev, 0, 0, 0, 0); 2198 2199 /* reset mec pipe */ 2200 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2201 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2202 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2203 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2204 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2205 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2206 2207 /* clear mec pipe reset */ 2208 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2209 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2210 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2211 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2212 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2213 } 2214 2215 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2216 { 2217 const struct gfx_firmware_header_v2_0 *cp_hdr; 2218 unsigned pipe_id, tmp; 2219 2220 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2221 adev->gfx.pfp_fw->data; 2222 mutex_lock(&adev->srbm_mutex); 2223 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2224 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2225 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2226 (cp_hdr->ucode_start_addr_hi << 30) | 2227 (cp_hdr->ucode_start_addr_lo >> 2)); 2228 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2229 cp_hdr->ucode_start_addr_hi>>2); 2230 2231 /* 2232 * Program CP_ME_CNTL to reset given PIPE to take 2233 * effect of CP_PFP_PRGRM_CNTR_START. 2234 */ 2235 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2236 if (pipe_id == 0) 2237 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2238 PFP_PIPE0_RESET, 1); 2239 else 2240 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2241 PFP_PIPE1_RESET, 1); 2242 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2243 2244 /* Clear pfp pipe0 reset bit. */ 2245 if (pipe_id == 0) 2246 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2247 PFP_PIPE0_RESET, 0); 2248 else 2249 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2250 PFP_PIPE1_RESET, 0); 2251 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2252 } 2253 soc24_grbm_select(adev, 0, 0, 0, 0); 2254 mutex_unlock(&adev->srbm_mutex); 2255 } 2256 2257 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2258 { 2259 const struct gfx_firmware_header_v2_0 *cp_hdr; 2260 unsigned pipe_id, tmp; 2261 2262 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2263 adev->gfx.me_fw->data; 2264 mutex_lock(&adev->srbm_mutex); 2265 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2266 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2267 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2268 (cp_hdr->ucode_start_addr_hi << 30) | 2269 (cp_hdr->ucode_start_addr_lo >> 2) ); 2270 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2271 cp_hdr->ucode_start_addr_hi>>2); 2272 2273 /* 2274 * Program CP_ME_CNTL to reset given PIPE to take 2275 * effect of CP_ME_PRGRM_CNTR_START. 2276 */ 2277 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2278 if (pipe_id == 0) 2279 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2280 ME_PIPE0_RESET, 1); 2281 else 2282 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2283 ME_PIPE1_RESET, 1); 2284 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2285 2286 /* Clear pfp pipe0 reset bit. */ 2287 if (pipe_id == 0) 2288 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2289 ME_PIPE0_RESET, 0); 2290 else 2291 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2292 ME_PIPE1_RESET, 0); 2293 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2294 } 2295 soc24_grbm_select(adev, 0, 0, 0, 0); 2296 mutex_unlock(&adev->srbm_mutex); 2297 } 2298 2299 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2300 { 2301 const struct gfx_firmware_header_v2_0 *cp_hdr; 2302 unsigned pipe_id; 2303 2304 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2305 adev->gfx.mec_fw->data; 2306 mutex_lock(&adev->srbm_mutex); 2307 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2308 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2309 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2310 cp_hdr->ucode_start_addr_lo >> 2 | 2311 cp_hdr->ucode_start_addr_hi << 30); 2312 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2313 cp_hdr->ucode_start_addr_hi >> 2); 2314 } 2315 soc24_grbm_select(adev, 0, 0, 0, 0); 2316 mutex_unlock(&adev->srbm_mutex); 2317 } 2318 2319 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2320 { 2321 uint32_t cp_status; 2322 uint32_t bootload_status; 2323 int i; 2324 2325 for (i = 0; i < adev->usec_timeout; i++) { 2326 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2327 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2328 2329 if ((cp_status == 0) && 2330 (REG_GET_FIELD(bootload_status, 2331 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2332 break; 2333 } 2334 udelay(1); 2335 if (amdgpu_emu_mode) 2336 msleep(10); 2337 } 2338 2339 if (i >= adev->usec_timeout) { 2340 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2341 return -ETIMEDOUT; 2342 } 2343 2344 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2345 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2346 gfx_v12_0_set_me_ucode_start_addr(adev); 2347 gfx_v12_0_set_mec_ucode_start_addr(adev); 2348 } 2349 2350 return 0; 2351 } 2352 2353 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2354 { 2355 int i; 2356 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2357 2358 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2359 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2360 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2361 2362 for (i = 0; i < adev->usec_timeout; i++) { 2363 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2364 break; 2365 udelay(1); 2366 } 2367 2368 if (i >= adev->usec_timeout) 2369 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2370 2371 return 0; 2372 } 2373 2374 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2375 { 2376 int r; 2377 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2378 const __le32 *fw_ucode, *fw_data; 2379 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2380 uint32_t tmp; 2381 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2382 2383 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2384 adev->gfx.pfp_fw->data; 2385 2386 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2387 2388 /* instruction */ 2389 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2390 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2391 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2392 /* data */ 2393 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2394 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2395 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2396 2397 /* 64kb align */ 2398 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2399 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2400 &adev->gfx.pfp.pfp_fw_obj, 2401 &adev->gfx.pfp.pfp_fw_gpu_addr, 2402 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2403 if (r) { 2404 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2405 gfx_v12_0_pfp_fini(adev); 2406 return r; 2407 } 2408 2409 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2410 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2411 &adev->gfx.pfp.pfp_fw_data_obj, 2412 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2413 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2414 if (r) { 2415 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2416 gfx_v12_0_pfp_fini(adev); 2417 return r; 2418 } 2419 2420 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2421 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2422 2423 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2424 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2425 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2426 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2427 2428 if (amdgpu_emu_mode == 1) 2429 amdgpu_device_flush_hdp(adev, NULL); 2430 2431 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2432 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2433 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2434 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2435 2436 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2437 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2438 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2439 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2440 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2441 2442 /* 2443 * Programming any of the CP_PFP_IC_BASE registers 2444 * forces invalidation of the ME L1 I$. Wait for the 2445 * invalidation complete 2446 */ 2447 for (i = 0; i < usec_timeout; i++) { 2448 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2449 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2450 INVALIDATE_CACHE_COMPLETE)) 2451 break; 2452 udelay(1); 2453 } 2454 2455 if (i >= usec_timeout) { 2456 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2457 return -EINVAL; 2458 } 2459 2460 /* Prime the L1 instruction caches */ 2461 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2462 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2463 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2464 /* Waiting for cache primed*/ 2465 for (i = 0; i < usec_timeout; i++) { 2466 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2467 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2468 ICACHE_PRIMED)) 2469 break; 2470 udelay(1); 2471 } 2472 2473 if (i >= usec_timeout) { 2474 dev_err(adev->dev, "failed to prime instruction cache\n"); 2475 return -EINVAL; 2476 } 2477 2478 mutex_lock(&adev->srbm_mutex); 2479 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2480 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2481 2482 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2483 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2484 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2485 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2486 } 2487 soc24_grbm_select(adev, 0, 0, 0, 0); 2488 mutex_unlock(&adev->srbm_mutex); 2489 2490 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2491 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2492 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2493 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2494 2495 /* Invalidate the data caches */ 2496 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2497 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2498 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2499 2500 for (i = 0; i < usec_timeout; i++) { 2501 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2502 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2503 INVALIDATE_DCACHE_COMPLETE)) 2504 break; 2505 udelay(1); 2506 } 2507 2508 if (i >= usec_timeout) { 2509 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2510 return -EINVAL; 2511 } 2512 2513 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2514 2515 return 0; 2516 } 2517 2518 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2519 { 2520 int r; 2521 const struct gfx_firmware_header_v2_0 *me_hdr; 2522 const __le32 *fw_ucode, *fw_data; 2523 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2524 uint32_t tmp; 2525 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2526 2527 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2528 adev->gfx.me_fw->data; 2529 2530 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2531 2532 /* instruction */ 2533 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2534 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2535 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2536 /* data */ 2537 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2538 le32_to_cpu(me_hdr->data_offset_bytes)); 2539 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2540 2541 /* 64kb align*/ 2542 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2543 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2544 &adev->gfx.me.me_fw_obj, 2545 &adev->gfx.me.me_fw_gpu_addr, 2546 (void **)&adev->gfx.me.me_fw_ptr); 2547 if (r) { 2548 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2549 gfx_v12_0_me_fini(adev); 2550 return r; 2551 } 2552 2553 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2554 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2555 &adev->gfx.me.me_fw_data_obj, 2556 &adev->gfx.me.me_fw_data_gpu_addr, 2557 (void **)&adev->gfx.me.me_fw_data_ptr); 2558 if (r) { 2559 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2560 gfx_v12_0_me_fini(adev); 2561 return r; 2562 } 2563 2564 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2565 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2566 2567 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2568 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2569 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2570 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2571 2572 if (amdgpu_emu_mode == 1) 2573 amdgpu_device_flush_hdp(adev, NULL); 2574 2575 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2576 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2577 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2578 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2579 2580 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2581 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2582 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2583 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2584 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2585 2586 /* 2587 * Programming any of the CP_ME_IC_BASE registers 2588 * forces invalidation of the ME L1 I$. Wait for the 2589 * invalidation complete 2590 */ 2591 for (i = 0; i < usec_timeout; i++) { 2592 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2593 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2594 INVALIDATE_CACHE_COMPLETE)) 2595 break; 2596 udelay(1); 2597 } 2598 2599 if (i >= usec_timeout) { 2600 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2601 return -EINVAL; 2602 } 2603 2604 /* Prime the instruction caches */ 2605 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2606 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2607 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2608 2609 /* Waiting for instruction cache primed*/ 2610 for (i = 0; i < usec_timeout; i++) { 2611 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2612 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2613 ICACHE_PRIMED)) 2614 break; 2615 udelay(1); 2616 } 2617 2618 if (i >= usec_timeout) { 2619 dev_err(adev->dev, "failed to prime instruction cache\n"); 2620 return -EINVAL; 2621 } 2622 2623 mutex_lock(&adev->srbm_mutex); 2624 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2625 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2626 2627 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2628 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2629 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2630 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2631 } 2632 soc24_grbm_select(adev, 0, 0, 0, 0); 2633 mutex_unlock(&adev->srbm_mutex); 2634 2635 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2636 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2637 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2638 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2639 2640 /* Invalidate the data caches */ 2641 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2642 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2643 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2644 2645 for (i = 0; i < usec_timeout; i++) { 2646 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2647 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2648 INVALIDATE_DCACHE_COMPLETE)) 2649 break; 2650 udelay(1); 2651 } 2652 2653 if (i >= usec_timeout) { 2654 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2655 return -EINVAL; 2656 } 2657 2658 gfx_v12_0_set_me_ucode_start_addr(adev); 2659 2660 return 0; 2661 } 2662 2663 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2664 { 2665 int r; 2666 2667 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2668 return -EINVAL; 2669 2670 gfx_v12_0_cp_gfx_enable(adev, false); 2671 2672 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2673 if (r) { 2674 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2675 return r; 2676 } 2677 2678 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2679 if (r) { 2680 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2681 return r; 2682 } 2683 2684 return 0; 2685 } 2686 2687 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2688 { 2689 /* init the CP */ 2690 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2691 adev->gfx.config.max_hw_contexts - 1); 2692 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2693 2694 if (!amdgpu_async_gfx_ring) 2695 gfx_v12_0_cp_gfx_enable(adev, true); 2696 2697 return 0; 2698 } 2699 2700 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2701 CP_PIPE_ID pipe) 2702 { 2703 u32 tmp; 2704 2705 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2706 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2707 2708 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2709 } 2710 2711 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2712 struct amdgpu_ring *ring) 2713 { 2714 u32 tmp; 2715 2716 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2717 if (ring->use_doorbell) { 2718 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2719 DOORBELL_OFFSET, ring->doorbell_index); 2720 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2721 DOORBELL_EN, 1); 2722 } else { 2723 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2724 DOORBELL_EN, 0); 2725 } 2726 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2727 2728 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2729 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2730 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2731 2732 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2733 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2734 } 2735 2736 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2737 { 2738 struct amdgpu_ring *ring; 2739 u32 tmp; 2740 u32 rb_bufsz; 2741 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2742 2743 /* Set the write pointer delay */ 2744 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2745 2746 /* set the RB to use vmid 0 */ 2747 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2748 2749 /* Init gfx ring 0 for pipe 0 */ 2750 mutex_lock(&adev->srbm_mutex); 2751 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2752 2753 /* Set ring buffer size */ 2754 ring = &adev->gfx.gfx_ring[0]; 2755 rb_bufsz = order_base_2(ring->ring_size / 8); 2756 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2757 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2758 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2759 2760 /* Initialize the ring buffer's write pointers */ 2761 ring->wptr = 0; 2762 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2763 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2764 2765 /* set the wb address whether it's enabled or not */ 2766 rptr_addr = ring->rptr_gpu_addr; 2767 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2768 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2769 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2770 2771 wptr_gpu_addr = ring->wptr_gpu_addr; 2772 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2773 lower_32_bits(wptr_gpu_addr)); 2774 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2775 upper_32_bits(wptr_gpu_addr)); 2776 2777 mdelay(1); 2778 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2779 2780 rb_addr = ring->gpu_addr >> 8; 2781 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2782 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2783 2784 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2785 2786 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2787 mutex_unlock(&adev->srbm_mutex); 2788 2789 /* Switch to pipe 0 */ 2790 mutex_lock(&adev->srbm_mutex); 2791 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2792 mutex_unlock(&adev->srbm_mutex); 2793 2794 /* start the ring */ 2795 gfx_v12_0_cp_gfx_start(adev); 2796 return 0; 2797 } 2798 2799 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2800 { 2801 u32 data; 2802 2803 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2804 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2805 enable ? 0 : 1); 2806 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2807 enable ? 0 : 1); 2808 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2809 enable ? 0 : 1); 2810 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2811 enable ? 0 : 1); 2812 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2813 enable ? 0 : 1); 2814 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2815 enable ? 1 : 0); 2816 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2817 enable ? 1 : 0); 2818 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2819 enable ? 1 : 0); 2820 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2821 enable ? 1 : 0); 2822 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2823 enable ? 0 : 1); 2824 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2825 2826 adev->gfx.kiq[0].ring.sched.ready = enable; 2827 2828 udelay(50); 2829 } 2830 2831 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2832 { 2833 const struct gfx_firmware_header_v2_0 *mec_hdr; 2834 const __le32 *fw_ucode, *fw_data; 2835 u32 tmp, fw_ucode_size, fw_data_size; 2836 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2837 u32 *fw_ucode_ptr, *fw_data_ptr; 2838 int r; 2839 2840 if (!adev->gfx.mec_fw) 2841 return -EINVAL; 2842 2843 gfx_v12_0_cp_compute_enable(adev, false); 2844 2845 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2846 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2847 2848 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2849 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2850 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2851 2852 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2853 le32_to_cpu(mec_hdr->data_offset_bytes)); 2854 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2855 2856 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2857 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2858 &adev->gfx.mec.mec_fw_obj, 2859 &adev->gfx.mec.mec_fw_gpu_addr, 2860 (void **)&fw_ucode_ptr); 2861 if (r) { 2862 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2863 gfx_v12_0_mec_fini(adev); 2864 return r; 2865 } 2866 2867 r = amdgpu_bo_create_reserved(adev, 2868 ALIGN(fw_data_size, 64 * 1024) * 2869 adev->gfx.mec.num_pipe_per_mec, 2870 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2871 &adev->gfx.mec.mec_fw_data_obj, 2872 &adev->gfx.mec.mec_fw_data_gpu_addr, 2873 (void **)&fw_data_ptr); 2874 if (r) { 2875 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2876 gfx_v12_0_mec_fini(adev); 2877 return r; 2878 } 2879 2880 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2881 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2882 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2883 } 2884 2885 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2886 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2887 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2888 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2889 2890 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2891 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2892 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2893 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2894 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2895 2896 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2897 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2898 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2899 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2900 2901 mutex_lock(&adev->srbm_mutex); 2902 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2903 soc24_grbm_select(adev, 1, i, 0, 0); 2904 2905 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2906 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2907 i * ALIGN(fw_data_size, 64 * 1024))); 2908 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2909 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2910 i * ALIGN(fw_data_size, 64 * 1024))); 2911 2912 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2913 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2914 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2915 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2916 } 2917 mutex_unlock(&adev->srbm_mutex); 2918 soc24_grbm_select(adev, 0, 0, 0, 0); 2919 2920 /* Trigger an invalidation of the L1 instruction caches */ 2921 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2922 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2923 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2924 2925 /* Wait for invalidation complete */ 2926 for (i = 0; i < usec_timeout; i++) { 2927 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2928 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2929 INVALIDATE_DCACHE_COMPLETE)) 2930 break; 2931 udelay(1); 2932 } 2933 2934 if (i >= usec_timeout) { 2935 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2936 return -EINVAL; 2937 } 2938 2939 /* Trigger an invalidation of the L1 instruction caches */ 2940 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2941 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2942 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2943 2944 /* Wait for invalidation complete */ 2945 for (i = 0; i < usec_timeout; i++) { 2946 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2947 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2948 INVALIDATE_CACHE_COMPLETE)) 2949 break; 2950 udelay(1); 2951 } 2952 2953 if (i >= usec_timeout) { 2954 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2955 return -EINVAL; 2956 } 2957 2958 gfx_v12_0_set_mec_ucode_start_addr(adev); 2959 2960 return 0; 2961 } 2962 2963 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2964 { 2965 uint32_t tmp; 2966 struct amdgpu_device *adev = ring->adev; 2967 2968 /* tell RLC which is KIQ queue */ 2969 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2970 tmp &= 0xffffff00; 2971 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2972 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2973 } 2974 2975 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2976 { 2977 /* set graphics engine doorbell range */ 2978 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2979 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2980 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2981 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2982 2983 /* set compute engine doorbell range */ 2984 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2985 (adev->doorbell_index.kiq * 2) << 2); 2986 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2987 (adev->doorbell_index.userqueue_end * 2) << 2); 2988 } 2989 2990 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2991 struct amdgpu_mqd_prop *prop) 2992 { 2993 struct v12_gfx_mqd *mqd = m; 2994 uint64_t hqd_gpu_addr, wb_gpu_addr; 2995 uint32_t tmp; 2996 uint32_t rb_bufsz; 2997 2998 /* set up gfx hqd wptr */ 2999 mqd->cp_gfx_hqd_wptr = 0; 3000 mqd->cp_gfx_hqd_wptr_hi = 0; 3001 3002 /* set the pointer to the MQD */ 3003 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3004 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3005 3006 /* set up mqd control */ 3007 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3009 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3010 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3011 mqd->cp_gfx_mqd_control = tmp; 3012 3013 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3014 tmp = regCP_GFX_HQD_VMID_DEFAULT; 3015 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3016 mqd->cp_gfx_hqd_vmid = 0; 3017 3018 /* set up default queue priority level 3019 * 0x0 = low priority, 0x1 = high priority */ 3020 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 3021 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3022 mqd->cp_gfx_hqd_queue_priority = tmp; 3023 3024 /* set up time quantum */ 3025 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3026 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3027 mqd->cp_gfx_hqd_quantum = tmp; 3028 3029 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3030 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3031 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3032 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3033 3034 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3035 wb_gpu_addr = prop->rptr_gpu_addr; 3036 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3037 mqd->cp_gfx_hqd_rptr_addr_hi = 3038 upper_32_bits(wb_gpu_addr) & 0xffff; 3039 3040 /* set up rb_wptr_poll addr */ 3041 wb_gpu_addr = prop->wptr_gpu_addr; 3042 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3043 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3044 3045 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3046 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3047 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3048 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3049 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3050 #ifdef __BIG_ENDIAN 3051 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3052 #endif 3053 if (prop->tmz_queue) 3054 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3055 if (!prop->kernel_queue) 3056 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3057 mqd->cp_gfx_hqd_cntl = tmp; 3058 3059 /* set up cp_doorbell_control */ 3060 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3061 if (prop->use_doorbell) { 3062 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3063 DOORBELL_OFFSET, prop->doorbell_index); 3064 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3065 DOORBELL_EN, 1); 3066 } else 3067 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3068 DOORBELL_EN, 0); 3069 mqd->cp_rb_doorbell_control = tmp; 3070 3071 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3072 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3073 3074 /* active the queue */ 3075 mqd->cp_gfx_hqd_active = 1; 3076 3077 /* set gfx UQ items */ 3078 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3079 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3080 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3081 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3082 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3083 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3084 3085 return 0; 3086 } 3087 3088 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring) 3089 { 3090 struct amdgpu_device *adev = ring->adev; 3091 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3092 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3093 3094 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3095 memset((void *)mqd, 0, sizeof(*mqd)); 3096 mutex_lock(&adev->srbm_mutex); 3097 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3098 amdgpu_ring_init_mqd(ring); 3099 soc24_grbm_select(adev, 0, 0, 0, 0); 3100 mutex_unlock(&adev->srbm_mutex); 3101 if (adev->gfx.me.mqd_backup[mqd_idx]) 3102 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3103 } else { 3104 /* restore mqd with the backup copy */ 3105 if (adev->gfx.me.mqd_backup[mqd_idx]) 3106 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3107 /* reset the ring */ 3108 ring->wptr = 0; 3109 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3110 amdgpu_ring_clear_ring(ring); 3111 } 3112 3113 return 0; 3114 } 3115 3116 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3117 { 3118 int i, r; 3119 3120 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3121 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i]); 3122 if (r) 3123 return r; 3124 } 3125 3126 r = amdgpu_gfx_enable_kgq(adev, 0); 3127 if (r) 3128 return r; 3129 3130 return gfx_v12_0_cp_gfx_start(adev); 3131 } 3132 3133 static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 3134 struct v12_compute_mqd *mqd, 3135 struct amdgpu_mqd_prop *prop) 3136 { 3137 uint32_t se_mask[8] = {0}; 3138 uint32_t wa_mask; 3139 bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 3140 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 3141 3142 if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 3143 return; 3144 3145 if (has_wa_flag) { 3146 wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 3147 0xffff : 0xffffffff; 3148 mqd->compute_static_thread_mgmt_se0 = wa_mask; 3149 mqd->compute_static_thread_mgmt_se1 = wa_mask; 3150 mqd->compute_static_thread_mgmt_se2 = wa_mask; 3151 mqd->compute_static_thread_mgmt_se3 = wa_mask; 3152 return; 3153 } 3154 3155 amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 3156 prop->cu_mask_count, se_mask); 3157 3158 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 3159 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 3160 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 3161 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 3162 } 3163 3164 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3165 struct amdgpu_mqd_prop *prop) 3166 { 3167 struct v12_compute_mqd *mqd = m; 3168 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3169 uint32_t tmp; 3170 3171 mqd->header = 0xC0310800; 3172 mqd->compute_pipelinestat_enable = 0x00000001; 3173 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3174 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3175 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3176 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3177 mqd->compute_misc_reserved = 0x00000007; 3178 3179 eop_base_addr = prop->eop_gpu_addr >> 8; 3180 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3181 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3182 3183 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3184 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3185 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3186 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3187 3188 mqd->cp_hqd_eop_control = tmp; 3189 3190 /* enable doorbell? */ 3191 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3192 3193 if (prop->use_doorbell) { 3194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3195 DOORBELL_OFFSET, prop->doorbell_index); 3196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3197 DOORBELL_EN, 1); 3198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3199 DOORBELL_SOURCE, 0); 3200 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3201 DOORBELL_HIT, 0); 3202 } else { 3203 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3204 DOORBELL_EN, 0); 3205 } 3206 3207 mqd->cp_hqd_pq_doorbell_control = tmp; 3208 3209 /* disable the queue if it's active */ 3210 mqd->cp_hqd_dequeue_request = 0; 3211 mqd->cp_hqd_pq_rptr = 0; 3212 mqd->cp_hqd_pq_wptr_lo = 0; 3213 mqd->cp_hqd_pq_wptr_hi = 0; 3214 3215 /* set the pointer to the MQD */ 3216 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3217 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3218 3219 /* set MQD vmid to 0 */ 3220 tmp = regCP_MQD_CONTROL_DEFAULT; 3221 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3222 mqd->cp_mqd_control = tmp; 3223 3224 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3225 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3226 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3227 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3228 3229 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3230 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3232 (order_base_2(prop->queue_size / 4) - 1)); 3233 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3234 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3235 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3236 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3237 if (prop->kernel_queue) { 3238 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3239 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3240 } 3241 if (prop->tmz_queue) 3242 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3243 mqd->cp_hqd_pq_control = tmp; 3244 3245 /* set the wb address whether it's enabled or not */ 3246 wb_gpu_addr = prop->rptr_gpu_addr; 3247 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3248 mqd->cp_hqd_pq_rptr_report_addr_hi = 3249 upper_32_bits(wb_gpu_addr) & 0xffff; 3250 3251 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3252 wb_gpu_addr = prop->wptr_gpu_addr; 3253 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3254 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3255 3256 tmp = 0; 3257 /* enable the doorbell if requested */ 3258 if (prop->use_doorbell) { 3259 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3260 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3261 DOORBELL_OFFSET, prop->doorbell_index); 3262 3263 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3264 DOORBELL_EN, 1); 3265 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3266 DOORBELL_SOURCE, 0); 3267 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3268 DOORBELL_HIT, 0); 3269 } 3270 3271 mqd->cp_hqd_pq_doorbell_control = tmp; 3272 3273 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3274 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3275 3276 /* set the vmid for the queue */ 3277 mqd->cp_hqd_vmid = 0; 3278 3279 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3280 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3281 mqd->cp_hqd_persistent_state = tmp; 3282 3283 /* set MIN_IB_AVAIL_SIZE */ 3284 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3285 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3286 mqd->cp_hqd_ib_control = tmp; 3287 3288 /* set static priority for a compute queue/ring */ 3289 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3290 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3291 3292 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 3293 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 3294 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 3295 mqd->cp_hqd_quantum = tmp; 3296 3297 mqd->cp_hqd_active = prop->hqd_active; 3298 3299 /* set UQ fenceaddress */ 3300 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3301 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3302 /* set CU mask */ 3303 gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); 3304 3305 return 0; 3306 } 3307 3308 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3309 { 3310 struct amdgpu_device *adev = ring->adev; 3311 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3312 int j; 3313 3314 /* inactivate the queue */ 3315 if (amdgpu_sriov_vf(adev)) 3316 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3317 3318 /* disable wptr polling */ 3319 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3320 3321 /* write the EOP addr */ 3322 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3323 mqd->cp_hqd_eop_base_addr_lo); 3324 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3325 mqd->cp_hqd_eop_base_addr_hi); 3326 3327 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3328 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3329 mqd->cp_hqd_eop_control); 3330 3331 /* enable doorbell? */ 3332 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3333 mqd->cp_hqd_pq_doorbell_control); 3334 3335 /* disable the queue if it's active */ 3336 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3337 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3338 for (j = 0; j < adev->usec_timeout; j++) { 3339 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3340 break; 3341 udelay(1); 3342 } 3343 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3344 mqd->cp_hqd_dequeue_request); 3345 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3346 mqd->cp_hqd_pq_rptr); 3347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3348 mqd->cp_hqd_pq_wptr_lo); 3349 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3350 mqd->cp_hqd_pq_wptr_hi); 3351 } 3352 3353 /* set the pointer to the MQD */ 3354 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3355 mqd->cp_mqd_base_addr_lo); 3356 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3357 mqd->cp_mqd_base_addr_hi); 3358 3359 /* set MQD vmid to 0 */ 3360 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3361 mqd->cp_mqd_control); 3362 3363 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3364 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3365 mqd->cp_hqd_pq_base_lo); 3366 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3367 mqd->cp_hqd_pq_base_hi); 3368 3369 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3370 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3371 mqd->cp_hqd_pq_control); 3372 3373 /* set the wb address whether it's enabled or not */ 3374 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3375 mqd->cp_hqd_pq_rptr_report_addr_lo); 3376 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3377 mqd->cp_hqd_pq_rptr_report_addr_hi); 3378 3379 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3380 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3381 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3382 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3383 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3384 3385 /* enable the doorbell if requested */ 3386 if (ring->use_doorbell) { 3387 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3388 (adev->doorbell_index.kiq * 2) << 2); 3389 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3390 (adev->doorbell_index.userqueue_end * 2) << 2); 3391 } 3392 3393 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3394 mqd->cp_hqd_pq_doorbell_control); 3395 3396 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3397 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3398 mqd->cp_hqd_pq_wptr_lo); 3399 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3400 mqd->cp_hqd_pq_wptr_hi); 3401 3402 /* set the vmid for the queue */ 3403 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3404 3405 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3406 mqd->cp_hqd_persistent_state); 3407 3408 /* activate the queue */ 3409 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3410 mqd->cp_hqd_active); 3411 3412 if (ring->use_doorbell) 3413 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3414 3415 return 0; 3416 } 3417 3418 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3419 { 3420 struct amdgpu_device *adev = ring->adev; 3421 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3422 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3423 3424 gfx_v12_0_kiq_setting(ring); 3425 3426 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3427 /* reset MQD to a clean status */ 3428 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3429 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3430 3431 /* reset ring buffer */ 3432 ring->wptr = 0; 3433 amdgpu_ring_clear_ring(ring); 3434 3435 mutex_lock(&adev->srbm_mutex); 3436 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3437 gfx_v12_0_kiq_init_register(ring); 3438 soc24_grbm_select(adev, 0, 0, 0, 0); 3439 mutex_unlock(&adev->srbm_mutex); 3440 } else { 3441 memset((void *)mqd, 0, sizeof(*mqd)); 3442 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3443 amdgpu_ring_clear_ring(ring); 3444 mutex_lock(&adev->srbm_mutex); 3445 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3446 amdgpu_ring_init_mqd(ring); 3447 gfx_v12_0_kiq_init_register(ring); 3448 soc24_grbm_select(adev, 0, 0, 0, 0); 3449 mutex_unlock(&adev->srbm_mutex); 3450 3451 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3452 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3453 } 3454 3455 return 0; 3456 } 3457 3458 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring) 3459 { 3460 struct amdgpu_device *adev = ring->adev; 3461 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3462 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3463 3464 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3465 memset((void *)mqd, 0, sizeof(*mqd)); 3466 mutex_lock(&adev->srbm_mutex); 3467 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3468 amdgpu_ring_init_mqd(ring); 3469 soc24_grbm_select(adev, 0, 0, 0, 0); 3470 mutex_unlock(&adev->srbm_mutex); 3471 3472 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3473 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3474 } else { 3475 /* restore MQD to a clean status */ 3476 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3477 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3478 /* reset ring buffer */ 3479 ring->wptr = 0; 3480 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3481 amdgpu_ring_clear_ring(ring); 3482 } 3483 3484 return 0; 3485 } 3486 3487 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3488 { 3489 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3490 adev->gfx.kiq[0].ring.sched.ready = true; 3491 return 0; 3492 } 3493 3494 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3495 { 3496 int i, r; 3497 3498 if (!amdgpu_async_gfx_ring) 3499 gfx_v12_0_cp_compute_enable(adev, true); 3500 3501 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3502 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i]); 3503 if (r) 3504 return r; 3505 } 3506 3507 return amdgpu_gfx_enable_kcq(adev, 0); 3508 } 3509 3510 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3511 { 3512 int r, i; 3513 struct amdgpu_ring *ring; 3514 3515 if (!(adev->flags & AMD_IS_APU)) 3516 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3517 3518 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3519 /* legacy firmware loading */ 3520 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3521 if (r) 3522 return r; 3523 3524 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3525 if (r) 3526 return r; 3527 } 3528 3529 gfx_v12_0_cp_set_doorbell_range(adev); 3530 3531 if (amdgpu_async_gfx_ring) { 3532 gfx_v12_0_cp_compute_enable(adev, true); 3533 gfx_v12_0_cp_gfx_enable(adev, true); 3534 } 3535 3536 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) { 3537 r = amdgpu_mes_kiq_hw_init(adev, 0); 3538 /* 3539 * With MES, GFX KIQ ring is owned by the MES and is never 3540 * initialized/used directly by the driver, so it must 3541 * not be left flagged as ready. mes_v12_0_hw_init() clears 3542 * but clear here if MES init fails 3543 */ 3544 if (r) 3545 adev->gfx.kiq[0].ring.sched.ready = false; 3546 } else { 3547 r = gfx_v12_0_kiq_resume(adev); 3548 } 3549 if (r) 3550 return r; 3551 3552 r = gfx_v12_0_kcq_resume(adev); 3553 if (r) 3554 return r; 3555 3556 if (!amdgpu_async_gfx_ring) { 3557 r = gfx_v12_0_cp_gfx_resume(adev); 3558 if (r) 3559 return r; 3560 } else { 3561 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3562 if (r) 3563 return r; 3564 } 3565 3566 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3567 ring = &adev->gfx.gfx_ring[i]; 3568 r = amdgpu_ring_test_helper(ring); 3569 if (r) 3570 return r; 3571 } 3572 3573 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3574 ring = &adev->gfx.compute_ring[i]; 3575 r = amdgpu_ring_test_helper(ring); 3576 if (r) 3577 return r; 3578 } 3579 3580 return 0; 3581 } 3582 3583 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3584 { 3585 gfx_v12_0_cp_gfx_enable(adev, enable); 3586 gfx_v12_0_cp_compute_enable(adev, enable); 3587 } 3588 3589 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3590 { 3591 int r; 3592 bool value; 3593 3594 r = adev->gfxhub.funcs->gart_enable(adev); 3595 if (r) 3596 return r; 3597 3598 amdgpu_device_flush_hdp(adev, NULL); 3599 3600 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3601 3602 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3603 /* TODO investigate why this and the hdp flush above is needed, 3604 * are we missing a flush somewhere else? */ 3605 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3606 3607 return 0; 3608 } 3609 3610 static int get_gb_addr_config(struct amdgpu_device *adev) 3611 { 3612 u32 gb_addr_config; 3613 3614 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3615 if (gb_addr_config == 0) 3616 return -EINVAL; 3617 3618 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3619 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3620 3621 adev->gfx.config.gb_addr_config = gb_addr_config; 3622 3623 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3624 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3625 GB_ADDR_CONFIG, NUM_PIPES); 3626 3627 adev->gfx.config.max_tile_pipes = 3628 adev->gfx.config.gb_addr_config_fields.num_pipes; 3629 3630 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3631 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3632 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3633 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3634 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3635 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3636 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3637 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3638 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3639 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3640 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3641 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3642 3643 return 0; 3644 } 3645 3646 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3647 { 3648 uint32_t data; 3649 3650 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3651 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3652 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3653 3654 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3655 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3656 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3657 } 3658 3659 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3660 { 3661 if (amdgpu_sriov_vf(adev)) 3662 return; 3663 3664 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3665 case IP_VERSION(12, 0, 0): 3666 case IP_VERSION(12, 0, 1): 3667 soc15_program_register_sequence(adev, 3668 golden_settings_gc_12_0, 3669 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3670 3671 if (adev->rev_id == 0) 3672 soc15_program_register_sequence(adev, 3673 golden_settings_gc_12_0_rev0, 3674 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3675 break; 3676 default: 3677 break; 3678 } 3679 } 3680 3681 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3682 bool enable) 3683 { 3684 unsigned int irq_type; 3685 int m, p, r; 3686 3687 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3688 for (m = 0; m < adev->gfx.me.num_me; m++) { 3689 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3690 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3691 if (enable) 3692 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3693 else 3694 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3695 if (r) { 3696 if (!enable) 3697 return r; 3698 goto err_gfx; 3699 } 3700 } 3701 } 3702 } 3703 3704 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3705 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3706 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3707 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3708 + (m * adev->gfx.mec.num_pipe_per_mec) 3709 + p; 3710 if (enable) 3711 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3712 else 3713 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3714 if (r) { 3715 if (!enable) 3716 return r; 3717 goto err_compute; 3718 } 3719 } 3720 } 3721 } 3722 3723 return 0; 3724 3725 err_compute: 3726 for (p--; p >= 0; p--) { 3727 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3728 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3729 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3730 } 3731 for (m--; m >= 0; m--) { 3732 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 3733 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3734 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3735 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3736 } 3737 } 3738 m = adev->gfx.me.num_me; 3739 err_gfx: 3740 for (p--; p >= 0; p--) { 3741 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3742 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3743 } 3744 for (m--; m >= 0; m--) { 3745 for (p = adev->gfx.me.num_pipe_per_me - 1; p >= 0; p--) { 3746 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3747 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3748 } 3749 } 3750 return r; 3751 } 3752 3753 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3754 { 3755 int r; 3756 struct amdgpu_device *adev = ip_block->adev; 3757 3758 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3759 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3760 /* RLC autoload sequence 1: Program rlc ram */ 3761 if (adev->gfx.imu.funcs->program_rlc_ram) 3762 adev->gfx.imu.funcs->program_rlc_ram(adev); 3763 } 3764 /* rlc autoload firmware */ 3765 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3766 if (r) 3767 return r; 3768 } else { 3769 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3770 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3771 if (adev->gfx.imu.funcs->load_microcode) 3772 adev->gfx.imu.funcs->load_microcode(adev); 3773 if (adev->gfx.imu.funcs->setup_imu) 3774 adev->gfx.imu.funcs->setup_imu(adev); 3775 if (adev->gfx.imu.funcs->start_imu) 3776 adev->gfx.imu.funcs->start_imu(adev); 3777 } 3778 3779 /* disable gpa mode in backdoor loading */ 3780 gfx_v12_0_disable_gpa_mode(adev); 3781 } 3782 } 3783 3784 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3785 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3786 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3787 if (r) { 3788 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3789 return r; 3790 } 3791 } 3792 3793 if (!amdgpu_emu_mode) 3794 gfx_v12_0_init_golden_registers(adev); 3795 3796 adev->gfx.is_poweron = true; 3797 3798 if (get_gb_addr_config(adev)) 3799 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 3800 3801 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3802 gfx_v12_0_config_gfx_rs64(adev); 3803 3804 r = gfx_v12_0_gfxhub_enable(adev); 3805 if (r) 3806 return r; 3807 3808 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3809 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3810 (amdgpu_dpm == 1)) { 3811 /** 3812 * For gfx 12, rlc firmware loading relies on smu firmware is 3813 * loaded firstly, so in direct type, it has to load smc ucode 3814 * here before rlc. 3815 */ 3816 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3817 if (r) 3818 return r; 3819 } 3820 3821 gfx_v12_0_constants_init(adev); 3822 3823 if (adev->nbio.funcs->gc_doorbell_init) 3824 adev->nbio.funcs->gc_doorbell_init(adev); 3825 3826 r = gfx_v12_0_rlc_resume(adev); 3827 if (r) 3828 return r; 3829 3830 /* 3831 * init golden registers and rlc resume may override some registers, 3832 * reconfig them here 3833 */ 3834 gfx_v12_0_tcp_harvest(adev); 3835 3836 r = gfx_v12_0_cp_resume(adev); 3837 if (r) 3838 return r; 3839 3840 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3841 if (r) 3842 return r; 3843 3844 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3845 if (r) 3846 goto err_priv_inst; 3847 3848 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3849 if (r) 3850 goto err_bad_op; 3851 3852 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3853 if (r) 3854 goto err_userq_eop; 3855 3856 return 0; 3857 3858 err_userq_eop: 3859 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3860 err_bad_op: 3861 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3862 err_priv_inst: 3863 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3864 return r; 3865 } 3866 3867 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3868 { 3869 struct amdgpu_device *adev = ip_block->adev; 3870 uint32_t tmp; 3871 3872 cancel_delayed_work_sync(&adev->gfx.idle_work); 3873 3874 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3875 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3876 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3877 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3878 3879 if (!adev->no_hw_access) { 3880 if (amdgpu_async_gfx_ring) { 3881 if (amdgpu_gfx_disable_kgq(adev, 0)) 3882 DRM_ERROR("KGQ disable failed\n"); 3883 } 3884 3885 if (amdgpu_gfx_disable_kcq(adev, 0)) 3886 DRM_ERROR("KCQ disable failed\n"); 3887 3888 amdgpu_mes_kiq_hw_fini(adev, 0); 3889 } 3890 3891 if (amdgpu_sriov_vf(adev)) { 3892 gfx_v12_0_cp_gfx_enable(adev, false); 3893 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3894 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3895 tmp &= 0xffffff00; 3896 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3897 3898 return 0; 3899 } 3900 gfx_v12_0_cp_enable(adev, false); 3901 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3902 3903 adev->gfxhub.funcs->gart_disable(adev); 3904 3905 adev->gfx.is_poweron = false; 3906 3907 return 0; 3908 } 3909 3910 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3911 { 3912 return gfx_v12_0_hw_fini(ip_block); 3913 } 3914 3915 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3916 { 3917 return gfx_v12_0_hw_init(ip_block); 3918 } 3919 3920 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3921 { 3922 struct amdgpu_device *adev = ip_block->adev; 3923 3924 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3925 GRBM_STATUS, GUI_ACTIVE)) 3926 return false; 3927 else 3928 return true; 3929 } 3930 3931 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3932 { 3933 unsigned i; 3934 u32 tmp; 3935 struct amdgpu_device *adev = ip_block->adev; 3936 3937 for (i = 0; i < adev->usec_timeout; i++) { 3938 /* read MC_STATUS */ 3939 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3940 GRBM_STATUS__GUI_ACTIVE_MASK; 3941 3942 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3943 return 0; 3944 udelay(1); 3945 } 3946 return -ETIMEDOUT; 3947 } 3948 3949 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3950 { 3951 uint64_t clock = 0; 3952 3953 if (adev->smuio.funcs && 3954 adev->smuio.funcs->get_gpu_clock_counter) 3955 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3956 else 3957 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3958 3959 return clock; 3960 } 3961 3962 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3963 { 3964 struct amdgpu_device *adev = ip_block->adev; 3965 3966 switch (amdgpu_user_queue) { 3967 case -1: 3968 case 0: 3969 default: 3970 adev->gfx.disable_kq = false; 3971 adev->gfx.disable_uq = true; 3972 break; 3973 case 1: 3974 adev->gfx.disable_kq = false; 3975 adev->gfx.disable_uq = false; 3976 break; 3977 case 2: 3978 adev->gfx.disable_kq = true; 3979 adev->gfx.disable_uq = false; 3980 break; 3981 } 3982 3983 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3984 3985 if (adev->gfx.disable_kq) { 3986 adev->gfx.num_gfx_rings = 0; 3987 adev->gfx.num_compute_rings = 0; 3988 } else { 3989 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3990 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3991 AMDGPU_MAX_COMPUTE_RINGS); 3992 } 3993 3994 gfx_v12_0_set_kiq_pm4_funcs(adev); 3995 gfx_v12_0_set_ring_funcs(adev); 3996 gfx_v12_0_set_irq_funcs(adev); 3997 gfx_v12_0_set_rlc_funcs(adev); 3998 gfx_v12_0_set_mqd_funcs(adev); 3999 gfx_v12_0_set_imu_funcs(adev); 4000 4001 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 4002 4003 amdgpu_init_rlc_reg_funcs(adev); 4004 4005 return gfx_v12_0_init_microcode(adev); 4006 } 4007 4008 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 4009 { 4010 uint32_t rlc_cntl; 4011 4012 /* if RLC is not enabled, do nothing */ 4013 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4014 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4015 } 4016 4017 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 4018 int xcc_id) 4019 { 4020 uint32_t data; 4021 unsigned i; 4022 4023 data = RLC_SAFE_MODE__CMD_MASK; 4024 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4025 4026 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4027 4028 /* wait for RLC_SAFE_MODE */ 4029 for (i = 0; i < adev->usec_timeout; i++) { 4030 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4031 RLC_SAFE_MODE, CMD)) 4032 break; 4033 udelay(1); 4034 } 4035 } 4036 4037 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 4038 int xcc_id) 4039 { 4040 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4041 } 4042 4043 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 4044 bool enable) 4045 { 4046 uint32_t def, data; 4047 4048 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4049 return; 4050 4051 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4052 4053 if (enable) 4054 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4055 else 4056 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4057 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4060 } 4061 4062 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 4063 int xcc_id, 4064 struct amdgpu_ring *ring, 4065 unsigned vmid) 4066 { 4067 u32 reg, data; 4068 4069 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4070 if (amdgpu_sriov_is_pp_one_vf(adev)) 4071 data = RREG32_NO_KIQ(reg); 4072 else 4073 data = RREG32(reg); 4074 4075 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4076 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4077 4078 if (amdgpu_sriov_is_pp_one_vf(adev)) 4079 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 4080 else 4081 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 4082 4083 if (ring 4084 && amdgpu_sriov_is_pp_one_vf(adev) 4085 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 4086 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 4087 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4088 amdgpu_ring_emit_wreg(ring, reg, data); 4089 } 4090 } 4091 4092 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 4093 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 4094 .set_safe_mode = gfx_v12_0_set_safe_mode, 4095 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 4096 .init = gfx_v12_0_rlc_init, 4097 .get_csb_size = gfx_v12_0_get_csb_size, 4098 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 4099 .resume = gfx_v12_0_rlc_resume, 4100 .stop = gfx_v12_0_rlc_stop, 4101 .reset = gfx_v12_0_rlc_reset, 4102 .start = gfx_v12_0_rlc_start, 4103 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4104 }; 4105 4106 #if 0 4107 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4108 { 4109 /* TODO */ 4110 } 4111 4112 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4113 { 4114 /* TODO */ 4115 } 4116 #endif 4117 4118 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4119 enum amd_powergating_state state) 4120 { 4121 struct amdgpu_device *adev = ip_block->adev; 4122 bool enable = (state == AMD_PG_STATE_GATE); 4123 4124 if (amdgpu_sriov_vf(adev)) 4125 return 0; 4126 4127 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4128 case IP_VERSION(12, 0, 0): 4129 case IP_VERSION(12, 0, 1): 4130 amdgpu_gfx_off_ctrl(adev, enable); 4131 break; 4132 default: 4133 break; 4134 } 4135 4136 return 0; 4137 } 4138 4139 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4140 bool enable) 4141 { 4142 uint32_t def, data; 4143 4144 if (!(adev->cg_flags & 4145 (AMD_CG_SUPPORT_GFX_CGCG | 4146 AMD_CG_SUPPORT_GFX_CGLS | 4147 AMD_CG_SUPPORT_GFX_3D_CGCG | 4148 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4149 return; 4150 4151 if (enable) { 4152 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4153 4154 /* unset CGCG override */ 4155 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4156 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4157 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4158 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4159 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4160 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4161 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4162 4163 /* update CGCG override bits */ 4164 if (def != data) 4165 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4166 4167 /* enable cgcg FSM(0x0000363F) */ 4168 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4169 4170 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4171 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4172 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4173 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4174 } 4175 4176 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4177 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4178 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4179 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4180 } 4181 4182 if (def != data) 4183 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4184 4185 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4186 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4187 4188 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4189 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4190 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4191 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4192 } 4193 4194 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4195 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4196 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4197 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4198 } 4199 4200 if (def != data) 4201 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4202 4203 /* set IDLE_POLL_COUNT(0x00900100) */ 4204 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4205 4206 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4207 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4208 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4209 4210 if (def != data) 4211 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4212 4213 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4214 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4215 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4216 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4217 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4218 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4219 4220 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4221 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4222 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4223 4224 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4225 if (adev->sdma.num_instances > 1) { 4226 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4227 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4228 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4229 } 4230 } else { 4231 /* Program RLC_CGCG_CGLS_CTRL */ 4232 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4233 4234 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4235 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4236 4237 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4238 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4239 4240 if (def != data) 4241 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4242 4243 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4244 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4245 4246 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4247 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4248 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4249 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4250 4251 if (def != data) 4252 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4253 } 4254 } 4255 4256 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4257 bool enable) 4258 { 4259 uint32_t data, def; 4260 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4261 return; 4262 4263 /* It is disabled by HW by default */ 4264 if (enable) { 4265 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4266 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4267 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4268 4269 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4270 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4271 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4272 4273 if (def != data) 4274 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4275 } 4276 } else { 4277 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4278 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4279 4280 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4281 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4282 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4283 4284 if (def != data) 4285 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4286 } 4287 } 4288 } 4289 4290 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4291 bool enable) 4292 { 4293 uint32_t def, data; 4294 4295 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4296 return; 4297 4298 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4299 4300 if (enable) 4301 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4302 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4303 else 4304 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4305 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4306 4307 if (def != data) 4308 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4309 } 4310 4311 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4312 bool enable) 4313 { 4314 uint32_t def, data; 4315 4316 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4317 return; 4318 4319 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4320 4321 if (enable) 4322 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4323 else 4324 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4325 4326 if (def != data) 4327 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4328 } 4329 4330 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4331 bool enable) 4332 { 4333 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4334 4335 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4336 4337 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4338 4339 gfx_v12_0_update_repeater_fgcg(adev, enable); 4340 4341 gfx_v12_0_update_sram_fgcg(adev, enable); 4342 4343 gfx_v12_0_update_perf_clk(adev, enable); 4344 4345 if (adev->cg_flags & 4346 (AMD_CG_SUPPORT_GFX_MGCG | 4347 AMD_CG_SUPPORT_GFX_CGLS | 4348 AMD_CG_SUPPORT_GFX_CGCG | 4349 AMD_CG_SUPPORT_GFX_3D_CGCG | 4350 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4351 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4352 4353 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4354 4355 return 0; 4356 } 4357 4358 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4359 enum amd_clockgating_state state) 4360 { 4361 struct amdgpu_device *adev = ip_block->adev; 4362 4363 if (amdgpu_sriov_vf(adev)) 4364 return 0; 4365 4366 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4367 case IP_VERSION(12, 0, 0): 4368 case IP_VERSION(12, 0, 1): 4369 gfx_v12_0_update_gfx_clock_gating(adev, 4370 state == AMD_CG_STATE_GATE); 4371 break; 4372 default: 4373 break; 4374 } 4375 4376 return 0; 4377 } 4378 4379 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4380 { 4381 struct amdgpu_device *adev = ip_block->adev; 4382 int data; 4383 4384 /* AMD_CG_SUPPORT_GFX_MGCG */ 4385 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4386 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4387 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4388 4389 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4390 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4391 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4392 4393 /* AMD_CG_SUPPORT_GFX_FGCG */ 4394 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4395 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4396 4397 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4398 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4399 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4400 4401 /* AMD_CG_SUPPORT_GFX_CGCG */ 4402 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4403 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4404 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4405 4406 /* AMD_CG_SUPPORT_GFX_CGLS */ 4407 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4408 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4409 4410 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4411 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4412 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4413 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4414 4415 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4416 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4417 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4418 } 4419 4420 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4421 { 4422 /* gfx12 is 32bit rptr*/ 4423 return *(uint32_t *)ring->rptr_cpu_addr; 4424 } 4425 4426 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4427 { 4428 struct amdgpu_device *adev = ring->adev; 4429 u64 wptr; 4430 4431 /* XXX check if swapping is necessary on BE */ 4432 if (ring->use_doorbell) { 4433 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4434 } else { 4435 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4436 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4437 } 4438 4439 return wptr; 4440 } 4441 4442 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4443 { 4444 struct amdgpu_device *adev = ring->adev; 4445 4446 if (ring->use_doorbell) { 4447 /* XXX check if swapping is necessary on BE */ 4448 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4449 ring->wptr); 4450 WDOORBELL64(ring->doorbell_index, ring->wptr); 4451 } else { 4452 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4453 lower_32_bits(ring->wptr)); 4454 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4455 upper_32_bits(ring->wptr)); 4456 } 4457 } 4458 4459 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4460 { 4461 /* gfx12 hardware is 32bit rptr */ 4462 return *(uint32_t *)ring->rptr_cpu_addr; 4463 } 4464 4465 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4466 { 4467 u64 wptr; 4468 4469 /* XXX check if swapping is necessary on BE */ 4470 if (ring->use_doorbell) 4471 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4472 else 4473 BUG(); 4474 return wptr; 4475 } 4476 4477 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4478 { 4479 struct amdgpu_device *adev = ring->adev; 4480 4481 /* XXX check if swapping is necessary on BE */ 4482 if (ring->use_doorbell) { 4483 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4484 ring->wptr); 4485 WDOORBELL64(ring->doorbell_index, ring->wptr); 4486 } else { 4487 BUG(); /* only DOORBELL method supported on gfx12 now */ 4488 } 4489 } 4490 4491 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4492 { 4493 struct amdgpu_device *adev = ring->adev; 4494 u32 ref_and_mask, reg_mem_engine; 4495 4496 if (!adev->gfx.funcs->get_hdp_flush_mask) { 4497 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 4498 return; 4499 } 4500 4501 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 4502 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4503 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4504 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4505 ref_and_mask, ref_and_mask, 0x20); 4506 } 4507 4508 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4509 struct amdgpu_job *job, 4510 struct amdgpu_ib *ib, 4511 uint32_t flags) 4512 { 4513 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4514 u32 header, control = 0; 4515 4516 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4517 4518 control |= ib->length_dw | (vmid << 24); 4519 4520 amdgpu_ring_write(ring, header); 4521 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4522 amdgpu_ring_write(ring, 4523 #ifdef __BIG_ENDIAN 4524 (2 << 0) | 4525 #endif 4526 lower_32_bits(ib->gpu_addr)); 4527 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4528 amdgpu_ring_write(ring, control); 4529 } 4530 4531 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4532 struct amdgpu_job *job, 4533 struct amdgpu_ib *ib, 4534 uint32_t flags) 4535 { 4536 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4537 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4538 4539 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4540 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4541 amdgpu_ring_write(ring, 4542 #ifdef __BIG_ENDIAN 4543 (2 << 0) | 4544 #endif 4545 lower_32_bits(ib->gpu_addr)); 4546 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4547 amdgpu_ring_write(ring, control); 4548 } 4549 4550 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4551 u64 seq, unsigned flags) 4552 { 4553 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4554 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4555 4556 /* RELEASE_MEM - flush caches, send int */ 4557 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4558 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4559 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4560 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4561 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4562 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4563 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4564 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4565 4566 /* 4567 * the address should be Qword aligned if 64bit write, Dword 4568 * aligned if only send 32bit data low (discard data high) 4569 */ 4570 if (write64bit) 4571 WARN_ON(addr & 0x7); 4572 else 4573 WARN_ON(addr & 0x3); 4574 amdgpu_ring_write(ring, lower_32_bits(addr)); 4575 amdgpu_ring_write(ring, upper_32_bits(addr)); 4576 amdgpu_ring_write(ring, lower_32_bits(seq)); 4577 amdgpu_ring_write(ring, upper_32_bits(seq)); 4578 amdgpu_ring_write(ring, 0); 4579 } 4580 4581 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4582 { 4583 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4584 uint32_t seq = ring->fence_drv.sync_seq; 4585 uint64_t addr = ring->fence_drv.gpu_addr; 4586 4587 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4588 upper_32_bits(addr), seq, 0xffffffff, 4); 4589 } 4590 4591 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4592 uint16_t pasid, uint32_t flush_type, 4593 bool all_hub, uint8_t dst_sel) 4594 { 4595 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4596 amdgpu_ring_write(ring, 4597 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4598 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4599 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4600 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4601 } 4602 4603 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4604 unsigned vmid, uint64_t pd_addr) 4605 { 4606 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4607 4608 /* compute doesn't have PFP */ 4609 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4610 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4611 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4612 amdgpu_ring_write(ring, 0x0); 4613 } 4614 } 4615 4616 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4617 u64 seq, unsigned int flags) 4618 { 4619 struct amdgpu_device *adev = ring->adev; 4620 4621 /* write fence seq to the "addr" */ 4622 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4623 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4624 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4625 amdgpu_ring_write(ring, lower_32_bits(addr)); 4626 amdgpu_ring_write(ring, upper_32_bits(addr)); 4627 amdgpu_ring_write(ring, lower_32_bits(seq)); 4628 4629 if (flags & AMDGPU_FENCE_FLAG_INT) { 4630 /* set register to trigger INT */ 4631 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4632 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4633 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4634 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4635 amdgpu_ring_write(ring, 0); 4636 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4637 } 4638 } 4639 4640 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4641 uint32_t flags) 4642 { 4643 uint32_t dw2 = 0; 4644 4645 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4646 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4647 /* set load_global_config & load_global_uconfig */ 4648 dw2 |= 0x8001; 4649 /* set load_cs_sh_regs */ 4650 dw2 |= 0x01000000; 4651 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4652 dw2 |= 0x10002; 4653 } 4654 4655 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4656 amdgpu_ring_write(ring, dw2); 4657 amdgpu_ring_write(ring, 0); 4658 } 4659 4660 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4661 uint64_t addr) 4662 { 4663 unsigned ret; 4664 4665 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4666 amdgpu_ring_write(ring, lower_32_bits(addr)); 4667 amdgpu_ring_write(ring, upper_32_bits(addr)); 4668 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4669 amdgpu_ring_write(ring, 0); 4670 ret = ring->wptr & ring->buf_mask; 4671 /* patch dummy value later */ 4672 amdgpu_ring_write(ring, 0); 4673 4674 return ret; 4675 } 4676 4677 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4678 uint32_t reg_val_offs) 4679 { 4680 struct amdgpu_device *adev = ring->adev; 4681 4682 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4683 amdgpu_ring_write(ring, 0 | /* src: register*/ 4684 (5 << 8) | /* dst: memory */ 4685 (1 << 20)); /* write confirm */ 4686 amdgpu_ring_write(ring, reg); 4687 amdgpu_ring_write(ring, 0); 4688 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4689 reg_val_offs * 4)); 4690 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4691 reg_val_offs * 4)); 4692 } 4693 4694 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4695 uint32_t reg, 4696 uint32_t val) 4697 { 4698 uint32_t cmd = 0; 4699 4700 switch (ring->funcs->type) { 4701 case AMDGPU_RING_TYPE_GFX: 4702 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4703 break; 4704 case AMDGPU_RING_TYPE_KIQ: 4705 cmd = (1 << 16); /* no inc addr */ 4706 break; 4707 default: 4708 cmd = WR_CONFIRM; 4709 break; 4710 } 4711 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4712 amdgpu_ring_write(ring, cmd); 4713 amdgpu_ring_write(ring, reg); 4714 amdgpu_ring_write(ring, 0); 4715 amdgpu_ring_write(ring, val); 4716 } 4717 4718 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4719 uint32_t val, uint32_t mask) 4720 { 4721 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4722 } 4723 4724 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4725 uint32_t reg0, uint32_t reg1, 4726 uint32_t ref, uint32_t mask) 4727 { 4728 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4729 4730 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4731 ref, mask, 0x20); 4732 } 4733 4734 static void 4735 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4736 uint32_t me, uint32_t pipe, 4737 enum amdgpu_interrupt_state state) 4738 { 4739 uint32_t cp_int_cntl, cp_int_cntl_reg; 4740 4741 if (!me) { 4742 switch (pipe) { 4743 case 0: 4744 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4745 break; 4746 default: 4747 DRM_DEBUG("invalid pipe %d\n", pipe); 4748 return; 4749 } 4750 } else { 4751 DRM_DEBUG("invalid me %d\n", me); 4752 return; 4753 } 4754 4755 switch (state) { 4756 case AMDGPU_IRQ_STATE_DISABLE: 4757 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4758 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4759 TIME_STAMP_INT_ENABLE, 0); 4760 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4761 GENERIC0_INT_ENABLE, 0); 4762 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4763 break; 4764 case AMDGPU_IRQ_STATE_ENABLE: 4765 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4766 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4767 TIME_STAMP_INT_ENABLE, 1); 4768 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4769 GENERIC0_INT_ENABLE, 1); 4770 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4771 break; 4772 default: 4773 break; 4774 } 4775 } 4776 4777 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4778 int me, int pipe, 4779 enum amdgpu_interrupt_state state) 4780 { 4781 u32 mec_int_cntl, mec_int_cntl_reg; 4782 4783 /* 4784 * amdgpu controls only the first MEC. That's why this function only 4785 * handles the setting of interrupts for this specific MEC. All other 4786 * pipes' interrupts are set by amdkfd. 4787 */ 4788 4789 if (me == 1) { 4790 switch (pipe) { 4791 case 0: 4792 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4793 break; 4794 case 1: 4795 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4796 break; 4797 default: 4798 DRM_DEBUG("invalid pipe %d\n", pipe); 4799 return; 4800 } 4801 } else { 4802 DRM_DEBUG("invalid me %d\n", me); 4803 return; 4804 } 4805 4806 switch (state) { 4807 case AMDGPU_IRQ_STATE_DISABLE: 4808 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4809 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4810 TIME_STAMP_INT_ENABLE, 0); 4811 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4812 GENERIC0_INT_ENABLE, 0); 4813 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4814 break; 4815 case AMDGPU_IRQ_STATE_ENABLE: 4816 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4817 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4818 TIME_STAMP_INT_ENABLE, 1); 4819 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4820 GENERIC0_INT_ENABLE, 1); 4821 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4822 break; 4823 default: 4824 break; 4825 } 4826 } 4827 4828 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4829 struct amdgpu_irq_src *src, 4830 unsigned type, 4831 enum amdgpu_interrupt_state state) 4832 { 4833 switch (type) { 4834 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4835 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4836 break; 4837 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4838 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4839 break; 4840 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4841 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4842 break; 4843 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4844 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4845 break; 4846 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4847 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4848 break; 4849 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4850 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4851 break; 4852 default: 4853 break; 4854 } 4855 return 0; 4856 } 4857 4858 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4859 struct amdgpu_irq_src *source, 4860 struct amdgpu_iv_entry *entry) 4861 { 4862 u32 doorbell_offset = entry->src_data[0]; 4863 4864 DRM_DEBUG("IH: CP EOP\n"); 4865 4866 if (!adev->gfx.disable_kq) { 4867 u8 me_id = (entry->ring_id & 0x0c) >> 2; 4868 u8 pipe_id = (entry->ring_id & 0x03) >> 0; 4869 u8 queue_id = (entry->ring_id & 0x70) >> 4; 4870 struct amdgpu_ring *ring; 4871 int i; 4872 4873 switch (me_id) { 4874 case 0: 4875 /* 4876 * MES splits gfx HQDs per (me,pipe): KGQ owns queue=0, 4877 * userq gfx owns queue>=1 (see amdgpu_mes_get_hqd_mask). 4878 * Require a strict (me,pipe,queue) match so userq gfx 4879 * EOPs fall through to amdgpu_userq_process_fence_irq(). 4880 */ 4881 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4882 ring = &adev->gfx.gfx_ring[i]; 4883 if ((ring->me == me_id) && 4884 (ring->pipe == pipe_id) && 4885 (ring->queue == queue_id)) { 4886 amdgpu_fence_process(ring); 4887 return 0; 4888 } 4889 } 4890 break; 4891 case 1: 4892 case 2: 4893 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4894 ring = &adev->gfx.compute_ring[i]; 4895 /* Per-queue interrupt is supported for MEC starting from VI. 4896 * The interrupt can only be enabled/disabled per pipe instead 4897 * of per queue. 4898 */ 4899 if ((ring->me == me_id) && 4900 (ring->pipe == pipe_id) && 4901 (ring->queue == queue_id)) { 4902 amdgpu_fence_process(ring); 4903 return 0; 4904 } 4905 } 4906 break; 4907 default: 4908 break; 4909 } 4910 } 4911 4912 if (adev->enable_mes && doorbell_offset) 4913 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 4914 4915 return 0; 4916 } 4917 4918 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4919 struct amdgpu_irq_src *source, 4920 unsigned int type, 4921 enum amdgpu_interrupt_state state) 4922 { 4923 u32 cp_int_cntl_reg, cp_int_cntl; 4924 int i, j; 4925 4926 switch (state) { 4927 case AMDGPU_IRQ_STATE_DISABLE: 4928 case AMDGPU_IRQ_STATE_ENABLE: 4929 for (i = 0; i < adev->gfx.me.num_me; i++) { 4930 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4931 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4932 4933 if (cp_int_cntl_reg) { 4934 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4935 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4936 PRIV_REG_INT_ENABLE, 4937 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4938 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4939 } 4940 } 4941 } 4942 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4943 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4944 /* MECs start at 1 */ 4945 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4946 4947 if (cp_int_cntl_reg) { 4948 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4949 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4950 PRIV_REG_INT_ENABLE, 4951 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4952 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4953 } 4954 } 4955 } 4956 break; 4957 default: 4958 break; 4959 } 4960 4961 return 0; 4962 } 4963 4964 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4965 struct amdgpu_irq_src *source, 4966 unsigned type, 4967 enum amdgpu_interrupt_state state) 4968 { 4969 u32 cp_int_cntl_reg, cp_int_cntl; 4970 int i, j; 4971 4972 switch (state) { 4973 case AMDGPU_IRQ_STATE_DISABLE: 4974 case AMDGPU_IRQ_STATE_ENABLE: 4975 for (i = 0; i < adev->gfx.me.num_me; i++) { 4976 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4977 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4978 4979 if (cp_int_cntl_reg) { 4980 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4981 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4982 OPCODE_ERROR_INT_ENABLE, 4983 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4984 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4985 } 4986 } 4987 } 4988 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4989 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4990 /* MECs start at 1 */ 4991 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4992 4993 if (cp_int_cntl_reg) { 4994 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4995 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4996 OPCODE_ERROR_INT_ENABLE, 4997 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4998 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4999 } 5000 } 5001 } 5002 break; 5003 default: 5004 break; 5005 } 5006 return 0; 5007 } 5008 5009 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5010 struct amdgpu_irq_src *source, 5011 unsigned int type, 5012 enum amdgpu_interrupt_state state) 5013 { 5014 u32 cp_int_cntl_reg, cp_int_cntl; 5015 int i, j; 5016 5017 switch (state) { 5018 case AMDGPU_IRQ_STATE_DISABLE: 5019 case AMDGPU_IRQ_STATE_ENABLE: 5020 for (i = 0; i < adev->gfx.me.num_me; i++) { 5021 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5022 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 5023 5024 if (cp_int_cntl_reg) { 5025 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5026 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5027 PRIV_INSTR_INT_ENABLE, 5028 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5029 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5030 } 5031 } 5032 } 5033 break; 5034 default: 5035 break; 5036 } 5037 5038 return 0; 5039 } 5040 5041 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5042 struct amdgpu_iv_entry *entry) 5043 { 5044 u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK; 5045 5046 /* 5047 * Try KQ first by ring_id; UQ as fallback. KCQ and UQ never share 5048 * a HW slot (compute_hqd_mask contract). 5049 */ 5050 if (!adev->gfx.disable_kq) { 5051 u8 me_id, pipe_id, queue_id; 5052 struct amdgpu_ring *ring; 5053 int i; 5054 5055 me_id = (entry->ring_id & 0x0c) >> 2; 5056 pipe_id = (entry->ring_id & 0x03) >> 0; 5057 queue_id = (entry->ring_id & 0x70) >> 4; 5058 5059 switch (me_id) { 5060 case 0: 5061 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5062 ring = &adev->gfx.gfx_ring[i]; 5063 if (ring->me == me_id && ring->pipe == pipe_id && 5064 ring->queue == queue_id) { 5065 drm_sched_fault(&ring->sched); 5066 return; 5067 } 5068 } 5069 break; 5070 case 1: 5071 case 2: 5072 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5073 ring = &adev->gfx.compute_ring[i]; 5074 if (ring->me == me_id && ring->pipe == pipe_id && 5075 ring->queue == queue_id) { 5076 drm_sched_fault(&ring->sched); 5077 return; 5078 } 5079 } 5080 break; 5081 default: 5082 BUG(); 5083 break; 5084 } 5085 } 5086 5087 /* No KQ matched: HW slot is a MES-scheduled user queue. */ 5088 if (adev->enable_mes && doorbell_offset) 5089 amdgpu_userq_process_reset_irq(adev, entry->pasid, 5090 doorbell_offset); 5091 } 5092 5093 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5094 struct amdgpu_irq_src *source, 5095 struct amdgpu_iv_entry *entry) 5096 { 5097 DRM_ERROR("Illegal register access in command stream\n"); 5098 gfx_v12_0_handle_priv_fault(adev, entry); 5099 return 0; 5100 } 5101 5102 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5103 struct amdgpu_irq_src *source, 5104 struct amdgpu_iv_entry *entry) 5105 { 5106 DRM_ERROR("Illegal opcode in command stream\n"); 5107 gfx_v12_0_handle_priv_fault(adev, entry); 5108 return 0; 5109 } 5110 5111 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5112 struct amdgpu_irq_src *source, 5113 struct amdgpu_iv_entry *entry) 5114 { 5115 DRM_ERROR("Illegal instruction in command stream\n"); 5116 gfx_v12_0_handle_priv_fault(adev, entry); 5117 return 0; 5118 } 5119 5120 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5121 { 5122 const unsigned int gcr_cntl = 5123 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5124 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5125 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5126 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5127 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5128 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5129 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5130 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5131 5132 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5133 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5134 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5135 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5136 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5137 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5138 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5139 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5140 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5141 } 5142 5143 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5144 { 5145 /* Header itself is a NOP packet */ 5146 if (num_nop == 1) { 5147 amdgpu_ring_write(ring, ring->funcs->nop); 5148 return; 5149 } 5150 5151 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5152 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5153 5154 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5155 amdgpu_ring_insert_nop(ring, num_nop - 1); 5156 } 5157 5158 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5159 { 5160 /* Emit the cleaner shader */ 5161 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5162 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5163 } 5164 5165 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5166 { 5167 struct amdgpu_device *adev = ip_block->adev; 5168 uint32_t i, j, k, reg, index = 0; 5169 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5170 5171 if (!adev->gfx.ip_dump_core) 5172 return; 5173 5174 for (i = 0; i < reg_count; i++) 5175 drm_printf(p, "%-50s \t 0x%08x\n", 5176 gc_reg_list_12_0[i].reg_name, 5177 adev->gfx.ip_dump_core[i]); 5178 5179 /* print compute queue registers for all instances */ 5180 if (!adev->gfx.ip_dump_compute_queues) 5181 return; 5182 5183 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5184 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5185 adev->gfx.mec.num_mec, 5186 adev->gfx.mec.num_pipe_per_mec, 5187 adev->gfx.mec.num_queue_per_pipe); 5188 5189 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5190 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5191 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5192 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5193 for (reg = 0; reg < reg_count; reg++) { 5194 drm_printf(p, "%-50s \t 0x%08x\n", 5195 gc_cp_reg_list_12[reg].reg_name, 5196 adev->gfx.ip_dump_compute_queues[index + reg]); 5197 } 5198 index += reg_count; 5199 } 5200 } 5201 } 5202 5203 /* print gfx queue registers for all instances */ 5204 if (!adev->gfx.ip_dump_gfx_queues) 5205 return; 5206 5207 index = 0; 5208 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5209 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5210 adev->gfx.me.num_me, 5211 adev->gfx.me.num_pipe_per_me, 5212 adev->gfx.me.num_queue_per_pipe); 5213 5214 for (i = 0; i < adev->gfx.me.num_me; i++) { 5215 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5216 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5217 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5218 for (reg = 0; reg < reg_count; reg++) { 5219 drm_printf(p, "%-50s \t 0x%08x\n", 5220 gc_gfx_queue_reg_list_12[reg].reg_name, 5221 adev->gfx.ip_dump_gfx_queues[index + reg]); 5222 } 5223 index += reg_count; 5224 } 5225 } 5226 } 5227 } 5228 5229 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5230 { 5231 struct amdgpu_device *adev = ip_block->adev; 5232 uint32_t i, j, k, reg, index = 0; 5233 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5234 5235 if (!adev->gfx.ip_dump_core) 5236 return; 5237 5238 amdgpu_gfx_off_ctrl(adev, false); 5239 for (i = 0; i < reg_count; i++) 5240 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5241 amdgpu_gfx_off_ctrl(adev, true); 5242 5243 /* dump compute queue registers for all instances */ 5244 if (!adev->gfx.ip_dump_compute_queues) 5245 return; 5246 5247 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5248 amdgpu_gfx_off_ctrl(adev, false); 5249 mutex_lock(&adev->srbm_mutex); 5250 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5251 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5252 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5253 /* ME0 is for GFX so start from 1 for CP */ 5254 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5255 for (reg = 0; reg < reg_count; reg++) { 5256 adev->gfx.ip_dump_compute_queues[index + reg] = 5257 RREG32(SOC15_REG_ENTRY_OFFSET( 5258 gc_cp_reg_list_12[reg])); 5259 } 5260 index += reg_count; 5261 } 5262 } 5263 } 5264 soc24_grbm_select(adev, 0, 0, 0, 0); 5265 mutex_unlock(&adev->srbm_mutex); 5266 amdgpu_gfx_off_ctrl(adev, true); 5267 5268 /* dump gfx queue registers for all instances */ 5269 if (!adev->gfx.ip_dump_gfx_queues) 5270 return; 5271 5272 index = 0; 5273 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5274 amdgpu_gfx_off_ctrl(adev, false); 5275 mutex_lock(&adev->srbm_mutex); 5276 for (i = 0; i < adev->gfx.me.num_me; i++) { 5277 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5278 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5279 soc24_grbm_select(adev, i, j, k, 0); 5280 5281 for (reg = 0; reg < reg_count; reg++) { 5282 adev->gfx.ip_dump_gfx_queues[index + reg] = 5283 RREG32(SOC15_REG_ENTRY_OFFSET( 5284 gc_gfx_queue_reg_list_12[reg])); 5285 } 5286 index += reg_count; 5287 } 5288 } 5289 } 5290 soc24_grbm_select(adev, 0, 0, 0, 0); 5291 mutex_unlock(&adev->srbm_mutex); 5292 amdgpu_gfx_off_ctrl(adev, true); 5293 } 5294 5295 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5296 unsigned int vmid, 5297 struct amdgpu_fence *timedout_fence) 5298 { 5299 struct amdgpu_device *adev = ring->adev; 5300 bool use_mmio = adev->gfx.me.use_mmio_for_reset; 5301 5302 return amdgpu_gfx_mes_reset_queue(ring, vmid, timedout_fence, use_mmio); 5303 } 5304 5305 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5306 unsigned int vmid, 5307 struct amdgpu_fence *timedout_fence) 5308 { 5309 struct amdgpu_device *adev = ring->adev; 5310 5311 return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); 5312 } 5313 5314 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5315 { 5316 amdgpu_gfx_profile_ring_begin_use(ring); 5317 5318 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5319 } 5320 5321 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5322 { 5323 amdgpu_gfx_profile_ring_end_use(ring); 5324 5325 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5326 } 5327 5328 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5329 .name = "gfx_v12_0", 5330 .early_init = gfx_v12_0_early_init, 5331 .sw_init = gfx_v12_0_sw_init, 5332 .sw_fini = gfx_v12_0_sw_fini, 5333 .hw_init = gfx_v12_0_hw_init, 5334 .hw_fini = gfx_v12_0_hw_fini, 5335 .suspend = gfx_v12_0_suspend, 5336 .resume = gfx_v12_0_resume, 5337 .is_idle = gfx_v12_0_is_idle, 5338 .wait_for_idle = gfx_v12_0_wait_for_idle, 5339 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5340 .set_powergating_state = gfx_v12_0_set_powergating_state, 5341 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5342 .dump_ip_state = gfx_v12_ip_dump, 5343 .print_ip_state = gfx_v12_ip_print, 5344 }; 5345 5346 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5347 .type = AMDGPU_RING_TYPE_GFX, 5348 .align_mask = 0xff, 5349 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5350 .support_64bit_ptrs = true, 5351 .secure_submission_supported = true, 5352 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5353 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5354 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5355 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5356 5 + /* COND_EXEC */ 5357 7 + /* PIPELINE_SYNC */ 5358 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5359 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5360 2 + /* VM_FLUSH */ 5361 8 + /* FENCE for VM_FLUSH */ 5362 5 + /* COND_EXEC */ 5363 7 + /* HDP_flush */ 5364 4 + /* VGT_flush */ 5365 31 + /* DE_META */ 5366 3 + /* CNTX_CTRL */ 5367 5 + /* HDP_INVL */ 5368 8 + 8 + /* FENCE x2 */ 5369 8 + /* gfx_v12_0_emit_mem_sync */ 5370 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5371 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5372 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5373 .emit_fence = gfx_v12_0_ring_emit_fence, 5374 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5375 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5376 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5377 .test_ring = gfx_v12_0_ring_test_ring, 5378 .test_ib = gfx_v12_0_ring_test_ib, 5379 .insert_nop = gfx_v12_ring_insert_nop, 5380 .pad_ib = amdgpu_ring_generic_pad_ib, 5381 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5382 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5383 .preempt_ib = amdgpu_gfx_ring_preempt_ib, 5384 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5385 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5386 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5387 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5388 .reset = gfx_v12_0_reset_kgq, 5389 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5390 .begin_use = gfx_v12_0_ring_begin_use, 5391 .end_use = gfx_v12_0_ring_end_use, 5392 }; 5393 5394 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5395 .type = AMDGPU_RING_TYPE_COMPUTE, 5396 .align_mask = 0xff, 5397 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5398 .support_64bit_ptrs = true, 5399 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5400 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5401 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5402 .emit_frame_size = 5403 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5404 5 + /* hdp invalidate */ 5405 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5406 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5407 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5408 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5409 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5410 8 + /* gfx_v12_0_emit_mem_sync */ 5411 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5412 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5413 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5414 .emit_fence = gfx_v12_0_ring_emit_fence, 5415 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5416 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5417 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5418 .test_ring = gfx_v12_0_ring_test_ring, 5419 .test_ib = gfx_v12_0_ring_test_ib, 5420 .insert_nop = gfx_v12_ring_insert_nop, 5421 .pad_ib = amdgpu_ring_generic_pad_ib, 5422 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5423 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5424 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5425 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5426 .reset = gfx_v12_0_reset_kcq, 5427 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5428 .begin_use = gfx_v12_0_ring_begin_use, 5429 .end_use = gfx_v12_0_ring_end_use, 5430 }; 5431 5432 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5433 .type = AMDGPU_RING_TYPE_KIQ, 5434 .align_mask = 0xff, 5435 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5436 .support_64bit_ptrs = true, 5437 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5438 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5439 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5440 .emit_frame_size = 5441 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5442 5 + /*hdp invalidate */ 5443 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5444 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5445 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5446 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5447 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5448 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5449 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5450 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5451 .test_ring = gfx_v12_0_ring_test_ring, 5452 .test_ib = gfx_v12_0_ring_test_ib, 5453 .insert_nop = amdgpu_ring_insert_nop, 5454 .pad_ib = amdgpu_ring_generic_pad_ib, 5455 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5456 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5457 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5458 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5459 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5460 }; 5461 5462 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5463 { 5464 int i; 5465 5466 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5467 5468 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5469 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5470 5471 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5472 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5473 } 5474 5475 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5476 .set = gfx_v12_0_set_eop_interrupt_state, 5477 .process = gfx_v12_0_eop_irq, 5478 }; 5479 5480 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5481 .set = gfx_v12_0_set_priv_reg_fault_state, 5482 .process = gfx_v12_0_priv_reg_irq, 5483 }; 5484 5485 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5486 .set = gfx_v12_0_set_bad_op_fault_state, 5487 .process = gfx_v12_0_bad_op_irq, 5488 }; 5489 5490 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5491 .set = gfx_v12_0_set_priv_inst_fault_state, 5492 .process = gfx_v12_0_priv_inst_irq, 5493 }; 5494 5495 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5496 { 5497 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5498 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5499 5500 adev->gfx.priv_reg_irq.num_types = 1; 5501 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5502 5503 adev->gfx.bad_op_irq.num_types = 1; 5504 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5505 5506 adev->gfx.priv_inst_irq.num_types = 1; 5507 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5508 } 5509 5510 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5511 { 5512 if (adev->flags & AMD_IS_APU) 5513 adev->gfx.imu.mode = MISSION_MODE; 5514 else 5515 adev->gfx.imu.mode = DEBUG_MODE; 5516 5517 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5518 } 5519 5520 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5521 { 5522 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5523 } 5524 5525 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5526 { 5527 /* set gfx eng mqd */ 5528 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5529 sizeof(struct v12_gfx_mqd); 5530 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5531 gfx_v12_0_gfx_mqd_init; 5532 /* set compute eng mqd */ 5533 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5534 sizeof(struct v12_compute_mqd); 5535 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5536 gfx_v12_0_compute_mqd_init; 5537 } 5538 5539 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5540 u32 bitmap) 5541 { 5542 u32 data; 5543 5544 if (!bitmap) 5545 return; 5546 5547 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5548 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5549 5550 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5551 } 5552 5553 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5554 { 5555 u32 data, wgp_bitmask; 5556 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5557 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5558 5559 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5560 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5561 5562 wgp_bitmask = 5563 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5564 5565 return (~data) & wgp_bitmask; 5566 } 5567 5568 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5569 { 5570 u32 wgp_idx, wgp_active_bitmap; 5571 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5572 5573 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5574 cu_active_bitmap = 0; 5575 5576 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5577 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5578 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5579 if (wgp_active_bitmap & (1 << wgp_idx)) 5580 cu_active_bitmap |= cu_bitmap_per_wgp; 5581 } 5582 5583 return cu_active_bitmap; 5584 } 5585 5586 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5587 struct amdgpu_cu_info *cu_info) 5588 { 5589 int i, j, k, counter, active_cu_number = 0; 5590 u32 mask, bitmap; 5591 unsigned disable_masks[8 * 2]; 5592 5593 if (!adev || !cu_info) 5594 return -EINVAL; 5595 5596 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 5597 5598 mutex_lock(&adev->grbm_idx_mutex); 5599 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5600 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5601 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5602 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5603 continue; 5604 mask = 1; 5605 counter = 0; 5606 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5607 if (i < 8 && j < 2) 5608 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5609 adev, disable_masks[i * 2 + j]); 5610 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5611 5612 /** 5613 * GFX12 could support more than 4 SEs, while the bitmap 5614 * in cu_info struct is 4x4 and ioctl interface struct 5615 * drm_amdgpu_info_device should keep stable. 5616 * So we use last two columns of bitmap to store cu mask for 5617 * SEs 4 to 7, the layout of the bitmap is as below: 5618 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5619 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5620 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5621 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5622 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5623 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5624 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5625 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5626 */ 5627 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5628 5629 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5630 if (bitmap & mask) 5631 counter++; 5632 5633 mask <<= 1; 5634 } 5635 active_cu_number += counter; 5636 } 5637 } 5638 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5639 mutex_unlock(&adev->grbm_idx_mutex); 5640 5641 cu_info->number = active_cu_number; 5642 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5643 5644 return 0; 5645 } 5646 5647 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5648 .type = AMD_IP_BLOCK_TYPE_GFX, 5649 .major = 12, 5650 .minor = 0, 5651 .rev = 0, 5652 .funcs = &gfx_v12_0_ip_funcs, 5653 }; 5654