1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_0.h" 47 #include "nbif_v6_3_1.h" 48 #include "mes_v12_0.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 65 66 #define DEFAULT_SH_MEM_CONFIG \ 67 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 68 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 69 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 70 71 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 72 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 73 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 74 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 75 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 76 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 77 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 78 struct amdgpu_cu_info *cu_info); 79 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 80 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 81 u32 sh_num, u32 instance, int xcc_id); 82 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 83 84 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 85 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 86 uint32_t val); 87 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 88 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 89 uint16_t pasid, uint32_t flush_type, 90 bool all_hub, uint8_t dst_sel); 91 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 92 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 93 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 94 bool enable); 95 96 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 97 uint64_t queue_mask) 98 { 99 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 100 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 101 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 102 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 103 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 104 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 105 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 106 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 107 amdgpu_ring_write(kiq_ring, 0); 108 } 109 110 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 111 struct amdgpu_ring *ring) 112 { 113 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 114 uint64_t wptr_addr = ring->wptr_gpu_addr; 115 uint32_t me = 0, eng_sel = 0; 116 117 switch (ring->funcs->type) { 118 case AMDGPU_RING_TYPE_COMPUTE: 119 me = 1; 120 eng_sel = 0; 121 break; 122 case AMDGPU_RING_TYPE_GFX: 123 me = 0; 124 eng_sel = 4; 125 break; 126 case AMDGPU_RING_TYPE_MES: 127 me = 2; 128 eng_sel = 5; 129 break; 130 default: 131 WARN_ON(1); 132 } 133 134 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 135 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 136 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 137 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 138 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 139 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 140 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 141 PACKET3_MAP_QUEUES_ME((me)) | 142 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 143 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 144 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 145 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 146 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 147 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 148 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 149 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 150 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 151 } 152 153 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 154 struct amdgpu_ring *ring, 155 enum amdgpu_unmap_queues_action action, 156 u64 gpu_addr, u64 seq) 157 { 158 struct amdgpu_device *adev = kiq_ring->adev; 159 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 160 161 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 162 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 163 return; 164 } 165 166 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 167 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 168 PACKET3_UNMAP_QUEUES_ACTION(action) | 169 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 170 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 171 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 172 amdgpu_ring_write(kiq_ring, 173 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 174 175 if (action == PREEMPT_QUEUES_NO_UNMAP) { 176 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 177 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 178 amdgpu_ring_write(kiq_ring, seq); 179 } else { 180 amdgpu_ring_write(kiq_ring, 0); 181 amdgpu_ring_write(kiq_ring, 0); 182 amdgpu_ring_write(kiq_ring, 0); 183 } 184 } 185 186 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 187 struct amdgpu_ring *ring, 188 u64 addr, u64 seq) 189 { 190 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 191 192 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 193 amdgpu_ring_write(kiq_ring, 194 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 195 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 196 PACKET3_QUERY_STATUS_COMMAND(2)); 197 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 198 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 199 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 200 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 201 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 202 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 203 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 204 } 205 206 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 207 uint16_t pasid, 208 uint32_t flush_type, 209 bool all_hub) 210 { 211 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 212 } 213 214 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 215 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 216 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 217 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 218 .kiq_query_status = gfx_v12_0_kiq_query_status, 219 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 220 .set_resources_size = 8, 221 .map_queues_size = 7, 222 .unmap_queues_size = 6, 223 .query_status_size = 7, 224 .invalidate_tlbs_size = 2, 225 }; 226 227 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 228 { 229 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 230 } 231 232 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 233 int mem_space, int opt, uint32_t addr0, 234 uint32_t addr1, uint32_t ref, 235 uint32_t mask, uint32_t inv) 236 { 237 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 238 amdgpu_ring_write(ring, 239 /* memory (1) or register (0) */ 240 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 241 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 242 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 243 WAIT_REG_MEM_ENGINE(eng_sel))); 244 245 if (mem_space) 246 BUG_ON(addr0 & 0x3); /* Dword align */ 247 amdgpu_ring_write(ring, addr0); 248 amdgpu_ring_write(ring, addr1); 249 amdgpu_ring_write(ring, ref); 250 amdgpu_ring_write(ring, mask); 251 amdgpu_ring_write(ring, inv); /* poll interval */ 252 } 253 254 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 255 { 256 struct amdgpu_device *adev = ring->adev; 257 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 258 uint32_t tmp = 0; 259 unsigned i; 260 int r; 261 262 WREG32(scratch, 0xCAFEDEAD); 263 r = amdgpu_ring_alloc(ring, 5); 264 if (r) { 265 dev_err(adev->dev, 266 "amdgpu: cp failed to lock ring %d (%d).\n", 267 ring->idx, r); 268 return r; 269 } 270 271 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 272 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 273 } else { 274 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 275 amdgpu_ring_write(ring, scratch - 276 PACKET3_SET_UCONFIG_REG_START); 277 amdgpu_ring_write(ring, 0xDEADBEEF); 278 } 279 amdgpu_ring_commit(ring); 280 281 for (i = 0; i < adev->usec_timeout; i++) { 282 tmp = RREG32(scratch); 283 if (tmp == 0xDEADBEEF) 284 break; 285 if (amdgpu_emu_mode == 1) 286 msleep(1); 287 else 288 udelay(1); 289 } 290 291 if (i >= adev->usec_timeout) 292 r = -ETIMEDOUT; 293 return r; 294 } 295 296 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 297 { 298 struct amdgpu_device *adev = ring->adev; 299 struct amdgpu_ib ib; 300 struct dma_fence *f = NULL; 301 unsigned index; 302 uint64_t gpu_addr; 303 volatile uint32_t *cpu_ptr; 304 long r; 305 306 /* MES KIQ fw hasn't indirect buffer support for now */ 307 if (adev->enable_mes_kiq && 308 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 309 return 0; 310 311 memset(&ib, 0, sizeof(ib)); 312 313 if (ring->is_mes_queue) { 314 uint32_t padding, offset; 315 316 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 317 padding = amdgpu_mes_ctx_get_offs(ring, 318 AMDGPU_MES_CTX_PADDING_OFFS); 319 320 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 321 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 322 323 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 324 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 325 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 326 } else { 327 r = amdgpu_device_wb_get(adev, &index); 328 if (r) 329 return r; 330 331 gpu_addr = adev->wb.gpu_addr + (index * 4); 332 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 333 cpu_ptr = &adev->wb.wb[index]; 334 335 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 336 if (r) { 337 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 338 goto err1; 339 } 340 } 341 342 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 343 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 344 ib.ptr[2] = lower_32_bits(gpu_addr); 345 ib.ptr[3] = upper_32_bits(gpu_addr); 346 ib.ptr[4] = 0xDEADBEEF; 347 ib.length_dw = 5; 348 349 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 350 if (r) 351 goto err2; 352 353 r = dma_fence_wait_timeout(f, false, timeout); 354 if (r == 0) { 355 r = -ETIMEDOUT; 356 goto err2; 357 } else if (r < 0) { 358 goto err2; 359 } 360 361 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 362 r = 0; 363 else 364 r = -EINVAL; 365 err2: 366 if (!ring->is_mes_queue) 367 amdgpu_ib_free(adev, &ib, NULL); 368 dma_fence_put(f); 369 err1: 370 if (!ring->is_mes_queue) 371 amdgpu_device_wb_free(adev, index); 372 return r; 373 } 374 375 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 376 { 377 amdgpu_ucode_release(&adev->gfx.pfp_fw); 378 amdgpu_ucode_release(&adev->gfx.me_fw); 379 amdgpu_ucode_release(&adev->gfx.rlc_fw); 380 amdgpu_ucode_release(&adev->gfx.mec_fw); 381 382 kfree(adev->gfx.rlc.register_list_format); 383 } 384 385 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 386 { 387 const struct psp_firmware_header_v1_0 *toc_hdr; 388 int err = 0; 389 390 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 391 "amdgpu/%s_toc.bin", ucode_prefix); 392 if (err) 393 goto out; 394 395 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 396 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 397 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 398 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 399 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 400 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 401 return 0; 402 out: 403 amdgpu_ucode_release(&adev->psp.toc_fw); 404 return err; 405 } 406 407 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 408 { 409 char ucode_prefix[15]; 410 int err; 411 const struct rlc_firmware_header_v2_0 *rlc_hdr; 412 uint16_t version_major; 413 uint16_t version_minor; 414 415 DRM_DEBUG("\n"); 416 417 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 418 419 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 420 "amdgpu/%s_pfp.bin", ucode_prefix); 421 if (err) 422 goto out; 423 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 424 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 425 426 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 427 "amdgpu/%s_me.bin", ucode_prefix); 428 if (err) 429 goto out; 430 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 431 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 432 433 if (!amdgpu_sriov_vf(adev)) { 434 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 435 "amdgpu/%s_rlc.bin", ucode_prefix); 436 if (err) 437 goto out; 438 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 439 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 440 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 441 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 442 if (err) 443 goto out; 444 } 445 446 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 447 "amdgpu/%s_mec.bin", ucode_prefix); 448 if (err) 449 goto out; 450 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 451 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 452 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 453 454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 455 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 456 457 /* only one MEC for gfx 12 */ 458 adev->gfx.mec2_fw = NULL; 459 460 if (adev->gfx.imu.funcs) { 461 if (adev->gfx.imu.funcs->init_microcode) { 462 err = adev->gfx.imu.funcs->init_microcode(adev); 463 if (err) 464 dev_err(adev->dev, "Failed to load imu firmware!\n"); 465 } 466 } 467 468 out: 469 if (err) { 470 amdgpu_ucode_release(&adev->gfx.pfp_fw); 471 amdgpu_ucode_release(&adev->gfx.me_fw); 472 amdgpu_ucode_release(&adev->gfx.rlc_fw); 473 amdgpu_ucode_release(&adev->gfx.mec_fw); 474 } 475 476 return err; 477 } 478 479 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 480 { 481 u32 count = 0; 482 const struct cs_section_def *sect = NULL; 483 const struct cs_extent_def *ext = NULL; 484 485 count += 1; 486 487 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 488 if (sect->id == SECT_CONTEXT) { 489 for (ext = sect->section; ext->extent != NULL; ++ext) 490 count += 2 + ext->reg_count; 491 } else 492 return 0; 493 } 494 495 return count; 496 } 497 498 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 499 volatile u32 *buffer) 500 { 501 u32 count = 0, clustercount = 0, i; 502 const struct cs_section_def *sect = NULL; 503 const struct cs_extent_def *ext = NULL; 504 505 if (adev->gfx.rlc.cs_data == NULL) 506 return; 507 if (buffer == NULL) 508 return; 509 510 count += 1; 511 512 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 513 if (sect->id == SECT_CONTEXT) { 514 for (ext = sect->section; ext->extent != NULL; ++ext) { 515 clustercount++; 516 buffer[count++] = ext->reg_count; 517 buffer[count++] = ext->reg_index; 518 519 for (i = 0; i < ext->reg_count; i++) 520 buffer[count++] = cpu_to_le32(ext->extent[i]); 521 } 522 } else 523 return; 524 } 525 526 buffer[0] = clustercount; 527 } 528 529 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 530 { 531 /* clear state block */ 532 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 533 &adev->gfx.rlc.clear_state_gpu_addr, 534 (void **)&adev->gfx.rlc.cs_ptr); 535 536 /* jump table block */ 537 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 538 &adev->gfx.rlc.cp_table_gpu_addr, 539 (void **)&adev->gfx.rlc.cp_table_ptr); 540 } 541 542 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 543 { 544 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 545 546 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 547 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 548 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 549 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 550 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 551 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 552 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 553 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 554 adev->gfx.rlc.rlcg_reg_access_supported = true; 555 } 556 557 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 558 { 559 const struct cs_section_def *cs_data; 560 int r; 561 562 adev->gfx.rlc.cs_data = gfx12_cs_data; 563 564 cs_data = adev->gfx.rlc.cs_data; 565 566 if (cs_data) { 567 /* init clear state block */ 568 r = amdgpu_gfx_rlc_init_csb(adev); 569 if (r) 570 return r; 571 } 572 573 /* init spm vmid with 0xf */ 574 if (adev->gfx.rlc.funcs->update_spm_vmid) 575 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 576 577 return 0; 578 } 579 580 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 581 { 582 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 583 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 584 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 585 } 586 587 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 588 { 589 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 590 591 amdgpu_gfx_graphics_queue_acquire(adev); 592 } 593 594 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 595 { 596 int r; 597 u32 *hpd; 598 size_t mec_hpd_size; 599 600 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 601 602 /* take ownership of the relevant compute queues */ 603 amdgpu_gfx_compute_queue_acquire(adev); 604 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 605 606 if (mec_hpd_size) { 607 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 608 AMDGPU_GEM_DOMAIN_GTT, 609 &adev->gfx.mec.hpd_eop_obj, 610 &adev->gfx.mec.hpd_eop_gpu_addr, 611 (void **)&hpd); 612 if (r) { 613 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 614 gfx_v12_0_mec_fini(adev); 615 return r; 616 } 617 618 memset(hpd, 0, mec_hpd_size); 619 620 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 621 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 622 } 623 624 return 0; 625 } 626 627 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 628 { 629 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 630 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 631 (address << SQ_IND_INDEX__INDEX__SHIFT)); 632 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 633 } 634 635 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 636 uint32_t thread, uint32_t regno, 637 uint32_t num, uint32_t *out) 638 { 639 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 640 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 641 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 642 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 643 (SQ_IND_INDEX__AUTO_INCR_MASK)); 644 while (num--) 645 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 646 } 647 648 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 649 uint32_t xcc_id, 650 uint32_t simd, uint32_t wave, 651 uint32_t *dst, int *no_fields) 652 { 653 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 654 * field when performing a select_se_sh so it should be 655 * zero here */ 656 WARN_ON(simd != 0); 657 658 /* type 4 wave data */ 659 dst[(*no_fields)++] = 4; 660 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 661 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 662 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 663 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 664 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 665 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 666 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 667 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 668 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 669 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 670 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 671 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 672 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 673 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 674 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 675 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 676 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 677 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 678 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 679 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 680 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 681 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 682 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 683 } 684 685 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 686 uint32_t xcc_id, uint32_t simd, 687 uint32_t wave, uint32_t start, 688 uint32_t size, uint32_t *dst) 689 { 690 WARN_ON(simd != 0); 691 692 wave_read_regs( 693 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 694 dst); 695 } 696 697 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 698 uint32_t xcc_id, uint32_t simd, 699 uint32_t wave, uint32_t thread, 700 uint32_t start, uint32_t size, 701 uint32_t *dst) 702 { 703 wave_read_regs( 704 adev, wave, thread, 705 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 706 } 707 708 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 709 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 710 { 711 soc24_grbm_select(adev, me, pipe, q, vm); 712 } 713 714 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 715 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 716 .select_se_sh = &gfx_v12_0_select_se_sh, 717 .read_wave_data = &gfx_v12_0_read_wave_data, 718 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 719 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 720 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 721 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 722 }; 723 724 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 725 { 726 727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 728 case IP_VERSION(12, 0, 0): 729 case IP_VERSION(12, 0, 1): 730 adev->gfx.config.max_hw_contexts = 8; 731 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 732 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 733 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 734 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 735 break; 736 default: 737 BUG(); 738 break; 739 } 740 741 return 0; 742 } 743 744 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 745 int me, int pipe, int queue) 746 { 747 int r; 748 struct amdgpu_ring *ring; 749 unsigned int irq_type; 750 751 ring = &adev->gfx.gfx_ring[ring_id]; 752 753 ring->me = me; 754 ring->pipe = pipe; 755 ring->queue = queue; 756 757 ring->ring_obj = NULL; 758 ring->use_doorbell = true; 759 760 if (!ring_id) 761 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 762 else 763 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 764 ring->vm_hub = AMDGPU_GFXHUB(0); 765 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 766 767 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 768 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 769 AMDGPU_RING_PRIO_DEFAULT, NULL); 770 if (r) 771 return r; 772 return 0; 773 } 774 775 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 776 int mec, int pipe, int queue) 777 { 778 int r; 779 unsigned irq_type; 780 struct amdgpu_ring *ring; 781 unsigned int hw_prio; 782 783 ring = &adev->gfx.compute_ring[ring_id]; 784 785 /* mec0 is me1 */ 786 ring->me = mec + 1; 787 ring->pipe = pipe; 788 ring->queue = queue; 789 790 ring->ring_obj = NULL; 791 ring->use_doorbell = true; 792 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 793 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 794 + (ring_id * GFX12_MEC_HPD_SIZE); 795 ring->vm_hub = AMDGPU_GFXHUB(0); 796 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 797 798 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 799 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 800 + ring->pipe; 801 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 802 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 803 /* type-2 packets are deprecated on MEC, use type-3 instead */ 804 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 805 hw_prio, NULL); 806 if (r) 807 return r; 808 809 return 0; 810 } 811 812 static struct { 813 SOC24_FIRMWARE_ID id; 814 unsigned int offset; 815 unsigned int size; 816 unsigned int size_x16; 817 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 818 819 #define RLC_TOC_OFFSET_DWUNIT 8 820 #define RLC_SIZE_MULTIPLE 1024 821 #define RLC_TOC_UMF_SIZE_inM 23ULL 822 #define RLC_TOC_FORMAT_API 165ULL 823 824 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 825 { 826 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 827 828 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 829 rlc_autoload_info[ucode->id].id = ucode->id; 830 rlc_autoload_info[ucode->id].offset = 831 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 832 rlc_autoload_info[ucode->id].size = 833 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 834 ucode->size * 4; 835 ucode++; 836 } 837 } 838 839 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 840 { 841 uint32_t total_size = 0; 842 SOC24_FIRMWARE_ID id; 843 844 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 845 846 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 847 total_size += rlc_autoload_info[id].size; 848 849 /* In case the offset in rlc toc ucode is aligned */ 850 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 851 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 852 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 853 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 854 total_size = RLC_TOC_UMF_SIZE_inM << 20; 855 856 return total_size; 857 } 858 859 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 860 { 861 int r; 862 uint32_t total_size; 863 864 total_size = gfx_v12_0_calc_toc_total_size(adev); 865 866 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 867 AMDGPU_GEM_DOMAIN_VRAM, 868 &adev->gfx.rlc.rlc_autoload_bo, 869 &adev->gfx.rlc.rlc_autoload_gpu_addr, 870 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 871 872 if (r) { 873 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 874 return r; 875 } 876 877 return 0; 878 } 879 880 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 881 SOC24_FIRMWARE_ID id, 882 const void *fw_data, 883 uint32_t fw_size) 884 { 885 uint32_t toc_offset; 886 uint32_t toc_fw_size; 887 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 888 889 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 890 return; 891 892 toc_offset = rlc_autoload_info[id].offset; 893 toc_fw_size = rlc_autoload_info[id].size; 894 895 if (fw_size == 0) 896 fw_size = toc_fw_size; 897 898 if (fw_size > toc_fw_size) 899 fw_size = toc_fw_size; 900 901 memcpy(ptr + toc_offset, fw_data, fw_size); 902 903 if (fw_size < toc_fw_size) 904 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 905 } 906 907 static void 908 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 909 { 910 void *data; 911 uint32_t size; 912 uint32_t *toc_ptr; 913 914 data = adev->psp.toc.start_addr; 915 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 916 917 toc_ptr = (uint32_t *)data + size / 4 - 2; 918 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 919 920 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 921 data, size); 922 } 923 924 static void 925 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 926 { 927 const __le32 *fw_data; 928 uint32_t fw_size; 929 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 930 const struct rlc_firmware_header_v2_0 *rlc_hdr; 931 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 932 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 933 uint16_t version_major, version_minor; 934 935 /* pfp ucode */ 936 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 937 adev->gfx.pfp_fw->data; 938 /* instruction */ 939 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 940 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 941 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 942 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 943 fw_data, fw_size); 944 /* data */ 945 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 946 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 947 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 948 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 949 fw_data, fw_size); 950 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 951 fw_data, fw_size); 952 /* me ucode */ 953 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 954 adev->gfx.me_fw->data; 955 /* instruction */ 956 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 957 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 958 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 959 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 960 fw_data, fw_size); 961 /* data */ 962 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 963 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 964 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 965 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 966 fw_data, fw_size); 967 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 968 fw_data, fw_size); 969 /* mec ucode */ 970 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 971 adev->gfx.mec_fw->data; 972 /* instruction */ 973 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 974 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 975 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 976 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 977 fw_data, fw_size); 978 /* data */ 979 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 980 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 981 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 982 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 983 fw_data, fw_size); 984 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 985 fw_data, fw_size); 986 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 987 fw_data, fw_size); 988 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 989 fw_data, fw_size); 990 991 /* rlc ucode */ 992 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 993 adev->gfx.rlc_fw->data; 994 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 995 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 996 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 997 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 998 fw_data, fw_size); 999 1000 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1001 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1002 if (version_major == 2) { 1003 if (version_minor >= 1) { 1004 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1005 1006 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1007 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1008 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1009 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1010 fw_data, fw_size); 1011 1012 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1013 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1014 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1015 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1016 fw_data, fw_size); 1017 } 1018 if (version_minor >= 2) { 1019 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1020 1021 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1022 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1023 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1024 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1025 fw_data, fw_size); 1026 1027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1028 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1029 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1030 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1031 fw_data, fw_size); 1032 } 1033 } 1034 } 1035 1036 static void 1037 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1038 { 1039 const __le32 *fw_data; 1040 uint32_t fw_size; 1041 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1042 1043 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1044 adev->sdma.instance[0].fw->data; 1045 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1046 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1047 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1048 1049 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1050 fw_data, fw_size); 1051 } 1052 1053 static void 1054 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1055 { 1056 const __le32 *fw_data; 1057 unsigned fw_size; 1058 const struct mes_firmware_header_v1_0 *mes_hdr; 1059 int pipe, ucode_id, data_id; 1060 1061 for (pipe = 0; pipe < 2; pipe++) { 1062 if (pipe == 0) { 1063 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1064 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1065 } else { 1066 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1067 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1068 } 1069 1070 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1071 adev->mes.fw[pipe]->data; 1072 1073 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1074 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1075 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1076 1077 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1078 1079 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1080 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1081 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1082 1083 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1084 } 1085 } 1086 1087 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1088 { 1089 uint32_t rlc_g_offset, rlc_g_size; 1090 uint64_t gpu_addr; 1091 uint32_t data; 1092 1093 /* RLC autoload sequence 2: copy ucode */ 1094 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1095 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1096 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1097 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1098 1099 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1100 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1101 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1102 1103 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1104 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1105 1106 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1107 1108 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1109 /* RLC autoload sequence 3: load IMU fw */ 1110 if (adev->gfx.imu.funcs->load_microcode) 1111 adev->gfx.imu.funcs->load_microcode(adev); 1112 /* RLC autoload sequence 4 init IMU fw */ 1113 if (adev->gfx.imu.funcs->setup_imu) 1114 adev->gfx.imu.funcs->setup_imu(adev); 1115 if (adev->gfx.imu.funcs->start_imu) 1116 adev->gfx.imu.funcs->start_imu(adev); 1117 1118 /* RLC autoload sequence 5 disable gpa mode */ 1119 gfx_v12_0_disable_gpa_mode(adev); 1120 } else { 1121 /* unhalt rlc to start autoload without imu */ 1122 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1123 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1124 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1125 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1126 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int gfx_v12_0_sw_init(void *handle) 1133 { 1134 int i, j, k, r, ring_id = 0; 1135 unsigned num_compute_rings; 1136 int xcc_id = 0; 1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1138 1139 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1140 case IP_VERSION(12, 0, 0): 1141 case IP_VERSION(12, 0, 1): 1142 adev->gfx.me.num_me = 1; 1143 adev->gfx.me.num_pipe_per_me = 1; 1144 adev->gfx.me.num_queue_per_pipe = 1; 1145 adev->gfx.mec.num_mec = 2; 1146 adev->gfx.mec.num_pipe_per_mec = 2; 1147 adev->gfx.mec.num_queue_per_pipe = 4; 1148 break; 1149 default: 1150 adev->gfx.me.num_me = 1; 1151 adev->gfx.me.num_pipe_per_me = 1; 1152 adev->gfx.me.num_queue_per_pipe = 1; 1153 adev->gfx.mec.num_mec = 1; 1154 adev->gfx.mec.num_pipe_per_mec = 4; 1155 adev->gfx.mec.num_queue_per_pipe = 8; 1156 break; 1157 } 1158 1159 /* recalculate compute rings to use based on hardware configuration */ 1160 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1161 adev->gfx.mec.num_queue_per_pipe) / 2; 1162 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1163 num_compute_rings); 1164 1165 /* EOP Event */ 1166 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1167 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1168 &adev->gfx.eop_irq); 1169 if (r) 1170 return r; 1171 1172 /* Privileged reg */ 1173 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1174 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1175 &adev->gfx.priv_reg_irq); 1176 if (r) 1177 return r; 1178 1179 /* Privileged inst */ 1180 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1181 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1182 &adev->gfx.priv_inst_irq); 1183 if (r) 1184 return r; 1185 1186 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1187 1188 gfx_v12_0_me_init(adev); 1189 1190 r = gfx_v12_0_rlc_init(adev); 1191 if (r) { 1192 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1193 return r; 1194 } 1195 1196 r = gfx_v12_0_mec_init(adev); 1197 if (r) { 1198 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1199 return r; 1200 } 1201 1202 /* set up the gfx ring */ 1203 for (i = 0; i < adev->gfx.me.num_me; i++) { 1204 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1205 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1206 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1207 continue; 1208 1209 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1210 i, k, j); 1211 if (r) 1212 return r; 1213 ring_id++; 1214 } 1215 } 1216 } 1217 1218 ring_id = 0; 1219 /* set up the compute queues - allocate horizontally across pipes */ 1220 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1221 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1222 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1223 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1224 0, i, k, j)) 1225 continue; 1226 1227 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1228 i, k, j); 1229 if (r) 1230 return r; 1231 1232 ring_id++; 1233 } 1234 } 1235 } 1236 1237 if (!adev->enable_mes_kiq) { 1238 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1239 if (r) { 1240 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1241 return r; 1242 } 1243 1244 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1245 if (r) 1246 return r; 1247 } 1248 1249 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1250 if (r) 1251 return r; 1252 1253 /* allocate visible FB for rlc auto-loading fw */ 1254 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1255 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1256 if (r) 1257 return r; 1258 } 1259 1260 r = gfx_v12_0_gpu_early_init(adev); 1261 if (r) 1262 return r; 1263 1264 return 0; 1265 } 1266 1267 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1268 { 1269 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1270 &adev->gfx.pfp.pfp_fw_gpu_addr, 1271 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1272 1273 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1274 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1275 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1276 } 1277 1278 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1279 { 1280 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1281 &adev->gfx.me.me_fw_gpu_addr, 1282 (void **)&adev->gfx.me.me_fw_ptr); 1283 1284 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1285 &adev->gfx.me.me_fw_data_gpu_addr, 1286 (void **)&adev->gfx.me.me_fw_data_ptr); 1287 } 1288 1289 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1290 { 1291 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1292 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1293 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1294 } 1295 1296 static int gfx_v12_0_sw_fini(void *handle) 1297 { 1298 int i; 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 1301 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1302 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1303 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1304 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1305 1306 amdgpu_gfx_mqd_sw_fini(adev, 0); 1307 1308 if (!adev->enable_mes_kiq) { 1309 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1310 amdgpu_gfx_kiq_fini(adev, 0); 1311 } 1312 1313 gfx_v12_0_pfp_fini(adev); 1314 gfx_v12_0_me_fini(adev); 1315 gfx_v12_0_rlc_fini(adev); 1316 gfx_v12_0_mec_fini(adev); 1317 1318 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1319 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1320 1321 gfx_v12_0_free_microcode(adev); 1322 1323 return 0; 1324 } 1325 1326 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1327 u32 sh_num, u32 instance, int xcc_id) 1328 { 1329 u32 data; 1330 1331 if (instance == 0xffffffff) 1332 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1333 INSTANCE_BROADCAST_WRITES, 1); 1334 else 1335 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1336 instance); 1337 1338 if (se_num == 0xffffffff) 1339 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1340 1); 1341 else 1342 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1343 1344 if (sh_num == 0xffffffff) 1345 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1346 1); 1347 else 1348 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1349 1350 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1351 } 1352 1353 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1354 { 1355 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1356 1357 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1358 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1359 GRBM_CC_GC_SA_UNIT_DISABLE, 1360 SA_DISABLE); 1361 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1362 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1363 GRBM_GC_USER_SA_UNIT_DISABLE, 1364 SA_DISABLE); 1365 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1366 adev->gfx.config.max_shader_engines); 1367 1368 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1369 } 1370 1371 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1372 { 1373 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1374 u32 rb_mask; 1375 1376 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1377 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1378 CC_RB_BACKEND_DISABLE, 1379 BACKEND_DISABLE); 1380 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1381 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1382 GC_USER_RB_BACKEND_DISABLE, 1383 BACKEND_DISABLE); 1384 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1385 adev->gfx.config.max_shader_engines); 1386 1387 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1388 } 1389 1390 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1391 { 1392 u32 rb_bitmap_width_per_sa; 1393 u32 max_sa; 1394 u32 active_sa_bitmap; 1395 u32 global_active_rb_bitmap; 1396 u32 active_rb_bitmap = 0; 1397 u32 i; 1398 1399 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1400 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1401 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1402 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1403 1404 /* generate active rb bitmap according to active sa bitmap */ 1405 max_sa = adev->gfx.config.max_shader_engines * 1406 adev->gfx.config.max_sh_per_se; 1407 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1408 adev->gfx.config.max_sh_per_se; 1409 for (i = 0; i < max_sa; i++) { 1410 if (active_sa_bitmap & (1 << i)) 1411 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1412 } 1413 1414 active_rb_bitmap |= global_active_rb_bitmap; 1415 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1416 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1417 } 1418 1419 #define LDS_APP_BASE 0x1 1420 #define SCRATCH_APP_BASE 0x2 1421 1422 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1423 { 1424 int i; 1425 uint32_t sh_mem_bases; 1426 uint32_t data; 1427 1428 /* 1429 * Configure apertures: 1430 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1431 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1432 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1433 */ 1434 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1435 SCRATCH_APP_BASE; 1436 1437 mutex_lock(&adev->srbm_mutex); 1438 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1439 soc24_grbm_select(adev, 0, 0, 0, i); 1440 /* CP and shaders */ 1441 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1442 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1443 1444 /* Enable trap for each kfd vmid. */ 1445 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1446 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1447 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1448 } 1449 soc24_grbm_select(adev, 0, 0, 0, 0); 1450 mutex_unlock(&adev->srbm_mutex); 1451 } 1452 1453 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1454 { 1455 /* TODO: harvest feature to be added later. */ 1456 } 1457 1458 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1459 { 1460 } 1461 1462 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1463 { 1464 u32 tmp; 1465 int i; 1466 1467 if (!amdgpu_sriov_vf(adev)) 1468 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1469 1470 gfx_v12_0_setup_rb(adev); 1471 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1472 gfx_v12_0_get_tcc_info(adev); 1473 adev->gfx.config.pa_sc_tile_steering_override = 0; 1474 1475 /* XXX SH_MEM regs */ 1476 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1477 mutex_lock(&adev->srbm_mutex); 1478 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1479 soc24_grbm_select(adev, 0, 0, 0, i); 1480 /* CP and shaders */ 1481 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1482 if (i != 0) { 1483 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1484 (adev->gmc.private_aperture_start >> 48)); 1485 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1486 (adev->gmc.shared_aperture_start >> 48)); 1487 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1488 } 1489 } 1490 soc24_grbm_select(adev, 0, 0, 0, 0); 1491 1492 mutex_unlock(&adev->srbm_mutex); 1493 1494 gfx_v12_0_init_compute_vmid(adev); 1495 } 1496 1497 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1498 bool enable) 1499 { 1500 u32 tmp; 1501 1502 if (amdgpu_sriov_vf(adev)) 1503 return; 1504 1505 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1506 1507 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1508 enable ? 1 : 0); 1509 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1510 enable ? 1 : 0); 1511 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1512 enable ? 1 : 0); 1513 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1514 enable ? 1 : 0); 1515 1516 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1517 } 1518 1519 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1520 { 1521 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1522 1523 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1524 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1525 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1526 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1527 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1528 1529 return 0; 1530 } 1531 1532 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1533 { 1534 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1535 1536 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1537 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1538 } 1539 1540 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1541 { 1542 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1543 udelay(50); 1544 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1545 udelay(50); 1546 } 1547 1548 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1549 bool enable) 1550 { 1551 uint32_t rlc_pg_cntl; 1552 1553 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1554 1555 if (!enable) { 1556 /* RLC_PG_CNTL[23] = 0 (default) 1557 * RLC will wait for handshake acks with SMU 1558 * GFXOFF will be enabled 1559 * RLC_PG_CNTL[23] = 1 1560 * RLC will not issue any message to SMU 1561 * hence no handshake between SMU & RLC 1562 * GFXOFF will be disabled 1563 */ 1564 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1565 } else 1566 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1567 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1568 } 1569 1570 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1571 { 1572 /* TODO: enable rlc & smu handshake until smu 1573 * and gfxoff feature works as expected */ 1574 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1575 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1576 1577 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1578 udelay(50); 1579 } 1580 1581 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1582 { 1583 uint32_t tmp; 1584 1585 /* enable Save Restore Machine */ 1586 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1587 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1588 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1589 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1590 } 1591 1592 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1593 { 1594 const struct rlc_firmware_header_v2_0 *hdr; 1595 const __le32 *fw_data; 1596 unsigned i, fw_size; 1597 1598 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1599 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1600 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1601 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1602 1603 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1604 RLCG_UCODE_LOADING_START_ADDRESS); 1605 1606 for (i = 0; i < fw_size; i++) 1607 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1608 le32_to_cpup(fw_data++)); 1609 1610 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1611 } 1612 1613 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1614 { 1615 const struct rlc_firmware_header_v2_2 *hdr; 1616 const __le32 *fw_data; 1617 unsigned i, fw_size; 1618 u32 tmp; 1619 1620 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1621 1622 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1623 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1624 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1625 1626 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1627 1628 for (i = 0; i < fw_size; i++) { 1629 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1630 msleep(1); 1631 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1632 le32_to_cpup(fw_data++)); 1633 } 1634 1635 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1636 1637 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1638 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1639 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1640 1641 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1642 for (i = 0; i < fw_size; i++) { 1643 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1644 msleep(1); 1645 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1646 le32_to_cpup(fw_data++)); 1647 } 1648 1649 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1650 1651 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1652 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1653 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1654 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1655 } 1656 1657 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1658 { 1659 const struct rlc_firmware_header_v2_0 *hdr; 1660 uint16_t version_major; 1661 uint16_t version_minor; 1662 1663 if (!adev->gfx.rlc_fw) 1664 return -EINVAL; 1665 1666 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1667 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1668 1669 version_major = le16_to_cpu(hdr->header.header_version_major); 1670 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1671 1672 if (version_major == 2) { 1673 gfx_v12_0_load_rlcg_microcode(adev); 1674 if (amdgpu_dpm == 1) { 1675 if (version_minor >= 2) 1676 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1677 } 1678 1679 return 0; 1680 } 1681 1682 return -EINVAL; 1683 } 1684 1685 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1686 { 1687 int r; 1688 1689 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1690 gfx_v12_0_init_csb(adev); 1691 1692 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1693 gfx_v12_0_rlc_enable_srm(adev); 1694 } else { 1695 if (amdgpu_sriov_vf(adev)) { 1696 gfx_v12_0_init_csb(adev); 1697 return 0; 1698 } 1699 1700 adev->gfx.rlc.funcs->stop(adev); 1701 1702 /* disable CG */ 1703 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1704 1705 /* disable PG */ 1706 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1707 1708 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1709 /* legacy rlc firmware loading */ 1710 r = gfx_v12_0_rlc_load_microcode(adev); 1711 if (r) 1712 return r; 1713 } 1714 1715 gfx_v12_0_init_csb(adev); 1716 1717 adev->gfx.rlc.funcs->start(adev); 1718 } 1719 1720 return 0; 1721 } 1722 1723 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 1724 { 1725 const struct gfx_firmware_header_v2_0 *pfp_hdr; 1726 const struct gfx_firmware_header_v2_0 *me_hdr; 1727 const struct gfx_firmware_header_v2_0 *mec_hdr; 1728 uint32_t pipe_id, tmp; 1729 1730 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1731 adev->gfx.mec_fw->data; 1732 me_hdr = (const struct gfx_firmware_header_v2_0 *) 1733 adev->gfx.me_fw->data; 1734 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 1735 adev->gfx.pfp_fw->data; 1736 1737 /* config pfp program start addr */ 1738 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 1739 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 1740 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 1741 (pfp_hdr->ucode_start_addr_hi << 30) | 1742 (pfp_hdr->ucode_start_addr_lo >> 2)); 1743 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 1744 pfp_hdr->ucode_start_addr_hi >> 2); 1745 } 1746 soc24_grbm_select(adev, 0, 0, 0, 0); 1747 1748 /* reset pfp pipe */ 1749 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 1750 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 1751 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 1752 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1753 1754 /* clear pfp pipe reset */ 1755 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 1756 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 1757 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1758 1759 /* config me program start addr */ 1760 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 1761 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 1762 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 1763 (me_hdr->ucode_start_addr_hi << 30) | 1764 (me_hdr->ucode_start_addr_lo >> 2)); 1765 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 1766 me_hdr->ucode_start_addr_hi>>2); 1767 } 1768 soc24_grbm_select(adev, 0, 0, 0, 0); 1769 1770 /* reset me pipe */ 1771 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 1772 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 1773 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 1774 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1775 1776 /* clear me pipe reset */ 1777 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 1778 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 1779 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1780 1781 /* config mec program start addr */ 1782 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 1783 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 1784 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 1785 mec_hdr->ucode_start_addr_lo >> 2 | 1786 mec_hdr->ucode_start_addr_hi << 30); 1787 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1788 mec_hdr->ucode_start_addr_hi >> 2); 1789 } 1790 soc24_grbm_select(adev, 0, 0, 0, 0); 1791 1792 /* reset mec pipe */ 1793 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 1794 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 1795 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 1796 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 1797 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 1798 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 1799 1800 /* clear mec pipe reset */ 1801 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 1802 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 1803 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 1804 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 1805 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 1806 } 1807 1808 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 1809 { 1810 const struct gfx_firmware_header_v2_0 *cp_hdr; 1811 unsigned pipe_id, tmp; 1812 1813 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1814 adev->gfx.pfp_fw->data; 1815 mutex_lock(&adev->srbm_mutex); 1816 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 1817 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 1818 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 1819 (cp_hdr->ucode_start_addr_hi << 30) | 1820 (cp_hdr->ucode_start_addr_lo >> 2)); 1821 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 1822 cp_hdr->ucode_start_addr_hi>>2); 1823 1824 /* 1825 * Program CP_ME_CNTL to reset given PIPE to take 1826 * effect of CP_PFP_PRGRM_CNTR_START. 1827 */ 1828 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 1829 if (pipe_id == 0) 1830 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1831 PFP_PIPE0_RESET, 1); 1832 else 1833 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1834 PFP_PIPE1_RESET, 1); 1835 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1836 1837 /* Clear pfp pipe0 reset bit. */ 1838 if (pipe_id == 0) 1839 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1840 PFP_PIPE0_RESET, 0); 1841 else 1842 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1843 PFP_PIPE1_RESET, 0); 1844 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1845 } 1846 soc24_grbm_select(adev, 0, 0, 0, 0); 1847 mutex_unlock(&adev->srbm_mutex); 1848 } 1849 1850 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 1851 { 1852 const struct gfx_firmware_header_v2_0 *cp_hdr; 1853 unsigned pipe_id, tmp; 1854 1855 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1856 adev->gfx.me_fw->data; 1857 mutex_lock(&adev->srbm_mutex); 1858 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 1859 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 1860 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 1861 (cp_hdr->ucode_start_addr_hi << 30) | 1862 (cp_hdr->ucode_start_addr_lo >> 2) ); 1863 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 1864 cp_hdr->ucode_start_addr_hi>>2); 1865 1866 /* 1867 * Program CP_ME_CNTL to reset given PIPE to take 1868 * effect of CP_ME_PRGRM_CNTR_START. 1869 */ 1870 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 1871 if (pipe_id == 0) 1872 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1873 ME_PIPE0_RESET, 1); 1874 else 1875 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1876 ME_PIPE1_RESET, 1); 1877 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1878 1879 /* Clear pfp pipe0 reset bit. */ 1880 if (pipe_id == 0) 1881 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1882 ME_PIPE0_RESET, 0); 1883 else 1884 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 1885 ME_PIPE1_RESET, 0); 1886 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1887 } 1888 soc24_grbm_select(adev, 0, 0, 0, 0); 1889 mutex_unlock(&adev->srbm_mutex); 1890 } 1891 1892 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 1893 { 1894 const struct gfx_firmware_header_v2_0 *cp_hdr; 1895 unsigned pipe_id; 1896 1897 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1898 adev->gfx.mec_fw->data; 1899 mutex_lock(&adev->srbm_mutex); 1900 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 1901 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 1902 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 1903 cp_hdr->ucode_start_addr_lo >> 2 | 1904 cp_hdr->ucode_start_addr_hi << 30); 1905 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1906 cp_hdr->ucode_start_addr_hi >> 2); 1907 } 1908 soc24_grbm_select(adev, 0, 0, 0, 0); 1909 mutex_unlock(&adev->srbm_mutex); 1910 } 1911 1912 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 1913 { 1914 uint32_t cp_status; 1915 uint32_t bootload_status; 1916 int i; 1917 1918 for (i = 0; i < adev->usec_timeout; i++) { 1919 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 1920 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 1921 1922 if ((cp_status == 0) && 1923 (REG_GET_FIELD(bootload_status, 1924 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 1925 break; 1926 } 1927 udelay(1); 1928 if (amdgpu_emu_mode) 1929 msleep(10); 1930 } 1931 1932 if (i >= adev->usec_timeout) { 1933 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 1934 return -ETIMEDOUT; 1935 } 1936 1937 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1938 gfx_v12_0_set_pfp_ucode_start_addr(adev); 1939 gfx_v12_0_set_me_ucode_start_addr(adev); 1940 gfx_v12_0_set_mec_ucode_start_addr(adev); 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1947 { 1948 int i; 1949 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 1950 1951 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 1952 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 1953 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 1954 1955 for (i = 0; i < adev->usec_timeout; i++) { 1956 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 1957 break; 1958 udelay(1); 1959 } 1960 1961 if (i >= adev->usec_timeout) 1962 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 1963 1964 return 0; 1965 } 1966 1967 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 1968 { 1969 int r; 1970 const struct gfx_firmware_header_v2_0 *pfp_hdr; 1971 const __le32 *fw_ucode, *fw_data; 1972 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 1973 uint32_t tmp; 1974 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1975 1976 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 1977 adev->gfx.pfp_fw->data; 1978 1979 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1980 1981 /* instruction */ 1982 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 1983 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 1984 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 1985 /* data */ 1986 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1987 le32_to_cpu(pfp_hdr->data_offset_bytes)); 1988 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 1989 1990 /* 64kb align */ 1991 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 1992 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 1993 &adev->gfx.pfp.pfp_fw_obj, 1994 &adev->gfx.pfp.pfp_fw_gpu_addr, 1995 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1996 if (r) { 1997 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 1998 gfx_v12_0_pfp_fini(adev); 1999 return r; 2000 } 2001 2002 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2003 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2004 &adev->gfx.pfp.pfp_fw_data_obj, 2005 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2006 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2007 if (r) { 2008 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2009 gfx_v12_0_pfp_fini(adev); 2010 return r; 2011 } 2012 2013 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2014 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2015 2016 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2017 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2018 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2019 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2020 2021 if (amdgpu_emu_mode == 1) 2022 adev->hdp.funcs->flush_hdp(adev, NULL); 2023 2024 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2025 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2026 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2027 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2028 2029 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2030 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2031 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2032 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2033 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2034 2035 /* 2036 * Programming any of the CP_PFP_IC_BASE registers 2037 * forces invalidation of the ME L1 I$. Wait for the 2038 * invalidation complete 2039 */ 2040 for (i = 0; i < usec_timeout; i++) { 2041 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2042 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2043 INVALIDATE_CACHE_COMPLETE)) 2044 break; 2045 udelay(1); 2046 } 2047 2048 if (i >= usec_timeout) { 2049 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2050 return -EINVAL; 2051 } 2052 2053 /* Prime the L1 instruction caches */ 2054 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2055 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2056 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2057 /* Waiting for cache primed*/ 2058 for (i = 0; i < usec_timeout; i++) { 2059 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2060 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2061 ICACHE_PRIMED)) 2062 break; 2063 udelay(1); 2064 } 2065 2066 if (i >= usec_timeout) { 2067 dev_err(adev->dev, "failed to prime instruction cache\n"); 2068 return -EINVAL; 2069 } 2070 2071 mutex_lock(&adev->srbm_mutex); 2072 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2073 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2074 2075 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2076 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2077 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2078 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2079 } 2080 soc24_grbm_select(adev, 0, 0, 0, 0); 2081 mutex_unlock(&adev->srbm_mutex); 2082 2083 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2084 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2085 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2086 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2087 2088 /* Invalidate the data caches */ 2089 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2090 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2091 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2092 2093 for (i = 0; i < usec_timeout; i++) { 2094 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2095 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2096 INVALIDATE_DCACHE_COMPLETE)) 2097 break; 2098 udelay(1); 2099 } 2100 2101 if (i >= usec_timeout) { 2102 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2103 return -EINVAL; 2104 } 2105 2106 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2107 2108 return 0; 2109 } 2110 2111 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2112 { 2113 int r; 2114 const struct gfx_firmware_header_v2_0 *me_hdr; 2115 const __le32 *fw_ucode, *fw_data; 2116 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2117 uint32_t tmp; 2118 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2119 2120 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2121 adev->gfx.me_fw->data; 2122 2123 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2124 2125 /* instruction */ 2126 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2127 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2128 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2129 /* data */ 2130 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2131 le32_to_cpu(me_hdr->data_offset_bytes)); 2132 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2133 2134 /* 64kb align*/ 2135 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2136 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2137 &adev->gfx.me.me_fw_obj, 2138 &adev->gfx.me.me_fw_gpu_addr, 2139 (void **)&adev->gfx.me.me_fw_ptr); 2140 if (r) { 2141 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2142 gfx_v12_0_me_fini(adev); 2143 return r; 2144 } 2145 2146 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2147 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2148 &adev->gfx.me.me_fw_data_obj, 2149 &adev->gfx.me.me_fw_data_gpu_addr, 2150 (void **)&adev->gfx.me.me_fw_data_ptr); 2151 if (r) { 2152 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2153 gfx_v12_0_pfp_fini(adev); 2154 return r; 2155 } 2156 2157 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2158 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2159 2160 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2161 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2162 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2163 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2164 2165 if (amdgpu_emu_mode == 1) 2166 adev->hdp.funcs->flush_hdp(adev, NULL); 2167 2168 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2169 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2170 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2171 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2172 2173 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2174 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2175 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2176 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2177 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2178 2179 /* 2180 * Programming any of the CP_ME_IC_BASE registers 2181 * forces invalidation of the ME L1 I$. Wait for the 2182 * invalidation complete 2183 */ 2184 for (i = 0; i < usec_timeout; i++) { 2185 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2186 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2187 INVALIDATE_CACHE_COMPLETE)) 2188 break; 2189 udelay(1); 2190 } 2191 2192 if (i >= usec_timeout) { 2193 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2194 return -EINVAL; 2195 } 2196 2197 /* Prime the instruction caches */ 2198 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2199 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2200 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2201 2202 /* Waiting for instruction cache primed*/ 2203 for (i = 0; i < usec_timeout; i++) { 2204 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2205 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2206 ICACHE_PRIMED)) 2207 break; 2208 udelay(1); 2209 } 2210 2211 if (i >= usec_timeout) { 2212 dev_err(adev->dev, "failed to prime instruction cache\n"); 2213 return -EINVAL; 2214 } 2215 2216 mutex_lock(&adev->srbm_mutex); 2217 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2218 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2219 2220 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2221 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2222 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2223 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2224 } 2225 soc24_grbm_select(adev, 0, 0, 0, 0); 2226 mutex_unlock(&adev->srbm_mutex); 2227 2228 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2229 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2230 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2231 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2232 2233 /* Invalidate the data caches */ 2234 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2235 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2236 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2237 2238 for (i = 0; i < usec_timeout; i++) { 2239 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2240 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2241 INVALIDATE_DCACHE_COMPLETE)) 2242 break; 2243 udelay(1); 2244 } 2245 2246 if (i >= usec_timeout) { 2247 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2248 return -EINVAL; 2249 } 2250 2251 gfx_v12_0_set_me_ucode_start_addr(adev); 2252 2253 return 0; 2254 } 2255 2256 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2257 { 2258 int r; 2259 2260 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2261 return -EINVAL; 2262 2263 gfx_v12_0_cp_gfx_enable(adev, false); 2264 2265 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2266 if (r) { 2267 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2268 return r; 2269 } 2270 2271 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2272 if (r) { 2273 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2274 return r; 2275 } 2276 2277 return 0; 2278 } 2279 2280 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2281 { 2282 /* init the CP */ 2283 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2284 adev->gfx.config.max_hw_contexts - 1); 2285 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2286 2287 if (!amdgpu_async_gfx_ring) 2288 gfx_v12_0_cp_gfx_enable(adev, true); 2289 2290 return 0; 2291 } 2292 2293 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2294 CP_PIPE_ID pipe) 2295 { 2296 u32 tmp; 2297 2298 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2299 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2300 2301 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2302 } 2303 2304 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2305 struct amdgpu_ring *ring) 2306 { 2307 u32 tmp; 2308 2309 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2310 if (ring->use_doorbell) { 2311 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2312 DOORBELL_OFFSET, ring->doorbell_index); 2313 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2314 DOORBELL_EN, 1); 2315 } else { 2316 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2317 DOORBELL_EN, 0); 2318 } 2319 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2320 2321 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2322 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2323 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2324 2325 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2326 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2327 } 2328 2329 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2330 { 2331 struct amdgpu_ring *ring; 2332 u32 tmp; 2333 u32 rb_bufsz; 2334 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2335 u32 i; 2336 2337 /* Set the write pointer delay */ 2338 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2339 2340 /* set the RB to use vmid 0 */ 2341 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2342 2343 /* Init gfx ring 0 for pipe 0 */ 2344 mutex_lock(&adev->srbm_mutex); 2345 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2346 2347 /* Set ring buffer size */ 2348 ring = &adev->gfx.gfx_ring[0]; 2349 rb_bufsz = order_base_2(ring->ring_size / 8); 2350 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2351 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2352 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2353 2354 /* Initialize the ring buffer's write pointers */ 2355 ring->wptr = 0; 2356 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2357 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2358 2359 /* set the wb address wether it's enabled or not */ 2360 rptr_addr = ring->rptr_gpu_addr; 2361 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2362 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2363 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2364 2365 wptr_gpu_addr = ring->wptr_gpu_addr; 2366 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2367 lower_32_bits(wptr_gpu_addr)); 2368 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2369 upper_32_bits(wptr_gpu_addr)); 2370 2371 mdelay(1); 2372 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2373 2374 rb_addr = ring->gpu_addr >> 8; 2375 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2376 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2377 2378 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2379 2380 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2381 mutex_unlock(&adev->srbm_mutex); 2382 2383 /* Switch to pipe 0 */ 2384 mutex_lock(&adev->srbm_mutex); 2385 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2386 mutex_unlock(&adev->srbm_mutex); 2387 2388 /* start the ring */ 2389 gfx_v12_0_cp_gfx_start(adev); 2390 2391 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2392 ring = &adev->gfx.gfx_ring[i]; 2393 ring->sched.ready = true; 2394 } 2395 2396 return 0; 2397 } 2398 2399 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2400 { 2401 u32 data; 2402 2403 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2404 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2405 enable ? 0 : 1); 2406 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2407 enable ? 0 : 1); 2408 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2409 enable ? 0 : 1); 2410 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2411 enable ? 0 : 1); 2412 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2413 enable ? 0 : 1); 2414 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2415 enable ? 1 : 0); 2416 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2417 enable ? 1 : 0); 2418 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2419 enable ? 1 : 0); 2420 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2421 enable ? 1 : 0); 2422 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2423 enable ? 0 : 1); 2424 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2425 2426 adev->gfx.kiq[0].ring.sched.ready = enable; 2427 2428 udelay(50); 2429 } 2430 2431 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2432 { 2433 const struct gfx_firmware_header_v2_0 *mec_hdr; 2434 const __le32 *fw_ucode, *fw_data; 2435 u32 tmp, fw_ucode_size, fw_data_size; 2436 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2437 u32 *fw_ucode_ptr, *fw_data_ptr; 2438 int r; 2439 2440 if (!adev->gfx.mec_fw) 2441 return -EINVAL; 2442 2443 gfx_v12_0_cp_compute_enable(adev, false); 2444 2445 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2446 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2447 2448 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2449 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2450 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2451 2452 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2453 le32_to_cpu(mec_hdr->data_offset_bytes)); 2454 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2455 2456 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2457 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2458 &adev->gfx.mec.mec_fw_obj, 2459 &adev->gfx.mec.mec_fw_gpu_addr, 2460 (void **)&fw_ucode_ptr); 2461 if (r) { 2462 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2463 gfx_v12_0_mec_fini(adev); 2464 return r; 2465 } 2466 2467 r = amdgpu_bo_create_reserved(adev, 2468 ALIGN(fw_data_size, 64 * 1024) * 2469 adev->gfx.mec.num_pipe_per_mec, 2470 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2471 &adev->gfx.mec.mec_fw_data_obj, 2472 &adev->gfx.mec.mec_fw_data_gpu_addr, 2473 (void **)&fw_data_ptr); 2474 if (r) { 2475 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2476 gfx_v12_0_mec_fini(adev); 2477 return r; 2478 } 2479 2480 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2481 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2482 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2483 } 2484 2485 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2486 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2487 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2488 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2489 2490 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2491 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2492 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2493 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2494 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2495 2496 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2497 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2498 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2499 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2500 2501 mutex_lock(&adev->srbm_mutex); 2502 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2503 soc24_grbm_select(adev, 1, i, 0, 0); 2504 2505 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2506 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2507 i * ALIGN(fw_data_size, 64 * 1024))); 2508 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2509 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2510 i * ALIGN(fw_data_size, 64 * 1024))); 2511 2512 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2513 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2514 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2515 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2516 } 2517 mutex_unlock(&adev->srbm_mutex); 2518 soc24_grbm_select(adev, 0, 0, 0, 0); 2519 2520 /* Trigger an invalidation of the L1 instruction caches */ 2521 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2522 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2523 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2524 2525 /* Wait for invalidation complete */ 2526 for (i = 0; i < usec_timeout; i++) { 2527 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2528 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2529 INVALIDATE_DCACHE_COMPLETE)) 2530 break; 2531 udelay(1); 2532 } 2533 2534 if (i >= usec_timeout) { 2535 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2536 return -EINVAL; 2537 } 2538 2539 /* Trigger an invalidation of the L1 instruction caches */ 2540 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2541 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2542 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2543 2544 /* Wait for invalidation complete */ 2545 for (i = 0; i < usec_timeout; i++) { 2546 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2547 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2548 INVALIDATE_CACHE_COMPLETE)) 2549 break; 2550 udelay(1); 2551 } 2552 2553 if (i >= usec_timeout) { 2554 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2555 return -EINVAL; 2556 } 2557 2558 gfx_v12_0_set_mec_ucode_start_addr(adev); 2559 2560 return 0; 2561 } 2562 2563 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2564 { 2565 uint32_t tmp; 2566 struct amdgpu_device *adev = ring->adev; 2567 2568 /* tell RLC which is KIQ queue */ 2569 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2570 tmp &= 0xffffff00; 2571 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2572 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 2573 tmp |= 0x80; 2574 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 2575 } 2576 2577 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2578 { 2579 /* set graphics engine doorbell range */ 2580 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2581 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2582 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2583 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2584 2585 /* set compute engine doorbell range */ 2586 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2587 (adev->doorbell_index.kiq * 2) << 2); 2588 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2589 (adev->doorbell_index.userqueue_end * 2) << 2); 2590 } 2591 2592 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2593 struct amdgpu_mqd_prop *prop) 2594 { 2595 struct v12_gfx_mqd *mqd = m; 2596 uint64_t hqd_gpu_addr, wb_gpu_addr; 2597 uint32_t tmp; 2598 uint32_t rb_bufsz; 2599 2600 /* set up gfx hqd wptr */ 2601 mqd->cp_gfx_hqd_wptr = 0; 2602 mqd->cp_gfx_hqd_wptr_hi = 0; 2603 2604 /* set the pointer to the MQD */ 2605 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2606 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2607 2608 /* set up mqd control */ 2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2610 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2611 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2612 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2613 mqd->cp_gfx_mqd_control = tmp; 2614 2615 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2616 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2617 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2618 mqd->cp_gfx_hqd_vmid = 0; 2619 2620 /* set up default queue priority level 2621 * 0x0 = low priority, 0x1 = high priority */ 2622 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2623 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2624 mqd->cp_gfx_hqd_queue_priority = tmp; 2625 2626 /* set up time quantum */ 2627 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2628 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2629 mqd->cp_gfx_hqd_quantum = tmp; 2630 2631 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2632 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2633 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2634 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2635 2636 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2637 wb_gpu_addr = prop->rptr_gpu_addr; 2638 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2639 mqd->cp_gfx_hqd_rptr_addr_hi = 2640 upper_32_bits(wb_gpu_addr) & 0xffff; 2641 2642 /* set up rb_wptr_poll addr */ 2643 wb_gpu_addr = prop->wptr_gpu_addr; 2644 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2645 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2646 2647 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2648 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2649 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2650 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2651 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2652 #ifdef __BIG_ENDIAN 2653 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2654 #endif 2655 mqd->cp_gfx_hqd_cntl = tmp; 2656 2657 /* set up cp_doorbell_control */ 2658 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2659 if (prop->use_doorbell) { 2660 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2661 DOORBELL_OFFSET, prop->doorbell_index); 2662 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2663 DOORBELL_EN, 1); 2664 } else 2665 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2666 DOORBELL_EN, 0); 2667 mqd->cp_rb_doorbell_control = tmp; 2668 2669 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2670 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2671 2672 /* active the queue */ 2673 mqd->cp_gfx_hqd_active = 1; 2674 2675 return 0; 2676 } 2677 2678 static int gfx_v12_0_gfx_init_queue(struct amdgpu_ring *ring) 2679 { 2680 struct amdgpu_device *adev = ring->adev; 2681 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2682 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2683 2684 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2685 memset((void *)mqd, 0, sizeof(*mqd)); 2686 mutex_lock(&adev->srbm_mutex); 2687 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2688 amdgpu_ring_init_mqd(ring); 2689 soc24_grbm_select(adev, 0, 0, 0, 0); 2690 mutex_unlock(&adev->srbm_mutex); 2691 if (adev->gfx.me.mqd_backup[mqd_idx]) 2692 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2693 } else { 2694 /* restore mqd with the backup copy */ 2695 if (adev->gfx.me.mqd_backup[mqd_idx]) 2696 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2697 /* reset the ring */ 2698 ring->wptr = 0; 2699 *ring->wptr_cpu_addr = 0; 2700 amdgpu_ring_clear_ring(ring); 2701 } 2702 2703 return 0; 2704 } 2705 2706 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2707 { 2708 int r, i; 2709 struct amdgpu_ring *ring; 2710 2711 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2712 ring = &adev->gfx.gfx_ring[i]; 2713 2714 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2715 if (unlikely(r != 0)) 2716 goto done; 2717 2718 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2719 if (!r) { 2720 r = gfx_v12_0_gfx_init_queue(ring); 2721 amdgpu_bo_kunmap(ring->mqd_obj); 2722 ring->mqd_ptr = NULL; 2723 } 2724 amdgpu_bo_unreserve(ring->mqd_obj); 2725 if (r) 2726 goto done; 2727 } 2728 2729 r = amdgpu_gfx_enable_kgq(adev, 0); 2730 if (r) 2731 goto done; 2732 2733 r = gfx_v12_0_cp_gfx_start(adev); 2734 if (r) 2735 goto done; 2736 2737 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2738 ring = &adev->gfx.gfx_ring[i]; 2739 ring->sched.ready = true; 2740 } 2741 done: 2742 return r; 2743 } 2744 2745 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 2746 struct amdgpu_mqd_prop *prop) 2747 { 2748 struct v12_compute_mqd *mqd = m; 2749 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2750 uint32_t tmp; 2751 2752 mqd->header = 0xC0310800; 2753 mqd->compute_pipelinestat_enable = 0x00000001; 2754 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2755 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2756 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2757 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2758 mqd->compute_misc_reserved = 0x00000007; 2759 2760 eop_base_addr = prop->eop_gpu_addr >> 8; 2761 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2762 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2763 2764 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2765 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 2766 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2767 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 2768 2769 mqd->cp_hqd_eop_control = tmp; 2770 2771 /* enable doorbell? */ 2772 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 2773 2774 if (prop->use_doorbell) { 2775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2776 DOORBELL_OFFSET, prop->doorbell_index); 2777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2778 DOORBELL_EN, 1); 2779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2780 DOORBELL_SOURCE, 0); 2781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2782 DOORBELL_HIT, 0); 2783 } else { 2784 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2785 DOORBELL_EN, 0); 2786 } 2787 2788 mqd->cp_hqd_pq_doorbell_control = tmp; 2789 2790 /* disable the queue if it's active */ 2791 mqd->cp_hqd_dequeue_request = 0; 2792 mqd->cp_hqd_pq_rptr = 0; 2793 mqd->cp_hqd_pq_wptr_lo = 0; 2794 mqd->cp_hqd_pq_wptr_hi = 0; 2795 2796 /* set the pointer to the MQD */ 2797 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 2798 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2799 2800 /* set MQD vmid to 0 */ 2801 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 2802 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2803 mqd->cp_mqd_control = tmp; 2804 2805 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2806 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2807 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2808 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2809 2810 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2811 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 2812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2813 (order_base_2(prop->queue_size / 4) - 1)); 2814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2815 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 2816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 2818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2819 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2820 mqd->cp_hqd_pq_control = tmp; 2821 2822 /* set the wb address whether it's enabled or not */ 2823 wb_gpu_addr = prop->rptr_gpu_addr; 2824 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2825 mqd->cp_hqd_pq_rptr_report_addr_hi = 2826 upper_32_bits(wb_gpu_addr) & 0xffff; 2827 2828 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2829 wb_gpu_addr = prop->wptr_gpu_addr; 2830 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2831 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2832 2833 tmp = 0; 2834 /* enable the doorbell if requested */ 2835 if (prop->use_doorbell) { 2836 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 2837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2838 DOORBELL_OFFSET, prop->doorbell_index); 2839 2840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2841 DOORBELL_EN, 1); 2842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2843 DOORBELL_SOURCE, 0); 2844 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2845 DOORBELL_HIT, 0); 2846 } 2847 2848 mqd->cp_hqd_pq_doorbell_control = tmp; 2849 2850 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2851 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 2852 2853 /* set the vmid for the queue */ 2854 mqd->cp_hqd_vmid = 0; 2855 2856 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 2857 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 2858 mqd->cp_hqd_persistent_state = tmp; 2859 2860 /* set MIN_IB_AVAIL_SIZE */ 2861 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 2862 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2863 mqd->cp_hqd_ib_control = tmp; 2864 2865 /* set static priority for a compute queue/ring */ 2866 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 2867 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2868 2869 mqd->cp_hqd_active = prop->hqd_active; 2870 2871 return 0; 2872 } 2873 2874 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 2875 { 2876 struct amdgpu_device *adev = ring->adev; 2877 struct v12_compute_mqd *mqd = ring->mqd_ptr; 2878 int j; 2879 2880 /* inactivate the queue */ 2881 if (amdgpu_sriov_vf(adev)) 2882 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 2883 2884 /* disable wptr polling */ 2885 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2886 2887 /* write the EOP addr */ 2888 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 2889 mqd->cp_hqd_eop_base_addr_lo); 2890 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 2891 mqd->cp_hqd_eop_base_addr_hi); 2892 2893 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2894 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 2895 mqd->cp_hqd_eop_control); 2896 2897 /* enable doorbell? */ 2898 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 2899 mqd->cp_hqd_pq_doorbell_control); 2900 2901 /* disable the queue if it's active */ 2902 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 2903 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 2904 for (j = 0; j < adev->usec_timeout; j++) { 2905 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 2906 break; 2907 udelay(1); 2908 } 2909 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 2910 mqd->cp_hqd_dequeue_request); 2911 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 2912 mqd->cp_hqd_pq_rptr); 2913 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 2914 mqd->cp_hqd_pq_wptr_lo); 2915 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 2916 mqd->cp_hqd_pq_wptr_hi); 2917 } 2918 2919 /* set the pointer to the MQD */ 2920 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 2921 mqd->cp_mqd_base_addr_lo); 2922 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 2923 mqd->cp_mqd_base_addr_hi); 2924 2925 /* set MQD vmid to 0 */ 2926 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 2927 mqd->cp_mqd_control); 2928 2929 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2930 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 2931 mqd->cp_hqd_pq_base_lo); 2932 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 2933 mqd->cp_hqd_pq_base_hi); 2934 2935 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2936 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 2937 mqd->cp_hqd_pq_control); 2938 2939 /* set the wb address whether it's enabled or not */ 2940 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 2941 mqd->cp_hqd_pq_rptr_report_addr_lo); 2942 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2943 mqd->cp_hqd_pq_rptr_report_addr_hi); 2944 2945 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2946 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 2947 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2948 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2949 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2950 2951 /* enable the doorbell if requested */ 2952 if (ring->use_doorbell) { 2953 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2954 (adev->doorbell_index.kiq * 2) << 2); 2955 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2956 (adev->doorbell_index.userqueue_end * 2) << 2); 2957 } 2958 2959 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 2960 mqd->cp_hqd_pq_doorbell_control); 2961 2962 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2963 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 2964 mqd->cp_hqd_pq_wptr_lo); 2965 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 2966 mqd->cp_hqd_pq_wptr_hi); 2967 2968 /* set the vmid for the queue */ 2969 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 2970 2971 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 2972 mqd->cp_hqd_persistent_state); 2973 2974 /* activate the queue */ 2975 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 2976 mqd->cp_hqd_active); 2977 2978 if (ring->use_doorbell) 2979 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2980 2981 return 0; 2982 } 2983 2984 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 2985 { 2986 struct amdgpu_device *adev = ring->adev; 2987 struct v12_compute_mqd *mqd = ring->mqd_ptr; 2988 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2989 2990 gfx_v12_0_kiq_setting(ring); 2991 2992 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 2993 /* reset MQD to a clean status */ 2994 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2995 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2996 2997 /* reset ring buffer */ 2998 ring->wptr = 0; 2999 amdgpu_ring_clear_ring(ring); 3000 3001 mutex_lock(&adev->srbm_mutex); 3002 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3003 gfx_v12_0_kiq_init_register(ring); 3004 soc24_grbm_select(adev, 0, 0, 0, 0); 3005 mutex_unlock(&adev->srbm_mutex); 3006 } else { 3007 memset((void *)mqd, 0, sizeof(*mqd)); 3008 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3009 amdgpu_ring_clear_ring(ring); 3010 mutex_lock(&adev->srbm_mutex); 3011 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3012 amdgpu_ring_init_mqd(ring); 3013 gfx_v12_0_kiq_init_register(ring); 3014 soc24_grbm_select(adev, 0, 0, 0, 0); 3015 mutex_unlock(&adev->srbm_mutex); 3016 3017 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3018 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3019 } 3020 3021 return 0; 3022 } 3023 3024 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring) 3025 { 3026 struct amdgpu_device *adev = ring->adev; 3027 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3028 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3029 3030 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3031 memset((void *)mqd, 0, sizeof(*mqd)); 3032 mutex_lock(&adev->srbm_mutex); 3033 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3034 amdgpu_ring_init_mqd(ring); 3035 soc24_grbm_select(adev, 0, 0, 0, 0); 3036 mutex_unlock(&adev->srbm_mutex); 3037 3038 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3039 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3040 } else { 3041 /* restore MQD to a clean status */ 3042 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3043 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3044 /* reset ring buffer */ 3045 ring->wptr = 0; 3046 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3047 amdgpu_ring_clear_ring(ring); 3048 } 3049 3050 return 0; 3051 } 3052 3053 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3054 { 3055 struct amdgpu_ring *ring; 3056 int r; 3057 3058 ring = &adev->gfx.kiq[0].ring; 3059 3060 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3061 if (unlikely(r != 0)) 3062 return r; 3063 3064 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3065 if (unlikely(r != 0)) { 3066 amdgpu_bo_unreserve(ring->mqd_obj); 3067 return r; 3068 } 3069 3070 gfx_v12_0_kiq_init_queue(ring); 3071 amdgpu_bo_kunmap(ring->mqd_obj); 3072 ring->mqd_ptr = NULL; 3073 amdgpu_bo_unreserve(ring->mqd_obj); 3074 ring->sched.ready = true; 3075 return 0; 3076 } 3077 3078 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3079 { 3080 struct amdgpu_ring *ring = NULL; 3081 int r = 0, i; 3082 3083 if (!amdgpu_async_gfx_ring) 3084 gfx_v12_0_cp_compute_enable(adev, true); 3085 3086 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3087 ring = &adev->gfx.compute_ring[i]; 3088 3089 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3090 if (unlikely(r != 0)) 3091 goto done; 3092 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3093 if (!r) { 3094 r = gfx_v12_0_kcq_init_queue(ring); 3095 amdgpu_bo_kunmap(ring->mqd_obj); 3096 ring->mqd_ptr = NULL; 3097 } 3098 amdgpu_bo_unreserve(ring->mqd_obj); 3099 if (r) 3100 goto done; 3101 } 3102 3103 r = amdgpu_gfx_enable_kcq(adev, 0); 3104 done: 3105 return r; 3106 } 3107 3108 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3109 { 3110 int r, i; 3111 struct amdgpu_ring *ring; 3112 3113 if (!(adev->flags & AMD_IS_APU)) 3114 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3115 3116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3117 /* legacy firmware loading */ 3118 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3119 if (r) 3120 return r; 3121 3122 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3123 if (r) 3124 return r; 3125 } 3126 3127 gfx_v12_0_cp_set_doorbell_range(adev); 3128 3129 if (amdgpu_async_gfx_ring) { 3130 gfx_v12_0_cp_compute_enable(adev, true); 3131 gfx_v12_0_cp_gfx_enable(adev, true); 3132 } 3133 3134 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3135 r = amdgpu_mes_kiq_hw_init(adev); 3136 else 3137 r = gfx_v12_0_kiq_resume(adev); 3138 if (r) 3139 return r; 3140 3141 r = gfx_v12_0_kcq_resume(adev); 3142 if (r) 3143 return r; 3144 3145 if (!amdgpu_async_gfx_ring) { 3146 r = gfx_v12_0_cp_gfx_resume(adev); 3147 if (r) 3148 return r; 3149 } else { 3150 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3151 if (r) 3152 return r; 3153 } 3154 3155 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3156 ring = &adev->gfx.gfx_ring[i]; 3157 r = amdgpu_ring_test_helper(ring); 3158 if (r) 3159 return r; 3160 } 3161 3162 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3163 ring = &adev->gfx.compute_ring[i]; 3164 r = amdgpu_ring_test_helper(ring); 3165 if (r) 3166 return r; 3167 } 3168 3169 return 0; 3170 } 3171 3172 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3173 { 3174 gfx_v12_0_cp_gfx_enable(adev, enable); 3175 gfx_v12_0_cp_compute_enable(adev, enable); 3176 } 3177 3178 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3179 { 3180 int r; 3181 bool value; 3182 3183 r = adev->gfxhub.funcs->gart_enable(adev); 3184 if (r) 3185 return r; 3186 3187 adev->hdp.funcs->flush_hdp(adev, NULL); 3188 3189 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3190 false : true; 3191 3192 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3193 /* TODO investigate why this and the hdp flush above is needed, 3194 * are we missing a flush somewhere else? */ 3195 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3196 3197 return 0; 3198 } 3199 3200 static int get_gb_addr_config(struct amdgpu_device *adev) 3201 { 3202 u32 gb_addr_config; 3203 3204 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3205 if (gb_addr_config == 0) 3206 return -EINVAL; 3207 3208 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3209 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3210 3211 adev->gfx.config.gb_addr_config = gb_addr_config; 3212 3213 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3214 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3215 GB_ADDR_CONFIG, NUM_PIPES); 3216 3217 adev->gfx.config.max_tile_pipes = 3218 adev->gfx.config.gb_addr_config_fields.num_pipes; 3219 3220 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3221 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3222 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3223 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3224 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3225 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3226 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3227 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3228 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3229 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3230 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3231 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3232 3233 return 0; 3234 } 3235 3236 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3237 { 3238 uint32_t data; 3239 3240 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3241 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3242 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3243 3244 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3245 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3246 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3247 } 3248 3249 static int gfx_v12_0_hw_init(void *handle) 3250 { 3251 int r; 3252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3253 3254 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3255 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3256 /* RLC autoload sequence 1: Program rlc ram */ 3257 if (adev->gfx.imu.funcs->program_rlc_ram) 3258 adev->gfx.imu.funcs->program_rlc_ram(adev); 3259 } 3260 /* rlc autoload firmware */ 3261 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3262 if (r) 3263 return r; 3264 } else { 3265 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3266 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3267 if (adev->gfx.imu.funcs->load_microcode) 3268 adev->gfx.imu.funcs->load_microcode(adev); 3269 if (adev->gfx.imu.funcs->setup_imu) 3270 adev->gfx.imu.funcs->setup_imu(adev); 3271 if (adev->gfx.imu.funcs->start_imu) 3272 adev->gfx.imu.funcs->start_imu(adev); 3273 } 3274 3275 /* disable gpa mode in backdoor loading */ 3276 gfx_v12_0_disable_gpa_mode(adev); 3277 } 3278 } 3279 3280 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3281 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3282 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3283 if (r) { 3284 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3285 return r; 3286 } 3287 } 3288 3289 adev->gfx.is_poweron = true; 3290 3291 if (get_gb_addr_config(adev)) 3292 DRM_WARN("Invalid gb_addr_config !\n"); 3293 3294 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3295 gfx_v12_0_config_gfx_rs64(adev); 3296 3297 r = gfx_v12_0_gfxhub_enable(adev); 3298 if (r) 3299 return r; 3300 3301 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3302 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3303 (amdgpu_dpm == 1)) { 3304 /** 3305 * For gfx 12, rlc firmware loading relies on smu firmware is 3306 * loaded firstly, so in direct type, it has to load smc ucode 3307 * here before rlc. 3308 */ 3309 if (!(adev->flags & AMD_IS_APU)) { 3310 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3311 if (r) 3312 return r; 3313 } 3314 } 3315 3316 gfx_v12_0_constants_init(adev); 3317 3318 if (adev->nbio.funcs->gc_doorbell_init) 3319 adev->nbio.funcs->gc_doorbell_init(adev); 3320 3321 r = gfx_v12_0_rlc_resume(adev); 3322 if (r) 3323 return r; 3324 3325 /* 3326 * init golden registers and rlc resume may override some registers, 3327 * reconfig them here 3328 */ 3329 gfx_v12_0_tcp_harvest(adev); 3330 3331 r = gfx_v12_0_cp_resume(adev); 3332 if (r) 3333 return r; 3334 3335 return r; 3336 } 3337 3338 static int gfx_v12_0_kiq_disable_kgq(struct amdgpu_device *adev) 3339 { 3340 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 3341 struct amdgpu_ring *kiq_ring = &kiq->ring; 3342 int i, r = 0; 3343 3344 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3345 return -EINVAL; 3346 3347 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3348 adev->gfx.num_gfx_rings)) 3349 return -ENOMEM; 3350 3351 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3352 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3353 PREEMPT_QUEUES, 0, 0); 3354 3355 if (adev->gfx.kiq[0].ring.sched.ready) 3356 r = amdgpu_ring_test_helper(kiq_ring); 3357 3358 return r; 3359 } 3360 3361 static int gfx_v12_0_hw_fini(void *handle) 3362 { 3363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3364 int r; 3365 uint32_t tmp; 3366 3367 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3368 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3369 3370 if (!adev->no_hw_access) { 3371 if (amdgpu_async_gfx_ring) { 3372 r = gfx_v12_0_kiq_disable_kgq(adev); 3373 if (r) 3374 DRM_ERROR("KGQ disable failed\n"); 3375 } 3376 3377 if (amdgpu_gfx_disable_kcq(adev, 0)) 3378 DRM_ERROR("KCQ disable failed\n"); 3379 3380 amdgpu_mes_kiq_hw_fini(adev); 3381 } 3382 3383 if (amdgpu_sriov_vf(adev)) { 3384 gfx_v12_0_cp_gfx_enable(adev, false); 3385 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3386 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3387 tmp &= 0xffffff00; 3388 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3389 3390 return 0; 3391 } 3392 gfx_v12_0_cp_enable(adev, false); 3393 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3394 3395 adev->gfxhub.funcs->gart_disable(adev); 3396 3397 adev->gfx.is_poweron = false; 3398 3399 return 0; 3400 } 3401 3402 static int gfx_v12_0_suspend(void *handle) 3403 { 3404 return gfx_v12_0_hw_fini(handle); 3405 } 3406 3407 static int gfx_v12_0_resume(void *handle) 3408 { 3409 return gfx_v12_0_hw_init(handle); 3410 } 3411 3412 static bool gfx_v12_0_is_idle(void *handle) 3413 { 3414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3415 3416 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3417 GRBM_STATUS, GUI_ACTIVE)) 3418 return false; 3419 else 3420 return true; 3421 } 3422 3423 static int gfx_v12_0_wait_for_idle(void *handle) 3424 { 3425 unsigned i; 3426 u32 tmp; 3427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3428 3429 for (i = 0; i < adev->usec_timeout; i++) { 3430 /* read MC_STATUS */ 3431 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3432 GRBM_STATUS__GUI_ACTIVE_MASK; 3433 3434 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3435 return 0; 3436 udelay(1); 3437 } 3438 return -ETIMEDOUT; 3439 } 3440 3441 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3442 { 3443 uint64_t clock = 0; 3444 3445 if (adev->smuio.funcs && 3446 adev->smuio.funcs->get_gpu_clock_counter) 3447 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3448 else 3449 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3450 3451 return clock; 3452 } 3453 3454 static int gfx_v12_0_early_init(void *handle) 3455 { 3456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3457 3458 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3459 3460 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3461 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3462 AMDGPU_MAX_COMPUTE_RINGS); 3463 3464 gfx_v12_0_set_kiq_pm4_funcs(adev); 3465 gfx_v12_0_set_ring_funcs(adev); 3466 gfx_v12_0_set_irq_funcs(adev); 3467 gfx_v12_0_set_rlc_funcs(adev); 3468 gfx_v12_0_set_mqd_funcs(adev); 3469 gfx_v12_0_set_imu_funcs(adev); 3470 3471 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3472 3473 return gfx_v12_0_init_microcode(adev); 3474 } 3475 3476 static int gfx_v12_0_late_init(void *handle) 3477 { 3478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3479 int r; 3480 3481 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3482 if (r) 3483 return r; 3484 3485 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3486 if (r) 3487 return r; 3488 3489 return 0; 3490 } 3491 3492 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3493 { 3494 uint32_t rlc_cntl; 3495 3496 /* if RLC is not enabled, do nothing */ 3497 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3498 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3499 } 3500 3501 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3502 int xcc_id) 3503 { 3504 uint32_t data; 3505 unsigned i; 3506 3507 data = RLC_SAFE_MODE__CMD_MASK; 3508 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3509 3510 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3511 3512 /* wait for RLC_SAFE_MODE */ 3513 for (i = 0; i < adev->usec_timeout; i++) { 3514 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3515 RLC_SAFE_MODE, CMD)) 3516 break; 3517 udelay(1); 3518 } 3519 } 3520 3521 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3522 int xcc_id) 3523 { 3524 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3525 } 3526 3527 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3528 bool enable) 3529 { 3530 uint32_t def, data; 3531 3532 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3533 return; 3534 3535 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3536 3537 if (enable) 3538 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3539 else 3540 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3541 3542 if (def != data) 3543 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3544 } 3545 3546 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3547 struct amdgpu_ring *ring, 3548 unsigned vmid) 3549 { 3550 u32 reg, data; 3551 3552 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3553 if (amdgpu_sriov_is_pp_one_vf(adev)) 3554 data = RREG32_NO_KIQ(reg); 3555 else 3556 data = RREG32(reg); 3557 3558 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3559 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3560 3561 if (amdgpu_sriov_is_pp_one_vf(adev)) 3562 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3563 else 3564 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3565 3566 if (ring 3567 && amdgpu_sriov_is_pp_one_vf(adev) 3568 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3569 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3570 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3571 amdgpu_ring_emit_wreg(ring, reg, data); 3572 } 3573 } 3574 3575 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3576 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3577 .set_safe_mode = gfx_v12_0_set_safe_mode, 3578 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3579 .init = gfx_v12_0_rlc_init, 3580 .get_csb_size = gfx_v12_0_get_csb_size, 3581 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3582 .resume = gfx_v12_0_rlc_resume, 3583 .stop = gfx_v12_0_rlc_stop, 3584 .reset = gfx_v12_0_rlc_reset, 3585 .start = gfx_v12_0_rlc_start, 3586 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3587 }; 3588 3589 #if 0 3590 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3591 { 3592 /* TODO */ 3593 } 3594 3595 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3596 { 3597 /* TODO */ 3598 } 3599 #endif 3600 3601 static int gfx_v12_0_set_powergating_state(void *handle, 3602 enum amd_powergating_state state) 3603 { 3604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3605 bool enable = (state == AMD_PG_STATE_GATE); 3606 3607 if (amdgpu_sriov_vf(adev)) 3608 return 0; 3609 3610 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3611 case IP_VERSION(12, 0, 0): 3612 case IP_VERSION(12, 0, 1): 3613 amdgpu_gfx_off_ctrl(adev, enable); 3614 break; 3615 default: 3616 break; 3617 } 3618 3619 return 0; 3620 } 3621 3622 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3623 bool enable) 3624 { 3625 uint32_t def, data; 3626 3627 if (!(adev->cg_flags & 3628 (AMD_CG_SUPPORT_GFX_CGCG | 3629 AMD_CG_SUPPORT_GFX_CGLS | 3630 AMD_CG_SUPPORT_GFX_3D_CGCG | 3631 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3632 return; 3633 3634 if (enable) { 3635 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3636 3637 /* unset CGCG override */ 3638 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3639 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3640 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3641 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3642 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3643 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3644 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3645 3646 /* update CGCG override bits */ 3647 if (def != data) 3648 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3649 3650 /* enable cgcg FSM(0x0000363F) */ 3651 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3652 3653 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3654 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3655 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3656 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3657 } 3658 3659 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3660 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3661 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3662 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3663 } 3664 3665 if (def != data) 3666 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3667 3668 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3669 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3670 3671 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3672 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3673 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3674 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3675 } 3676 3677 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3678 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3679 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3680 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3681 } 3682 3683 if (def != data) 3684 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3685 3686 /* set IDLE_POLL_COUNT(0x00900100) */ 3687 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3688 3689 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3690 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3691 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3692 3693 if (def != data) 3694 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3695 3696 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3697 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3698 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3699 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3700 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3701 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3702 3703 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3704 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3705 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3706 3707 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3708 if (adev->sdma.num_instances > 1) { 3709 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3710 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3711 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3712 } 3713 } else { 3714 /* Program RLC_CGCG_CGLS_CTRL */ 3715 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3716 3717 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3718 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3719 3720 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3721 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3722 3723 if (def != data) 3724 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3725 3726 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3727 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3728 3729 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 3730 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3731 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3732 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3733 3734 if (def != data) 3735 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3736 3737 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3738 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 3739 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3740 3741 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3742 if (adev->sdma.num_instances > 1) { 3743 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 3744 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 3745 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 3746 } 3747 } 3748 } 3749 3750 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3751 bool enable) 3752 { 3753 uint32_t data, def; 3754 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 3755 return; 3756 3757 /* It is disabled by HW by default */ 3758 if (enable) { 3759 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3760 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3761 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3762 3763 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3764 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3765 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3766 3767 if (def != data) 3768 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3769 } 3770 } else { 3771 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 3772 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3773 3774 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3775 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3776 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3777 3778 if (def != data) 3779 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3780 } 3781 } 3782 } 3783 3784 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 3785 bool enable) 3786 { 3787 uint32_t def, data; 3788 3789 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 3790 return; 3791 3792 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3793 3794 if (enable) 3795 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3796 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 3797 else 3798 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3799 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 3800 3801 if (def != data) 3802 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3803 } 3804 3805 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 3806 bool enable) 3807 { 3808 uint32_t def, data; 3809 3810 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 3811 return; 3812 3813 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3814 3815 if (enable) 3816 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3817 else 3818 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3819 3820 if (def != data) 3821 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3822 } 3823 3824 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3825 bool enable) 3826 { 3827 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 3828 3829 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 3830 3831 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 3832 3833 gfx_v12_0_update_repeater_fgcg(adev, enable); 3834 3835 gfx_v12_0_update_sram_fgcg(adev, enable); 3836 3837 gfx_v12_0_update_perf_clk(adev, enable); 3838 3839 if (adev->cg_flags & 3840 (AMD_CG_SUPPORT_GFX_MGCG | 3841 AMD_CG_SUPPORT_GFX_CGLS | 3842 AMD_CG_SUPPORT_GFX_CGCG | 3843 AMD_CG_SUPPORT_GFX_3D_CGCG | 3844 AMD_CG_SUPPORT_GFX_3D_CGLS)) 3845 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 3846 3847 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 3848 3849 return 0; 3850 } 3851 3852 static int gfx_v12_0_set_clockgating_state(void *handle, 3853 enum amd_clockgating_state state) 3854 { 3855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3856 3857 if (amdgpu_sriov_vf(adev)) 3858 return 0; 3859 3860 switch (adev->ip_versions[GC_HWIP][0]) { 3861 case IP_VERSION(12, 0, 0): 3862 case IP_VERSION(12, 0, 1): 3863 gfx_v12_0_update_gfx_clock_gating(adev, 3864 state == AMD_CG_STATE_GATE); 3865 break; 3866 default: 3867 break; 3868 } 3869 3870 return 0; 3871 } 3872 3873 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 3874 { 3875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3876 int data; 3877 3878 /* AMD_CG_SUPPORT_GFX_MGCG */ 3879 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3880 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3881 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3882 3883 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 3884 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 3885 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 3886 3887 /* AMD_CG_SUPPORT_GFX_FGCG */ 3888 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 3889 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 3890 3891 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 3892 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 3893 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 3894 3895 /* AMD_CG_SUPPORT_GFX_CGCG */ 3896 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3897 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3898 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3899 3900 /* AMD_CG_SUPPORT_GFX_CGLS */ 3901 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3902 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3903 3904 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3905 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3906 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3907 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3908 3909 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3910 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3911 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3912 } 3913 3914 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3915 { 3916 /* gfx12 is 32bit rptr*/ 3917 return *(uint32_t *)ring->rptr_cpu_addr; 3918 } 3919 3920 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3921 { 3922 struct amdgpu_device *adev = ring->adev; 3923 u64 wptr; 3924 3925 /* XXX check if swapping is necessary on BE */ 3926 if (ring->use_doorbell) { 3927 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3928 } else { 3929 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 3930 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 3931 } 3932 3933 return wptr; 3934 } 3935 3936 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3937 { 3938 struct amdgpu_device *adev = ring->adev; 3939 uint32_t *wptr_saved; 3940 uint32_t *is_queue_unmap; 3941 uint64_t aggregated_db_index; 3942 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 3943 uint64_t wptr_tmp; 3944 3945 if (ring->is_mes_queue) { 3946 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 3947 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 3948 sizeof(uint32_t)); 3949 aggregated_db_index = 3950 amdgpu_mes_get_aggregated_doorbell_index(adev, 3951 ring->hw_prio); 3952 3953 wptr_tmp = ring->wptr & ring->buf_mask; 3954 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 3955 *wptr_saved = wptr_tmp; 3956 /* assume doorbell always being used by mes mapped queue */ 3957 if (*is_queue_unmap) { 3958 WDOORBELL64(aggregated_db_index, wptr_tmp); 3959 WDOORBELL64(ring->doorbell_index, wptr_tmp); 3960 } else { 3961 WDOORBELL64(ring->doorbell_index, wptr_tmp); 3962 3963 if (*is_queue_unmap) 3964 WDOORBELL64(aggregated_db_index, wptr_tmp); 3965 } 3966 } else { 3967 if (ring->use_doorbell) { 3968 /* XXX check if swapping is necessary on BE */ 3969 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 3970 ring->wptr); 3971 WDOORBELL64(ring->doorbell_index, ring->wptr); 3972 } else { 3973 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 3974 lower_32_bits(ring->wptr)); 3975 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 3976 upper_32_bits(ring->wptr)); 3977 } 3978 } 3979 } 3980 3981 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3982 { 3983 /* gfx12 hardware is 32bit rptr */ 3984 return *(uint32_t *)ring->rptr_cpu_addr; 3985 } 3986 3987 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3988 { 3989 u64 wptr; 3990 3991 /* XXX check if swapping is necessary on BE */ 3992 if (ring->use_doorbell) 3993 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3994 else 3995 BUG(); 3996 return wptr; 3997 } 3998 3999 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4000 { 4001 struct amdgpu_device *adev = ring->adev; 4002 uint32_t *wptr_saved; 4003 uint32_t *is_queue_unmap; 4004 uint64_t aggregated_db_index; 4005 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4006 uint64_t wptr_tmp; 4007 4008 if (ring->is_mes_queue) { 4009 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4010 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4011 sizeof(uint32_t)); 4012 aggregated_db_index = 4013 amdgpu_mes_get_aggregated_doorbell_index(adev, 4014 ring->hw_prio); 4015 4016 wptr_tmp = ring->wptr & ring->buf_mask; 4017 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4018 *wptr_saved = wptr_tmp; 4019 /* assume doorbell always used by mes mapped queue */ 4020 if (*is_queue_unmap) { 4021 WDOORBELL64(aggregated_db_index, wptr_tmp); 4022 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4023 } else { 4024 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4025 4026 if (*is_queue_unmap) 4027 WDOORBELL64(aggregated_db_index, wptr_tmp); 4028 } 4029 } else { 4030 /* XXX check if swapping is necessary on BE */ 4031 if (ring->use_doorbell) { 4032 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4033 ring->wptr); 4034 WDOORBELL64(ring->doorbell_index, ring->wptr); 4035 } else { 4036 BUG(); /* only DOORBELL method supported on gfx12 now */ 4037 } 4038 } 4039 } 4040 4041 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4042 { 4043 struct amdgpu_device *adev = ring->adev; 4044 u32 ref_and_mask, reg_mem_engine; 4045 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4046 4047 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4048 switch (ring->me) { 4049 case 1: 4050 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4051 break; 4052 case 2: 4053 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4054 break; 4055 default: 4056 return; 4057 } 4058 reg_mem_engine = 0; 4059 } else { 4060 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4061 reg_mem_engine = 1; /* pfp */ 4062 } 4063 4064 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4065 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4066 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4067 ref_and_mask, ref_and_mask, 0x20); 4068 } 4069 4070 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4071 struct amdgpu_job *job, 4072 struct amdgpu_ib *ib, 4073 uint32_t flags) 4074 { 4075 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4076 u32 header, control = 0; 4077 4078 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4079 4080 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4081 4082 control |= ib->length_dw | (vmid << 24); 4083 4084 if (ring->is_mes_queue) 4085 /* inherit vmid from mqd */ 4086 control |= 0x400000; 4087 4088 amdgpu_ring_write(ring, header); 4089 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4090 amdgpu_ring_write(ring, 4091 #ifdef __BIG_ENDIAN 4092 (2 << 0) | 4093 #endif 4094 lower_32_bits(ib->gpu_addr)); 4095 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4096 amdgpu_ring_write(ring, control); 4097 } 4098 4099 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4100 struct amdgpu_job *job, 4101 struct amdgpu_ib *ib, 4102 uint32_t flags) 4103 { 4104 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4105 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4106 4107 if (ring->is_mes_queue) 4108 /* inherit vmid from mqd */ 4109 control |= 0x40000000; 4110 4111 /* Currently, there is a high possibility to get wave ID mismatch 4112 * between ME and GDS, leading to a hw deadlock, because ME generates 4113 * different wave IDs than the GDS expects. This situation happens 4114 * randomly when at least 5 compute pipes use GDS ordered append. 4115 * The wave IDs generated by ME are also wrong after suspend/resume. 4116 * Those are probably bugs somewhere else in the kernel driver. 4117 * 4118 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4119 * GDS to 0 for this ring (me/pipe). 4120 */ 4121 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4122 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4123 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 4124 } 4125 4126 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4127 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4128 amdgpu_ring_write(ring, 4129 #ifdef __BIG_ENDIAN 4130 (2 << 0) | 4131 #endif 4132 lower_32_bits(ib->gpu_addr)); 4133 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4134 amdgpu_ring_write(ring, control); 4135 } 4136 4137 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4138 u64 seq, unsigned flags) 4139 { 4140 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4141 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4142 4143 /* RELEASE_MEM - flush caches, send int */ 4144 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4145 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4146 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4147 PACKET3_RELEASE_MEM_GCR_GL2_INV | 4148 PACKET3_RELEASE_MEM_GCR_GL2_US | 4149 PACKET3_RELEASE_MEM_GCR_GL1_INV | 4150 PACKET3_RELEASE_MEM_GCR_GLV_INV | 4151 PACKET3_RELEASE_MEM_GCR_GLM_INV | 4152 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4153 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4154 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4155 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4156 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4157 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4158 4159 /* 4160 * the address should be Qword aligned if 64bit write, Dword 4161 * aligned if only send 32bit data low (discard data high) 4162 */ 4163 if (write64bit) 4164 BUG_ON(addr & 0x7); 4165 else 4166 BUG_ON(addr & 0x3); 4167 amdgpu_ring_write(ring, lower_32_bits(addr)); 4168 amdgpu_ring_write(ring, upper_32_bits(addr)); 4169 amdgpu_ring_write(ring, lower_32_bits(seq)); 4170 amdgpu_ring_write(ring, upper_32_bits(seq)); 4171 amdgpu_ring_write(ring, ring->is_mes_queue ? 4172 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4173 } 4174 4175 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4176 { 4177 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4178 uint32_t seq = ring->fence_drv.sync_seq; 4179 uint64_t addr = ring->fence_drv.gpu_addr; 4180 4181 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4182 upper_32_bits(addr), seq, 0xffffffff, 4); 4183 } 4184 4185 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4186 uint16_t pasid, uint32_t flush_type, 4187 bool all_hub, uint8_t dst_sel) 4188 { 4189 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4190 amdgpu_ring_write(ring, 4191 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4192 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4193 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4194 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4195 } 4196 4197 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4198 unsigned vmid, uint64_t pd_addr) 4199 { 4200 if (ring->is_mes_queue) 4201 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4202 else 4203 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4204 4205 /* compute doesn't have PFP */ 4206 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4207 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4208 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4209 amdgpu_ring_write(ring, 0x0); 4210 } 4211 } 4212 4213 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4214 u64 seq, unsigned int flags) 4215 { 4216 struct amdgpu_device *adev = ring->adev; 4217 4218 /* we only allocate 32bit for each seq wb address */ 4219 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4220 4221 /* write fence seq to the "addr" */ 4222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4223 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4224 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4225 amdgpu_ring_write(ring, lower_32_bits(addr)); 4226 amdgpu_ring_write(ring, upper_32_bits(addr)); 4227 amdgpu_ring_write(ring, lower_32_bits(seq)); 4228 4229 if (flags & AMDGPU_FENCE_FLAG_INT) { 4230 /* set register to trigger INT */ 4231 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4232 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4233 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4234 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4235 amdgpu_ring_write(ring, 0); 4236 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4237 } 4238 } 4239 4240 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4241 uint32_t flags) 4242 { 4243 uint32_t dw2 = 0; 4244 4245 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4246 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4247 /* set load_global_config & load_global_uconfig */ 4248 dw2 |= 0x8001; 4249 /* set load_cs_sh_regs */ 4250 dw2 |= 0x01000000; 4251 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4252 dw2 |= 0x10002; 4253 } 4254 4255 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4256 amdgpu_ring_write(ring, dw2); 4257 amdgpu_ring_write(ring, 0); 4258 } 4259 4260 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4261 uint64_t addr) 4262 { 4263 unsigned ret; 4264 4265 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4266 amdgpu_ring_write(ring, lower_32_bits(addr)); 4267 amdgpu_ring_write(ring, upper_32_bits(addr)); 4268 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4269 amdgpu_ring_write(ring, 0); 4270 ret = ring->wptr & ring->buf_mask; 4271 /* patch dummy value later */ 4272 amdgpu_ring_write(ring, 0); 4273 4274 return ret; 4275 } 4276 4277 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4278 { 4279 int i, r = 0; 4280 struct amdgpu_device *adev = ring->adev; 4281 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4282 struct amdgpu_ring *kiq_ring = &kiq->ring; 4283 unsigned long flags; 4284 4285 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4286 return -EINVAL; 4287 4288 spin_lock_irqsave(&kiq->ring_lock, flags); 4289 4290 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4291 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4292 return -ENOMEM; 4293 } 4294 4295 /* assert preemption condition */ 4296 amdgpu_ring_set_preempt_cond_exec(ring, false); 4297 4298 /* assert IB preemption, emit the trailing fence */ 4299 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4300 ring->trail_fence_gpu_addr, 4301 ++ring->trail_seq); 4302 amdgpu_ring_commit(kiq_ring); 4303 4304 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4305 4306 /* poll the trailing fence */ 4307 for (i = 0; i < adev->usec_timeout; i++) { 4308 if (ring->trail_seq == 4309 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4310 break; 4311 udelay(1); 4312 } 4313 4314 if (i >= adev->usec_timeout) { 4315 r = -EINVAL; 4316 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4317 } 4318 4319 /* deassert preemption condition */ 4320 amdgpu_ring_set_preempt_cond_exec(ring, true); 4321 return r; 4322 } 4323 4324 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4325 bool start, 4326 bool secure) 4327 { 4328 uint32_t v = secure ? FRAME_TMZ : 0; 4329 4330 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4331 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4332 } 4333 4334 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4335 uint32_t reg_val_offs) 4336 { 4337 struct amdgpu_device *adev = ring->adev; 4338 4339 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4340 amdgpu_ring_write(ring, 0 | /* src: register*/ 4341 (5 << 8) | /* dst: memory */ 4342 (1 << 20)); /* write confirm */ 4343 amdgpu_ring_write(ring, reg); 4344 amdgpu_ring_write(ring, 0); 4345 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4346 reg_val_offs * 4)); 4347 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4348 reg_val_offs * 4)); 4349 } 4350 4351 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4352 uint32_t reg, 4353 uint32_t val) 4354 { 4355 uint32_t cmd = 0; 4356 4357 switch (ring->funcs->type) { 4358 case AMDGPU_RING_TYPE_GFX: 4359 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4360 break; 4361 case AMDGPU_RING_TYPE_KIQ: 4362 cmd = (1 << 16); /* no inc addr */ 4363 break; 4364 default: 4365 cmd = WR_CONFIRM; 4366 break; 4367 } 4368 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4369 amdgpu_ring_write(ring, cmd); 4370 amdgpu_ring_write(ring, reg); 4371 amdgpu_ring_write(ring, 0); 4372 amdgpu_ring_write(ring, val); 4373 } 4374 4375 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4376 uint32_t val, uint32_t mask) 4377 { 4378 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4379 } 4380 4381 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4382 uint32_t reg0, uint32_t reg1, 4383 uint32_t ref, uint32_t mask) 4384 { 4385 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4386 4387 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4388 ref, mask, 0x20); 4389 } 4390 4391 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4392 unsigned vmid) 4393 { 4394 struct amdgpu_device *adev = ring->adev; 4395 uint32_t value = 0; 4396 4397 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4398 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4399 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4400 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4401 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4402 } 4403 4404 static void 4405 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4406 uint32_t me, uint32_t pipe, 4407 enum amdgpu_interrupt_state state) 4408 { 4409 uint32_t cp_int_cntl, cp_int_cntl_reg; 4410 4411 if (!me) { 4412 switch (pipe) { 4413 case 0: 4414 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4415 break; 4416 default: 4417 DRM_DEBUG("invalid pipe %d\n", pipe); 4418 return; 4419 } 4420 } else { 4421 DRM_DEBUG("invalid me %d\n", me); 4422 return; 4423 } 4424 4425 switch (state) { 4426 case AMDGPU_IRQ_STATE_DISABLE: 4427 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4428 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4429 TIME_STAMP_INT_ENABLE, 0); 4430 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4431 GENERIC0_INT_ENABLE, 0); 4432 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4433 break; 4434 case AMDGPU_IRQ_STATE_ENABLE: 4435 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4436 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4437 TIME_STAMP_INT_ENABLE, 1); 4438 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4439 GENERIC0_INT_ENABLE, 1); 4440 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4441 break; 4442 default: 4443 break; 4444 } 4445 } 4446 4447 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4448 int me, int pipe, 4449 enum amdgpu_interrupt_state state) 4450 { 4451 u32 mec_int_cntl, mec_int_cntl_reg; 4452 4453 /* 4454 * amdgpu controls only the first MEC. That's why this function only 4455 * handles the setting of interrupts for this specific MEC. All other 4456 * pipes' interrupts are set by amdkfd. 4457 */ 4458 4459 if (me == 1) { 4460 switch (pipe) { 4461 case 0: 4462 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4463 break; 4464 case 1: 4465 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4466 break; 4467 default: 4468 DRM_DEBUG("invalid pipe %d\n", pipe); 4469 return; 4470 } 4471 } else { 4472 DRM_DEBUG("invalid me %d\n", me); 4473 return; 4474 } 4475 4476 switch (state) { 4477 case AMDGPU_IRQ_STATE_DISABLE: 4478 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4479 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4480 TIME_STAMP_INT_ENABLE, 0); 4481 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4482 GENERIC0_INT_ENABLE, 0); 4483 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4484 break; 4485 case AMDGPU_IRQ_STATE_ENABLE: 4486 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4487 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4488 TIME_STAMP_INT_ENABLE, 1); 4489 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4490 GENERIC0_INT_ENABLE, 1); 4491 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4492 break; 4493 default: 4494 break; 4495 } 4496 } 4497 4498 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4499 struct amdgpu_irq_src *src, 4500 unsigned type, 4501 enum amdgpu_interrupt_state state) 4502 { 4503 switch (type) { 4504 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4505 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4506 break; 4507 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4508 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4509 break; 4510 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4511 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4512 break; 4513 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4514 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4515 break; 4516 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4517 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4518 break; 4519 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4520 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4521 break; 4522 default: 4523 break; 4524 } 4525 return 0; 4526 } 4527 4528 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4529 struct amdgpu_irq_src *source, 4530 struct amdgpu_iv_entry *entry) 4531 { 4532 int i; 4533 u8 me_id, pipe_id, queue_id; 4534 struct amdgpu_ring *ring; 4535 uint32_t mes_queue_id = entry->src_data[0]; 4536 4537 DRM_DEBUG("IH: CP EOP\n"); 4538 4539 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4540 struct amdgpu_mes_queue *queue; 4541 4542 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4543 4544 spin_lock(&adev->mes.queue_id_lock); 4545 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4546 if (queue) { 4547 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4548 amdgpu_fence_process(queue->ring); 4549 } 4550 spin_unlock(&adev->mes.queue_id_lock); 4551 } else { 4552 me_id = (entry->ring_id & 0x0c) >> 2; 4553 pipe_id = (entry->ring_id & 0x03) >> 0; 4554 queue_id = (entry->ring_id & 0x70) >> 4; 4555 4556 switch (me_id) { 4557 case 0: 4558 if (pipe_id == 0) 4559 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4560 else 4561 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4562 break; 4563 case 1: 4564 case 2: 4565 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4566 ring = &adev->gfx.compute_ring[i]; 4567 /* Per-queue interrupt is supported for MEC starting from VI. 4568 * The interrupt can only be enabled/disabled per pipe instead 4569 * of per queue. 4570 */ 4571 if ((ring->me == me_id) && 4572 (ring->pipe == pipe_id) && 4573 (ring->queue == queue_id)) 4574 amdgpu_fence_process(ring); 4575 } 4576 break; 4577 } 4578 } 4579 4580 return 0; 4581 } 4582 4583 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4584 struct amdgpu_irq_src *source, 4585 unsigned type, 4586 enum amdgpu_interrupt_state state) 4587 { 4588 switch (state) { 4589 case AMDGPU_IRQ_STATE_DISABLE: 4590 case AMDGPU_IRQ_STATE_ENABLE: 4591 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 4592 PRIV_REG_INT_ENABLE, 4593 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4594 break; 4595 default: 4596 break; 4597 } 4598 4599 return 0; 4600 } 4601 4602 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4603 struct amdgpu_irq_src *source, 4604 unsigned type, 4605 enum amdgpu_interrupt_state state) 4606 { 4607 switch (state) { 4608 case AMDGPU_IRQ_STATE_DISABLE: 4609 case AMDGPU_IRQ_STATE_ENABLE: 4610 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 4611 PRIV_INSTR_INT_ENABLE, 4612 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4613 break; 4614 default: 4615 break; 4616 } 4617 4618 return 0; 4619 } 4620 4621 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4622 struct amdgpu_iv_entry *entry) 4623 { 4624 u8 me_id, pipe_id, queue_id; 4625 struct amdgpu_ring *ring; 4626 int i; 4627 4628 me_id = (entry->ring_id & 0x0c) >> 2; 4629 pipe_id = (entry->ring_id & 0x03) >> 0; 4630 queue_id = (entry->ring_id & 0x70) >> 4; 4631 4632 switch (me_id) { 4633 case 0: 4634 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4635 ring = &adev->gfx.gfx_ring[i]; 4636 /* we only enabled 1 gfx queue per pipe for now */ 4637 if (ring->me == me_id && ring->pipe == pipe_id) 4638 drm_sched_fault(&ring->sched); 4639 } 4640 break; 4641 case 1: 4642 case 2: 4643 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4644 ring = &adev->gfx.compute_ring[i]; 4645 if (ring->me == me_id && ring->pipe == pipe_id && 4646 ring->queue == queue_id) 4647 drm_sched_fault(&ring->sched); 4648 } 4649 break; 4650 default: 4651 BUG(); 4652 break; 4653 } 4654 } 4655 4656 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 4657 struct amdgpu_irq_src *source, 4658 struct amdgpu_iv_entry *entry) 4659 { 4660 DRM_ERROR("Illegal register access in command stream\n"); 4661 gfx_v12_0_handle_priv_fault(adev, entry); 4662 return 0; 4663 } 4664 4665 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 4666 struct amdgpu_irq_src *source, 4667 struct amdgpu_iv_entry *entry) 4668 { 4669 DRM_ERROR("Illegal instruction in command stream\n"); 4670 gfx_v12_0_handle_priv_fault(adev, entry); 4671 return 0; 4672 } 4673 4674 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 4675 { 4676 const unsigned int gcr_cntl = 4677 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 4678 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 4679 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 4680 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 4681 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 4682 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 4683 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 4684 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 4685 4686 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 4687 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 4688 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 4689 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4690 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 4691 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4692 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 4693 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 4694 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 4695 } 4696 4697 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 4698 .name = "gfx_v12_0", 4699 .early_init = gfx_v12_0_early_init, 4700 .late_init = gfx_v12_0_late_init, 4701 .sw_init = gfx_v12_0_sw_init, 4702 .sw_fini = gfx_v12_0_sw_fini, 4703 .hw_init = gfx_v12_0_hw_init, 4704 .hw_fini = gfx_v12_0_hw_fini, 4705 .suspend = gfx_v12_0_suspend, 4706 .resume = gfx_v12_0_resume, 4707 .is_idle = gfx_v12_0_is_idle, 4708 .wait_for_idle = gfx_v12_0_wait_for_idle, 4709 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 4710 .set_powergating_state = gfx_v12_0_set_powergating_state, 4711 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 4712 }; 4713 4714 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 4715 .type = AMDGPU_RING_TYPE_GFX, 4716 .align_mask = 0xff, 4717 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4718 .support_64bit_ptrs = true, 4719 .secure_submission_supported = true, 4720 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 4721 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 4722 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 4723 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4724 5 + /* COND_EXEC */ 4725 7 + /* PIPELINE_SYNC */ 4726 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4727 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4728 2 + /* VM_FLUSH */ 4729 8 + /* FENCE for VM_FLUSH */ 4730 20 + /* GDS switch */ 4731 5 + /* COND_EXEC */ 4732 7 + /* HDP_flush */ 4733 4 + /* VGT_flush */ 4734 31 + /* DE_META */ 4735 3 + /* CNTX_CTRL */ 4736 5 + /* HDP_INVL */ 4737 8 + 8 + /* FENCE x2 */ 4738 8, /* gfx_v12_0_emit_mem_sync */ 4739 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 4740 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 4741 .emit_fence = gfx_v12_0_ring_emit_fence, 4742 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 4743 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 4744 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 4745 .test_ring = gfx_v12_0_ring_test_ring, 4746 .test_ib = gfx_v12_0_ring_test_ib, 4747 .insert_nop = amdgpu_ring_insert_nop, 4748 .pad_ib = amdgpu_ring_generic_pad_ib, 4749 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 4750 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 4751 .preempt_ib = gfx_v12_0_ring_preempt_ib, 4752 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 4753 .emit_wreg = gfx_v12_0_ring_emit_wreg, 4754 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 4755 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 4756 .soft_recovery = gfx_v12_0_ring_soft_recovery, 4757 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 4758 }; 4759 4760 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 4761 .type = AMDGPU_RING_TYPE_COMPUTE, 4762 .align_mask = 0xff, 4763 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4764 .support_64bit_ptrs = true, 4765 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 4766 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 4767 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 4768 .emit_frame_size = 4769 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 4770 5 + /* hdp invalidate */ 4771 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 4772 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4773 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4774 2 + /* gfx_v12_0_ring_emit_vm_flush */ 4775 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 4776 8, /* gfx_v12_0_emit_mem_sync */ 4777 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 4778 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 4779 .emit_fence = gfx_v12_0_ring_emit_fence, 4780 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 4781 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 4782 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 4783 .test_ring = gfx_v12_0_ring_test_ring, 4784 .test_ib = gfx_v12_0_ring_test_ib, 4785 .insert_nop = amdgpu_ring_insert_nop, 4786 .pad_ib = amdgpu_ring_generic_pad_ib, 4787 .emit_wreg = gfx_v12_0_ring_emit_wreg, 4788 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 4789 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 4790 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 4791 }; 4792 4793 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 4794 .type = AMDGPU_RING_TYPE_KIQ, 4795 .align_mask = 0xff, 4796 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4797 .support_64bit_ptrs = true, 4798 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 4799 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 4800 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 4801 .emit_frame_size = 4802 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 4803 5 + /*hdp invalidate */ 4804 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 4805 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4806 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4807 2 + /* gfx_v12_0_ring_emit_vm_flush */ 4808 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4809 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 4810 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 4811 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 4812 .test_ring = gfx_v12_0_ring_test_ring, 4813 .test_ib = gfx_v12_0_ring_test_ib, 4814 .insert_nop = amdgpu_ring_insert_nop, 4815 .pad_ib = amdgpu_ring_generic_pad_ib, 4816 .emit_rreg = gfx_v12_0_ring_emit_rreg, 4817 .emit_wreg = gfx_v12_0_ring_emit_wreg, 4818 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 4819 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 4820 }; 4821 4822 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 4823 { 4824 int i; 4825 4826 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 4827 4828 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4829 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 4830 4831 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4832 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 4833 } 4834 4835 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 4836 .set = gfx_v12_0_set_eop_interrupt_state, 4837 .process = gfx_v12_0_eop_irq, 4838 }; 4839 4840 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 4841 .set = gfx_v12_0_set_priv_reg_fault_state, 4842 .process = gfx_v12_0_priv_reg_irq, 4843 }; 4844 4845 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 4846 .set = gfx_v12_0_set_priv_inst_fault_state, 4847 .process = gfx_v12_0_priv_inst_irq, 4848 }; 4849 4850 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 4851 { 4852 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4853 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 4854 4855 adev->gfx.priv_reg_irq.num_types = 1; 4856 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 4857 4858 adev->gfx.priv_inst_irq.num_types = 1; 4859 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 4860 } 4861 4862 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 4863 { 4864 if (adev->flags & AMD_IS_APU) 4865 adev->gfx.imu.mode = MISSION_MODE; 4866 else 4867 adev->gfx.imu.mode = DEBUG_MODE; 4868 4869 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 4870 } 4871 4872 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 4873 { 4874 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 4875 } 4876 4877 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 4878 { 4879 /* set gfx eng mqd */ 4880 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 4881 sizeof(struct v12_gfx_mqd); 4882 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 4883 gfx_v12_0_gfx_mqd_init; 4884 /* set compute eng mqd */ 4885 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 4886 sizeof(struct v12_compute_mqd); 4887 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 4888 gfx_v12_0_compute_mqd_init; 4889 } 4890 4891 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 4892 u32 bitmap) 4893 { 4894 u32 data; 4895 4896 if (!bitmap) 4897 return; 4898 4899 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4900 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4901 4902 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 4903 } 4904 4905 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 4906 { 4907 u32 data, wgp_bitmask; 4908 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 4909 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 4910 4911 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 4912 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 4913 4914 wgp_bitmask = 4915 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 4916 4917 return (~data) & wgp_bitmask; 4918 } 4919 4920 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 4921 { 4922 u32 wgp_idx, wgp_active_bitmap; 4923 u32 cu_bitmap_per_wgp, cu_active_bitmap; 4924 4925 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 4926 cu_active_bitmap = 0; 4927 4928 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 4929 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 4930 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 4931 if (wgp_active_bitmap & (1 << wgp_idx)) 4932 cu_active_bitmap |= cu_bitmap_per_wgp; 4933 } 4934 4935 return cu_active_bitmap; 4936 } 4937 4938 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 4939 struct amdgpu_cu_info *cu_info) 4940 { 4941 int i, j, k, counter, active_cu_number = 0; 4942 u32 mask, bitmap; 4943 unsigned disable_masks[8 * 2]; 4944 4945 if (!adev || !cu_info) 4946 return -EINVAL; 4947 4948 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 4949 4950 mutex_lock(&adev->grbm_idx_mutex); 4951 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4952 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4953 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4954 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 4955 continue; 4956 mask = 1; 4957 counter = 0; 4958 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4959 if (i < 8 && j < 2) 4960 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 4961 adev, disable_masks[i * 2 + j]); 4962 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 4963 4964 /** 4965 * GFX12 could support more than 4 SEs, while the bitmap 4966 * in cu_info struct is 4x4 and ioctl interface struct 4967 * drm_amdgpu_info_device should keep stable. 4968 * So we use last two columns of bitmap to store cu mask for 4969 * SEs 4 to 7, the layout of the bitmap is as below: 4970 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 4971 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 4972 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 4973 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 4974 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 4975 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 4976 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 4977 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 4978 */ 4979 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 4980 4981 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4982 if (bitmap & mask) 4983 counter++; 4984 4985 mask <<= 1; 4986 } 4987 active_cu_number += counter; 4988 } 4989 } 4990 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4991 mutex_unlock(&adev->grbm_idx_mutex); 4992 4993 cu_info->number = active_cu_number; 4994 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4995 4996 return 0; 4997 } 4998 4999 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5000 .type = AMD_IP_BLOCK_TYPE_GFX, 5001 .major = 12, 5002 .minor = 0, 5003 .rev = 0, 5004 .funcs = &gfx_v12_0_ip_funcs, 5005 }; 5006