1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v12_0.h" 34 #include "soc24.h" 35 #include "nvd.h" 36 37 #include "gc/gc_12_0_0_offset.h" 38 #include "gc/gc_12_0_0_sh_mask.h" 39 #include "soc24_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 41 42 #include "soc15.h" 43 #include "clearstate_gfx12.h" 44 #include "v12_structs.h" 45 #include "gfx_v12_0.h" 46 #include "nbif_v6_3_1.h" 47 #include "mes_v12_0.h" 48 49 #define GFX12_NUM_GFX_RINGS 1 50 #define GFX12_MEC_HPD_SIZE 2048 51 52 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 53 54 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 64 65 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 66 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 69 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 96 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 97 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 101 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 102 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 104 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 105 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 106 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 107 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 108 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 119 120 /* cp header registers */ 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 125 /* SE status registers */ 126 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 128 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 130 }; 131 132 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 133 /* compute registers */ 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 173 }; 174 175 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 176 /* gfx queue registers */ 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 202 }; 203 204 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 205 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 208 }; 209 210 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 211 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 212 }; 213 214 #define DEFAULT_SH_MEM_CONFIG \ 215 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 216 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 217 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 218 219 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 220 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 221 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 222 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 223 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 224 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 225 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 226 struct amdgpu_cu_info *cu_info); 227 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 228 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 229 u32 sh_num, u32 instance, int xcc_id); 230 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 231 232 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 233 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 234 uint32_t val); 235 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 236 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 237 uint16_t pasid, uint32_t flush_type, 238 bool all_hub, uint8_t dst_sel); 239 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 240 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 241 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 242 bool enable); 243 244 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 245 uint64_t queue_mask) 246 { 247 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 248 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 249 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 250 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 251 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 252 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 253 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 254 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 255 amdgpu_ring_write(kiq_ring, 0); 256 } 257 258 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 259 struct amdgpu_ring *ring) 260 { 261 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 262 uint64_t wptr_addr = ring->wptr_gpu_addr; 263 uint32_t me = 0, eng_sel = 0; 264 265 switch (ring->funcs->type) { 266 case AMDGPU_RING_TYPE_COMPUTE: 267 me = 1; 268 eng_sel = 0; 269 break; 270 case AMDGPU_RING_TYPE_GFX: 271 me = 0; 272 eng_sel = 4; 273 break; 274 case AMDGPU_RING_TYPE_MES: 275 me = 2; 276 eng_sel = 5; 277 break; 278 default: 279 WARN_ON(1); 280 } 281 282 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 283 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 284 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 285 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 286 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 287 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 288 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 289 PACKET3_MAP_QUEUES_ME((me)) | 290 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 291 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 292 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 293 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 294 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 295 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 296 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 297 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 298 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 299 } 300 301 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 302 struct amdgpu_ring *ring, 303 enum amdgpu_unmap_queues_action action, 304 u64 gpu_addr, u64 seq) 305 { 306 struct amdgpu_device *adev = kiq_ring->adev; 307 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 308 309 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 310 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 311 return; 312 } 313 314 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 315 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 316 PACKET3_UNMAP_QUEUES_ACTION(action) | 317 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 318 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 319 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 320 amdgpu_ring_write(kiq_ring, 321 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 322 323 if (action == PREEMPT_QUEUES_NO_UNMAP) { 324 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 325 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 326 amdgpu_ring_write(kiq_ring, seq); 327 } else { 328 amdgpu_ring_write(kiq_ring, 0); 329 amdgpu_ring_write(kiq_ring, 0); 330 amdgpu_ring_write(kiq_ring, 0); 331 } 332 } 333 334 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 335 struct amdgpu_ring *ring, 336 u64 addr, u64 seq) 337 { 338 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 339 340 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 341 amdgpu_ring_write(kiq_ring, 342 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 343 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 344 PACKET3_QUERY_STATUS_COMMAND(2)); 345 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 346 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 347 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 348 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 349 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 350 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 351 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 352 } 353 354 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 355 uint16_t pasid, 356 uint32_t flush_type, 357 bool all_hub) 358 { 359 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 360 } 361 362 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 363 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 364 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 365 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 366 .kiq_query_status = gfx_v12_0_kiq_query_status, 367 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 368 .set_resources_size = 8, 369 .map_queues_size = 7, 370 .unmap_queues_size = 6, 371 .query_status_size = 7, 372 .invalidate_tlbs_size = 2, 373 }; 374 375 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 376 { 377 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 378 } 379 380 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 381 int mem_space, int opt, uint32_t addr0, 382 uint32_t addr1, uint32_t ref, 383 uint32_t mask, uint32_t inv) 384 { 385 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 386 amdgpu_ring_write(ring, 387 /* memory (1) or register (0) */ 388 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 389 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 390 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 391 WAIT_REG_MEM_ENGINE(eng_sel))); 392 393 if (mem_space) 394 BUG_ON(addr0 & 0x3); /* Dword align */ 395 amdgpu_ring_write(ring, addr0); 396 amdgpu_ring_write(ring, addr1); 397 amdgpu_ring_write(ring, ref); 398 amdgpu_ring_write(ring, mask); 399 amdgpu_ring_write(ring, inv); /* poll interval */ 400 } 401 402 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 403 { 404 struct amdgpu_device *adev = ring->adev; 405 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 406 uint32_t tmp = 0; 407 unsigned i; 408 int r; 409 410 WREG32(scratch, 0xCAFEDEAD); 411 r = amdgpu_ring_alloc(ring, 5); 412 if (r) { 413 dev_err(adev->dev, 414 "amdgpu: cp failed to lock ring %d (%d).\n", 415 ring->idx, r); 416 return r; 417 } 418 419 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 420 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 421 } else { 422 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 423 amdgpu_ring_write(ring, scratch - 424 PACKET3_SET_UCONFIG_REG_START); 425 amdgpu_ring_write(ring, 0xDEADBEEF); 426 } 427 amdgpu_ring_commit(ring); 428 429 for (i = 0; i < adev->usec_timeout; i++) { 430 tmp = RREG32(scratch); 431 if (tmp == 0xDEADBEEF) 432 break; 433 if (amdgpu_emu_mode == 1) 434 msleep(1); 435 else 436 udelay(1); 437 } 438 439 if (i >= adev->usec_timeout) 440 r = -ETIMEDOUT; 441 return r; 442 } 443 444 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 445 { 446 struct amdgpu_device *adev = ring->adev; 447 struct amdgpu_ib ib; 448 struct dma_fence *f = NULL; 449 unsigned index; 450 uint64_t gpu_addr; 451 volatile uint32_t *cpu_ptr; 452 long r; 453 454 /* MES KIQ fw hasn't indirect buffer support for now */ 455 if (adev->enable_mes_kiq && 456 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 457 return 0; 458 459 memset(&ib, 0, sizeof(ib)); 460 461 if (ring->is_mes_queue) { 462 uint32_t padding, offset; 463 464 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 465 padding = amdgpu_mes_ctx_get_offs(ring, 466 AMDGPU_MES_CTX_PADDING_OFFS); 467 468 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 469 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 470 471 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 472 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 473 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 474 } else { 475 r = amdgpu_device_wb_get(adev, &index); 476 if (r) 477 return r; 478 479 gpu_addr = adev->wb.gpu_addr + (index * 4); 480 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 481 cpu_ptr = &adev->wb.wb[index]; 482 483 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 484 if (r) { 485 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 486 goto err1; 487 } 488 } 489 490 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 491 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 492 ib.ptr[2] = lower_32_bits(gpu_addr); 493 ib.ptr[3] = upper_32_bits(gpu_addr); 494 ib.ptr[4] = 0xDEADBEEF; 495 ib.length_dw = 5; 496 497 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 498 if (r) 499 goto err2; 500 501 r = dma_fence_wait_timeout(f, false, timeout); 502 if (r == 0) { 503 r = -ETIMEDOUT; 504 goto err2; 505 } else if (r < 0) { 506 goto err2; 507 } 508 509 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 510 r = 0; 511 else 512 r = -EINVAL; 513 err2: 514 if (!ring->is_mes_queue) 515 amdgpu_ib_free(&ib, NULL); 516 dma_fence_put(f); 517 err1: 518 if (!ring->is_mes_queue) 519 amdgpu_device_wb_free(adev, index); 520 return r; 521 } 522 523 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 524 { 525 amdgpu_ucode_release(&adev->gfx.pfp_fw); 526 amdgpu_ucode_release(&adev->gfx.me_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 530 kfree(adev->gfx.rlc.register_list_format); 531 } 532 533 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 534 { 535 const struct psp_firmware_header_v1_0 *toc_hdr; 536 int err = 0; 537 538 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 539 AMDGPU_UCODE_REQUIRED, 540 "amdgpu/%s_toc.bin", ucode_prefix); 541 if (err) 542 goto out; 543 544 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 545 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 546 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 547 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 548 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 549 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 550 return 0; 551 out: 552 amdgpu_ucode_release(&adev->psp.toc_fw); 553 return err; 554 } 555 556 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 557 { 558 char ucode_prefix[15]; 559 int err; 560 const struct rlc_firmware_header_v2_0 *rlc_hdr; 561 uint16_t version_major; 562 uint16_t version_minor; 563 564 DRM_DEBUG("\n"); 565 566 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 567 568 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 569 AMDGPU_UCODE_REQUIRED, 570 "amdgpu/%s_pfp.bin", ucode_prefix); 571 if (err) 572 goto out; 573 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 574 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 575 576 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 577 AMDGPU_UCODE_REQUIRED, 578 "amdgpu/%s_me.bin", ucode_prefix); 579 if (err) 580 goto out; 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 583 584 if (!amdgpu_sriov_vf(adev)) { 585 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 586 AMDGPU_UCODE_REQUIRED, 587 "amdgpu/%s_rlc.bin", ucode_prefix); 588 if (err) 589 goto out; 590 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 591 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 592 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 593 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 594 if (err) 595 goto out; 596 } 597 598 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 599 AMDGPU_UCODE_REQUIRED, 600 "amdgpu/%s_mec.bin", ucode_prefix); 601 if (err) 602 goto out; 603 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 606 607 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 608 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 609 610 /* only one MEC for gfx 12 */ 611 adev->gfx.mec2_fw = NULL; 612 613 if (adev->gfx.imu.funcs) { 614 if (adev->gfx.imu.funcs->init_microcode) { 615 err = adev->gfx.imu.funcs->init_microcode(adev); 616 if (err) 617 dev_err(adev->dev, "Failed to load imu firmware!\n"); 618 } 619 } 620 621 out: 622 if (err) { 623 amdgpu_ucode_release(&adev->gfx.pfp_fw); 624 amdgpu_ucode_release(&adev->gfx.me_fw); 625 amdgpu_ucode_release(&adev->gfx.rlc_fw); 626 amdgpu_ucode_release(&adev->gfx.mec_fw); 627 } 628 629 return err; 630 } 631 632 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 633 { 634 u32 count = 0; 635 const struct cs_section_def *sect = NULL; 636 const struct cs_extent_def *ext = NULL; 637 638 count += 1; 639 640 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 641 if (sect->id == SECT_CONTEXT) { 642 for (ext = sect->section; ext->extent != NULL; ++ext) 643 count += 2 + ext->reg_count; 644 } else 645 return 0; 646 } 647 648 return count; 649 } 650 651 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 652 volatile u32 *buffer) 653 { 654 u32 count = 0, clustercount = 0, i; 655 const struct cs_section_def *sect = NULL; 656 const struct cs_extent_def *ext = NULL; 657 658 if (adev->gfx.rlc.cs_data == NULL) 659 return; 660 if (buffer == NULL) 661 return; 662 663 count += 1; 664 665 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 666 if (sect->id == SECT_CONTEXT) { 667 for (ext = sect->section; ext->extent != NULL; ++ext) { 668 clustercount++; 669 buffer[count++] = ext->reg_count; 670 buffer[count++] = ext->reg_index; 671 672 for (i = 0; i < ext->reg_count; i++) 673 buffer[count++] = cpu_to_le32(ext->extent[i]); 674 } 675 } else 676 return; 677 } 678 679 buffer[0] = clustercount; 680 } 681 682 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 683 { 684 /* clear state block */ 685 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 686 &adev->gfx.rlc.clear_state_gpu_addr, 687 (void **)&adev->gfx.rlc.cs_ptr); 688 689 /* jump table block */ 690 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 691 &adev->gfx.rlc.cp_table_gpu_addr, 692 (void **)&adev->gfx.rlc.cp_table_ptr); 693 } 694 695 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 696 { 697 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 698 699 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 700 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 701 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 702 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 703 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 704 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 705 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 706 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 707 adev->gfx.rlc.rlcg_reg_access_supported = true; 708 } 709 710 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 711 { 712 const struct cs_section_def *cs_data; 713 int r; 714 715 adev->gfx.rlc.cs_data = gfx12_cs_data; 716 717 cs_data = adev->gfx.rlc.cs_data; 718 719 if (cs_data) { 720 /* init clear state block */ 721 r = amdgpu_gfx_rlc_init_csb(adev); 722 if (r) 723 return r; 724 } 725 726 /* init spm vmid with 0xf */ 727 if (adev->gfx.rlc.funcs->update_spm_vmid) 728 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 729 730 return 0; 731 } 732 733 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 734 { 735 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 736 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 737 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 738 } 739 740 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 741 { 742 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 743 744 amdgpu_gfx_graphics_queue_acquire(adev); 745 } 746 747 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 748 { 749 int r; 750 u32 *hpd; 751 size_t mec_hpd_size; 752 753 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 754 755 /* take ownership of the relevant compute queues */ 756 amdgpu_gfx_compute_queue_acquire(adev); 757 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 758 759 if (mec_hpd_size) { 760 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 761 AMDGPU_GEM_DOMAIN_GTT, 762 &adev->gfx.mec.hpd_eop_obj, 763 &adev->gfx.mec.hpd_eop_gpu_addr, 764 (void **)&hpd); 765 if (r) { 766 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 767 gfx_v12_0_mec_fini(adev); 768 return r; 769 } 770 771 memset(hpd, 0, mec_hpd_size); 772 773 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 774 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 775 } 776 777 return 0; 778 } 779 780 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 781 { 782 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 783 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 784 (address << SQ_IND_INDEX__INDEX__SHIFT)); 785 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 786 } 787 788 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 789 uint32_t thread, uint32_t regno, 790 uint32_t num, uint32_t *out) 791 { 792 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 793 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 794 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 795 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 796 (SQ_IND_INDEX__AUTO_INCR_MASK)); 797 while (num--) 798 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 799 } 800 801 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 802 uint32_t xcc_id, 803 uint32_t simd, uint32_t wave, 804 uint32_t *dst, int *no_fields) 805 { 806 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 807 * field when performing a select_se_sh so it should be 808 * zero here */ 809 WARN_ON(simd != 0); 810 811 /* type 4 wave data */ 812 dst[(*no_fields)++] = 4; 813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 836 } 837 838 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 839 uint32_t xcc_id, uint32_t simd, 840 uint32_t wave, uint32_t start, 841 uint32_t size, uint32_t *dst) 842 { 843 WARN_ON(simd != 0); 844 845 wave_read_regs( 846 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 847 dst); 848 } 849 850 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 851 uint32_t xcc_id, uint32_t simd, 852 uint32_t wave, uint32_t thread, 853 uint32_t start, uint32_t size, 854 uint32_t *dst) 855 { 856 wave_read_regs( 857 adev, wave, thread, 858 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 859 } 860 861 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 862 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 863 { 864 soc24_grbm_select(adev, me, pipe, q, vm); 865 } 866 867 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 868 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 869 .select_se_sh = &gfx_v12_0_select_se_sh, 870 .read_wave_data = &gfx_v12_0_read_wave_data, 871 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 872 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 873 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 874 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 875 }; 876 877 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 878 { 879 880 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 881 case IP_VERSION(12, 0, 0): 882 case IP_VERSION(12, 0, 1): 883 adev->gfx.config.max_hw_contexts = 8; 884 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 885 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 886 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 887 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 888 break; 889 default: 890 BUG(); 891 break; 892 } 893 894 return 0; 895 } 896 897 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 898 int me, int pipe, int queue) 899 { 900 int r; 901 struct amdgpu_ring *ring; 902 unsigned int irq_type; 903 904 ring = &adev->gfx.gfx_ring[ring_id]; 905 906 ring->me = me; 907 ring->pipe = pipe; 908 ring->queue = queue; 909 910 ring->ring_obj = NULL; 911 ring->use_doorbell = true; 912 913 if (!ring_id) 914 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 915 else 916 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 917 ring->vm_hub = AMDGPU_GFXHUB(0); 918 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 919 920 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 921 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 922 AMDGPU_RING_PRIO_DEFAULT, NULL); 923 if (r) 924 return r; 925 return 0; 926 } 927 928 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 929 int mec, int pipe, int queue) 930 { 931 int r; 932 unsigned irq_type; 933 struct amdgpu_ring *ring; 934 unsigned int hw_prio; 935 936 ring = &adev->gfx.compute_ring[ring_id]; 937 938 /* mec0 is me1 */ 939 ring->me = mec + 1; 940 ring->pipe = pipe; 941 ring->queue = queue; 942 943 ring->ring_obj = NULL; 944 ring->use_doorbell = true; 945 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 946 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 947 + (ring_id * GFX12_MEC_HPD_SIZE); 948 ring->vm_hub = AMDGPU_GFXHUB(0); 949 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 950 951 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 952 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 953 + ring->pipe; 954 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 955 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 956 /* type-2 packets are deprecated on MEC, use type-3 instead */ 957 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 958 hw_prio, NULL); 959 if (r) 960 return r; 961 962 return 0; 963 } 964 965 static struct { 966 SOC24_FIRMWARE_ID id; 967 unsigned int offset; 968 unsigned int size; 969 unsigned int size_x16; 970 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 971 972 #define RLC_TOC_OFFSET_DWUNIT 8 973 #define RLC_SIZE_MULTIPLE 1024 974 #define RLC_TOC_UMF_SIZE_inM 23ULL 975 #define RLC_TOC_FORMAT_API 165ULL 976 977 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 978 { 979 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 980 981 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 982 rlc_autoload_info[ucode->id].id = ucode->id; 983 rlc_autoload_info[ucode->id].offset = 984 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 985 rlc_autoload_info[ucode->id].size = 986 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 987 ucode->size * 4; 988 ucode++; 989 } 990 } 991 992 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 993 { 994 uint32_t total_size = 0; 995 SOC24_FIRMWARE_ID id; 996 997 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 998 999 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1000 total_size += rlc_autoload_info[id].size; 1001 1002 /* In case the offset in rlc toc ucode is aligned */ 1003 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1004 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1005 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1006 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1007 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1008 1009 return total_size; 1010 } 1011 1012 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1013 { 1014 int r; 1015 uint32_t total_size; 1016 1017 total_size = gfx_v12_0_calc_toc_total_size(adev); 1018 1019 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1020 AMDGPU_GEM_DOMAIN_VRAM, 1021 &adev->gfx.rlc.rlc_autoload_bo, 1022 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1023 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1024 1025 if (r) { 1026 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1027 return r; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1034 SOC24_FIRMWARE_ID id, 1035 const void *fw_data, 1036 uint32_t fw_size) 1037 { 1038 uint32_t toc_offset; 1039 uint32_t toc_fw_size; 1040 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1041 1042 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1043 return; 1044 1045 toc_offset = rlc_autoload_info[id].offset; 1046 toc_fw_size = rlc_autoload_info[id].size; 1047 1048 if (fw_size == 0) 1049 fw_size = toc_fw_size; 1050 1051 if (fw_size > toc_fw_size) 1052 fw_size = toc_fw_size; 1053 1054 memcpy(ptr + toc_offset, fw_data, fw_size); 1055 1056 if (fw_size < toc_fw_size) 1057 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1058 } 1059 1060 static void 1061 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1062 { 1063 void *data; 1064 uint32_t size; 1065 uint32_t *toc_ptr; 1066 1067 data = adev->psp.toc.start_addr; 1068 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1069 1070 toc_ptr = (uint32_t *)data + size / 4 - 2; 1071 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1072 1073 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1074 data, size); 1075 } 1076 1077 static void 1078 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1079 { 1080 const __le32 *fw_data; 1081 uint32_t fw_size; 1082 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1083 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1084 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1085 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1086 uint16_t version_major, version_minor; 1087 1088 /* pfp ucode */ 1089 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1090 adev->gfx.pfp_fw->data; 1091 /* instruction */ 1092 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1093 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1094 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1095 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1096 fw_data, fw_size); 1097 /* data */ 1098 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1099 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1100 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1101 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1102 fw_data, fw_size); 1103 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1104 fw_data, fw_size); 1105 /* me ucode */ 1106 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1107 adev->gfx.me_fw->data; 1108 /* instruction */ 1109 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1110 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1111 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1112 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1113 fw_data, fw_size); 1114 /* data */ 1115 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1116 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1117 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1118 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1119 fw_data, fw_size); 1120 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1121 fw_data, fw_size); 1122 /* mec ucode */ 1123 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1124 adev->gfx.mec_fw->data; 1125 /* instruction */ 1126 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1127 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1128 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1129 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1130 fw_data, fw_size); 1131 /* data */ 1132 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1133 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1134 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1135 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1136 fw_data, fw_size); 1137 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1138 fw_data, fw_size); 1139 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1140 fw_data, fw_size); 1141 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1142 fw_data, fw_size); 1143 1144 /* rlc ucode */ 1145 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1146 adev->gfx.rlc_fw->data; 1147 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1148 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1149 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1150 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1151 fw_data, fw_size); 1152 1153 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1154 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1155 if (version_major == 2) { 1156 if (version_minor >= 1) { 1157 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1158 1159 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1160 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1161 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1162 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1163 fw_data, fw_size); 1164 1165 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1166 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1167 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1168 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1169 fw_data, fw_size); 1170 } 1171 if (version_minor >= 2) { 1172 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1173 1174 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1175 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1176 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1177 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1178 fw_data, fw_size); 1179 1180 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1181 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1182 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1183 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1184 fw_data, fw_size); 1185 } 1186 } 1187 } 1188 1189 static void 1190 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1191 { 1192 const __le32 *fw_data; 1193 uint32_t fw_size; 1194 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1195 1196 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1197 adev->sdma.instance[0].fw->data; 1198 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1199 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1200 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1201 1202 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1203 fw_data, fw_size); 1204 } 1205 1206 static void 1207 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1208 { 1209 const __le32 *fw_data; 1210 unsigned fw_size; 1211 const struct mes_firmware_header_v1_0 *mes_hdr; 1212 int pipe, ucode_id, data_id; 1213 1214 for (pipe = 0; pipe < 2; pipe++) { 1215 if (pipe == 0) { 1216 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1217 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1218 } else { 1219 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1220 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1221 } 1222 1223 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1224 adev->mes.fw[pipe]->data; 1225 1226 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1227 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1228 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1229 1230 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1231 1232 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1233 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1234 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1235 1236 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1237 } 1238 } 1239 1240 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1241 { 1242 uint32_t rlc_g_offset, rlc_g_size; 1243 uint64_t gpu_addr; 1244 uint32_t data; 1245 1246 /* RLC autoload sequence 2: copy ucode */ 1247 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1248 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1249 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1250 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1251 1252 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1253 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1254 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1255 1256 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1257 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1258 1259 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1260 1261 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1262 /* RLC autoload sequence 3: load IMU fw */ 1263 if (adev->gfx.imu.funcs->load_microcode) 1264 adev->gfx.imu.funcs->load_microcode(adev); 1265 /* RLC autoload sequence 4 init IMU fw */ 1266 if (adev->gfx.imu.funcs->setup_imu) 1267 adev->gfx.imu.funcs->setup_imu(adev); 1268 if (adev->gfx.imu.funcs->start_imu) 1269 adev->gfx.imu.funcs->start_imu(adev); 1270 1271 /* RLC autoload sequence 5 disable gpa mode */ 1272 gfx_v12_0_disable_gpa_mode(adev); 1273 } else { 1274 /* unhalt rlc to start autoload without imu */ 1275 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1276 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1277 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1278 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1279 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1280 } 1281 1282 return 0; 1283 } 1284 1285 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1286 { 1287 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1288 uint32_t *ptr; 1289 uint32_t inst; 1290 1291 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1292 if (!ptr) { 1293 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1294 adev->gfx.ip_dump_core = NULL; 1295 } else { 1296 adev->gfx.ip_dump_core = ptr; 1297 } 1298 1299 /* Allocate memory for compute queue registers for all the instances */ 1300 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1301 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1302 adev->gfx.mec.num_queue_per_pipe; 1303 1304 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1305 if (!ptr) { 1306 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1307 adev->gfx.ip_dump_compute_queues = NULL; 1308 } else { 1309 adev->gfx.ip_dump_compute_queues = ptr; 1310 } 1311 1312 /* Allocate memory for gfx queue registers for all the instances */ 1313 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1314 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1315 adev->gfx.me.num_queue_per_pipe; 1316 1317 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1318 if (!ptr) { 1319 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1320 adev->gfx.ip_dump_gfx_queues = NULL; 1321 } else { 1322 adev->gfx.ip_dump_gfx_queues = ptr; 1323 } 1324 } 1325 1326 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1327 { 1328 int i, j, k, r, ring_id = 0; 1329 unsigned num_compute_rings; 1330 int xcc_id = 0; 1331 struct amdgpu_device *adev = ip_block->adev; 1332 1333 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1334 1335 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1336 case IP_VERSION(12, 0, 0): 1337 case IP_VERSION(12, 0, 1): 1338 adev->gfx.me.num_me = 1; 1339 adev->gfx.me.num_pipe_per_me = 1; 1340 adev->gfx.me.num_queue_per_pipe = 1; 1341 adev->gfx.mec.num_mec = 2; 1342 adev->gfx.mec.num_pipe_per_mec = 2; 1343 adev->gfx.mec.num_queue_per_pipe = 4; 1344 break; 1345 default: 1346 adev->gfx.me.num_me = 1; 1347 adev->gfx.me.num_pipe_per_me = 1; 1348 adev->gfx.me.num_queue_per_pipe = 1; 1349 adev->gfx.mec.num_mec = 1; 1350 adev->gfx.mec.num_pipe_per_mec = 4; 1351 adev->gfx.mec.num_queue_per_pipe = 8; 1352 break; 1353 } 1354 1355 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1356 case IP_VERSION(12, 0, 0): 1357 case IP_VERSION(12, 0, 1): 1358 if (adev->gfx.me_fw_version >= 2480 && 1359 adev->gfx.pfp_fw_version >= 2530 && 1360 adev->gfx.mec_fw_version >= 2680 && 1361 adev->mes.fw_version[0] >= 100) 1362 adev->gfx.enable_cleaner_shader = true; 1363 break; 1364 default: 1365 adev->gfx.enable_cleaner_shader = false; 1366 break; 1367 } 1368 1369 /* recalculate compute rings to use based on hardware configuration */ 1370 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1371 adev->gfx.mec.num_queue_per_pipe) / 2; 1372 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1373 num_compute_rings); 1374 1375 /* EOP Event */ 1376 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1377 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1378 &adev->gfx.eop_irq); 1379 if (r) 1380 return r; 1381 1382 /* Bad opcode Event */ 1383 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1384 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1385 &adev->gfx.bad_op_irq); 1386 if (r) 1387 return r; 1388 1389 /* Privileged reg */ 1390 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1391 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1392 &adev->gfx.priv_reg_irq); 1393 if (r) 1394 return r; 1395 1396 /* Privileged inst */ 1397 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1398 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1399 &adev->gfx.priv_inst_irq); 1400 if (r) 1401 return r; 1402 1403 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1404 1405 gfx_v12_0_me_init(adev); 1406 1407 r = gfx_v12_0_rlc_init(adev); 1408 if (r) { 1409 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1410 return r; 1411 } 1412 1413 r = gfx_v12_0_mec_init(adev); 1414 if (r) { 1415 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1416 return r; 1417 } 1418 1419 /* set up the gfx ring */ 1420 for (i = 0; i < adev->gfx.me.num_me; i++) { 1421 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1422 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1423 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1424 continue; 1425 1426 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1427 i, k, j); 1428 if (r) 1429 return r; 1430 ring_id++; 1431 } 1432 } 1433 } 1434 1435 ring_id = 0; 1436 /* set up the compute queues - allocate horizontally across pipes */ 1437 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1438 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1439 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1440 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1441 0, i, k, j)) 1442 continue; 1443 1444 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1445 i, k, j); 1446 if (r) 1447 return r; 1448 1449 ring_id++; 1450 } 1451 } 1452 } 1453 1454 adev->gfx.gfx_supported_reset = 1455 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1456 adev->gfx.compute_supported_reset = 1457 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1458 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1459 case IP_VERSION(12, 0, 0): 1460 case IP_VERSION(12, 0, 1): 1461 if ((adev->gfx.me_fw_version >= 2660) && 1462 (adev->gfx.mec_fw_version >= 2920)) { 1463 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1464 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1465 } 1466 } 1467 1468 if (!adev->enable_mes_kiq) { 1469 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1470 if (r) { 1471 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1472 return r; 1473 } 1474 1475 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1476 if (r) 1477 return r; 1478 } 1479 1480 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1481 if (r) 1482 return r; 1483 1484 /* allocate visible FB for rlc auto-loading fw */ 1485 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1486 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1487 if (r) 1488 return r; 1489 } 1490 1491 r = gfx_v12_0_gpu_early_init(adev); 1492 if (r) 1493 return r; 1494 1495 gfx_v12_0_alloc_ip_dump(adev); 1496 1497 r = amdgpu_gfx_sysfs_init(adev); 1498 if (r) 1499 return r; 1500 1501 return 0; 1502 } 1503 1504 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1505 { 1506 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1507 &adev->gfx.pfp.pfp_fw_gpu_addr, 1508 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1509 1510 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1511 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1512 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1513 } 1514 1515 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1516 { 1517 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1518 &adev->gfx.me.me_fw_gpu_addr, 1519 (void **)&adev->gfx.me.me_fw_ptr); 1520 1521 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1522 &adev->gfx.me.me_fw_data_gpu_addr, 1523 (void **)&adev->gfx.me.me_fw_data_ptr); 1524 } 1525 1526 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1527 { 1528 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1529 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1530 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1531 } 1532 1533 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1534 { 1535 int i; 1536 struct amdgpu_device *adev = ip_block->adev; 1537 1538 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1539 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1540 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1541 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1542 1543 amdgpu_gfx_mqd_sw_fini(adev, 0); 1544 1545 if (!adev->enable_mes_kiq) { 1546 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1547 amdgpu_gfx_kiq_fini(adev, 0); 1548 } 1549 1550 gfx_v12_0_pfp_fini(adev); 1551 gfx_v12_0_me_fini(adev); 1552 gfx_v12_0_rlc_fini(adev); 1553 gfx_v12_0_mec_fini(adev); 1554 1555 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1556 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1557 1558 gfx_v12_0_free_microcode(adev); 1559 1560 amdgpu_gfx_sysfs_fini(adev); 1561 1562 kfree(adev->gfx.ip_dump_core); 1563 kfree(adev->gfx.ip_dump_compute_queues); 1564 kfree(adev->gfx.ip_dump_gfx_queues); 1565 1566 return 0; 1567 } 1568 1569 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1570 u32 sh_num, u32 instance, int xcc_id) 1571 { 1572 u32 data; 1573 1574 if (instance == 0xffffffff) 1575 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1576 INSTANCE_BROADCAST_WRITES, 1); 1577 else 1578 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1579 instance); 1580 1581 if (se_num == 0xffffffff) 1582 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1583 1); 1584 else 1585 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1586 1587 if (sh_num == 0xffffffff) 1588 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1589 1); 1590 else 1591 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1592 1593 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1594 } 1595 1596 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1597 { 1598 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1599 1600 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1601 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1602 GRBM_CC_GC_SA_UNIT_DISABLE, 1603 SA_DISABLE); 1604 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1605 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1606 GRBM_GC_USER_SA_UNIT_DISABLE, 1607 SA_DISABLE); 1608 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1609 adev->gfx.config.max_shader_engines); 1610 1611 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1612 } 1613 1614 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1615 { 1616 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1617 u32 rb_mask; 1618 1619 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1620 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1621 CC_RB_BACKEND_DISABLE, 1622 BACKEND_DISABLE); 1623 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1624 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1625 GC_USER_RB_BACKEND_DISABLE, 1626 BACKEND_DISABLE); 1627 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1628 adev->gfx.config.max_shader_engines); 1629 1630 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1631 } 1632 1633 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1634 { 1635 u32 rb_bitmap_per_sa; 1636 u32 rb_bitmap_width_per_sa; 1637 u32 max_sa; 1638 u32 active_sa_bitmap; 1639 u32 global_active_rb_bitmap; 1640 u32 active_rb_bitmap = 0; 1641 u32 i; 1642 1643 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1644 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1645 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1646 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1647 1648 /* generate active rb bitmap according to active sa bitmap */ 1649 max_sa = adev->gfx.config.max_shader_engines * 1650 adev->gfx.config.max_sh_per_se; 1651 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1652 adev->gfx.config.max_sh_per_se; 1653 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1654 1655 for (i = 0; i < max_sa; i++) { 1656 if (active_sa_bitmap & (1 << i)) 1657 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1658 } 1659 1660 active_rb_bitmap &= global_active_rb_bitmap; 1661 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1662 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1663 } 1664 1665 #define LDS_APP_BASE 0x1 1666 #define SCRATCH_APP_BASE 0x2 1667 1668 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1669 { 1670 int i; 1671 uint32_t sh_mem_bases; 1672 uint32_t data; 1673 1674 /* 1675 * Configure apertures: 1676 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1677 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1678 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1679 */ 1680 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1681 SCRATCH_APP_BASE; 1682 1683 mutex_lock(&adev->srbm_mutex); 1684 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1685 soc24_grbm_select(adev, 0, 0, 0, i); 1686 /* CP and shaders */ 1687 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1688 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1689 1690 /* Enable trap for each kfd vmid. */ 1691 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1692 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1693 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1694 } 1695 soc24_grbm_select(adev, 0, 0, 0, 0); 1696 mutex_unlock(&adev->srbm_mutex); 1697 } 1698 1699 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1700 { 1701 /* TODO: harvest feature to be added later. */ 1702 } 1703 1704 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1705 { 1706 } 1707 1708 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1709 { 1710 u32 tmp; 1711 int i; 1712 1713 if (!amdgpu_sriov_vf(adev)) 1714 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1715 1716 gfx_v12_0_setup_rb(adev); 1717 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1718 gfx_v12_0_get_tcc_info(adev); 1719 adev->gfx.config.pa_sc_tile_steering_override = 0; 1720 1721 /* XXX SH_MEM regs */ 1722 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1723 mutex_lock(&adev->srbm_mutex); 1724 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1725 soc24_grbm_select(adev, 0, 0, 0, i); 1726 /* CP and shaders */ 1727 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1728 if (i != 0) { 1729 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1730 (adev->gmc.private_aperture_start >> 48)); 1731 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1732 (adev->gmc.shared_aperture_start >> 48)); 1733 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1734 } 1735 } 1736 soc24_grbm_select(adev, 0, 0, 0, 0); 1737 1738 mutex_unlock(&adev->srbm_mutex); 1739 1740 gfx_v12_0_init_compute_vmid(adev); 1741 } 1742 1743 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1744 int me, int pipe) 1745 { 1746 if (me != 0) 1747 return 0; 1748 1749 switch (pipe) { 1750 case 0: 1751 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1752 default: 1753 return 0; 1754 } 1755 } 1756 1757 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1758 int me, int pipe) 1759 { 1760 /* 1761 * amdgpu controls only the first MEC. That's why this function only 1762 * handles the setting of interrupts for this specific MEC. All other 1763 * pipes' interrupts are set by amdkfd. 1764 */ 1765 if (me != 1) 1766 return 0; 1767 1768 switch (pipe) { 1769 case 0: 1770 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1771 case 1: 1772 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1773 default: 1774 return 0; 1775 } 1776 } 1777 1778 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1779 bool enable) 1780 { 1781 u32 tmp, cp_int_cntl_reg; 1782 int i, j; 1783 1784 if (amdgpu_sriov_vf(adev)) 1785 return; 1786 1787 for (i = 0; i < adev->gfx.me.num_me; i++) { 1788 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1789 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1790 1791 if (cp_int_cntl_reg) { 1792 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1793 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1794 enable ? 1 : 0); 1795 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1796 enable ? 1 : 0); 1797 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1798 enable ? 1 : 0); 1799 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1800 enable ? 1 : 0); 1801 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1802 } 1803 } 1804 } 1805 } 1806 1807 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1808 { 1809 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1810 1811 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1812 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1813 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1814 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1815 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1816 1817 return 0; 1818 } 1819 1820 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1821 { 1822 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1823 1824 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1825 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1826 } 1827 1828 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1829 { 1830 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1831 udelay(50); 1832 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1833 udelay(50); 1834 } 1835 1836 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1837 bool enable) 1838 { 1839 uint32_t rlc_pg_cntl; 1840 1841 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1842 1843 if (!enable) { 1844 /* RLC_PG_CNTL[23] = 0 (default) 1845 * RLC will wait for handshake acks with SMU 1846 * GFXOFF will be enabled 1847 * RLC_PG_CNTL[23] = 1 1848 * RLC will not issue any message to SMU 1849 * hence no handshake between SMU & RLC 1850 * GFXOFF will be disabled 1851 */ 1852 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1853 } else 1854 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1855 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1856 } 1857 1858 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1859 { 1860 /* TODO: enable rlc & smu handshake until smu 1861 * and gfxoff feature works as expected */ 1862 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1863 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1864 1865 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1866 udelay(50); 1867 } 1868 1869 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1870 { 1871 uint32_t tmp; 1872 1873 /* enable Save Restore Machine */ 1874 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1875 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1876 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1877 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1878 } 1879 1880 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1881 { 1882 const struct rlc_firmware_header_v2_0 *hdr; 1883 const __le32 *fw_data; 1884 unsigned i, fw_size; 1885 1886 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1887 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1888 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1889 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1890 1891 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1892 RLCG_UCODE_LOADING_START_ADDRESS); 1893 1894 for (i = 0; i < fw_size; i++) 1895 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1896 le32_to_cpup(fw_data++)); 1897 1898 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1899 } 1900 1901 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1902 { 1903 const struct rlc_firmware_header_v2_2 *hdr; 1904 const __le32 *fw_data; 1905 unsigned i, fw_size; 1906 u32 tmp; 1907 1908 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1909 1910 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1911 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1912 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1913 1914 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1915 1916 for (i = 0; i < fw_size; i++) { 1917 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1918 msleep(1); 1919 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1920 le32_to_cpup(fw_data++)); 1921 } 1922 1923 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1924 1925 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1926 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1927 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1928 1929 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1930 for (i = 0; i < fw_size; i++) { 1931 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1932 msleep(1); 1933 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1934 le32_to_cpup(fw_data++)); 1935 } 1936 1937 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1938 1939 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1940 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1941 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1942 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1943 } 1944 1945 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 1946 { 1947 const struct rlc_firmware_header_v2_0 *hdr; 1948 uint16_t version_major; 1949 uint16_t version_minor; 1950 1951 if (!adev->gfx.rlc_fw) 1952 return -EINVAL; 1953 1954 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1955 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1956 1957 version_major = le16_to_cpu(hdr->header.header_version_major); 1958 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1959 1960 if (version_major == 2) { 1961 gfx_v12_0_load_rlcg_microcode(adev); 1962 if (amdgpu_dpm == 1) { 1963 if (version_minor >= 2) 1964 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 1965 } 1966 1967 return 0; 1968 } 1969 1970 return -EINVAL; 1971 } 1972 1973 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 1974 { 1975 int r; 1976 1977 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1978 gfx_v12_0_init_csb(adev); 1979 1980 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1981 gfx_v12_0_rlc_enable_srm(adev); 1982 } else { 1983 if (amdgpu_sriov_vf(adev)) { 1984 gfx_v12_0_init_csb(adev); 1985 return 0; 1986 } 1987 1988 adev->gfx.rlc.funcs->stop(adev); 1989 1990 /* disable CG */ 1991 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1992 1993 /* disable PG */ 1994 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1995 1996 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1997 /* legacy rlc firmware loading */ 1998 r = gfx_v12_0_rlc_load_microcode(adev); 1999 if (r) 2000 return r; 2001 } 2002 2003 gfx_v12_0_init_csb(adev); 2004 2005 adev->gfx.rlc.funcs->start(adev); 2006 } 2007 2008 return 0; 2009 } 2010 2011 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2012 { 2013 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2014 const struct gfx_firmware_header_v2_0 *me_hdr; 2015 const struct gfx_firmware_header_v2_0 *mec_hdr; 2016 uint32_t pipe_id, tmp; 2017 2018 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2019 adev->gfx.mec_fw->data; 2020 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2021 adev->gfx.me_fw->data; 2022 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2023 adev->gfx.pfp_fw->data; 2024 2025 /* config pfp program start addr */ 2026 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2027 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2028 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2029 (pfp_hdr->ucode_start_addr_hi << 30) | 2030 (pfp_hdr->ucode_start_addr_lo >> 2)); 2031 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2032 pfp_hdr->ucode_start_addr_hi >> 2); 2033 } 2034 soc24_grbm_select(adev, 0, 0, 0, 0); 2035 2036 /* reset pfp pipe */ 2037 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2038 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2039 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2040 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2041 2042 /* clear pfp pipe reset */ 2043 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2044 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2045 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2046 2047 /* config me program start addr */ 2048 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2049 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2050 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2051 (me_hdr->ucode_start_addr_hi << 30) | 2052 (me_hdr->ucode_start_addr_lo >> 2)); 2053 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2054 me_hdr->ucode_start_addr_hi>>2); 2055 } 2056 soc24_grbm_select(adev, 0, 0, 0, 0); 2057 2058 /* reset me pipe */ 2059 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2060 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2061 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2062 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2063 2064 /* clear me pipe reset */ 2065 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2066 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2067 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2068 2069 /* config mec program start addr */ 2070 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2071 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2072 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2073 mec_hdr->ucode_start_addr_lo >> 2 | 2074 mec_hdr->ucode_start_addr_hi << 30); 2075 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2076 mec_hdr->ucode_start_addr_hi >> 2); 2077 } 2078 soc24_grbm_select(adev, 0, 0, 0, 0); 2079 2080 /* reset mec pipe */ 2081 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2082 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2083 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2084 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2085 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2086 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2087 2088 /* clear mec pipe reset */ 2089 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2090 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2091 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2092 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2093 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2094 } 2095 2096 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2097 { 2098 const struct gfx_firmware_header_v2_0 *cp_hdr; 2099 unsigned pipe_id, tmp; 2100 2101 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2102 adev->gfx.pfp_fw->data; 2103 mutex_lock(&adev->srbm_mutex); 2104 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2105 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2106 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2107 (cp_hdr->ucode_start_addr_hi << 30) | 2108 (cp_hdr->ucode_start_addr_lo >> 2)); 2109 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2110 cp_hdr->ucode_start_addr_hi>>2); 2111 2112 /* 2113 * Program CP_ME_CNTL to reset given PIPE to take 2114 * effect of CP_PFP_PRGRM_CNTR_START. 2115 */ 2116 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2117 if (pipe_id == 0) 2118 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2119 PFP_PIPE0_RESET, 1); 2120 else 2121 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2122 PFP_PIPE1_RESET, 1); 2123 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2124 2125 /* Clear pfp pipe0 reset bit. */ 2126 if (pipe_id == 0) 2127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2128 PFP_PIPE0_RESET, 0); 2129 else 2130 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2131 PFP_PIPE1_RESET, 0); 2132 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2133 } 2134 soc24_grbm_select(adev, 0, 0, 0, 0); 2135 mutex_unlock(&adev->srbm_mutex); 2136 } 2137 2138 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2139 { 2140 const struct gfx_firmware_header_v2_0 *cp_hdr; 2141 unsigned pipe_id, tmp; 2142 2143 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2144 adev->gfx.me_fw->data; 2145 mutex_lock(&adev->srbm_mutex); 2146 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2147 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2148 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2149 (cp_hdr->ucode_start_addr_hi << 30) | 2150 (cp_hdr->ucode_start_addr_lo >> 2) ); 2151 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2152 cp_hdr->ucode_start_addr_hi>>2); 2153 2154 /* 2155 * Program CP_ME_CNTL to reset given PIPE to take 2156 * effect of CP_ME_PRGRM_CNTR_START. 2157 */ 2158 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2159 if (pipe_id == 0) 2160 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2161 ME_PIPE0_RESET, 1); 2162 else 2163 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2164 ME_PIPE1_RESET, 1); 2165 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2166 2167 /* Clear pfp pipe0 reset bit. */ 2168 if (pipe_id == 0) 2169 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2170 ME_PIPE0_RESET, 0); 2171 else 2172 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2173 ME_PIPE1_RESET, 0); 2174 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2175 } 2176 soc24_grbm_select(adev, 0, 0, 0, 0); 2177 mutex_unlock(&adev->srbm_mutex); 2178 } 2179 2180 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2181 { 2182 const struct gfx_firmware_header_v2_0 *cp_hdr; 2183 unsigned pipe_id; 2184 2185 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2186 adev->gfx.mec_fw->data; 2187 mutex_lock(&adev->srbm_mutex); 2188 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2189 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2190 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2191 cp_hdr->ucode_start_addr_lo >> 2 | 2192 cp_hdr->ucode_start_addr_hi << 30); 2193 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2194 cp_hdr->ucode_start_addr_hi >> 2); 2195 } 2196 soc24_grbm_select(adev, 0, 0, 0, 0); 2197 mutex_unlock(&adev->srbm_mutex); 2198 } 2199 2200 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2201 { 2202 uint32_t cp_status; 2203 uint32_t bootload_status; 2204 int i; 2205 2206 for (i = 0; i < adev->usec_timeout; i++) { 2207 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2208 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2209 2210 if ((cp_status == 0) && 2211 (REG_GET_FIELD(bootload_status, 2212 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2213 break; 2214 } 2215 udelay(1); 2216 if (amdgpu_emu_mode) 2217 msleep(10); 2218 } 2219 2220 if (i >= adev->usec_timeout) { 2221 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2222 return -ETIMEDOUT; 2223 } 2224 2225 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2226 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2227 gfx_v12_0_set_me_ucode_start_addr(adev); 2228 gfx_v12_0_set_mec_ucode_start_addr(adev); 2229 } 2230 2231 return 0; 2232 } 2233 2234 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2235 { 2236 int i; 2237 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2238 2239 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2240 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2241 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2242 2243 for (i = 0; i < adev->usec_timeout; i++) { 2244 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2245 break; 2246 udelay(1); 2247 } 2248 2249 if (i >= adev->usec_timeout) 2250 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2251 2252 return 0; 2253 } 2254 2255 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2256 { 2257 int r; 2258 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2259 const __le32 *fw_ucode, *fw_data; 2260 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2261 uint32_t tmp; 2262 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2263 2264 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2265 adev->gfx.pfp_fw->data; 2266 2267 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2268 2269 /* instruction */ 2270 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2271 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2272 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2273 /* data */ 2274 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2275 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2276 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2277 2278 /* 64kb align */ 2279 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2280 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2281 &adev->gfx.pfp.pfp_fw_obj, 2282 &adev->gfx.pfp.pfp_fw_gpu_addr, 2283 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2284 if (r) { 2285 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2286 gfx_v12_0_pfp_fini(adev); 2287 return r; 2288 } 2289 2290 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2291 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2292 &adev->gfx.pfp.pfp_fw_data_obj, 2293 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2294 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2295 if (r) { 2296 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2297 gfx_v12_0_pfp_fini(adev); 2298 return r; 2299 } 2300 2301 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2302 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2303 2304 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2305 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2306 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2307 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2308 2309 if (amdgpu_emu_mode == 1) 2310 adev->hdp.funcs->flush_hdp(adev, NULL); 2311 2312 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2313 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2314 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2315 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2316 2317 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2318 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2319 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2320 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2321 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2322 2323 /* 2324 * Programming any of the CP_PFP_IC_BASE registers 2325 * forces invalidation of the ME L1 I$. Wait for the 2326 * invalidation complete 2327 */ 2328 for (i = 0; i < usec_timeout; i++) { 2329 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2330 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2331 INVALIDATE_CACHE_COMPLETE)) 2332 break; 2333 udelay(1); 2334 } 2335 2336 if (i >= usec_timeout) { 2337 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2338 return -EINVAL; 2339 } 2340 2341 /* Prime the L1 instruction caches */ 2342 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2343 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2344 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2345 /* Waiting for cache primed*/ 2346 for (i = 0; i < usec_timeout; i++) { 2347 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2348 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2349 ICACHE_PRIMED)) 2350 break; 2351 udelay(1); 2352 } 2353 2354 if (i >= usec_timeout) { 2355 dev_err(adev->dev, "failed to prime instruction cache\n"); 2356 return -EINVAL; 2357 } 2358 2359 mutex_lock(&adev->srbm_mutex); 2360 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2361 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2362 2363 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2364 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2365 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2366 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2367 } 2368 soc24_grbm_select(adev, 0, 0, 0, 0); 2369 mutex_unlock(&adev->srbm_mutex); 2370 2371 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2372 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2373 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2374 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2375 2376 /* Invalidate the data caches */ 2377 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2378 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2379 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2380 2381 for (i = 0; i < usec_timeout; i++) { 2382 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2383 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2384 INVALIDATE_DCACHE_COMPLETE)) 2385 break; 2386 udelay(1); 2387 } 2388 2389 if (i >= usec_timeout) { 2390 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2391 return -EINVAL; 2392 } 2393 2394 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2395 2396 return 0; 2397 } 2398 2399 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2400 { 2401 int r; 2402 const struct gfx_firmware_header_v2_0 *me_hdr; 2403 const __le32 *fw_ucode, *fw_data; 2404 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2405 uint32_t tmp; 2406 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2407 2408 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2409 adev->gfx.me_fw->data; 2410 2411 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2412 2413 /* instruction */ 2414 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2415 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2416 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2417 /* data */ 2418 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2419 le32_to_cpu(me_hdr->data_offset_bytes)); 2420 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2421 2422 /* 64kb align*/ 2423 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2424 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2425 &adev->gfx.me.me_fw_obj, 2426 &adev->gfx.me.me_fw_gpu_addr, 2427 (void **)&adev->gfx.me.me_fw_ptr); 2428 if (r) { 2429 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2430 gfx_v12_0_me_fini(adev); 2431 return r; 2432 } 2433 2434 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2435 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2436 &adev->gfx.me.me_fw_data_obj, 2437 &adev->gfx.me.me_fw_data_gpu_addr, 2438 (void **)&adev->gfx.me.me_fw_data_ptr); 2439 if (r) { 2440 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2441 gfx_v12_0_pfp_fini(adev); 2442 return r; 2443 } 2444 2445 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2446 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2447 2448 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2449 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2450 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2451 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2452 2453 if (amdgpu_emu_mode == 1) 2454 adev->hdp.funcs->flush_hdp(adev, NULL); 2455 2456 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2457 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2458 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2459 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2460 2461 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2462 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2463 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2464 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2465 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2466 2467 /* 2468 * Programming any of the CP_ME_IC_BASE registers 2469 * forces invalidation of the ME L1 I$. Wait for the 2470 * invalidation complete 2471 */ 2472 for (i = 0; i < usec_timeout; i++) { 2473 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2474 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2475 INVALIDATE_CACHE_COMPLETE)) 2476 break; 2477 udelay(1); 2478 } 2479 2480 if (i >= usec_timeout) { 2481 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2482 return -EINVAL; 2483 } 2484 2485 /* Prime the instruction caches */ 2486 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2487 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2488 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2489 2490 /* Waiting for instruction cache primed*/ 2491 for (i = 0; i < usec_timeout; i++) { 2492 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2493 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2494 ICACHE_PRIMED)) 2495 break; 2496 udelay(1); 2497 } 2498 2499 if (i >= usec_timeout) { 2500 dev_err(adev->dev, "failed to prime instruction cache\n"); 2501 return -EINVAL; 2502 } 2503 2504 mutex_lock(&adev->srbm_mutex); 2505 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2506 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2507 2508 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2509 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2510 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2511 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2512 } 2513 soc24_grbm_select(adev, 0, 0, 0, 0); 2514 mutex_unlock(&adev->srbm_mutex); 2515 2516 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2517 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2518 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2519 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2520 2521 /* Invalidate the data caches */ 2522 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2523 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2524 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2525 2526 for (i = 0; i < usec_timeout; i++) { 2527 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2528 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2529 INVALIDATE_DCACHE_COMPLETE)) 2530 break; 2531 udelay(1); 2532 } 2533 2534 if (i >= usec_timeout) { 2535 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2536 return -EINVAL; 2537 } 2538 2539 gfx_v12_0_set_me_ucode_start_addr(adev); 2540 2541 return 0; 2542 } 2543 2544 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2545 { 2546 int r; 2547 2548 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2549 return -EINVAL; 2550 2551 gfx_v12_0_cp_gfx_enable(adev, false); 2552 2553 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2554 if (r) { 2555 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2556 return r; 2557 } 2558 2559 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2560 if (r) { 2561 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2562 return r; 2563 } 2564 2565 return 0; 2566 } 2567 2568 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2569 { 2570 /* init the CP */ 2571 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2572 adev->gfx.config.max_hw_contexts - 1); 2573 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2574 2575 if (!amdgpu_async_gfx_ring) 2576 gfx_v12_0_cp_gfx_enable(adev, true); 2577 2578 return 0; 2579 } 2580 2581 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2582 CP_PIPE_ID pipe) 2583 { 2584 u32 tmp; 2585 2586 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2587 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2588 2589 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2590 } 2591 2592 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2593 struct amdgpu_ring *ring) 2594 { 2595 u32 tmp; 2596 2597 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2598 if (ring->use_doorbell) { 2599 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2600 DOORBELL_OFFSET, ring->doorbell_index); 2601 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2602 DOORBELL_EN, 1); 2603 } else { 2604 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2605 DOORBELL_EN, 0); 2606 } 2607 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2608 2609 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2610 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2611 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2612 2613 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2614 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2615 } 2616 2617 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2618 { 2619 struct amdgpu_ring *ring; 2620 u32 tmp; 2621 u32 rb_bufsz; 2622 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2623 u32 i; 2624 2625 /* Set the write pointer delay */ 2626 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2627 2628 /* set the RB to use vmid 0 */ 2629 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2630 2631 /* Init gfx ring 0 for pipe 0 */ 2632 mutex_lock(&adev->srbm_mutex); 2633 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2634 2635 /* Set ring buffer size */ 2636 ring = &adev->gfx.gfx_ring[0]; 2637 rb_bufsz = order_base_2(ring->ring_size / 8); 2638 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2639 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2640 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2641 2642 /* Initialize the ring buffer's write pointers */ 2643 ring->wptr = 0; 2644 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2645 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2646 2647 /* set the wb address whether it's enabled or not */ 2648 rptr_addr = ring->rptr_gpu_addr; 2649 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2650 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2651 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2652 2653 wptr_gpu_addr = ring->wptr_gpu_addr; 2654 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2655 lower_32_bits(wptr_gpu_addr)); 2656 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2657 upper_32_bits(wptr_gpu_addr)); 2658 2659 mdelay(1); 2660 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2661 2662 rb_addr = ring->gpu_addr >> 8; 2663 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2664 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2665 2666 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2667 2668 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2669 mutex_unlock(&adev->srbm_mutex); 2670 2671 /* Switch to pipe 0 */ 2672 mutex_lock(&adev->srbm_mutex); 2673 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2674 mutex_unlock(&adev->srbm_mutex); 2675 2676 /* start the ring */ 2677 gfx_v12_0_cp_gfx_start(adev); 2678 2679 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2680 ring = &adev->gfx.gfx_ring[i]; 2681 ring->sched.ready = true; 2682 } 2683 2684 return 0; 2685 } 2686 2687 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2688 { 2689 u32 data; 2690 2691 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2692 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2693 enable ? 0 : 1); 2694 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2695 enable ? 0 : 1); 2696 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2697 enable ? 0 : 1); 2698 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2699 enable ? 0 : 1); 2700 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2701 enable ? 0 : 1); 2702 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2703 enable ? 1 : 0); 2704 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2705 enable ? 1 : 0); 2706 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2707 enable ? 1 : 0); 2708 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2709 enable ? 1 : 0); 2710 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2711 enable ? 0 : 1); 2712 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2713 2714 adev->gfx.kiq[0].ring.sched.ready = enable; 2715 2716 udelay(50); 2717 } 2718 2719 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2720 { 2721 const struct gfx_firmware_header_v2_0 *mec_hdr; 2722 const __le32 *fw_ucode, *fw_data; 2723 u32 tmp, fw_ucode_size, fw_data_size; 2724 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2725 u32 *fw_ucode_ptr, *fw_data_ptr; 2726 int r; 2727 2728 if (!adev->gfx.mec_fw) 2729 return -EINVAL; 2730 2731 gfx_v12_0_cp_compute_enable(adev, false); 2732 2733 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2734 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2735 2736 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2737 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2738 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2739 2740 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2741 le32_to_cpu(mec_hdr->data_offset_bytes)); 2742 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2743 2744 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2745 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2746 &adev->gfx.mec.mec_fw_obj, 2747 &adev->gfx.mec.mec_fw_gpu_addr, 2748 (void **)&fw_ucode_ptr); 2749 if (r) { 2750 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2751 gfx_v12_0_mec_fini(adev); 2752 return r; 2753 } 2754 2755 r = amdgpu_bo_create_reserved(adev, 2756 ALIGN(fw_data_size, 64 * 1024) * 2757 adev->gfx.mec.num_pipe_per_mec, 2758 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2759 &adev->gfx.mec.mec_fw_data_obj, 2760 &adev->gfx.mec.mec_fw_data_gpu_addr, 2761 (void **)&fw_data_ptr); 2762 if (r) { 2763 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2764 gfx_v12_0_mec_fini(adev); 2765 return r; 2766 } 2767 2768 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2769 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2770 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2771 } 2772 2773 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2774 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2775 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2776 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2777 2778 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2779 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2780 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2781 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2782 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2783 2784 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2785 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2786 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2787 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2788 2789 mutex_lock(&adev->srbm_mutex); 2790 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2791 soc24_grbm_select(adev, 1, i, 0, 0); 2792 2793 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2794 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2795 i * ALIGN(fw_data_size, 64 * 1024))); 2796 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2797 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2798 i * ALIGN(fw_data_size, 64 * 1024))); 2799 2800 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2801 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2802 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2803 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2804 } 2805 mutex_unlock(&adev->srbm_mutex); 2806 soc24_grbm_select(adev, 0, 0, 0, 0); 2807 2808 /* Trigger an invalidation of the L1 instruction caches */ 2809 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2810 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2811 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2812 2813 /* Wait for invalidation complete */ 2814 for (i = 0; i < usec_timeout; i++) { 2815 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2816 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2817 INVALIDATE_DCACHE_COMPLETE)) 2818 break; 2819 udelay(1); 2820 } 2821 2822 if (i >= usec_timeout) { 2823 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2824 return -EINVAL; 2825 } 2826 2827 /* Trigger an invalidation of the L1 instruction caches */ 2828 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2829 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2830 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2831 2832 /* Wait for invalidation complete */ 2833 for (i = 0; i < usec_timeout; i++) { 2834 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2835 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2836 INVALIDATE_CACHE_COMPLETE)) 2837 break; 2838 udelay(1); 2839 } 2840 2841 if (i >= usec_timeout) { 2842 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2843 return -EINVAL; 2844 } 2845 2846 gfx_v12_0_set_mec_ucode_start_addr(adev); 2847 2848 return 0; 2849 } 2850 2851 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2852 { 2853 uint32_t tmp; 2854 struct amdgpu_device *adev = ring->adev; 2855 2856 /* tell RLC which is KIQ queue */ 2857 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2858 tmp &= 0xffffff00; 2859 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2860 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2861 } 2862 2863 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2864 { 2865 /* set graphics engine doorbell range */ 2866 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2867 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2868 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2869 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2870 2871 /* set compute engine doorbell range */ 2872 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2873 (adev->doorbell_index.kiq * 2) << 2); 2874 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2875 (adev->doorbell_index.userqueue_end * 2) << 2); 2876 } 2877 2878 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2879 struct amdgpu_mqd_prop *prop) 2880 { 2881 struct v12_gfx_mqd *mqd = m; 2882 uint64_t hqd_gpu_addr, wb_gpu_addr; 2883 uint32_t tmp; 2884 uint32_t rb_bufsz; 2885 2886 /* set up gfx hqd wptr */ 2887 mqd->cp_gfx_hqd_wptr = 0; 2888 mqd->cp_gfx_hqd_wptr_hi = 0; 2889 2890 /* set the pointer to the MQD */ 2891 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2892 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2893 2894 /* set up mqd control */ 2895 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 2896 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2897 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2898 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2899 mqd->cp_gfx_mqd_control = tmp; 2900 2901 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2902 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 2903 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2904 mqd->cp_gfx_hqd_vmid = 0; 2905 2906 /* set up default queue priority level 2907 * 0x0 = low priority, 0x1 = high priority */ 2908 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 2909 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2910 mqd->cp_gfx_hqd_queue_priority = tmp; 2911 2912 /* set up time quantum */ 2913 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 2914 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2915 mqd->cp_gfx_hqd_quantum = tmp; 2916 2917 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2918 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2919 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2920 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2921 2922 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2923 wb_gpu_addr = prop->rptr_gpu_addr; 2924 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2925 mqd->cp_gfx_hqd_rptr_addr_hi = 2926 upper_32_bits(wb_gpu_addr) & 0xffff; 2927 2928 /* set up rb_wptr_poll addr */ 2929 wb_gpu_addr = prop->wptr_gpu_addr; 2930 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2931 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2932 2933 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2934 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 2935 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 2936 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2937 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2938 #ifdef __BIG_ENDIAN 2939 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2940 #endif 2941 mqd->cp_gfx_hqd_cntl = tmp; 2942 2943 /* set up cp_doorbell_control */ 2944 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2945 if (prop->use_doorbell) { 2946 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2947 DOORBELL_OFFSET, prop->doorbell_index); 2948 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2949 DOORBELL_EN, 1); 2950 } else 2951 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2952 DOORBELL_EN, 0); 2953 mqd->cp_rb_doorbell_control = tmp; 2954 2955 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2956 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 2957 2958 /* active the queue */ 2959 mqd->cp_gfx_hqd_active = 1; 2960 2961 return 0; 2962 } 2963 2964 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 2965 { 2966 struct amdgpu_device *adev = ring->adev; 2967 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 2968 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 2969 2970 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2971 memset((void *)mqd, 0, sizeof(*mqd)); 2972 mutex_lock(&adev->srbm_mutex); 2973 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2974 amdgpu_ring_init_mqd(ring); 2975 soc24_grbm_select(adev, 0, 0, 0, 0); 2976 mutex_unlock(&adev->srbm_mutex); 2977 if (adev->gfx.me.mqd_backup[mqd_idx]) 2978 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2979 } else { 2980 /* restore mqd with the backup copy */ 2981 if (adev->gfx.me.mqd_backup[mqd_idx]) 2982 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 2983 /* reset the ring */ 2984 ring->wptr = 0; 2985 *ring->wptr_cpu_addr = 0; 2986 amdgpu_ring_clear_ring(ring); 2987 } 2988 2989 return 0; 2990 } 2991 2992 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 2993 { 2994 int r, i; 2995 struct amdgpu_ring *ring; 2996 2997 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2998 ring = &adev->gfx.gfx_ring[i]; 2999 3000 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3001 if (unlikely(r != 0)) 3002 goto done; 3003 3004 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3005 if (!r) { 3006 r = gfx_v12_0_kgq_init_queue(ring, false); 3007 amdgpu_bo_kunmap(ring->mqd_obj); 3008 ring->mqd_ptr = NULL; 3009 } 3010 amdgpu_bo_unreserve(ring->mqd_obj); 3011 if (r) 3012 goto done; 3013 } 3014 3015 r = amdgpu_gfx_enable_kgq(adev, 0); 3016 if (r) 3017 goto done; 3018 3019 r = gfx_v12_0_cp_gfx_start(adev); 3020 if (r) 3021 goto done; 3022 3023 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3024 ring = &adev->gfx.gfx_ring[i]; 3025 ring->sched.ready = true; 3026 } 3027 done: 3028 return r; 3029 } 3030 3031 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3032 struct amdgpu_mqd_prop *prop) 3033 { 3034 struct v12_compute_mqd *mqd = m; 3035 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3036 uint32_t tmp; 3037 3038 mqd->header = 0xC0310800; 3039 mqd->compute_pipelinestat_enable = 0x00000001; 3040 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3041 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3042 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3043 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3044 mqd->compute_misc_reserved = 0x00000007; 3045 3046 eop_base_addr = prop->eop_gpu_addr >> 8; 3047 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3048 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3049 3050 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3051 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3052 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3053 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3054 3055 mqd->cp_hqd_eop_control = tmp; 3056 3057 /* enable doorbell? */ 3058 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3059 3060 if (prop->use_doorbell) { 3061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3062 DOORBELL_OFFSET, prop->doorbell_index); 3063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3064 DOORBELL_EN, 1); 3065 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3066 DOORBELL_SOURCE, 0); 3067 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3068 DOORBELL_HIT, 0); 3069 } else { 3070 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3071 DOORBELL_EN, 0); 3072 } 3073 3074 mqd->cp_hqd_pq_doorbell_control = tmp; 3075 3076 /* disable the queue if it's active */ 3077 mqd->cp_hqd_dequeue_request = 0; 3078 mqd->cp_hqd_pq_rptr = 0; 3079 mqd->cp_hqd_pq_wptr_lo = 0; 3080 mqd->cp_hqd_pq_wptr_hi = 0; 3081 3082 /* set the pointer to the MQD */ 3083 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3084 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3085 3086 /* set MQD vmid to 0 */ 3087 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3088 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3089 mqd->cp_mqd_control = tmp; 3090 3091 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3092 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3093 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3094 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3095 3096 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3097 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3098 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3099 (order_base_2(prop->queue_size / 4) - 1)); 3100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3101 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3102 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3104 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3106 mqd->cp_hqd_pq_control = tmp; 3107 3108 /* set the wb address whether it's enabled or not */ 3109 wb_gpu_addr = prop->rptr_gpu_addr; 3110 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3111 mqd->cp_hqd_pq_rptr_report_addr_hi = 3112 upper_32_bits(wb_gpu_addr) & 0xffff; 3113 3114 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3115 wb_gpu_addr = prop->wptr_gpu_addr; 3116 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3117 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3118 3119 tmp = 0; 3120 /* enable the doorbell if requested */ 3121 if (prop->use_doorbell) { 3122 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3123 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3124 DOORBELL_OFFSET, prop->doorbell_index); 3125 3126 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3127 DOORBELL_EN, 1); 3128 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3129 DOORBELL_SOURCE, 0); 3130 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3131 DOORBELL_HIT, 0); 3132 } 3133 3134 mqd->cp_hqd_pq_doorbell_control = tmp; 3135 3136 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3137 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3138 3139 /* set the vmid for the queue */ 3140 mqd->cp_hqd_vmid = 0; 3141 3142 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3143 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3144 mqd->cp_hqd_persistent_state = tmp; 3145 3146 /* set MIN_IB_AVAIL_SIZE */ 3147 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3148 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3149 mqd->cp_hqd_ib_control = tmp; 3150 3151 /* set static priority for a compute queue/ring */ 3152 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3153 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3154 3155 mqd->cp_hqd_active = prop->hqd_active; 3156 3157 return 0; 3158 } 3159 3160 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3161 { 3162 struct amdgpu_device *adev = ring->adev; 3163 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3164 int j; 3165 3166 /* inactivate the queue */ 3167 if (amdgpu_sriov_vf(adev)) 3168 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3169 3170 /* disable wptr polling */ 3171 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3172 3173 /* write the EOP addr */ 3174 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3175 mqd->cp_hqd_eop_base_addr_lo); 3176 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3177 mqd->cp_hqd_eop_base_addr_hi); 3178 3179 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3180 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3181 mqd->cp_hqd_eop_control); 3182 3183 /* enable doorbell? */ 3184 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3185 mqd->cp_hqd_pq_doorbell_control); 3186 3187 /* disable the queue if it's active */ 3188 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3189 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3190 for (j = 0; j < adev->usec_timeout; j++) { 3191 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3192 break; 3193 udelay(1); 3194 } 3195 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3196 mqd->cp_hqd_dequeue_request); 3197 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3198 mqd->cp_hqd_pq_rptr); 3199 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3200 mqd->cp_hqd_pq_wptr_lo); 3201 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3202 mqd->cp_hqd_pq_wptr_hi); 3203 } 3204 3205 /* set the pointer to the MQD */ 3206 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3207 mqd->cp_mqd_base_addr_lo); 3208 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3209 mqd->cp_mqd_base_addr_hi); 3210 3211 /* set MQD vmid to 0 */ 3212 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3213 mqd->cp_mqd_control); 3214 3215 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3216 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3217 mqd->cp_hqd_pq_base_lo); 3218 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3219 mqd->cp_hqd_pq_base_hi); 3220 3221 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3223 mqd->cp_hqd_pq_control); 3224 3225 /* set the wb address whether it's enabled or not */ 3226 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3227 mqd->cp_hqd_pq_rptr_report_addr_lo); 3228 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3229 mqd->cp_hqd_pq_rptr_report_addr_hi); 3230 3231 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3233 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3234 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3235 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3236 3237 /* enable the doorbell if requested */ 3238 if (ring->use_doorbell) { 3239 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3240 (adev->doorbell_index.kiq * 2) << 2); 3241 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3242 (adev->doorbell_index.userqueue_end * 2) << 2); 3243 } 3244 3245 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3246 mqd->cp_hqd_pq_doorbell_control); 3247 3248 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3249 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3250 mqd->cp_hqd_pq_wptr_lo); 3251 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3252 mqd->cp_hqd_pq_wptr_hi); 3253 3254 /* set the vmid for the queue */ 3255 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3256 3257 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3258 mqd->cp_hqd_persistent_state); 3259 3260 /* activate the queue */ 3261 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3262 mqd->cp_hqd_active); 3263 3264 if (ring->use_doorbell) 3265 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3266 3267 return 0; 3268 } 3269 3270 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3271 { 3272 struct amdgpu_device *adev = ring->adev; 3273 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3274 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3275 3276 gfx_v12_0_kiq_setting(ring); 3277 3278 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3279 /* reset MQD to a clean status */ 3280 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3281 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3282 3283 /* reset ring buffer */ 3284 ring->wptr = 0; 3285 amdgpu_ring_clear_ring(ring); 3286 3287 mutex_lock(&adev->srbm_mutex); 3288 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3289 gfx_v12_0_kiq_init_register(ring); 3290 soc24_grbm_select(adev, 0, 0, 0, 0); 3291 mutex_unlock(&adev->srbm_mutex); 3292 } else { 3293 memset((void *)mqd, 0, sizeof(*mqd)); 3294 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3295 amdgpu_ring_clear_ring(ring); 3296 mutex_lock(&adev->srbm_mutex); 3297 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3298 amdgpu_ring_init_mqd(ring); 3299 gfx_v12_0_kiq_init_register(ring); 3300 soc24_grbm_select(adev, 0, 0, 0, 0); 3301 mutex_unlock(&adev->srbm_mutex); 3302 3303 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3304 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3305 } 3306 3307 return 0; 3308 } 3309 3310 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3311 { 3312 struct amdgpu_device *adev = ring->adev; 3313 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3314 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3315 3316 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3317 memset((void *)mqd, 0, sizeof(*mqd)); 3318 mutex_lock(&adev->srbm_mutex); 3319 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3320 amdgpu_ring_init_mqd(ring); 3321 soc24_grbm_select(adev, 0, 0, 0, 0); 3322 mutex_unlock(&adev->srbm_mutex); 3323 3324 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3325 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3326 } else { 3327 /* restore MQD to a clean status */ 3328 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3329 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3330 /* reset ring buffer */ 3331 ring->wptr = 0; 3332 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3333 amdgpu_ring_clear_ring(ring); 3334 } 3335 3336 return 0; 3337 } 3338 3339 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3340 { 3341 struct amdgpu_ring *ring; 3342 int r; 3343 3344 ring = &adev->gfx.kiq[0].ring; 3345 3346 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3347 if (unlikely(r != 0)) 3348 return r; 3349 3350 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3351 if (unlikely(r != 0)) { 3352 amdgpu_bo_unreserve(ring->mqd_obj); 3353 return r; 3354 } 3355 3356 gfx_v12_0_kiq_init_queue(ring); 3357 amdgpu_bo_kunmap(ring->mqd_obj); 3358 ring->mqd_ptr = NULL; 3359 amdgpu_bo_unreserve(ring->mqd_obj); 3360 ring->sched.ready = true; 3361 return 0; 3362 } 3363 3364 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3365 { 3366 struct amdgpu_ring *ring = NULL; 3367 int r = 0, i; 3368 3369 if (!amdgpu_async_gfx_ring) 3370 gfx_v12_0_cp_compute_enable(adev, true); 3371 3372 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3373 ring = &adev->gfx.compute_ring[i]; 3374 3375 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3376 if (unlikely(r != 0)) 3377 goto done; 3378 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3379 if (!r) { 3380 r = gfx_v12_0_kcq_init_queue(ring, false); 3381 amdgpu_bo_kunmap(ring->mqd_obj); 3382 ring->mqd_ptr = NULL; 3383 } 3384 amdgpu_bo_unreserve(ring->mqd_obj); 3385 if (r) 3386 goto done; 3387 } 3388 3389 r = amdgpu_gfx_enable_kcq(adev, 0); 3390 done: 3391 return r; 3392 } 3393 3394 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3395 { 3396 int r, i; 3397 struct amdgpu_ring *ring; 3398 3399 if (!(adev->flags & AMD_IS_APU)) 3400 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3401 3402 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3403 /* legacy firmware loading */ 3404 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3405 if (r) 3406 return r; 3407 3408 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3409 if (r) 3410 return r; 3411 } 3412 3413 gfx_v12_0_cp_set_doorbell_range(adev); 3414 3415 if (amdgpu_async_gfx_ring) { 3416 gfx_v12_0_cp_compute_enable(adev, true); 3417 gfx_v12_0_cp_gfx_enable(adev, true); 3418 } 3419 3420 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3421 r = amdgpu_mes_kiq_hw_init(adev); 3422 else 3423 r = gfx_v12_0_kiq_resume(adev); 3424 if (r) 3425 return r; 3426 3427 r = gfx_v12_0_kcq_resume(adev); 3428 if (r) 3429 return r; 3430 3431 if (!amdgpu_async_gfx_ring) { 3432 r = gfx_v12_0_cp_gfx_resume(adev); 3433 if (r) 3434 return r; 3435 } else { 3436 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3437 if (r) 3438 return r; 3439 } 3440 3441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3442 ring = &adev->gfx.gfx_ring[i]; 3443 r = amdgpu_ring_test_helper(ring); 3444 if (r) 3445 return r; 3446 } 3447 3448 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3449 ring = &adev->gfx.compute_ring[i]; 3450 r = amdgpu_ring_test_helper(ring); 3451 if (r) 3452 return r; 3453 } 3454 3455 return 0; 3456 } 3457 3458 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3459 { 3460 gfx_v12_0_cp_gfx_enable(adev, enable); 3461 gfx_v12_0_cp_compute_enable(adev, enable); 3462 } 3463 3464 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3465 { 3466 int r; 3467 bool value; 3468 3469 r = adev->gfxhub.funcs->gart_enable(adev); 3470 if (r) 3471 return r; 3472 3473 adev->hdp.funcs->flush_hdp(adev, NULL); 3474 3475 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3476 false : true; 3477 3478 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3479 /* TODO investigate why this and the hdp flush above is needed, 3480 * are we missing a flush somewhere else? */ 3481 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3482 3483 return 0; 3484 } 3485 3486 static int get_gb_addr_config(struct amdgpu_device *adev) 3487 { 3488 u32 gb_addr_config; 3489 3490 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3491 if (gb_addr_config == 0) 3492 return -EINVAL; 3493 3494 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3495 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3496 3497 adev->gfx.config.gb_addr_config = gb_addr_config; 3498 3499 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3500 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3501 GB_ADDR_CONFIG, NUM_PIPES); 3502 3503 adev->gfx.config.max_tile_pipes = 3504 adev->gfx.config.gb_addr_config_fields.num_pipes; 3505 3506 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3507 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3508 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3509 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3510 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3511 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3512 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3513 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3514 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3515 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3516 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3517 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3518 3519 return 0; 3520 } 3521 3522 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3523 { 3524 uint32_t data; 3525 3526 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3527 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3528 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3529 3530 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3531 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3532 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3533 } 3534 3535 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3536 { 3537 if (amdgpu_sriov_vf(adev)) 3538 return; 3539 3540 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3541 case IP_VERSION(12, 0, 0): 3542 case IP_VERSION(12, 0, 1): 3543 soc15_program_register_sequence(adev, 3544 golden_settings_gc_12_0, 3545 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3546 3547 if (adev->rev_id == 0) 3548 soc15_program_register_sequence(adev, 3549 golden_settings_gc_12_0_rev0, 3550 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3551 break; 3552 default: 3553 break; 3554 } 3555 } 3556 3557 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3558 { 3559 int r; 3560 struct amdgpu_device *adev = ip_block->adev; 3561 3562 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3563 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3564 /* RLC autoload sequence 1: Program rlc ram */ 3565 if (adev->gfx.imu.funcs->program_rlc_ram) 3566 adev->gfx.imu.funcs->program_rlc_ram(adev); 3567 } 3568 /* rlc autoload firmware */ 3569 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3570 if (r) 3571 return r; 3572 } else { 3573 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3574 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3575 if (adev->gfx.imu.funcs->load_microcode) 3576 adev->gfx.imu.funcs->load_microcode(adev); 3577 if (adev->gfx.imu.funcs->setup_imu) 3578 adev->gfx.imu.funcs->setup_imu(adev); 3579 if (adev->gfx.imu.funcs->start_imu) 3580 adev->gfx.imu.funcs->start_imu(adev); 3581 } 3582 3583 /* disable gpa mode in backdoor loading */ 3584 gfx_v12_0_disable_gpa_mode(adev); 3585 } 3586 } 3587 3588 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3589 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3590 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3591 if (r) { 3592 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3593 return r; 3594 } 3595 } 3596 3597 if (!amdgpu_emu_mode) 3598 gfx_v12_0_init_golden_registers(adev); 3599 3600 adev->gfx.is_poweron = true; 3601 3602 if (get_gb_addr_config(adev)) 3603 DRM_WARN("Invalid gb_addr_config !\n"); 3604 3605 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3606 gfx_v12_0_config_gfx_rs64(adev); 3607 3608 r = gfx_v12_0_gfxhub_enable(adev); 3609 if (r) 3610 return r; 3611 3612 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3613 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3614 (amdgpu_dpm == 1)) { 3615 /** 3616 * For gfx 12, rlc firmware loading relies on smu firmware is 3617 * loaded firstly, so in direct type, it has to load smc ucode 3618 * here before rlc. 3619 */ 3620 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3621 if (r) 3622 return r; 3623 } 3624 3625 gfx_v12_0_constants_init(adev); 3626 3627 if (adev->nbio.funcs->gc_doorbell_init) 3628 adev->nbio.funcs->gc_doorbell_init(adev); 3629 3630 r = gfx_v12_0_rlc_resume(adev); 3631 if (r) 3632 return r; 3633 3634 /* 3635 * init golden registers and rlc resume may override some registers, 3636 * reconfig them here 3637 */ 3638 gfx_v12_0_tcp_harvest(adev); 3639 3640 r = gfx_v12_0_cp_resume(adev); 3641 if (r) 3642 return r; 3643 3644 return r; 3645 } 3646 3647 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3648 { 3649 struct amdgpu_device *adev = ip_block->adev; 3650 uint32_t tmp; 3651 3652 cancel_delayed_work_sync(&adev->gfx.idle_work); 3653 3654 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3655 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3656 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3657 3658 if (!adev->no_hw_access) { 3659 if (amdgpu_async_gfx_ring) { 3660 if (amdgpu_gfx_disable_kgq(adev, 0)) 3661 DRM_ERROR("KGQ disable failed\n"); 3662 } 3663 3664 if (amdgpu_gfx_disable_kcq(adev, 0)) 3665 DRM_ERROR("KCQ disable failed\n"); 3666 3667 amdgpu_mes_kiq_hw_fini(adev); 3668 } 3669 3670 if (amdgpu_sriov_vf(adev)) { 3671 gfx_v12_0_cp_gfx_enable(adev, false); 3672 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3673 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3674 tmp &= 0xffffff00; 3675 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3676 3677 return 0; 3678 } 3679 gfx_v12_0_cp_enable(adev, false); 3680 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3681 3682 adev->gfxhub.funcs->gart_disable(adev); 3683 3684 adev->gfx.is_poweron = false; 3685 3686 return 0; 3687 } 3688 3689 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3690 { 3691 return gfx_v12_0_hw_fini(ip_block); 3692 } 3693 3694 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3695 { 3696 return gfx_v12_0_hw_init(ip_block); 3697 } 3698 3699 static bool gfx_v12_0_is_idle(void *handle) 3700 { 3701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3702 3703 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3704 GRBM_STATUS, GUI_ACTIVE)) 3705 return false; 3706 else 3707 return true; 3708 } 3709 3710 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3711 { 3712 unsigned i; 3713 u32 tmp; 3714 struct amdgpu_device *adev = ip_block->adev; 3715 3716 for (i = 0; i < adev->usec_timeout; i++) { 3717 /* read MC_STATUS */ 3718 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3719 GRBM_STATUS__GUI_ACTIVE_MASK; 3720 3721 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3722 return 0; 3723 udelay(1); 3724 } 3725 return -ETIMEDOUT; 3726 } 3727 3728 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3729 { 3730 uint64_t clock = 0; 3731 3732 if (adev->smuio.funcs && 3733 adev->smuio.funcs->get_gpu_clock_counter) 3734 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3735 else 3736 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3737 3738 return clock; 3739 } 3740 3741 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3742 { 3743 struct amdgpu_device *adev = ip_block->adev; 3744 3745 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3746 3747 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3748 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3749 AMDGPU_MAX_COMPUTE_RINGS); 3750 3751 gfx_v12_0_set_kiq_pm4_funcs(adev); 3752 gfx_v12_0_set_ring_funcs(adev); 3753 gfx_v12_0_set_irq_funcs(adev); 3754 gfx_v12_0_set_rlc_funcs(adev); 3755 gfx_v12_0_set_mqd_funcs(adev); 3756 gfx_v12_0_set_imu_funcs(adev); 3757 3758 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3759 3760 return gfx_v12_0_init_microcode(adev); 3761 } 3762 3763 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3764 { 3765 struct amdgpu_device *adev = ip_block->adev; 3766 int r; 3767 3768 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3769 if (r) 3770 return r; 3771 3772 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3773 if (r) 3774 return r; 3775 3776 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3777 if (r) 3778 return r; 3779 3780 return 0; 3781 } 3782 3783 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3784 { 3785 uint32_t rlc_cntl; 3786 3787 /* if RLC is not enabled, do nothing */ 3788 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3789 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3790 } 3791 3792 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3793 int xcc_id) 3794 { 3795 uint32_t data; 3796 unsigned i; 3797 3798 data = RLC_SAFE_MODE__CMD_MASK; 3799 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3800 3801 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3802 3803 /* wait for RLC_SAFE_MODE */ 3804 for (i = 0; i < adev->usec_timeout; i++) { 3805 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3806 RLC_SAFE_MODE, CMD)) 3807 break; 3808 udelay(1); 3809 } 3810 } 3811 3812 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3813 int xcc_id) 3814 { 3815 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3816 } 3817 3818 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3819 bool enable) 3820 { 3821 uint32_t def, data; 3822 3823 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3824 return; 3825 3826 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3827 3828 if (enable) 3829 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3830 else 3831 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3832 3833 if (def != data) 3834 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3835 } 3836 3837 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3838 struct amdgpu_ring *ring, 3839 unsigned vmid) 3840 { 3841 u32 reg, data; 3842 3843 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3844 if (amdgpu_sriov_is_pp_one_vf(adev)) 3845 data = RREG32_NO_KIQ(reg); 3846 else 3847 data = RREG32(reg); 3848 3849 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3850 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3851 3852 if (amdgpu_sriov_is_pp_one_vf(adev)) 3853 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3854 else 3855 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3856 3857 if (ring 3858 && amdgpu_sriov_is_pp_one_vf(adev) 3859 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3860 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3861 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3862 amdgpu_ring_emit_wreg(ring, reg, data); 3863 } 3864 } 3865 3866 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3867 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3868 .set_safe_mode = gfx_v12_0_set_safe_mode, 3869 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3870 .init = gfx_v12_0_rlc_init, 3871 .get_csb_size = gfx_v12_0_get_csb_size, 3872 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3873 .resume = gfx_v12_0_rlc_resume, 3874 .stop = gfx_v12_0_rlc_stop, 3875 .reset = gfx_v12_0_rlc_reset, 3876 .start = gfx_v12_0_rlc_start, 3877 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3878 }; 3879 3880 #if 0 3881 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3882 { 3883 /* TODO */ 3884 } 3885 3886 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3887 { 3888 /* TODO */ 3889 } 3890 #endif 3891 3892 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3893 enum amd_powergating_state state) 3894 { 3895 struct amdgpu_device *adev = ip_block->adev; 3896 bool enable = (state == AMD_PG_STATE_GATE); 3897 3898 if (amdgpu_sriov_vf(adev)) 3899 return 0; 3900 3901 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3902 case IP_VERSION(12, 0, 0): 3903 case IP_VERSION(12, 0, 1): 3904 amdgpu_gfx_off_ctrl(adev, enable); 3905 break; 3906 default: 3907 break; 3908 } 3909 3910 return 0; 3911 } 3912 3913 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3914 bool enable) 3915 { 3916 uint32_t def, data; 3917 3918 if (!(adev->cg_flags & 3919 (AMD_CG_SUPPORT_GFX_CGCG | 3920 AMD_CG_SUPPORT_GFX_CGLS | 3921 AMD_CG_SUPPORT_GFX_3D_CGCG | 3922 AMD_CG_SUPPORT_GFX_3D_CGLS))) 3923 return; 3924 3925 if (enable) { 3926 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3927 3928 /* unset CGCG override */ 3929 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3930 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3932 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3933 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3934 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3935 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3936 3937 /* update CGCG override bits */ 3938 if (def != data) 3939 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3940 3941 /* enable cgcg FSM(0x0000363F) */ 3942 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 3943 3944 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3945 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3946 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3947 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3948 } 3949 3950 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3951 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3952 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3953 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3954 } 3955 3956 if (def != data) 3957 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 3958 3959 /* Program RLC_CGCG_CGLS_CTRL_3D */ 3960 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 3961 3962 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 3963 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 3964 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3965 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3966 } 3967 3968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 3969 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 3970 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3971 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3972 } 3973 3974 if (def != data) 3975 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 3976 3977 /* set IDLE_POLL_COUNT(0x00900100) */ 3978 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 3979 3980 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 3981 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3982 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3983 3984 if (def != data) 3985 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 3986 3987 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 3988 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3989 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3990 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3991 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3992 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 3993 3994 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 3995 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 3996 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 3997 3998 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 3999 if (adev->sdma.num_instances > 1) { 4000 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4001 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4002 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4003 } 4004 } else { 4005 /* Program RLC_CGCG_CGLS_CTRL */ 4006 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4007 4008 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4009 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4010 4011 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4012 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4013 4014 if (def != data) 4015 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4016 4017 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4018 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4019 4020 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4021 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4022 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4023 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4024 4025 if (def != data) 4026 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4027 } 4028 } 4029 4030 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4031 bool enable) 4032 { 4033 uint32_t data, def; 4034 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4035 return; 4036 4037 /* It is disabled by HW by default */ 4038 if (enable) { 4039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4040 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4041 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4042 4043 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4044 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4045 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4046 4047 if (def != data) 4048 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4049 } 4050 } else { 4051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4052 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4053 4054 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4055 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4056 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4057 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4060 } 4061 } 4062 } 4063 4064 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4065 bool enable) 4066 { 4067 uint32_t def, data; 4068 4069 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4070 return; 4071 4072 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4073 4074 if (enable) 4075 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4076 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4077 else 4078 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4079 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4080 4081 if (def != data) 4082 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4083 } 4084 4085 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4086 bool enable) 4087 { 4088 uint32_t def, data; 4089 4090 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4091 return; 4092 4093 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4094 4095 if (enable) 4096 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4097 else 4098 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4099 4100 if (def != data) 4101 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4102 } 4103 4104 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4105 bool enable) 4106 { 4107 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4108 4109 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4110 4111 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4112 4113 gfx_v12_0_update_repeater_fgcg(adev, enable); 4114 4115 gfx_v12_0_update_sram_fgcg(adev, enable); 4116 4117 gfx_v12_0_update_perf_clk(adev, enable); 4118 4119 if (adev->cg_flags & 4120 (AMD_CG_SUPPORT_GFX_MGCG | 4121 AMD_CG_SUPPORT_GFX_CGLS | 4122 AMD_CG_SUPPORT_GFX_CGCG | 4123 AMD_CG_SUPPORT_GFX_3D_CGCG | 4124 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4125 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4126 4127 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4128 4129 return 0; 4130 } 4131 4132 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4133 enum amd_clockgating_state state) 4134 { 4135 struct amdgpu_device *adev = ip_block->adev; 4136 4137 if (amdgpu_sriov_vf(adev)) 4138 return 0; 4139 4140 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4141 case IP_VERSION(12, 0, 0): 4142 case IP_VERSION(12, 0, 1): 4143 gfx_v12_0_update_gfx_clock_gating(adev, 4144 state == AMD_CG_STATE_GATE); 4145 break; 4146 default: 4147 break; 4148 } 4149 4150 return 0; 4151 } 4152 4153 static void gfx_v12_0_get_clockgating_state(void *handle, u64 *flags) 4154 { 4155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4156 int data; 4157 4158 /* AMD_CG_SUPPORT_GFX_MGCG */ 4159 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4160 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4161 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4162 4163 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4164 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4165 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4166 4167 /* AMD_CG_SUPPORT_GFX_FGCG */ 4168 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4169 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4170 4171 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4172 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4173 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4174 4175 /* AMD_CG_SUPPORT_GFX_CGCG */ 4176 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4177 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4178 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4179 4180 /* AMD_CG_SUPPORT_GFX_CGLS */ 4181 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4182 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4183 4184 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4185 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4186 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4187 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4188 4189 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4190 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4191 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4192 } 4193 4194 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4195 { 4196 /* gfx12 is 32bit rptr*/ 4197 return *(uint32_t *)ring->rptr_cpu_addr; 4198 } 4199 4200 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4201 { 4202 struct amdgpu_device *adev = ring->adev; 4203 u64 wptr; 4204 4205 /* XXX check if swapping is necessary on BE */ 4206 if (ring->use_doorbell) { 4207 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4208 } else { 4209 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4210 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4211 } 4212 4213 return wptr; 4214 } 4215 4216 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4217 { 4218 struct amdgpu_device *adev = ring->adev; 4219 uint32_t *wptr_saved; 4220 uint32_t *is_queue_unmap; 4221 uint64_t aggregated_db_index; 4222 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 4223 uint64_t wptr_tmp; 4224 4225 if (ring->is_mes_queue) { 4226 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4227 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4228 sizeof(uint32_t)); 4229 aggregated_db_index = 4230 amdgpu_mes_get_aggregated_doorbell_index(adev, 4231 ring->hw_prio); 4232 4233 wptr_tmp = ring->wptr & ring->buf_mask; 4234 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4235 *wptr_saved = wptr_tmp; 4236 /* assume doorbell always being used by mes mapped queue */ 4237 if (*is_queue_unmap) { 4238 WDOORBELL64(aggregated_db_index, wptr_tmp); 4239 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4240 } else { 4241 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4242 4243 if (*is_queue_unmap) 4244 WDOORBELL64(aggregated_db_index, wptr_tmp); 4245 } 4246 } else { 4247 if (ring->use_doorbell) { 4248 /* XXX check if swapping is necessary on BE */ 4249 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4250 ring->wptr); 4251 WDOORBELL64(ring->doorbell_index, ring->wptr); 4252 } else { 4253 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4254 lower_32_bits(ring->wptr)); 4255 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4256 upper_32_bits(ring->wptr)); 4257 } 4258 } 4259 } 4260 4261 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4262 { 4263 /* gfx12 hardware is 32bit rptr */ 4264 return *(uint32_t *)ring->rptr_cpu_addr; 4265 } 4266 4267 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4268 { 4269 u64 wptr; 4270 4271 /* XXX check if swapping is necessary on BE */ 4272 if (ring->use_doorbell) 4273 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4274 else 4275 BUG(); 4276 return wptr; 4277 } 4278 4279 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4280 { 4281 struct amdgpu_device *adev = ring->adev; 4282 uint32_t *wptr_saved; 4283 uint32_t *is_queue_unmap; 4284 uint64_t aggregated_db_index; 4285 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 4286 uint64_t wptr_tmp; 4287 4288 if (ring->is_mes_queue) { 4289 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 4290 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 4291 sizeof(uint32_t)); 4292 aggregated_db_index = 4293 amdgpu_mes_get_aggregated_doorbell_index(adev, 4294 ring->hw_prio); 4295 4296 wptr_tmp = ring->wptr & ring->buf_mask; 4297 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 4298 *wptr_saved = wptr_tmp; 4299 /* assume doorbell always used by mes mapped queue */ 4300 if (*is_queue_unmap) { 4301 WDOORBELL64(aggregated_db_index, wptr_tmp); 4302 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4303 } else { 4304 WDOORBELL64(ring->doorbell_index, wptr_tmp); 4305 4306 if (*is_queue_unmap) 4307 WDOORBELL64(aggregated_db_index, wptr_tmp); 4308 } 4309 } else { 4310 /* XXX check if swapping is necessary on BE */ 4311 if (ring->use_doorbell) { 4312 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4313 ring->wptr); 4314 WDOORBELL64(ring->doorbell_index, ring->wptr); 4315 } else { 4316 BUG(); /* only DOORBELL method supported on gfx12 now */ 4317 } 4318 } 4319 } 4320 4321 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4322 { 4323 struct amdgpu_device *adev = ring->adev; 4324 u32 ref_and_mask, reg_mem_engine; 4325 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4326 4327 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4328 switch (ring->me) { 4329 case 1: 4330 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4331 break; 4332 case 2: 4333 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4334 break; 4335 default: 4336 return; 4337 } 4338 reg_mem_engine = 0; 4339 } else { 4340 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4341 reg_mem_engine = 1; /* pfp */ 4342 } 4343 4344 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4345 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4346 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4347 ref_and_mask, ref_and_mask, 0x20); 4348 } 4349 4350 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4351 struct amdgpu_job *job, 4352 struct amdgpu_ib *ib, 4353 uint32_t flags) 4354 { 4355 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4356 u32 header, control = 0; 4357 4358 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4359 4360 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4361 4362 control |= ib->length_dw | (vmid << 24); 4363 4364 if (ring->is_mes_queue) 4365 /* inherit vmid from mqd */ 4366 control |= 0x400000; 4367 4368 amdgpu_ring_write(ring, header); 4369 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4370 amdgpu_ring_write(ring, 4371 #ifdef __BIG_ENDIAN 4372 (2 << 0) | 4373 #endif 4374 lower_32_bits(ib->gpu_addr)); 4375 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4376 amdgpu_ring_write(ring, control); 4377 } 4378 4379 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4380 struct amdgpu_job *job, 4381 struct amdgpu_ib *ib, 4382 uint32_t flags) 4383 { 4384 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4385 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4386 4387 if (ring->is_mes_queue) 4388 /* inherit vmid from mqd */ 4389 control |= 0x40000000; 4390 4391 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4392 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4393 amdgpu_ring_write(ring, 4394 #ifdef __BIG_ENDIAN 4395 (2 << 0) | 4396 #endif 4397 lower_32_bits(ib->gpu_addr)); 4398 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4399 amdgpu_ring_write(ring, control); 4400 } 4401 4402 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4403 u64 seq, unsigned flags) 4404 { 4405 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4406 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4407 4408 /* RELEASE_MEM - flush caches, send int */ 4409 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4410 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4411 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4412 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4413 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4414 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4415 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4416 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4417 4418 /* 4419 * the address should be Qword aligned if 64bit write, Dword 4420 * aligned if only send 32bit data low (discard data high) 4421 */ 4422 if (write64bit) 4423 BUG_ON(addr & 0x7); 4424 else 4425 BUG_ON(addr & 0x3); 4426 amdgpu_ring_write(ring, lower_32_bits(addr)); 4427 amdgpu_ring_write(ring, upper_32_bits(addr)); 4428 amdgpu_ring_write(ring, lower_32_bits(seq)); 4429 amdgpu_ring_write(ring, upper_32_bits(seq)); 4430 amdgpu_ring_write(ring, ring->is_mes_queue ? 4431 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 4432 } 4433 4434 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4435 { 4436 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4437 uint32_t seq = ring->fence_drv.sync_seq; 4438 uint64_t addr = ring->fence_drv.gpu_addr; 4439 4440 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4441 upper_32_bits(addr), seq, 0xffffffff, 4); 4442 } 4443 4444 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4445 uint16_t pasid, uint32_t flush_type, 4446 bool all_hub, uint8_t dst_sel) 4447 { 4448 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4449 amdgpu_ring_write(ring, 4450 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4451 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4452 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4453 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4454 } 4455 4456 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4457 unsigned vmid, uint64_t pd_addr) 4458 { 4459 if (ring->is_mes_queue) 4460 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 4461 else 4462 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4463 4464 /* compute doesn't have PFP */ 4465 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4466 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4467 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4468 amdgpu_ring_write(ring, 0x0); 4469 } 4470 } 4471 4472 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4473 u64 seq, unsigned int flags) 4474 { 4475 struct amdgpu_device *adev = ring->adev; 4476 4477 /* we only allocate 32bit for each seq wb address */ 4478 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4479 4480 /* write fence seq to the "addr" */ 4481 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4482 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4483 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4484 amdgpu_ring_write(ring, lower_32_bits(addr)); 4485 amdgpu_ring_write(ring, upper_32_bits(addr)); 4486 amdgpu_ring_write(ring, lower_32_bits(seq)); 4487 4488 if (flags & AMDGPU_FENCE_FLAG_INT) { 4489 /* set register to trigger INT */ 4490 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4491 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4492 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4493 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4494 amdgpu_ring_write(ring, 0); 4495 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4496 } 4497 } 4498 4499 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4500 uint32_t flags) 4501 { 4502 uint32_t dw2 = 0; 4503 4504 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4505 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4506 /* set load_global_config & load_global_uconfig */ 4507 dw2 |= 0x8001; 4508 /* set load_cs_sh_regs */ 4509 dw2 |= 0x01000000; 4510 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4511 dw2 |= 0x10002; 4512 } 4513 4514 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4515 amdgpu_ring_write(ring, dw2); 4516 amdgpu_ring_write(ring, 0); 4517 } 4518 4519 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4520 uint64_t addr) 4521 { 4522 unsigned ret; 4523 4524 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4525 amdgpu_ring_write(ring, lower_32_bits(addr)); 4526 amdgpu_ring_write(ring, upper_32_bits(addr)); 4527 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4528 amdgpu_ring_write(ring, 0); 4529 ret = ring->wptr & ring->buf_mask; 4530 /* patch dummy value later */ 4531 amdgpu_ring_write(ring, 0); 4532 4533 return ret; 4534 } 4535 4536 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4537 { 4538 int i, r = 0; 4539 struct amdgpu_device *adev = ring->adev; 4540 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4541 struct amdgpu_ring *kiq_ring = &kiq->ring; 4542 unsigned long flags; 4543 4544 if (adev->enable_mes) 4545 return -EINVAL; 4546 4547 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4548 return -EINVAL; 4549 4550 spin_lock_irqsave(&kiq->ring_lock, flags); 4551 4552 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4553 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4554 return -ENOMEM; 4555 } 4556 4557 /* assert preemption condition */ 4558 amdgpu_ring_set_preempt_cond_exec(ring, false); 4559 4560 /* assert IB preemption, emit the trailing fence */ 4561 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4562 ring->trail_fence_gpu_addr, 4563 ++ring->trail_seq); 4564 amdgpu_ring_commit(kiq_ring); 4565 4566 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4567 4568 /* poll the trailing fence */ 4569 for (i = 0; i < adev->usec_timeout; i++) { 4570 if (ring->trail_seq == 4571 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4572 break; 4573 udelay(1); 4574 } 4575 4576 if (i >= adev->usec_timeout) { 4577 r = -EINVAL; 4578 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4579 } 4580 4581 /* deassert preemption condition */ 4582 amdgpu_ring_set_preempt_cond_exec(ring, true); 4583 return r; 4584 } 4585 4586 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4587 bool start, 4588 bool secure) 4589 { 4590 uint32_t v = secure ? FRAME_TMZ : 0; 4591 4592 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4593 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4594 } 4595 4596 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4597 uint32_t reg_val_offs) 4598 { 4599 struct amdgpu_device *adev = ring->adev; 4600 4601 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4602 amdgpu_ring_write(ring, 0 | /* src: register*/ 4603 (5 << 8) | /* dst: memory */ 4604 (1 << 20)); /* write confirm */ 4605 amdgpu_ring_write(ring, reg); 4606 amdgpu_ring_write(ring, 0); 4607 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4608 reg_val_offs * 4)); 4609 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4610 reg_val_offs * 4)); 4611 } 4612 4613 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4614 uint32_t reg, 4615 uint32_t val) 4616 { 4617 uint32_t cmd = 0; 4618 4619 switch (ring->funcs->type) { 4620 case AMDGPU_RING_TYPE_GFX: 4621 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4622 break; 4623 case AMDGPU_RING_TYPE_KIQ: 4624 cmd = (1 << 16); /* no inc addr */ 4625 break; 4626 default: 4627 cmd = WR_CONFIRM; 4628 break; 4629 } 4630 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4631 amdgpu_ring_write(ring, cmd); 4632 amdgpu_ring_write(ring, reg); 4633 amdgpu_ring_write(ring, 0); 4634 amdgpu_ring_write(ring, val); 4635 } 4636 4637 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4638 uint32_t val, uint32_t mask) 4639 { 4640 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4641 } 4642 4643 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4644 uint32_t reg0, uint32_t reg1, 4645 uint32_t ref, uint32_t mask) 4646 { 4647 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4648 4649 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4650 ref, mask, 0x20); 4651 } 4652 4653 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4654 unsigned vmid) 4655 { 4656 struct amdgpu_device *adev = ring->adev; 4657 uint32_t value = 0; 4658 4659 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4660 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4661 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4662 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4663 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4664 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4665 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4666 } 4667 4668 static void 4669 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4670 uint32_t me, uint32_t pipe, 4671 enum amdgpu_interrupt_state state) 4672 { 4673 uint32_t cp_int_cntl, cp_int_cntl_reg; 4674 4675 if (!me) { 4676 switch (pipe) { 4677 case 0: 4678 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4679 break; 4680 default: 4681 DRM_DEBUG("invalid pipe %d\n", pipe); 4682 return; 4683 } 4684 } else { 4685 DRM_DEBUG("invalid me %d\n", me); 4686 return; 4687 } 4688 4689 switch (state) { 4690 case AMDGPU_IRQ_STATE_DISABLE: 4691 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4692 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4693 TIME_STAMP_INT_ENABLE, 0); 4694 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4695 GENERIC0_INT_ENABLE, 0); 4696 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4697 break; 4698 case AMDGPU_IRQ_STATE_ENABLE: 4699 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4700 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4701 TIME_STAMP_INT_ENABLE, 1); 4702 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4703 GENERIC0_INT_ENABLE, 1); 4704 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4705 break; 4706 default: 4707 break; 4708 } 4709 } 4710 4711 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4712 int me, int pipe, 4713 enum amdgpu_interrupt_state state) 4714 { 4715 u32 mec_int_cntl, mec_int_cntl_reg; 4716 4717 /* 4718 * amdgpu controls only the first MEC. That's why this function only 4719 * handles the setting of interrupts for this specific MEC. All other 4720 * pipes' interrupts are set by amdkfd. 4721 */ 4722 4723 if (me == 1) { 4724 switch (pipe) { 4725 case 0: 4726 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4727 break; 4728 case 1: 4729 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4730 break; 4731 default: 4732 DRM_DEBUG("invalid pipe %d\n", pipe); 4733 return; 4734 } 4735 } else { 4736 DRM_DEBUG("invalid me %d\n", me); 4737 return; 4738 } 4739 4740 switch (state) { 4741 case AMDGPU_IRQ_STATE_DISABLE: 4742 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4743 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4744 TIME_STAMP_INT_ENABLE, 0); 4745 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4746 GENERIC0_INT_ENABLE, 0); 4747 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4748 break; 4749 case AMDGPU_IRQ_STATE_ENABLE: 4750 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4751 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4752 TIME_STAMP_INT_ENABLE, 1); 4753 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4754 GENERIC0_INT_ENABLE, 1); 4755 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4756 break; 4757 default: 4758 break; 4759 } 4760 } 4761 4762 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4763 struct amdgpu_irq_src *src, 4764 unsigned type, 4765 enum amdgpu_interrupt_state state) 4766 { 4767 switch (type) { 4768 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4769 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4770 break; 4771 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4772 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4773 break; 4774 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4775 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4776 break; 4777 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4778 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4779 break; 4780 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4781 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4782 break; 4783 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4784 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4785 break; 4786 default: 4787 break; 4788 } 4789 return 0; 4790 } 4791 4792 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4793 struct amdgpu_irq_src *source, 4794 struct amdgpu_iv_entry *entry) 4795 { 4796 int i; 4797 u8 me_id, pipe_id, queue_id; 4798 struct amdgpu_ring *ring; 4799 uint32_t mes_queue_id = entry->src_data[0]; 4800 4801 DRM_DEBUG("IH: CP EOP\n"); 4802 4803 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 4804 struct amdgpu_mes_queue *queue; 4805 4806 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 4807 4808 spin_lock(&adev->mes.queue_id_lock); 4809 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 4810 if (queue) { 4811 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 4812 amdgpu_fence_process(queue->ring); 4813 } 4814 spin_unlock(&adev->mes.queue_id_lock); 4815 } else { 4816 me_id = (entry->ring_id & 0x0c) >> 2; 4817 pipe_id = (entry->ring_id & 0x03) >> 0; 4818 queue_id = (entry->ring_id & 0x70) >> 4; 4819 4820 switch (me_id) { 4821 case 0: 4822 if (pipe_id == 0) 4823 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4824 else 4825 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4826 break; 4827 case 1: 4828 case 2: 4829 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4830 ring = &adev->gfx.compute_ring[i]; 4831 /* Per-queue interrupt is supported for MEC starting from VI. 4832 * The interrupt can only be enabled/disabled per pipe instead 4833 * of per queue. 4834 */ 4835 if ((ring->me == me_id) && 4836 (ring->pipe == pipe_id) && 4837 (ring->queue == queue_id)) 4838 amdgpu_fence_process(ring); 4839 } 4840 break; 4841 } 4842 } 4843 4844 return 0; 4845 } 4846 4847 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4848 struct amdgpu_irq_src *source, 4849 unsigned int type, 4850 enum amdgpu_interrupt_state state) 4851 { 4852 u32 cp_int_cntl_reg, cp_int_cntl; 4853 int i, j; 4854 4855 switch (state) { 4856 case AMDGPU_IRQ_STATE_DISABLE: 4857 case AMDGPU_IRQ_STATE_ENABLE: 4858 for (i = 0; i < adev->gfx.me.num_me; i++) { 4859 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4860 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4861 4862 if (cp_int_cntl_reg) { 4863 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4864 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4865 PRIV_REG_INT_ENABLE, 4866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4867 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4868 } 4869 } 4870 } 4871 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4872 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4873 /* MECs start at 1 */ 4874 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4875 4876 if (cp_int_cntl_reg) { 4877 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4878 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4879 PRIV_REG_INT_ENABLE, 4880 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4881 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4882 } 4883 } 4884 } 4885 break; 4886 default: 4887 break; 4888 } 4889 4890 return 0; 4891 } 4892 4893 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4894 struct amdgpu_irq_src *source, 4895 unsigned type, 4896 enum amdgpu_interrupt_state state) 4897 { 4898 u32 cp_int_cntl_reg, cp_int_cntl; 4899 int i, j; 4900 4901 switch (state) { 4902 case AMDGPU_IRQ_STATE_DISABLE: 4903 case AMDGPU_IRQ_STATE_ENABLE: 4904 for (i = 0; i < adev->gfx.me.num_me; i++) { 4905 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4906 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4907 4908 if (cp_int_cntl_reg) { 4909 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4910 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4911 OPCODE_ERROR_INT_ENABLE, 4912 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4913 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4914 } 4915 } 4916 } 4917 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4918 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4919 /* MECs start at 1 */ 4920 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4921 4922 if (cp_int_cntl_reg) { 4923 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4924 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4925 OPCODE_ERROR_INT_ENABLE, 4926 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4927 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4928 } 4929 } 4930 } 4931 break; 4932 default: 4933 break; 4934 } 4935 return 0; 4936 } 4937 4938 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4939 struct amdgpu_irq_src *source, 4940 unsigned int type, 4941 enum amdgpu_interrupt_state state) 4942 { 4943 u32 cp_int_cntl_reg, cp_int_cntl; 4944 int i, j; 4945 4946 switch (state) { 4947 case AMDGPU_IRQ_STATE_DISABLE: 4948 case AMDGPU_IRQ_STATE_ENABLE: 4949 for (i = 0; i < adev->gfx.me.num_me; i++) { 4950 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4951 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4952 4953 if (cp_int_cntl_reg) { 4954 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4955 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4956 PRIV_INSTR_INT_ENABLE, 4957 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4958 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4959 } 4960 } 4961 } 4962 break; 4963 default: 4964 break; 4965 } 4966 4967 return 0; 4968 } 4969 4970 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4971 struct amdgpu_iv_entry *entry) 4972 { 4973 u8 me_id, pipe_id, queue_id; 4974 struct amdgpu_ring *ring; 4975 int i; 4976 4977 me_id = (entry->ring_id & 0x0c) >> 2; 4978 pipe_id = (entry->ring_id & 0x03) >> 0; 4979 queue_id = (entry->ring_id & 0x70) >> 4; 4980 4981 switch (me_id) { 4982 case 0: 4983 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4984 ring = &adev->gfx.gfx_ring[i]; 4985 if (ring->me == me_id && ring->pipe == pipe_id && 4986 ring->queue == queue_id) 4987 drm_sched_fault(&ring->sched); 4988 } 4989 break; 4990 case 1: 4991 case 2: 4992 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4993 ring = &adev->gfx.compute_ring[i]; 4994 if (ring->me == me_id && ring->pipe == pipe_id && 4995 ring->queue == queue_id) 4996 drm_sched_fault(&ring->sched); 4997 } 4998 break; 4999 default: 5000 BUG(); 5001 break; 5002 } 5003 } 5004 5005 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5006 struct amdgpu_irq_src *source, 5007 struct amdgpu_iv_entry *entry) 5008 { 5009 DRM_ERROR("Illegal register access in command stream\n"); 5010 gfx_v12_0_handle_priv_fault(adev, entry); 5011 return 0; 5012 } 5013 5014 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5015 struct amdgpu_irq_src *source, 5016 struct amdgpu_iv_entry *entry) 5017 { 5018 DRM_ERROR("Illegal opcode in command stream \n"); 5019 gfx_v12_0_handle_priv_fault(adev, entry); 5020 return 0; 5021 } 5022 5023 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5024 struct amdgpu_irq_src *source, 5025 struct amdgpu_iv_entry *entry) 5026 { 5027 DRM_ERROR("Illegal instruction in command stream\n"); 5028 gfx_v12_0_handle_priv_fault(adev, entry); 5029 return 0; 5030 } 5031 5032 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5033 { 5034 const unsigned int gcr_cntl = 5035 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5036 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5037 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5038 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5039 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5040 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5041 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5042 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5043 5044 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5045 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5046 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5047 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5048 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5049 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5050 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5051 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5052 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5053 } 5054 5055 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5056 { 5057 /* Header itself is a NOP packet */ 5058 if (num_nop == 1) { 5059 amdgpu_ring_write(ring, ring->funcs->nop); 5060 return; 5061 } 5062 5063 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5064 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5065 5066 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5067 amdgpu_ring_insert_nop(ring, num_nop - 1); 5068 } 5069 5070 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5071 { 5072 /* Emit the cleaner shader */ 5073 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5074 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5075 } 5076 5077 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5078 { 5079 struct amdgpu_device *adev = ip_block->adev; 5080 uint32_t i, j, k, reg, index = 0; 5081 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5082 5083 if (!adev->gfx.ip_dump_core) 5084 return; 5085 5086 for (i = 0; i < reg_count; i++) 5087 drm_printf(p, "%-50s \t 0x%08x\n", 5088 gc_reg_list_12_0[i].reg_name, 5089 adev->gfx.ip_dump_core[i]); 5090 5091 /* print compute queue registers for all instances */ 5092 if (!adev->gfx.ip_dump_compute_queues) 5093 return; 5094 5095 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5096 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5097 adev->gfx.mec.num_mec, 5098 adev->gfx.mec.num_pipe_per_mec, 5099 adev->gfx.mec.num_queue_per_pipe); 5100 5101 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5102 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5103 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5104 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5105 for (reg = 0; reg < reg_count; reg++) { 5106 drm_printf(p, "%-50s \t 0x%08x\n", 5107 gc_cp_reg_list_12[reg].reg_name, 5108 adev->gfx.ip_dump_compute_queues[index + reg]); 5109 } 5110 index += reg_count; 5111 } 5112 } 5113 } 5114 5115 /* print gfx queue registers for all instances */ 5116 if (!adev->gfx.ip_dump_gfx_queues) 5117 return; 5118 5119 index = 0; 5120 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5121 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5122 adev->gfx.me.num_me, 5123 adev->gfx.me.num_pipe_per_me, 5124 adev->gfx.me.num_queue_per_pipe); 5125 5126 for (i = 0; i < adev->gfx.me.num_me; i++) { 5127 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5128 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5129 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5130 for (reg = 0; reg < reg_count; reg++) { 5131 drm_printf(p, "%-50s \t 0x%08x\n", 5132 gc_gfx_queue_reg_list_12[reg].reg_name, 5133 adev->gfx.ip_dump_gfx_queues[index + reg]); 5134 } 5135 index += reg_count; 5136 } 5137 } 5138 } 5139 } 5140 5141 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5142 { 5143 struct amdgpu_device *adev = ip_block->adev; 5144 uint32_t i, j, k, reg, index = 0; 5145 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5146 5147 if (!adev->gfx.ip_dump_core) 5148 return; 5149 5150 amdgpu_gfx_off_ctrl(adev, false); 5151 for (i = 0; i < reg_count; i++) 5152 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5153 amdgpu_gfx_off_ctrl(adev, true); 5154 5155 /* dump compute queue registers for all instances */ 5156 if (!adev->gfx.ip_dump_compute_queues) 5157 return; 5158 5159 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5160 amdgpu_gfx_off_ctrl(adev, false); 5161 mutex_lock(&adev->srbm_mutex); 5162 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5163 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5164 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5165 /* ME0 is for GFX so start from 1 for CP */ 5166 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5167 for (reg = 0; reg < reg_count; reg++) { 5168 adev->gfx.ip_dump_compute_queues[index + reg] = 5169 RREG32(SOC15_REG_ENTRY_OFFSET( 5170 gc_cp_reg_list_12[reg])); 5171 } 5172 index += reg_count; 5173 } 5174 } 5175 } 5176 soc24_grbm_select(adev, 0, 0, 0, 0); 5177 mutex_unlock(&adev->srbm_mutex); 5178 amdgpu_gfx_off_ctrl(adev, true); 5179 5180 /* dump gfx queue registers for all instances */ 5181 if (!adev->gfx.ip_dump_gfx_queues) 5182 return; 5183 5184 index = 0; 5185 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5186 amdgpu_gfx_off_ctrl(adev, false); 5187 mutex_lock(&adev->srbm_mutex); 5188 for (i = 0; i < adev->gfx.me.num_me; i++) { 5189 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5190 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5191 soc24_grbm_select(adev, i, j, k, 0); 5192 5193 for (reg = 0; reg < reg_count; reg++) { 5194 adev->gfx.ip_dump_gfx_queues[index + reg] = 5195 RREG32(SOC15_REG_ENTRY_OFFSET( 5196 gc_gfx_queue_reg_list_12[reg])); 5197 } 5198 index += reg_count; 5199 } 5200 } 5201 } 5202 soc24_grbm_select(adev, 0, 0, 0, 0); 5203 mutex_unlock(&adev->srbm_mutex); 5204 amdgpu_gfx_off_ctrl(adev, true); 5205 } 5206 5207 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5208 { 5209 struct amdgpu_device *adev = ring->adev; 5210 int r; 5211 5212 if (amdgpu_sriov_vf(adev)) 5213 return -EINVAL; 5214 5215 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5216 if (r) { 5217 dev_err(adev->dev, "reset via MES failed %d\n", r); 5218 return r; 5219 } 5220 5221 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5222 if (unlikely(r != 0)) { 5223 dev_err(adev->dev, "fail to resv mqd_obj\n"); 5224 return r; 5225 } 5226 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5227 if (!r) { 5228 r = gfx_v12_0_kgq_init_queue(ring, true); 5229 amdgpu_bo_kunmap(ring->mqd_obj); 5230 ring->mqd_ptr = NULL; 5231 } 5232 amdgpu_bo_unreserve(ring->mqd_obj); 5233 if (r) { 5234 DRM_ERROR("fail to unresv mqd_obj\n"); 5235 return r; 5236 } 5237 5238 r = amdgpu_mes_map_legacy_queue(adev, ring); 5239 if (r) { 5240 dev_err(adev->dev, "failed to remap kgq\n"); 5241 return r; 5242 } 5243 5244 return amdgpu_ring_test_ring(ring); 5245 } 5246 5247 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5248 { 5249 struct amdgpu_device *adev = ring->adev; 5250 int r; 5251 5252 if (amdgpu_sriov_vf(adev)) 5253 return -EINVAL; 5254 5255 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5256 if (r) { 5257 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 5258 return r; 5259 } 5260 5261 r = amdgpu_bo_reserve(ring->mqd_obj, false); 5262 if (unlikely(r != 0)) { 5263 DRM_ERROR("fail to resv mqd_obj\n"); 5264 return r; 5265 } 5266 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 5267 if (!r) { 5268 r = gfx_v12_0_kcq_init_queue(ring, true); 5269 amdgpu_bo_kunmap(ring->mqd_obj); 5270 ring->mqd_ptr = NULL; 5271 } 5272 amdgpu_bo_unreserve(ring->mqd_obj); 5273 if (r) { 5274 DRM_ERROR("fail to unresv mqd_obj\n"); 5275 return r; 5276 } 5277 r = amdgpu_mes_map_legacy_queue(adev, ring); 5278 if (r) { 5279 dev_err(adev->dev, "failed to remap kcq\n"); 5280 return r; 5281 } 5282 5283 return amdgpu_ring_test_ring(ring); 5284 } 5285 5286 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5287 { 5288 amdgpu_gfx_profile_ring_begin_use(ring); 5289 5290 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5291 } 5292 5293 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5294 { 5295 amdgpu_gfx_profile_ring_end_use(ring); 5296 5297 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5298 } 5299 5300 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5301 .name = "gfx_v12_0", 5302 .early_init = gfx_v12_0_early_init, 5303 .late_init = gfx_v12_0_late_init, 5304 .sw_init = gfx_v12_0_sw_init, 5305 .sw_fini = gfx_v12_0_sw_fini, 5306 .hw_init = gfx_v12_0_hw_init, 5307 .hw_fini = gfx_v12_0_hw_fini, 5308 .suspend = gfx_v12_0_suspend, 5309 .resume = gfx_v12_0_resume, 5310 .is_idle = gfx_v12_0_is_idle, 5311 .wait_for_idle = gfx_v12_0_wait_for_idle, 5312 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5313 .set_powergating_state = gfx_v12_0_set_powergating_state, 5314 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5315 .dump_ip_state = gfx_v12_ip_dump, 5316 .print_ip_state = gfx_v12_ip_print, 5317 }; 5318 5319 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5320 .type = AMDGPU_RING_TYPE_GFX, 5321 .align_mask = 0xff, 5322 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5323 .support_64bit_ptrs = true, 5324 .secure_submission_supported = true, 5325 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5326 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5327 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5328 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5329 5 + /* COND_EXEC */ 5330 7 + /* PIPELINE_SYNC */ 5331 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5332 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5333 2 + /* VM_FLUSH */ 5334 8 + /* FENCE for VM_FLUSH */ 5335 5 + /* COND_EXEC */ 5336 7 + /* HDP_flush */ 5337 4 + /* VGT_flush */ 5338 31 + /* DE_META */ 5339 3 + /* CNTX_CTRL */ 5340 5 + /* HDP_INVL */ 5341 8 + 8 + /* FENCE x2 */ 5342 8 + /* gfx_v12_0_emit_mem_sync */ 5343 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5344 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5345 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5346 .emit_fence = gfx_v12_0_ring_emit_fence, 5347 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5348 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5349 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5350 .test_ring = gfx_v12_0_ring_test_ring, 5351 .test_ib = gfx_v12_0_ring_test_ib, 5352 .insert_nop = gfx_v12_ring_insert_nop, 5353 .pad_ib = amdgpu_ring_generic_pad_ib, 5354 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5355 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5356 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5357 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5358 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5359 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5360 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5361 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5362 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5363 .reset = gfx_v12_0_reset_kgq, 5364 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5365 .begin_use = gfx_v12_0_ring_begin_use, 5366 .end_use = gfx_v12_0_ring_end_use, 5367 }; 5368 5369 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5370 .type = AMDGPU_RING_TYPE_COMPUTE, 5371 .align_mask = 0xff, 5372 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5373 .support_64bit_ptrs = true, 5374 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5375 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5376 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5377 .emit_frame_size = 5378 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5379 5 + /* hdp invalidate */ 5380 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5381 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5382 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5383 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5384 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5385 8 + /* gfx_v12_0_emit_mem_sync */ 5386 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5387 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5388 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5389 .emit_fence = gfx_v12_0_ring_emit_fence, 5390 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5391 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5392 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5393 .test_ring = gfx_v12_0_ring_test_ring, 5394 .test_ib = gfx_v12_0_ring_test_ib, 5395 .insert_nop = gfx_v12_ring_insert_nop, 5396 .pad_ib = amdgpu_ring_generic_pad_ib, 5397 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5398 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5399 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5400 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5401 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5402 .reset = gfx_v12_0_reset_kcq, 5403 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5404 .begin_use = gfx_v12_0_ring_begin_use, 5405 .end_use = gfx_v12_0_ring_end_use, 5406 }; 5407 5408 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5409 .type = AMDGPU_RING_TYPE_KIQ, 5410 .align_mask = 0xff, 5411 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5412 .support_64bit_ptrs = true, 5413 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5414 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5415 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5416 .emit_frame_size = 5417 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5418 5 + /*hdp invalidate */ 5419 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5420 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5421 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5422 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5423 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5424 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5425 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5426 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5427 .test_ring = gfx_v12_0_ring_test_ring, 5428 .test_ib = gfx_v12_0_ring_test_ib, 5429 .insert_nop = amdgpu_ring_insert_nop, 5430 .pad_ib = amdgpu_ring_generic_pad_ib, 5431 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5432 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5433 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5434 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5435 }; 5436 5437 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5438 { 5439 int i; 5440 5441 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5442 5443 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5444 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5445 5446 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5447 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5448 } 5449 5450 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5451 .set = gfx_v12_0_set_eop_interrupt_state, 5452 .process = gfx_v12_0_eop_irq, 5453 }; 5454 5455 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5456 .set = gfx_v12_0_set_priv_reg_fault_state, 5457 .process = gfx_v12_0_priv_reg_irq, 5458 }; 5459 5460 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5461 .set = gfx_v12_0_set_bad_op_fault_state, 5462 .process = gfx_v12_0_bad_op_irq, 5463 }; 5464 5465 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5466 .set = gfx_v12_0_set_priv_inst_fault_state, 5467 .process = gfx_v12_0_priv_inst_irq, 5468 }; 5469 5470 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5471 { 5472 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5473 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5474 5475 adev->gfx.priv_reg_irq.num_types = 1; 5476 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5477 5478 adev->gfx.bad_op_irq.num_types = 1; 5479 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5480 5481 adev->gfx.priv_inst_irq.num_types = 1; 5482 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5483 } 5484 5485 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5486 { 5487 if (adev->flags & AMD_IS_APU) 5488 adev->gfx.imu.mode = MISSION_MODE; 5489 else 5490 adev->gfx.imu.mode = DEBUG_MODE; 5491 5492 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5493 } 5494 5495 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5496 { 5497 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5498 } 5499 5500 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5501 { 5502 /* set gfx eng mqd */ 5503 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5504 sizeof(struct v12_gfx_mqd); 5505 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5506 gfx_v12_0_gfx_mqd_init; 5507 /* set compute eng mqd */ 5508 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5509 sizeof(struct v12_compute_mqd); 5510 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5511 gfx_v12_0_compute_mqd_init; 5512 } 5513 5514 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5515 u32 bitmap) 5516 { 5517 u32 data; 5518 5519 if (!bitmap) 5520 return; 5521 5522 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5523 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5524 5525 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5526 } 5527 5528 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5529 { 5530 u32 data, wgp_bitmask; 5531 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5532 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5533 5534 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5535 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5536 5537 wgp_bitmask = 5538 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5539 5540 return (~data) & wgp_bitmask; 5541 } 5542 5543 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5544 { 5545 u32 wgp_idx, wgp_active_bitmap; 5546 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5547 5548 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5549 cu_active_bitmap = 0; 5550 5551 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5552 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5553 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5554 if (wgp_active_bitmap & (1 << wgp_idx)) 5555 cu_active_bitmap |= cu_bitmap_per_wgp; 5556 } 5557 5558 return cu_active_bitmap; 5559 } 5560 5561 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5562 struct amdgpu_cu_info *cu_info) 5563 { 5564 int i, j, k, counter, active_cu_number = 0; 5565 u32 mask, bitmap; 5566 unsigned disable_masks[8 * 2]; 5567 5568 if (!adev || !cu_info) 5569 return -EINVAL; 5570 5571 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5572 5573 mutex_lock(&adev->grbm_idx_mutex); 5574 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5575 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5576 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5577 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5578 continue; 5579 mask = 1; 5580 counter = 0; 5581 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5582 if (i < 8 && j < 2) 5583 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5584 adev, disable_masks[i * 2 + j]); 5585 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5586 5587 /** 5588 * GFX12 could support more than 4 SEs, while the bitmap 5589 * in cu_info struct is 4x4 and ioctl interface struct 5590 * drm_amdgpu_info_device should keep stable. 5591 * So we use last two columns of bitmap to store cu mask for 5592 * SEs 4 to 7, the layout of the bitmap is as below: 5593 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5594 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5595 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5596 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5597 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5598 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5599 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5600 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5601 */ 5602 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5603 5604 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5605 if (bitmap & mask) 5606 counter++; 5607 5608 mask <<= 1; 5609 } 5610 active_cu_number += counter; 5611 } 5612 } 5613 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5614 mutex_unlock(&adev->grbm_idx_mutex); 5615 5616 cu_info->number = active_cu_number; 5617 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5618 5619 return 0; 5620 } 5621 5622 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5623 .type = AMD_IP_BLOCK_TYPE_GFX, 5624 .major = 12, 5625 .minor = 0, 5626 .rev = 0, 5627 .funcs = &gfx_v12_0_ip_funcs, 5628 }; 5629