1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 83 84 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 120 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 121 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 124 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 138 /* cp header registers */ 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 /* SE status registers */ 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 152 }; 153 154 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 155 /* compute registers */ 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 195 /* cp header registers */ 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 }; 205 206 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 207 /* gfx queue registers */ 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 233 /* cp header registers */ 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 }; 251 252 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 256 }; 257 258 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 260 }; 261 262 #define DEFAULT_SH_MEM_CONFIG \ 263 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 264 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 265 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 266 267 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 268 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 273 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 274 struct amdgpu_cu_info *cu_info); 275 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 276 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 277 u32 sh_num, u32 instance, int xcc_id); 278 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 279 280 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 359 return; 360 } 361 362 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 363 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 364 PACKET3_UNMAP_QUEUES_ACTION(action) | 365 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 366 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 367 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 368 amdgpu_ring_write(kiq_ring, 369 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 370 371 if (action == PREEMPT_QUEUES_NO_UNMAP) { 372 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 373 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, seq); 375 } else { 376 amdgpu_ring_write(kiq_ring, 0); 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 } 380 } 381 382 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 383 struct amdgpu_ring *ring, 384 u64 addr, u64 seq) 385 { 386 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 387 388 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 389 amdgpu_ring_write(kiq_ring, 390 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 391 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 392 PACKET3_QUERY_STATUS_COMMAND(2)); 393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 394 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 395 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 396 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 397 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 400 } 401 402 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 403 uint16_t pasid, 404 uint32_t flush_type, 405 bool all_hub) 406 { 407 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 408 } 409 410 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 411 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 412 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 413 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 414 .kiq_query_status = gfx_v12_0_kiq_query_status, 415 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 416 .set_resources_size = 8, 417 .map_queues_size = 7, 418 .unmap_queues_size = 6, 419 .query_status_size = 7, 420 .invalidate_tlbs_size = 2, 421 }; 422 423 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 424 { 425 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 426 } 427 428 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 429 int mem_space, int opt, uint32_t addr0, 430 uint32_t addr1, uint32_t ref, 431 uint32_t mask, uint32_t inv) 432 { 433 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 434 amdgpu_ring_write(ring, 435 /* memory (1) or register (0) */ 436 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 437 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 438 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 439 WAIT_REG_MEM_ENGINE(eng_sel))); 440 441 if (mem_space) 442 BUG_ON(addr0 & 0x3); /* Dword align */ 443 amdgpu_ring_write(ring, addr0); 444 amdgpu_ring_write(ring, addr1); 445 amdgpu_ring_write(ring, ref); 446 amdgpu_ring_write(ring, mask); 447 amdgpu_ring_write(ring, inv); /* poll interval */ 448 } 449 450 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 454 uint32_t tmp = 0; 455 unsigned i; 456 int r; 457 458 WREG32(scratch, 0xCAFEDEAD); 459 r = amdgpu_ring_alloc(ring, 5); 460 if (r) { 461 dev_err(adev->dev, 462 "amdgpu: cp failed to lock ring %d (%d).\n", 463 ring->idx, r); 464 return r; 465 } 466 467 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 468 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 469 } else { 470 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 471 amdgpu_ring_write(ring, scratch - 472 PACKET3_SET_UCONFIG_REG_START); 473 amdgpu_ring_write(ring, 0xDEADBEEF); 474 } 475 amdgpu_ring_commit(ring); 476 477 for (i = 0; i < adev->usec_timeout; i++) { 478 tmp = RREG32(scratch); 479 if (tmp == 0xDEADBEEF) 480 break; 481 if (amdgpu_emu_mode == 1) 482 msleep(1); 483 else 484 udelay(1); 485 } 486 487 if (i >= adev->usec_timeout) 488 r = -ETIMEDOUT; 489 return r; 490 } 491 492 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 struct amdgpu_ib ib; 496 struct dma_fence *f = NULL; 497 unsigned index; 498 uint64_t gpu_addr; 499 volatile uint32_t *cpu_ptr; 500 long r; 501 502 /* MES KIQ fw hasn't indirect buffer support for now */ 503 if (adev->enable_mes_kiq && 504 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 505 return 0; 506 507 memset(&ib, 0, sizeof(ib)); 508 509 r = amdgpu_device_wb_get(adev, &index); 510 if (r) 511 return r; 512 513 gpu_addr = adev->wb.gpu_addr + (index * 4); 514 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 515 cpu_ptr = &adev->wb.wb[index]; 516 517 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 518 if (r) { 519 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 520 goto err1; 521 } 522 523 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 524 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 525 ib.ptr[2] = lower_32_bits(gpu_addr); 526 ib.ptr[3] = upper_32_bits(gpu_addr); 527 ib.ptr[4] = 0xDEADBEEF; 528 ib.length_dw = 5; 529 530 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 531 if (r) 532 goto err2; 533 534 r = dma_fence_wait_timeout(f, false, timeout); 535 if (r == 0) { 536 r = -ETIMEDOUT; 537 goto err2; 538 } else if (r < 0) { 539 goto err2; 540 } 541 542 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 543 r = 0; 544 else 545 r = -EINVAL; 546 err2: 547 amdgpu_ib_free(&ib, NULL); 548 dma_fence_put(f); 549 err1: 550 amdgpu_device_wb_free(adev, index); 551 return r; 552 } 553 554 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 555 { 556 amdgpu_ucode_release(&adev->gfx.pfp_fw); 557 amdgpu_ucode_release(&adev->gfx.me_fw); 558 amdgpu_ucode_release(&adev->gfx.rlc_fw); 559 amdgpu_ucode_release(&adev->gfx.mec_fw); 560 561 kfree(adev->gfx.rlc.register_list_format); 562 } 563 564 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 565 { 566 const struct psp_firmware_header_v1_0 *toc_hdr; 567 int err = 0; 568 569 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_toc.bin", ucode_prefix); 572 if (err) 573 goto out; 574 575 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 576 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 577 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 578 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 579 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 580 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 581 return 0; 582 out: 583 amdgpu_ucode_release(&adev->psp.toc_fw); 584 return err; 585 } 586 587 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int err; 591 const struct rlc_firmware_header_v2_0 *rlc_hdr; 592 uint16_t version_major; 593 uint16_t version_minor; 594 595 DRM_DEBUG("\n"); 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_pfp.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 606 607 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 608 AMDGPU_UCODE_REQUIRED, 609 "amdgpu/%s_me.bin", ucode_prefix); 610 if (err) 611 goto out; 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 614 615 if (!amdgpu_sriov_vf(adev)) { 616 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 617 AMDGPU_UCODE_REQUIRED, 618 "amdgpu/%s_rlc.bin", ucode_prefix); 619 if (err) 620 goto out; 621 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 622 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 623 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 624 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 625 if (err) 626 goto out; 627 } 628 629 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_mec.bin", ucode_prefix); 632 if (err) 633 goto out; 634 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 635 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 636 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 637 638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 639 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 640 641 /* only one MEC for gfx 12 */ 642 adev->gfx.mec2_fw = NULL; 643 644 if (adev->gfx.imu.funcs) { 645 if (adev->gfx.imu.funcs->init_microcode) { 646 err = adev->gfx.imu.funcs->init_microcode(adev); 647 if (err) 648 dev_err(adev->dev, "Failed to load imu firmware!\n"); 649 } 650 } 651 652 out: 653 if (err) { 654 amdgpu_ucode_release(&adev->gfx.pfp_fw); 655 amdgpu_ucode_release(&adev->gfx.me_fw); 656 amdgpu_ucode_release(&adev->gfx.rlc_fw); 657 amdgpu_ucode_release(&adev->gfx.mec_fw); 658 } 659 660 return err; 661 } 662 663 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 664 { 665 u32 count = 0; 666 const struct cs_section_def *sect = NULL; 667 const struct cs_extent_def *ext = NULL; 668 669 count += 1; 670 671 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 672 if (sect->id == SECT_CONTEXT) { 673 for (ext = sect->section; ext->extent != NULL; ++ext) 674 count += 2 + ext->reg_count; 675 } else 676 return 0; 677 } 678 679 return count; 680 } 681 682 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 683 volatile u32 *buffer) 684 { 685 u32 count = 0, clustercount = 0, i; 686 const struct cs_section_def *sect = NULL; 687 const struct cs_extent_def *ext = NULL; 688 689 if (adev->gfx.rlc.cs_data == NULL) 690 return; 691 if (buffer == NULL) 692 return; 693 694 count += 1; 695 696 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 697 if (sect->id == SECT_CONTEXT) { 698 for (ext = sect->section; ext->extent != NULL; ++ext) { 699 clustercount++; 700 buffer[count++] = ext->reg_count; 701 buffer[count++] = ext->reg_index; 702 703 for (i = 0; i < ext->reg_count; i++) 704 buffer[count++] = cpu_to_le32(ext->extent[i]); 705 } 706 } else 707 return; 708 } 709 710 buffer[0] = clustercount; 711 } 712 713 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 714 { 715 /* clear state block */ 716 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 717 &adev->gfx.rlc.clear_state_gpu_addr, 718 (void **)&adev->gfx.rlc.cs_ptr); 719 720 /* jump table block */ 721 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 722 &adev->gfx.rlc.cp_table_gpu_addr, 723 (void **)&adev->gfx.rlc.cp_table_ptr); 724 } 725 726 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 727 { 728 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 729 730 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 731 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 732 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 733 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 734 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 735 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 736 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 737 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 738 adev->gfx.rlc.rlcg_reg_access_supported = true; 739 } 740 741 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 742 { 743 const struct cs_section_def *cs_data; 744 int r; 745 746 adev->gfx.rlc.cs_data = gfx12_cs_data; 747 748 cs_data = adev->gfx.rlc.cs_data; 749 750 if (cs_data) { 751 /* init clear state block */ 752 r = amdgpu_gfx_rlc_init_csb(adev); 753 if (r) 754 return r; 755 } 756 757 /* init spm vmid with 0xf */ 758 if (adev->gfx.rlc.funcs->update_spm_vmid) 759 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 760 761 return 0; 762 } 763 764 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 765 { 766 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 767 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 768 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 769 } 770 771 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 772 { 773 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 774 775 amdgpu_gfx_graphics_queue_acquire(adev); 776 } 777 778 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 779 { 780 int r; 781 u32 *hpd; 782 size_t mec_hpd_size; 783 784 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 785 786 /* take ownership of the relevant compute queues */ 787 amdgpu_gfx_compute_queue_acquire(adev); 788 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 789 790 if (mec_hpd_size) { 791 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 792 AMDGPU_GEM_DOMAIN_GTT, 793 &adev->gfx.mec.hpd_eop_obj, 794 &adev->gfx.mec.hpd_eop_gpu_addr, 795 (void **)&hpd); 796 if (r) { 797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 798 gfx_v12_0_mec_fini(adev); 799 return r; 800 } 801 802 memset(hpd, 0, mec_hpd_size); 803 804 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 805 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 806 } 807 808 return 0; 809 } 810 811 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 812 { 813 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 814 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 815 (address << SQ_IND_INDEX__INDEX__SHIFT)); 816 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 817 } 818 819 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 820 uint32_t thread, uint32_t regno, 821 uint32_t num, uint32_t *out) 822 { 823 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 824 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 825 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 826 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 827 (SQ_IND_INDEX__AUTO_INCR_MASK)); 828 while (num--) 829 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 830 } 831 832 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 833 uint32_t xcc_id, 834 uint32_t simd, uint32_t wave, 835 uint32_t *dst, int *no_fields) 836 { 837 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 838 * field when performing a select_se_sh so it should be 839 * zero here */ 840 WARN_ON(simd != 0); 841 842 /* type 4 wave data */ 843 dst[(*no_fields)++] = 4; 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 867 } 868 869 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 870 uint32_t xcc_id, uint32_t simd, 871 uint32_t wave, uint32_t start, 872 uint32_t size, uint32_t *dst) 873 { 874 WARN_ON(simd != 0); 875 876 wave_read_regs( 877 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 878 dst); 879 } 880 881 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t thread, 884 uint32_t start, uint32_t size, 885 uint32_t *dst) 886 { 887 wave_read_regs( 888 adev, wave, thread, 889 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 890 } 891 892 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 893 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 894 { 895 soc24_grbm_select(adev, me, pipe, q, vm); 896 } 897 898 /* all sizes are in bytes */ 899 #define MQD_SHADOW_BASE_SIZE 73728 900 #define MQD_SHADOW_BASE_ALIGNMENT 256 901 #define MQD_FWWORKAREA_SIZE 484 902 #define MQD_FWWORKAREA_ALIGNMENT 256 903 904 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 905 struct amdgpu_gfx_shadow_info *shadow_info) 906 { 907 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 908 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 909 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 910 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 911 } 912 913 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 914 struct amdgpu_gfx_shadow_info *shadow_info, 915 bool skip_check) 916 { 917 if (adev->gfx.cp_gfx_shadow || skip_check) { 918 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 919 return 0; 920 } 921 922 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 923 return -EINVAL; 924 } 925 926 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 927 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 928 .select_se_sh = &gfx_v12_0_select_se_sh, 929 .read_wave_data = &gfx_v12_0_read_wave_data, 930 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 931 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 932 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 933 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 934 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 935 }; 936 937 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 938 { 939 940 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 941 case IP_VERSION(12, 0, 0): 942 case IP_VERSION(12, 0, 1): 943 adev->gfx.config.max_hw_contexts = 8; 944 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 945 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 946 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 947 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 948 break; 949 default: 950 BUG(); 951 break; 952 } 953 954 return 0; 955 } 956 957 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 958 int me, int pipe, int queue) 959 { 960 int r; 961 struct amdgpu_ring *ring; 962 unsigned int irq_type; 963 964 ring = &adev->gfx.gfx_ring[ring_id]; 965 966 ring->me = me; 967 ring->pipe = pipe; 968 ring->queue = queue; 969 970 ring->ring_obj = NULL; 971 ring->use_doorbell = true; 972 973 if (!ring_id) 974 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 975 else 976 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 977 ring->vm_hub = AMDGPU_GFXHUB(0); 978 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 979 980 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 981 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 if (r) 984 return r; 985 return 0; 986 } 987 988 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 989 int mec, int pipe, int queue) 990 { 991 int r; 992 unsigned irq_type; 993 struct amdgpu_ring *ring; 994 unsigned int hw_prio; 995 996 ring = &adev->gfx.compute_ring[ring_id]; 997 998 /* mec0 is me1 */ 999 ring->me = mec + 1; 1000 ring->pipe = pipe; 1001 ring->queue = queue; 1002 1003 ring->ring_obj = NULL; 1004 ring->use_doorbell = true; 1005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1007 + (ring_id * GFX12_MEC_HPD_SIZE); 1008 ring->vm_hub = AMDGPU_GFXHUB(0); 1009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1010 1011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1013 + ring->pipe; 1014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1015 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1017 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1018 hw_prio, NULL); 1019 if (r) 1020 return r; 1021 1022 return 0; 1023 } 1024 1025 static struct { 1026 SOC24_FIRMWARE_ID id; 1027 unsigned int offset; 1028 unsigned int size; 1029 unsigned int size_x16; 1030 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1031 1032 #define RLC_TOC_OFFSET_DWUNIT 8 1033 #define RLC_SIZE_MULTIPLE 1024 1034 #define RLC_TOC_UMF_SIZE_inM 23ULL 1035 #define RLC_TOC_FORMAT_API 165ULL 1036 1037 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1038 { 1039 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1040 1041 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1042 rlc_autoload_info[ucode->id].id = ucode->id; 1043 rlc_autoload_info[ucode->id].offset = 1044 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1045 rlc_autoload_info[ucode->id].size = 1046 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1047 ucode->size * 4; 1048 ucode++; 1049 } 1050 } 1051 1052 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1053 { 1054 uint32_t total_size = 0; 1055 SOC24_FIRMWARE_ID id; 1056 1057 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1058 1059 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1060 total_size += rlc_autoload_info[id].size; 1061 1062 /* In case the offset in rlc toc ucode is aligned */ 1063 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1064 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1065 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1066 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1067 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1068 1069 return total_size; 1070 } 1071 1072 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1073 { 1074 int r; 1075 uint32_t total_size; 1076 1077 total_size = gfx_v12_0_calc_toc_total_size(adev); 1078 1079 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1080 AMDGPU_GEM_DOMAIN_VRAM, 1081 &adev->gfx.rlc.rlc_autoload_bo, 1082 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1083 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1084 1085 if (r) { 1086 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1087 return r; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1094 SOC24_FIRMWARE_ID id, 1095 const void *fw_data, 1096 uint32_t fw_size) 1097 { 1098 uint32_t toc_offset; 1099 uint32_t toc_fw_size; 1100 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1101 1102 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1103 return; 1104 1105 toc_offset = rlc_autoload_info[id].offset; 1106 toc_fw_size = rlc_autoload_info[id].size; 1107 1108 if (fw_size == 0) 1109 fw_size = toc_fw_size; 1110 1111 if (fw_size > toc_fw_size) 1112 fw_size = toc_fw_size; 1113 1114 memcpy(ptr + toc_offset, fw_data, fw_size); 1115 1116 if (fw_size < toc_fw_size) 1117 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1118 } 1119 1120 static void 1121 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1122 { 1123 void *data; 1124 uint32_t size; 1125 uint32_t *toc_ptr; 1126 1127 data = adev->psp.toc.start_addr; 1128 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1129 1130 toc_ptr = (uint32_t *)data + size / 4 - 2; 1131 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1132 1133 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1134 data, size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1139 { 1140 const __le32 *fw_data; 1141 uint32_t fw_size; 1142 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1143 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1144 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1145 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1146 uint16_t version_major, version_minor; 1147 1148 /* pfp ucode */ 1149 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1150 adev->gfx.pfp_fw->data; 1151 /* instruction */ 1152 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1153 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1154 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1155 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1156 fw_data, fw_size); 1157 /* data */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1162 fw_data, fw_size); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1164 fw_data, fw_size); 1165 /* me ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.me_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1181 fw_data, fw_size); 1182 /* mec ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.mec_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1198 fw_data, fw_size); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1200 fw_data, fw_size); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1202 fw_data, fw_size); 1203 1204 /* rlc ucode */ 1205 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1206 adev->gfx.rlc_fw->data; 1207 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1208 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1209 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1210 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1211 fw_data, fw_size); 1212 1213 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1214 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1215 if (version_major == 2) { 1216 if (version_minor >= 1) { 1217 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1218 1219 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1220 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1221 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1222 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1223 fw_data, fw_size); 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1229 fw_data, fw_size); 1230 } 1231 if (version_minor >= 2) { 1232 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1233 1234 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1235 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1236 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1238 fw_data, fw_size); 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1244 fw_data, fw_size); 1245 } 1246 } 1247 } 1248 1249 static void 1250 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1251 { 1252 const __le32 *fw_data; 1253 uint32_t fw_size; 1254 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1255 1256 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1257 adev->sdma.instance[0].fw->data; 1258 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1259 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1260 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1261 1262 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1263 fw_data, fw_size); 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 unsigned fw_size; 1271 const struct mes_firmware_header_v1_0 *mes_hdr; 1272 int pipe, ucode_id, data_id; 1273 1274 for (pipe = 0; pipe < 2; pipe++) { 1275 if (pipe == 0) { 1276 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1277 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1278 } else { 1279 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1280 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1281 } 1282 1283 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1284 adev->mes.fw[pipe]->data; 1285 1286 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1287 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1288 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1289 1290 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1297 } 1298 } 1299 1300 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1301 { 1302 uint32_t rlc_g_offset, rlc_g_size; 1303 uint64_t gpu_addr; 1304 uint32_t data; 1305 1306 /* RLC autoload sequence 2: copy ucode */ 1307 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1308 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1309 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1310 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1311 1312 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1313 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1314 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1315 1316 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1317 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1318 1319 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1320 1321 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1322 /* RLC autoload sequence 3: load IMU fw */ 1323 if (adev->gfx.imu.funcs->load_microcode) 1324 adev->gfx.imu.funcs->load_microcode(adev); 1325 /* RLC autoload sequence 4 init IMU fw */ 1326 if (adev->gfx.imu.funcs->setup_imu) 1327 adev->gfx.imu.funcs->setup_imu(adev); 1328 if (adev->gfx.imu.funcs->start_imu) 1329 adev->gfx.imu.funcs->start_imu(adev); 1330 1331 /* RLC autoload sequence 5 disable gpa mode */ 1332 gfx_v12_0_disable_gpa_mode(adev); 1333 } else { 1334 /* unhalt rlc to start autoload without imu */ 1335 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1336 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1337 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1338 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1339 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1346 { 1347 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1348 uint32_t *ptr; 1349 uint32_t inst; 1350 1351 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1352 if (!ptr) { 1353 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1354 adev->gfx.ip_dump_core = NULL; 1355 } else { 1356 adev->gfx.ip_dump_core = ptr; 1357 } 1358 1359 /* Allocate memory for compute queue registers for all the instances */ 1360 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1361 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe; 1363 1364 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1365 if (!ptr) { 1366 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1367 adev->gfx.ip_dump_compute_queues = NULL; 1368 } else { 1369 adev->gfx.ip_dump_compute_queues = ptr; 1370 } 1371 1372 /* Allocate memory for gfx queue registers for all the instances */ 1373 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1374 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1375 adev->gfx.me.num_queue_per_pipe; 1376 1377 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1378 if (!ptr) { 1379 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1380 adev->gfx.ip_dump_gfx_queues = NULL; 1381 } else { 1382 adev->gfx.ip_dump_gfx_queues = ptr; 1383 } 1384 } 1385 1386 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1387 { 1388 int i, j, k, r, ring_id = 0; 1389 unsigned num_compute_rings; 1390 int xcc_id = 0; 1391 struct amdgpu_device *adev = ip_block->adev; 1392 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1393 1394 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1395 1396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1397 case IP_VERSION(12, 0, 0): 1398 case IP_VERSION(12, 0, 1): 1399 adev->gfx.me.num_me = 1; 1400 adev->gfx.me.num_pipe_per_me = 1; 1401 adev->gfx.me.num_queue_per_pipe = 8; 1402 adev->gfx.mec.num_mec = 1; 1403 adev->gfx.mec.num_pipe_per_mec = 2; 1404 adev->gfx.mec.num_queue_per_pipe = 4; 1405 break; 1406 default: 1407 adev->gfx.me.num_me = 1; 1408 adev->gfx.me.num_pipe_per_me = 1; 1409 adev->gfx.me.num_queue_per_pipe = 1; 1410 adev->gfx.mec.num_mec = 1; 1411 adev->gfx.mec.num_pipe_per_mec = 4; 1412 adev->gfx.mec.num_queue_per_pipe = 8; 1413 break; 1414 } 1415 1416 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1417 case IP_VERSION(12, 0, 0): 1418 case IP_VERSION(12, 0, 1): 1419 if (!adev->gfx.disable_uq && 1420 adev->gfx.me_fw_version >= 2780 && 1421 adev->gfx.pfp_fw_version >= 2840 && 1422 adev->gfx.mec_fw_version >= 3050 && 1423 adev->mes.fw_version[0] >= 123) { 1424 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1425 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1426 } 1427 break; 1428 default: 1429 break; 1430 } 1431 1432 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1433 case IP_VERSION(12, 0, 0): 1434 case IP_VERSION(12, 0, 1): 1435 if (adev->gfx.me_fw_version >= 2480 && 1436 adev->gfx.pfp_fw_version >= 2530 && 1437 adev->gfx.mec_fw_version >= 2680 && 1438 adev->mes.fw_version[0] >= 100) 1439 adev->gfx.enable_cleaner_shader = true; 1440 break; 1441 default: 1442 adev->gfx.enable_cleaner_shader = false; 1443 break; 1444 } 1445 1446 if (adev->gfx.num_compute_rings) { 1447 /* recalculate compute rings to use based on hardware configuration */ 1448 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1449 adev->gfx.mec.num_queue_per_pipe) / 2; 1450 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1451 num_compute_rings); 1452 } 1453 1454 /* EOP Event */ 1455 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1456 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1457 &adev->gfx.eop_irq); 1458 if (r) 1459 return r; 1460 1461 /* Bad opcode Event */ 1462 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1463 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1464 &adev->gfx.bad_op_irq); 1465 if (r) 1466 return r; 1467 1468 /* Privileged reg */ 1469 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1470 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1471 &adev->gfx.priv_reg_irq); 1472 if (r) 1473 return r; 1474 1475 /* Privileged inst */ 1476 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1477 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1478 &adev->gfx.priv_inst_irq); 1479 if (r) 1480 return r; 1481 1482 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1483 1484 gfx_v12_0_me_init(adev); 1485 1486 r = gfx_v12_0_rlc_init(adev); 1487 if (r) { 1488 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1489 return r; 1490 } 1491 1492 r = gfx_v12_0_mec_init(adev); 1493 if (r) { 1494 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1495 return r; 1496 } 1497 1498 if (adev->gfx.num_gfx_rings) { 1499 /* set up the gfx ring */ 1500 for (i = 0; i < adev->gfx.me.num_me; i++) { 1501 for (j = 0; j < num_queue_per_pipe; j++) { 1502 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1503 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1504 continue; 1505 1506 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1507 i, k, j); 1508 if (r) 1509 return r; 1510 ring_id++; 1511 } 1512 } 1513 } 1514 } 1515 1516 if (adev->gfx.num_compute_rings) { 1517 ring_id = 0; 1518 /* set up the compute queues - allocate horizontally across pipes */ 1519 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1520 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1521 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1522 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1523 0, i, k, j)) 1524 continue; 1525 1526 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1527 i, k, j); 1528 if (r) 1529 return r; 1530 1531 ring_id++; 1532 } 1533 } 1534 } 1535 } 1536 1537 adev->gfx.gfx_supported_reset = 1538 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1539 adev->gfx.compute_supported_reset = 1540 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1541 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1542 case IP_VERSION(12, 0, 0): 1543 case IP_VERSION(12, 0, 1): 1544 if ((adev->gfx.me_fw_version >= 2660) && 1545 (adev->gfx.mec_fw_version >= 2920) && 1546 !amdgpu_sriov_vf(adev)) { 1547 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1548 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1549 } 1550 break; 1551 default: 1552 break; 1553 } 1554 1555 if (!adev->enable_mes_kiq) { 1556 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1557 if (r) { 1558 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1559 return r; 1560 } 1561 1562 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1563 if (r) 1564 return r; 1565 } 1566 1567 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1568 if (r) 1569 return r; 1570 1571 /* allocate visible FB for rlc auto-loading fw */ 1572 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1573 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1574 if (r) 1575 return r; 1576 } 1577 1578 r = gfx_v12_0_gpu_early_init(adev); 1579 if (r) 1580 return r; 1581 1582 gfx_v12_0_alloc_ip_dump(adev); 1583 1584 r = amdgpu_gfx_sysfs_init(adev); 1585 if (r) 1586 return r; 1587 1588 return 0; 1589 } 1590 1591 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1592 { 1593 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1594 &adev->gfx.pfp.pfp_fw_gpu_addr, 1595 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1596 1597 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1598 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1599 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1600 } 1601 1602 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1603 { 1604 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1605 &adev->gfx.me.me_fw_gpu_addr, 1606 (void **)&adev->gfx.me.me_fw_ptr); 1607 1608 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1609 &adev->gfx.me.me_fw_data_gpu_addr, 1610 (void **)&adev->gfx.me.me_fw_data_ptr); 1611 } 1612 1613 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1614 { 1615 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1616 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1617 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1618 } 1619 1620 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1621 { 1622 int i; 1623 struct amdgpu_device *adev = ip_block->adev; 1624 1625 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1626 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1627 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1628 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1629 1630 amdgpu_gfx_mqd_sw_fini(adev, 0); 1631 1632 if (!adev->enable_mes_kiq) { 1633 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1634 amdgpu_gfx_kiq_fini(adev, 0); 1635 } 1636 1637 gfx_v12_0_pfp_fini(adev); 1638 gfx_v12_0_me_fini(adev); 1639 gfx_v12_0_rlc_fini(adev); 1640 gfx_v12_0_mec_fini(adev); 1641 1642 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1643 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1644 1645 gfx_v12_0_free_microcode(adev); 1646 1647 amdgpu_gfx_sysfs_fini(adev); 1648 1649 kfree(adev->gfx.ip_dump_core); 1650 kfree(adev->gfx.ip_dump_compute_queues); 1651 kfree(adev->gfx.ip_dump_gfx_queues); 1652 1653 return 0; 1654 } 1655 1656 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1657 u32 sh_num, u32 instance, int xcc_id) 1658 { 1659 u32 data; 1660 1661 if (instance == 0xffffffff) 1662 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1663 INSTANCE_BROADCAST_WRITES, 1); 1664 else 1665 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1666 instance); 1667 1668 if (se_num == 0xffffffff) 1669 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1670 1); 1671 else 1672 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1673 1674 if (sh_num == 0xffffffff) 1675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1676 1); 1677 else 1678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1679 1680 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1681 } 1682 1683 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1684 { 1685 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1686 1687 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1688 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1689 GRBM_CC_GC_SA_UNIT_DISABLE, 1690 SA_DISABLE); 1691 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1692 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1693 GRBM_GC_USER_SA_UNIT_DISABLE, 1694 SA_DISABLE); 1695 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1696 adev->gfx.config.max_shader_engines); 1697 1698 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1699 } 1700 1701 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1702 { 1703 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1704 u32 rb_mask; 1705 1706 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1707 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1708 CC_RB_BACKEND_DISABLE, 1709 BACKEND_DISABLE); 1710 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1711 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1712 GC_USER_RB_BACKEND_DISABLE, 1713 BACKEND_DISABLE); 1714 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1715 adev->gfx.config.max_shader_engines); 1716 1717 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1718 } 1719 1720 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1721 { 1722 u32 rb_bitmap_per_sa; 1723 u32 rb_bitmap_width_per_sa; 1724 u32 max_sa; 1725 u32 active_sa_bitmap; 1726 u32 global_active_rb_bitmap; 1727 u32 active_rb_bitmap = 0; 1728 u32 i; 1729 1730 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1731 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1732 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1733 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1734 1735 /* generate active rb bitmap according to active sa bitmap */ 1736 max_sa = adev->gfx.config.max_shader_engines * 1737 adev->gfx.config.max_sh_per_se; 1738 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1739 adev->gfx.config.max_sh_per_se; 1740 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1741 1742 for (i = 0; i < max_sa; i++) { 1743 if (active_sa_bitmap & (1 << i)) 1744 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1745 } 1746 1747 active_rb_bitmap &= global_active_rb_bitmap; 1748 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1749 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1750 } 1751 1752 #define LDS_APP_BASE 0x1 1753 #define SCRATCH_APP_BASE 0x2 1754 1755 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1756 { 1757 int i; 1758 uint32_t sh_mem_bases; 1759 uint32_t data; 1760 1761 /* 1762 * Configure apertures: 1763 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1764 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1765 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1766 */ 1767 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1768 SCRATCH_APP_BASE; 1769 1770 mutex_lock(&adev->srbm_mutex); 1771 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1772 soc24_grbm_select(adev, 0, 0, 0, i); 1773 /* CP and shaders */ 1774 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1775 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1776 1777 /* Enable trap for each kfd vmid. */ 1778 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1779 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1780 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1781 } 1782 soc24_grbm_select(adev, 0, 0, 0, 0); 1783 mutex_unlock(&adev->srbm_mutex); 1784 } 1785 1786 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1787 { 1788 /* TODO: harvest feature to be added later. */ 1789 } 1790 1791 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1792 { 1793 } 1794 1795 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1796 { 1797 u32 tmp; 1798 int i; 1799 1800 if (!amdgpu_sriov_vf(adev)) 1801 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1802 1803 gfx_v12_0_setup_rb(adev); 1804 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1805 gfx_v12_0_get_tcc_info(adev); 1806 adev->gfx.config.pa_sc_tile_steering_override = 0; 1807 1808 /* XXX SH_MEM regs */ 1809 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1810 mutex_lock(&adev->srbm_mutex); 1811 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1812 soc24_grbm_select(adev, 0, 0, 0, i); 1813 /* CP and shaders */ 1814 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1815 if (i != 0) { 1816 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1817 (adev->gmc.private_aperture_start >> 48)); 1818 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1819 (adev->gmc.shared_aperture_start >> 48)); 1820 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1821 } 1822 } 1823 soc24_grbm_select(adev, 0, 0, 0, 0); 1824 1825 mutex_unlock(&adev->srbm_mutex); 1826 1827 gfx_v12_0_init_compute_vmid(adev); 1828 } 1829 1830 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1831 int me, int pipe) 1832 { 1833 if (me != 0) 1834 return 0; 1835 1836 switch (pipe) { 1837 case 0: 1838 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1839 default: 1840 return 0; 1841 } 1842 } 1843 1844 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1845 int me, int pipe) 1846 { 1847 /* 1848 * amdgpu controls only the first MEC. That's why this function only 1849 * handles the setting of interrupts for this specific MEC. All other 1850 * pipes' interrupts are set by amdkfd. 1851 */ 1852 if (me != 1) 1853 return 0; 1854 1855 switch (pipe) { 1856 case 0: 1857 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1858 case 1: 1859 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1860 default: 1861 return 0; 1862 } 1863 } 1864 1865 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1866 bool enable) 1867 { 1868 u32 tmp, cp_int_cntl_reg; 1869 int i, j; 1870 1871 if (amdgpu_sriov_vf(adev)) 1872 return; 1873 1874 for (i = 0; i < adev->gfx.me.num_me; i++) { 1875 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1876 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1877 1878 if (cp_int_cntl_reg) { 1879 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1880 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1881 enable ? 1 : 0); 1882 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1883 enable ? 1 : 0); 1884 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1885 enable ? 1 : 0); 1886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1887 enable ? 1 : 0); 1888 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1889 } 1890 } 1891 } 1892 } 1893 1894 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1895 { 1896 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1897 1898 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1899 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1900 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1901 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1902 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1903 1904 return 0; 1905 } 1906 1907 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1908 { 1909 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1910 1911 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1912 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1913 } 1914 1915 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1916 { 1917 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1918 udelay(50); 1919 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1920 udelay(50); 1921 } 1922 1923 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1924 bool enable) 1925 { 1926 uint32_t rlc_pg_cntl; 1927 1928 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1929 1930 if (!enable) { 1931 /* RLC_PG_CNTL[23] = 0 (default) 1932 * RLC will wait for handshake acks with SMU 1933 * GFXOFF will be enabled 1934 * RLC_PG_CNTL[23] = 1 1935 * RLC will not issue any message to SMU 1936 * hence no handshake between SMU & RLC 1937 * GFXOFF will be disabled 1938 */ 1939 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1940 } else 1941 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1942 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1943 } 1944 1945 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1946 { 1947 /* TODO: enable rlc & smu handshake until smu 1948 * and gfxoff feature works as expected */ 1949 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1950 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1951 1952 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1953 udelay(50); 1954 } 1955 1956 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1957 { 1958 uint32_t tmp; 1959 1960 /* enable Save Restore Machine */ 1961 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1962 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1963 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1964 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1965 } 1966 1967 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1968 { 1969 const struct rlc_firmware_header_v2_0 *hdr; 1970 const __le32 *fw_data; 1971 unsigned i, fw_size; 1972 1973 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1974 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1975 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1976 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1977 1978 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1979 RLCG_UCODE_LOADING_START_ADDRESS); 1980 1981 for (i = 0; i < fw_size; i++) 1982 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1983 le32_to_cpup(fw_data++)); 1984 1985 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1986 } 1987 1988 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1989 { 1990 const struct rlc_firmware_header_v2_2 *hdr; 1991 const __le32 *fw_data; 1992 unsigned i, fw_size; 1993 u32 tmp; 1994 1995 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1996 1997 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1998 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1999 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2000 2001 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2002 2003 for (i = 0; i < fw_size; i++) { 2004 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2005 msleep(1); 2006 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2007 le32_to_cpup(fw_data++)); 2008 } 2009 2010 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2011 2012 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2013 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2014 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2015 2016 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2017 for (i = 0; i < fw_size; i++) { 2018 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2019 msleep(1); 2020 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2021 le32_to_cpup(fw_data++)); 2022 } 2023 2024 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2025 2026 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2027 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2028 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2029 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2030 } 2031 2032 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2033 { 2034 const struct rlc_firmware_header_v2_0 *hdr; 2035 uint16_t version_major; 2036 uint16_t version_minor; 2037 2038 if (!adev->gfx.rlc_fw) 2039 return -EINVAL; 2040 2041 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2042 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2043 2044 version_major = le16_to_cpu(hdr->header.header_version_major); 2045 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2046 2047 if (version_major == 2) { 2048 gfx_v12_0_load_rlcg_microcode(adev); 2049 if (amdgpu_dpm == 1) { 2050 if (version_minor >= 2) 2051 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2052 } 2053 2054 return 0; 2055 } 2056 2057 return -EINVAL; 2058 } 2059 2060 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2061 { 2062 int r; 2063 2064 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2065 gfx_v12_0_init_csb(adev); 2066 2067 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2068 gfx_v12_0_rlc_enable_srm(adev); 2069 } else { 2070 if (amdgpu_sriov_vf(adev)) { 2071 gfx_v12_0_init_csb(adev); 2072 return 0; 2073 } 2074 2075 adev->gfx.rlc.funcs->stop(adev); 2076 2077 /* disable CG */ 2078 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2079 2080 /* disable PG */ 2081 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2082 2083 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2084 /* legacy rlc firmware loading */ 2085 r = gfx_v12_0_rlc_load_microcode(adev); 2086 if (r) 2087 return r; 2088 } 2089 2090 gfx_v12_0_init_csb(adev); 2091 2092 adev->gfx.rlc.funcs->start(adev); 2093 } 2094 2095 return 0; 2096 } 2097 2098 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2099 { 2100 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2101 const struct gfx_firmware_header_v2_0 *me_hdr; 2102 const struct gfx_firmware_header_v2_0 *mec_hdr; 2103 uint32_t pipe_id, tmp; 2104 2105 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2106 adev->gfx.mec_fw->data; 2107 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2108 adev->gfx.me_fw->data; 2109 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2110 adev->gfx.pfp_fw->data; 2111 2112 /* config pfp program start addr */ 2113 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2114 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2115 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2116 (pfp_hdr->ucode_start_addr_hi << 30) | 2117 (pfp_hdr->ucode_start_addr_lo >> 2)); 2118 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2119 pfp_hdr->ucode_start_addr_hi >> 2); 2120 } 2121 soc24_grbm_select(adev, 0, 0, 0, 0); 2122 2123 /* reset pfp pipe */ 2124 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2125 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2127 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2128 2129 /* clear pfp pipe reset */ 2130 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2132 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2133 2134 /* config me program start addr */ 2135 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2136 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2137 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2138 (me_hdr->ucode_start_addr_hi << 30) | 2139 (me_hdr->ucode_start_addr_lo >> 2)); 2140 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2141 me_hdr->ucode_start_addr_hi>>2); 2142 } 2143 soc24_grbm_select(adev, 0, 0, 0, 0); 2144 2145 /* reset me pipe */ 2146 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2150 2151 /* clear me pipe reset */ 2152 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2154 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2155 2156 /* config mec program start addr */ 2157 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2158 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2159 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2160 mec_hdr->ucode_start_addr_lo >> 2 | 2161 mec_hdr->ucode_start_addr_hi << 30); 2162 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2163 mec_hdr->ucode_start_addr_hi >> 2); 2164 } 2165 soc24_grbm_select(adev, 0, 0, 0, 0); 2166 2167 /* reset mec pipe */ 2168 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2169 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2170 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2171 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2172 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2173 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2174 2175 /* clear mec pipe reset */ 2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2178 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2179 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2180 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2181 } 2182 2183 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2184 { 2185 const struct gfx_firmware_header_v2_0 *cp_hdr; 2186 unsigned pipe_id, tmp; 2187 2188 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2189 adev->gfx.pfp_fw->data; 2190 mutex_lock(&adev->srbm_mutex); 2191 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2192 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2193 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2194 (cp_hdr->ucode_start_addr_hi << 30) | 2195 (cp_hdr->ucode_start_addr_lo >> 2)); 2196 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2197 cp_hdr->ucode_start_addr_hi>>2); 2198 2199 /* 2200 * Program CP_ME_CNTL to reset given PIPE to take 2201 * effect of CP_PFP_PRGRM_CNTR_START. 2202 */ 2203 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2204 if (pipe_id == 0) 2205 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2206 PFP_PIPE0_RESET, 1); 2207 else 2208 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2209 PFP_PIPE1_RESET, 1); 2210 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2211 2212 /* Clear pfp pipe0 reset bit. */ 2213 if (pipe_id == 0) 2214 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2215 PFP_PIPE0_RESET, 0); 2216 else 2217 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2218 PFP_PIPE1_RESET, 0); 2219 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2220 } 2221 soc24_grbm_select(adev, 0, 0, 0, 0); 2222 mutex_unlock(&adev->srbm_mutex); 2223 } 2224 2225 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2226 { 2227 const struct gfx_firmware_header_v2_0 *cp_hdr; 2228 unsigned pipe_id, tmp; 2229 2230 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2231 adev->gfx.me_fw->data; 2232 mutex_lock(&adev->srbm_mutex); 2233 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2234 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2235 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2236 (cp_hdr->ucode_start_addr_hi << 30) | 2237 (cp_hdr->ucode_start_addr_lo >> 2) ); 2238 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2239 cp_hdr->ucode_start_addr_hi>>2); 2240 2241 /* 2242 * Program CP_ME_CNTL to reset given PIPE to take 2243 * effect of CP_ME_PRGRM_CNTR_START. 2244 */ 2245 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2246 if (pipe_id == 0) 2247 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2248 ME_PIPE0_RESET, 1); 2249 else 2250 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2251 ME_PIPE1_RESET, 1); 2252 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2253 2254 /* Clear pfp pipe0 reset bit. */ 2255 if (pipe_id == 0) 2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2257 ME_PIPE0_RESET, 0); 2258 else 2259 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2260 ME_PIPE1_RESET, 0); 2261 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2262 } 2263 soc24_grbm_select(adev, 0, 0, 0, 0); 2264 mutex_unlock(&adev->srbm_mutex); 2265 } 2266 2267 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2268 { 2269 const struct gfx_firmware_header_v2_0 *cp_hdr; 2270 unsigned pipe_id; 2271 2272 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2273 adev->gfx.mec_fw->data; 2274 mutex_lock(&adev->srbm_mutex); 2275 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2276 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2277 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2278 cp_hdr->ucode_start_addr_lo >> 2 | 2279 cp_hdr->ucode_start_addr_hi << 30); 2280 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2281 cp_hdr->ucode_start_addr_hi >> 2); 2282 } 2283 soc24_grbm_select(adev, 0, 0, 0, 0); 2284 mutex_unlock(&adev->srbm_mutex); 2285 } 2286 2287 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2288 { 2289 uint32_t cp_status; 2290 uint32_t bootload_status; 2291 int i; 2292 2293 for (i = 0; i < adev->usec_timeout; i++) { 2294 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2295 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2296 2297 if ((cp_status == 0) && 2298 (REG_GET_FIELD(bootload_status, 2299 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2300 break; 2301 } 2302 udelay(1); 2303 if (amdgpu_emu_mode) 2304 msleep(10); 2305 } 2306 2307 if (i >= adev->usec_timeout) { 2308 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2309 return -ETIMEDOUT; 2310 } 2311 2312 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2313 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2314 gfx_v12_0_set_me_ucode_start_addr(adev); 2315 gfx_v12_0_set_mec_ucode_start_addr(adev); 2316 } 2317 2318 return 0; 2319 } 2320 2321 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2322 { 2323 int i; 2324 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2325 2326 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2327 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2328 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2329 2330 for (i = 0; i < adev->usec_timeout; i++) { 2331 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2332 break; 2333 udelay(1); 2334 } 2335 2336 if (i >= adev->usec_timeout) 2337 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2338 2339 return 0; 2340 } 2341 2342 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2343 { 2344 int r; 2345 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2346 const __le32 *fw_ucode, *fw_data; 2347 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2348 uint32_t tmp; 2349 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2350 2351 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2352 adev->gfx.pfp_fw->data; 2353 2354 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2355 2356 /* instruction */ 2357 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2358 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2359 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2360 /* data */ 2361 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2362 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2363 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2364 2365 /* 64kb align */ 2366 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2367 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2368 &adev->gfx.pfp.pfp_fw_obj, 2369 &adev->gfx.pfp.pfp_fw_gpu_addr, 2370 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2371 if (r) { 2372 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2373 gfx_v12_0_pfp_fini(adev); 2374 return r; 2375 } 2376 2377 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2378 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2379 &adev->gfx.pfp.pfp_fw_data_obj, 2380 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2381 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2382 if (r) { 2383 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2384 gfx_v12_0_pfp_fini(adev); 2385 return r; 2386 } 2387 2388 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2389 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2390 2391 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2392 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2393 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2394 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2395 2396 if (amdgpu_emu_mode == 1) 2397 amdgpu_device_flush_hdp(adev, NULL); 2398 2399 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2400 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2401 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2402 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2403 2404 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2405 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2406 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2407 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2408 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2409 2410 /* 2411 * Programming any of the CP_PFP_IC_BASE registers 2412 * forces invalidation of the ME L1 I$. Wait for the 2413 * invalidation complete 2414 */ 2415 for (i = 0; i < usec_timeout; i++) { 2416 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2417 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2418 INVALIDATE_CACHE_COMPLETE)) 2419 break; 2420 udelay(1); 2421 } 2422 2423 if (i >= usec_timeout) { 2424 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2425 return -EINVAL; 2426 } 2427 2428 /* Prime the L1 instruction caches */ 2429 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2430 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2431 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2432 /* Waiting for cache primed*/ 2433 for (i = 0; i < usec_timeout; i++) { 2434 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2435 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2436 ICACHE_PRIMED)) 2437 break; 2438 udelay(1); 2439 } 2440 2441 if (i >= usec_timeout) { 2442 dev_err(adev->dev, "failed to prime instruction cache\n"); 2443 return -EINVAL; 2444 } 2445 2446 mutex_lock(&adev->srbm_mutex); 2447 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2448 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2449 2450 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2451 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2452 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2453 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2454 } 2455 soc24_grbm_select(adev, 0, 0, 0, 0); 2456 mutex_unlock(&adev->srbm_mutex); 2457 2458 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2459 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2460 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2461 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2462 2463 /* Invalidate the data caches */ 2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2466 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2467 2468 for (i = 0; i < usec_timeout; i++) { 2469 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2470 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2471 INVALIDATE_DCACHE_COMPLETE)) 2472 break; 2473 udelay(1); 2474 } 2475 2476 if (i >= usec_timeout) { 2477 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2478 return -EINVAL; 2479 } 2480 2481 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2482 2483 return 0; 2484 } 2485 2486 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2487 { 2488 int r; 2489 const struct gfx_firmware_header_v2_0 *me_hdr; 2490 const __le32 *fw_ucode, *fw_data; 2491 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2492 uint32_t tmp; 2493 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2494 2495 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2496 adev->gfx.me_fw->data; 2497 2498 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2499 2500 /* instruction */ 2501 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2502 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2503 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2504 /* data */ 2505 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2506 le32_to_cpu(me_hdr->data_offset_bytes)); 2507 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2508 2509 /* 64kb align*/ 2510 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2511 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2512 &adev->gfx.me.me_fw_obj, 2513 &adev->gfx.me.me_fw_gpu_addr, 2514 (void **)&adev->gfx.me.me_fw_ptr); 2515 if (r) { 2516 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2517 gfx_v12_0_me_fini(adev); 2518 return r; 2519 } 2520 2521 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2522 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2523 &adev->gfx.me.me_fw_data_obj, 2524 &adev->gfx.me.me_fw_data_gpu_addr, 2525 (void **)&adev->gfx.me.me_fw_data_ptr); 2526 if (r) { 2527 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2528 gfx_v12_0_me_fini(adev); 2529 return r; 2530 } 2531 2532 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2533 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2534 2535 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2536 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2537 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2538 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2539 2540 if (amdgpu_emu_mode == 1) 2541 amdgpu_device_flush_hdp(adev, NULL); 2542 2543 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2544 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2545 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2546 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2547 2548 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2549 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2550 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2551 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2552 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2553 2554 /* 2555 * Programming any of the CP_ME_IC_BASE registers 2556 * forces invalidation of the ME L1 I$. Wait for the 2557 * invalidation complete 2558 */ 2559 for (i = 0; i < usec_timeout; i++) { 2560 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2561 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2562 INVALIDATE_CACHE_COMPLETE)) 2563 break; 2564 udelay(1); 2565 } 2566 2567 if (i >= usec_timeout) { 2568 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2569 return -EINVAL; 2570 } 2571 2572 /* Prime the instruction caches */ 2573 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2574 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2575 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2576 2577 /* Waiting for instruction cache primed*/ 2578 for (i = 0; i < usec_timeout; i++) { 2579 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2580 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2581 ICACHE_PRIMED)) 2582 break; 2583 udelay(1); 2584 } 2585 2586 if (i >= usec_timeout) { 2587 dev_err(adev->dev, "failed to prime instruction cache\n"); 2588 return -EINVAL; 2589 } 2590 2591 mutex_lock(&adev->srbm_mutex); 2592 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2593 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2594 2595 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2596 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2597 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2598 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2599 } 2600 soc24_grbm_select(adev, 0, 0, 0, 0); 2601 mutex_unlock(&adev->srbm_mutex); 2602 2603 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2604 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2605 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2607 2608 /* Invalidate the data caches */ 2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2611 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2612 2613 for (i = 0; i < usec_timeout; i++) { 2614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2615 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2616 INVALIDATE_DCACHE_COMPLETE)) 2617 break; 2618 udelay(1); 2619 } 2620 2621 if (i >= usec_timeout) { 2622 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2623 return -EINVAL; 2624 } 2625 2626 gfx_v12_0_set_me_ucode_start_addr(adev); 2627 2628 return 0; 2629 } 2630 2631 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2632 { 2633 int r; 2634 2635 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2636 return -EINVAL; 2637 2638 gfx_v12_0_cp_gfx_enable(adev, false); 2639 2640 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2641 if (r) { 2642 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2643 return r; 2644 } 2645 2646 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2647 if (r) { 2648 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2649 return r; 2650 } 2651 2652 return 0; 2653 } 2654 2655 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2656 { 2657 /* init the CP */ 2658 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2659 adev->gfx.config.max_hw_contexts - 1); 2660 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2661 2662 if (!amdgpu_async_gfx_ring) 2663 gfx_v12_0_cp_gfx_enable(adev, true); 2664 2665 return 0; 2666 } 2667 2668 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2669 CP_PIPE_ID pipe) 2670 { 2671 u32 tmp; 2672 2673 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2674 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2675 2676 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2677 } 2678 2679 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2680 struct amdgpu_ring *ring) 2681 { 2682 u32 tmp; 2683 2684 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2685 if (ring->use_doorbell) { 2686 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2687 DOORBELL_OFFSET, ring->doorbell_index); 2688 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2689 DOORBELL_EN, 1); 2690 } else { 2691 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2692 DOORBELL_EN, 0); 2693 } 2694 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2695 2696 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2697 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2698 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2699 2700 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2701 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2702 } 2703 2704 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2705 { 2706 struct amdgpu_ring *ring; 2707 u32 tmp; 2708 u32 rb_bufsz; 2709 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2710 2711 /* Set the write pointer delay */ 2712 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2713 2714 /* set the RB to use vmid 0 */ 2715 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2716 2717 /* Init gfx ring 0 for pipe 0 */ 2718 mutex_lock(&adev->srbm_mutex); 2719 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2720 2721 /* Set ring buffer size */ 2722 ring = &adev->gfx.gfx_ring[0]; 2723 rb_bufsz = order_base_2(ring->ring_size / 8); 2724 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2725 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2726 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2727 2728 /* Initialize the ring buffer's write pointers */ 2729 ring->wptr = 0; 2730 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2731 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2732 2733 /* set the wb address whether it's enabled or not */ 2734 rptr_addr = ring->rptr_gpu_addr; 2735 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2736 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2737 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2738 2739 wptr_gpu_addr = ring->wptr_gpu_addr; 2740 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2741 lower_32_bits(wptr_gpu_addr)); 2742 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2743 upper_32_bits(wptr_gpu_addr)); 2744 2745 mdelay(1); 2746 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2747 2748 rb_addr = ring->gpu_addr >> 8; 2749 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2750 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2751 2752 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2753 2754 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2755 mutex_unlock(&adev->srbm_mutex); 2756 2757 /* Switch to pipe 0 */ 2758 mutex_lock(&adev->srbm_mutex); 2759 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2760 mutex_unlock(&adev->srbm_mutex); 2761 2762 /* start the ring */ 2763 gfx_v12_0_cp_gfx_start(adev); 2764 return 0; 2765 } 2766 2767 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2768 { 2769 u32 data; 2770 2771 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2772 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2773 enable ? 0 : 1); 2774 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2775 enable ? 0 : 1); 2776 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2777 enable ? 0 : 1); 2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2779 enable ? 0 : 1); 2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2781 enable ? 0 : 1); 2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2783 enable ? 1 : 0); 2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2785 enable ? 1 : 0); 2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2787 enable ? 1 : 0); 2788 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2789 enable ? 1 : 0); 2790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2791 enable ? 0 : 1); 2792 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2793 2794 adev->gfx.kiq[0].ring.sched.ready = enable; 2795 2796 udelay(50); 2797 } 2798 2799 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2800 { 2801 const struct gfx_firmware_header_v2_0 *mec_hdr; 2802 const __le32 *fw_ucode, *fw_data; 2803 u32 tmp, fw_ucode_size, fw_data_size; 2804 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2805 u32 *fw_ucode_ptr, *fw_data_ptr; 2806 int r; 2807 2808 if (!adev->gfx.mec_fw) 2809 return -EINVAL; 2810 2811 gfx_v12_0_cp_compute_enable(adev, false); 2812 2813 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2814 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2815 2816 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2817 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2818 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2819 2820 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2821 le32_to_cpu(mec_hdr->data_offset_bytes)); 2822 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2823 2824 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2825 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2826 &adev->gfx.mec.mec_fw_obj, 2827 &adev->gfx.mec.mec_fw_gpu_addr, 2828 (void **)&fw_ucode_ptr); 2829 if (r) { 2830 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2831 gfx_v12_0_mec_fini(adev); 2832 return r; 2833 } 2834 2835 r = amdgpu_bo_create_reserved(adev, 2836 ALIGN(fw_data_size, 64 * 1024) * 2837 adev->gfx.mec.num_pipe_per_mec, 2838 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2839 &adev->gfx.mec.mec_fw_data_obj, 2840 &adev->gfx.mec.mec_fw_data_gpu_addr, 2841 (void **)&fw_data_ptr); 2842 if (r) { 2843 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2844 gfx_v12_0_mec_fini(adev); 2845 return r; 2846 } 2847 2848 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2849 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2850 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2851 } 2852 2853 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2854 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2855 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2856 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2857 2858 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2859 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2860 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2861 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2862 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2863 2864 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2865 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2866 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2867 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2868 2869 mutex_lock(&adev->srbm_mutex); 2870 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2871 soc24_grbm_select(adev, 1, i, 0, 0); 2872 2873 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2874 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2875 i * ALIGN(fw_data_size, 64 * 1024))); 2876 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2877 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2878 i * ALIGN(fw_data_size, 64 * 1024))); 2879 2880 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2881 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2882 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2883 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2884 } 2885 mutex_unlock(&adev->srbm_mutex); 2886 soc24_grbm_select(adev, 0, 0, 0, 0); 2887 2888 /* Trigger an invalidation of the L1 instruction caches */ 2889 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2890 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2891 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2892 2893 /* Wait for invalidation complete */ 2894 for (i = 0; i < usec_timeout; i++) { 2895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2896 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2897 INVALIDATE_DCACHE_COMPLETE)) 2898 break; 2899 udelay(1); 2900 } 2901 2902 if (i >= usec_timeout) { 2903 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2904 return -EINVAL; 2905 } 2906 2907 /* Trigger an invalidation of the L1 instruction caches */ 2908 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2909 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2910 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2911 2912 /* Wait for invalidation complete */ 2913 for (i = 0; i < usec_timeout; i++) { 2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2915 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2916 INVALIDATE_CACHE_COMPLETE)) 2917 break; 2918 udelay(1); 2919 } 2920 2921 if (i >= usec_timeout) { 2922 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2923 return -EINVAL; 2924 } 2925 2926 gfx_v12_0_set_mec_ucode_start_addr(adev); 2927 2928 return 0; 2929 } 2930 2931 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2932 { 2933 uint32_t tmp; 2934 struct amdgpu_device *adev = ring->adev; 2935 2936 /* tell RLC which is KIQ queue */ 2937 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2938 tmp &= 0xffffff00; 2939 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2940 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2941 } 2942 2943 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2944 { 2945 /* set graphics engine doorbell range */ 2946 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2947 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2948 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2949 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2950 2951 /* set compute engine doorbell range */ 2952 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2953 (adev->doorbell_index.kiq * 2) << 2); 2954 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2955 (adev->doorbell_index.userqueue_end * 2) << 2); 2956 } 2957 2958 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2959 struct amdgpu_mqd_prop *prop) 2960 { 2961 struct v12_gfx_mqd *mqd = m; 2962 uint64_t hqd_gpu_addr, wb_gpu_addr; 2963 uint32_t tmp; 2964 uint32_t rb_bufsz; 2965 2966 /* set up gfx hqd wptr */ 2967 mqd->cp_gfx_hqd_wptr = 0; 2968 mqd->cp_gfx_hqd_wptr_hi = 0; 2969 2970 /* set the pointer to the MQD */ 2971 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2972 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2973 2974 /* set up mqd control */ 2975 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2976 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2977 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2978 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2979 mqd->cp_gfx_mqd_control = tmp; 2980 2981 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2982 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2983 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2984 mqd->cp_gfx_hqd_vmid = 0; 2985 2986 /* set up default queue priority level 2987 * 0x0 = low priority, 0x1 = high priority */ 2988 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2990 mqd->cp_gfx_hqd_queue_priority = tmp; 2991 2992 /* set up time quantum */ 2993 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2994 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2995 mqd->cp_gfx_hqd_quantum = tmp; 2996 2997 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2998 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2999 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3000 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3001 3002 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3003 wb_gpu_addr = prop->rptr_gpu_addr; 3004 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3005 mqd->cp_gfx_hqd_rptr_addr_hi = 3006 upper_32_bits(wb_gpu_addr) & 0xffff; 3007 3008 /* set up rb_wptr_poll addr */ 3009 wb_gpu_addr = prop->wptr_gpu_addr; 3010 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3011 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3012 3013 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3014 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3015 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3016 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3017 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3018 #ifdef __BIG_ENDIAN 3019 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3020 #endif 3021 if (prop->tmz_queue) 3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3023 mqd->cp_gfx_hqd_cntl = tmp; 3024 3025 /* set up cp_doorbell_control */ 3026 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3027 if (prop->use_doorbell) { 3028 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3029 DOORBELL_OFFSET, prop->doorbell_index); 3030 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3031 DOORBELL_EN, 1); 3032 } else 3033 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3034 DOORBELL_EN, 0); 3035 mqd->cp_rb_doorbell_control = tmp; 3036 3037 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3038 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3039 3040 /* active the queue */ 3041 mqd->cp_gfx_hqd_active = 1; 3042 3043 /* set gfx UQ items */ 3044 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3045 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3046 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3047 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3048 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3049 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3050 3051 return 0; 3052 } 3053 3054 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3055 { 3056 struct amdgpu_device *adev = ring->adev; 3057 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3058 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3059 3060 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3061 memset((void *)mqd, 0, sizeof(*mqd)); 3062 mutex_lock(&adev->srbm_mutex); 3063 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3064 amdgpu_ring_init_mqd(ring); 3065 soc24_grbm_select(adev, 0, 0, 0, 0); 3066 mutex_unlock(&adev->srbm_mutex); 3067 if (adev->gfx.me.mqd_backup[mqd_idx]) 3068 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3069 } else { 3070 /* restore mqd with the backup copy */ 3071 if (adev->gfx.me.mqd_backup[mqd_idx]) 3072 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3073 /* reset the ring */ 3074 ring->wptr = 0; 3075 *ring->wptr_cpu_addr = 0; 3076 amdgpu_ring_clear_ring(ring); 3077 } 3078 3079 return 0; 3080 } 3081 3082 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3083 { 3084 int i, r; 3085 3086 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3087 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3088 if (r) 3089 return r; 3090 } 3091 3092 r = amdgpu_gfx_enable_kgq(adev, 0); 3093 if (r) 3094 return r; 3095 3096 return gfx_v12_0_cp_gfx_start(adev); 3097 } 3098 3099 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3100 struct amdgpu_mqd_prop *prop) 3101 { 3102 struct v12_compute_mqd *mqd = m; 3103 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3104 uint32_t tmp; 3105 3106 mqd->header = 0xC0310800; 3107 mqd->compute_pipelinestat_enable = 0x00000001; 3108 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3109 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3110 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3111 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3112 mqd->compute_misc_reserved = 0x00000007; 3113 3114 eop_base_addr = prop->eop_gpu_addr >> 8; 3115 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3116 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3117 3118 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3119 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3120 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3121 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3122 3123 mqd->cp_hqd_eop_control = tmp; 3124 3125 /* enable doorbell? */ 3126 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3127 3128 if (prop->use_doorbell) { 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3130 DOORBELL_OFFSET, prop->doorbell_index); 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_EN, 1); 3133 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3134 DOORBELL_SOURCE, 0); 3135 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3136 DOORBELL_HIT, 0); 3137 } else { 3138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3139 DOORBELL_EN, 0); 3140 } 3141 3142 mqd->cp_hqd_pq_doorbell_control = tmp; 3143 3144 /* disable the queue if it's active */ 3145 mqd->cp_hqd_dequeue_request = 0; 3146 mqd->cp_hqd_pq_rptr = 0; 3147 mqd->cp_hqd_pq_wptr_lo = 0; 3148 mqd->cp_hqd_pq_wptr_hi = 0; 3149 3150 /* set the pointer to the MQD */ 3151 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3152 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3153 3154 /* set MQD vmid to 0 */ 3155 tmp = regCP_MQD_CONTROL_DEFAULT; 3156 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3157 mqd->cp_mqd_control = tmp; 3158 3159 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3160 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3161 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3162 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3163 3164 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3165 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3167 (order_base_2(prop->queue_size / 4) - 1)); 3168 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3169 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3170 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3171 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3173 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3174 if (prop->tmz_queue) 3175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3176 mqd->cp_hqd_pq_control = tmp; 3177 3178 /* set the wb address whether it's enabled or not */ 3179 wb_gpu_addr = prop->rptr_gpu_addr; 3180 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3181 mqd->cp_hqd_pq_rptr_report_addr_hi = 3182 upper_32_bits(wb_gpu_addr) & 0xffff; 3183 3184 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3185 wb_gpu_addr = prop->wptr_gpu_addr; 3186 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3187 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3188 3189 tmp = 0; 3190 /* enable the doorbell if requested */ 3191 if (prop->use_doorbell) { 3192 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3193 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3194 DOORBELL_OFFSET, prop->doorbell_index); 3195 3196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3197 DOORBELL_EN, 1); 3198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3199 DOORBELL_SOURCE, 0); 3200 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3201 DOORBELL_HIT, 0); 3202 } 3203 3204 mqd->cp_hqd_pq_doorbell_control = tmp; 3205 3206 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3207 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3208 3209 /* set the vmid for the queue */ 3210 mqd->cp_hqd_vmid = 0; 3211 3212 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3213 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3214 mqd->cp_hqd_persistent_state = tmp; 3215 3216 /* set MIN_IB_AVAIL_SIZE */ 3217 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3218 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3219 mqd->cp_hqd_ib_control = tmp; 3220 3221 /* set static priority for a compute queue/ring */ 3222 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3223 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3224 3225 mqd->cp_hqd_active = prop->hqd_active; 3226 3227 /* set UQ fenceaddress */ 3228 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3229 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3230 3231 return 0; 3232 } 3233 3234 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3235 { 3236 struct amdgpu_device *adev = ring->adev; 3237 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3238 int j; 3239 3240 /* inactivate the queue */ 3241 if (amdgpu_sriov_vf(adev)) 3242 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3243 3244 /* disable wptr polling */ 3245 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3246 3247 /* write the EOP addr */ 3248 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3249 mqd->cp_hqd_eop_base_addr_lo); 3250 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3251 mqd->cp_hqd_eop_base_addr_hi); 3252 3253 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3254 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3255 mqd->cp_hqd_eop_control); 3256 3257 /* enable doorbell? */ 3258 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3259 mqd->cp_hqd_pq_doorbell_control); 3260 3261 /* disable the queue if it's active */ 3262 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3263 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3264 for (j = 0; j < adev->usec_timeout; j++) { 3265 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3266 break; 3267 udelay(1); 3268 } 3269 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3270 mqd->cp_hqd_dequeue_request); 3271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3272 mqd->cp_hqd_pq_rptr); 3273 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3274 mqd->cp_hqd_pq_wptr_lo); 3275 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3276 mqd->cp_hqd_pq_wptr_hi); 3277 } 3278 3279 /* set the pointer to the MQD */ 3280 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3281 mqd->cp_mqd_base_addr_lo); 3282 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3283 mqd->cp_mqd_base_addr_hi); 3284 3285 /* set MQD vmid to 0 */ 3286 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3287 mqd->cp_mqd_control); 3288 3289 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3290 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3291 mqd->cp_hqd_pq_base_lo); 3292 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3293 mqd->cp_hqd_pq_base_hi); 3294 3295 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3297 mqd->cp_hqd_pq_control); 3298 3299 /* set the wb address whether it's enabled or not */ 3300 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3301 mqd->cp_hqd_pq_rptr_report_addr_lo); 3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3303 mqd->cp_hqd_pq_rptr_report_addr_hi); 3304 3305 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3307 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3308 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3309 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3310 3311 /* enable the doorbell if requested */ 3312 if (ring->use_doorbell) { 3313 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3314 (adev->doorbell_index.kiq * 2) << 2); 3315 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3316 (adev->doorbell_index.userqueue_end * 2) << 2); 3317 } 3318 3319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3320 mqd->cp_hqd_pq_doorbell_control); 3321 3322 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3323 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3324 mqd->cp_hqd_pq_wptr_lo); 3325 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3326 mqd->cp_hqd_pq_wptr_hi); 3327 3328 /* set the vmid for the queue */ 3329 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3330 3331 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3332 mqd->cp_hqd_persistent_state); 3333 3334 /* activate the queue */ 3335 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3336 mqd->cp_hqd_active); 3337 3338 if (ring->use_doorbell) 3339 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3340 3341 return 0; 3342 } 3343 3344 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3345 { 3346 struct amdgpu_device *adev = ring->adev; 3347 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3348 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3349 3350 gfx_v12_0_kiq_setting(ring); 3351 3352 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3353 /* reset MQD to a clean status */ 3354 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3355 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3356 3357 /* reset ring buffer */ 3358 ring->wptr = 0; 3359 amdgpu_ring_clear_ring(ring); 3360 3361 mutex_lock(&adev->srbm_mutex); 3362 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3363 gfx_v12_0_kiq_init_register(ring); 3364 soc24_grbm_select(adev, 0, 0, 0, 0); 3365 mutex_unlock(&adev->srbm_mutex); 3366 } else { 3367 memset((void *)mqd, 0, sizeof(*mqd)); 3368 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3369 amdgpu_ring_clear_ring(ring); 3370 mutex_lock(&adev->srbm_mutex); 3371 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3372 amdgpu_ring_init_mqd(ring); 3373 gfx_v12_0_kiq_init_register(ring); 3374 soc24_grbm_select(adev, 0, 0, 0, 0); 3375 mutex_unlock(&adev->srbm_mutex); 3376 3377 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3378 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3379 } 3380 3381 return 0; 3382 } 3383 3384 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3385 { 3386 struct amdgpu_device *adev = ring->adev; 3387 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3388 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3389 3390 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3391 memset((void *)mqd, 0, sizeof(*mqd)); 3392 mutex_lock(&adev->srbm_mutex); 3393 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3394 amdgpu_ring_init_mqd(ring); 3395 soc24_grbm_select(adev, 0, 0, 0, 0); 3396 mutex_unlock(&adev->srbm_mutex); 3397 3398 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3399 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3400 } else { 3401 /* restore MQD to a clean status */ 3402 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3403 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3404 /* reset ring buffer */ 3405 ring->wptr = 0; 3406 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3407 amdgpu_ring_clear_ring(ring); 3408 } 3409 3410 return 0; 3411 } 3412 3413 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3414 { 3415 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3416 adev->gfx.kiq[0].ring.sched.ready = true; 3417 return 0; 3418 } 3419 3420 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3421 { 3422 int i, r; 3423 3424 if (!amdgpu_async_gfx_ring) 3425 gfx_v12_0_cp_compute_enable(adev, true); 3426 3427 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3428 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3429 if (r) 3430 return r; 3431 } 3432 3433 return amdgpu_gfx_enable_kcq(adev, 0); 3434 } 3435 3436 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3437 { 3438 int r, i; 3439 struct amdgpu_ring *ring; 3440 3441 if (!(adev->flags & AMD_IS_APU)) 3442 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3443 3444 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3445 /* legacy firmware loading */ 3446 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3447 if (r) 3448 return r; 3449 3450 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3451 if (r) 3452 return r; 3453 } 3454 3455 gfx_v12_0_cp_set_doorbell_range(adev); 3456 3457 if (amdgpu_async_gfx_ring) { 3458 gfx_v12_0_cp_compute_enable(adev, true); 3459 gfx_v12_0_cp_gfx_enable(adev, true); 3460 } 3461 3462 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3463 r = amdgpu_mes_kiq_hw_init(adev); 3464 else 3465 r = gfx_v12_0_kiq_resume(adev); 3466 if (r) 3467 return r; 3468 3469 r = gfx_v12_0_kcq_resume(adev); 3470 if (r) 3471 return r; 3472 3473 if (!amdgpu_async_gfx_ring) { 3474 r = gfx_v12_0_cp_gfx_resume(adev); 3475 if (r) 3476 return r; 3477 } else { 3478 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3479 if (r) 3480 return r; 3481 } 3482 3483 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3484 ring = &adev->gfx.gfx_ring[i]; 3485 r = amdgpu_ring_test_helper(ring); 3486 if (r) 3487 return r; 3488 } 3489 3490 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3491 ring = &adev->gfx.compute_ring[i]; 3492 r = amdgpu_ring_test_helper(ring); 3493 if (r) 3494 return r; 3495 } 3496 3497 return 0; 3498 } 3499 3500 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3501 { 3502 gfx_v12_0_cp_gfx_enable(adev, enable); 3503 gfx_v12_0_cp_compute_enable(adev, enable); 3504 } 3505 3506 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3507 { 3508 int r; 3509 bool value; 3510 3511 r = adev->gfxhub.funcs->gart_enable(adev); 3512 if (r) 3513 return r; 3514 3515 amdgpu_device_flush_hdp(adev, NULL); 3516 3517 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3518 false : true; 3519 3520 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3521 /* TODO investigate why this and the hdp flush above is needed, 3522 * are we missing a flush somewhere else? */ 3523 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3524 3525 return 0; 3526 } 3527 3528 static int get_gb_addr_config(struct amdgpu_device *adev) 3529 { 3530 u32 gb_addr_config; 3531 3532 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3533 if (gb_addr_config == 0) 3534 return -EINVAL; 3535 3536 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3537 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3538 3539 adev->gfx.config.gb_addr_config = gb_addr_config; 3540 3541 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3542 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3543 GB_ADDR_CONFIG, NUM_PIPES); 3544 3545 adev->gfx.config.max_tile_pipes = 3546 adev->gfx.config.gb_addr_config_fields.num_pipes; 3547 3548 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3549 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3550 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3551 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3552 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3553 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3554 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3555 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3556 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3557 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3558 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3559 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3560 3561 return 0; 3562 } 3563 3564 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3565 { 3566 uint32_t data; 3567 3568 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3569 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3570 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3571 3572 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3573 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3574 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3575 } 3576 3577 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3578 { 3579 if (amdgpu_sriov_vf(adev)) 3580 return; 3581 3582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3583 case IP_VERSION(12, 0, 0): 3584 case IP_VERSION(12, 0, 1): 3585 soc15_program_register_sequence(adev, 3586 golden_settings_gc_12_0, 3587 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3588 3589 if (adev->rev_id == 0) 3590 soc15_program_register_sequence(adev, 3591 golden_settings_gc_12_0_rev0, 3592 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3593 break; 3594 default: 3595 break; 3596 } 3597 } 3598 3599 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3600 { 3601 int r; 3602 struct amdgpu_device *adev = ip_block->adev; 3603 3604 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3605 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3606 /* RLC autoload sequence 1: Program rlc ram */ 3607 if (adev->gfx.imu.funcs->program_rlc_ram) 3608 adev->gfx.imu.funcs->program_rlc_ram(adev); 3609 } 3610 /* rlc autoload firmware */ 3611 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3612 if (r) 3613 return r; 3614 } else { 3615 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3616 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3617 if (adev->gfx.imu.funcs->load_microcode) 3618 adev->gfx.imu.funcs->load_microcode(adev); 3619 if (adev->gfx.imu.funcs->setup_imu) 3620 adev->gfx.imu.funcs->setup_imu(adev); 3621 if (adev->gfx.imu.funcs->start_imu) 3622 adev->gfx.imu.funcs->start_imu(adev); 3623 } 3624 3625 /* disable gpa mode in backdoor loading */ 3626 gfx_v12_0_disable_gpa_mode(adev); 3627 } 3628 } 3629 3630 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3631 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3632 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3633 if (r) { 3634 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3635 return r; 3636 } 3637 } 3638 3639 if (!amdgpu_emu_mode) 3640 gfx_v12_0_init_golden_registers(adev); 3641 3642 adev->gfx.is_poweron = true; 3643 3644 if (get_gb_addr_config(adev)) 3645 DRM_WARN("Invalid gb_addr_config !\n"); 3646 3647 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3648 gfx_v12_0_config_gfx_rs64(adev); 3649 3650 r = gfx_v12_0_gfxhub_enable(adev); 3651 if (r) 3652 return r; 3653 3654 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3655 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3656 (amdgpu_dpm == 1)) { 3657 /** 3658 * For gfx 12, rlc firmware loading relies on smu firmware is 3659 * loaded firstly, so in direct type, it has to load smc ucode 3660 * here before rlc. 3661 */ 3662 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3663 if (r) 3664 return r; 3665 } 3666 3667 gfx_v12_0_constants_init(adev); 3668 3669 if (adev->nbio.funcs->gc_doorbell_init) 3670 adev->nbio.funcs->gc_doorbell_init(adev); 3671 3672 r = gfx_v12_0_rlc_resume(adev); 3673 if (r) 3674 return r; 3675 3676 /* 3677 * init golden registers and rlc resume may override some registers, 3678 * reconfig them here 3679 */ 3680 gfx_v12_0_tcp_harvest(adev); 3681 3682 r = gfx_v12_0_cp_resume(adev); 3683 if (r) 3684 return r; 3685 3686 return r; 3687 } 3688 3689 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3690 bool enable) 3691 { 3692 unsigned int irq_type; 3693 int m, p, r; 3694 3695 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3696 for (m = 0; m < adev->gfx.me.num_me; m++) { 3697 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3698 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3699 if (enable) 3700 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3701 irq_type); 3702 else 3703 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3704 irq_type); 3705 if (r) 3706 return r; 3707 } 3708 } 3709 } 3710 3711 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3712 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3713 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3714 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3715 + (m * adev->gfx.mec.num_pipe_per_mec) 3716 + p; 3717 if (enable) 3718 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3719 irq_type); 3720 else 3721 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3722 irq_type); 3723 if (r) 3724 return r; 3725 } 3726 } 3727 } 3728 3729 return 0; 3730 } 3731 3732 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3733 { 3734 struct amdgpu_device *adev = ip_block->adev; 3735 uint32_t tmp; 3736 3737 cancel_delayed_work_sync(&adev->gfx.idle_work); 3738 3739 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3740 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3741 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3742 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3743 3744 if (!adev->no_hw_access) { 3745 if (amdgpu_async_gfx_ring) { 3746 if (amdgpu_gfx_disable_kgq(adev, 0)) 3747 DRM_ERROR("KGQ disable failed\n"); 3748 } 3749 3750 if (amdgpu_gfx_disable_kcq(adev, 0)) 3751 DRM_ERROR("KCQ disable failed\n"); 3752 3753 amdgpu_mes_kiq_hw_fini(adev); 3754 } 3755 3756 if (amdgpu_sriov_vf(adev)) { 3757 gfx_v12_0_cp_gfx_enable(adev, false); 3758 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3759 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3760 tmp &= 0xffffff00; 3761 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3762 3763 return 0; 3764 } 3765 gfx_v12_0_cp_enable(adev, false); 3766 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3767 3768 adev->gfxhub.funcs->gart_disable(adev); 3769 3770 adev->gfx.is_poweron = false; 3771 3772 return 0; 3773 } 3774 3775 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3776 { 3777 return gfx_v12_0_hw_fini(ip_block); 3778 } 3779 3780 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3781 { 3782 return gfx_v12_0_hw_init(ip_block); 3783 } 3784 3785 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3786 { 3787 struct amdgpu_device *adev = ip_block->adev; 3788 3789 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3790 GRBM_STATUS, GUI_ACTIVE)) 3791 return false; 3792 else 3793 return true; 3794 } 3795 3796 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3797 { 3798 unsigned i; 3799 u32 tmp; 3800 struct amdgpu_device *adev = ip_block->adev; 3801 3802 for (i = 0; i < adev->usec_timeout; i++) { 3803 /* read MC_STATUS */ 3804 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3805 GRBM_STATUS__GUI_ACTIVE_MASK; 3806 3807 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3808 return 0; 3809 udelay(1); 3810 } 3811 return -ETIMEDOUT; 3812 } 3813 3814 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3815 { 3816 uint64_t clock = 0; 3817 3818 if (adev->smuio.funcs && 3819 adev->smuio.funcs->get_gpu_clock_counter) 3820 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3821 else 3822 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3823 3824 return clock; 3825 } 3826 3827 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3828 { 3829 struct amdgpu_device *adev = ip_block->adev; 3830 3831 switch (amdgpu_user_queue) { 3832 case -1: 3833 case 0: 3834 default: 3835 adev->gfx.disable_kq = false; 3836 adev->gfx.disable_uq = true; 3837 break; 3838 case 1: 3839 adev->gfx.disable_kq = false; 3840 adev->gfx.disable_uq = false; 3841 break; 3842 case 2: 3843 adev->gfx.disable_kq = true; 3844 adev->gfx.disable_uq = false; 3845 break; 3846 } 3847 3848 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3849 3850 if (adev->gfx.disable_kq) { 3851 adev->gfx.num_gfx_rings = 0; 3852 adev->gfx.num_compute_rings = 0; 3853 } else { 3854 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3855 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3856 AMDGPU_MAX_COMPUTE_RINGS); 3857 } 3858 3859 gfx_v12_0_set_kiq_pm4_funcs(adev); 3860 gfx_v12_0_set_ring_funcs(adev); 3861 gfx_v12_0_set_irq_funcs(adev); 3862 gfx_v12_0_set_rlc_funcs(adev); 3863 gfx_v12_0_set_mqd_funcs(adev); 3864 gfx_v12_0_set_imu_funcs(adev); 3865 3866 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3867 3868 return gfx_v12_0_init_microcode(adev); 3869 } 3870 3871 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3872 { 3873 struct amdgpu_device *adev = ip_block->adev; 3874 int r; 3875 3876 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3877 if (r) 3878 return r; 3879 3880 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3881 if (r) 3882 return r; 3883 3884 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3885 if (r) 3886 return r; 3887 3888 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3889 if (r) 3890 return r; 3891 3892 return 0; 3893 } 3894 3895 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3896 { 3897 uint32_t rlc_cntl; 3898 3899 /* if RLC is not enabled, do nothing */ 3900 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3901 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3902 } 3903 3904 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3905 int xcc_id) 3906 { 3907 uint32_t data; 3908 unsigned i; 3909 3910 data = RLC_SAFE_MODE__CMD_MASK; 3911 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3912 3913 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3914 3915 /* wait for RLC_SAFE_MODE */ 3916 for (i = 0; i < adev->usec_timeout; i++) { 3917 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3918 RLC_SAFE_MODE, CMD)) 3919 break; 3920 udelay(1); 3921 } 3922 } 3923 3924 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3925 int xcc_id) 3926 { 3927 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3928 } 3929 3930 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3931 bool enable) 3932 { 3933 uint32_t def, data; 3934 3935 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3936 return; 3937 3938 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3939 3940 if (enable) 3941 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3942 else 3943 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3944 3945 if (def != data) 3946 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3947 } 3948 3949 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3950 struct amdgpu_ring *ring, 3951 unsigned vmid) 3952 { 3953 u32 reg, data; 3954 3955 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3956 if (amdgpu_sriov_is_pp_one_vf(adev)) 3957 data = RREG32_NO_KIQ(reg); 3958 else 3959 data = RREG32(reg); 3960 3961 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3962 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3963 3964 if (amdgpu_sriov_is_pp_one_vf(adev)) 3965 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3966 else 3967 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3968 3969 if (ring 3970 && amdgpu_sriov_is_pp_one_vf(adev) 3971 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3972 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3973 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3974 amdgpu_ring_emit_wreg(ring, reg, data); 3975 } 3976 } 3977 3978 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3979 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3980 .set_safe_mode = gfx_v12_0_set_safe_mode, 3981 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3982 .init = gfx_v12_0_rlc_init, 3983 .get_csb_size = gfx_v12_0_get_csb_size, 3984 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3985 .resume = gfx_v12_0_rlc_resume, 3986 .stop = gfx_v12_0_rlc_stop, 3987 .reset = gfx_v12_0_rlc_reset, 3988 .start = gfx_v12_0_rlc_start, 3989 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3990 }; 3991 3992 #if 0 3993 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3994 { 3995 /* TODO */ 3996 } 3997 3998 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3999 { 4000 /* TODO */ 4001 } 4002 #endif 4003 4004 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4005 enum amd_powergating_state state) 4006 { 4007 struct amdgpu_device *adev = ip_block->adev; 4008 bool enable = (state == AMD_PG_STATE_GATE); 4009 4010 if (amdgpu_sriov_vf(adev)) 4011 return 0; 4012 4013 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4014 case IP_VERSION(12, 0, 0): 4015 case IP_VERSION(12, 0, 1): 4016 amdgpu_gfx_off_ctrl(adev, enable); 4017 break; 4018 default: 4019 break; 4020 } 4021 4022 return 0; 4023 } 4024 4025 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4026 bool enable) 4027 { 4028 uint32_t def, data; 4029 4030 if (!(adev->cg_flags & 4031 (AMD_CG_SUPPORT_GFX_CGCG | 4032 AMD_CG_SUPPORT_GFX_CGLS | 4033 AMD_CG_SUPPORT_GFX_3D_CGCG | 4034 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4035 return; 4036 4037 if (enable) { 4038 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4039 4040 /* unset CGCG override */ 4041 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4042 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4043 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4044 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4045 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4046 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4047 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4048 4049 /* update CGCG override bits */ 4050 if (def != data) 4051 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4052 4053 /* enable cgcg FSM(0x0000363F) */ 4054 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4055 4056 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4057 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4058 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4059 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4060 } 4061 4062 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4063 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4064 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4065 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4066 } 4067 4068 if (def != data) 4069 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4070 4071 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4072 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4073 4074 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4075 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4076 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4077 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4078 } 4079 4080 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4081 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4082 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4083 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4084 } 4085 4086 if (def != data) 4087 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4088 4089 /* set IDLE_POLL_COUNT(0x00900100) */ 4090 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4091 4092 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4093 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4094 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4095 4096 if (def != data) 4097 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4098 4099 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4100 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4101 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4102 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4103 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4104 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4105 4106 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4107 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4108 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4109 4110 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4111 if (adev->sdma.num_instances > 1) { 4112 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4113 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4114 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4115 } 4116 } else { 4117 /* Program RLC_CGCG_CGLS_CTRL */ 4118 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4119 4120 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4121 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4122 4123 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4124 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4125 4126 if (def != data) 4127 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4128 4129 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4130 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4131 4132 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4133 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4134 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4135 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4136 4137 if (def != data) 4138 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4139 } 4140 } 4141 4142 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4143 bool enable) 4144 { 4145 uint32_t data, def; 4146 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4147 return; 4148 4149 /* It is disabled by HW by default */ 4150 if (enable) { 4151 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4152 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4153 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4154 4155 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4156 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4157 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4158 4159 if (def != data) 4160 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4161 } 4162 } else { 4163 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4164 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4165 4166 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4167 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4168 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4169 4170 if (def != data) 4171 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4172 } 4173 } 4174 } 4175 4176 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4177 bool enable) 4178 { 4179 uint32_t def, data; 4180 4181 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4182 return; 4183 4184 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4185 4186 if (enable) 4187 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4188 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4189 else 4190 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4191 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4192 4193 if (def != data) 4194 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4195 } 4196 4197 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4198 bool enable) 4199 { 4200 uint32_t def, data; 4201 4202 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4203 return; 4204 4205 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4206 4207 if (enable) 4208 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4209 else 4210 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4211 4212 if (def != data) 4213 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4214 } 4215 4216 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4217 bool enable) 4218 { 4219 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4220 4221 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4222 4223 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4224 4225 gfx_v12_0_update_repeater_fgcg(adev, enable); 4226 4227 gfx_v12_0_update_sram_fgcg(adev, enable); 4228 4229 gfx_v12_0_update_perf_clk(adev, enable); 4230 4231 if (adev->cg_flags & 4232 (AMD_CG_SUPPORT_GFX_MGCG | 4233 AMD_CG_SUPPORT_GFX_CGLS | 4234 AMD_CG_SUPPORT_GFX_CGCG | 4235 AMD_CG_SUPPORT_GFX_3D_CGCG | 4236 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4237 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4238 4239 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4240 4241 return 0; 4242 } 4243 4244 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4245 enum amd_clockgating_state state) 4246 { 4247 struct amdgpu_device *adev = ip_block->adev; 4248 4249 if (amdgpu_sriov_vf(adev)) 4250 return 0; 4251 4252 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4253 case IP_VERSION(12, 0, 0): 4254 case IP_VERSION(12, 0, 1): 4255 gfx_v12_0_update_gfx_clock_gating(adev, 4256 state == AMD_CG_STATE_GATE); 4257 break; 4258 default: 4259 break; 4260 } 4261 4262 return 0; 4263 } 4264 4265 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4266 { 4267 struct amdgpu_device *adev = ip_block->adev; 4268 int data; 4269 4270 /* AMD_CG_SUPPORT_GFX_MGCG */ 4271 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4272 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4273 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4274 4275 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4276 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4277 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4278 4279 /* AMD_CG_SUPPORT_GFX_FGCG */ 4280 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4281 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4282 4283 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4284 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4285 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4286 4287 /* AMD_CG_SUPPORT_GFX_CGCG */ 4288 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4289 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4290 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4291 4292 /* AMD_CG_SUPPORT_GFX_CGLS */ 4293 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4294 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4295 4296 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4297 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4298 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4299 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4300 4301 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4302 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4303 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4304 } 4305 4306 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4307 { 4308 /* gfx12 is 32bit rptr*/ 4309 return *(uint32_t *)ring->rptr_cpu_addr; 4310 } 4311 4312 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4313 { 4314 struct amdgpu_device *adev = ring->adev; 4315 u64 wptr; 4316 4317 /* XXX check if swapping is necessary on BE */ 4318 if (ring->use_doorbell) { 4319 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4320 } else { 4321 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4322 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4323 } 4324 4325 return wptr; 4326 } 4327 4328 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4329 { 4330 struct amdgpu_device *adev = ring->adev; 4331 4332 if (ring->use_doorbell) { 4333 /* XXX check if swapping is necessary on BE */ 4334 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4335 ring->wptr); 4336 WDOORBELL64(ring->doorbell_index, ring->wptr); 4337 } else { 4338 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4339 lower_32_bits(ring->wptr)); 4340 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4341 upper_32_bits(ring->wptr)); 4342 } 4343 } 4344 4345 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4346 { 4347 /* gfx12 hardware is 32bit rptr */ 4348 return *(uint32_t *)ring->rptr_cpu_addr; 4349 } 4350 4351 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4352 { 4353 u64 wptr; 4354 4355 /* XXX check if swapping is necessary on BE */ 4356 if (ring->use_doorbell) 4357 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4358 else 4359 BUG(); 4360 return wptr; 4361 } 4362 4363 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4364 { 4365 struct amdgpu_device *adev = ring->adev; 4366 4367 /* XXX check if swapping is necessary on BE */ 4368 if (ring->use_doorbell) { 4369 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4370 ring->wptr); 4371 WDOORBELL64(ring->doorbell_index, ring->wptr); 4372 } else { 4373 BUG(); /* only DOORBELL method supported on gfx12 now */ 4374 } 4375 } 4376 4377 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4378 { 4379 struct amdgpu_device *adev = ring->adev; 4380 u32 ref_and_mask, reg_mem_engine; 4381 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4382 4383 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4384 switch (ring->me) { 4385 case 1: 4386 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4387 break; 4388 case 2: 4389 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4390 break; 4391 default: 4392 return; 4393 } 4394 reg_mem_engine = 0; 4395 } else { 4396 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4397 reg_mem_engine = 1; /* pfp */ 4398 } 4399 4400 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4401 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4402 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4403 ref_and_mask, ref_and_mask, 0x20); 4404 } 4405 4406 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4407 struct amdgpu_job *job, 4408 struct amdgpu_ib *ib, 4409 uint32_t flags) 4410 { 4411 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4412 u32 header, control = 0; 4413 4414 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4415 4416 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4417 4418 control |= ib->length_dw | (vmid << 24); 4419 4420 amdgpu_ring_write(ring, header); 4421 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4422 amdgpu_ring_write(ring, 4423 #ifdef __BIG_ENDIAN 4424 (2 << 0) | 4425 #endif 4426 lower_32_bits(ib->gpu_addr)); 4427 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4428 amdgpu_ring_write(ring, control); 4429 } 4430 4431 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4432 struct amdgpu_job *job, 4433 struct amdgpu_ib *ib, 4434 uint32_t flags) 4435 { 4436 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4437 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4438 4439 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4440 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4441 amdgpu_ring_write(ring, 4442 #ifdef __BIG_ENDIAN 4443 (2 << 0) | 4444 #endif 4445 lower_32_bits(ib->gpu_addr)); 4446 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4447 amdgpu_ring_write(ring, control); 4448 } 4449 4450 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4451 u64 seq, unsigned flags) 4452 { 4453 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4454 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4455 4456 /* RELEASE_MEM - flush caches, send int */ 4457 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4458 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4459 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4460 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4461 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4462 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4463 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4464 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4465 4466 /* 4467 * the address should be Qword aligned if 64bit write, Dword 4468 * aligned if only send 32bit data low (discard data high) 4469 */ 4470 if (write64bit) 4471 BUG_ON(addr & 0x7); 4472 else 4473 BUG_ON(addr & 0x3); 4474 amdgpu_ring_write(ring, lower_32_bits(addr)); 4475 amdgpu_ring_write(ring, upper_32_bits(addr)); 4476 amdgpu_ring_write(ring, lower_32_bits(seq)); 4477 amdgpu_ring_write(ring, upper_32_bits(seq)); 4478 amdgpu_ring_write(ring, 0); 4479 } 4480 4481 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4482 { 4483 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4484 uint32_t seq = ring->fence_drv.sync_seq; 4485 uint64_t addr = ring->fence_drv.gpu_addr; 4486 4487 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4488 upper_32_bits(addr), seq, 0xffffffff, 4); 4489 } 4490 4491 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4492 uint16_t pasid, uint32_t flush_type, 4493 bool all_hub, uint8_t dst_sel) 4494 { 4495 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4496 amdgpu_ring_write(ring, 4497 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4498 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4499 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4500 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4501 } 4502 4503 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4504 unsigned vmid, uint64_t pd_addr) 4505 { 4506 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4507 4508 /* compute doesn't have PFP */ 4509 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4510 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4511 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4512 amdgpu_ring_write(ring, 0x0); 4513 } 4514 } 4515 4516 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4517 u64 seq, unsigned int flags) 4518 { 4519 struct amdgpu_device *adev = ring->adev; 4520 4521 /* we only allocate 32bit for each seq wb address */ 4522 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4523 4524 /* write fence seq to the "addr" */ 4525 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4526 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4527 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4528 amdgpu_ring_write(ring, lower_32_bits(addr)); 4529 amdgpu_ring_write(ring, upper_32_bits(addr)); 4530 amdgpu_ring_write(ring, lower_32_bits(seq)); 4531 4532 if (flags & AMDGPU_FENCE_FLAG_INT) { 4533 /* set register to trigger INT */ 4534 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4535 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4536 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4537 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4538 amdgpu_ring_write(ring, 0); 4539 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4540 } 4541 } 4542 4543 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4544 uint32_t flags) 4545 { 4546 uint32_t dw2 = 0; 4547 4548 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4549 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4550 /* set load_global_config & load_global_uconfig */ 4551 dw2 |= 0x8001; 4552 /* set load_cs_sh_regs */ 4553 dw2 |= 0x01000000; 4554 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4555 dw2 |= 0x10002; 4556 } 4557 4558 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4559 amdgpu_ring_write(ring, dw2); 4560 amdgpu_ring_write(ring, 0); 4561 } 4562 4563 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4564 uint64_t addr) 4565 { 4566 unsigned ret; 4567 4568 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4569 amdgpu_ring_write(ring, lower_32_bits(addr)); 4570 amdgpu_ring_write(ring, upper_32_bits(addr)); 4571 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4572 amdgpu_ring_write(ring, 0); 4573 ret = ring->wptr & ring->buf_mask; 4574 /* patch dummy value later */ 4575 amdgpu_ring_write(ring, 0); 4576 4577 return ret; 4578 } 4579 4580 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4581 { 4582 int i, r = 0; 4583 struct amdgpu_device *adev = ring->adev; 4584 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4585 struct amdgpu_ring *kiq_ring = &kiq->ring; 4586 unsigned long flags; 4587 4588 if (adev->enable_mes) 4589 return -EINVAL; 4590 4591 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4592 return -EINVAL; 4593 4594 spin_lock_irqsave(&kiq->ring_lock, flags); 4595 4596 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4597 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4598 return -ENOMEM; 4599 } 4600 4601 /* assert preemption condition */ 4602 amdgpu_ring_set_preempt_cond_exec(ring, false); 4603 4604 /* assert IB preemption, emit the trailing fence */ 4605 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4606 ring->trail_fence_gpu_addr, 4607 ++ring->trail_seq); 4608 amdgpu_ring_commit(kiq_ring); 4609 4610 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4611 4612 /* poll the trailing fence */ 4613 for (i = 0; i < adev->usec_timeout; i++) { 4614 if (ring->trail_seq == 4615 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4616 break; 4617 udelay(1); 4618 } 4619 4620 if (i >= adev->usec_timeout) { 4621 r = -EINVAL; 4622 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4623 } 4624 4625 /* deassert preemption condition */ 4626 amdgpu_ring_set_preempt_cond_exec(ring, true); 4627 return r; 4628 } 4629 4630 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4631 bool start, 4632 bool secure) 4633 { 4634 uint32_t v = secure ? FRAME_TMZ : 0; 4635 4636 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4637 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4638 } 4639 4640 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4641 uint32_t reg_val_offs) 4642 { 4643 struct amdgpu_device *adev = ring->adev; 4644 4645 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4646 amdgpu_ring_write(ring, 0 | /* src: register*/ 4647 (5 << 8) | /* dst: memory */ 4648 (1 << 20)); /* write confirm */ 4649 amdgpu_ring_write(ring, reg); 4650 amdgpu_ring_write(ring, 0); 4651 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4652 reg_val_offs * 4)); 4653 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4654 reg_val_offs * 4)); 4655 } 4656 4657 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4658 uint32_t reg, 4659 uint32_t val) 4660 { 4661 uint32_t cmd = 0; 4662 4663 switch (ring->funcs->type) { 4664 case AMDGPU_RING_TYPE_GFX: 4665 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4666 break; 4667 case AMDGPU_RING_TYPE_KIQ: 4668 cmd = (1 << 16); /* no inc addr */ 4669 break; 4670 default: 4671 cmd = WR_CONFIRM; 4672 break; 4673 } 4674 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4675 amdgpu_ring_write(ring, cmd); 4676 amdgpu_ring_write(ring, reg); 4677 amdgpu_ring_write(ring, 0); 4678 amdgpu_ring_write(ring, val); 4679 } 4680 4681 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4682 uint32_t val, uint32_t mask) 4683 { 4684 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4685 } 4686 4687 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4688 uint32_t reg0, uint32_t reg1, 4689 uint32_t ref, uint32_t mask) 4690 { 4691 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4692 4693 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4694 ref, mask, 0x20); 4695 } 4696 4697 static void 4698 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4699 uint32_t me, uint32_t pipe, 4700 enum amdgpu_interrupt_state state) 4701 { 4702 uint32_t cp_int_cntl, cp_int_cntl_reg; 4703 4704 if (!me) { 4705 switch (pipe) { 4706 case 0: 4707 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4708 break; 4709 default: 4710 DRM_DEBUG("invalid pipe %d\n", pipe); 4711 return; 4712 } 4713 } else { 4714 DRM_DEBUG("invalid me %d\n", me); 4715 return; 4716 } 4717 4718 switch (state) { 4719 case AMDGPU_IRQ_STATE_DISABLE: 4720 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4721 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4722 TIME_STAMP_INT_ENABLE, 0); 4723 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4724 GENERIC0_INT_ENABLE, 0); 4725 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4726 break; 4727 case AMDGPU_IRQ_STATE_ENABLE: 4728 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4729 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4730 TIME_STAMP_INT_ENABLE, 1); 4731 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4732 GENERIC0_INT_ENABLE, 1); 4733 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4734 break; 4735 default: 4736 break; 4737 } 4738 } 4739 4740 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4741 int me, int pipe, 4742 enum amdgpu_interrupt_state state) 4743 { 4744 u32 mec_int_cntl, mec_int_cntl_reg; 4745 4746 /* 4747 * amdgpu controls only the first MEC. That's why this function only 4748 * handles the setting of interrupts for this specific MEC. All other 4749 * pipes' interrupts are set by amdkfd. 4750 */ 4751 4752 if (me == 1) { 4753 switch (pipe) { 4754 case 0: 4755 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4756 break; 4757 case 1: 4758 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4759 break; 4760 default: 4761 DRM_DEBUG("invalid pipe %d\n", pipe); 4762 return; 4763 } 4764 } else { 4765 DRM_DEBUG("invalid me %d\n", me); 4766 return; 4767 } 4768 4769 switch (state) { 4770 case AMDGPU_IRQ_STATE_DISABLE: 4771 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4772 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4773 TIME_STAMP_INT_ENABLE, 0); 4774 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4775 GENERIC0_INT_ENABLE, 0); 4776 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4777 break; 4778 case AMDGPU_IRQ_STATE_ENABLE: 4779 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4780 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4781 TIME_STAMP_INT_ENABLE, 1); 4782 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4783 GENERIC0_INT_ENABLE, 1); 4784 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4785 break; 4786 default: 4787 break; 4788 } 4789 } 4790 4791 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4792 struct amdgpu_irq_src *src, 4793 unsigned type, 4794 enum amdgpu_interrupt_state state) 4795 { 4796 switch (type) { 4797 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4798 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4799 break; 4800 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4801 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4802 break; 4803 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4804 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4805 break; 4806 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4807 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4808 break; 4809 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4810 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4811 break; 4812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4813 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4814 break; 4815 default: 4816 break; 4817 } 4818 return 0; 4819 } 4820 4821 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4822 struct amdgpu_irq_src *source, 4823 struct amdgpu_iv_entry *entry) 4824 { 4825 u32 doorbell_offset = entry->src_data[0]; 4826 u8 me_id, pipe_id, queue_id; 4827 struct amdgpu_ring *ring; 4828 int i; 4829 4830 DRM_DEBUG("IH: CP EOP\n"); 4831 4832 if (adev->enable_mes && doorbell_offset) { 4833 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4834 struct xarray *xa = &adev->userq_xa; 4835 unsigned long flags; 4836 4837 xa_lock_irqsave(xa, flags); 4838 fence_drv = xa_load(xa, doorbell_offset); 4839 if (fence_drv) 4840 amdgpu_userq_fence_driver_process(fence_drv); 4841 xa_unlock_irqrestore(xa, flags); 4842 } else { 4843 me_id = (entry->ring_id & 0x0c) >> 2; 4844 pipe_id = (entry->ring_id & 0x03) >> 0; 4845 queue_id = (entry->ring_id & 0x70) >> 4; 4846 4847 switch (me_id) { 4848 case 0: 4849 if (pipe_id == 0) 4850 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4851 else 4852 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4853 break; 4854 case 1: 4855 case 2: 4856 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4857 ring = &adev->gfx.compute_ring[i]; 4858 /* Per-queue interrupt is supported for MEC starting from VI. 4859 * The interrupt can only be enabled/disabled per pipe instead 4860 * of per queue. 4861 */ 4862 if ((ring->me == me_id) && 4863 (ring->pipe == pipe_id) && 4864 (ring->queue == queue_id)) 4865 amdgpu_fence_process(ring); 4866 } 4867 break; 4868 } 4869 } 4870 4871 return 0; 4872 } 4873 4874 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4875 struct amdgpu_irq_src *source, 4876 unsigned int type, 4877 enum amdgpu_interrupt_state state) 4878 { 4879 u32 cp_int_cntl_reg, cp_int_cntl; 4880 int i, j; 4881 4882 switch (state) { 4883 case AMDGPU_IRQ_STATE_DISABLE: 4884 case AMDGPU_IRQ_STATE_ENABLE: 4885 for (i = 0; i < adev->gfx.me.num_me; i++) { 4886 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4887 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4888 4889 if (cp_int_cntl_reg) { 4890 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4891 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4892 PRIV_REG_INT_ENABLE, 4893 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4895 } 4896 } 4897 } 4898 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4899 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4900 /* MECs start at 1 */ 4901 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4902 4903 if (cp_int_cntl_reg) { 4904 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4905 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4906 PRIV_REG_INT_ENABLE, 4907 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4908 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4909 } 4910 } 4911 } 4912 break; 4913 default: 4914 break; 4915 } 4916 4917 return 0; 4918 } 4919 4920 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4921 struct amdgpu_irq_src *source, 4922 unsigned type, 4923 enum amdgpu_interrupt_state state) 4924 { 4925 u32 cp_int_cntl_reg, cp_int_cntl; 4926 int i, j; 4927 4928 switch (state) { 4929 case AMDGPU_IRQ_STATE_DISABLE: 4930 case AMDGPU_IRQ_STATE_ENABLE: 4931 for (i = 0; i < adev->gfx.me.num_me; i++) { 4932 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4933 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4934 4935 if (cp_int_cntl_reg) { 4936 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4937 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4938 OPCODE_ERROR_INT_ENABLE, 4939 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4940 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4941 } 4942 } 4943 } 4944 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4945 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4946 /* MECs start at 1 */ 4947 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4948 4949 if (cp_int_cntl_reg) { 4950 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4951 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4952 OPCODE_ERROR_INT_ENABLE, 4953 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4954 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4955 } 4956 } 4957 } 4958 break; 4959 default: 4960 break; 4961 } 4962 return 0; 4963 } 4964 4965 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4966 struct amdgpu_irq_src *source, 4967 unsigned int type, 4968 enum amdgpu_interrupt_state state) 4969 { 4970 u32 cp_int_cntl_reg, cp_int_cntl; 4971 int i, j; 4972 4973 switch (state) { 4974 case AMDGPU_IRQ_STATE_DISABLE: 4975 case AMDGPU_IRQ_STATE_ENABLE: 4976 for (i = 0; i < adev->gfx.me.num_me; i++) { 4977 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4978 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4979 4980 if (cp_int_cntl_reg) { 4981 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4982 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4983 PRIV_INSTR_INT_ENABLE, 4984 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4985 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4986 } 4987 } 4988 } 4989 break; 4990 default: 4991 break; 4992 } 4993 4994 return 0; 4995 } 4996 4997 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4998 struct amdgpu_iv_entry *entry) 4999 { 5000 u8 me_id, pipe_id, queue_id; 5001 struct amdgpu_ring *ring; 5002 int i; 5003 5004 me_id = (entry->ring_id & 0x0c) >> 2; 5005 pipe_id = (entry->ring_id & 0x03) >> 0; 5006 queue_id = (entry->ring_id & 0x70) >> 4; 5007 5008 if (!adev->gfx.disable_kq) { 5009 switch (me_id) { 5010 case 0: 5011 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5012 ring = &adev->gfx.gfx_ring[i]; 5013 if (ring->me == me_id && ring->pipe == pipe_id && 5014 ring->queue == queue_id) 5015 drm_sched_fault(&ring->sched); 5016 } 5017 break; 5018 case 1: 5019 case 2: 5020 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5021 ring = &adev->gfx.compute_ring[i]; 5022 if (ring->me == me_id && ring->pipe == pipe_id && 5023 ring->queue == queue_id) 5024 drm_sched_fault(&ring->sched); 5025 } 5026 break; 5027 default: 5028 BUG(); 5029 break; 5030 } 5031 } 5032 } 5033 5034 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5035 struct amdgpu_irq_src *source, 5036 struct amdgpu_iv_entry *entry) 5037 { 5038 DRM_ERROR("Illegal register access in command stream\n"); 5039 gfx_v12_0_handle_priv_fault(adev, entry); 5040 return 0; 5041 } 5042 5043 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5044 struct amdgpu_irq_src *source, 5045 struct amdgpu_iv_entry *entry) 5046 { 5047 DRM_ERROR("Illegal opcode in command stream \n"); 5048 gfx_v12_0_handle_priv_fault(adev, entry); 5049 return 0; 5050 } 5051 5052 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5053 struct amdgpu_irq_src *source, 5054 struct amdgpu_iv_entry *entry) 5055 { 5056 DRM_ERROR("Illegal instruction in command stream\n"); 5057 gfx_v12_0_handle_priv_fault(adev, entry); 5058 return 0; 5059 } 5060 5061 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5062 { 5063 const unsigned int gcr_cntl = 5064 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5065 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5066 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5067 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5068 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5069 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5070 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5072 5073 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5074 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5075 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5076 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5077 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5078 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5079 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5080 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5081 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5082 } 5083 5084 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5085 { 5086 /* Header itself is a NOP packet */ 5087 if (num_nop == 1) { 5088 amdgpu_ring_write(ring, ring->funcs->nop); 5089 return; 5090 } 5091 5092 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5093 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5094 5095 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5096 amdgpu_ring_insert_nop(ring, num_nop - 1); 5097 } 5098 5099 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5100 { 5101 /* Emit the cleaner shader */ 5102 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5103 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5104 } 5105 5106 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5107 { 5108 struct amdgpu_device *adev = ip_block->adev; 5109 uint32_t i, j, k, reg, index = 0; 5110 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5111 5112 if (!adev->gfx.ip_dump_core) 5113 return; 5114 5115 for (i = 0; i < reg_count; i++) 5116 drm_printf(p, "%-50s \t 0x%08x\n", 5117 gc_reg_list_12_0[i].reg_name, 5118 adev->gfx.ip_dump_core[i]); 5119 5120 /* print compute queue registers for all instances */ 5121 if (!adev->gfx.ip_dump_compute_queues) 5122 return; 5123 5124 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5125 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5126 adev->gfx.mec.num_mec, 5127 adev->gfx.mec.num_pipe_per_mec, 5128 adev->gfx.mec.num_queue_per_pipe); 5129 5130 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5131 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5132 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5133 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5134 for (reg = 0; reg < reg_count; reg++) { 5135 drm_printf(p, "%-50s \t 0x%08x\n", 5136 gc_cp_reg_list_12[reg].reg_name, 5137 adev->gfx.ip_dump_compute_queues[index + reg]); 5138 } 5139 index += reg_count; 5140 } 5141 } 5142 } 5143 5144 /* print gfx queue registers for all instances */ 5145 if (!adev->gfx.ip_dump_gfx_queues) 5146 return; 5147 5148 index = 0; 5149 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5150 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5151 adev->gfx.me.num_me, 5152 adev->gfx.me.num_pipe_per_me, 5153 adev->gfx.me.num_queue_per_pipe); 5154 5155 for (i = 0; i < adev->gfx.me.num_me; i++) { 5156 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5157 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5158 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5159 for (reg = 0; reg < reg_count; reg++) { 5160 drm_printf(p, "%-50s \t 0x%08x\n", 5161 gc_gfx_queue_reg_list_12[reg].reg_name, 5162 adev->gfx.ip_dump_gfx_queues[index + reg]); 5163 } 5164 index += reg_count; 5165 } 5166 } 5167 } 5168 } 5169 5170 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5171 { 5172 struct amdgpu_device *adev = ip_block->adev; 5173 uint32_t i, j, k, reg, index = 0; 5174 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5175 5176 if (!adev->gfx.ip_dump_core) 5177 return; 5178 5179 amdgpu_gfx_off_ctrl(adev, false); 5180 for (i = 0; i < reg_count; i++) 5181 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5182 amdgpu_gfx_off_ctrl(adev, true); 5183 5184 /* dump compute queue registers for all instances */ 5185 if (!adev->gfx.ip_dump_compute_queues) 5186 return; 5187 5188 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5189 amdgpu_gfx_off_ctrl(adev, false); 5190 mutex_lock(&adev->srbm_mutex); 5191 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5192 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5193 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5194 /* ME0 is for GFX so start from 1 for CP */ 5195 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5196 for (reg = 0; reg < reg_count; reg++) { 5197 adev->gfx.ip_dump_compute_queues[index + reg] = 5198 RREG32(SOC15_REG_ENTRY_OFFSET( 5199 gc_cp_reg_list_12[reg])); 5200 } 5201 index += reg_count; 5202 } 5203 } 5204 } 5205 soc24_grbm_select(adev, 0, 0, 0, 0); 5206 mutex_unlock(&adev->srbm_mutex); 5207 amdgpu_gfx_off_ctrl(adev, true); 5208 5209 /* dump gfx queue registers for all instances */ 5210 if (!adev->gfx.ip_dump_gfx_queues) 5211 return; 5212 5213 index = 0; 5214 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5215 amdgpu_gfx_off_ctrl(adev, false); 5216 mutex_lock(&adev->srbm_mutex); 5217 for (i = 0; i < adev->gfx.me.num_me; i++) { 5218 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5219 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5220 soc24_grbm_select(adev, i, j, k, 0); 5221 5222 for (reg = 0; reg < reg_count; reg++) { 5223 adev->gfx.ip_dump_gfx_queues[index + reg] = 5224 RREG32(SOC15_REG_ENTRY_OFFSET( 5225 gc_gfx_queue_reg_list_12[reg])); 5226 } 5227 index += reg_count; 5228 } 5229 } 5230 } 5231 soc24_grbm_select(adev, 0, 0, 0, 0); 5232 mutex_unlock(&adev->srbm_mutex); 5233 amdgpu_gfx_off_ctrl(adev, true); 5234 } 5235 5236 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5237 { 5238 /* Disable the pipe reset until the CPFW fully support it.*/ 5239 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5240 return false; 5241 } 5242 5243 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5244 { 5245 struct amdgpu_device *adev = ring->adev; 5246 uint32_t reset_pipe = 0, clean_pipe = 0; 5247 int r; 5248 5249 if (!gfx_v12_pipe_reset_support(adev)) 5250 return -EOPNOTSUPP; 5251 5252 gfx_v12_0_set_safe_mode(adev, 0); 5253 mutex_lock(&adev->srbm_mutex); 5254 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5255 5256 switch (ring->pipe) { 5257 case 0: 5258 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5259 PFP_PIPE0_RESET, 1); 5260 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5261 ME_PIPE0_RESET, 1); 5262 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5263 PFP_PIPE0_RESET, 0); 5264 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5265 ME_PIPE0_RESET, 0); 5266 break; 5267 case 1: 5268 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5269 PFP_PIPE1_RESET, 1); 5270 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5271 ME_PIPE1_RESET, 1); 5272 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5273 PFP_PIPE1_RESET, 0); 5274 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5275 ME_PIPE1_RESET, 0); 5276 break; 5277 default: 5278 break; 5279 } 5280 5281 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5282 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5283 5284 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5285 RS64_FW_UC_START_ADDR_LO; 5286 soc24_grbm_select(adev, 0, 0, 0, 0); 5287 mutex_unlock(&adev->srbm_mutex); 5288 gfx_v12_0_unset_safe_mode(adev, 0); 5289 5290 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5291 r == 0 ? "successfully" : "failed"); 5292 /* Sometimes the ME start pc counter can't cache correctly, so the 5293 * PC check only as a reference and pipe reset result rely on the 5294 * later ring test. 5295 */ 5296 return 0; 5297 } 5298 5299 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5300 unsigned int vmid, 5301 struct amdgpu_fence *timedout_fence) 5302 { 5303 struct amdgpu_device *adev = ring->adev; 5304 int r; 5305 5306 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5307 5308 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5309 if (r) { 5310 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5311 r = gfx_v12_reset_gfx_pipe(ring); 5312 if (r) 5313 return r; 5314 } 5315 5316 r = gfx_v12_0_kgq_init_queue(ring, true); 5317 if (r) { 5318 dev_err(adev->dev, "failed to init kgq\n"); 5319 return r; 5320 } 5321 5322 r = amdgpu_mes_map_legacy_queue(adev, ring); 5323 if (r) { 5324 dev_err(adev->dev, "failed to remap kgq\n"); 5325 return r; 5326 } 5327 5328 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5329 } 5330 5331 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5332 { 5333 struct amdgpu_device *adev = ring->adev; 5334 uint32_t reset_pipe = 0, clean_pipe = 0; 5335 int r = 0; 5336 5337 if (!gfx_v12_pipe_reset_support(adev)) 5338 return -EOPNOTSUPP; 5339 5340 gfx_v12_0_set_safe_mode(adev, 0); 5341 mutex_lock(&adev->srbm_mutex); 5342 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5343 5344 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5345 clean_pipe = reset_pipe; 5346 5347 if (adev->gfx.rs64_enable) { 5348 switch (ring->pipe) { 5349 case 0: 5350 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5351 MEC_PIPE0_RESET, 1); 5352 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5353 MEC_PIPE0_RESET, 0); 5354 break; 5355 case 1: 5356 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5357 MEC_PIPE1_RESET, 1); 5358 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5359 MEC_PIPE1_RESET, 0); 5360 break; 5361 case 2: 5362 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5363 MEC_PIPE2_RESET, 1); 5364 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5365 MEC_PIPE2_RESET, 0); 5366 break; 5367 case 3: 5368 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5369 MEC_PIPE3_RESET, 1); 5370 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5371 MEC_PIPE3_RESET, 0); 5372 break; 5373 default: 5374 break; 5375 } 5376 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5377 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5378 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5379 RS64_FW_UC_START_ADDR_LO; 5380 } else { 5381 switch (ring->pipe) { 5382 case 0: 5383 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5384 MEC_ME1_PIPE0_RESET, 1); 5385 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5386 MEC_ME1_PIPE0_RESET, 0); 5387 break; 5388 case 1: 5389 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5390 MEC_ME1_PIPE1_RESET, 1); 5391 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5392 MEC_ME1_PIPE1_RESET, 0); 5393 break; 5394 default: 5395 break; 5396 } 5397 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5398 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5399 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5400 * the driver won't run into the F32 mode. 5401 */ 5402 } 5403 5404 soc24_grbm_select(adev, 0, 0, 0, 0); 5405 mutex_unlock(&adev->srbm_mutex); 5406 gfx_v12_0_unset_safe_mode(adev, 0); 5407 5408 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5409 r == 0 ? "successfully" : "failed"); 5410 /* Need the ring test to verify the pipe reset result.*/ 5411 return 0; 5412 } 5413 5414 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5415 unsigned int vmid, 5416 struct amdgpu_fence *timedout_fence) 5417 { 5418 struct amdgpu_device *adev = ring->adev; 5419 int r; 5420 5421 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5422 5423 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5424 if (r) { 5425 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5426 r = gfx_v12_0_reset_compute_pipe(ring); 5427 if (r) 5428 return r; 5429 } 5430 5431 r = gfx_v12_0_kcq_init_queue(ring, true); 5432 if (r) { 5433 dev_err(adev->dev, "failed to init kcq\n"); 5434 return r; 5435 } 5436 r = amdgpu_mes_map_legacy_queue(adev, ring); 5437 if (r) { 5438 dev_err(adev->dev, "failed to remap kcq\n"); 5439 return r; 5440 } 5441 5442 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5443 } 5444 5445 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5446 { 5447 amdgpu_gfx_profile_ring_begin_use(ring); 5448 5449 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5450 } 5451 5452 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5453 { 5454 amdgpu_gfx_profile_ring_end_use(ring); 5455 5456 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5457 } 5458 5459 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5460 .name = "gfx_v12_0", 5461 .early_init = gfx_v12_0_early_init, 5462 .late_init = gfx_v12_0_late_init, 5463 .sw_init = gfx_v12_0_sw_init, 5464 .sw_fini = gfx_v12_0_sw_fini, 5465 .hw_init = gfx_v12_0_hw_init, 5466 .hw_fini = gfx_v12_0_hw_fini, 5467 .suspend = gfx_v12_0_suspend, 5468 .resume = gfx_v12_0_resume, 5469 .is_idle = gfx_v12_0_is_idle, 5470 .wait_for_idle = gfx_v12_0_wait_for_idle, 5471 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5472 .set_powergating_state = gfx_v12_0_set_powergating_state, 5473 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5474 .dump_ip_state = gfx_v12_ip_dump, 5475 .print_ip_state = gfx_v12_ip_print, 5476 }; 5477 5478 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5479 .type = AMDGPU_RING_TYPE_GFX, 5480 .align_mask = 0xff, 5481 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5482 .support_64bit_ptrs = true, 5483 .secure_submission_supported = true, 5484 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5485 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5486 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5487 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5488 5 + /* COND_EXEC */ 5489 7 + /* PIPELINE_SYNC */ 5490 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5491 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5492 2 + /* VM_FLUSH */ 5493 8 + /* FENCE for VM_FLUSH */ 5494 5 + /* COND_EXEC */ 5495 7 + /* HDP_flush */ 5496 4 + /* VGT_flush */ 5497 31 + /* DE_META */ 5498 3 + /* CNTX_CTRL */ 5499 5 + /* HDP_INVL */ 5500 8 + 8 + /* FENCE x2 */ 5501 8 + /* gfx_v12_0_emit_mem_sync */ 5502 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5503 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5504 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5505 .emit_fence = gfx_v12_0_ring_emit_fence, 5506 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5507 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5508 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5509 .test_ring = gfx_v12_0_ring_test_ring, 5510 .test_ib = gfx_v12_0_ring_test_ib, 5511 .insert_nop = gfx_v12_ring_insert_nop, 5512 .pad_ib = amdgpu_ring_generic_pad_ib, 5513 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5514 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5515 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5516 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5517 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5518 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5519 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5520 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5521 .reset = gfx_v12_0_reset_kgq, 5522 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5523 .begin_use = gfx_v12_0_ring_begin_use, 5524 .end_use = gfx_v12_0_ring_end_use, 5525 }; 5526 5527 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5528 .type = AMDGPU_RING_TYPE_COMPUTE, 5529 .align_mask = 0xff, 5530 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5531 .support_64bit_ptrs = true, 5532 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5533 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5534 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5535 .emit_frame_size = 5536 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5537 5 + /* hdp invalidate */ 5538 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5539 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5540 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5541 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5542 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5543 8 + /* gfx_v12_0_emit_mem_sync */ 5544 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5545 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5546 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5547 .emit_fence = gfx_v12_0_ring_emit_fence, 5548 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5549 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5550 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5551 .test_ring = gfx_v12_0_ring_test_ring, 5552 .test_ib = gfx_v12_0_ring_test_ib, 5553 .insert_nop = gfx_v12_ring_insert_nop, 5554 .pad_ib = amdgpu_ring_generic_pad_ib, 5555 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5556 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5557 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5558 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5559 .reset = gfx_v12_0_reset_kcq, 5560 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5561 .begin_use = gfx_v12_0_ring_begin_use, 5562 .end_use = gfx_v12_0_ring_end_use, 5563 }; 5564 5565 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5566 .type = AMDGPU_RING_TYPE_KIQ, 5567 .align_mask = 0xff, 5568 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5569 .support_64bit_ptrs = true, 5570 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5571 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5572 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5573 .emit_frame_size = 5574 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5575 5 + /*hdp invalidate */ 5576 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5577 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5578 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5579 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5580 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5581 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5582 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5583 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5584 .test_ring = gfx_v12_0_ring_test_ring, 5585 .test_ib = gfx_v12_0_ring_test_ib, 5586 .insert_nop = amdgpu_ring_insert_nop, 5587 .pad_ib = amdgpu_ring_generic_pad_ib, 5588 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5589 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5590 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5591 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5592 }; 5593 5594 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5595 { 5596 int i; 5597 5598 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5599 5600 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5601 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5602 5603 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5604 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5605 } 5606 5607 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5608 .set = gfx_v12_0_set_eop_interrupt_state, 5609 .process = gfx_v12_0_eop_irq, 5610 }; 5611 5612 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5613 .set = gfx_v12_0_set_priv_reg_fault_state, 5614 .process = gfx_v12_0_priv_reg_irq, 5615 }; 5616 5617 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5618 .set = gfx_v12_0_set_bad_op_fault_state, 5619 .process = gfx_v12_0_bad_op_irq, 5620 }; 5621 5622 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5623 .set = gfx_v12_0_set_priv_inst_fault_state, 5624 .process = gfx_v12_0_priv_inst_irq, 5625 }; 5626 5627 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5628 { 5629 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5630 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5631 5632 adev->gfx.priv_reg_irq.num_types = 1; 5633 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5634 5635 adev->gfx.bad_op_irq.num_types = 1; 5636 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5637 5638 adev->gfx.priv_inst_irq.num_types = 1; 5639 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5640 } 5641 5642 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5643 { 5644 if (adev->flags & AMD_IS_APU) 5645 adev->gfx.imu.mode = MISSION_MODE; 5646 else 5647 adev->gfx.imu.mode = DEBUG_MODE; 5648 5649 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5650 } 5651 5652 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5653 { 5654 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5655 } 5656 5657 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5658 { 5659 /* set gfx eng mqd */ 5660 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5661 sizeof(struct v12_gfx_mqd); 5662 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5663 gfx_v12_0_gfx_mqd_init; 5664 /* set compute eng mqd */ 5665 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5666 sizeof(struct v12_compute_mqd); 5667 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5668 gfx_v12_0_compute_mqd_init; 5669 } 5670 5671 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5672 u32 bitmap) 5673 { 5674 u32 data; 5675 5676 if (!bitmap) 5677 return; 5678 5679 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5680 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5681 5682 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5683 } 5684 5685 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5686 { 5687 u32 data, wgp_bitmask; 5688 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5689 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5690 5691 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5692 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5693 5694 wgp_bitmask = 5695 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5696 5697 return (~data) & wgp_bitmask; 5698 } 5699 5700 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5701 { 5702 u32 wgp_idx, wgp_active_bitmap; 5703 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5704 5705 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5706 cu_active_bitmap = 0; 5707 5708 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5709 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5710 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5711 if (wgp_active_bitmap & (1 << wgp_idx)) 5712 cu_active_bitmap |= cu_bitmap_per_wgp; 5713 } 5714 5715 return cu_active_bitmap; 5716 } 5717 5718 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5719 struct amdgpu_cu_info *cu_info) 5720 { 5721 int i, j, k, counter, active_cu_number = 0; 5722 u32 mask, bitmap; 5723 unsigned disable_masks[8 * 2]; 5724 5725 if (!adev || !cu_info) 5726 return -EINVAL; 5727 5728 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5729 5730 mutex_lock(&adev->grbm_idx_mutex); 5731 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5732 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5733 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5734 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5735 continue; 5736 mask = 1; 5737 counter = 0; 5738 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5739 if (i < 8 && j < 2) 5740 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5741 adev, disable_masks[i * 2 + j]); 5742 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5743 5744 /** 5745 * GFX12 could support more than 4 SEs, while the bitmap 5746 * in cu_info struct is 4x4 and ioctl interface struct 5747 * drm_amdgpu_info_device should keep stable. 5748 * So we use last two columns of bitmap to store cu mask for 5749 * SEs 4 to 7, the layout of the bitmap is as below: 5750 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5751 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5752 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5753 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5754 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5755 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5756 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5757 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5758 */ 5759 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5760 5761 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5762 if (bitmap & mask) 5763 counter++; 5764 5765 mask <<= 1; 5766 } 5767 active_cu_number += counter; 5768 } 5769 } 5770 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5771 mutex_unlock(&adev->grbm_idx_mutex); 5772 5773 cu_info->number = active_cu_number; 5774 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5775 5776 return 0; 5777 } 5778 5779 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5780 .type = AMD_IP_BLOCK_TYPE_GFX, 5781 .major = 12, 5782 .minor = 0, 5783 .rev = 0, 5784 .funcs = &gfx_v12_0_ip_funcs, 5785 }; 5786