1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 83 84 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 115 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 120 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 121 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 124 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 138 /* cp header registers */ 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 /* SE status registers */ 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 152 }; 153 154 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 155 /* compute registers */ 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 195 /* cp header registers */ 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 }; 205 206 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 207 /* gfx queue registers */ 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 233 /* cp header registers */ 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 }; 251 252 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 256 }; 257 258 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 260 }; 261 262 #define DEFAULT_SH_MEM_CONFIG \ 263 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 264 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 265 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 266 267 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 268 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 273 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 274 struct amdgpu_cu_info *cu_info); 275 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 276 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 277 u32 sh_num, u32 instance, int xcc_id); 278 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 279 280 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 359 return; 360 } 361 362 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 363 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 364 PACKET3_UNMAP_QUEUES_ACTION(action) | 365 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 366 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 367 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 368 amdgpu_ring_write(kiq_ring, 369 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 370 371 if (action == PREEMPT_QUEUES_NO_UNMAP) { 372 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 373 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, seq); 375 } else { 376 amdgpu_ring_write(kiq_ring, 0); 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 } 380 } 381 382 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 383 struct amdgpu_ring *ring, 384 u64 addr, u64 seq) 385 { 386 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 387 388 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 389 amdgpu_ring_write(kiq_ring, 390 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 391 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 392 PACKET3_QUERY_STATUS_COMMAND(2)); 393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 394 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 395 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 396 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 397 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 400 } 401 402 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 403 uint16_t pasid, 404 uint32_t flush_type, 405 bool all_hub) 406 { 407 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 408 } 409 410 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 411 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 412 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 413 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 414 .kiq_query_status = gfx_v12_0_kiq_query_status, 415 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 416 .set_resources_size = 8, 417 .map_queues_size = 7, 418 .unmap_queues_size = 6, 419 .query_status_size = 7, 420 .invalidate_tlbs_size = 2, 421 }; 422 423 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 424 { 425 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 426 } 427 428 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 429 int mem_space, int opt, uint32_t addr0, 430 uint32_t addr1, uint32_t ref, 431 uint32_t mask, uint32_t inv) 432 { 433 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 434 amdgpu_ring_write(ring, 435 /* memory (1) or register (0) */ 436 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 437 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 438 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 439 WAIT_REG_MEM_ENGINE(eng_sel))); 440 441 if (mem_space) 442 BUG_ON(addr0 & 0x3); /* Dword align */ 443 amdgpu_ring_write(ring, addr0); 444 amdgpu_ring_write(ring, addr1); 445 amdgpu_ring_write(ring, ref); 446 amdgpu_ring_write(ring, mask); 447 amdgpu_ring_write(ring, inv); /* poll interval */ 448 } 449 450 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 454 uint32_t tmp = 0; 455 unsigned i; 456 int r; 457 458 WREG32(scratch, 0xCAFEDEAD); 459 r = amdgpu_ring_alloc(ring, 5); 460 if (r) { 461 dev_err(adev->dev, 462 "amdgpu: cp failed to lock ring %d (%d).\n", 463 ring->idx, r); 464 return r; 465 } 466 467 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 468 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 469 } else { 470 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 471 amdgpu_ring_write(ring, scratch - 472 PACKET3_SET_UCONFIG_REG_START); 473 amdgpu_ring_write(ring, 0xDEADBEEF); 474 } 475 amdgpu_ring_commit(ring); 476 477 for (i = 0; i < adev->usec_timeout; i++) { 478 tmp = RREG32(scratch); 479 if (tmp == 0xDEADBEEF) 480 break; 481 if (amdgpu_emu_mode == 1) 482 msleep(1); 483 else 484 udelay(1); 485 } 486 487 if (i >= adev->usec_timeout) 488 r = -ETIMEDOUT; 489 return r; 490 } 491 492 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 struct amdgpu_ib ib; 496 struct dma_fence *f = NULL; 497 unsigned index; 498 uint64_t gpu_addr; 499 volatile uint32_t *cpu_ptr; 500 long r; 501 502 /* MES KIQ fw hasn't indirect buffer support for now */ 503 if (adev->enable_mes_kiq && 504 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 505 return 0; 506 507 memset(&ib, 0, sizeof(ib)); 508 509 r = amdgpu_device_wb_get(adev, &index); 510 if (r) 511 return r; 512 513 gpu_addr = adev->wb.gpu_addr + (index * 4); 514 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 515 cpu_ptr = &adev->wb.wb[index]; 516 517 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 518 if (r) { 519 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 520 goto err1; 521 } 522 523 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 524 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 525 ib.ptr[2] = lower_32_bits(gpu_addr); 526 ib.ptr[3] = upper_32_bits(gpu_addr); 527 ib.ptr[4] = 0xDEADBEEF; 528 ib.length_dw = 5; 529 530 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 531 if (r) 532 goto err2; 533 534 r = dma_fence_wait_timeout(f, false, timeout); 535 if (r == 0) { 536 r = -ETIMEDOUT; 537 goto err2; 538 } else if (r < 0) { 539 goto err2; 540 } 541 542 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 543 r = 0; 544 else 545 r = -EINVAL; 546 err2: 547 amdgpu_ib_free(&ib, NULL); 548 dma_fence_put(f); 549 err1: 550 amdgpu_device_wb_free(adev, index); 551 return r; 552 } 553 554 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 555 { 556 amdgpu_ucode_release(&adev->gfx.pfp_fw); 557 amdgpu_ucode_release(&adev->gfx.me_fw); 558 amdgpu_ucode_release(&adev->gfx.rlc_fw); 559 amdgpu_ucode_release(&adev->gfx.mec_fw); 560 561 kfree(adev->gfx.rlc.register_list_format); 562 } 563 564 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 565 { 566 const struct psp_firmware_header_v1_0 *toc_hdr; 567 int err = 0; 568 569 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 570 AMDGPU_UCODE_REQUIRED, 571 "amdgpu/%s_toc.bin", ucode_prefix); 572 if (err) 573 goto out; 574 575 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 576 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 577 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 578 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 579 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 580 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 581 return 0; 582 out: 583 amdgpu_ucode_release(&adev->psp.toc_fw); 584 return err; 585 } 586 587 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 588 { 589 char ucode_prefix[15]; 590 int err; 591 const struct rlc_firmware_header_v2_0 *rlc_hdr; 592 uint16_t version_major; 593 uint16_t version_minor; 594 595 DRM_DEBUG("\n"); 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 600 AMDGPU_UCODE_REQUIRED, 601 "amdgpu/%s_pfp.bin", ucode_prefix); 602 if (err) 603 goto out; 604 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 606 607 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 608 AMDGPU_UCODE_REQUIRED, 609 "amdgpu/%s_me.bin", ucode_prefix); 610 if (err) 611 goto out; 612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 614 615 if (!amdgpu_sriov_vf(adev)) { 616 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 617 AMDGPU_UCODE_REQUIRED, 618 "amdgpu/%s_rlc.bin", ucode_prefix); 619 if (err) 620 goto out; 621 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 622 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 623 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 624 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 625 if (err) 626 goto out; 627 } 628 629 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 630 AMDGPU_UCODE_REQUIRED, 631 "amdgpu/%s_mec.bin", ucode_prefix); 632 if (err) 633 goto out; 634 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 635 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 636 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 637 638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 639 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 640 641 /* only one MEC for gfx 12 */ 642 adev->gfx.mec2_fw = NULL; 643 644 if (adev->gfx.imu.funcs) { 645 if (adev->gfx.imu.funcs->init_microcode) { 646 err = adev->gfx.imu.funcs->init_microcode(adev); 647 if (err) 648 dev_err(adev->dev, "Failed to load imu firmware!\n"); 649 } 650 } 651 652 out: 653 if (err) { 654 amdgpu_ucode_release(&adev->gfx.pfp_fw); 655 amdgpu_ucode_release(&adev->gfx.me_fw); 656 amdgpu_ucode_release(&adev->gfx.rlc_fw); 657 amdgpu_ucode_release(&adev->gfx.mec_fw); 658 } 659 660 return err; 661 } 662 663 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 664 { 665 u32 count = 0; 666 const struct cs_section_def *sect = NULL; 667 const struct cs_extent_def *ext = NULL; 668 669 count += 1; 670 671 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 672 if (sect->id == SECT_CONTEXT) { 673 for (ext = sect->section; ext->extent != NULL; ++ext) 674 count += 2 + ext->reg_count; 675 } else 676 return 0; 677 } 678 679 return count; 680 } 681 682 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, 683 volatile u32 *buffer) 684 { 685 u32 count = 0, clustercount = 0, i; 686 const struct cs_section_def *sect = NULL; 687 const struct cs_extent_def *ext = NULL; 688 689 if (adev->gfx.rlc.cs_data == NULL) 690 return; 691 if (buffer == NULL) 692 return; 693 694 count += 1; 695 696 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 697 if (sect->id == SECT_CONTEXT) { 698 for (ext = sect->section; ext->extent != NULL; ++ext) { 699 clustercount++; 700 buffer[count++] = ext->reg_count; 701 buffer[count++] = ext->reg_index; 702 703 for (i = 0; i < ext->reg_count; i++) 704 buffer[count++] = cpu_to_le32(ext->extent[i]); 705 } 706 } else 707 return; 708 } 709 710 buffer[0] = clustercount; 711 } 712 713 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 714 { 715 /* clear state block */ 716 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 717 &adev->gfx.rlc.clear_state_gpu_addr, 718 (void **)&adev->gfx.rlc.cs_ptr); 719 720 /* jump table block */ 721 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 722 &adev->gfx.rlc.cp_table_gpu_addr, 723 (void **)&adev->gfx.rlc.cp_table_ptr); 724 } 725 726 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 727 { 728 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 729 730 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 731 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 732 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 733 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 734 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 735 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 736 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 737 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 738 adev->gfx.rlc.rlcg_reg_access_supported = true; 739 } 740 741 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 742 { 743 const struct cs_section_def *cs_data; 744 int r; 745 746 adev->gfx.rlc.cs_data = gfx12_cs_data; 747 748 cs_data = adev->gfx.rlc.cs_data; 749 750 if (cs_data) { 751 /* init clear state block */ 752 r = amdgpu_gfx_rlc_init_csb(adev); 753 if (r) 754 return r; 755 } 756 757 /* init spm vmid with 0xf */ 758 if (adev->gfx.rlc.funcs->update_spm_vmid) 759 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 760 761 return 0; 762 } 763 764 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 765 { 766 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 767 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 768 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 769 } 770 771 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 772 { 773 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 774 775 amdgpu_gfx_graphics_queue_acquire(adev); 776 } 777 778 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 779 { 780 int r; 781 u32 *hpd; 782 size_t mec_hpd_size; 783 784 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 785 786 /* take ownership of the relevant compute queues */ 787 amdgpu_gfx_compute_queue_acquire(adev); 788 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 789 790 if (mec_hpd_size) { 791 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 792 AMDGPU_GEM_DOMAIN_GTT, 793 &adev->gfx.mec.hpd_eop_obj, 794 &adev->gfx.mec.hpd_eop_gpu_addr, 795 (void **)&hpd); 796 if (r) { 797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 798 gfx_v12_0_mec_fini(adev); 799 return r; 800 } 801 802 memset(hpd, 0, mec_hpd_size); 803 804 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 805 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 806 } 807 808 return 0; 809 } 810 811 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 812 { 813 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 814 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 815 (address << SQ_IND_INDEX__INDEX__SHIFT)); 816 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 817 } 818 819 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 820 uint32_t thread, uint32_t regno, 821 uint32_t num, uint32_t *out) 822 { 823 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 824 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 825 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 826 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 827 (SQ_IND_INDEX__AUTO_INCR_MASK)); 828 while (num--) 829 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 830 } 831 832 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 833 uint32_t xcc_id, 834 uint32_t simd, uint32_t wave, 835 uint32_t *dst, int *no_fields) 836 { 837 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 838 * field when performing a select_se_sh so it should be 839 * zero here */ 840 WARN_ON(simd != 0); 841 842 /* type 4 wave data */ 843 dst[(*no_fields)++] = 4; 844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 867 } 868 869 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 870 uint32_t xcc_id, uint32_t simd, 871 uint32_t wave, uint32_t start, 872 uint32_t size, uint32_t *dst) 873 { 874 WARN_ON(simd != 0); 875 876 wave_read_regs( 877 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 878 dst); 879 } 880 881 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 882 uint32_t xcc_id, uint32_t simd, 883 uint32_t wave, uint32_t thread, 884 uint32_t start, uint32_t size, 885 uint32_t *dst) 886 { 887 wave_read_regs( 888 adev, wave, thread, 889 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 890 } 891 892 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 893 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 894 { 895 soc24_grbm_select(adev, me, pipe, q, vm); 896 } 897 898 /* all sizes are in bytes */ 899 #define MQD_SHADOW_BASE_SIZE 73728 900 #define MQD_SHADOW_BASE_ALIGNMENT 256 901 #define MQD_FWWORKAREA_SIZE 484 902 #define MQD_FWWORKAREA_ALIGNMENT 256 903 904 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 905 struct amdgpu_gfx_shadow_info *shadow_info) 906 { 907 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 908 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 909 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 910 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 911 } 912 913 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 914 struct amdgpu_gfx_shadow_info *shadow_info, 915 bool skip_check) 916 { 917 if (adev->gfx.cp_gfx_shadow || skip_check) { 918 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 919 return 0; 920 } 921 922 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 923 return -EINVAL; 924 } 925 926 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 927 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 928 .select_se_sh = &gfx_v12_0_select_se_sh, 929 .read_wave_data = &gfx_v12_0_read_wave_data, 930 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 931 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 932 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 933 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 934 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 935 }; 936 937 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 938 { 939 940 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 941 case IP_VERSION(12, 0, 0): 942 case IP_VERSION(12, 0, 1): 943 adev->gfx.config.max_hw_contexts = 8; 944 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 945 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 946 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 947 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 948 break; 949 default: 950 BUG(); 951 break; 952 } 953 954 return 0; 955 } 956 957 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 958 int me, int pipe, int queue) 959 { 960 int r; 961 struct amdgpu_ring *ring; 962 unsigned int irq_type; 963 964 ring = &adev->gfx.gfx_ring[ring_id]; 965 966 ring->me = me; 967 ring->pipe = pipe; 968 ring->queue = queue; 969 970 ring->ring_obj = NULL; 971 ring->use_doorbell = true; 972 973 if (!ring_id) 974 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 975 else 976 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 977 ring->vm_hub = AMDGPU_GFXHUB(0); 978 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 979 980 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 981 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 982 AMDGPU_RING_PRIO_DEFAULT, NULL); 983 if (r) 984 return r; 985 return 0; 986 } 987 988 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 989 int mec, int pipe, int queue) 990 { 991 int r; 992 unsigned irq_type; 993 struct amdgpu_ring *ring; 994 unsigned int hw_prio; 995 996 ring = &adev->gfx.compute_ring[ring_id]; 997 998 /* mec0 is me1 */ 999 ring->me = mec + 1; 1000 ring->pipe = pipe; 1001 ring->queue = queue; 1002 1003 ring->ring_obj = NULL; 1004 ring->use_doorbell = true; 1005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1007 + (ring_id * GFX12_MEC_HPD_SIZE); 1008 ring->vm_hub = AMDGPU_GFXHUB(0); 1009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1010 1011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1013 + ring->pipe; 1014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1015 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1017 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1018 hw_prio, NULL); 1019 if (r) 1020 return r; 1021 1022 return 0; 1023 } 1024 1025 static struct { 1026 SOC24_FIRMWARE_ID id; 1027 unsigned int offset; 1028 unsigned int size; 1029 unsigned int size_x16; 1030 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1031 1032 #define RLC_TOC_OFFSET_DWUNIT 8 1033 #define RLC_SIZE_MULTIPLE 1024 1034 #define RLC_TOC_UMF_SIZE_inM 23ULL 1035 #define RLC_TOC_FORMAT_API 165ULL 1036 1037 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1038 { 1039 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1040 1041 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1042 rlc_autoload_info[ucode->id].id = ucode->id; 1043 rlc_autoload_info[ucode->id].offset = 1044 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1045 rlc_autoload_info[ucode->id].size = 1046 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1047 ucode->size * 4; 1048 ucode++; 1049 } 1050 } 1051 1052 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1053 { 1054 uint32_t total_size = 0; 1055 SOC24_FIRMWARE_ID id; 1056 1057 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1058 1059 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1060 total_size += rlc_autoload_info[id].size; 1061 1062 /* In case the offset in rlc toc ucode is aligned */ 1063 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1064 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1065 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1066 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1067 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1068 1069 return total_size; 1070 } 1071 1072 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1073 { 1074 int r; 1075 uint32_t total_size; 1076 1077 total_size = gfx_v12_0_calc_toc_total_size(adev); 1078 1079 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1080 AMDGPU_GEM_DOMAIN_VRAM, 1081 &adev->gfx.rlc.rlc_autoload_bo, 1082 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1083 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1084 1085 if (r) { 1086 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1087 return r; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1094 SOC24_FIRMWARE_ID id, 1095 const void *fw_data, 1096 uint32_t fw_size) 1097 { 1098 uint32_t toc_offset; 1099 uint32_t toc_fw_size; 1100 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1101 1102 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1103 return; 1104 1105 toc_offset = rlc_autoload_info[id].offset; 1106 toc_fw_size = rlc_autoload_info[id].size; 1107 1108 if (fw_size == 0) 1109 fw_size = toc_fw_size; 1110 1111 if (fw_size > toc_fw_size) 1112 fw_size = toc_fw_size; 1113 1114 memcpy(ptr + toc_offset, fw_data, fw_size); 1115 1116 if (fw_size < toc_fw_size) 1117 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1118 } 1119 1120 static void 1121 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1122 { 1123 void *data; 1124 uint32_t size; 1125 uint32_t *toc_ptr; 1126 1127 data = adev->psp.toc.start_addr; 1128 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1129 1130 toc_ptr = (uint32_t *)data + size / 4 - 2; 1131 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1132 1133 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1134 data, size); 1135 } 1136 1137 static void 1138 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1139 { 1140 const __le32 *fw_data; 1141 uint32_t fw_size; 1142 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1143 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1144 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1145 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1146 uint16_t version_major, version_minor; 1147 1148 /* pfp ucode */ 1149 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1150 adev->gfx.pfp_fw->data; 1151 /* instruction */ 1152 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1153 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1154 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1155 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1156 fw_data, fw_size); 1157 /* data */ 1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1159 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1160 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1162 fw_data, fw_size); 1163 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1164 fw_data, fw_size); 1165 /* me ucode */ 1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1167 adev->gfx.me_fw->data; 1168 /* instruction */ 1169 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1173 fw_data, fw_size); 1174 /* data */ 1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1176 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1179 fw_data, fw_size); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1181 fw_data, fw_size); 1182 /* mec ucode */ 1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1184 adev->gfx.mec_fw->data; 1185 /* instruction */ 1186 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1190 fw_data, fw_size); 1191 /* data */ 1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1193 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1196 fw_data, fw_size); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1198 fw_data, fw_size); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1200 fw_data, fw_size); 1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1202 fw_data, fw_size); 1203 1204 /* rlc ucode */ 1205 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1206 adev->gfx.rlc_fw->data; 1207 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1208 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1209 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1210 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1211 fw_data, fw_size); 1212 1213 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1214 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1215 if (version_major == 2) { 1216 if (version_minor >= 1) { 1217 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1218 1219 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1220 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1221 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1222 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1223 fw_data, fw_size); 1224 1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1226 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1229 fw_data, fw_size); 1230 } 1231 if (version_minor >= 2) { 1232 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1233 1234 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1235 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1236 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1237 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1238 fw_data, fw_size); 1239 1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1241 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1244 fw_data, fw_size); 1245 } 1246 } 1247 } 1248 1249 static void 1250 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1251 { 1252 const __le32 *fw_data; 1253 uint32_t fw_size; 1254 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1255 1256 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1257 adev->sdma.instance[0].fw->data; 1258 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1259 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1260 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1261 1262 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1263 fw_data, fw_size); 1264 } 1265 1266 static void 1267 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1268 { 1269 const __le32 *fw_data; 1270 unsigned fw_size; 1271 const struct mes_firmware_header_v1_0 *mes_hdr; 1272 int pipe, ucode_id, data_id; 1273 1274 for (pipe = 0; pipe < 2; pipe++) { 1275 if (pipe == 0) { 1276 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1277 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1278 } else { 1279 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1280 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1281 } 1282 1283 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1284 adev->mes.fw[pipe]->data; 1285 1286 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1287 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1288 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1289 1290 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1291 1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1293 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1295 1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1297 } 1298 } 1299 1300 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1301 { 1302 uint32_t rlc_g_offset, rlc_g_size; 1303 uint64_t gpu_addr; 1304 uint32_t data; 1305 1306 /* RLC autoload sequence 2: copy ucode */ 1307 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1308 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1309 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1310 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1311 1312 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1313 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1314 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1315 1316 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1317 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1318 1319 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1320 1321 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1322 /* RLC autoload sequence 3: load IMU fw */ 1323 if (adev->gfx.imu.funcs->load_microcode) 1324 adev->gfx.imu.funcs->load_microcode(adev); 1325 /* RLC autoload sequence 4 init IMU fw */ 1326 if (adev->gfx.imu.funcs->setup_imu) 1327 adev->gfx.imu.funcs->setup_imu(adev); 1328 if (adev->gfx.imu.funcs->start_imu) 1329 adev->gfx.imu.funcs->start_imu(adev); 1330 1331 /* RLC autoload sequence 5 disable gpa mode */ 1332 gfx_v12_0_disable_gpa_mode(adev); 1333 } else { 1334 /* unhalt rlc to start autoload without imu */ 1335 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1336 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1337 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1338 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1339 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1346 { 1347 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1348 uint32_t *ptr; 1349 uint32_t inst; 1350 1351 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1352 if (!ptr) { 1353 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1354 adev->gfx.ip_dump_core = NULL; 1355 } else { 1356 adev->gfx.ip_dump_core = ptr; 1357 } 1358 1359 /* Allocate memory for compute queue registers for all the instances */ 1360 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1361 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1362 adev->gfx.mec.num_queue_per_pipe; 1363 1364 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1365 if (!ptr) { 1366 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1367 adev->gfx.ip_dump_compute_queues = NULL; 1368 } else { 1369 adev->gfx.ip_dump_compute_queues = ptr; 1370 } 1371 1372 /* Allocate memory for gfx queue registers for all the instances */ 1373 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1374 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1375 adev->gfx.me.num_queue_per_pipe; 1376 1377 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1378 if (!ptr) { 1379 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1380 adev->gfx.ip_dump_gfx_queues = NULL; 1381 } else { 1382 adev->gfx.ip_dump_gfx_queues = ptr; 1383 } 1384 } 1385 1386 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1387 { 1388 int i, j, k, r, ring_id = 0; 1389 unsigned num_compute_rings; 1390 int xcc_id = 0; 1391 struct amdgpu_device *adev = ip_block->adev; 1392 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1393 1394 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1395 1396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1397 case IP_VERSION(12, 0, 0): 1398 case IP_VERSION(12, 0, 1): 1399 adev->gfx.me.num_me = 1; 1400 adev->gfx.me.num_pipe_per_me = 1; 1401 adev->gfx.me.num_queue_per_pipe = 8; 1402 adev->gfx.mec.num_mec = 1; 1403 adev->gfx.mec.num_pipe_per_mec = 2; 1404 adev->gfx.mec.num_queue_per_pipe = 4; 1405 break; 1406 default: 1407 adev->gfx.me.num_me = 1; 1408 adev->gfx.me.num_pipe_per_me = 1; 1409 adev->gfx.me.num_queue_per_pipe = 1; 1410 adev->gfx.mec.num_mec = 1; 1411 adev->gfx.mec.num_pipe_per_mec = 4; 1412 adev->gfx.mec.num_queue_per_pipe = 8; 1413 break; 1414 } 1415 1416 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1417 case IP_VERSION(12, 0, 0): 1418 case IP_VERSION(12, 0, 1): 1419 if (!adev->gfx.disable_uq && 1420 adev->gfx.me_fw_version >= 2780 && 1421 adev->gfx.pfp_fw_version >= 2840 && 1422 adev->gfx.mec_fw_version >= 3050 && 1423 adev->mes.fw_version[0] >= 123) { 1424 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1425 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1426 } 1427 break; 1428 default: 1429 break; 1430 } 1431 1432 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1433 case IP_VERSION(12, 0, 0): 1434 case IP_VERSION(12, 0, 1): 1435 if (adev->gfx.me_fw_version >= 2480 && 1436 adev->gfx.pfp_fw_version >= 2530 && 1437 adev->gfx.mec_fw_version >= 2680 && 1438 adev->mes.fw_version[0] >= 100) 1439 adev->gfx.enable_cleaner_shader = true; 1440 break; 1441 default: 1442 adev->gfx.enable_cleaner_shader = false; 1443 break; 1444 } 1445 1446 if (adev->gfx.num_compute_rings) { 1447 /* recalculate compute rings to use based on hardware configuration */ 1448 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1449 adev->gfx.mec.num_queue_per_pipe) / 2; 1450 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1451 num_compute_rings); 1452 } 1453 1454 /* EOP Event */ 1455 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1456 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1457 &adev->gfx.eop_irq); 1458 if (r) 1459 return r; 1460 1461 /* Bad opcode Event */ 1462 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1463 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1464 &adev->gfx.bad_op_irq); 1465 if (r) 1466 return r; 1467 1468 /* Privileged reg */ 1469 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1470 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1471 &adev->gfx.priv_reg_irq); 1472 if (r) 1473 return r; 1474 1475 /* Privileged inst */ 1476 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1477 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1478 &adev->gfx.priv_inst_irq); 1479 if (r) 1480 return r; 1481 1482 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1483 1484 gfx_v12_0_me_init(adev); 1485 1486 r = gfx_v12_0_rlc_init(adev); 1487 if (r) { 1488 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1489 return r; 1490 } 1491 1492 r = gfx_v12_0_mec_init(adev); 1493 if (r) { 1494 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1495 return r; 1496 } 1497 1498 if (adev->gfx.num_gfx_rings) { 1499 /* set up the gfx ring */ 1500 for (i = 0; i < adev->gfx.me.num_me; i++) { 1501 for (j = 0; j < num_queue_per_pipe; j++) { 1502 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1503 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1504 continue; 1505 1506 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1507 i, k, j); 1508 if (r) 1509 return r; 1510 ring_id++; 1511 } 1512 } 1513 } 1514 } 1515 1516 if (adev->gfx.num_compute_rings) { 1517 ring_id = 0; 1518 /* set up the compute queues - allocate horizontally across pipes */ 1519 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1520 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1521 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1522 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1523 0, i, k, j)) 1524 continue; 1525 1526 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1527 i, k, j); 1528 if (r) 1529 return r; 1530 1531 ring_id++; 1532 } 1533 } 1534 } 1535 } 1536 1537 adev->gfx.gfx_supported_reset = 1538 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1539 adev->gfx.compute_supported_reset = 1540 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1541 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1542 case IP_VERSION(12, 0, 0): 1543 case IP_VERSION(12, 0, 1): 1544 if ((adev->gfx.me_fw_version >= 2660) && 1545 (adev->gfx.mec_fw_version >= 2920)) { 1546 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1547 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1548 } 1549 } 1550 1551 if (!adev->enable_mes_kiq) { 1552 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1553 if (r) { 1554 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1555 return r; 1556 } 1557 1558 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1559 if (r) 1560 return r; 1561 } 1562 1563 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1564 if (r) 1565 return r; 1566 1567 /* allocate visible FB for rlc auto-loading fw */ 1568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1569 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1570 if (r) 1571 return r; 1572 } 1573 1574 r = gfx_v12_0_gpu_early_init(adev); 1575 if (r) 1576 return r; 1577 1578 gfx_v12_0_alloc_ip_dump(adev); 1579 1580 r = amdgpu_gfx_sysfs_init(adev); 1581 if (r) 1582 return r; 1583 1584 return 0; 1585 } 1586 1587 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1588 { 1589 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1590 &adev->gfx.pfp.pfp_fw_gpu_addr, 1591 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1592 1593 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1594 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1595 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1596 } 1597 1598 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1599 { 1600 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1601 &adev->gfx.me.me_fw_gpu_addr, 1602 (void **)&adev->gfx.me.me_fw_ptr); 1603 1604 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1605 &adev->gfx.me.me_fw_data_gpu_addr, 1606 (void **)&adev->gfx.me.me_fw_data_ptr); 1607 } 1608 1609 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1610 { 1611 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1612 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1613 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1614 } 1615 1616 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1617 { 1618 int i; 1619 struct amdgpu_device *adev = ip_block->adev; 1620 1621 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1622 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1623 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1624 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1625 1626 amdgpu_gfx_mqd_sw_fini(adev, 0); 1627 1628 if (!adev->enable_mes_kiq) { 1629 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1630 amdgpu_gfx_kiq_fini(adev, 0); 1631 } 1632 1633 gfx_v12_0_pfp_fini(adev); 1634 gfx_v12_0_me_fini(adev); 1635 gfx_v12_0_rlc_fini(adev); 1636 gfx_v12_0_mec_fini(adev); 1637 1638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1639 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1640 1641 gfx_v12_0_free_microcode(adev); 1642 1643 amdgpu_gfx_sysfs_fini(adev); 1644 1645 kfree(adev->gfx.ip_dump_core); 1646 kfree(adev->gfx.ip_dump_compute_queues); 1647 kfree(adev->gfx.ip_dump_gfx_queues); 1648 1649 return 0; 1650 } 1651 1652 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1653 u32 sh_num, u32 instance, int xcc_id) 1654 { 1655 u32 data; 1656 1657 if (instance == 0xffffffff) 1658 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1659 INSTANCE_BROADCAST_WRITES, 1); 1660 else 1661 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1662 instance); 1663 1664 if (se_num == 0xffffffff) 1665 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1666 1); 1667 else 1668 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1669 1670 if (sh_num == 0xffffffff) 1671 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1672 1); 1673 else 1674 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1675 1676 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1677 } 1678 1679 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1680 { 1681 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1682 1683 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1684 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1685 GRBM_CC_GC_SA_UNIT_DISABLE, 1686 SA_DISABLE); 1687 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1688 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1689 GRBM_GC_USER_SA_UNIT_DISABLE, 1690 SA_DISABLE); 1691 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1692 adev->gfx.config.max_shader_engines); 1693 1694 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1695 } 1696 1697 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1698 { 1699 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1700 u32 rb_mask; 1701 1702 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1703 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1704 CC_RB_BACKEND_DISABLE, 1705 BACKEND_DISABLE); 1706 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1707 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1708 GC_USER_RB_BACKEND_DISABLE, 1709 BACKEND_DISABLE); 1710 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1711 adev->gfx.config.max_shader_engines); 1712 1713 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1714 } 1715 1716 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1717 { 1718 u32 rb_bitmap_per_sa; 1719 u32 rb_bitmap_width_per_sa; 1720 u32 max_sa; 1721 u32 active_sa_bitmap; 1722 u32 global_active_rb_bitmap; 1723 u32 active_rb_bitmap = 0; 1724 u32 i; 1725 1726 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1727 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1728 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1729 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1730 1731 /* generate active rb bitmap according to active sa bitmap */ 1732 max_sa = adev->gfx.config.max_shader_engines * 1733 adev->gfx.config.max_sh_per_se; 1734 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1735 adev->gfx.config.max_sh_per_se; 1736 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1737 1738 for (i = 0; i < max_sa; i++) { 1739 if (active_sa_bitmap & (1 << i)) 1740 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1741 } 1742 1743 active_rb_bitmap &= global_active_rb_bitmap; 1744 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1745 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1746 } 1747 1748 #define LDS_APP_BASE 0x1 1749 #define SCRATCH_APP_BASE 0x2 1750 1751 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1752 { 1753 int i; 1754 uint32_t sh_mem_bases; 1755 uint32_t data; 1756 1757 /* 1758 * Configure apertures: 1759 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1760 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1761 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1762 */ 1763 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1764 SCRATCH_APP_BASE; 1765 1766 mutex_lock(&adev->srbm_mutex); 1767 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1768 soc24_grbm_select(adev, 0, 0, 0, i); 1769 /* CP and shaders */ 1770 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1771 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1772 1773 /* Enable trap for each kfd vmid. */ 1774 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1775 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1776 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1777 } 1778 soc24_grbm_select(adev, 0, 0, 0, 0); 1779 mutex_unlock(&adev->srbm_mutex); 1780 } 1781 1782 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1783 { 1784 /* TODO: harvest feature to be added later. */ 1785 } 1786 1787 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1788 { 1789 } 1790 1791 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1792 { 1793 u32 tmp; 1794 int i; 1795 1796 if (!amdgpu_sriov_vf(adev)) 1797 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1798 1799 gfx_v12_0_setup_rb(adev); 1800 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1801 gfx_v12_0_get_tcc_info(adev); 1802 adev->gfx.config.pa_sc_tile_steering_override = 0; 1803 1804 /* XXX SH_MEM regs */ 1805 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1806 mutex_lock(&adev->srbm_mutex); 1807 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1808 soc24_grbm_select(adev, 0, 0, 0, i); 1809 /* CP and shaders */ 1810 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1811 if (i != 0) { 1812 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1813 (adev->gmc.private_aperture_start >> 48)); 1814 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1815 (adev->gmc.shared_aperture_start >> 48)); 1816 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1817 } 1818 } 1819 soc24_grbm_select(adev, 0, 0, 0, 0); 1820 1821 mutex_unlock(&adev->srbm_mutex); 1822 1823 gfx_v12_0_init_compute_vmid(adev); 1824 } 1825 1826 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1827 int me, int pipe) 1828 { 1829 if (me != 0) 1830 return 0; 1831 1832 switch (pipe) { 1833 case 0: 1834 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1835 default: 1836 return 0; 1837 } 1838 } 1839 1840 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1841 int me, int pipe) 1842 { 1843 /* 1844 * amdgpu controls only the first MEC. That's why this function only 1845 * handles the setting of interrupts for this specific MEC. All other 1846 * pipes' interrupts are set by amdkfd. 1847 */ 1848 if (me != 1) 1849 return 0; 1850 1851 switch (pipe) { 1852 case 0: 1853 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1854 case 1: 1855 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1856 default: 1857 return 0; 1858 } 1859 } 1860 1861 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1862 bool enable) 1863 { 1864 u32 tmp, cp_int_cntl_reg; 1865 int i, j; 1866 1867 if (amdgpu_sriov_vf(adev)) 1868 return; 1869 1870 for (i = 0; i < adev->gfx.me.num_me; i++) { 1871 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1872 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1873 1874 if (cp_int_cntl_reg) { 1875 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1876 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1877 enable ? 1 : 0); 1878 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1879 enable ? 1 : 0); 1880 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1881 enable ? 1 : 0); 1882 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1883 enable ? 1 : 0); 1884 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1885 } 1886 } 1887 } 1888 } 1889 1890 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1891 { 1892 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1893 1894 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1895 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1896 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1897 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1898 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1899 1900 return 0; 1901 } 1902 1903 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1904 { 1905 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1906 1907 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1908 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1909 } 1910 1911 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1912 { 1913 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1914 udelay(50); 1915 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1916 udelay(50); 1917 } 1918 1919 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1920 bool enable) 1921 { 1922 uint32_t rlc_pg_cntl; 1923 1924 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1925 1926 if (!enable) { 1927 /* RLC_PG_CNTL[23] = 0 (default) 1928 * RLC will wait for handshake acks with SMU 1929 * GFXOFF will be enabled 1930 * RLC_PG_CNTL[23] = 1 1931 * RLC will not issue any message to SMU 1932 * hence no handshake between SMU & RLC 1933 * GFXOFF will be disabled 1934 */ 1935 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1936 } else 1937 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1938 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1939 } 1940 1941 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1942 { 1943 /* TODO: enable rlc & smu handshake until smu 1944 * and gfxoff feature works as expected */ 1945 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1946 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1947 1948 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1949 udelay(50); 1950 } 1951 1952 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1953 { 1954 uint32_t tmp; 1955 1956 /* enable Save Restore Machine */ 1957 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1958 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1959 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1960 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1961 } 1962 1963 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1964 { 1965 const struct rlc_firmware_header_v2_0 *hdr; 1966 const __le32 *fw_data; 1967 unsigned i, fw_size; 1968 1969 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1970 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1971 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1972 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1973 1974 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1975 RLCG_UCODE_LOADING_START_ADDRESS); 1976 1977 for (i = 0; i < fw_size; i++) 1978 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1979 le32_to_cpup(fw_data++)); 1980 1981 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1982 } 1983 1984 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1985 { 1986 const struct rlc_firmware_header_v2_2 *hdr; 1987 const __le32 *fw_data; 1988 unsigned i, fw_size; 1989 u32 tmp; 1990 1991 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1992 1993 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1994 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1995 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1996 1997 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1998 1999 for (i = 0; i < fw_size; i++) { 2000 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2001 msleep(1); 2002 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2003 le32_to_cpup(fw_data++)); 2004 } 2005 2006 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2007 2008 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2009 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2010 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2011 2012 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2013 for (i = 0; i < fw_size; i++) { 2014 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2015 msleep(1); 2016 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2017 le32_to_cpup(fw_data++)); 2018 } 2019 2020 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2021 2022 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2023 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2024 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2025 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2026 } 2027 2028 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2029 { 2030 const struct rlc_firmware_header_v2_0 *hdr; 2031 uint16_t version_major; 2032 uint16_t version_minor; 2033 2034 if (!adev->gfx.rlc_fw) 2035 return -EINVAL; 2036 2037 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2038 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2039 2040 version_major = le16_to_cpu(hdr->header.header_version_major); 2041 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2042 2043 if (version_major == 2) { 2044 gfx_v12_0_load_rlcg_microcode(adev); 2045 if (amdgpu_dpm == 1) { 2046 if (version_minor >= 2) 2047 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2048 } 2049 2050 return 0; 2051 } 2052 2053 return -EINVAL; 2054 } 2055 2056 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2057 { 2058 int r; 2059 2060 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2061 gfx_v12_0_init_csb(adev); 2062 2063 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2064 gfx_v12_0_rlc_enable_srm(adev); 2065 } else { 2066 if (amdgpu_sriov_vf(adev)) { 2067 gfx_v12_0_init_csb(adev); 2068 return 0; 2069 } 2070 2071 adev->gfx.rlc.funcs->stop(adev); 2072 2073 /* disable CG */ 2074 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2075 2076 /* disable PG */ 2077 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2078 2079 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2080 /* legacy rlc firmware loading */ 2081 r = gfx_v12_0_rlc_load_microcode(adev); 2082 if (r) 2083 return r; 2084 } 2085 2086 gfx_v12_0_init_csb(adev); 2087 2088 adev->gfx.rlc.funcs->start(adev); 2089 } 2090 2091 return 0; 2092 } 2093 2094 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2095 { 2096 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2097 const struct gfx_firmware_header_v2_0 *me_hdr; 2098 const struct gfx_firmware_header_v2_0 *mec_hdr; 2099 uint32_t pipe_id, tmp; 2100 2101 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2102 adev->gfx.mec_fw->data; 2103 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2104 adev->gfx.me_fw->data; 2105 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2106 adev->gfx.pfp_fw->data; 2107 2108 /* config pfp program start addr */ 2109 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2110 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2111 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2112 (pfp_hdr->ucode_start_addr_hi << 30) | 2113 (pfp_hdr->ucode_start_addr_lo >> 2)); 2114 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2115 pfp_hdr->ucode_start_addr_hi >> 2); 2116 } 2117 soc24_grbm_select(adev, 0, 0, 0, 0); 2118 2119 /* reset pfp pipe */ 2120 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2121 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2122 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2123 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2124 2125 /* clear pfp pipe reset */ 2126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2128 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2129 2130 /* config me program start addr */ 2131 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2132 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2133 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2134 (me_hdr->ucode_start_addr_hi << 30) | 2135 (me_hdr->ucode_start_addr_lo >> 2)); 2136 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2137 me_hdr->ucode_start_addr_hi>>2); 2138 } 2139 soc24_grbm_select(adev, 0, 0, 0, 0); 2140 2141 /* reset me pipe */ 2142 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2145 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2146 2147 /* clear me pipe reset */ 2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2150 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2151 2152 /* config mec program start addr */ 2153 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2154 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2155 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2156 mec_hdr->ucode_start_addr_lo >> 2 | 2157 mec_hdr->ucode_start_addr_hi << 30); 2158 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2159 mec_hdr->ucode_start_addr_hi >> 2); 2160 } 2161 soc24_grbm_select(adev, 0, 0, 0, 0); 2162 2163 /* reset mec pipe */ 2164 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2165 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2166 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2167 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2168 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2169 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2170 2171 /* clear mec pipe reset */ 2172 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2173 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2174 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2176 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2177 } 2178 2179 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2180 { 2181 const struct gfx_firmware_header_v2_0 *cp_hdr; 2182 unsigned pipe_id, tmp; 2183 2184 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2185 adev->gfx.pfp_fw->data; 2186 mutex_lock(&adev->srbm_mutex); 2187 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2188 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2189 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2190 (cp_hdr->ucode_start_addr_hi << 30) | 2191 (cp_hdr->ucode_start_addr_lo >> 2)); 2192 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2193 cp_hdr->ucode_start_addr_hi>>2); 2194 2195 /* 2196 * Program CP_ME_CNTL to reset given PIPE to take 2197 * effect of CP_PFP_PRGRM_CNTR_START. 2198 */ 2199 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2200 if (pipe_id == 0) 2201 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2202 PFP_PIPE0_RESET, 1); 2203 else 2204 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2205 PFP_PIPE1_RESET, 1); 2206 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2207 2208 /* Clear pfp pipe0 reset bit. */ 2209 if (pipe_id == 0) 2210 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2211 PFP_PIPE0_RESET, 0); 2212 else 2213 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2214 PFP_PIPE1_RESET, 0); 2215 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2216 } 2217 soc24_grbm_select(adev, 0, 0, 0, 0); 2218 mutex_unlock(&adev->srbm_mutex); 2219 } 2220 2221 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2222 { 2223 const struct gfx_firmware_header_v2_0 *cp_hdr; 2224 unsigned pipe_id, tmp; 2225 2226 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2227 adev->gfx.me_fw->data; 2228 mutex_lock(&adev->srbm_mutex); 2229 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2230 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2231 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2232 (cp_hdr->ucode_start_addr_hi << 30) | 2233 (cp_hdr->ucode_start_addr_lo >> 2) ); 2234 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2235 cp_hdr->ucode_start_addr_hi>>2); 2236 2237 /* 2238 * Program CP_ME_CNTL to reset given PIPE to take 2239 * effect of CP_ME_PRGRM_CNTR_START. 2240 */ 2241 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2242 if (pipe_id == 0) 2243 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2244 ME_PIPE0_RESET, 1); 2245 else 2246 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2247 ME_PIPE1_RESET, 1); 2248 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2249 2250 /* Clear pfp pipe0 reset bit. */ 2251 if (pipe_id == 0) 2252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2253 ME_PIPE0_RESET, 0); 2254 else 2255 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2256 ME_PIPE1_RESET, 0); 2257 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2258 } 2259 soc24_grbm_select(adev, 0, 0, 0, 0); 2260 mutex_unlock(&adev->srbm_mutex); 2261 } 2262 2263 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2264 { 2265 const struct gfx_firmware_header_v2_0 *cp_hdr; 2266 unsigned pipe_id; 2267 2268 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2269 adev->gfx.mec_fw->data; 2270 mutex_lock(&adev->srbm_mutex); 2271 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2272 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2273 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2274 cp_hdr->ucode_start_addr_lo >> 2 | 2275 cp_hdr->ucode_start_addr_hi << 30); 2276 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2277 cp_hdr->ucode_start_addr_hi >> 2); 2278 } 2279 soc24_grbm_select(adev, 0, 0, 0, 0); 2280 mutex_unlock(&adev->srbm_mutex); 2281 } 2282 2283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2284 { 2285 uint32_t cp_status; 2286 uint32_t bootload_status; 2287 int i; 2288 2289 for (i = 0; i < adev->usec_timeout; i++) { 2290 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2291 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2292 2293 if ((cp_status == 0) && 2294 (REG_GET_FIELD(bootload_status, 2295 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2296 break; 2297 } 2298 udelay(1); 2299 if (amdgpu_emu_mode) 2300 msleep(10); 2301 } 2302 2303 if (i >= adev->usec_timeout) { 2304 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2305 return -ETIMEDOUT; 2306 } 2307 2308 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2309 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2310 gfx_v12_0_set_me_ucode_start_addr(adev); 2311 gfx_v12_0_set_mec_ucode_start_addr(adev); 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2318 { 2319 int i; 2320 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2321 2322 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2323 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2324 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2325 2326 for (i = 0; i < adev->usec_timeout; i++) { 2327 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2328 break; 2329 udelay(1); 2330 } 2331 2332 if (i >= adev->usec_timeout) 2333 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2334 2335 return 0; 2336 } 2337 2338 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2339 { 2340 int r; 2341 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2342 const __le32 *fw_ucode, *fw_data; 2343 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2344 uint32_t tmp; 2345 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2346 2347 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2348 adev->gfx.pfp_fw->data; 2349 2350 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2351 2352 /* instruction */ 2353 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2354 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2355 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2356 /* data */ 2357 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2358 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2359 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2360 2361 /* 64kb align */ 2362 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2363 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2364 &adev->gfx.pfp.pfp_fw_obj, 2365 &adev->gfx.pfp.pfp_fw_gpu_addr, 2366 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2367 if (r) { 2368 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2369 gfx_v12_0_pfp_fini(adev); 2370 return r; 2371 } 2372 2373 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2374 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2375 &adev->gfx.pfp.pfp_fw_data_obj, 2376 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2377 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2378 if (r) { 2379 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2380 gfx_v12_0_pfp_fini(adev); 2381 return r; 2382 } 2383 2384 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2385 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2386 2387 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2388 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2389 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2390 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2391 2392 if (amdgpu_emu_mode == 1) 2393 amdgpu_device_flush_hdp(adev, NULL); 2394 2395 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2396 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2397 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2398 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2399 2400 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2401 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2402 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2403 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2404 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2405 2406 /* 2407 * Programming any of the CP_PFP_IC_BASE registers 2408 * forces invalidation of the ME L1 I$. Wait for the 2409 * invalidation complete 2410 */ 2411 for (i = 0; i < usec_timeout; i++) { 2412 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2413 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2414 INVALIDATE_CACHE_COMPLETE)) 2415 break; 2416 udelay(1); 2417 } 2418 2419 if (i >= usec_timeout) { 2420 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2421 return -EINVAL; 2422 } 2423 2424 /* Prime the L1 instruction caches */ 2425 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2426 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2427 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2428 /* Waiting for cache primed*/ 2429 for (i = 0; i < usec_timeout; i++) { 2430 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2431 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2432 ICACHE_PRIMED)) 2433 break; 2434 udelay(1); 2435 } 2436 2437 if (i >= usec_timeout) { 2438 dev_err(adev->dev, "failed to prime instruction cache\n"); 2439 return -EINVAL; 2440 } 2441 2442 mutex_lock(&adev->srbm_mutex); 2443 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2444 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2445 2446 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2447 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2448 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2449 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2450 } 2451 soc24_grbm_select(adev, 0, 0, 0, 0); 2452 mutex_unlock(&adev->srbm_mutex); 2453 2454 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2455 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2456 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2457 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2458 2459 /* Invalidate the data caches */ 2460 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2461 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2462 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2463 2464 for (i = 0; i < usec_timeout; i++) { 2465 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2466 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2467 INVALIDATE_DCACHE_COMPLETE)) 2468 break; 2469 udelay(1); 2470 } 2471 2472 if (i >= usec_timeout) { 2473 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2474 return -EINVAL; 2475 } 2476 2477 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2478 2479 return 0; 2480 } 2481 2482 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2483 { 2484 int r; 2485 const struct gfx_firmware_header_v2_0 *me_hdr; 2486 const __le32 *fw_ucode, *fw_data; 2487 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2488 uint32_t tmp; 2489 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2490 2491 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2492 adev->gfx.me_fw->data; 2493 2494 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2495 2496 /* instruction */ 2497 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2498 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2499 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2500 /* data */ 2501 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2502 le32_to_cpu(me_hdr->data_offset_bytes)); 2503 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2504 2505 /* 64kb align*/ 2506 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2507 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2508 &adev->gfx.me.me_fw_obj, 2509 &adev->gfx.me.me_fw_gpu_addr, 2510 (void **)&adev->gfx.me.me_fw_ptr); 2511 if (r) { 2512 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2513 gfx_v12_0_me_fini(adev); 2514 return r; 2515 } 2516 2517 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2518 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2519 &adev->gfx.me.me_fw_data_obj, 2520 &adev->gfx.me.me_fw_data_gpu_addr, 2521 (void **)&adev->gfx.me.me_fw_data_ptr); 2522 if (r) { 2523 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2524 gfx_v12_0_me_fini(adev); 2525 return r; 2526 } 2527 2528 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2529 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2530 2531 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2532 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2533 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2534 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2535 2536 if (amdgpu_emu_mode == 1) 2537 amdgpu_device_flush_hdp(adev, NULL); 2538 2539 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2540 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2541 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2542 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2543 2544 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2545 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2546 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2547 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2548 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2549 2550 /* 2551 * Programming any of the CP_ME_IC_BASE registers 2552 * forces invalidation of the ME L1 I$. Wait for the 2553 * invalidation complete 2554 */ 2555 for (i = 0; i < usec_timeout; i++) { 2556 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2557 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2558 INVALIDATE_CACHE_COMPLETE)) 2559 break; 2560 udelay(1); 2561 } 2562 2563 if (i >= usec_timeout) { 2564 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2565 return -EINVAL; 2566 } 2567 2568 /* Prime the instruction caches */ 2569 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2570 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2571 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2572 2573 /* Waiting for instruction cache primed*/ 2574 for (i = 0; i < usec_timeout; i++) { 2575 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2576 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2577 ICACHE_PRIMED)) 2578 break; 2579 udelay(1); 2580 } 2581 2582 if (i >= usec_timeout) { 2583 dev_err(adev->dev, "failed to prime instruction cache\n"); 2584 return -EINVAL; 2585 } 2586 2587 mutex_lock(&adev->srbm_mutex); 2588 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2589 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2590 2591 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2592 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2593 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2594 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2595 } 2596 soc24_grbm_select(adev, 0, 0, 0, 0); 2597 mutex_unlock(&adev->srbm_mutex); 2598 2599 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2600 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2601 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2602 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2603 2604 /* Invalidate the data caches */ 2605 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2606 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2607 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2608 2609 for (i = 0; i < usec_timeout; i++) { 2610 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2611 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2612 INVALIDATE_DCACHE_COMPLETE)) 2613 break; 2614 udelay(1); 2615 } 2616 2617 if (i >= usec_timeout) { 2618 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2619 return -EINVAL; 2620 } 2621 2622 gfx_v12_0_set_me_ucode_start_addr(adev); 2623 2624 return 0; 2625 } 2626 2627 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2628 { 2629 int r; 2630 2631 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2632 return -EINVAL; 2633 2634 gfx_v12_0_cp_gfx_enable(adev, false); 2635 2636 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2637 if (r) { 2638 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2639 return r; 2640 } 2641 2642 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2643 if (r) { 2644 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2645 return r; 2646 } 2647 2648 return 0; 2649 } 2650 2651 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2652 { 2653 /* init the CP */ 2654 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2655 adev->gfx.config.max_hw_contexts - 1); 2656 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2657 2658 if (!amdgpu_async_gfx_ring) 2659 gfx_v12_0_cp_gfx_enable(adev, true); 2660 2661 return 0; 2662 } 2663 2664 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2665 CP_PIPE_ID pipe) 2666 { 2667 u32 tmp; 2668 2669 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2670 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2671 2672 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2673 } 2674 2675 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2676 struct amdgpu_ring *ring) 2677 { 2678 u32 tmp; 2679 2680 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2681 if (ring->use_doorbell) { 2682 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2683 DOORBELL_OFFSET, ring->doorbell_index); 2684 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2685 DOORBELL_EN, 1); 2686 } else { 2687 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2688 DOORBELL_EN, 0); 2689 } 2690 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2691 2692 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2693 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2694 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2695 2696 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2697 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2698 } 2699 2700 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2701 { 2702 struct amdgpu_ring *ring; 2703 u32 tmp; 2704 u32 rb_bufsz; 2705 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2706 2707 /* Set the write pointer delay */ 2708 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2709 2710 /* set the RB to use vmid 0 */ 2711 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2712 2713 /* Init gfx ring 0 for pipe 0 */ 2714 mutex_lock(&adev->srbm_mutex); 2715 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2716 2717 /* Set ring buffer size */ 2718 ring = &adev->gfx.gfx_ring[0]; 2719 rb_bufsz = order_base_2(ring->ring_size / 8); 2720 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2721 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2722 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2723 2724 /* Initialize the ring buffer's write pointers */ 2725 ring->wptr = 0; 2726 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2727 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2728 2729 /* set the wb address whether it's enabled or not */ 2730 rptr_addr = ring->rptr_gpu_addr; 2731 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2732 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2733 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2734 2735 wptr_gpu_addr = ring->wptr_gpu_addr; 2736 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2737 lower_32_bits(wptr_gpu_addr)); 2738 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2739 upper_32_bits(wptr_gpu_addr)); 2740 2741 mdelay(1); 2742 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2743 2744 rb_addr = ring->gpu_addr >> 8; 2745 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2746 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2747 2748 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2749 2750 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2751 mutex_unlock(&adev->srbm_mutex); 2752 2753 /* Switch to pipe 0 */ 2754 mutex_lock(&adev->srbm_mutex); 2755 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2756 mutex_unlock(&adev->srbm_mutex); 2757 2758 /* start the ring */ 2759 gfx_v12_0_cp_gfx_start(adev); 2760 return 0; 2761 } 2762 2763 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2764 { 2765 u32 data; 2766 2767 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2768 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2769 enable ? 0 : 1); 2770 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2771 enable ? 0 : 1); 2772 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2773 enable ? 0 : 1); 2774 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2775 enable ? 0 : 1); 2776 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2777 enable ? 0 : 1); 2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2779 enable ? 1 : 0); 2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2781 enable ? 1 : 0); 2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2783 enable ? 1 : 0); 2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2785 enable ? 1 : 0); 2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2787 enable ? 0 : 1); 2788 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2789 2790 adev->gfx.kiq[0].ring.sched.ready = enable; 2791 2792 udelay(50); 2793 } 2794 2795 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2796 { 2797 const struct gfx_firmware_header_v2_0 *mec_hdr; 2798 const __le32 *fw_ucode, *fw_data; 2799 u32 tmp, fw_ucode_size, fw_data_size; 2800 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2801 u32 *fw_ucode_ptr, *fw_data_ptr; 2802 int r; 2803 2804 if (!adev->gfx.mec_fw) 2805 return -EINVAL; 2806 2807 gfx_v12_0_cp_compute_enable(adev, false); 2808 2809 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2810 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2811 2812 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2813 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2814 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2815 2816 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2817 le32_to_cpu(mec_hdr->data_offset_bytes)); 2818 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2819 2820 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2821 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2822 &adev->gfx.mec.mec_fw_obj, 2823 &adev->gfx.mec.mec_fw_gpu_addr, 2824 (void **)&fw_ucode_ptr); 2825 if (r) { 2826 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2827 gfx_v12_0_mec_fini(adev); 2828 return r; 2829 } 2830 2831 r = amdgpu_bo_create_reserved(adev, 2832 ALIGN(fw_data_size, 64 * 1024) * 2833 adev->gfx.mec.num_pipe_per_mec, 2834 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2835 &adev->gfx.mec.mec_fw_data_obj, 2836 &adev->gfx.mec.mec_fw_data_gpu_addr, 2837 (void **)&fw_data_ptr); 2838 if (r) { 2839 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2840 gfx_v12_0_mec_fini(adev); 2841 return r; 2842 } 2843 2844 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2845 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2846 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2847 } 2848 2849 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2850 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2851 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2852 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2853 2854 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2855 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2856 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2857 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2858 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2859 2860 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2861 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2862 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2863 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2864 2865 mutex_lock(&adev->srbm_mutex); 2866 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2867 soc24_grbm_select(adev, 1, i, 0, 0); 2868 2869 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2870 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2871 i * ALIGN(fw_data_size, 64 * 1024))); 2872 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2873 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2874 i * ALIGN(fw_data_size, 64 * 1024))); 2875 2876 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2877 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2878 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2879 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2880 } 2881 mutex_unlock(&adev->srbm_mutex); 2882 soc24_grbm_select(adev, 0, 0, 0, 0); 2883 2884 /* Trigger an invalidation of the L1 instruction caches */ 2885 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2886 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2887 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2888 2889 /* Wait for invalidation complete */ 2890 for (i = 0; i < usec_timeout; i++) { 2891 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2892 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2893 INVALIDATE_DCACHE_COMPLETE)) 2894 break; 2895 udelay(1); 2896 } 2897 2898 if (i >= usec_timeout) { 2899 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2900 return -EINVAL; 2901 } 2902 2903 /* Trigger an invalidation of the L1 instruction caches */ 2904 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2905 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2906 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2907 2908 /* Wait for invalidation complete */ 2909 for (i = 0; i < usec_timeout; i++) { 2910 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2911 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2912 INVALIDATE_CACHE_COMPLETE)) 2913 break; 2914 udelay(1); 2915 } 2916 2917 if (i >= usec_timeout) { 2918 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2919 return -EINVAL; 2920 } 2921 2922 gfx_v12_0_set_mec_ucode_start_addr(adev); 2923 2924 return 0; 2925 } 2926 2927 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2928 { 2929 uint32_t tmp; 2930 struct amdgpu_device *adev = ring->adev; 2931 2932 /* tell RLC which is KIQ queue */ 2933 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2934 tmp &= 0xffffff00; 2935 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2936 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2937 } 2938 2939 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2940 { 2941 /* set graphics engine doorbell range */ 2942 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2943 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2944 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2945 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2946 2947 /* set compute engine doorbell range */ 2948 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2949 (adev->doorbell_index.kiq * 2) << 2); 2950 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2951 (adev->doorbell_index.userqueue_end * 2) << 2); 2952 } 2953 2954 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2955 struct amdgpu_mqd_prop *prop) 2956 { 2957 struct v12_gfx_mqd *mqd = m; 2958 uint64_t hqd_gpu_addr, wb_gpu_addr; 2959 uint32_t tmp; 2960 uint32_t rb_bufsz; 2961 2962 /* set up gfx hqd wptr */ 2963 mqd->cp_gfx_hqd_wptr = 0; 2964 mqd->cp_gfx_hqd_wptr_hi = 0; 2965 2966 /* set the pointer to the MQD */ 2967 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2968 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2969 2970 /* set up mqd control */ 2971 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2972 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2973 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2974 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2975 mqd->cp_gfx_mqd_control = tmp; 2976 2977 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2978 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2979 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2980 mqd->cp_gfx_hqd_vmid = 0; 2981 2982 /* set up default queue priority level 2983 * 0x0 = low priority, 0x1 = high priority */ 2984 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 2985 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2986 mqd->cp_gfx_hqd_queue_priority = tmp; 2987 2988 /* set up time quantum */ 2989 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 2990 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2991 mqd->cp_gfx_hqd_quantum = tmp; 2992 2993 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2994 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2995 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2996 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2997 2998 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2999 wb_gpu_addr = prop->rptr_gpu_addr; 3000 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3001 mqd->cp_gfx_hqd_rptr_addr_hi = 3002 upper_32_bits(wb_gpu_addr) & 0xffff; 3003 3004 /* set up rb_wptr_poll addr */ 3005 wb_gpu_addr = prop->wptr_gpu_addr; 3006 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3007 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3008 3009 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3010 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3011 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3012 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3013 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3014 #ifdef __BIG_ENDIAN 3015 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3016 #endif 3017 if (prop->tmz_queue) 3018 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3019 mqd->cp_gfx_hqd_cntl = tmp; 3020 3021 /* set up cp_doorbell_control */ 3022 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3023 if (prop->use_doorbell) { 3024 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3025 DOORBELL_OFFSET, prop->doorbell_index); 3026 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3027 DOORBELL_EN, 1); 3028 } else 3029 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3030 DOORBELL_EN, 0); 3031 mqd->cp_rb_doorbell_control = tmp; 3032 3033 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3034 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3035 3036 /* active the queue */ 3037 mqd->cp_gfx_hqd_active = 1; 3038 3039 /* set gfx UQ items */ 3040 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3041 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3042 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3043 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3044 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3045 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3046 3047 return 0; 3048 } 3049 3050 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3051 { 3052 struct amdgpu_device *adev = ring->adev; 3053 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3054 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3055 3056 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3057 memset((void *)mqd, 0, sizeof(*mqd)); 3058 mutex_lock(&adev->srbm_mutex); 3059 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3060 amdgpu_ring_init_mqd(ring); 3061 soc24_grbm_select(adev, 0, 0, 0, 0); 3062 mutex_unlock(&adev->srbm_mutex); 3063 if (adev->gfx.me.mqd_backup[mqd_idx]) 3064 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3065 } else { 3066 /* restore mqd with the backup copy */ 3067 if (adev->gfx.me.mqd_backup[mqd_idx]) 3068 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3069 /* reset the ring */ 3070 ring->wptr = 0; 3071 *ring->wptr_cpu_addr = 0; 3072 amdgpu_ring_clear_ring(ring); 3073 } 3074 3075 return 0; 3076 } 3077 3078 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3079 { 3080 int i, r; 3081 3082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3083 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3084 if (r) 3085 return r; 3086 } 3087 3088 r = amdgpu_gfx_enable_kgq(adev, 0); 3089 if (r) 3090 return r; 3091 3092 return gfx_v12_0_cp_gfx_start(adev); 3093 } 3094 3095 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3096 struct amdgpu_mqd_prop *prop) 3097 { 3098 struct v12_compute_mqd *mqd = m; 3099 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3100 uint32_t tmp; 3101 3102 mqd->header = 0xC0310800; 3103 mqd->compute_pipelinestat_enable = 0x00000001; 3104 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3105 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3106 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3107 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3108 mqd->compute_misc_reserved = 0x00000007; 3109 3110 eop_base_addr = prop->eop_gpu_addr >> 8; 3111 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3112 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3113 3114 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3115 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3116 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3117 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3118 3119 mqd->cp_hqd_eop_control = tmp; 3120 3121 /* enable doorbell? */ 3122 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3123 3124 if (prop->use_doorbell) { 3125 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3126 DOORBELL_OFFSET, prop->doorbell_index); 3127 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3128 DOORBELL_EN, 1); 3129 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3130 DOORBELL_SOURCE, 0); 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_HIT, 0); 3133 } else { 3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3135 DOORBELL_EN, 0); 3136 } 3137 3138 mqd->cp_hqd_pq_doorbell_control = tmp; 3139 3140 /* disable the queue if it's active */ 3141 mqd->cp_hqd_dequeue_request = 0; 3142 mqd->cp_hqd_pq_rptr = 0; 3143 mqd->cp_hqd_pq_wptr_lo = 0; 3144 mqd->cp_hqd_pq_wptr_hi = 0; 3145 3146 /* set the pointer to the MQD */ 3147 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3148 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3149 3150 /* set MQD vmid to 0 */ 3151 tmp = regCP_MQD_CONTROL_DEFAULT; 3152 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3153 mqd->cp_mqd_control = tmp; 3154 3155 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3156 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3157 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3158 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3159 3160 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3161 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3162 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3163 (order_base_2(prop->queue_size / 4) - 1)); 3164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3165 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3167 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3168 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3169 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3170 if (prop->tmz_queue) 3171 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3172 mqd->cp_hqd_pq_control = tmp; 3173 3174 /* set the wb address whether it's enabled or not */ 3175 wb_gpu_addr = prop->rptr_gpu_addr; 3176 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3177 mqd->cp_hqd_pq_rptr_report_addr_hi = 3178 upper_32_bits(wb_gpu_addr) & 0xffff; 3179 3180 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3181 wb_gpu_addr = prop->wptr_gpu_addr; 3182 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3183 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3184 3185 tmp = 0; 3186 /* enable the doorbell if requested */ 3187 if (prop->use_doorbell) { 3188 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3190 DOORBELL_OFFSET, prop->doorbell_index); 3191 3192 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3193 DOORBELL_EN, 1); 3194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3195 DOORBELL_SOURCE, 0); 3196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3197 DOORBELL_HIT, 0); 3198 } 3199 3200 mqd->cp_hqd_pq_doorbell_control = tmp; 3201 3202 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3203 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3204 3205 /* set the vmid for the queue */ 3206 mqd->cp_hqd_vmid = 0; 3207 3208 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3209 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3210 mqd->cp_hqd_persistent_state = tmp; 3211 3212 /* set MIN_IB_AVAIL_SIZE */ 3213 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3214 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3215 mqd->cp_hqd_ib_control = tmp; 3216 3217 /* set static priority for a compute queue/ring */ 3218 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3219 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3220 3221 mqd->cp_hqd_active = prop->hqd_active; 3222 3223 /* set UQ fenceaddress */ 3224 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3225 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3226 3227 return 0; 3228 } 3229 3230 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3231 { 3232 struct amdgpu_device *adev = ring->adev; 3233 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3234 int j; 3235 3236 /* inactivate the queue */ 3237 if (amdgpu_sriov_vf(adev)) 3238 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3239 3240 /* disable wptr polling */ 3241 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3242 3243 /* write the EOP addr */ 3244 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3245 mqd->cp_hqd_eop_base_addr_lo); 3246 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3247 mqd->cp_hqd_eop_base_addr_hi); 3248 3249 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3250 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3251 mqd->cp_hqd_eop_control); 3252 3253 /* enable doorbell? */ 3254 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3255 mqd->cp_hqd_pq_doorbell_control); 3256 3257 /* disable the queue if it's active */ 3258 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3259 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3260 for (j = 0; j < adev->usec_timeout; j++) { 3261 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3262 break; 3263 udelay(1); 3264 } 3265 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3266 mqd->cp_hqd_dequeue_request); 3267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3268 mqd->cp_hqd_pq_rptr); 3269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3270 mqd->cp_hqd_pq_wptr_lo); 3271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3272 mqd->cp_hqd_pq_wptr_hi); 3273 } 3274 3275 /* set the pointer to the MQD */ 3276 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3277 mqd->cp_mqd_base_addr_lo); 3278 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3279 mqd->cp_mqd_base_addr_hi); 3280 3281 /* set MQD vmid to 0 */ 3282 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3283 mqd->cp_mqd_control); 3284 3285 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3287 mqd->cp_hqd_pq_base_lo); 3288 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3289 mqd->cp_hqd_pq_base_hi); 3290 3291 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3292 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3293 mqd->cp_hqd_pq_control); 3294 3295 /* set the wb address whether it's enabled or not */ 3296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3297 mqd->cp_hqd_pq_rptr_report_addr_lo); 3298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3299 mqd->cp_hqd_pq_rptr_report_addr_hi); 3300 3301 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3303 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3304 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3305 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3306 3307 /* enable the doorbell if requested */ 3308 if (ring->use_doorbell) { 3309 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3310 (adev->doorbell_index.kiq * 2) << 2); 3311 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3312 (adev->doorbell_index.userqueue_end * 2) << 2); 3313 } 3314 3315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3316 mqd->cp_hqd_pq_doorbell_control); 3317 3318 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3320 mqd->cp_hqd_pq_wptr_lo); 3321 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3322 mqd->cp_hqd_pq_wptr_hi); 3323 3324 /* set the vmid for the queue */ 3325 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3326 3327 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3328 mqd->cp_hqd_persistent_state); 3329 3330 /* activate the queue */ 3331 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3332 mqd->cp_hqd_active); 3333 3334 if (ring->use_doorbell) 3335 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3336 3337 return 0; 3338 } 3339 3340 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3341 { 3342 struct amdgpu_device *adev = ring->adev; 3343 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3344 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3345 3346 gfx_v12_0_kiq_setting(ring); 3347 3348 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3349 /* reset MQD to a clean status */ 3350 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3351 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3352 3353 /* reset ring buffer */ 3354 ring->wptr = 0; 3355 amdgpu_ring_clear_ring(ring); 3356 3357 mutex_lock(&adev->srbm_mutex); 3358 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3359 gfx_v12_0_kiq_init_register(ring); 3360 soc24_grbm_select(adev, 0, 0, 0, 0); 3361 mutex_unlock(&adev->srbm_mutex); 3362 } else { 3363 memset((void *)mqd, 0, sizeof(*mqd)); 3364 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3365 amdgpu_ring_clear_ring(ring); 3366 mutex_lock(&adev->srbm_mutex); 3367 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3368 amdgpu_ring_init_mqd(ring); 3369 gfx_v12_0_kiq_init_register(ring); 3370 soc24_grbm_select(adev, 0, 0, 0, 0); 3371 mutex_unlock(&adev->srbm_mutex); 3372 3373 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3374 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3375 } 3376 3377 return 0; 3378 } 3379 3380 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3381 { 3382 struct amdgpu_device *adev = ring->adev; 3383 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3384 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3385 3386 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3387 memset((void *)mqd, 0, sizeof(*mqd)); 3388 mutex_lock(&adev->srbm_mutex); 3389 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3390 amdgpu_ring_init_mqd(ring); 3391 soc24_grbm_select(adev, 0, 0, 0, 0); 3392 mutex_unlock(&adev->srbm_mutex); 3393 3394 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3395 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3396 } else { 3397 /* restore MQD to a clean status */ 3398 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3399 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3400 /* reset ring buffer */ 3401 ring->wptr = 0; 3402 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3403 amdgpu_ring_clear_ring(ring); 3404 } 3405 3406 return 0; 3407 } 3408 3409 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3410 { 3411 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3412 adev->gfx.kiq[0].ring.sched.ready = true; 3413 return 0; 3414 } 3415 3416 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3417 { 3418 int i, r; 3419 3420 if (!amdgpu_async_gfx_ring) 3421 gfx_v12_0_cp_compute_enable(adev, true); 3422 3423 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3424 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3425 if (r) 3426 return r; 3427 } 3428 3429 return amdgpu_gfx_enable_kcq(adev, 0); 3430 } 3431 3432 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3433 { 3434 int r, i; 3435 struct amdgpu_ring *ring; 3436 3437 if (!(adev->flags & AMD_IS_APU)) 3438 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3439 3440 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3441 /* legacy firmware loading */ 3442 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3443 if (r) 3444 return r; 3445 3446 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3447 if (r) 3448 return r; 3449 } 3450 3451 gfx_v12_0_cp_set_doorbell_range(adev); 3452 3453 if (amdgpu_async_gfx_ring) { 3454 gfx_v12_0_cp_compute_enable(adev, true); 3455 gfx_v12_0_cp_gfx_enable(adev, true); 3456 } 3457 3458 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3459 r = amdgpu_mes_kiq_hw_init(adev); 3460 else 3461 r = gfx_v12_0_kiq_resume(adev); 3462 if (r) 3463 return r; 3464 3465 r = gfx_v12_0_kcq_resume(adev); 3466 if (r) 3467 return r; 3468 3469 if (!amdgpu_async_gfx_ring) { 3470 r = gfx_v12_0_cp_gfx_resume(adev); 3471 if (r) 3472 return r; 3473 } else { 3474 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3475 if (r) 3476 return r; 3477 } 3478 3479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3480 ring = &adev->gfx.gfx_ring[i]; 3481 r = amdgpu_ring_test_helper(ring); 3482 if (r) 3483 return r; 3484 } 3485 3486 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3487 ring = &adev->gfx.compute_ring[i]; 3488 r = amdgpu_ring_test_helper(ring); 3489 if (r) 3490 return r; 3491 } 3492 3493 return 0; 3494 } 3495 3496 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3497 { 3498 gfx_v12_0_cp_gfx_enable(adev, enable); 3499 gfx_v12_0_cp_compute_enable(adev, enable); 3500 } 3501 3502 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3503 { 3504 int r; 3505 bool value; 3506 3507 r = adev->gfxhub.funcs->gart_enable(adev); 3508 if (r) 3509 return r; 3510 3511 amdgpu_device_flush_hdp(adev, NULL); 3512 3513 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3514 false : true; 3515 3516 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3517 /* TODO investigate why this and the hdp flush above is needed, 3518 * are we missing a flush somewhere else? */ 3519 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3520 3521 return 0; 3522 } 3523 3524 static int get_gb_addr_config(struct amdgpu_device *adev) 3525 { 3526 u32 gb_addr_config; 3527 3528 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3529 if (gb_addr_config == 0) 3530 return -EINVAL; 3531 3532 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3533 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3534 3535 adev->gfx.config.gb_addr_config = gb_addr_config; 3536 3537 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3538 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3539 GB_ADDR_CONFIG, NUM_PIPES); 3540 3541 adev->gfx.config.max_tile_pipes = 3542 adev->gfx.config.gb_addr_config_fields.num_pipes; 3543 3544 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3545 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3546 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3547 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3548 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3549 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3550 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3551 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3552 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3553 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3554 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3555 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3556 3557 return 0; 3558 } 3559 3560 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3561 { 3562 uint32_t data; 3563 3564 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3565 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3566 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3567 3568 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3569 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3570 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3571 } 3572 3573 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3574 { 3575 if (amdgpu_sriov_vf(adev)) 3576 return; 3577 3578 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3579 case IP_VERSION(12, 0, 0): 3580 case IP_VERSION(12, 0, 1): 3581 soc15_program_register_sequence(adev, 3582 golden_settings_gc_12_0, 3583 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3584 3585 if (adev->rev_id == 0) 3586 soc15_program_register_sequence(adev, 3587 golden_settings_gc_12_0_rev0, 3588 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3589 break; 3590 default: 3591 break; 3592 } 3593 } 3594 3595 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3596 { 3597 int r; 3598 struct amdgpu_device *adev = ip_block->adev; 3599 3600 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3601 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3602 /* RLC autoload sequence 1: Program rlc ram */ 3603 if (adev->gfx.imu.funcs->program_rlc_ram) 3604 adev->gfx.imu.funcs->program_rlc_ram(adev); 3605 } 3606 /* rlc autoload firmware */ 3607 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3608 if (r) 3609 return r; 3610 } else { 3611 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3612 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3613 if (adev->gfx.imu.funcs->load_microcode) 3614 adev->gfx.imu.funcs->load_microcode(adev); 3615 if (adev->gfx.imu.funcs->setup_imu) 3616 adev->gfx.imu.funcs->setup_imu(adev); 3617 if (adev->gfx.imu.funcs->start_imu) 3618 adev->gfx.imu.funcs->start_imu(adev); 3619 } 3620 3621 /* disable gpa mode in backdoor loading */ 3622 gfx_v12_0_disable_gpa_mode(adev); 3623 } 3624 } 3625 3626 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3627 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3628 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3629 if (r) { 3630 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3631 return r; 3632 } 3633 } 3634 3635 if (!amdgpu_emu_mode) 3636 gfx_v12_0_init_golden_registers(adev); 3637 3638 adev->gfx.is_poweron = true; 3639 3640 if (get_gb_addr_config(adev)) 3641 DRM_WARN("Invalid gb_addr_config !\n"); 3642 3643 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3644 gfx_v12_0_config_gfx_rs64(adev); 3645 3646 r = gfx_v12_0_gfxhub_enable(adev); 3647 if (r) 3648 return r; 3649 3650 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3651 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3652 (amdgpu_dpm == 1)) { 3653 /** 3654 * For gfx 12, rlc firmware loading relies on smu firmware is 3655 * loaded firstly, so in direct type, it has to load smc ucode 3656 * here before rlc. 3657 */ 3658 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3659 if (r) 3660 return r; 3661 } 3662 3663 gfx_v12_0_constants_init(adev); 3664 3665 if (adev->nbio.funcs->gc_doorbell_init) 3666 adev->nbio.funcs->gc_doorbell_init(adev); 3667 3668 r = gfx_v12_0_rlc_resume(adev); 3669 if (r) 3670 return r; 3671 3672 /* 3673 * init golden registers and rlc resume may override some registers, 3674 * reconfig them here 3675 */ 3676 gfx_v12_0_tcp_harvest(adev); 3677 3678 r = gfx_v12_0_cp_resume(adev); 3679 if (r) 3680 return r; 3681 3682 return r; 3683 } 3684 3685 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3686 bool enable) 3687 { 3688 unsigned int irq_type; 3689 int m, p, r; 3690 3691 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3692 for (m = 0; m < adev->gfx.me.num_me; m++) { 3693 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3694 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3695 if (enable) 3696 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3697 irq_type); 3698 else 3699 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3700 irq_type); 3701 if (r) 3702 return r; 3703 } 3704 } 3705 } 3706 3707 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3708 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3709 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3710 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3711 + (m * adev->gfx.mec.num_pipe_per_mec) 3712 + p; 3713 if (enable) 3714 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3715 irq_type); 3716 else 3717 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3718 irq_type); 3719 if (r) 3720 return r; 3721 } 3722 } 3723 } 3724 3725 return 0; 3726 } 3727 3728 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3729 { 3730 struct amdgpu_device *adev = ip_block->adev; 3731 uint32_t tmp; 3732 3733 cancel_delayed_work_sync(&adev->gfx.idle_work); 3734 3735 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3736 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3737 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3738 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3739 3740 if (!adev->no_hw_access) { 3741 if (amdgpu_async_gfx_ring) { 3742 if (amdgpu_gfx_disable_kgq(adev, 0)) 3743 DRM_ERROR("KGQ disable failed\n"); 3744 } 3745 3746 if (amdgpu_gfx_disable_kcq(adev, 0)) 3747 DRM_ERROR("KCQ disable failed\n"); 3748 3749 amdgpu_mes_kiq_hw_fini(adev); 3750 } 3751 3752 if (amdgpu_sriov_vf(adev)) { 3753 gfx_v12_0_cp_gfx_enable(adev, false); 3754 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3755 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3756 tmp &= 0xffffff00; 3757 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3758 3759 return 0; 3760 } 3761 gfx_v12_0_cp_enable(adev, false); 3762 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3763 3764 adev->gfxhub.funcs->gart_disable(adev); 3765 3766 adev->gfx.is_poweron = false; 3767 3768 return 0; 3769 } 3770 3771 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3772 { 3773 return gfx_v12_0_hw_fini(ip_block); 3774 } 3775 3776 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3777 { 3778 return gfx_v12_0_hw_init(ip_block); 3779 } 3780 3781 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3782 { 3783 struct amdgpu_device *adev = ip_block->adev; 3784 3785 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3786 GRBM_STATUS, GUI_ACTIVE)) 3787 return false; 3788 else 3789 return true; 3790 } 3791 3792 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3793 { 3794 unsigned i; 3795 u32 tmp; 3796 struct amdgpu_device *adev = ip_block->adev; 3797 3798 for (i = 0; i < adev->usec_timeout; i++) { 3799 /* read MC_STATUS */ 3800 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3801 GRBM_STATUS__GUI_ACTIVE_MASK; 3802 3803 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3804 return 0; 3805 udelay(1); 3806 } 3807 return -ETIMEDOUT; 3808 } 3809 3810 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3811 { 3812 uint64_t clock = 0; 3813 3814 if (adev->smuio.funcs && 3815 adev->smuio.funcs->get_gpu_clock_counter) 3816 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3817 else 3818 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3819 3820 return clock; 3821 } 3822 3823 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3824 { 3825 struct amdgpu_device *adev = ip_block->adev; 3826 3827 switch (amdgpu_user_queue) { 3828 case -1: 3829 case 0: 3830 default: 3831 adev->gfx.disable_kq = false; 3832 adev->gfx.disable_uq = true; 3833 break; 3834 case 1: 3835 adev->gfx.disable_kq = false; 3836 adev->gfx.disable_uq = false; 3837 break; 3838 case 2: 3839 adev->gfx.disable_kq = true; 3840 adev->gfx.disable_uq = false; 3841 break; 3842 } 3843 3844 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3845 3846 if (adev->gfx.disable_kq) { 3847 adev->gfx.num_gfx_rings = 0; 3848 adev->gfx.num_compute_rings = 0; 3849 } else { 3850 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3851 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3852 AMDGPU_MAX_COMPUTE_RINGS); 3853 } 3854 3855 gfx_v12_0_set_kiq_pm4_funcs(adev); 3856 gfx_v12_0_set_ring_funcs(adev); 3857 gfx_v12_0_set_irq_funcs(adev); 3858 gfx_v12_0_set_rlc_funcs(adev); 3859 gfx_v12_0_set_mqd_funcs(adev); 3860 gfx_v12_0_set_imu_funcs(adev); 3861 3862 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3863 3864 return gfx_v12_0_init_microcode(adev); 3865 } 3866 3867 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3868 { 3869 struct amdgpu_device *adev = ip_block->adev; 3870 int r; 3871 3872 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3873 if (r) 3874 return r; 3875 3876 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3877 if (r) 3878 return r; 3879 3880 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3881 if (r) 3882 return r; 3883 3884 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3885 if (r) 3886 return r; 3887 3888 return 0; 3889 } 3890 3891 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3892 { 3893 uint32_t rlc_cntl; 3894 3895 /* if RLC is not enabled, do nothing */ 3896 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3897 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3898 } 3899 3900 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3901 int xcc_id) 3902 { 3903 uint32_t data; 3904 unsigned i; 3905 3906 data = RLC_SAFE_MODE__CMD_MASK; 3907 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3908 3909 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3910 3911 /* wait for RLC_SAFE_MODE */ 3912 for (i = 0; i < adev->usec_timeout; i++) { 3913 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3914 RLC_SAFE_MODE, CMD)) 3915 break; 3916 udelay(1); 3917 } 3918 } 3919 3920 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3921 int xcc_id) 3922 { 3923 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3924 } 3925 3926 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3927 bool enable) 3928 { 3929 uint32_t def, data; 3930 3931 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3932 return; 3933 3934 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3935 3936 if (enable) 3937 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3938 else 3939 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3940 3941 if (def != data) 3942 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3943 } 3944 3945 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3946 struct amdgpu_ring *ring, 3947 unsigned vmid) 3948 { 3949 u32 reg, data; 3950 3951 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3952 if (amdgpu_sriov_is_pp_one_vf(adev)) 3953 data = RREG32_NO_KIQ(reg); 3954 else 3955 data = RREG32(reg); 3956 3957 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3958 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3959 3960 if (amdgpu_sriov_is_pp_one_vf(adev)) 3961 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3962 else 3963 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3964 3965 if (ring 3966 && amdgpu_sriov_is_pp_one_vf(adev) 3967 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3968 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3969 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3970 amdgpu_ring_emit_wreg(ring, reg, data); 3971 } 3972 } 3973 3974 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3975 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3976 .set_safe_mode = gfx_v12_0_set_safe_mode, 3977 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3978 .init = gfx_v12_0_rlc_init, 3979 .get_csb_size = gfx_v12_0_get_csb_size, 3980 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 3981 .resume = gfx_v12_0_rlc_resume, 3982 .stop = gfx_v12_0_rlc_stop, 3983 .reset = gfx_v12_0_rlc_reset, 3984 .start = gfx_v12_0_rlc_start, 3985 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 3986 }; 3987 3988 #if 0 3989 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 3990 { 3991 /* TODO */ 3992 } 3993 3994 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 3995 { 3996 /* TODO */ 3997 } 3998 #endif 3999 4000 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4001 enum amd_powergating_state state) 4002 { 4003 struct amdgpu_device *adev = ip_block->adev; 4004 bool enable = (state == AMD_PG_STATE_GATE); 4005 4006 if (amdgpu_sriov_vf(adev)) 4007 return 0; 4008 4009 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4010 case IP_VERSION(12, 0, 0): 4011 case IP_VERSION(12, 0, 1): 4012 amdgpu_gfx_off_ctrl(adev, enable); 4013 break; 4014 default: 4015 break; 4016 } 4017 4018 return 0; 4019 } 4020 4021 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4022 bool enable) 4023 { 4024 uint32_t def, data; 4025 4026 if (!(adev->cg_flags & 4027 (AMD_CG_SUPPORT_GFX_CGCG | 4028 AMD_CG_SUPPORT_GFX_CGLS | 4029 AMD_CG_SUPPORT_GFX_3D_CGCG | 4030 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4031 return; 4032 4033 if (enable) { 4034 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4035 4036 /* unset CGCG override */ 4037 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4038 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4040 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4041 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4042 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4043 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4044 4045 /* update CGCG override bits */ 4046 if (def != data) 4047 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4048 4049 /* enable cgcg FSM(0x0000363F) */ 4050 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4051 4052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4053 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4054 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4055 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4056 } 4057 4058 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4059 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4060 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4061 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4062 } 4063 4064 if (def != data) 4065 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4066 4067 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4068 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4069 4070 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4071 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4072 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4073 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4074 } 4075 4076 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4077 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4078 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4079 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4080 } 4081 4082 if (def != data) 4083 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4084 4085 /* set IDLE_POLL_COUNT(0x00900100) */ 4086 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4087 4088 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4089 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4090 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4091 4092 if (def != data) 4093 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4094 4095 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4096 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4097 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4098 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4099 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4100 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4101 4102 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4103 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4104 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4105 4106 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4107 if (adev->sdma.num_instances > 1) { 4108 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4109 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4110 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4111 } 4112 } else { 4113 /* Program RLC_CGCG_CGLS_CTRL */ 4114 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4115 4116 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4117 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4118 4119 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4120 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4121 4122 if (def != data) 4123 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4124 4125 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4126 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4127 4128 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4129 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4130 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4131 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4132 4133 if (def != data) 4134 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4135 } 4136 } 4137 4138 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4139 bool enable) 4140 { 4141 uint32_t data, def; 4142 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4143 return; 4144 4145 /* It is disabled by HW by default */ 4146 if (enable) { 4147 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4148 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4149 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4150 4151 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4152 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4153 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4154 4155 if (def != data) 4156 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4157 } 4158 } else { 4159 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4160 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4161 4162 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4163 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4164 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4165 4166 if (def != data) 4167 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4168 } 4169 } 4170 } 4171 4172 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4173 bool enable) 4174 { 4175 uint32_t def, data; 4176 4177 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4178 return; 4179 4180 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4181 4182 if (enable) 4183 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4184 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4185 else 4186 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4187 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4188 4189 if (def != data) 4190 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4191 } 4192 4193 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4194 bool enable) 4195 { 4196 uint32_t def, data; 4197 4198 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4199 return; 4200 4201 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4202 4203 if (enable) 4204 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4205 else 4206 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4207 4208 if (def != data) 4209 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4210 } 4211 4212 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4213 bool enable) 4214 { 4215 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4216 4217 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4218 4219 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4220 4221 gfx_v12_0_update_repeater_fgcg(adev, enable); 4222 4223 gfx_v12_0_update_sram_fgcg(adev, enable); 4224 4225 gfx_v12_0_update_perf_clk(adev, enable); 4226 4227 if (adev->cg_flags & 4228 (AMD_CG_SUPPORT_GFX_MGCG | 4229 AMD_CG_SUPPORT_GFX_CGLS | 4230 AMD_CG_SUPPORT_GFX_CGCG | 4231 AMD_CG_SUPPORT_GFX_3D_CGCG | 4232 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4233 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4234 4235 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4236 4237 return 0; 4238 } 4239 4240 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4241 enum amd_clockgating_state state) 4242 { 4243 struct amdgpu_device *adev = ip_block->adev; 4244 4245 if (amdgpu_sriov_vf(adev)) 4246 return 0; 4247 4248 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4249 case IP_VERSION(12, 0, 0): 4250 case IP_VERSION(12, 0, 1): 4251 gfx_v12_0_update_gfx_clock_gating(adev, 4252 state == AMD_CG_STATE_GATE); 4253 break; 4254 default: 4255 break; 4256 } 4257 4258 return 0; 4259 } 4260 4261 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4262 { 4263 struct amdgpu_device *adev = ip_block->adev; 4264 int data; 4265 4266 /* AMD_CG_SUPPORT_GFX_MGCG */ 4267 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4268 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4269 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4270 4271 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4272 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4273 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4274 4275 /* AMD_CG_SUPPORT_GFX_FGCG */ 4276 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4277 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4278 4279 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4280 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4281 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4282 4283 /* AMD_CG_SUPPORT_GFX_CGCG */ 4284 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4285 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4286 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4287 4288 /* AMD_CG_SUPPORT_GFX_CGLS */ 4289 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4290 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4291 4292 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4293 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4294 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4295 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4296 4297 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4298 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4299 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4300 } 4301 4302 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4303 { 4304 /* gfx12 is 32bit rptr*/ 4305 return *(uint32_t *)ring->rptr_cpu_addr; 4306 } 4307 4308 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4309 { 4310 struct amdgpu_device *adev = ring->adev; 4311 u64 wptr; 4312 4313 /* XXX check if swapping is necessary on BE */ 4314 if (ring->use_doorbell) { 4315 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4316 } else { 4317 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4318 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4319 } 4320 4321 return wptr; 4322 } 4323 4324 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4325 { 4326 struct amdgpu_device *adev = ring->adev; 4327 4328 if (ring->use_doorbell) { 4329 /* XXX check if swapping is necessary on BE */ 4330 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4331 ring->wptr); 4332 WDOORBELL64(ring->doorbell_index, ring->wptr); 4333 } else { 4334 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4335 lower_32_bits(ring->wptr)); 4336 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4337 upper_32_bits(ring->wptr)); 4338 } 4339 } 4340 4341 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4342 { 4343 /* gfx12 hardware is 32bit rptr */ 4344 return *(uint32_t *)ring->rptr_cpu_addr; 4345 } 4346 4347 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4348 { 4349 u64 wptr; 4350 4351 /* XXX check if swapping is necessary on BE */ 4352 if (ring->use_doorbell) 4353 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4354 else 4355 BUG(); 4356 return wptr; 4357 } 4358 4359 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4360 { 4361 struct amdgpu_device *adev = ring->adev; 4362 4363 /* XXX check if swapping is necessary on BE */ 4364 if (ring->use_doorbell) { 4365 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4366 ring->wptr); 4367 WDOORBELL64(ring->doorbell_index, ring->wptr); 4368 } else { 4369 BUG(); /* only DOORBELL method supported on gfx12 now */ 4370 } 4371 } 4372 4373 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4374 { 4375 struct amdgpu_device *adev = ring->adev; 4376 u32 ref_and_mask, reg_mem_engine; 4377 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4378 4379 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4380 switch (ring->me) { 4381 case 1: 4382 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4383 break; 4384 case 2: 4385 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4386 break; 4387 default: 4388 return; 4389 } 4390 reg_mem_engine = 0; 4391 } else { 4392 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4393 reg_mem_engine = 1; /* pfp */ 4394 } 4395 4396 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4397 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4398 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4399 ref_and_mask, ref_and_mask, 0x20); 4400 } 4401 4402 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4403 struct amdgpu_job *job, 4404 struct amdgpu_ib *ib, 4405 uint32_t flags) 4406 { 4407 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4408 u32 header, control = 0; 4409 4410 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 4411 4412 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4413 4414 control |= ib->length_dw | (vmid << 24); 4415 4416 amdgpu_ring_write(ring, header); 4417 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4418 amdgpu_ring_write(ring, 4419 #ifdef __BIG_ENDIAN 4420 (2 << 0) | 4421 #endif 4422 lower_32_bits(ib->gpu_addr)); 4423 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4424 amdgpu_ring_write(ring, control); 4425 } 4426 4427 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4428 struct amdgpu_job *job, 4429 struct amdgpu_ib *ib, 4430 uint32_t flags) 4431 { 4432 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4433 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4434 4435 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4436 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4437 amdgpu_ring_write(ring, 4438 #ifdef __BIG_ENDIAN 4439 (2 << 0) | 4440 #endif 4441 lower_32_bits(ib->gpu_addr)); 4442 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4443 amdgpu_ring_write(ring, control); 4444 } 4445 4446 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4447 u64 seq, unsigned flags) 4448 { 4449 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4450 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4451 4452 /* RELEASE_MEM - flush caches, send int */ 4453 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4454 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4455 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4456 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4457 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4458 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4459 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4460 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4461 4462 /* 4463 * the address should be Qword aligned if 64bit write, Dword 4464 * aligned if only send 32bit data low (discard data high) 4465 */ 4466 if (write64bit) 4467 BUG_ON(addr & 0x7); 4468 else 4469 BUG_ON(addr & 0x3); 4470 amdgpu_ring_write(ring, lower_32_bits(addr)); 4471 amdgpu_ring_write(ring, upper_32_bits(addr)); 4472 amdgpu_ring_write(ring, lower_32_bits(seq)); 4473 amdgpu_ring_write(ring, upper_32_bits(seq)); 4474 amdgpu_ring_write(ring, 0); 4475 } 4476 4477 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4478 { 4479 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4480 uint32_t seq = ring->fence_drv.sync_seq; 4481 uint64_t addr = ring->fence_drv.gpu_addr; 4482 4483 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4484 upper_32_bits(addr), seq, 0xffffffff, 4); 4485 } 4486 4487 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4488 uint16_t pasid, uint32_t flush_type, 4489 bool all_hub, uint8_t dst_sel) 4490 { 4491 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4492 amdgpu_ring_write(ring, 4493 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4494 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4495 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4496 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4497 } 4498 4499 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4500 unsigned vmid, uint64_t pd_addr) 4501 { 4502 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4503 4504 /* compute doesn't have PFP */ 4505 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4506 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4507 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4508 amdgpu_ring_write(ring, 0x0); 4509 } 4510 } 4511 4512 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4513 u64 seq, unsigned int flags) 4514 { 4515 struct amdgpu_device *adev = ring->adev; 4516 4517 /* we only allocate 32bit for each seq wb address */ 4518 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4519 4520 /* write fence seq to the "addr" */ 4521 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4522 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4523 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4524 amdgpu_ring_write(ring, lower_32_bits(addr)); 4525 amdgpu_ring_write(ring, upper_32_bits(addr)); 4526 amdgpu_ring_write(ring, lower_32_bits(seq)); 4527 4528 if (flags & AMDGPU_FENCE_FLAG_INT) { 4529 /* set register to trigger INT */ 4530 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4531 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4532 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4533 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4534 amdgpu_ring_write(ring, 0); 4535 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4536 } 4537 } 4538 4539 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4540 uint32_t flags) 4541 { 4542 uint32_t dw2 = 0; 4543 4544 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4545 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4546 /* set load_global_config & load_global_uconfig */ 4547 dw2 |= 0x8001; 4548 /* set load_cs_sh_regs */ 4549 dw2 |= 0x01000000; 4550 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4551 dw2 |= 0x10002; 4552 } 4553 4554 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4555 amdgpu_ring_write(ring, dw2); 4556 amdgpu_ring_write(ring, 0); 4557 } 4558 4559 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4560 uint64_t addr) 4561 { 4562 unsigned ret; 4563 4564 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4565 amdgpu_ring_write(ring, lower_32_bits(addr)); 4566 amdgpu_ring_write(ring, upper_32_bits(addr)); 4567 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4568 amdgpu_ring_write(ring, 0); 4569 ret = ring->wptr & ring->buf_mask; 4570 /* patch dummy value later */ 4571 amdgpu_ring_write(ring, 0); 4572 4573 return ret; 4574 } 4575 4576 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4577 { 4578 int i, r = 0; 4579 struct amdgpu_device *adev = ring->adev; 4580 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4581 struct amdgpu_ring *kiq_ring = &kiq->ring; 4582 unsigned long flags; 4583 4584 if (adev->enable_mes) 4585 return -EINVAL; 4586 4587 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4588 return -EINVAL; 4589 4590 spin_lock_irqsave(&kiq->ring_lock, flags); 4591 4592 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4593 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4594 return -ENOMEM; 4595 } 4596 4597 /* assert preemption condition */ 4598 amdgpu_ring_set_preempt_cond_exec(ring, false); 4599 4600 /* assert IB preemption, emit the trailing fence */ 4601 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4602 ring->trail_fence_gpu_addr, 4603 ++ring->trail_seq); 4604 amdgpu_ring_commit(kiq_ring); 4605 4606 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4607 4608 /* poll the trailing fence */ 4609 for (i = 0; i < adev->usec_timeout; i++) { 4610 if (ring->trail_seq == 4611 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4612 break; 4613 udelay(1); 4614 } 4615 4616 if (i >= adev->usec_timeout) { 4617 r = -EINVAL; 4618 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4619 } 4620 4621 /* deassert preemption condition */ 4622 amdgpu_ring_set_preempt_cond_exec(ring, true); 4623 return r; 4624 } 4625 4626 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, 4627 bool start, 4628 bool secure) 4629 { 4630 uint32_t v = secure ? FRAME_TMZ : 0; 4631 4632 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4633 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 4634 } 4635 4636 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4637 uint32_t reg_val_offs) 4638 { 4639 struct amdgpu_device *adev = ring->adev; 4640 4641 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4642 amdgpu_ring_write(ring, 0 | /* src: register*/ 4643 (5 << 8) | /* dst: memory */ 4644 (1 << 20)); /* write confirm */ 4645 amdgpu_ring_write(ring, reg); 4646 amdgpu_ring_write(ring, 0); 4647 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4648 reg_val_offs * 4)); 4649 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4650 reg_val_offs * 4)); 4651 } 4652 4653 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4654 uint32_t reg, 4655 uint32_t val) 4656 { 4657 uint32_t cmd = 0; 4658 4659 switch (ring->funcs->type) { 4660 case AMDGPU_RING_TYPE_GFX: 4661 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4662 break; 4663 case AMDGPU_RING_TYPE_KIQ: 4664 cmd = (1 << 16); /* no inc addr */ 4665 break; 4666 default: 4667 cmd = WR_CONFIRM; 4668 break; 4669 } 4670 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4671 amdgpu_ring_write(ring, cmd); 4672 amdgpu_ring_write(ring, reg); 4673 amdgpu_ring_write(ring, 0); 4674 amdgpu_ring_write(ring, val); 4675 } 4676 4677 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4678 uint32_t val, uint32_t mask) 4679 { 4680 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4681 } 4682 4683 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4684 uint32_t reg0, uint32_t reg1, 4685 uint32_t ref, uint32_t mask) 4686 { 4687 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4688 4689 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4690 ref, mask, 0x20); 4691 } 4692 4693 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, 4694 unsigned vmid) 4695 { 4696 struct amdgpu_device *adev = ring->adev; 4697 uint32_t value = 0; 4698 4699 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4700 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4701 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4702 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4703 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4704 WREG32_SOC15(GC, 0, regSQ_CMD, value); 4705 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4706 } 4707 4708 static void 4709 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4710 uint32_t me, uint32_t pipe, 4711 enum amdgpu_interrupt_state state) 4712 { 4713 uint32_t cp_int_cntl, cp_int_cntl_reg; 4714 4715 if (!me) { 4716 switch (pipe) { 4717 case 0: 4718 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4719 break; 4720 default: 4721 DRM_DEBUG("invalid pipe %d\n", pipe); 4722 return; 4723 } 4724 } else { 4725 DRM_DEBUG("invalid me %d\n", me); 4726 return; 4727 } 4728 4729 switch (state) { 4730 case AMDGPU_IRQ_STATE_DISABLE: 4731 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4732 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4733 TIME_STAMP_INT_ENABLE, 0); 4734 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4735 GENERIC0_INT_ENABLE, 0); 4736 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4737 break; 4738 case AMDGPU_IRQ_STATE_ENABLE: 4739 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4740 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4741 TIME_STAMP_INT_ENABLE, 1); 4742 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4743 GENERIC0_INT_ENABLE, 1); 4744 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4745 break; 4746 default: 4747 break; 4748 } 4749 } 4750 4751 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4752 int me, int pipe, 4753 enum amdgpu_interrupt_state state) 4754 { 4755 u32 mec_int_cntl, mec_int_cntl_reg; 4756 4757 /* 4758 * amdgpu controls only the first MEC. That's why this function only 4759 * handles the setting of interrupts for this specific MEC. All other 4760 * pipes' interrupts are set by amdkfd. 4761 */ 4762 4763 if (me == 1) { 4764 switch (pipe) { 4765 case 0: 4766 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4767 break; 4768 case 1: 4769 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4770 break; 4771 default: 4772 DRM_DEBUG("invalid pipe %d\n", pipe); 4773 return; 4774 } 4775 } else { 4776 DRM_DEBUG("invalid me %d\n", me); 4777 return; 4778 } 4779 4780 switch (state) { 4781 case AMDGPU_IRQ_STATE_DISABLE: 4782 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4783 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4784 TIME_STAMP_INT_ENABLE, 0); 4785 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4786 GENERIC0_INT_ENABLE, 0); 4787 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4788 break; 4789 case AMDGPU_IRQ_STATE_ENABLE: 4790 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4791 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4792 TIME_STAMP_INT_ENABLE, 1); 4793 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4794 GENERIC0_INT_ENABLE, 1); 4795 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4796 break; 4797 default: 4798 break; 4799 } 4800 } 4801 4802 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4803 struct amdgpu_irq_src *src, 4804 unsigned type, 4805 enum amdgpu_interrupt_state state) 4806 { 4807 switch (type) { 4808 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4809 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4810 break; 4811 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4812 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4813 break; 4814 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4815 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4816 break; 4817 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4818 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4819 break; 4820 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4821 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4822 break; 4823 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4824 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4825 break; 4826 default: 4827 break; 4828 } 4829 return 0; 4830 } 4831 4832 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4833 struct amdgpu_irq_src *source, 4834 struct amdgpu_iv_entry *entry) 4835 { 4836 u32 doorbell_offset = entry->src_data[0]; 4837 u8 me_id, pipe_id, queue_id; 4838 struct amdgpu_ring *ring; 4839 int i; 4840 4841 DRM_DEBUG("IH: CP EOP\n"); 4842 4843 if (adev->enable_mes && doorbell_offset) { 4844 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4845 struct xarray *xa = &adev->userq_xa; 4846 unsigned long flags; 4847 4848 xa_lock_irqsave(xa, flags); 4849 fence_drv = xa_load(xa, doorbell_offset); 4850 if (fence_drv) 4851 amdgpu_userq_fence_driver_process(fence_drv); 4852 xa_unlock_irqrestore(xa, flags); 4853 } else { 4854 me_id = (entry->ring_id & 0x0c) >> 2; 4855 pipe_id = (entry->ring_id & 0x03) >> 0; 4856 queue_id = (entry->ring_id & 0x70) >> 4; 4857 4858 switch (me_id) { 4859 case 0: 4860 if (pipe_id == 0) 4861 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4862 else 4863 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4864 break; 4865 case 1: 4866 case 2: 4867 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4868 ring = &adev->gfx.compute_ring[i]; 4869 /* Per-queue interrupt is supported for MEC starting from VI. 4870 * The interrupt can only be enabled/disabled per pipe instead 4871 * of per queue. 4872 */ 4873 if ((ring->me == me_id) && 4874 (ring->pipe == pipe_id) && 4875 (ring->queue == queue_id)) 4876 amdgpu_fence_process(ring); 4877 } 4878 break; 4879 } 4880 } 4881 4882 return 0; 4883 } 4884 4885 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4886 struct amdgpu_irq_src *source, 4887 unsigned int type, 4888 enum amdgpu_interrupt_state state) 4889 { 4890 u32 cp_int_cntl_reg, cp_int_cntl; 4891 int i, j; 4892 4893 switch (state) { 4894 case AMDGPU_IRQ_STATE_DISABLE: 4895 case AMDGPU_IRQ_STATE_ENABLE: 4896 for (i = 0; i < adev->gfx.me.num_me; i++) { 4897 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4898 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4899 4900 if (cp_int_cntl_reg) { 4901 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4902 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4903 PRIV_REG_INT_ENABLE, 4904 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4905 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4906 } 4907 } 4908 } 4909 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4910 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4911 /* MECs start at 1 */ 4912 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4913 4914 if (cp_int_cntl_reg) { 4915 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4916 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4917 PRIV_REG_INT_ENABLE, 4918 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4919 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4920 } 4921 } 4922 } 4923 break; 4924 default: 4925 break; 4926 } 4927 4928 return 0; 4929 } 4930 4931 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4932 struct amdgpu_irq_src *source, 4933 unsigned type, 4934 enum amdgpu_interrupt_state state) 4935 { 4936 u32 cp_int_cntl_reg, cp_int_cntl; 4937 int i, j; 4938 4939 switch (state) { 4940 case AMDGPU_IRQ_STATE_DISABLE: 4941 case AMDGPU_IRQ_STATE_ENABLE: 4942 for (i = 0; i < adev->gfx.me.num_me; i++) { 4943 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4944 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4945 4946 if (cp_int_cntl_reg) { 4947 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4948 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4949 OPCODE_ERROR_INT_ENABLE, 4950 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4951 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4952 } 4953 } 4954 } 4955 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4956 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4957 /* MECs start at 1 */ 4958 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4959 4960 if (cp_int_cntl_reg) { 4961 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4962 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4963 OPCODE_ERROR_INT_ENABLE, 4964 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4965 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4966 } 4967 } 4968 } 4969 break; 4970 default: 4971 break; 4972 } 4973 return 0; 4974 } 4975 4976 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4977 struct amdgpu_irq_src *source, 4978 unsigned int type, 4979 enum amdgpu_interrupt_state state) 4980 { 4981 u32 cp_int_cntl_reg, cp_int_cntl; 4982 int i, j; 4983 4984 switch (state) { 4985 case AMDGPU_IRQ_STATE_DISABLE: 4986 case AMDGPU_IRQ_STATE_ENABLE: 4987 for (i = 0; i < adev->gfx.me.num_me; i++) { 4988 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4989 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4990 4991 if (cp_int_cntl_reg) { 4992 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4993 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4994 PRIV_INSTR_INT_ENABLE, 4995 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4996 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4997 } 4998 } 4999 } 5000 break; 5001 default: 5002 break; 5003 } 5004 5005 return 0; 5006 } 5007 5008 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5009 struct amdgpu_iv_entry *entry) 5010 { 5011 u8 me_id, pipe_id, queue_id; 5012 struct amdgpu_ring *ring; 5013 int i; 5014 5015 me_id = (entry->ring_id & 0x0c) >> 2; 5016 pipe_id = (entry->ring_id & 0x03) >> 0; 5017 queue_id = (entry->ring_id & 0x70) >> 4; 5018 5019 if (!adev->gfx.disable_kq) { 5020 switch (me_id) { 5021 case 0: 5022 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5023 ring = &adev->gfx.gfx_ring[i]; 5024 if (ring->me == me_id && ring->pipe == pipe_id && 5025 ring->queue == queue_id) 5026 drm_sched_fault(&ring->sched); 5027 } 5028 break; 5029 case 1: 5030 case 2: 5031 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5032 ring = &adev->gfx.compute_ring[i]; 5033 if (ring->me == me_id && ring->pipe == pipe_id && 5034 ring->queue == queue_id) 5035 drm_sched_fault(&ring->sched); 5036 } 5037 break; 5038 default: 5039 BUG(); 5040 break; 5041 } 5042 } 5043 } 5044 5045 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5046 struct amdgpu_irq_src *source, 5047 struct amdgpu_iv_entry *entry) 5048 { 5049 DRM_ERROR("Illegal register access in command stream\n"); 5050 gfx_v12_0_handle_priv_fault(adev, entry); 5051 return 0; 5052 } 5053 5054 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5055 struct amdgpu_irq_src *source, 5056 struct amdgpu_iv_entry *entry) 5057 { 5058 DRM_ERROR("Illegal opcode in command stream \n"); 5059 gfx_v12_0_handle_priv_fault(adev, entry); 5060 return 0; 5061 } 5062 5063 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5064 struct amdgpu_irq_src *source, 5065 struct amdgpu_iv_entry *entry) 5066 { 5067 DRM_ERROR("Illegal instruction in command stream\n"); 5068 gfx_v12_0_handle_priv_fault(adev, entry); 5069 return 0; 5070 } 5071 5072 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5073 { 5074 const unsigned int gcr_cntl = 5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5079 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5080 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5081 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5082 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5083 5084 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5085 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5086 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5087 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5088 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5089 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5090 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5091 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5092 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5093 } 5094 5095 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5096 { 5097 /* Header itself is a NOP packet */ 5098 if (num_nop == 1) { 5099 amdgpu_ring_write(ring, ring->funcs->nop); 5100 return; 5101 } 5102 5103 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5104 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5105 5106 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5107 amdgpu_ring_insert_nop(ring, num_nop - 1); 5108 } 5109 5110 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5111 { 5112 /* Emit the cleaner shader */ 5113 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5114 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5115 } 5116 5117 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5118 { 5119 struct amdgpu_device *adev = ip_block->adev; 5120 uint32_t i, j, k, reg, index = 0; 5121 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5122 5123 if (!adev->gfx.ip_dump_core) 5124 return; 5125 5126 for (i = 0; i < reg_count; i++) 5127 drm_printf(p, "%-50s \t 0x%08x\n", 5128 gc_reg_list_12_0[i].reg_name, 5129 adev->gfx.ip_dump_core[i]); 5130 5131 /* print compute queue registers for all instances */ 5132 if (!adev->gfx.ip_dump_compute_queues) 5133 return; 5134 5135 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5136 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5137 adev->gfx.mec.num_mec, 5138 adev->gfx.mec.num_pipe_per_mec, 5139 adev->gfx.mec.num_queue_per_pipe); 5140 5141 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5142 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5143 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5144 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5145 for (reg = 0; reg < reg_count; reg++) { 5146 drm_printf(p, "%-50s \t 0x%08x\n", 5147 gc_cp_reg_list_12[reg].reg_name, 5148 adev->gfx.ip_dump_compute_queues[index + reg]); 5149 } 5150 index += reg_count; 5151 } 5152 } 5153 } 5154 5155 /* print gfx queue registers for all instances */ 5156 if (!adev->gfx.ip_dump_gfx_queues) 5157 return; 5158 5159 index = 0; 5160 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5161 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5162 adev->gfx.me.num_me, 5163 adev->gfx.me.num_pipe_per_me, 5164 adev->gfx.me.num_queue_per_pipe); 5165 5166 for (i = 0; i < adev->gfx.me.num_me; i++) { 5167 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5168 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5169 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5170 for (reg = 0; reg < reg_count; reg++) { 5171 drm_printf(p, "%-50s \t 0x%08x\n", 5172 gc_gfx_queue_reg_list_12[reg].reg_name, 5173 adev->gfx.ip_dump_gfx_queues[index + reg]); 5174 } 5175 index += reg_count; 5176 } 5177 } 5178 } 5179 } 5180 5181 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5182 { 5183 struct amdgpu_device *adev = ip_block->adev; 5184 uint32_t i, j, k, reg, index = 0; 5185 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5186 5187 if (!adev->gfx.ip_dump_core) 5188 return; 5189 5190 amdgpu_gfx_off_ctrl(adev, false); 5191 for (i = 0; i < reg_count; i++) 5192 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5193 amdgpu_gfx_off_ctrl(adev, true); 5194 5195 /* dump compute queue registers for all instances */ 5196 if (!adev->gfx.ip_dump_compute_queues) 5197 return; 5198 5199 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5200 amdgpu_gfx_off_ctrl(adev, false); 5201 mutex_lock(&adev->srbm_mutex); 5202 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5203 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5204 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5205 /* ME0 is for GFX so start from 1 for CP */ 5206 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5207 for (reg = 0; reg < reg_count; reg++) { 5208 adev->gfx.ip_dump_compute_queues[index + reg] = 5209 RREG32(SOC15_REG_ENTRY_OFFSET( 5210 gc_cp_reg_list_12[reg])); 5211 } 5212 index += reg_count; 5213 } 5214 } 5215 } 5216 soc24_grbm_select(adev, 0, 0, 0, 0); 5217 mutex_unlock(&adev->srbm_mutex); 5218 amdgpu_gfx_off_ctrl(adev, true); 5219 5220 /* dump gfx queue registers for all instances */ 5221 if (!adev->gfx.ip_dump_gfx_queues) 5222 return; 5223 5224 index = 0; 5225 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5226 amdgpu_gfx_off_ctrl(adev, false); 5227 mutex_lock(&adev->srbm_mutex); 5228 for (i = 0; i < adev->gfx.me.num_me; i++) { 5229 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5230 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5231 soc24_grbm_select(adev, i, j, k, 0); 5232 5233 for (reg = 0; reg < reg_count; reg++) { 5234 adev->gfx.ip_dump_gfx_queues[index + reg] = 5235 RREG32(SOC15_REG_ENTRY_OFFSET( 5236 gc_gfx_queue_reg_list_12[reg])); 5237 } 5238 index += reg_count; 5239 } 5240 } 5241 } 5242 soc24_grbm_select(adev, 0, 0, 0, 0); 5243 mutex_unlock(&adev->srbm_mutex); 5244 amdgpu_gfx_off_ctrl(adev, true); 5245 } 5246 5247 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5248 { 5249 /* Disable the pipe reset until the CPFW fully support it.*/ 5250 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5251 return false; 5252 } 5253 5254 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5255 { 5256 struct amdgpu_device *adev = ring->adev; 5257 uint32_t reset_pipe = 0, clean_pipe = 0; 5258 int r; 5259 5260 if (!gfx_v12_pipe_reset_support(adev)) 5261 return -EOPNOTSUPP; 5262 5263 gfx_v12_0_set_safe_mode(adev, 0); 5264 mutex_lock(&adev->srbm_mutex); 5265 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5266 5267 switch (ring->pipe) { 5268 case 0: 5269 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5270 PFP_PIPE0_RESET, 1); 5271 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5272 ME_PIPE0_RESET, 1); 5273 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5274 PFP_PIPE0_RESET, 0); 5275 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5276 ME_PIPE0_RESET, 0); 5277 break; 5278 case 1: 5279 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5280 PFP_PIPE1_RESET, 1); 5281 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5282 ME_PIPE1_RESET, 1); 5283 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5284 PFP_PIPE1_RESET, 0); 5285 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5286 ME_PIPE1_RESET, 0); 5287 break; 5288 default: 5289 break; 5290 } 5291 5292 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5293 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5294 5295 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5296 RS64_FW_UC_START_ADDR_LO; 5297 soc24_grbm_select(adev, 0, 0, 0, 0); 5298 mutex_unlock(&adev->srbm_mutex); 5299 gfx_v12_0_unset_safe_mode(adev, 0); 5300 5301 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5302 r == 0 ? "successfully" : "failed"); 5303 /* Sometimes the ME start pc counter can't cache correctly, so the 5304 * PC check only as a reference and pipe reset result rely on the 5305 * later ring test. 5306 */ 5307 return 0; 5308 } 5309 5310 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 5311 { 5312 struct amdgpu_device *adev = ring->adev; 5313 int r; 5314 5315 if (amdgpu_sriov_vf(adev)) 5316 return -EINVAL; 5317 5318 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5319 if (r) { 5320 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5321 r = gfx_v12_reset_gfx_pipe(ring); 5322 if (r) 5323 return r; 5324 } 5325 5326 r = gfx_v12_0_kgq_init_queue(ring, true); 5327 if (r) { 5328 dev_err(adev->dev, "failed to init kgq\n"); 5329 return r; 5330 } 5331 5332 r = amdgpu_mes_map_legacy_queue(adev, ring); 5333 if (r) { 5334 dev_err(adev->dev, "failed to remap kgq\n"); 5335 return r; 5336 } 5337 5338 return amdgpu_ring_test_ring(ring); 5339 } 5340 5341 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5342 { 5343 struct amdgpu_device *adev = ring->adev; 5344 uint32_t reset_pipe = 0, clean_pipe = 0; 5345 int r = 0; 5346 5347 if (!gfx_v12_pipe_reset_support(adev)) 5348 return -EOPNOTSUPP; 5349 5350 gfx_v12_0_set_safe_mode(adev, 0); 5351 mutex_lock(&adev->srbm_mutex); 5352 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5353 5354 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5355 clean_pipe = reset_pipe; 5356 5357 if (adev->gfx.rs64_enable) { 5358 switch (ring->pipe) { 5359 case 0: 5360 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5361 MEC_PIPE0_RESET, 1); 5362 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5363 MEC_PIPE0_RESET, 0); 5364 break; 5365 case 1: 5366 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5367 MEC_PIPE1_RESET, 1); 5368 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5369 MEC_PIPE1_RESET, 0); 5370 break; 5371 case 2: 5372 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5373 MEC_PIPE2_RESET, 1); 5374 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5375 MEC_PIPE2_RESET, 0); 5376 break; 5377 case 3: 5378 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5379 MEC_PIPE3_RESET, 1); 5380 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5381 MEC_PIPE3_RESET, 0); 5382 break; 5383 default: 5384 break; 5385 } 5386 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5387 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5388 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5389 RS64_FW_UC_START_ADDR_LO; 5390 } else { 5391 switch (ring->pipe) { 5392 case 0: 5393 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5394 MEC_ME1_PIPE0_RESET, 1); 5395 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5396 MEC_ME1_PIPE0_RESET, 0); 5397 break; 5398 case 1: 5399 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5400 MEC_ME1_PIPE1_RESET, 1); 5401 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5402 MEC_ME1_PIPE1_RESET, 0); 5403 break; 5404 default: 5405 break; 5406 } 5407 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5408 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5409 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5410 * the driver won't run into the F32 mode. 5411 */ 5412 } 5413 5414 soc24_grbm_select(adev, 0, 0, 0, 0); 5415 mutex_unlock(&adev->srbm_mutex); 5416 gfx_v12_0_unset_safe_mode(adev, 0); 5417 5418 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5419 r == 0 ? "successfully" : "failed"); 5420 /* Need the ring test to verify the pipe reset result.*/ 5421 return 0; 5422 } 5423 5424 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 5425 { 5426 struct amdgpu_device *adev = ring->adev; 5427 int r; 5428 5429 if (amdgpu_sriov_vf(adev)) 5430 return -EINVAL; 5431 5432 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5433 if (r) { 5434 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5435 r = gfx_v12_0_reset_compute_pipe(ring); 5436 if (r) 5437 return r; 5438 } 5439 5440 r = gfx_v12_0_kcq_init_queue(ring, true); 5441 if (r) { 5442 dev_err(adev->dev, "failed to init kcq\n"); 5443 return r; 5444 } 5445 r = amdgpu_mes_map_legacy_queue(adev, ring); 5446 if (r) { 5447 dev_err(adev->dev, "failed to remap kcq\n"); 5448 return r; 5449 } 5450 5451 return amdgpu_ring_test_ring(ring); 5452 } 5453 5454 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5455 { 5456 amdgpu_gfx_profile_ring_begin_use(ring); 5457 5458 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5459 } 5460 5461 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5462 { 5463 amdgpu_gfx_profile_ring_end_use(ring); 5464 5465 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5466 } 5467 5468 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5469 .name = "gfx_v12_0", 5470 .early_init = gfx_v12_0_early_init, 5471 .late_init = gfx_v12_0_late_init, 5472 .sw_init = gfx_v12_0_sw_init, 5473 .sw_fini = gfx_v12_0_sw_fini, 5474 .hw_init = gfx_v12_0_hw_init, 5475 .hw_fini = gfx_v12_0_hw_fini, 5476 .suspend = gfx_v12_0_suspend, 5477 .resume = gfx_v12_0_resume, 5478 .is_idle = gfx_v12_0_is_idle, 5479 .wait_for_idle = gfx_v12_0_wait_for_idle, 5480 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5481 .set_powergating_state = gfx_v12_0_set_powergating_state, 5482 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5483 .dump_ip_state = gfx_v12_ip_dump, 5484 .print_ip_state = gfx_v12_ip_print, 5485 }; 5486 5487 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5488 .type = AMDGPU_RING_TYPE_GFX, 5489 .align_mask = 0xff, 5490 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5491 .support_64bit_ptrs = true, 5492 .secure_submission_supported = true, 5493 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5494 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5495 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5496 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5497 5 + /* COND_EXEC */ 5498 7 + /* PIPELINE_SYNC */ 5499 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5500 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5501 2 + /* VM_FLUSH */ 5502 8 + /* FENCE for VM_FLUSH */ 5503 5 + /* COND_EXEC */ 5504 7 + /* HDP_flush */ 5505 4 + /* VGT_flush */ 5506 31 + /* DE_META */ 5507 3 + /* CNTX_CTRL */ 5508 5 + /* HDP_INVL */ 5509 8 + 8 + /* FENCE x2 */ 5510 8 + /* gfx_v12_0_emit_mem_sync */ 5511 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5512 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5513 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5514 .emit_fence = gfx_v12_0_ring_emit_fence, 5515 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5516 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5517 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5518 .test_ring = gfx_v12_0_ring_test_ring, 5519 .test_ib = gfx_v12_0_ring_test_ib, 5520 .insert_nop = gfx_v12_ring_insert_nop, 5521 .pad_ib = amdgpu_ring_generic_pad_ib, 5522 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5523 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5524 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5525 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl, 5526 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5527 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5528 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5529 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5530 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5531 .reset = gfx_v12_0_reset_kgq, 5532 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5533 .begin_use = gfx_v12_0_ring_begin_use, 5534 .end_use = gfx_v12_0_ring_end_use, 5535 }; 5536 5537 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5538 .type = AMDGPU_RING_TYPE_COMPUTE, 5539 .align_mask = 0xff, 5540 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5541 .support_64bit_ptrs = true, 5542 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5543 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5544 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5545 .emit_frame_size = 5546 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5547 5 + /* hdp invalidate */ 5548 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5549 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5550 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5551 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5552 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5553 8 + /* gfx_v12_0_emit_mem_sync */ 5554 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5555 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5556 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5557 .emit_fence = gfx_v12_0_ring_emit_fence, 5558 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5559 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5560 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5561 .test_ring = gfx_v12_0_ring_test_ring, 5562 .test_ib = gfx_v12_0_ring_test_ib, 5563 .insert_nop = gfx_v12_ring_insert_nop, 5564 .pad_ib = amdgpu_ring_generic_pad_ib, 5565 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5566 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5567 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5568 .soft_recovery = gfx_v12_0_ring_soft_recovery, 5569 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5570 .reset = gfx_v12_0_reset_kcq, 5571 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5572 .begin_use = gfx_v12_0_ring_begin_use, 5573 .end_use = gfx_v12_0_ring_end_use, 5574 }; 5575 5576 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5577 .type = AMDGPU_RING_TYPE_KIQ, 5578 .align_mask = 0xff, 5579 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5580 .support_64bit_ptrs = true, 5581 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5582 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5583 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5584 .emit_frame_size = 5585 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5586 5 + /*hdp invalidate */ 5587 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5588 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5589 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5590 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5591 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5592 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5593 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5594 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5595 .test_ring = gfx_v12_0_ring_test_ring, 5596 .test_ib = gfx_v12_0_ring_test_ib, 5597 .insert_nop = amdgpu_ring_insert_nop, 5598 .pad_ib = amdgpu_ring_generic_pad_ib, 5599 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5600 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5601 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5602 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5603 }; 5604 5605 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5606 { 5607 int i; 5608 5609 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5610 5611 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5612 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5613 5614 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5615 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5616 } 5617 5618 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5619 .set = gfx_v12_0_set_eop_interrupt_state, 5620 .process = gfx_v12_0_eop_irq, 5621 }; 5622 5623 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5624 .set = gfx_v12_0_set_priv_reg_fault_state, 5625 .process = gfx_v12_0_priv_reg_irq, 5626 }; 5627 5628 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5629 .set = gfx_v12_0_set_bad_op_fault_state, 5630 .process = gfx_v12_0_bad_op_irq, 5631 }; 5632 5633 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5634 .set = gfx_v12_0_set_priv_inst_fault_state, 5635 .process = gfx_v12_0_priv_inst_irq, 5636 }; 5637 5638 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5639 { 5640 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5641 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5642 5643 adev->gfx.priv_reg_irq.num_types = 1; 5644 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5645 5646 adev->gfx.bad_op_irq.num_types = 1; 5647 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5648 5649 adev->gfx.priv_inst_irq.num_types = 1; 5650 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5651 } 5652 5653 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5654 { 5655 if (adev->flags & AMD_IS_APU) 5656 adev->gfx.imu.mode = MISSION_MODE; 5657 else 5658 adev->gfx.imu.mode = DEBUG_MODE; 5659 5660 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5661 } 5662 5663 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5664 { 5665 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5666 } 5667 5668 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5669 { 5670 /* set gfx eng mqd */ 5671 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5672 sizeof(struct v12_gfx_mqd); 5673 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5674 gfx_v12_0_gfx_mqd_init; 5675 /* set compute eng mqd */ 5676 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5677 sizeof(struct v12_compute_mqd); 5678 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5679 gfx_v12_0_compute_mqd_init; 5680 } 5681 5682 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5683 u32 bitmap) 5684 { 5685 u32 data; 5686 5687 if (!bitmap) 5688 return; 5689 5690 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5691 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5692 5693 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5694 } 5695 5696 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5697 { 5698 u32 data, wgp_bitmask; 5699 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5700 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5701 5702 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5703 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5704 5705 wgp_bitmask = 5706 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5707 5708 return (~data) & wgp_bitmask; 5709 } 5710 5711 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5712 { 5713 u32 wgp_idx, wgp_active_bitmap; 5714 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5715 5716 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5717 cu_active_bitmap = 0; 5718 5719 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5720 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5721 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5722 if (wgp_active_bitmap & (1 << wgp_idx)) 5723 cu_active_bitmap |= cu_bitmap_per_wgp; 5724 } 5725 5726 return cu_active_bitmap; 5727 } 5728 5729 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5730 struct amdgpu_cu_info *cu_info) 5731 { 5732 int i, j, k, counter, active_cu_number = 0; 5733 u32 mask, bitmap; 5734 unsigned disable_masks[8 * 2]; 5735 5736 if (!adev || !cu_info) 5737 return -EINVAL; 5738 5739 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5740 5741 mutex_lock(&adev->grbm_idx_mutex); 5742 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5743 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5744 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5745 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5746 continue; 5747 mask = 1; 5748 counter = 0; 5749 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5750 if (i < 8 && j < 2) 5751 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5752 adev, disable_masks[i * 2 + j]); 5753 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5754 5755 /** 5756 * GFX12 could support more than 4 SEs, while the bitmap 5757 * in cu_info struct is 4x4 and ioctl interface struct 5758 * drm_amdgpu_info_device should keep stable. 5759 * So we use last two columns of bitmap to store cu mask for 5760 * SEs 4 to 7, the layout of the bitmap is as below: 5761 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5762 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5763 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5764 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5765 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5766 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5767 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5768 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5769 */ 5770 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5771 5772 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5773 if (bitmap & mask) 5774 counter++; 5775 5776 mask <<= 1; 5777 } 5778 active_cu_number += counter; 5779 } 5780 } 5781 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5782 mutex_unlock(&adev->grbm_idx_mutex); 5783 5784 cu_info->number = active_cu_number; 5785 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5786 5787 return 0; 5788 } 5789 5790 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5791 .type = AMD_IP_BLOCK_TYPE_GFX, 5792 .major = 12, 5793 .minor = 0, 5794 .rev = 0, 5795 .funcs = &gfx_v12_0_ip_funcs, 5796 }; 5797