1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_userq_priv_fault_work(struct work_struct *work); 290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 291 bool enable); 292 293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 294 uint64_t queue_mask) 295 { 296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 304 amdgpu_ring_write(kiq_ring, 0); 305 } 306 307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 308 struct amdgpu_ring *ring) 309 { 310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 311 uint64_t wptr_addr = ring->wptr_gpu_addr; 312 uint32_t me = 0, eng_sel = 0; 313 314 switch (ring->funcs->type) { 315 case AMDGPU_RING_TYPE_COMPUTE: 316 me = 1; 317 eng_sel = 0; 318 break; 319 case AMDGPU_RING_TYPE_GFX: 320 me = 0; 321 eng_sel = 4; 322 break; 323 case AMDGPU_RING_TYPE_MES: 324 me = 2; 325 eng_sel = 5; 326 break; 327 default: 328 WARN_ON(1); 329 } 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 338 PACKET3_MAP_QUEUES_ME((me)) | 339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 348 } 349 350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 351 struct amdgpu_ring *ring, 352 enum amdgpu_unmap_queues_action action, 353 u64 gpu_addr, u64 seq) 354 { 355 struct amdgpu_device *adev = kiq_ring->adev; 356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 357 358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 360 gpu_addr, seq, 0); 361 return; 362 } 363 364 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 366 PACKET3_UNMAP_QUEUES_ACTION(action) | 367 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 368 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 369 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 370 amdgpu_ring_write(kiq_ring, 371 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 372 373 if (action == PREEMPT_QUEUES_NO_UNMAP) { 374 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 376 amdgpu_ring_write(kiq_ring, seq); 377 } else { 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 amdgpu_ring_write(kiq_ring, 0); 381 } 382 } 383 384 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 385 struct amdgpu_ring *ring, 386 u64 addr, u64 seq) 387 { 388 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 389 390 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 391 amdgpu_ring_write(kiq_ring, 392 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 393 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 394 PACKET3_QUERY_STATUS_COMMAND(2)); 395 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 396 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 397 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 398 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 400 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 401 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 402 } 403 404 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 405 uint16_t pasid, 406 uint32_t flush_type, 407 bool all_hub) 408 { 409 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 410 } 411 412 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 413 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 414 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 415 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 416 .kiq_query_status = gfx_v12_0_kiq_query_status, 417 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 418 .set_resources_size = 8, 419 .map_queues_size = 7, 420 .unmap_queues_size = 6, 421 .query_status_size = 7, 422 .invalidate_tlbs_size = 2, 423 }; 424 425 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 426 { 427 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 428 } 429 430 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 431 int mem_space, int opt, uint32_t addr0, 432 uint32_t addr1, uint32_t ref, 433 uint32_t mask, uint32_t inv) 434 { 435 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 436 amdgpu_ring_write(ring, 437 /* memory (1) or register (0) */ 438 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 439 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 440 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 441 WAIT_REG_MEM_ENGINE(eng_sel))); 442 443 if (mem_space) 444 WARN_ON(addr0 & 0x3); /* Dword align */ 445 amdgpu_ring_write(ring, addr0); 446 amdgpu_ring_write(ring, addr1); 447 amdgpu_ring_write(ring, ref); 448 amdgpu_ring_write(ring, mask); 449 amdgpu_ring_write(ring, inv); /* poll interval */ 450 } 451 452 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 453 { 454 struct amdgpu_device *adev = ring->adev; 455 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 456 uint32_t tmp = 0; 457 unsigned i; 458 int r; 459 460 WREG32(scratch, 0xCAFEDEAD); 461 r = amdgpu_ring_alloc(ring, 5); 462 if (r) { 463 drm_err(adev_to_drm(adev), 464 "cp failed to lock ring %d (%d).\n", 465 ring->idx, r); 466 return r; 467 } 468 469 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 470 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 471 } else { 472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 473 amdgpu_ring_write(ring, scratch - 474 PACKET3_SET_UCONFIG_REG_START); 475 amdgpu_ring_write(ring, 0xDEADBEEF); 476 } 477 amdgpu_ring_commit(ring); 478 479 for (i = 0; i < adev->usec_timeout; i++) { 480 tmp = RREG32(scratch); 481 if (tmp == 0xDEADBEEF) 482 break; 483 if (amdgpu_emu_mode == 1) 484 msleep(1); 485 else 486 udelay(1); 487 } 488 489 if (i >= adev->usec_timeout) 490 r = -ETIMEDOUT; 491 return r; 492 } 493 494 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 495 { 496 struct amdgpu_device *adev = ring->adev; 497 struct amdgpu_ib ib; 498 struct dma_fence *f = NULL; 499 unsigned index; 500 uint64_t gpu_addr; 501 uint32_t *cpu_ptr; 502 long r; 503 504 /* MES KIQ fw hasn't indirect buffer support for now */ 505 if (adev->enable_mes_kiq && 506 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 507 return 0; 508 509 memset(&ib, 0, sizeof(ib)); 510 511 r = amdgpu_wb_get(adev, &index); 512 if (r) 513 return r; 514 515 gpu_addr = adev->wb.gpu_addr + (index * 4); 516 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 517 cpu_ptr = &adev->wb.wb[index]; 518 519 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 520 if (r) { 521 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 522 goto err1; 523 } 524 525 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 526 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 527 ib.ptr[2] = lower_32_bits(gpu_addr); 528 ib.ptr[3] = upper_32_bits(gpu_addr); 529 ib.ptr[4] = 0xDEADBEEF; 530 ib.length_dw = 5; 531 532 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 533 if (r) 534 goto err2; 535 536 r = dma_fence_wait_timeout(f, false, timeout); 537 if (r == 0) { 538 r = -ETIMEDOUT; 539 goto err2; 540 } else if (r < 0) { 541 goto err2; 542 } 543 544 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 545 r = 0; 546 else 547 r = -EINVAL; 548 err2: 549 amdgpu_ib_free(&ib, NULL); 550 dma_fence_put(f); 551 err1: 552 amdgpu_wb_free(adev, index); 553 return r; 554 } 555 556 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 557 { 558 amdgpu_ucode_release(&adev->gfx.pfp_fw); 559 amdgpu_ucode_release(&adev->gfx.me_fw); 560 amdgpu_ucode_release(&adev->gfx.rlc_fw); 561 amdgpu_ucode_release(&adev->gfx.mec_fw); 562 563 kfree(adev->gfx.rlc.register_list_format); 564 } 565 566 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 567 { 568 const struct psp_firmware_header_v1_0 *toc_hdr; 569 int err = 0; 570 571 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_toc.bin", ucode_prefix); 574 if (err) 575 goto out; 576 577 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 578 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 579 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 580 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 581 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 582 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 583 return 0; 584 out: 585 amdgpu_ucode_release(&adev->psp.toc_fw); 586 return err; 587 } 588 589 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 590 { 591 char ucode_prefix[30]; 592 int err; 593 const struct rlc_firmware_header_v2_0 *rlc_hdr; 594 uint16_t version_major; 595 uint16_t version_minor; 596 597 DRM_DEBUG("\n"); 598 599 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 600 601 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 602 AMDGPU_UCODE_REQUIRED, 603 "amdgpu/%s_pfp.bin", ucode_prefix); 604 if (err) 605 goto out; 606 607 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 608 (union amdgpu_firmware_header *) 609 adev->gfx.pfp_fw->data, 2, 0); 610 if (adev->gfx.rs64_enable) 611 dev_dbg(adev->dev, "CP RS64 enable\n"); 612 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 615 616 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 617 AMDGPU_UCODE_REQUIRED, 618 "amdgpu/%s_me.bin", ucode_prefix); 619 if (err) 620 goto out; 621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 622 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 623 624 if (!amdgpu_sriov_vf(adev)) { 625 if (amdgpu_is_kicker_fw(adev)) 626 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 627 AMDGPU_UCODE_REQUIRED, 628 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 629 else 630 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 631 AMDGPU_UCODE_REQUIRED, 632 "amdgpu/%s_rlc.bin", ucode_prefix); 633 if (err) 634 goto out; 635 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 636 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 637 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 638 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 639 if (err) 640 goto out; 641 } 642 643 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 644 AMDGPU_UCODE_REQUIRED, 645 "amdgpu/%s_mec.bin", ucode_prefix); 646 if (err) 647 goto out; 648 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 649 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 650 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 651 652 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 653 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 654 655 /* only one MEC for gfx 12 */ 656 adev->gfx.mec2_fw = NULL; 657 658 if (adev->gfx.imu.funcs) { 659 if (adev->gfx.imu.funcs->init_microcode) { 660 err = adev->gfx.imu.funcs->init_microcode(adev); 661 if (err) 662 dev_err(adev->dev, "Failed to load imu firmware!\n"); 663 } 664 } 665 666 out: 667 if (err) { 668 amdgpu_ucode_release(&adev->gfx.pfp_fw); 669 amdgpu_ucode_release(&adev->gfx.me_fw); 670 amdgpu_ucode_release(&adev->gfx.rlc_fw); 671 amdgpu_ucode_release(&adev->gfx.mec_fw); 672 } 673 674 return err; 675 } 676 677 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 678 { 679 u32 count = 0; 680 const struct cs_section_def *sect = NULL; 681 const struct cs_extent_def *ext = NULL; 682 683 count += 1; 684 685 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 686 if (sect->id == SECT_CONTEXT) { 687 for (ext = sect->section; ext->extent != NULL; ++ext) 688 count += 2 + ext->reg_count; 689 } else 690 return 0; 691 } 692 693 return count; 694 } 695 696 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 697 { 698 u32 count = 0, clustercount = 0, i; 699 const struct cs_section_def *sect = NULL; 700 const struct cs_extent_def *ext = NULL; 701 702 if (adev->gfx.rlc.cs_data == NULL) 703 return; 704 if (buffer == NULL) 705 return; 706 707 count += 1; 708 709 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 710 if (sect->id == SECT_CONTEXT) { 711 for (ext = sect->section; ext->extent != NULL; ++ext) { 712 clustercount++; 713 buffer[count++] = ext->reg_count; 714 buffer[count++] = ext->reg_index; 715 716 for (i = 0; i < ext->reg_count; i++) 717 buffer[count++] = cpu_to_le32(ext->extent[i]); 718 } 719 } else 720 return; 721 } 722 723 buffer[0] = clustercount; 724 } 725 726 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 727 { 728 /* clear state block */ 729 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 730 &adev->gfx.rlc.clear_state_gpu_addr, 731 (void **)&adev->gfx.rlc.cs_ptr); 732 733 /* jump table block */ 734 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 735 &adev->gfx.rlc.cp_table_gpu_addr, 736 (void **)&adev->gfx.rlc.cp_table_ptr); 737 } 738 739 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 740 { 741 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 742 743 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 744 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 745 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 746 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 747 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 748 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 749 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 750 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 751 adev->gfx.rlc.rlcg_reg_access_supported = true; 752 } 753 754 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 755 { 756 const struct cs_section_def *cs_data; 757 int r; 758 759 adev->gfx.rlc.cs_data = gfx12_cs_data; 760 761 cs_data = adev->gfx.rlc.cs_data; 762 763 if (cs_data) { 764 /* init clear state block */ 765 r = amdgpu_gfx_rlc_init_csb(adev); 766 if (r) 767 return r; 768 } 769 770 /* init spm vmid with 0xf */ 771 if (adev->gfx.rlc.funcs->update_spm_vmid) 772 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 773 774 return 0; 775 } 776 777 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 778 { 779 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 780 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 781 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 782 } 783 784 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 785 { 786 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 787 788 amdgpu_gfx_graphics_queue_acquire(adev); 789 } 790 791 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 792 { 793 int r; 794 u32 *hpd; 795 size_t mec_hpd_size; 796 797 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 798 799 /* take ownership of the relevant compute queues */ 800 amdgpu_gfx_compute_queue_acquire(adev); 801 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 802 803 if (mec_hpd_size) { 804 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 805 AMDGPU_GEM_DOMAIN_GTT, 806 &adev->gfx.mec.hpd_eop_obj, 807 &adev->gfx.mec.hpd_eop_gpu_addr, 808 (void **)&hpd); 809 if (r) { 810 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 811 gfx_v12_0_mec_fini(adev); 812 return r; 813 } 814 815 memset(hpd, 0, mec_hpd_size); 816 817 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 818 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 819 } 820 821 return 0; 822 } 823 824 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 825 { 826 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 827 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 828 (address << SQ_IND_INDEX__INDEX__SHIFT)); 829 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 830 } 831 832 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 833 uint32_t thread, uint32_t regno, 834 uint32_t num, uint32_t *out) 835 { 836 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 837 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 838 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 839 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 840 (SQ_IND_INDEX__AUTO_INCR_MASK)); 841 while (num--) 842 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 843 } 844 845 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 846 uint32_t xcc_id, 847 uint32_t simd, uint32_t wave, 848 uint32_t *dst, int *no_fields) 849 { 850 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 851 * field when performing a select_se_sh so it should be 852 * zero here */ 853 WARN_ON(simd != 0); 854 855 /* type 4 wave data */ 856 dst[(*no_fields)++] = 4; 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 873 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 874 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 875 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 876 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 877 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 878 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 879 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 880 } 881 882 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 883 uint32_t xcc_id, uint32_t simd, 884 uint32_t wave, uint32_t start, 885 uint32_t size, uint32_t *dst) 886 { 887 WARN_ON(simd != 0); 888 889 wave_read_regs( 890 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 891 dst); 892 } 893 894 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 895 uint32_t xcc_id, uint32_t simd, 896 uint32_t wave, uint32_t thread, 897 uint32_t start, uint32_t size, 898 uint32_t *dst) 899 { 900 wave_read_regs( 901 adev, wave, thread, 902 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 903 } 904 905 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 906 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 907 { 908 soc24_grbm_select(adev, me, pipe, q, vm); 909 } 910 911 /* all sizes are in bytes */ 912 #define MQD_SHADOW_BASE_SIZE 73728 913 #define MQD_SHADOW_BASE_ALIGNMENT 256 914 #define MQD_FWWORKAREA_SIZE 484 915 #define MQD_FWWORKAREA_ALIGNMENT 256 916 917 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 918 struct amdgpu_gfx_shadow_info *shadow_info) 919 { 920 /* for gfx */ 921 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 922 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 923 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 924 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 925 /* for compute */ 926 shadow_info->eop_size = GFX12_MEC_HPD_SIZE; 927 shadow_info->eop_alignment = 256; 928 } 929 930 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 931 struct amdgpu_gfx_shadow_info *shadow_info, 932 bool skip_check) 933 { 934 if (adev->gfx.cp_gfx_shadow || skip_check) { 935 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 936 return 0; 937 } 938 939 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 940 return -EINVAL; 941 } 942 943 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 944 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 945 .select_se_sh = &gfx_v12_0_select_se_sh, 946 .read_wave_data = &gfx_v12_0_read_wave_data, 947 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 948 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 949 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 950 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 951 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 952 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 953 }; 954 955 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 956 { 957 958 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 959 case IP_VERSION(12, 0, 0): 960 case IP_VERSION(12, 0, 1): 961 adev->gfx.config.max_hw_contexts = 8; 962 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 963 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 964 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 965 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 966 break; 967 default: 968 dev_warn(adev->dev, "Unsupported GC version 0x%08x\n", 969 amdgpu_ip_version(adev, GC_HWIP, 0)); 970 return -EINVAL; 971 } 972 973 return 0; 974 } 975 976 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 977 int me, int pipe, int queue) 978 { 979 int r; 980 struct amdgpu_ring *ring; 981 unsigned int irq_type; 982 983 ring = &adev->gfx.gfx_ring[ring_id]; 984 985 ring->me = me; 986 ring->pipe = pipe; 987 ring->queue = queue; 988 989 ring->ring_obj = NULL; 990 ring->use_doorbell = true; 991 992 if (!ring_id) 993 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 994 else 995 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 996 ring->vm_hub = AMDGPU_GFXHUB(0); 997 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 998 999 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1000 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1001 AMDGPU_RING_PRIO_DEFAULT, NULL); 1002 if (r) 1003 return r; 1004 return 0; 1005 } 1006 1007 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1008 int mec, int pipe, int queue) 1009 { 1010 int r; 1011 unsigned irq_type; 1012 struct amdgpu_ring *ring; 1013 unsigned int hw_prio; 1014 1015 ring = &adev->gfx.compute_ring[ring_id]; 1016 1017 /* mec0 is me1 */ 1018 ring->me = mec + 1; 1019 ring->pipe = pipe; 1020 ring->queue = queue; 1021 1022 ring->ring_obj = NULL; 1023 ring->use_doorbell = true; 1024 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1025 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1026 + (ring_id * GFX12_MEC_HPD_SIZE); 1027 ring->vm_hub = AMDGPU_GFXHUB(0); 1028 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1029 1030 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1031 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1032 + ring->pipe; 1033 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1034 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1035 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1036 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1037 hw_prio, NULL); 1038 if (r) 1039 return r; 1040 1041 return 0; 1042 } 1043 1044 static struct { 1045 SOC24_FIRMWARE_ID id; 1046 unsigned int offset; 1047 unsigned int size; 1048 unsigned int size_x16; 1049 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1050 1051 #define RLC_TOC_OFFSET_DWUNIT 8 1052 #define RLC_SIZE_MULTIPLE 1024 1053 #define RLC_TOC_UMF_SIZE_inM 23ULL 1054 #define RLC_TOC_FORMAT_API 165ULL 1055 1056 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1057 { 1058 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1059 1060 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1061 rlc_autoload_info[ucode->id].id = ucode->id; 1062 rlc_autoload_info[ucode->id].offset = 1063 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1064 rlc_autoload_info[ucode->id].size = 1065 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1066 ucode->size * 4; 1067 ucode++; 1068 } 1069 } 1070 1071 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1072 { 1073 uint32_t total_size = 0; 1074 SOC24_FIRMWARE_ID id; 1075 1076 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1077 1078 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1079 total_size += rlc_autoload_info[id].size; 1080 1081 /* In case the offset in rlc toc ucode is aligned */ 1082 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1083 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1084 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1085 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1086 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1087 1088 return total_size; 1089 } 1090 1091 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1092 { 1093 int r; 1094 uint32_t total_size; 1095 1096 total_size = gfx_v12_0_calc_toc_total_size(adev); 1097 1098 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1099 AMDGPU_GEM_DOMAIN_VRAM, 1100 &adev->gfx.rlc.rlc_autoload_bo, 1101 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1102 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1103 1104 if (r) { 1105 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1106 return r; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1113 SOC24_FIRMWARE_ID id, 1114 const void *fw_data, 1115 uint32_t fw_size) 1116 { 1117 uint32_t toc_offset; 1118 uint32_t toc_fw_size; 1119 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1120 1121 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1122 return; 1123 1124 toc_offset = rlc_autoload_info[id].offset; 1125 toc_fw_size = rlc_autoload_info[id].size; 1126 1127 if (fw_size == 0) 1128 fw_size = toc_fw_size; 1129 1130 if (fw_size > toc_fw_size) 1131 fw_size = toc_fw_size; 1132 1133 memcpy(ptr + toc_offset, fw_data, fw_size); 1134 1135 if (fw_size < toc_fw_size) 1136 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1137 } 1138 1139 static void 1140 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1141 { 1142 void *data; 1143 uint32_t size; 1144 uint32_t *toc_ptr; 1145 1146 data = adev->psp.toc.start_addr; 1147 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1148 1149 toc_ptr = (uint32_t *)data + size / 4 - 2; 1150 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1151 1152 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1153 data, size); 1154 } 1155 1156 static void 1157 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1158 { 1159 const __le32 *fw_data; 1160 uint32_t fw_size; 1161 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1162 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1163 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1164 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1165 uint16_t version_major, version_minor; 1166 1167 /* pfp ucode */ 1168 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1169 adev->gfx.pfp_fw->data; 1170 /* instruction */ 1171 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1172 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1173 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1174 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1175 fw_data, fw_size); 1176 /* data */ 1177 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1178 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1179 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1181 fw_data, fw_size); 1182 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1183 fw_data, fw_size); 1184 /* me ucode */ 1185 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1186 adev->gfx.me_fw->data; 1187 /* instruction */ 1188 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1189 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1190 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1191 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1192 fw_data, fw_size); 1193 /* data */ 1194 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1195 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1196 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1198 fw_data, fw_size); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1200 fw_data, fw_size); 1201 /* mec ucode */ 1202 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1203 adev->gfx.mec_fw->data; 1204 /* instruction */ 1205 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1206 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1207 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1208 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1209 fw_data, fw_size); 1210 /* data */ 1211 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1212 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1213 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1214 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1215 fw_data, fw_size); 1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1217 fw_data, fw_size); 1218 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1219 fw_data, fw_size); 1220 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1221 fw_data, fw_size); 1222 1223 /* rlc ucode */ 1224 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1225 adev->gfx.rlc_fw->data; 1226 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1227 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1228 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1229 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1230 fw_data, fw_size); 1231 1232 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1233 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1234 if (version_major == 2) { 1235 if (version_minor >= 1) { 1236 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1237 1238 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1239 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1240 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1241 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1242 fw_data, fw_size); 1243 1244 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1245 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1246 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1247 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1248 fw_data, fw_size); 1249 } 1250 if (version_minor >= 2) { 1251 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1252 1253 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1254 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1255 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1256 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1257 fw_data, fw_size); 1258 1259 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1260 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1261 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1262 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1263 fw_data, fw_size); 1264 } 1265 } 1266 } 1267 1268 static void 1269 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1270 { 1271 const __le32 *fw_data; 1272 uint32_t fw_size; 1273 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1274 1275 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1276 adev->sdma.instance[0].fw->data; 1277 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1278 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1279 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1280 1281 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1282 fw_data, fw_size); 1283 } 1284 1285 static void 1286 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1287 { 1288 const __le32 *fw_data; 1289 unsigned fw_size; 1290 const struct mes_firmware_header_v1_0 *mes_hdr; 1291 int pipe, ucode_id, data_id; 1292 1293 for (pipe = 0; pipe < 2; pipe++) { 1294 if (pipe == 0) { 1295 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1296 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1297 } else { 1298 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1299 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1300 } 1301 1302 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1303 adev->mes.fw[pipe]->data; 1304 1305 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1306 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1307 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1308 1309 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1310 1311 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1312 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1313 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1314 1315 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1316 } 1317 } 1318 1319 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1320 { 1321 uint32_t rlc_g_offset, rlc_g_size; 1322 uint64_t gpu_addr; 1323 uint32_t data; 1324 1325 /* RLC autoload sequence 2: copy ucode */ 1326 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1327 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1328 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1329 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1330 1331 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1332 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1333 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1334 1335 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1336 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1337 1338 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1339 1340 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1341 /* RLC autoload sequence 3: load IMU fw */ 1342 if (adev->gfx.imu.funcs->load_microcode) 1343 adev->gfx.imu.funcs->load_microcode(adev); 1344 /* RLC autoload sequence 4 init IMU fw */ 1345 if (adev->gfx.imu.funcs->setup_imu) 1346 adev->gfx.imu.funcs->setup_imu(adev); 1347 if (adev->gfx.imu.funcs->start_imu) 1348 adev->gfx.imu.funcs->start_imu(adev); 1349 1350 /* RLC autoload sequence 5 disable gpa mode */ 1351 gfx_v12_0_disable_gpa_mode(adev); 1352 } else { 1353 /* unhalt rlc to start autoload without imu */ 1354 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1355 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1356 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1357 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1358 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1359 } 1360 1361 return 0; 1362 } 1363 1364 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1365 { 1366 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1367 uint32_t *ptr; 1368 uint32_t inst; 1369 1370 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1371 if (!ptr) { 1372 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1373 adev->gfx.ip_dump_core = NULL; 1374 } else { 1375 adev->gfx.ip_dump_core = ptr; 1376 } 1377 1378 /* Allocate memory for compute queue registers for all the instances */ 1379 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1380 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1381 adev->gfx.mec.num_queue_per_pipe; 1382 1383 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1384 if (!ptr) { 1385 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1386 adev->gfx.ip_dump_compute_queues = NULL; 1387 } else { 1388 adev->gfx.ip_dump_compute_queues = ptr; 1389 } 1390 1391 /* Allocate memory for gfx queue registers for all the instances */ 1392 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1393 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1394 adev->gfx.me.num_queue_per_pipe; 1395 1396 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1397 if (!ptr) { 1398 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1399 adev->gfx.ip_dump_gfx_queues = NULL; 1400 } else { 1401 adev->gfx.ip_dump_gfx_queues = ptr; 1402 } 1403 } 1404 1405 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1406 { 1407 int i, j, k, r, ring_id = 0; 1408 unsigned num_compute_rings; 1409 int xcc_id = 0; 1410 struct amdgpu_device *adev = ip_block->adev; 1411 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1412 1413 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1414 1415 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1416 case IP_VERSION(12, 0, 0): 1417 case IP_VERSION(12, 0, 1): 1418 adev->gfx.me.num_me = 1; 1419 adev->gfx.me.num_pipe_per_me = 1; 1420 adev->gfx.me.num_queue_per_pipe = 8; 1421 adev->gfx.mec.num_mec = 1; 1422 adev->gfx.mec.num_pipe_per_mec = 2; 1423 adev->gfx.mec.num_queue_per_pipe = 4; 1424 break; 1425 default: 1426 adev->gfx.me.num_me = 1; 1427 adev->gfx.me.num_pipe_per_me = 1; 1428 adev->gfx.me.num_queue_per_pipe = 1; 1429 adev->gfx.mec.num_mec = 1; 1430 adev->gfx.mec.num_pipe_per_mec = 4; 1431 adev->gfx.mec.num_queue_per_pipe = 8; 1432 break; 1433 } 1434 1435 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1436 case IP_VERSION(12, 0, 0): 1437 case IP_VERSION(12, 0, 1): 1438 if (!adev->gfx.disable_uq && 1439 adev->gfx.me_fw_version >= 3090 && 1440 adev->gfx.pfp_fw_version >= 3190 && 1441 adev->gfx.mec_fw_version >= 3450 && 1442 adev->mes.fw_version[0] >= 147) { 1443 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1444 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1445 } 1446 break; 1447 default: 1448 break; 1449 } 1450 1451 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1452 case IP_VERSION(12, 0, 0): 1453 case IP_VERSION(12, 0, 1): 1454 if (adev->gfx.me_fw_version >= 2480 && 1455 adev->gfx.pfp_fw_version >= 2530 && 1456 adev->gfx.mec_fw_version >= 2680 && 1457 adev->mes.fw_version[0] >= 100) 1458 adev->gfx.enable_cleaner_shader = true; 1459 break; 1460 default: 1461 adev->gfx.enable_cleaner_shader = false; 1462 break; 1463 } 1464 1465 if (adev->gfx.num_compute_rings) { 1466 /* recalculate compute rings to use based on hardware configuration */ 1467 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1468 adev->gfx.mec.num_queue_per_pipe) / 2; 1469 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1470 num_compute_rings); 1471 } 1472 1473 /* EOP Event */ 1474 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1475 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1476 &adev->gfx.eop_irq); 1477 if (r) 1478 return r; 1479 1480 /* Bad opcode Event */ 1481 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1482 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1483 &adev->gfx.bad_op_irq); 1484 if (r) 1485 return r; 1486 1487 /* Privileged reg */ 1488 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1489 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1490 &adev->gfx.priv_reg_irq); 1491 if (r) 1492 return r; 1493 1494 /* Privileged inst */ 1495 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1496 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1497 &adev->gfx.priv_inst_irq); 1498 if (r) 1499 return r; 1500 1501 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1502 1503 gfx_v12_0_me_init(adev); 1504 1505 r = gfx_v12_0_rlc_init(adev); 1506 if (r) { 1507 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1508 return r; 1509 } 1510 1511 r = gfx_v12_0_mec_init(adev); 1512 if (r) { 1513 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1514 return r; 1515 } 1516 1517 if (adev->gfx.num_gfx_rings) { 1518 /* set up the gfx ring */ 1519 for (i = 0; i < adev->gfx.me.num_me; i++) { 1520 for (j = 0; j < num_queue_per_pipe; j++) { 1521 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1522 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1523 continue; 1524 1525 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1526 i, k, j); 1527 if (r) 1528 return r; 1529 ring_id++; 1530 } 1531 } 1532 } 1533 } 1534 1535 if (adev->gfx.num_compute_rings) { 1536 ring_id = 0; 1537 /* set up the compute queues - allocate horizontally across pipes */ 1538 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1539 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1540 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1541 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1542 0, i, k, j)) 1543 continue; 1544 1545 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1546 i, k, j); 1547 if (r) 1548 return r; 1549 1550 ring_id++; 1551 } 1552 } 1553 } 1554 } 1555 1556 adev->gfx.gfx_supported_reset = 1557 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1558 adev->gfx.compute_supported_reset = 1559 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1560 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1561 case IP_VERSION(12, 0, 0): 1562 case IP_VERSION(12, 0, 1): 1563 if ((adev->gfx.me_fw_version >= 2660) && 1564 (adev->gfx.mec_fw_version >= 2920) && 1565 !amdgpu_sriov_vf(adev) && 1566 !adev->debug_disable_gpu_ring_reset) { 1567 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1568 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1569 } 1570 break; 1571 default: 1572 break; 1573 } 1574 1575 if (!adev->enable_mes_kiq) { 1576 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1577 if (r) { 1578 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1579 return r; 1580 } 1581 1582 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1583 if (r) 1584 return r; 1585 } 1586 1587 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1588 if (r) 1589 return r; 1590 1591 /* allocate visible FB for rlc auto-loading fw */ 1592 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1593 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1594 if (r) 1595 return r; 1596 } 1597 1598 r = gfx_v12_0_gpu_early_init(adev); 1599 if (r) 1600 return r; 1601 1602 r = amdgpu_gfx_sysfs_init(adev); 1603 if (r) 1604 return r; 1605 1606 gfx_v12_0_alloc_ip_dump(adev); 1607 1608 adev->gfx.me.use_mmio_for_reset = false; 1609 adev->gfx.mec.use_mmio_for_reset = true; 1610 1611 mutex_init(&adev->gfx.mec.reset_mutex); 1612 1613 INIT_WORK(&adev->gfx.userq_priv_fault_work, gfx_v12_0_userq_priv_fault_work); 1614 1615 return 0; 1616 } 1617 1618 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1619 { 1620 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1621 &adev->gfx.pfp.pfp_fw_gpu_addr, 1622 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1623 1624 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1625 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1626 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1627 } 1628 1629 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1630 { 1631 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1632 &adev->gfx.me.me_fw_gpu_addr, 1633 (void **)&adev->gfx.me.me_fw_ptr); 1634 1635 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1636 &adev->gfx.me.me_fw_data_gpu_addr, 1637 (void **)&adev->gfx.me.me_fw_data_ptr); 1638 } 1639 1640 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1641 { 1642 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1643 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1644 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1645 } 1646 1647 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1648 { 1649 int i; 1650 struct amdgpu_device *adev = ip_block->adev; 1651 1652 cancel_work_sync(&adev->gfx.userq_priv_fault_work); 1653 1654 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1655 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1656 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1657 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1658 1659 amdgpu_gfx_mqd_sw_fini(adev, 0); 1660 1661 if (!adev->enable_mes_kiq) { 1662 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1663 amdgpu_gfx_kiq_fini(adev, 0); 1664 } 1665 1666 gfx_v12_0_pfp_fini(adev); 1667 gfx_v12_0_me_fini(adev); 1668 gfx_v12_0_rlc_fini(adev); 1669 gfx_v12_0_mec_fini(adev); 1670 1671 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1672 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1673 1674 gfx_v12_0_free_microcode(adev); 1675 1676 amdgpu_gfx_sysfs_fini(adev); 1677 1678 kfree(adev->gfx.ip_dump_core); 1679 kfree(adev->gfx.ip_dump_compute_queues); 1680 kfree(adev->gfx.ip_dump_gfx_queues); 1681 1682 return 0; 1683 } 1684 1685 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1686 u32 sh_num, u32 instance, int xcc_id) 1687 { 1688 u32 data; 1689 1690 if (instance == 0xffffffff) 1691 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1692 INSTANCE_BROADCAST_WRITES, 1); 1693 else 1694 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1695 instance); 1696 1697 if (se_num == 0xffffffff) 1698 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1699 1); 1700 else 1701 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1702 1703 if (sh_num == 0xffffffff) 1704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1705 1); 1706 else 1707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1708 1709 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1710 } 1711 1712 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1713 { 1714 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1715 1716 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1717 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1718 GRBM_CC_GC_SA_UNIT_DISABLE, 1719 SA_DISABLE); 1720 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1721 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1722 GRBM_GC_USER_SA_UNIT_DISABLE, 1723 SA_DISABLE); 1724 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1725 adev->gfx.config.max_shader_engines); 1726 1727 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1728 } 1729 1730 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1731 { 1732 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1733 u32 rb_mask; 1734 1735 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1736 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1737 CC_RB_BACKEND_DISABLE, 1738 BACKEND_DISABLE); 1739 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1740 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1741 GC_USER_RB_BACKEND_DISABLE, 1742 BACKEND_DISABLE); 1743 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1744 adev->gfx.config.max_shader_engines); 1745 1746 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1747 } 1748 1749 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1750 { 1751 u32 rb_bitmap_per_sa; 1752 u32 rb_bitmap_width_per_sa; 1753 u32 max_sa; 1754 u32 active_sa_bitmap; 1755 u32 global_active_rb_bitmap; 1756 u32 active_rb_bitmap = 0; 1757 u32 i; 1758 1759 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1760 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1761 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1762 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1763 1764 /* generate active rb bitmap according to active sa bitmap */ 1765 max_sa = adev->gfx.config.max_shader_engines * 1766 adev->gfx.config.max_sh_per_se; 1767 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1768 adev->gfx.config.max_sh_per_se; 1769 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1770 1771 for (i = 0; i < max_sa; i++) { 1772 if (active_sa_bitmap & (1 << i)) 1773 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1774 } 1775 1776 active_rb_bitmap &= global_active_rb_bitmap; 1777 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1778 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1779 } 1780 1781 #define LDS_APP_BASE 0x1 1782 #define SCRATCH_APP_BASE 0x2 1783 1784 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1785 { 1786 int i; 1787 uint32_t sh_mem_bases; 1788 uint32_t data; 1789 1790 /* 1791 * Configure apertures: 1792 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1793 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1794 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1795 */ 1796 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1797 SCRATCH_APP_BASE; 1798 1799 mutex_lock(&adev->srbm_mutex); 1800 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1801 soc24_grbm_select(adev, 0, 0, 0, i); 1802 /* CP and shaders */ 1803 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1804 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1805 1806 /* Enable trap for each kfd vmid. */ 1807 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1808 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1809 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1810 } 1811 soc24_grbm_select(adev, 0, 0, 0, 0); 1812 mutex_unlock(&adev->srbm_mutex); 1813 } 1814 1815 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1816 { 1817 /* TODO: harvest feature to be added later. */ 1818 } 1819 1820 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1821 { 1822 } 1823 1824 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1825 { 1826 u32 tmp; 1827 int i; 1828 1829 if (!amdgpu_sriov_vf(adev)) 1830 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1831 1832 gfx_v12_0_setup_rb(adev); 1833 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1834 gfx_v12_0_get_tcc_info(adev); 1835 adev->gfx.config.pa_sc_tile_steering_override = 0; 1836 1837 /* Set whether texture coordinate truncation is conformant. */ 1838 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1839 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1840 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1841 1842 /* Program DB_RING_CONTROL for multiple GFX pipes 1843 * Default power up value is 1. 1844 * Possible values: 1845 * 0 - split occlusion counters between gfx pipes 1846 * 1 - all occlusion counters to pipe 0 1847 * 2 - all occlusion counters to pipe 1 1848 */ 1849 WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, 1850 (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); 1851 1852 /* XXX SH_MEM regs */ 1853 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1854 mutex_lock(&adev->srbm_mutex); 1855 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1856 soc24_grbm_select(adev, 0, 0, 0, i); 1857 /* CP and shaders */ 1858 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1859 if (i != 0) { 1860 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1861 (adev->gmc.private_aperture_start >> 48)); 1862 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1863 (adev->gmc.shared_aperture_start >> 48)); 1864 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1865 } 1866 } 1867 soc24_grbm_select(adev, 0, 0, 0, 0); 1868 1869 mutex_unlock(&adev->srbm_mutex); 1870 1871 gfx_v12_0_init_compute_vmid(adev); 1872 } 1873 1874 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1875 int me, int pipe) 1876 { 1877 if (me != 0) 1878 return 0; 1879 1880 switch (pipe) { 1881 case 0: 1882 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1883 default: 1884 return 0; 1885 } 1886 } 1887 1888 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1889 int me, int pipe) 1890 { 1891 /* 1892 * amdgpu controls only the first MEC. That's why this function only 1893 * handles the setting of interrupts for this specific MEC. All other 1894 * pipes' interrupts are set by amdkfd. 1895 */ 1896 if (me != 1) 1897 return 0; 1898 1899 switch (pipe) { 1900 case 0: 1901 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1902 case 1: 1903 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1904 default: 1905 return 0; 1906 } 1907 } 1908 1909 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1910 bool enable) 1911 { 1912 u32 tmp, cp_int_cntl_reg; 1913 int i, j; 1914 1915 if (amdgpu_sriov_vf(adev)) 1916 return; 1917 1918 for (i = 0; i < adev->gfx.me.num_me; i++) { 1919 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1920 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1921 1922 if (cp_int_cntl_reg) { 1923 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1924 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1925 enable ? 1 : 0); 1926 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1927 enable ? 1 : 0); 1928 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1929 enable ? 1 : 0); 1930 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1931 enable ? 1 : 0); 1932 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1933 } 1934 } 1935 } 1936 } 1937 1938 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1939 { 1940 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1941 1942 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1943 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1944 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1945 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1946 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1947 1948 return 0; 1949 } 1950 1951 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1952 { 1953 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1954 1955 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1956 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1957 } 1958 1959 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1960 { 1961 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1962 udelay(50); 1963 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1964 udelay(50); 1965 } 1966 1967 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1968 bool enable) 1969 { 1970 uint32_t rlc_pg_cntl; 1971 1972 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1973 1974 if (!enable) { 1975 /* RLC_PG_CNTL[23] = 0 (default) 1976 * RLC will wait for handshake acks with SMU 1977 * GFXOFF will be enabled 1978 * RLC_PG_CNTL[23] = 1 1979 * RLC will not issue any message to SMU 1980 * hence no handshake between SMU & RLC 1981 * GFXOFF will be disabled 1982 */ 1983 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1984 } else 1985 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1986 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1987 } 1988 1989 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1990 { 1991 /* TODO: enable rlc & smu handshake until smu 1992 * and gfxoff feature works as expected */ 1993 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1994 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1995 1996 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1997 udelay(50); 1998 } 1999 2000 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 2001 { 2002 uint32_t tmp; 2003 2004 /* enable Save Restore Machine */ 2005 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2006 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2007 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2008 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2009 } 2010 2011 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 2012 { 2013 const struct rlc_firmware_header_v2_0 *hdr; 2014 const __le32 *fw_data; 2015 unsigned i, fw_size; 2016 2017 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2018 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2019 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2020 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2021 2022 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2023 RLCG_UCODE_LOADING_START_ADDRESS); 2024 2025 for (i = 0; i < fw_size; i++) 2026 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2027 le32_to_cpup(fw_data++)); 2028 2029 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2030 } 2031 2032 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2033 { 2034 const struct rlc_firmware_header_v2_2 *hdr; 2035 const __le32 *fw_data; 2036 unsigned i, fw_size; 2037 u32 tmp; 2038 2039 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2040 2041 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2042 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2043 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2044 2045 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2046 2047 for (i = 0; i < fw_size; i++) { 2048 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2049 msleep(1); 2050 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2051 le32_to_cpup(fw_data++)); 2052 } 2053 2054 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2055 2056 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2057 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2058 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2059 2060 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2061 for (i = 0; i < fw_size; i++) { 2062 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2063 msleep(1); 2064 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2065 le32_to_cpup(fw_data++)); 2066 } 2067 2068 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2069 2070 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2071 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2072 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2073 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2074 } 2075 2076 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2077 { 2078 const struct rlc_firmware_header_v2_0 *hdr; 2079 uint16_t version_major; 2080 uint16_t version_minor; 2081 2082 if (!adev->gfx.rlc_fw) 2083 return -EINVAL; 2084 2085 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2086 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2087 2088 version_major = le16_to_cpu(hdr->header.header_version_major); 2089 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2090 2091 if (version_major == 2) { 2092 gfx_v12_0_load_rlcg_microcode(adev); 2093 if (amdgpu_dpm == 1) { 2094 if (version_minor >= 2) 2095 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2096 } 2097 2098 return 0; 2099 } 2100 2101 return -EINVAL; 2102 } 2103 2104 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2105 { 2106 int r; 2107 2108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2109 gfx_v12_0_init_csb(adev); 2110 2111 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2112 gfx_v12_0_rlc_enable_srm(adev); 2113 } else { 2114 if (amdgpu_sriov_vf(adev)) { 2115 gfx_v12_0_init_csb(adev); 2116 return 0; 2117 } 2118 2119 adev->gfx.rlc.funcs->stop(adev); 2120 2121 /* disable CG */ 2122 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2123 2124 /* disable PG */ 2125 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2126 2127 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2128 /* legacy rlc firmware loading */ 2129 r = gfx_v12_0_rlc_load_microcode(adev); 2130 if (r) 2131 return r; 2132 } 2133 2134 gfx_v12_0_init_csb(adev); 2135 2136 adev->gfx.rlc.funcs->start(adev); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2143 { 2144 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2145 const struct gfx_firmware_header_v2_0 *me_hdr; 2146 const struct gfx_firmware_header_v2_0 *mec_hdr; 2147 uint32_t pipe_id, tmp; 2148 2149 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2150 adev->gfx.mec_fw->data; 2151 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2152 adev->gfx.me_fw->data; 2153 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2154 adev->gfx.pfp_fw->data; 2155 2156 /* config pfp program start addr */ 2157 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2158 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2159 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2160 (pfp_hdr->ucode_start_addr_hi << 30) | 2161 (pfp_hdr->ucode_start_addr_lo >> 2)); 2162 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2163 pfp_hdr->ucode_start_addr_hi >> 2); 2164 } 2165 soc24_grbm_select(adev, 0, 0, 0, 0); 2166 2167 /* reset pfp pipe */ 2168 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2169 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2171 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2172 2173 /* clear pfp pipe reset */ 2174 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2175 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2176 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2177 2178 /* config me program start addr */ 2179 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2180 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2181 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2182 (me_hdr->ucode_start_addr_hi << 30) | 2183 (me_hdr->ucode_start_addr_lo >> 2)); 2184 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2185 me_hdr->ucode_start_addr_hi>>2); 2186 } 2187 soc24_grbm_select(adev, 0, 0, 0, 0); 2188 2189 /* reset me pipe */ 2190 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2191 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2192 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2193 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2194 2195 /* clear me pipe reset */ 2196 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2197 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2198 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2199 2200 /* config mec program start addr */ 2201 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2202 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2203 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2204 mec_hdr->ucode_start_addr_lo >> 2 | 2205 mec_hdr->ucode_start_addr_hi << 30); 2206 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2207 mec_hdr->ucode_start_addr_hi >> 2); 2208 } 2209 soc24_grbm_select(adev, 0, 0, 0, 0); 2210 2211 /* reset mec pipe */ 2212 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2213 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2214 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2215 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2216 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2217 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2218 2219 /* clear mec pipe reset */ 2220 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2221 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2222 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2223 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2224 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2225 } 2226 2227 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2228 { 2229 const struct gfx_firmware_header_v2_0 *cp_hdr; 2230 unsigned pipe_id, tmp; 2231 2232 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2233 adev->gfx.pfp_fw->data; 2234 mutex_lock(&adev->srbm_mutex); 2235 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2236 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2237 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2238 (cp_hdr->ucode_start_addr_hi << 30) | 2239 (cp_hdr->ucode_start_addr_lo >> 2)); 2240 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2241 cp_hdr->ucode_start_addr_hi>>2); 2242 2243 /* 2244 * Program CP_ME_CNTL to reset given PIPE to take 2245 * effect of CP_PFP_PRGRM_CNTR_START. 2246 */ 2247 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2248 if (pipe_id == 0) 2249 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2250 PFP_PIPE0_RESET, 1); 2251 else 2252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2253 PFP_PIPE1_RESET, 1); 2254 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2255 2256 /* Clear pfp pipe0 reset bit. */ 2257 if (pipe_id == 0) 2258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2259 PFP_PIPE0_RESET, 0); 2260 else 2261 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2262 PFP_PIPE1_RESET, 0); 2263 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2264 } 2265 soc24_grbm_select(adev, 0, 0, 0, 0); 2266 mutex_unlock(&adev->srbm_mutex); 2267 } 2268 2269 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2270 { 2271 const struct gfx_firmware_header_v2_0 *cp_hdr; 2272 unsigned pipe_id, tmp; 2273 2274 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2275 adev->gfx.me_fw->data; 2276 mutex_lock(&adev->srbm_mutex); 2277 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2278 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2279 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2280 (cp_hdr->ucode_start_addr_hi << 30) | 2281 (cp_hdr->ucode_start_addr_lo >> 2) ); 2282 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2283 cp_hdr->ucode_start_addr_hi>>2); 2284 2285 /* 2286 * Program CP_ME_CNTL to reset given PIPE to take 2287 * effect of CP_ME_PRGRM_CNTR_START. 2288 */ 2289 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2290 if (pipe_id == 0) 2291 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2292 ME_PIPE0_RESET, 1); 2293 else 2294 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2295 ME_PIPE1_RESET, 1); 2296 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2297 2298 /* Clear pfp pipe0 reset bit. */ 2299 if (pipe_id == 0) 2300 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2301 ME_PIPE0_RESET, 0); 2302 else 2303 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2304 ME_PIPE1_RESET, 0); 2305 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2306 } 2307 soc24_grbm_select(adev, 0, 0, 0, 0); 2308 mutex_unlock(&adev->srbm_mutex); 2309 } 2310 2311 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2312 { 2313 const struct gfx_firmware_header_v2_0 *cp_hdr; 2314 unsigned pipe_id; 2315 2316 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2317 adev->gfx.mec_fw->data; 2318 mutex_lock(&adev->srbm_mutex); 2319 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2320 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2321 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2322 cp_hdr->ucode_start_addr_lo >> 2 | 2323 cp_hdr->ucode_start_addr_hi << 30); 2324 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2325 cp_hdr->ucode_start_addr_hi >> 2); 2326 } 2327 soc24_grbm_select(adev, 0, 0, 0, 0); 2328 mutex_unlock(&adev->srbm_mutex); 2329 } 2330 2331 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2332 { 2333 uint32_t cp_status; 2334 uint32_t bootload_status; 2335 int i; 2336 2337 for (i = 0; i < adev->usec_timeout; i++) { 2338 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2339 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2340 2341 if ((cp_status == 0) && 2342 (REG_GET_FIELD(bootload_status, 2343 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2344 break; 2345 } 2346 udelay(1); 2347 if (amdgpu_emu_mode) 2348 msleep(10); 2349 } 2350 2351 if (i >= adev->usec_timeout) { 2352 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2353 return -ETIMEDOUT; 2354 } 2355 2356 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2357 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2358 gfx_v12_0_set_me_ucode_start_addr(adev); 2359 gfx_v12_0_set_mec_ucode_start_addr(adev); 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2366 { 2367 int i; 2368 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2369 2370 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2371 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2372 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2373 2374 for (i = 0; i < adev->usec_timeout; i++) { 2375 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2376 break; 2377 udelay(1); 2378 } 2379 2380 if (i >= adev->usec_timeout) 2381 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2382 2383 return 0; 2384 } 2385 2386 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2387 { 2388 int r; 2389 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2390 const __le32 *fw_ucode, *fw_data; 2391 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2392 uint32_t tmp; 2393 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2394 2395 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2396 adev->gfx.pfp_fw->data; 2397 2398 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2399 2400 /* instruction */ 2401 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2402 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2403 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2404 /* data */ 2405 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2406 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2407 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2408 2409 /* 64kb align */ 2410 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2411 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2412 &adev->gfx.pfp.pfp_fw_obj, 2413 &adev->gfx.pfp.pfp_fw_gpu_addr, 2414 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2415 if (r) { 2416 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2417 gfx_v12_0_pfp_fini(adev); 2418 return r; 2419 } 2420 2421 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2422 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2423 &adev->gfx.pfp.pfp_fw_data_obj, 2424 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2425 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2426 if (r) { 2427 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2428 gfx_v12_0_pfp_fini(adev); 2429 return r; 2430 } 2431 2432 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2433 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2434 2435 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2436 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2437 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2438 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2439 2440 if (amdgpu_emu_mode == 1) 2441 amdgpu_device_flush_hdp(adev, NULL); 2442 2443 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2444 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2445 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2446 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2447 2448 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2449 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2450 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2451 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2452 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2453 2454 /* 2455 * Programming any of the CP_PFP_IC_BASE registers 2456 * forces invalidation of the ME L1 I$. Wait for the 2457 * invalidation complete 2458 */ 2459 for (i = 0; i < usec_timeout; i++) { 2460 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2461 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2462 INVALIDATE_CACHE_COMPLETE)) 2463 break; 2464 udelay(1); 2465 } 2466 2467 if (i >= usec_timeout) { 2468 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2469 return -EINVAL; 2470 } 2471 2472 /* Prime the L1 instruction caches */ 2473 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2474 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2475 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2476 /* Waiting for cache primed*/ 2477 for (i = 0; i < usec_timeout; i++) { 2478 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2479 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2480 ICACHE_PRIMED)) 2481 break; 2482 udelay(1); 2483 } 2484 2485 if (i >= usec_timeout) { 2486 dev_err(adev->dev, "failed to prime instruction cache\n"); 2487 return -EINVAL; 2488 } 2489 2490 mutex_lock(&adev->srbm_mutex); 2491 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2492 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2493 2494 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2495 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2496 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2497 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2498 } 2499 soc24_grbm_select(adev, 0, 0, 0, 0); 2500 mutex_unlock(&adev->srbm_mutex); 2501 2502 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2503 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2504 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2505 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2506 2507 /* Invalidate the data caches */ 2508 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2509 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2510 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2511 2512 for (i = 0; i < usec_timeout; i++) { 2513 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2514 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2515 INVALIDATE_DCACHE_COMPLETE)) 2516 break; 2517 udelay(1); 2518 } 2519 2520 if (i >= usec_timeout) { 2521 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2522 return -EINVAL; 2523 } 2524 2525 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2526 2527 return 0; 2528 } 2529 2530 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2531 { 2532 int r; 2533 const struct gfx_firmware_header_v2_0 *me_hdr; 2534 const __le32 *fw_ucode, *fw_data; 2535 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2536 uint32_t tmp; 2537 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2538 2539 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2540 adev->gfx.me_fw->data; 2541 2542 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2543 2544 /* instruction */ 2545 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2546 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2547 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2548 /* data */ 2549 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2550 le32_to_cpu(me_hdr->data_offset_bytes)); 2551 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2552 2553 /* 64kb align*/ 2554 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2555 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2556 &adev->gfx.me.me_fw_obj, 2557 &adev->gfx.me.me_fw_gpu_addr, 2558 (void **)&adev->gfx.me.me_fw_ptr); 2559 if (r) { 2560 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2561 gfx_v12_0_me_fini(adev); 2562 return r; 2563 } 2564 2565 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2566 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2567 &adev->gfx.me.me_fw_data_obj, 2568 &adev->gfx.me.me_fw_data_gpu_addr, 2569 (void **)&adev->gfx.me.me_fw_data_ptr); 2570 if (r) { 2571 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2572 gfx_v12_0_me_fini(adev); 2573 return r; 2574 } 2575 2576 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2577 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2578 2579 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2580 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2581 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2582 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2583 2584 if (amdgpu_emu_mode == 1) 2585 amdgpu_device_flush_hdp(adev, NULL); 2586 2587 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2588 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2589 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2590 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2591 2592 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2593 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2594 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2595 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2596 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2597 2598 /* 2599 * Programming any of the CP_ME_IC_BASE registers 2600 * forces invalidation of the ME L1 I$. Wait for the 2601 * invalidation complete 2602 */ 2603 for (i = 0; i < usec_timeout; i++) { 2604 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2605 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2606 INVALIDATE_CACHE_COMPLETE)) 2607 break; 2608 udelay(1); 2609 } 2610 2611 if (i >= usec_timeout) { 2612 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2613 return -EINVAL; 2614 } 2615 2616 /* Prime the instruction caches */ 2617 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2618 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2619 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2620 2621 /* Waiting for instruction cache primed*/ 2622 for (i = 0; i < usec_timeout; i++) { 2623 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2624 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2625 ICACHE_PRIMED)) 2626 break; 2627 udelay(1); 2628 } 2629 2630 if (i >= usec_timeout) { 2631 dev_err(adev->dev, "failed to prime instruction cache\n"); 2632 return -EINVAL; 2633 } 2634 2635 mutex_lock(&adev->srbm_mutex); 2636 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2637 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2638 2639 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2640 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2641 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2642 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2643 } 2644 soc24_grbm_select(adev, 0, 0, 0, 0); 2645 mutex_unlock(&adev->srbm_mutex); 2646 2647 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2648 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2649 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2650 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2651 2652 /* Invalidate the data caches */ 2653 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2654 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2655 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2656 2657 for (i = 0; i < usec_timeout; i++) { 2658 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2659 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2660 INVALIDATE_DCACHE_COMPLETE)) 2661 break; 2662 udelay(1); 2663 } 2664 2665 if (i >= usec_timeout) { 2666 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2667 return -EINVAL; 2668 } 2669 2670 gfx_v12_0_set_me_ucode_start_addr(adev); 2671 2672 return 0; 2673 } 2674 2675 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2676 { 2677 int r; 2678 2679 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2680 return -EINVAL; 2681 2682 gfx_v12_0_cp_gfx_enable(adev, false); 2683 2684 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2685 if (r) { 2686 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2687 return r; 2688 } 2689 2690 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2691 if (r) { 2692 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2693 return r; 2694 } 2695 2696 return 0; 2697 } 2698 2699 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2700 { 2701 /* init the CP */ 2702 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2703 adev->gfx.config.max_hw_contexts - 1); 2704 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2705 2706 if (!amdgpu_async_gfx_ring) 2707 gfx_v12_0_cp_gfx_enable(adev, true); 2708 2709 return 0; 2710 } 2711 2712 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2713 CP_PIPE_ID pipe) 2714 { 2715 u32 tmp; 2716 2717 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2718 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2719 2720 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2721 } 2722 2723 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2724 struct amdgpu_ring *ring) 2725 { 2726 u32 tmp; 2727 2728 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2729 if (ring->use_doorbell) { 2730 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2731 DOORBELL_OFFSET, ring->doorbell_index); 2732 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2733 DOORBELL_EN, 1); 2734 } else { 2735 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2736 DOORBELL_EN, 0); 2737 } 2738 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2739 2740 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2741 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2742 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2743 2744 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2745 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2746 } 2747 2748 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2749 { 2750 struct amdgpu_ring *ring; 2751 u32 tmp; 2752 u32 rb_bufsz; 2753 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2754 2755 /* Set the write pointer delay */ 2756 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2757 2758 /* set the RB to use vmid 0 */ 2759 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2760 2761 /* Init gfx ring 0 for pipe 0 */ 2762 mutex_lock(&adev->srbm_mutex); 2763 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2764 2765 /* Set ring buffer size */ 2766 ring = &adev->gfx.gfx_ring[0]; 2767 rb_bufsz = order_base_2(ring->ring_size / 8); 2768 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2769 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2770 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, KMD_QUEUE, 1); 2771 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2772 2773 /* Initialize the ring buffer's write pointers */ 2774 ring->wptr = 0; 2775 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2776 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2777 2778 /* set the wb address whether it's enabled or not */ 2779 rptr_addr = ring->rptr_gpu_addr; 2780 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2781 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2782 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2783 2784 wptr_gpu_addr = ring->wptr_gpu_addr; 2785 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2786 lower_32_bits(wptr_gpu_addr)); 2787 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2788 upper_32_bits(wptr_gpu_addr)); 2789 2790 mdelay(1); 2791 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2792 2793 rb_addr = ring->gpu_addr >> 8; 2794 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2795 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2796 2797 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2798 2799 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2800 mutex_unlock(&adev->srbm_mutex); 2801 2802 /* Switch to pipe 0 */ 2803 mutex_lock(&adev->srbm_mutex); 2804 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2805 mutex_unlock(&adev->srbm_mutex); 2806 2807 /* start the ring */ 2808 gfx_v12_0_cp_gfx_start(adev); 2809 return 0; 2810 } 2811 2812 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2813 { 2814 u32 data; 2815 2816 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2817 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2818 enable ? 0 : 1); 2819 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2820 enable ? 0 : 1); 2821 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2822 enable ? 0 : 1); 2823 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2824 enable ? 0 : 1); 2825 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2826 enable ? 0 : 1); 2827 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2828 enable ? 1 : 0); 2829 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2830 enable ? 1 : 0); 2831 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2832 enable ? 1 : 0); 2833 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2834 enable ? 1 : 0); 2835 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2836 enable ? 0 : 1); 2837 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2838 2839 adev->gfx.kiq[0].ring.sched.ready = enable; 2840 2841 udelay(50); 2842 } 2843 2844 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2845 { 2846 const struct gfx_firmware_header_v2_0 *mec_hdr; 2847 const __le32 *fw_ucode, *fw_data; 2848 u32 tmp, fw_ucode_size, fw_data_size; 2849 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2850 u32 *fw_ucode_ptr, *fw_data_ptr; 2851 int r; 2852 2853 if (!adev->gfx.mec_fw) 2854 return -EINVAL; 2855 2856 gfx_v12_0_cp_compute_enable(adev, false); 2857 2858 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2859 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2860 2861 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2862 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2863 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2864 2865 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2866 le32_to_cpu(mec_hdr->data_offset_bytes)); 2867 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2868 2869 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2870 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2871 &adev->gfx.mec.mec_fw_obj, 2872 &adev->gfx.mec.mec_fw_gpu_addr, 2873 (void **)&fw_ucode_ptr); 2874 if (r) { 2875 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2876 gfx_v12_0_mec_fini(adev); 2877 return r; 2878 } 2879 2880 r = amdgpu_bo_create_reserved(adev, 2881 ALIGN(fw_data_size, 64 * 1024) * 2882 adev->gfx.mec.num_pipe_per_mec, 2883 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2884 &adev->gfx.mec.mec_fw_data_obj, 2885 &adev->gfx.mec.mec_fw_data_gpu_addr, 2886 (void **)&fw_data_ptr); 2887 if (r) { 2888 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2889 gfx_v12_0_mec_fini(adev); 2890 return r; 2891 } 2892 2893 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2894 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2895 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2896 } 2897 2898 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2899 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2900 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2901 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2902 2903 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2904 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2905 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2906 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2907 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2908 2909 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2910 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2911 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2912 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2913 2914 mutex_lock(&adev->srbm_mutex); 2915 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2916 soc24_grbm_select(adev, 1, i, 0, 0); 2917 2918 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2919 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2920 i * ALIGN(fw_data_size, 64 * 1024))); 2921 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2922 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2923 i * ALIGN(fw_data_size, 64 * 1024))); 2924 2925 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2926 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2927 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2928 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2929 } 2930 mutex_unlock(&adev->srbm_mutex); 2931 soc24_grbm_select(adev, 0, 0, 0, 0); 2932 2933 /* Trigger an invalidation of the L1 instruction caches */ 2934 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2935 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2936 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2937 2938 /* Wait for invalidation complete */ 2939 for (i = 0; i < usec_timeout; i++) { 2940 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2941 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2942 INVALIDATE_DCACHE_COMPLETE)) 2943 break; 2944 udelay(1); 2945 } 2946 2947 if (i >= usec_timeout) { 2948 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2949 return -EINVAL; 2950 } 2951 2952 /* Trigger an invalidation of the L1 instruction caches */ 2953 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2954 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2955 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2956 2957 /* Wait for invalidation complete */ 2958 for (i = 0; i < usec_timeout; i++) { 2959 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2960 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2961 INVALIDATE_CACHE_COMPLETE)) 2962 break; 2963 udelay(1); 2964 } 2965 2966 if (i >= usec_timeout) { 2967 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2968 return -EINVAL; 2969 } 2970 2971 gfx_v12_0_set_mec_ucode_start_addr(adev); 2972 2973 return 0; 2974 } 2975 2976 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2977 { 2978 uint32_t tmp; 2979 struct amdgpu_device *adev = ring->adev; 2980 2981 /* tell RLC which is KIQ queue */ 2982 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2983 tmp &= 0xffffff00; 2984 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2985 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2986 } 2987 2988 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2989 { 2990 /* set graphics engine doorbell range */ 2991 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2992 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2993 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2994 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2995 2996 /* set compute engine doorbell range */ 2997 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2998 (adev->doorbell_index.kiq * 2) << 2); 2999 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3000 (adev->doorbell_index.userqueue_end * 2) << 2); 3001 } 3002 3003 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3004 struct amdgpu_mqd_prop *prop) 3005 { 3006 struct v12_gfx_mqd *mqd = m; 3007 uint64_t hqd_gpu_addr, wb_gpu_addr; 3008 uint32_t tmp; 3009 uint32_t rb_bufsz; 3010 3011 /* set up gfx hqd wptr */ 3012 mqd->cp_gfx_hqd_wptr = 0; 3013 mqd->cp_gfx_hqd_wptr_hi = 0; 3014 3015 /* set the pointer to the MQD */ 3016 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3017 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3018 3019 /* set up mqd control */ 3020 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 3021 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3022 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3023 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3024 mqd->cp_gfx_mqd_control = tmp; 3025 3026 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3027 tmp = regCP_GFX_HQD_VMID_DEFAULT; 3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3029 mqd->cp_gfx_hqd_vmid = 0; 3030 3031 /* set up default queue priority level 3032 * 0x0 = low priority, 0x1 = high priority */ 3033 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 3034 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3035 mqd->cp_gfx_hqd_queue_priority = tmp; 3036 3037 /* set up time quantum */ 3038 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3039 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3040 mqd->cp_gfx_hqd_quantum = tmp; 3041 3042 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3043 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3044 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3045 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3046 3047 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3048 wb_gpu_addr = prop->rptr_gpu_addr; 3049 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3050 mqd->cp_gfx_hqd_rptr_addr_hi = 3051 upper_32_bits(wb_gpu_addr) & 0xffff; 3052 3053 /* set up rb_wptr_poll addr */ 3054 wb_gpu_addr = prop->wptr_gpu_addr; 3055 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3056 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3057 3058 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3059 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3060 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3061 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3062 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3063 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, KMD_QUEUE, prop->kernel_queue); 3064 #ifdef __BIG_ENDIAN 3065 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3066 #endif 3067 if (prop->tmz_queue) 3068 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3069 if (!prop->kernel_queue) 3070 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3071 mqd->cp_gfx_hqd_cntl = tmp; 3072 3073 /* set up cp_doorbell_control */ 3074 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3075 if (prop->use_doorbell) { 3076 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3077 DOORBELL_OFFSET, prop->doorbell_index); 3078 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3079 DOORBELL_EN, 1); 3080 } else 3081 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3082 DOORBELL_EN, 0); 3083 mqd->cp_rb_doorbell_control = tmp; 3084 3085 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3086 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3087 3088 /* active the queue */ 3089 mqd->cp_gfx_hqd_active = 1; 3090 3091 /* set gfx UQ items */ 3092 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3093 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3094 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3095 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3096 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3097 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3098 3099 return 0; 3100 } 3101 3102 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring) 3103 { 3104 struct amdgpu_device *adev = ring->adev; 3105 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3106 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3107 3108 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3109 memset((void *)mqd, 0, sizeof(*mqd)); 3110 mutex_lock(&adev->srbm_mutex); 3111 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3112 amdgpu_ring_init_mqd(ring); 3113 soc24_grbm_select(adev, 0, 0, 0, 0); 3114 mutex_unlock(&adev->srbm_mutex); 3115 if (adev->gfx.me.mqd_backup[mqd_idx]) 3116 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3117 } else { 3118 /* restore mqd with the backup copy */ 3119 if (adev->gfx.me.mqd_backup[mqd_idx]) 3120 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3121 /* reset the ring */ 3122 ring->wptr = 0; 3123 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3124 amdgpu_ring_clear_ring(ring); 3125 } 3126 3127 return 0; 3128 } 3129 3130 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3131 { 3132 int i, r; 3133 3134 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3135 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i]); 3136 if (r) 3137 return r; 3138 } 3139 3140 r = amdgpu_gfx_enable_kgq(adev, 0); 3141 if (r) 3142 return r; 3143 3144 return gfx_v12_0_cp_gfx_start(adev); 3145 } 3146 3147 static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 3148 struct v12_compute_mqd *mqd, 3149 struct amdgpu_mqd_prop *prop) 3150 { 3151 uint32_t se_mask[8] = {0}; 3152 uint32_t wa_mask; 3153 bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 3154 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 3155 3156 if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 3157 return; 3158 3159 if (has_wa_flag) { 3160 wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 3161 0xffff : 0xffffffff; 3162 mqd->compute_static_thread_mgmt_se0 = wa_mask; 3163 mqd->compute_static_thread_mgmt_se1 = wa_mask; 3164 mqd->compute_static_thread_mgmt_se2 = wa_mask; 3165 mqd->compute_static_thread_mgmt_se3 = wa_mask; 3166 return; 3167 } 3168 3169 amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 3170 prop->cu_mask_count, se_mask); 3171 3172 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 3173 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 3174 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 3175 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 3176 } 3177 3178 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3179 struct amdgpu_mqd_prop *prop) 3180 { 3181 struct v12_compute_mqd *mqd = m; 3182 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3183 uint32_t tmp; 3184 3185 mqd->header = 0xC0310800; 3186 mqd->compute_pipelinestat_enable = 0x00000001; 3187 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3188 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3189 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3190 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3191 mqd->compute_misc_reserved = 0x00000007; 3192 3193 eop_base_addr = prop->eop_gpu_addr >> 8; 3194 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3195 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3196 3197 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3198 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3199 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3200 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3201 3202 mqd->cp_hqd_eop_control = tmp; 3203 3204 /* enable doorbell? */ 3205 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3206 3207 if (prop->use_doorbell) { 3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3209 DOORBELL_OFFSET, prop->doorbell_index); 3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3211 DOORBELL_EN, 1); 3212 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3213 DOORBELL_SOURCE, 0); 3214 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3215 DOORBELL_HIT, 0); 3216 } else { 3217 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3218 DOORBELL_EN, 0); 3219 } 3220 3221 mqd->cp_hqd_pq_doorbell_control = tmp; 3222 3223 /* disable the queue if it's active */ 3224 mqd->cp_hqd_dequeue_request = 0; 3225 mqd->cp_hqd_pq_rptr = 0; 3226 mqd->cp_hqd_pq_wptr_lo = 0; 3227 mqd->cp_hqd_pq_wptr_hi = 0; 3228 3229 /* set the pointer to the MQD */ 3230 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3231 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3232 3233 /* set MQD vmid to 0 */ 3234 tmp = regCP_MQD_CONTROL_DEFAULT; 3235 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3236 mqd->cp_mqd_control = tmp; 3237 3238 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3239 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3240 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3241 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3242 3243 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3244 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3245 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3246 (order_base_2(prop->queue_size / 4) - 1)); 3247 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3248 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3250 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3251 if (prop->kernel_queue) { 3252 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3254 } 3255 if (prop->tmz_queue) 3256 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3257 mqd->cp_hqd_pq_control = tmp; 3258 3259 /* set the wb address whether it's enabled or not */ 3260 wb_gpu_addr = prop->rptr_gpu_addr; 3261 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3262 mqd->cp_hqd_pq_rptr_report_addr_hi = 3263 upper_32_bits(wb_gpu_addr) & 0xffff; 3264 3265 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3266 wb_gpu_addr = prop->wptr_gpu_addr; 3267 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3268 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3269 3270 tmp = 0; 3271 /* enable the doorbell if requested */ 3272 if (prop->use_doorbell) { 3273 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3274 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3275 DOORBELL_OFFSET, prop->doorbell_index); 3276 3277 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3278 DOORBELL_EN, 1); 3279 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3280 DOORBELL_SOURCE, 0); 3281 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3282 DOORBELL_HIT, 0); 3283 } 3284 3285 mqd->cp_hqd_pq_doorbell_control = tmp; 3286 3287 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3288 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3289 3290 /* set the vmid for the queue */ 3291 mqd->cp_hqd_vmid = 0; 3292 3293 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3294 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3295 mqd->cp_hqd_persistent_state = tmp; 3296 3297 /* set MIN_IB_AVAIL_SIZE */ 3298 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3299 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3300 mqd->cp_hqd_ib_control = tmp; 3301 3302 /* set static priority for a compute queue/ring */ 3303 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3304 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3305 3306 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 3307 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 3308 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 3309 mqd->cp_hqd_quantum = tmp; 3310 3311 mqd->cp_hqd_active = prop->hqd_active; 3312 3313 /* set UQ fenceaddress */ 3314 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3315 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3316 /* set CU mask */ 3317 gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); 3318 3319 return 0; 3320 } 3321 3322 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3323 { 3324 struct amdgpu_device *adev = ring->adev; 3325 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3326 int j; 3327 3328 /* inactivate the queue */ 3329 if (amdgpu_sriov_vf(adev)) 3330 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3331 3332 /* disable wptr polling */ 3333 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3334 3335 /* write the EOP addr */ 3336 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3337 mqd->cp_hqd_eop_base_addr_lo); 3338 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3339 mqd->cp_hqd_eop_base_addr_hi); 3340 3341 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3342 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3343 mqd->cp_hqd_eop_control); 3344 3345 /* enable doorbell? */ 3346 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3347 mqd->cp_hqd_pq_doorbell_control); 3348 3349 /* disable the queue if it's active */ 3350 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3351 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3352 for (j = 0; j < adev->usec_timeout; j++) { 3353 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3354 break; 3355 udelay(1); 3356 } 3357 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3358 mqd->cp_hqd_dequeue_request); 3359 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3360 mqd->cp_hqd_pq_rptr); 3361 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3362 mqd->cp_hqd_pq_wptr_lo); 3363 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3364 mqd->cp_hqd_pq_wptr_hi); 3365 } 3366 3367 /* set the pointer to the MQD */ 3368 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3369 mqd->cp_mqd_base_addr_lo); 3370 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3371 mqd->cp_mqd_base_addr_hi); 3372 3373 /* set MQD vmid to 0 */ 3374 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3375 mqd->cp_mqd_control); 3376 3377 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3378 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3379 mqd->cp_hqd_pq_base_lo); 3380 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3381 mqd->cp_hqd_pq_base_hi); 3382 3383 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3384 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3385 mqd->cp_hqd_pq_control); 3386 3387 /* set the wb address whether it's enabled or not */ 3388 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3389 mqd->cp_hqd_pq_rptr_report_addr_lo); 3390 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3391 mqd->cp_hqd_pq_rptr_report_addr_hi); 3392 3393 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3394 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3395 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3396 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3397 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3398 3399 /* enable the doorbell if requested */ 3400 if (ring->use_doorbell) { 3401 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3402 (adev->doorbell_index.kiq * 2) << 2); 3403 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3404 (adev->doorbell_index.userqueue_end * 2) << 2); 3405 } 3406 3407 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3408 mqd->cp_hqd_pq_doorbell_control); 3409 3410 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3411 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3412 mqd->cp_hqd_pq_wptr_lo); 3413 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3414 mqd->cp_hqd_pq_wptr_hi); 3415 3416 /* set the vmid for the queue */ 3417 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3418 3419 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3420 mqd->cp_hqd_persistent_state); 3421 3422 /* activate the queue */ 3423 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3424 mqd->cp_hqd_active); 3425 3426 if (ring->use_doorbell) 3427 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3428 3429 return 0; 3430 } 3431 3432 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3433 { 3434 struct amdgpu_device *adev = ring->adev; 3435 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3436 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3437 3438 gfx_v12_0_kiq_setting(ring); 3439 3440 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3441 /* reset MQD to a clean status */ 3442 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3443 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3444 3445 /* reset ring buffer */ 3446 ring->wptr = 0; 3447 amdgpu_ring_clear_ring(ring); 3448 3449 mutex_lock(&adev->srbm_mutex); 3450 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3451 gfx_v12_0_kiq_init_register(ring); 3452 soc24_grbm_select(adev, 0, 0, 0, 0); 3453 mutex_unlock(&adev->srbm_mutex); 3454 } else { 3455 memset((void *)mqd, 0, sizeof(*mqd)); 3456 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3457 amdgpu_ring_clear_ring(ring); 3458 mutex_lock(&adev->srbm_mutex); 3459 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3460 amdgpu_ring_init_mqd(ring); 3461 gfx_v12_0_kiq_init_register(ring); 3462 soc24_grbm_select(adev, 0, 0, 0, 0); 3463 mutex_unlock(&adev->srbm_mutex); 3464 3465 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3466 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3467 } 3468 3469 return 0; 3470 } 3471 3472 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring) 3473 { 3474 struct amdgpu_device *adev = ring->adev; 3475 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3476 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3477 3478 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3479 memset((void *)mqd, 0, sizeof(*mqd)); 3480 mutex_lock(&adev->srbm_mutex); 3481 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3482 amdgpu_ring_init_mqd(ring); 3483 soc24_grbm_select(adev, 0, 0, 0, 0); 3484 mutex_unlock(&adev->srbm_mutex); 3485 3486 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3487 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3488 } else { 3489 /* restore MQD to a clean status */ 3490 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3491 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3492 /* reset ring buffer */ 3493 ring->wptr = 0; 3494 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3495 amdgpu_ring_clear_ring(ring); 3496 } 3497 3498 return 0; 3499 } 3500 3501 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3502 { 3503 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3504 adev->gfx.kiq[0].ring.sched.ready = true; 3505 return 0; 3506 } 3507 3508 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3509 { 3510 int i, r; 3511 3512 if (!amdgpu_async_gfx_ring) 3513 gfx_v12_0_cp_compute_enable(adev, true); 3514 3515 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3516 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i]); 3517 if (r) 3518 return r; 3519 } 3520 3521 return amdgpu_gfx_enable_kcq(adev, 0); 3522 } 3523 3524 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3525 { 3526 int r, i; 3527 struct amdgpu_ring *ring; 3528 3529 if (!(adev->flags & AMD_IS_APU)) 3530 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3531 3532 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3533 /* legacy firmware loading */ 3534 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3535 if (r) 3536 return r; 3537 3538 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3539 if (r) 3540 return r; 3541 } 3542 3543 gfx_v12_0_cp_set_doorbell_range(adev); 3544 3545 if (amdgpu_async_gfx_ring) { 3546 gfx_v12_0_cp_compute_enable(adev, true); 3547 gfx_v12_0_cp_gfx_enable(adev, true); 3548 } 3549 3550 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) { 3551 r = amdgpu_mes_kiq_hw_init(adev, 0); 3552 /* 3553 * With MES, GFX KIQ ring is owned by the MES and is never 3554 * initialized/used directly by the driver, so it must 3555 * not be left flagged as ready. mes_v12_0_hw_init() clears 3556 * but clear here if MES init fails 3557 */ 3558 if (r) 3559 adev->gfx.kiq[0].ring.sched.ready = false; 3560 } else { 3561 r = gfx_v12_0_kiq_resume(adev); 3562 } 3563 if (r) 3564 return r; 3565 3566 r = gfx_v12_0_kcq_resume(adev); 3567 if (r) 3568 return r; 3569 3570 if (!amdgpu_async_gfx_ring) { 3571 r = gfx_v12_0_cp_gfx_resume(adev); 3572 if (r) 3573 return r; 3574 } else { 3575 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3576 if (r) 3577 return r; 3578 } 3579 3580 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3581 ring = &adev->gfx.gfx_ring[i]; 3582 r = amdgpu_ring_test_helper(ring); 3583 if (r) 3584 return r; 3585 } 3586 3587 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3588 ring = &adev->gfx.compute_ring[i]; 3589 r = amdgpu_ring_test_helper(ring); 3590 if (r) 3591 return r; 3592 } 3593 3594 return 0; 3595 } 3596 3597 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3598 { 3599 gfx_v12_0_cp_gfx_enable(adev, enable); 3600 gfx_v12_0_cp_compute_enable(adev, enable); 3601 } 3602 3603 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3604 { 3605 int r; 3606 bool value; 3607 3608 r = adev->gfxhub.funcs->gart_enable(adev); 3609 if (r) 3610 return r; 3611 3612 amdgpu_device_flush_hdp(adev, NULL); 3613 3614 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3615 3616 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3617 /* TODO investigate why this and the hdp flush above is needed, 3618 * are we missing a flush somewhere else? */ 3619 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3620 3621 return 0; 3622 } 3623 3624 static int get_gb_addr_config(struct amdgpu_device *adev) 3625 { 3626 u32 gb_addr_config; 3627 3628 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3629 if (gb_addr_config == 0) 3630 return -EINVAL; 3631 3632 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3633 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3634 3635 adev->gfx.config.gb_addr_config = gb_addr_config; 3636 3637 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3638 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3639 GB_ADDR_CONFIG, NUM_PIPES); 3640 3641 adev->gfx.config.max_tile_pipes = 3642 adev->gfx.config.gb_addr_config_fields.num_pipes; 3643 3644 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3645 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3646 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3647 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3648 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3649 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3650 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3651 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3652 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3653 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3654 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3655 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3656 3657 return 0; 3658 } 3659 3660 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3661 { 3662 uint32_t data; 3663 3664 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3665 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3666 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3667 3668 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3669 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3670 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3671 } 3672 3673 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3674 { 3675 if (amdgpu_sriov_vf(adev)) 3676 return; 3677 3678 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3679 case IP_VERSION(12, 0, 0): 3680 case IP_VERSION(12, 0, 1): 3681 soc15_program_register_sequence(adev, 3682 golden_settings_gc_12_0, 3683 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3684 3685 if (adev->rev_id == 0) 3686 soc15_program_register_sequence(adev, 3687 golden_settings_gc_12_0_rev0, 3688 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3689 break; 3690 default: 3691 break; 3692 } 3693 } 3694 3695 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3696 bool enable) 3697 { 3698 unsigned int irq_type; 3699 int m, p, r; 3700 3701 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3702 for (m = 0; m < adev->gfx.me.num_me; m++) { 3703 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3704 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3705 if (enable) 3706 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3707 else 3708 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3709 if (r) { 3710 if (!enable) 3711 return r; 3712 goto err_gfx; 3713 } 3714 } 3715 } 3716 } 3717 3718 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3719 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3720 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3721 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3722 + (m * adev->gfx.mec.num_pipe_per_mec) 3723 + p; 3724 if (enable) 3725 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 3726 else 3727 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3728 if (r) { 3729 if (!enable) 3730 return r; 3731 goto err_compute; 3732 } 3733 } 3734 } 3735 } 3736 3737 return 0; 3738 3739 err_compute: 3740 for (p--; p >= 0; p--) { 3741 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3742 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3743 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3744 } 3745 for (m--; m >= 0; m--) { 3746 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 3747 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3748 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 3749 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3750 } 3751 } 3752 m = adev->gfx.me.num_me; 3753 err_gfx: 3754 for (p--; p >= 0; p--) { 3755 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3756 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3757 } 3758 for (m--; m >= 0; m--) { 3759 for (p = adev->gfx.me.num_pipe_per_me - 1; p >= 0; p--) { 3760 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3761 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 3762 } 3763 } 3764 return r; 3765 } 3766 3767 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3768 { 3769 int r; 3770 struct amdgpu_device *adev = ip_block->adev; 3771 3772 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3773 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3774 /* RLC autoload sequence 1: Program rlc ram */ 3775 if (adev->gfx.imu.funcs->program_rlc_ram) 3776 adev->gfx.imu.funcs->program_rlc_ram(adev); 3777 } 3778 /* rlc autoload firmware */ 3779 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3780 if (r) 3781 return r; 3782 } else { 3783 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3784 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3785 if (adev->gfx.imu.funcs->load_microcode) 3786 adev->gfx.imu.funcs->load_microcode(adev); 3787 if (adev->gfx.imu.funcs->setup_imu) 3788 adev->gfx.imu.funcs->setup_imu(adev); 3789 if (adev->gfx.imu.funcs->start_imu) 3790 adev->gfx.imu.funcs->start_imu(adev); 3791 } 3792 3793 /* disable gpa mode in backdoor loading */ 3794 gfx_v12_0_disable_gpa_mode(adev); 3795 } 3796 } 3797 3798 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3799 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3800 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3801 if (r) { 3802 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3803 return r; 3804 } 3805 } 3806 3807 if (!amdgpu_emu_mode) 3808 gfx_v12_0_init_golden_registers(adev); 3809 3810 adev->gfx.is_poweron = true; 3811 3812 if (get_gb_addr_config(adev)) 3813 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 3814 3815 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3816 gfx_v12_0_config_gfx_rs64(adev); 3817 3818 r = gfx_v12_0_gfxhub_enable(adev); 3819 if (r) 3820 return r; 3821 3822 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3823 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3824 (amdgpu_dpm == 1)) { 3825 /** 3826 * For gfx 12, rlc firmware loading relies on smu firmware is 3827 * loaded firstly, so in direct type, it has to load smc ucode 3828 * here before rlc. 3829 */ 3830 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3831 if (r) 3832 return r; 3833 } 3834 3835 gfx_v12_0_constants_init(adev); 3836 3837 if (adev->nbio.funcs->gc_doorbell_init) 3838 adev->nbio.funcs->gc_doorbell_init(adev); 3839 3840 r = gfx_v12_0_rlc_resume(adev); 3841 if (r) 3842 return r; 3843 3844 /* 3845 * init golden registers and rlc resume may override some registers, 3846 * reconfig them here 3847 */ 3848 gfx_v12_0_tcp_harvest(adev); 3849 3850 r = gfx_v12_0_cp_resume(adev); 3851 if (r) 3852 return r; 3853 3854 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3855 if (r) 3856 return r; 3857 3858 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3859 if (r) 3860 goto err_priv_inst; 3861 3862 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3863 if (r) 3864 goto err_bad_op; 3865 3866 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3867 if (r) 3868 goto err_userq_eop; 3869 3870 return 0; 3871 3872 err_userq_eop: 3873 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3874 err_bad_op: 3875 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3876 err_priv_inst: 3877 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3878 return r; 3879 } 3880 3881 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3882 { 3883 struct amdgpu_device *adev = ip_block->adev; 3884 uint32_t tmp; 3885 3886 cancel_delayed_work_sync(&adev->gfx.idle_work); 3887 3888 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3889 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3890 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3891 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3892 3893 if (!adev->no_hw_access) { 3894 if (amdgpu_async_gfx_ring) { 3895 if (amdgpu_gfx_disable_kgq(adev, 0)) 3896 DRM_ERROR("KGQ disable failed\n"); 3897 } 3898 3899 if (amdgpu_gfx_disable_kcq(adev, 0)) 3900 DRM_ERROR("KCQ disable failed\n"); 3901 3902 amdgpu_mes_kiq_hw_fini(adev, 0); 3903 } 3904 3905 if (amdgpu_sriov_vf(adev)) { 3906 gfx_v12_0_cp_gfx_enable(adev, false); 3907 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3908 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3909 tmp &= 0xffffff00; 3910 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3911 3912 return 0; 3913 } 3914 gfx_v12_0_cp_enable(adev, false); 3915 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3916 3917 adev->gfxhub.funcs->gart_disable(adev); 3918 3919 adev->gfx.is_poweron = false; 3920 3921 return 0; 3922 } 3923 3924 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3925 { 3926 return gfx_v12_0_hw_fini(ip_block); 3927 } 3928 3929 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3930 { 3931 return gfx_v12_0_hw_init(ip_block); 3932 } 3933 3934 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3935 { 3936 struct amdgpu_device *adev = ip_block->adev; 3937 3938 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3939 GRBM_STATUS, GUI_ACTIVE)) 3940 return false; 3941 else 3942 return true; 3943 } 3944 3945 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3946 { 3947 unsigned i; 3948 u32 tmp; 3949 struct amdgpu_device *adev = ip_block->adev; 3950 3951 for (i = 0; i < adev->usec_timeout; i++) { 3952 /* read MC_STATUS */ 3953 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3954 GRBM_STATUS__GUI_ACTIVE_MASK; 3955 3956 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3957 return 0; 3958 udelay(1); 3959 } 3960 return -ETIMEDOUT; 3961 } 3962 3963 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3964 { 3965 uint64_t clock = 0; 3966 3967 if (adev->smuio.funcs && 3968 adev->smuio.funcs->get_gpu_clock_counter) 3969 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3970 else 3971 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3972 3973 return clock; 3974 } 3975 3976 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3977 { 3978 struct amdgpu_device *adev = ip_block->adev; 3979 3980 switch (amdgpu_user_queue) { 3981 case -1: 3982 case 0: 3983 default: 3984 adev->gfx.disable_kq = false; 3985 adev->gfx.disable_uq = true; 3986 break; 3987 case 1: 3988 adev->gfx.disable_kq = false; 3989 adev->gfx.disable_uq = false; 3990 break; 3991 case 2: 3992 adev->gfx.disable_kq = true; 3993 adev->gfx.disable_uq = false; 3994 break; 3995 } 3996 3997 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3998 3999 if (adev->gfx.disable_kq) { 4000 adev->gfx.num_gfx_rings = 0; 4001 adev->gfx.num_compute_rings = 0; 4002 } else { 4003 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 4004 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4005 AMDGPU_MAX_COMPUTE_RINGS); 4006 } 4007 4008 gfx_v12_0_set_kiq_pm4_funcs(adev); 4009 gfx_v12_0_set_ring_funcs(adev); 4010 gfx_v12_0_set_irq_funcs(adev); 4011 gfx_v12_0_set_rlc_funcs(adev); 4012 gfx_v12_0_set_mqd_funcs(adev); 4013 gfx_v12_0_set_imu_funcs(adev); 4014 4015 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 4016 4017 amdgpu_init_rlc_reg_funcs(adev); 4018 4019 return gfx_v12_0_init_microcode(adev); 4020 } 4021 4022 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 4023 { 4024 uint32_t rlc_cntl; 4025 4026 /* if RLC is not enabled, do nothing */ 4027 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4028 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4029 } 4030 4031 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 4032 int xcc_id) 4033 { 4034 uint32_t data; 4035 unsigned i; 4036 4037 data = RLC_SAFE_MODE__CMD_MASK; 4038 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4039 4040 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4041 4042 /* wait for RLC_SAFE_MODE */ 4043 for (i = 0; i < adev->usec_timeout; i++) { 4044 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4045 RLC_SAFE_MODE, CMD)) 4046 break; 4047 udelay(1); 4048 } 4049 } 4050 4051 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 4052 int xcc_id) 4053 { 4054 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4055 } 4056 4057 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 4058 bool enable) 4059 { 4060 uint32_t def, data; 4061 4062 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4063 return; 4064 4065 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4066 4067 if (enable) 4068 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4069 else 4070 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4071 4072 if (def != data) 4073 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4074 } 4075 4076 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 4077 int xcc_id, 4078 struct amdgpu_ring *ring, 4079 unsigned vmid) 4080 { 4081 u32 reg, data; 4082 4083 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4084 if (amdgpu_sriov_is_pp_one_vf(adev)) 4085 data = RREG32_NO_KIQ(reg); 4086 else 4087 data = RREG32(reg); 4088 4089 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4090 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4091 4092 if (amdgpu_sriov_is_pp_one_vf(adev)) 4093 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 4094 else 4095 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 4096 4097 if (ring 4098 && amdgpu_sriov_is_pp_one_vf(adev) 4099 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 4100 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 4101 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4102 amdgpu_ring_emit_wreg(ring, reg, data); 4103 } 4104 } 4105 4106 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 4107 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 4108 .set_safe_mode = gfx_v12_0_set_safe_mode, 4109 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 4110 .init = gfx_v12_0_rlc_init, 4111 .get_csb_size = gfx_v12_0_get_csb_size, 4112 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 4113 .resume = gfx_v12_0_rlc_resume, 4114 .stop = gfx_v12_0_rlc_stop, 4115 .reset = gfx_v12_0_rlc_reset, 4116 .start = gfx_v12_0_rlc_start, 4117 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4118 }; 4119 4120 #if 0 4121 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4122 { 4123 /* TODO */ 4124 } 4125 4126 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4127 { 4128 /* TODO */ 4129 } 4130 #endif 4131 4132 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4133 enum amd_powergating_state state) 4134 { 4135 struct amdgpu_device *adev = ip_block->adev; 4136 bool enable = (state == AMD_PG_STATE_GATE); 4137 4138 if (amdgpu_sriov_vf(adev)) 4139 return 0; 4140 4141 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4142 case IP_VERSION(12, 0, 0): 4143 case IP_VERSION(12, 0, 1): 4144 amdgpu_gfx_off_ctrl(adev, enable); 4145 break; 4146 default: 4147 break; 4148 } 4149 4150 return 0; 4151 } 4152 4153 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4154 bool enable) 4155 { 4156 uint32_t def, data; 4157 4158 if (!(adev->cg_flags & 4159 (AMD_CG_SUPPORT_GFX_CGCG | 4160 AMD_CG_SUPPORT_GFX_CGLS | 4161 AMD_CG_SUPPORT_GFX_3D_CGCG | 4162 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4163 return; 4164 4165 if (enable) { 4166 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4167 4168 /* unset CGCG override */ 4169 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4170 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4171 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4172 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4173 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4174 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4175 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4176 4177 /* update CGCG override bits */ 4178 if (def != data) 4179 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4180 4181 /* enable cgcg FSM(0x0000363F) */ 4182 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4183 4184 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4185 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4186 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4187 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4188 } 4189 4190 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4191 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4192 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4193 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4194 } 4195 4196 if (def != data) 4197 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4198 4199 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4200 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4201 4202 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4203 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4204 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4205 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4206 } 4207 4208 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4209 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4210 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4211 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4212 } 4213 4214 if (def != data) 4215 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4216 4217 /* set IDLE_POLL_COUNT(0x00900100) */ 4218 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4219 4220 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4221 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4222 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4223 4224 if (def != data) 4225 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4226 4227 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4228 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4229 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4230 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4231 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4232 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4233 4234 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4235 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4236 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4237 4238 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4239 if (adev->sdma.num_instances > 1) { 4240 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4241 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4242 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4243 } 4244 } else { 4245 /* Program RLC_CGCG_CGLS_CTRL */ 4246 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4247 4248 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4249 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4250 4251 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4252 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4253 4254 if (def != data) 4255 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4256 4257 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4258 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4259 4260 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4261 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4262 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4263 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4264 4265 if (def != data) 4266 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4267 } 4268 } 4269 4270 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4271 bool enable) 4272 { 4273 uint32_t data, def; 4274 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4275 return; 4276 4277 /* It is disabled by HW by default */ 4278 if (enable) { 4279 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4280 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4281 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4282 4283 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4284 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4285 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4286 4287 if (def != data) 4288 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4289 } 4290 } else { 4291 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4292 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4293 4294 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4295 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4296 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4297 4298 if (def != data) 4299 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4300 } 4301 } 4302 } 4303 4304 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4305 bool enable) 4306 { 4307 uint32_t def, data; 4308 4309 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4310 return; 4311 4312 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4313 4314 if (enable) 4315 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4316 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4317 else 4318 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4319 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4320 4321 if (def != data) 4322 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4323 } 4324 4325 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4326 bool enable) 4327 { 4328 uint32_t def, data; 4329 4330 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4331 return; 4332 4333 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4334 4335 if (enable) 4336 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4337 else 4338 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4339 4340 if (def != data) 4341 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4342 } 4343 4344 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4345 bool enable) 4346 { 4347 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4348 4349 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4350 4351 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4352 4353 gfx_v12_0_update_repeater_fgcg(adev, enable); 4354 4355 gfx_v12_0_update_sram_fgcg(adev, enable); 4356 4357 gfx_v12_0_update_perf_clk(adev, enable); 4358 4359 if (adev->cg_flags & 4360 (AMD_CG_SUPPORT_GFX_MGCG | 4361 AMD_CG_SUPPORT_GFX_CGLS | 4362 AMD_CG_SUPPORT_GFX_CGCG | 4363 AMD_CG_SUPPORT_GFX_3D_CGCG | 4364 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4365 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4366 4367 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4368 4369 return 0; 4370 } 4371 4372 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4373 enum amd_clockgating_state state) 4374 { 4375 struct amdgpu_device *adev = ip_block->adev; 4376 4377 if (amdgpu_sriov_vf(adev)) 4378 return 0; 4379 4380 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4381 case IP_VERSION(12, 0, 0): 4382 case IP_VERSION(12, 0, 1): 4383 gfx_v12_0_update_gfx_clock_gating(adev, 4384 state == AMD_CG_STATE_GATE); 4385 break; 4386 default: 4387 break; 4388 } 4389 4390 return 0; 4391 } 4392 4393 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4394 { 4395 struct amdgpu_device *adev = ip_block->adev; 4396 int data; 4397 4398 /* AMD_CG_SUPPORT_GFX_MGCG */ 4399 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4400 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4401 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4402 4403 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4404 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4405 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4406 4407 /* AMD_CG_SUPPORT_GFX_FGCG */ 4408 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4409 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4410 4411 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4412 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4413 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4414 4415 /* AMD_CG_SUPPORT_GFX_CGCG */ 4416 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4417 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4418 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4419 4420 /* AMD_CG_SUPPORT_GFX_CGLS */ 4421 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4422 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4423 4424 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4425 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4426 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4427 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4428 4429 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4430 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4431 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4432 } 4433 4434 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4435 { 4436 /* gfx12 is 32bit rptr*/ 4437 return *(uint32_t *)ring->rptr_cpu_addr; 4438 } 4439 4440 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4441 { 4442 struct amdgpu_device *adev = ring->adev; 4443 u64 wptr; 4444 4445 /* XXX check if swapping is necessary on BE */ 4446 if (ring->use_doorbell) { 4447 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4448 } else { 4449 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4450 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4451 } 4452 4453 return wptr; 4454 } 4455 4456 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4457 { 4458 struct amdgpu_device *adev = ring->adev; 4459 4460 if (ring->use_doorbell) { 4461 /* XXX check if swapping is necessary on BE */ 4462 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4463 ring->wptr); 4464 WDOORBELL64(ring->doorbell_index, ring->wptr); 4465 } else { 4466 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4467 lower_32_bits(ring->wptr)); 4468 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4469 upper_32_bits(ring->wptr)); 4470 } 4471 } 4472 4473 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4474 { 4475 /* gfx12 hardware is 32bit rptr */ 4476 return *(uint32_t *)ring->rptr_cpu_addr; 4477 } 4478 4479 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4480 { 4481 struct amdgpu_device *adev = ring->adev; 4482 u64 wptr; 4483 4484 /* XXX check if swapping is necessary on BE */ 4485 if (ring->use_doorbell) { 4486 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4487 } else { 4488 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 4489 wptr = 0; 4490 } 4491 return wptr; 4492 } 4493 4494 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4495 { 4496 struct amdgpu_device *adev = ring->adev; 4497 4498 /* XXX check if swapping is necessary on BE */ 4499 if (ring->use_doorbell) { 4500 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4501 ring->wptr); 4502 WDOORBELL64(ring->doorbell_index, ring->wptr); 4503 } else { 4504 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 4505 } 4506 } 4507 4508 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4509 { 4510 struct amdgpu_device *adev = ring->adev; 4511 u32 ref_and_mask, reg_mem_engine; 4512 4513 if (!adev->gfx.funcs->get_hdp_flush_mask) { 4514 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 4515 return; 4516 } 4517 4518 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 4519 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4520 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4521 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4522 ref_and_mask, ref_and_mask, 0x20); 4523 } 4524 4525 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4526 struct amdgpu_job *job, 4527 struct amdgpu_ib *ib, 4528 uint32_t flags) 4529 { 4530 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4531 u32 header, control = 0; 4532 4533 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4534 4535 control |= ib->length_dw | (vmid << 24); 4536 4537 amdgpu_ring_write(ring, header); 4538 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4539 amdgpu_ring_write(ring, 4540 #ifdef __BIG_ENDIAN 4541 (2 << 0) | 4542 #endif 4543 lower_32_bits(ib->gpu_addr)); 4544 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4545 amdgpu_ring_write(ring, control); 4546 } 4547 4548 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4549 struct amdgpu_job *job, 4550 struct amdgpu_ib *ib, 4551 uint32_t flags) 4552 { 4553 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4554 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4555 4556 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4557 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 4558 amdgpu_ring_write(ring, 4559 #ifdef __BIG_ENDIAN 4560 (2 << 0) | 4561 #endif 4562 lower_32_bits(ib->gpu_addr)); 4563 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4564 amdgpu_ring_write(ring, control); 4565 } 4566 4567 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4568 u64 seq, unsigned flags) 4569 { 4570 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4571 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4572 4573 /* RELEASE_MEM - flush caches, send int */ 4574 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4575 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4576 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4577 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4578 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4579 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4580 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4581 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4582 4583 /* 4584 * the address should be Qword aligned if 64bit write, Dword 4585 * aligned if only send 32bit data low (discard data high) 4586 */ 4587 if (write64bit) 4588 WARN_ON(addr & 0x7); 4589 else 4590 WARN_ON(addr & 0x3); 4591 amdgpu_ring_write(ring, lower_32_bits(addr)); 4592 amdgpu_ring_write(ring, upper_32_bits(addr)); 4593 amdgpu_ring_write(ring, lower_32_bits(seq)); 4594 amdgpu_ring_write(ring, upper_32_bits(seq)); 4595 amdgpu_ring_write(ring, 0); 4596 } 4597 4598 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4599 { 4600 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4601 uint32_t seq = ring->fence_drv.sync_seq; 4602 uint64_t addr = ring->fence_drv.gpu_addr; 4603 4604 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4605 upper_32_bits(addr), seq, 0xffffffff, 4); 4606 } 4607 4608 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4609 uint16_t pasid, uint32_t flush_type, 4610 bool all_hub, uint8_t dst_sel) 4611 { 4612 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4613 amdgpu_ring_write(ring, 4614 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4615 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4616 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4617 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4618 } 4619 4620 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4621 unsigned vmid, uint64_t pd_addr) 4622 { 4623 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4624 4625 /* compute doesn't have PFP */ 4626 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4627 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4628 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4629 amdgpu_ring_write(ring, 0x0); 4630 } 4631 } 4632 4633 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4634 u64 seq, unsigned int flags) 4635 { 4636 struct amdgpu_device *adev = ring->adev; 4637 4638 /* write fence seq to the "addr" */ 4639 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4640 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4641 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4642 amdgpu_ring_write(ring, lower_32_bits(addr)); 4643 amdgpu_ring_write(ring, upper_32_bits(addr)); 4644 amdgpu_ring_write(ring, lower_32_bits(seq)); 4645 4646 if (flags & AMDGPU_FENCE_FLAG_INT) { 4647 /* set register to trigger INT */ 4648 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4649 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4650 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4651 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4652 amdgpu_ring_write(ring, 0); 4653 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4654 } 4655 } 4656 4657 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4658 uint32_t flags) 4659 { 4660 uint32_t dw2 = 0; 4661 4662 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4663 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4664 /* set load_global_config & load_global_uconfig */ 4665 dw2 |= 0x8001; 4666 /* set load_cs_sh_regs */ 4667 dw2 |= 0x01000000; 4668 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4669 dw2 |= 0x10002; 4670 } 4671 4672 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4673 amdgpu_ring_write(ring, dw2); 4674 amdgpu_ring_write(ring, 0); 4675 } 4676 4677 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4678 uint64_t addr) 4679 { 4680 unsigned ret; 4681 4682 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4683 amdgpu_ring_write(ring, lower_32_bits(addr)); 4684 amdgpu_ring_write(ring, upper_32_bits(addr)); 4685 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4686 amdgpu_ring_write(ring, 0); 4687 ret = ring->wptr & ring->buf_mask; 4688 /* patch dummy value later */ 4689 amdgpu_ring_write(ring, 0); 4690 4691 return ret; 4692 } 4693 4694 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4695 uint32_t reg_val_offs) 4696 { 4697 struct amdgpu_device *adev = ring->adev; 4698 4699 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4700 amdgpu_ring_write(ring, 0 | /* src: register*/ 4701 (5 << 8) | /* dst: memory */ 4702 (1 << 20)); /* write confirm */ 4703 amdgpu_ring_write(ring, reg); 4704 amdgpu_ring_write(ring, 0); 4705 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4706 reg_val_offs * 4)); 4707 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4708 reg_val_offs * 4)); 4709 } 4710 4711 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4712 uint32_t reg, 4713 uint32_t val) 4714 { 4715 uint32_t cmd = 0; 4716 4717 switch (ring->funcs->type) { 4718 case AMDGPU_RING_TYPE_GFX: 4719 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4720 break; 4721 case AMDGPU_RING_TYPE_KIQ: 4722 cmd = (1 << 16); /* no inc addr */ 4723 break; 4724 default: 4725 cmd = WR_CONFIRM; 4726 break; 4727 } 4728 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4729 amdgpu_ring_write(ring, cmd); 4730 amdgpu_ring_write(ring, reg); 4731 amdgpu_ring_write(ring, 0); 4732 amdgpu_ring_write(ring, val); 4733 } 4734 4735 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4736 uint32_t val, uint32_t mask) 4737 { 4738 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4739 } 4740 4741 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4742 uint32_t reg0, uint32_t reg1, 4743 uint32_t ref, uint32_t mask) 4744 { 4745 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4746 4747 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4748 ref, mask, 0x20); 4749 } 4750 4751 static void 4752 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4753 uint32_t me, uint32_t pipe, 4754 enum amdgpu_interrupt_state state) 4755 { 4756 uint32_t cp_int_cntl, cp_int_cntl_reg; 4757 4758 if (!me) { 4759 switch (pipe) { 4760 case 0: 4761 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4762 break; 4763 default: 4764 DRM_DEBUG("invalid pipe %d\n", pipe); 4765 return; 4766 } 4767 } else { 4768 DRM_DEBUG("invalid me %d\n", me); 4769 return; 4770 } 4771 4772 switch (state) { 4773 case AMDGPU_IRQ_STATE_DISABLE: 4774 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4775 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4776 TIME_STAMP_INT_ENABLE, 0); 4777 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4778 GENERIC0_INT_ENABLE, 0); 4779 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4780 break; 4781 case AMDGPU_IRQ_STATE_ENABLE: 4782 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4783 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4784 TIME_STAMP_INT_ENABLE, 1); 4785 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4786 GENERIC0_INT_ENABLE, 1); 4787 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4788 break; 4789 default: 4790 break; 4791 } 4792 } 4793 4794 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4795 int me, int pipe, 4796 enum amdgpu_interrupt_state state) 4797 { 4798 u32 mec_int_cntl, mec_int_cntl_reg; 4799 4800 /* 4801 * amdgpu controls only the first MEC. That's why this function only 4802 * handles the setting of interrupts for this specific MEC. All other 4803 * pipes' interrupts are set by amdkfd. 4804 */ 4805 4806 if (me == 1) { 4807 switch (pipe) { 4808 case 0: 4809 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4810 break; 4811 case 1: 4812 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4813 break; 4814 default: 4815 DRM_DEBUG("invalid pipe %d\n", pipe); 4816 return; 4817 } 4818 } else { 4819 DRM_DEBUG("invalid me %d\n", me); 4820 return; 4821 } 4822 4823 switch (state) { 4824 case AMDGPU_IRQ_STATE_DISABLE: 4825 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4826 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4827 TIME_STAMP_INT_ENABLE, 0); 4828 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4829 GENERIC0_INT_ENABLE, 0); 4830 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4831 break; 4832 case AMDGPU_IRQ_STATE_ENABLE: 4833 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4834 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4835 TIME_STAMP_INT_ENABLE, 1); 4836 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4837 GENERIC0_INT_ENABLE, 1); 4838 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4839 break; 4840 default: 4841 break; 4842 } 4843 } 4844 4845 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4846 struct amdgpu_irq_src *src, 4847 unsigned type, 4848 enum amdgpu_interrupt_state state) 4849 { 4850 switch (type) { 4851 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4852 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4853 break; 4854 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4855 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4856 break; 4857 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4858 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4859 break; 4860 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4861 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4862 break; 4863 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4864 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4865 break; 4866 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4867 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4868 break; 4869 default: 4870 break; 4871 } 4872 return 0; 4873 } 4874 4875 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4876 struct amdgpu_irq_src *source, 4877 struct amdgpu_iv_entry *entry) 4878 { 4879 u32 doorbell_offset = entry->src_data[0]; 4880 4881 DRM_DEBUG("IH: CP EOP\n"); 4882 4883 if (!adev->gfx.disable_kq) { 4884 u8 me_id = (entry->ring_id & 0x0c) >> 2; 4885 u8 pipe_id = (entry->ring_id & 0x03) >> 0; 4886 u8 queue_id = (entry->ring_id & 0x70) >> 4; 4887 struct amdgpu_ring *ring; 4888 int i; 4889 4890 switch (me_id) { 4891 case 0: 4892 /* 4893 * MES splits gfx HQDs per (me,pipe): KGQ owns queue=0, 4894 * userq gfx owns queue>=1 (see amdgpu_mes_get_hqd_mask). 4895 * Require a strict (me,pipe,queue) match so userq gfx 4896 * EOPs fall through to amdgpu_userq_process_fence_irq(). 4897 */ 4898 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4899 ring = &adev->gfx.gfx_ring[i]; 4900 if ((ring->me == me_id) && 4901 (ring->pipe == pipe_id) && 4902 (ring->queue == queue_id)) { 4903 amdgpu_fence_process(ring); 4904 return 0; 4905 } 4906 } 4907 break; 4908 case 1: 4909 case 2: 4910 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4911 ring = &adev->gfx.compute_ring[i]; 4912 /* Per-queue interrupt is supported for MEC starting from VI. 4913 * The interrupt can only be enabled/disabled per pipe instead 4914 * of per queue. 4915 */ 4916 if ((ring->me == me_id) && 4917 (ring->pipe == pipe_id) && 4918 (ring->queue == queue_id)) { 4919 amdgpu_fence_process(ring); 4920 return 0; 4921 } 4922 } 4923 break; 4924 default: 4925 break; 4926 } 4927 } 4928 4929 if (adev->enable_mes && doorbell_offset) 4930 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 4931 4932 return 0; 4933 } 4934 4935 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4936 struct amdgpu_irq_src *source, 4937 unsigned int type, 4938 enum amdgpu_interrupt_state state) 4939 { 4940 u32 cp_int_cntl_reg, cp_int_cntl; 4941 int i, j; 4942 4943 switch (state) { 4944 case AMDGPU_IRQ_STATE_DISABLE: 4945 case AMDGPU_IRQ_STATE_ENABLE: 4946 for (i = 0; i < adev->gfx.me.num_me; i++) { 4947 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4948 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4949 4950 if (cp_int_cntl_reg) { 4951 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4952 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4953 PRIV_REG_INT_ENABLE, 4954 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4955 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4956 } 4957 } 4958 } 4959 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4960 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4961 /* MECs start at 1 */ 4962 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4963 4964 if (cp_int_cntl_reg) { 4965 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4966 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4967 PRIV_REG_INT_ENABLE, 4968 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4969 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4970 } 4971 } 4972 } 4973 break; 4974 default: 4975 break; 4976 } 4977 4978 return 0; 4979 } 4980 4981 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4982 struct amdgpu_irq_src *source, 4983 unsigned type, 4984 enum amdgpu_interrupt_state state) 4985 { 4986 u32 cp_int_cntl_reg, cp_int_cntl; 4987 int i, j; 4988 4989 switch (state) { 4990 case AMDGPU_IRQ_STATE_DISABLE: 4991 case AMDGPU_IRQ_STATE_ENABLE: 4992 for (i = 0; i < adev->gfx.me.num_me; i++) { 4993 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4994 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4995 4996 if (cp_int_cntl_reg) { 4997 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4998 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4999 OPCODE_ERROR_INT_ENABLE, 5000 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5001 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5002 } 5003 } 5004 } 5005 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5006 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5007 /* MECs start at 1 */ 5008 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 5009 5010 if (cp_int_cntl_reg) { 5011 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5012 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5013 OPCODE_ERROR_INT_ENABLE, 5014 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5015 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5016 } 5017 } 5018 } 5019 break; 5020 default: 5021 break; 5022 } 5023 return 0; 5024 } 5025 5026 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5027 struct amdgpu_irq_src *source, 5028 unsigned int type, 5029 enum amdgpu_interrupt_state state) 5030 { 5031 u32 cp_int_cntl_reg, cp_int_cntl; 5032 int i, j; 5033 5034 switch (state) { 5035 case AMDGPU_IRQ_STATE_DISABLE: 5036 case AMDGPU_IRQ_STATE_ENABLE: 5037 for (i = 0; i < adev->gfx.me.num_me; i++) { 5038 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5039 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 5040 5041 if (cp_int_cntl_reg) { 5042 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5043 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5044 PRIV_INSTR_INT_ENABLE, 5045 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5046 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5047 } 5048 } 5049 } 5050 break; 5051 default: 5052 break; 5053 } 5054 5055 return 0; 5056 } 5057 5058 /* 5059 * A gfx exception IV carries no doorbell. For each faulted slot, read the 5060 * doorbell back from the HQD (left in place by the fatal fault), look up the 5061 * user queue and kick its per-queue reset. 5062 */ 5063 static void gfx_v12_0_userq_priv_fault_work(struct work_struct *work) 5064 { 5065 struct amdgpu_device *adev = 5066 container_of(work, struct amdgpu_device, gfx.userq_priv_fault_work); 5067 unsigned long slots = xchg(&adev->gfx.userq_priv_fault_slots, 0); 5068 unsigned int id; 5069 5070 for_each_set_bit(id, &slots, BITS_PER_LONG) { 5071 u8 pipe = id & 0x3; 5072 u8 queue = (id >> 2) & 0x7; 5073 struct amdgpu_usermode_queue *q; 5074 u32 db_ctrl, doorbell; 5075 5076 amdgpu_gfx_off_ctrl(adev, false); 5077 mutex_lock(&adev->srbm_mutex); 5078 soc24_grbm_select(adev, 0, pipe, queue, 0); 5079 db_ctrl = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 5080 soc24_grbm_select(adev, 0, 0, 0, 0); 5081 mutex_unlock(&adev->srbm_mutex); 5082 amdgpu_gfx_off_ctrl(adev, true); 5083 5084 doorbell = (db_ctrl & CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK) >> 5085 CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 5086 q = xa_load(&adev->userq_doorbell_xa, doorbell); 5087 if (q) 5088 amdgpu_userq_start_hang_detect_work(q); 5089 } 5090 } 5091 5092 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 5093 struct amdgpu_iv_entry *entry) 5094 { 5095 u8 me_id, pipe_id, queue_id; 5096 5097 me_id = (entry->ring_id & 0x0c) >> 2; 5098 pipe_id = (entry->ring_id & 0x03) >> 0; 5099 queue_id = (entry->ring_id & 0x70) >> 4; 5100 5101 amdgpu_gfx_handle_priv_fault(adev, entry, me_id, pipe_id, queue_id); 5102 } 5103 5104 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5105 struct amdgpu_irq_src *source, 5106 struct amdgpu_iv_entry *entry) 5107 { 5108 DRM_ERROR("Illegal register access in command stream\n"); 5109 gfx_v12_0_handle_priv_fault(adev, entry); 5110 return 0; 5111 } 5112 5113 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5114 struct amdgpu_irq_src *source, 5115 struct amdgpu_iv_entry *entry) 5116 { 5117 DRM_ERROR("Illegal opcode in command stream\n"); 5118 gfx_v12_0_handle_priv_fault(adev, entry); 5119 return 0; 5120 } 5121 5122 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5123 struct amdgpu_irq_src *source, 5124 struct amdgpu_iv_entry *entry) 5125 { 5126 DRM_ERROR("Illegal instruction in command stream\n"); 5127 gfx_v12_0_handle_priv_fault(adev, entry); 5128 return 0; 5129 } 5130 5131 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5132 { 5133 const unsigned int gcr_cntl = 5134 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5135 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5136 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5137 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5138 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5139 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5140 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5141 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5142 5143 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5144 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5145 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5146 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5147 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5148 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5149 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5150 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5151 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5152 } 5153 5154 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5155 { 5156 /* Header itself is a NOP packet */ 5157 if (num_nop == 1) { 5158 amdgpu_ring_write(ring, ring->funcs->nop); 5159 return; 5160 } 5161 5162 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5163 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5164 5165 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5166 amdgpu_ring_insert_nop(ring, num_nop - 1); 5167 } 5168 5169 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5170 { 5171 /* Emit the cleaner shader */ 5172 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5173 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5174 } 5175 5176 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5177 { 5178 struct amdgpu_device *adev = ip_block->adev; 5179 uint32_t i, j, k, reg, index = 0; 5180 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5181 5182 if (!adev->gfx.ip_dump_core) 5183 return; 5184 5185 for (i = 0; i < reg_count; i++) 5186 drm_printf(p, "%-50s \t 0x%08x\n", 5187 gc_reg_list_12_0[i].reg_name, 5188 adev->gfx.ip_dump_core[i]); 5189 5190 /* print compute queue registers for all instances */ 5191 if (!adev->gfx.ip_dump_compute_queues) 5192 return; 5193 5194 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5195 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5196 adev->gfx.mec.num_mec, 5197 adev->gfx.mec.num_pipe_per_mec, 5198 adev->gfx.mec.num_queue_per_pipe); 5199 5200 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5201 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5202 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5203 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5204 for (reg = 0; reg < reg_count; reg++) { 5205 drm_printf(p, "%-50s \t 0x%08x\n", 5206 gc_cp_reg_list_12[reg].reg_name, 5207 adev->gfx.ip_dump_compute_queues[index + reg]); 5208 } 5209 index += reg_count; 5210 } 5211 } 5212 } 5213 5214 /* print gfx queue registers for all instances */ 5215 if (!adev->gfx.ip_dump_gfx_queues) 5216 return; 5217 5218 index = 0; 5219 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5220 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5221 adev->gfx.me.num_me, 5222 adev->gfx.me.num_pipe_per_me, 5223 adev->gfx.me.num_queue_per_pipe); 5224 5225 for (i = 0; i < adev->gfx.me.num_me; i++) { 5226 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5227 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5228 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5229 for (reg = 0; reg < reg_count; reg++) { 5230 drm_printf(p, "%-50s \t 0x%08x\n", 5231 gc_gfx_queue_reg_list_12[reg].reg_name, 5232 adev->gfx.ip_dump_gfx_queues[index + reg]); 5233 } 5234 index += reg_count; 5235 } 5236 } 5237 } 5238 } 5239 5240 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5241 { 5242 struct amdgpu_device *adev = ip_block->adev; 5243 uint32_t i, j, k, reg, index = 0; 5244 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5245 5246 if (!adev->gfx.ip_dump_core) 5247 return; 5248 5249 amdgpu_gfx_off_ctrl(adev, false); 5250 for (i = 0; i < reg_count; i++) 5251 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5252 amdgpu_gfx_off_ctrl(adev, true); 5253 5254 /* dump compute queue registers for all instances */ 5255 if (!adev->gfx.ip_dump_compute_queues) 5256 return; 5257 5258 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5259 amdgpu_gfx_off_ctrl(adev, false); 5260 mutex_lock(&adev->srbm_mutex); 5261 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5262 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5263 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5264 /* ME0 is for GFX so start from 1 for CP */ 5265 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5266 for (reg = 0; reg < reg_count; reg++) { 5267 adev->gfx.ip_dump_compute_queues[index + reg] = 5268 RREG32(SOC15_REG_ENTRY_OFFSET( 5269 gc_cp_reg_list_12[reg])); 5270 } 5271 index += reg_count; 5272 } 5273 } 5274 } 5275 soc24_grbm_select(adev, 0, 0, 0, 0); 5276 mutex_unlock(&adev->srbm_mutex); 5277 amdgpu_gfx_off_ctrl(adev, true); 5278 5279 /* dump gfx queue registers for all instances */ 5280 if (!adev->gfx.ip_dump_gfx_queues) 5281 return; 5282 5283 index = 0; 5284 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5285 amdgpu_gfx_off_ctrl(adev, false); 5286 mutex_lock(&adev->srbm_mutex); 5287 for (i = 0; i < adev->gfx.me.num_me; i++) { 5288 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5289 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5290 soc24_grbm_select(adev, i, j, k, 0); 5291 5292 for (reg = 0; reg < reg_count; reg++) { 5293 adev->gfx.ip_dump_gfx_queues[index + reg] = 5294 RREG32(SOC15_REG_ENTRY_OFFSET( 5295 gc_gfx_queue_reg_list_12[reg])); 5296 } 5297 index += reg_count; 5298 } 5299 } 5300 } 5301 soc24_grbm_select(adev, 0, 0, 0, 0); 5302 mutex_unlock(&adev->srbm_mutex); 5303 amdgpu_gfx_off_ctrl(adev, true); 5304 } 5305 5306 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5307 unsigned int vmid, 5308 struct amdgpu_fence *timedout_fence) 5309 { 5310 struct amdgpu_device *adev = ring->adev; 5311 bool use_mmio = adev->gfx.me.use_mmio_for_reset; 5312 5313 return amdgpu_gfx_mes_reset_queue(ring, vmid, timedout_fence, use_mmio); 5314 } 5315 5316 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5317 unsigned int vmid, 5318 struct amdgpu_fence *timedout_fence) 5319 { 5320 struct amdgpu_device *adev = ring->adev; 5321 5322 return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); 5323 } 5324 5325 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5326 { 5327 amdgpu_gfx_profile_ring_begin_use(ring); 5328 5329 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5330 } 5331 5332 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5333 { 5334 amdgpu_gfx_profile_ring_end_use(ring); 5335 5336 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5337 } 5338 5339 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5340 .name = "gfx_v12_0", 5341 .early_init = gfx_v12_0_early_init, 5342 .sw_init = gfx_v12_0_sw_init, 5343 .sw_fini = gfx_v12_0_sw_fini, 5344 .hw_init = gfx_v12_0_hw_init, 5345 .hw_fini = gfx_v12_0_hw_fini, 5346 .suspend = gfx_v12_0_suspend, 5347 .resume = gfx_v12_0_resume, 5348 .is_idle = gfx_v12_0_is_idle, 5349 .wait_for_idle = gfx_v12_0_wait_for_idle, 5350 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5351 .set_powergating_state = gfx_v12_0_set_powergating_state, 5352 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5353 .dump_ip_state = gfx_v12_ip_dump, 5354 .print_ip_state = gfx_v12_ip_print, 5355 }; 5356 5357 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5358 .type = AMDGPU_RING_TYPE_GFX, 5359 .align_mask = 0xff, 5360 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5361 .support_64bit_ptrs = true, 5362 .secure_submission_supported = true, 5363 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5364 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5365 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5366 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5367 5 + /* COND_EXEC */ 5368 7 + /* PIPELINE_SYNC */ 5369 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5370 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5371 2 + /* VM_FLUSH */ 5372 8 + /* FENCE for VM_FLUSH */ 5373 5 + /* COND_EXEC */ 5374 7 + /* HDP_flush */ 5375 4 + /* VGT_flush */ 5376 31 + /* DE_META */ 5377 3 + /* CNTX_CTRL */ 5378 5 + /* HDP_INVL */ 5379 8 + 8 + /* FENCE x2 */ 5380 8 + /* gfx_v12_0_emit_mem_sync */ 5381 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5382 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5383 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5384 .emit_fence = gfx_v12_0_ring_emit_fence, 5385 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5386 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5387 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5388 .test_ring = gfx_v12_0_ring_test_ring, 5389 .test_ib = gfx_v12_0_ring_test_ib, 5390 .insert_nop = gfx_v12_ring_insert_nop, 5391 .pad_ib = amdgpu_ring_generic_pad_ib, 5392 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5393 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5394 .preempt_ib = amdgpu_gfx_ring_preempt_ib, 5395 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5396 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5397 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5398 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5399 .reset = gfx_v12_0_reset_kgq, 5400 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5401 .begin_use = gfx_v12_0_ring_begin_use, 5402 .end_use = gfx_v12_0_ring_end_use, 5403 }; 5404 5405 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5406 .type = AMDGPU_RING_TYPE_COMPUTE, 5407 .align_mask = 0xff, 5408 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5409 .support_64bit_ptrs = true, 5410 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5411 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5412 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5413 .emit_frame_size = 5414 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5415 5 + /* hdp invalidate */ 5416 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5417 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5418 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5419 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5420 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5421 8 + /* gfx_v12_0_emit_mem_sync */ 5422 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5423 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5424 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5425 .emit_fence = gfx_v12_0_ring_emit_fence, 5426 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5427 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5428 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5429 .test_ring = gfx_v12_0_ring_test_ring, 5430 .test_ib = gfx_v12_0_ring_test_ib, 5431 .insert_nop = gfx_v12_ring_insert_nop, 5432 .pad_ib = amdgpu_ring_generic_pad_ib, 5433 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5434 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5435 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5436 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5437 .reset = gfx_v12_0_reset_kcq, 5438 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5439 .begin_use = gfx_v12_0_ring_begin_use, 5440 .end_use = gfx_v12_0_ring_end_use, 5441 }; 5442 5443 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5444 .type = AMDGPU_RING_TYPE_KIQ, 5445 .align_mask = 0xff, 5446 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5447 .support_64bit_ptrs = true, 5448 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5449 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5450 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5451 .emit_frame_size = 5452 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5453 5 + /*hdp invalidate */ 5454 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5455 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5456 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5457 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5458 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5459 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5460 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5461 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5462 .test_ring = gfx_v12_0_ring_test_ring, 5463 .test_ib = gfx_v12_0_ring_test_ib, 5464 .insert_nop = amdgpu_ring_insert_nop, 5465 .pad_ib = amdgpu_ring_generic_pad_ib, 5466 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5467 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5468 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5469 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5470 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5471 }; 5472 5473 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5474 { 5475 int i; 5476 5477 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5478 5479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5480 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5481 5482 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5483 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5484 } 5485 5486 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5487 .set = gfx_v12_0_set_eop_interrupt_state, 5488 .process = gfx_v12_0_eop_irq, 5489 }; 5490 5491 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5492 .set = gfx_v12_0_set_priv_reg_fault_state, 5493 .process = gfx_v12_0_priv_reg_irq, 5494 }; 5495 5496 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5497 .set = gfx_v12_0_set_bad_op_fault_state, 5498 .process = gfx_v12_0_bad_op_irq, 5499 }; 5500 5501 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5502 .set = gfx_v12_0_set_priv_inst_fault_state, 5503 .process = gfx_v12_0_priv_inst_irq, 5504 }; 5505 5506 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5507 { 5508 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5509 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5510 5511 adev->gfx.priv_reg_irq.num_types = 1; 5512 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5513 5514 adev->gfx.bad_op_irq.num_types = 1; 5515 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5516 5517 adev->gfx.priv_inst_irq.num_types = 1; 5518 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5519 } 5520 5521 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5522 { 5523 if (adev->flags & AMD_IS_APU) 5524 adev->gfx.imu.mode = MISSION_MODE; 5525 else 5526 adev->gfx.imu.mode = DEBUG_MODE; 5527 5528 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5529 } 5530 5531 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5532 { 5533 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5534 } 5535 5536 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5537 { 5538 /* set gfx eng mqd */ 5539 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5540 sizeof(struct v12_gfx_mqd); 5541 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5542 gfx_v12_0_gfx_mqd_init; 5543 /* set compute eng mqd */ 5544 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5545 sizeof(struct v12_compute_mqd); 5546 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5547 gfx_v12_0_compute_mqd_init; 5548 } 5549 5550 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5551 u32 bitmap) 5552 { 5553 u32 data; 5554 5555 if (!bitmap) 5556 return; 5557 5558 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5559 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5560 5561 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5562 } 5563 5564 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5565 { 5566 u32 data, wgp_bitmask; 5567 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5568 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5569 5570 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5571 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5572 5573 wgp_bitmask = 5574 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5575 5576 return (~data) & wgp_bitmask; 5577 } 5578 5579 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5580 { 5581 u32 wgp_idx, wgp_active_bitmap; 5582 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5583 5584 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5585 cu_active_bitmap = 0; 5586 5587 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5588 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5589 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5590 if (wgp_active_bitmap & (1 << wgp_idx)) 5591 cu_active_bitmap |= cu_bitmap_per_wgp; 5592 } 5593 5594 return cu_active_bitmap; 5595 } 5596 5597 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5598 struct amdgpu_cu_info *cu_info) 5599 { 5600 int i, j, k, counter, active_cu_number = 0; 5601 u32 mask, bitmap; 5602 unsigned disable_masks[8 * 2]; 5603 5604 if (!adev || !cu_info) 5605 return -EINVAL; 5606 5607 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 5608 5609 mutex_lock(&adev->grbm_idx_mutex); 5610 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5611 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5612 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5613 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5614 continue; 5615 mask = 1; 5616 counter = 0; 5617 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5618 if (i < 8 && j < 2) 5619 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5620 adev, disable_masks[i * 2 + j]); 5621 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5622 5623 /** 5624 * GFX12 could support more than 4 SEs, while the bitmap 5625 * in cu_info struct is 4x4 and ioctl interface struct 5626 * drm_amdgpu_info_device should keep stable. 5627 * So we use last two columns of bitmap to store cu mask for 5628 * SEs 4 to 7, the layout of the bitmap is as below: 5629 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5630 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5631 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5632 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5633 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5634 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5635 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5636 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5637 */ 5638 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5639 5640 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5641 if (bitmap & mask) 5642 counter++; 5643 5644 mask <<= 1; 5645 } 5646 active_cu_number += counter; 5647 } 5648 } 5649 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5650 mutex_unlock(&adev->grbm_idx_mutex); 5651 5652 cu_info->number = active_cu_number; 5653 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5654 5655 return 0; 5656 } 5657 5658 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5659 .type = AMD_IP_BLOCK_TYPE_GFX, 5660 .major = 12, 5661 .minor = 0, 5662 .rev = 0, 5663 .funcs = &gfx_v12_0_ip_funcs, 5664 }; 5665