1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v11_0.h" 33 #include "soc21.h" 34 #include "nvd.h" 35 36 #include "gc/gc_11_0_0_offset.h" 37 #include "gc/gc_11_0_0_sh_mask.h" 38 #include "smuio/smuio_13_0_6_offset.h" 39 #include "smuio/smuio_13_0_6_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx11.h" 45 #include "v11_structs.h" 46 #include "gfx_v11_0.h" 47 #include "gfx_v11_0_cleaner_shader.h" 48 #include "gfx_v11_0_3.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 57 58 #define regCGTT_WD_CLK_CTRL 0x5086 59 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 62 #define regPC_CONFIG_CNTL_1 0x194d 63 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 64 65 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 67 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 68 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 69 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 70 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 71 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 72 73 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 74 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 75 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 76 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 77 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 78 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 79 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 80 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 81 82 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 104 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 105 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 106 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 107 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 108 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 109 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 110 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 111 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 112 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 113 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 114 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 115 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 116 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 118 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 120 121 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 122 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 124 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 155 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 156 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 157 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 158 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 159 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 160 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 161 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 162 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 163 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 164 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 165 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 166 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 167 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 168 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 169 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 179 /* cp header registers */ 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 188 /* SE status registers */ 189 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 190 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 191 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 192 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 193 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 194 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 195 }; 196 197 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 198 /* compute registers */ 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 238 /* cp header registers */ 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 }; 248 249 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 250 /* gfx queue registers */ 251 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 252 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 253 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 254 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 255 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 256 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 257 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 258 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 259 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 260 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 261 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 262 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 263 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 264 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 265 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 266 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 267 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 268 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 269 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 270 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 271 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 272 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 273 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 274 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 275 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 276 /* cp header registers */ 277 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 278 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 279 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 280 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 281 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 282 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 283 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 284 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 285 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 286 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 287 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 288 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 289 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 290 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 291 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 292 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 293 }; 294 295 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 296 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 297 }; 298 299 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 300 { 301 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 310 }; 311 312 #define DEFAULT_SH_MEM_CONFIG \ 313 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 314 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 315 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 316 317 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 318 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 319 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 320 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 321 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 322 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 323 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 324 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 325 struct amdgpu_cu_info *cu_info); 326 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 327 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 328 u32 sh_num, u32 instance, int xcc_id); 329 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 330 331 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 332 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 333 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 334 uint32_t val); 335 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 336 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 337 uint16_t pasid, uint32_t flush_type, 338 bool all_hub, uint8_t dst_sel); 339 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 340 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 341 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 342 bool enable); 343 344 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 345 { 346 struct amdgpu_device *adev = kiq_ring->adev; 347 u64 shader_mc_addr; 348 349 /* Cleaner shader MC address */ 350 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 351 352 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 353 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 354 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 355 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 356 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 357 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 358 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 359 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 360 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 361 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 362 } 363 364 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 365 struct amdgpu_ring *ring) 366 { 367 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 368 uint64_t wptr_addr = ring->wptr_gpu_addr; 369 uint32_t me = 0, eng_sel = 0; 370 371 switch (ring->funcs->type) { 372 case AMDGPU_RING_TYPE_COMPUTE: 373 me = 1; 374 eng_sel = 0; 375 break; 376 case AMDGPU_RING_TYPE_GFX: 377 me = 0; 378 eng_sel = 4; 379 break; 380 case AMDGPU_RING_TYPE_MES: 381 me = 2; 382 eng_sel = 5; 383 break; 384 default: 385 WARN_ON(1); 386 } 387 388 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 389 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 390 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 391 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 392 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 393 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 394 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 395 PACKET3_MAP_QUEUES_ME((me)) | 396 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 397 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 398 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 399 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 400 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 401 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 402 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 403 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 404 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 405 } 406 407 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 408 struct amdgpu_ring *ring, 409 enum amdgpu_unmap_queues_action action, 410 u64 gpu_addr, u64 seq) 411 { 412 struct amdgpu_device *adev = kiq_ring->adev; 413 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 414 415 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 416 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 417 return; 418 } 419 420 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 421 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 422 PACKET3_UNMAP_QUEUES_ACTION(action) | 423 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 424 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 425 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 426 amdgpu_ring_write(kiq_ring, 427 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 428 429 if (action == PREEMPT_QUEUES_NO_UNMAP) { 430 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 431 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 432 amdgpu_ring_write(kiq_ring, seq); 433 } else { 434 amdgpu_ring_write(kiq_ring, 0); 435 amdgpu_ring_write(kiq_ring, 0); 436 amdgpu_ring_write(kiq_ring, 0); 437 } 438 } 439 440 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 441 struct amdgpu_ring *ring, 442 u64 addr, 443 u64 seq) 444 { 445 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 446 447 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 448 amdgpu_ring_write(kiq_ring, 449 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 450 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 451 PACKET3_QUERY_STATUS_COMMAND(2)); 452 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 453 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 454 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 455 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 456 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 457 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 458 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 459 } 460 461 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 462 uint16_t pasid, uint32_t flush_type, 463 bool all_hub) 464 { 465 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 466 } 467 468 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 469 .kiq_set_resources = gfx11_kiq_set_resources, 470 .kiq_map_queues = gfx11_kiq_map_queues, 471 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 472 .kiq_query_status = gfx11_kiq_query_status, 473 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 474 .set_resources_size = 8, 475 .map_queues_size = 7, 476 .unmap_queues_size = 6, 477 .query_status_size = 7, 478 .invalidate_tlbs_size = 2, 479 }; 480 481 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 482 { 483 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 484 } 485 486 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 487 { 488 if (amdgpu_sriov_vf(adev)) 489 return; 490 491 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 492 case IP_VERSION(11, 0, 1): 493 case IP_VERSION(11, 0, 4): 494 soc15_program_register_sequence(adev, 495 golden_settings_gc_11_0_1, 496 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 497 break; 498 default: 499 break; 500 } 501 soc15_program_register_sequence(adev, 502 golden_settings_gc_11_0, 503 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 504 505 } 506 507 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 508 bool wc, uint32_t reg, uint32_t val) 509 { 510 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 511 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 512 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 513 amdgpu_ring_write(ring, reg); 514 amdgpu_ring_write(ring, 0); 515 amdgpu_ring_write(ring, val); 516 } 517 518 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 519 int mem_space, int opt, uint32_t addr0, 520 uint32_t addr1, uint32_t ref, uint32_t mask, 521 uint32_t inv) 522 { 523 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 524 amdgpu_ring_write(ring, 525 /* memory (1) or register (0) */ 526 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 527 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 528 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 529 WAIT_REG_MEM_ENGINE(eng_sel))); 530 531 if (mem_space) 532 BUG_ON(addr0 & 0x3); /* Dword align */ 533 amdgpu_ring_write(ring, addr0); 534 amdgpu_ring_write(ring, addr1); 535 amdgpu_ring_write(ring, ref); 536 amdgpu_ring_write(ring, mask); 537 amdgpu_ring_write(ring, inv); /* poll interval */ 538 } 539 540 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 541 { 542 /* Header itself is a NOP packet */ 543 if (num_nop == 1) { 544 amdgpu_ring_write(ring, ring->funcs->nop); 545 return; 546 } 547 548 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 549 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 550 551 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 552 amdgpu_ring_insert_nop(ring, num_nop - 1); 553 } 554 555 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 556 { 557 struct amdgpu_device *adev = ring->adev; 558 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 559 uint32_t tmp = 0; 560 unsigned i; 561 int r; 562 563 WREG32(scratch, 0xCAFEDEAD); 564 r = amdgpu_ring_alloc(ring, 5); 565 if (r) { 566 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 567 ring->idx, r); 568 return r; 569 } 570 571 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 572 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 573 } else { 574 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 575 amdgpu_ring_write(ring, scratch - 576 PACKET3_SET_UCONFIG_REG_START); 577 amdgpu_ring_write(ring, 0xDEADBEEF); 578 } 579 amdgpu_ring_commit(ring); 580 581 for (i = 0; i < adev->usec_timeout; i++) { 582 tmp = RREG32(scratch); 583 if (tmp == 0xDEADBEEF) 584 break; 585 if (amdgpu_emu_mode == 1) 586 msleep(1); 587 else 588 udelay(1); 589 } 590 591 if (i >= adev->usec_timeout) 592 r = -ETIMEDOUT; 593 return r; 594 } 595 596 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 597 { 598 struct amdgpu_device *adev = ring->adev; 599 struct amdgpu_ib ib; 600 struct dma_fence *f = NULL; 601 unsigned index; 602 uint64_t gpu_addr; 603 volatile uint32_t *cpu_ptr; 604 long r; 605 606 /* MES KIQ fw hasn't indirect buffer support for now */ 607 if (adev->enable_mes_kiq && 608 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 609 return 0; 610 611 memset(&ib, 0, sizeof(ib)); 612 613 if (ring->is_mes_queue) { 614 uint32_t padding, offset; 615 616 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 617 padding = amdgpu_mes_ctx_get_offs(ring, 618 AMDGPU_MES_CTX_PADDING_OFFS); 619 620 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 621 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 622 623 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 624 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 625 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 626 } else { 627 r = amdgpu_device_wb_get(adev, &index); 628 if (r) 629 return r; 630 631 gpu_addr = adev->wb.gpu_addr + (index * 4); 632 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 633 cpu_ptr = &adev->wb.wb[index]; 634 635 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 636 if (r) { 637 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 638 goto err1; 639 } 640 } 641 642 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 643 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 644 ib.ptr[2] = lower_32_bits(gpu_addr); 645 ib.ptr[3] = upper_32_bits(gpu_addr); 646 ib.ptr[4] = 0xDEADBEEF; 647 ib.length_dw = 5; 648 649 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 650 if (r) 651 goto err2; 652 653 r = dma_fence_wait_timeout(f, false, timeout); 654 if (r == 0) { 655 r = -ETIMEDOUT; 656 goto err2; 657 } else if (r < 0) { 658 goto err2; 659 } 660 661 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 662 r = 0; 663 else 664 r = -EINVAL; 665 err2: 666 if (!ring->is_mes_queue) 667 amdgpu_ib_free(&ib, NULL); 668 dma_fence_put(f); 669 err1: 670 if (!ring->is_mes_queue) 671 amdgpu_device_wb_free(adev, index); 672 return r; 673 } 674 675 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 676 { 677 amdgpu_ucode_release(&adev->gfx.pfp_fw); 678 amdgpu_ucode_release(&adev->gfx.me_fw); 679 amdgpu_ucode_release(&adev->gfx.rlc_fw); 680 amdgpu_ucode_release(&adev->gfx.mec_fw); 681 682 kfree(adev->gfx.rlc.register_list_format); 683 } 684 685 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 686 { 687 const struct psp_firmware_header_v1_0 *toc_hdr; 688 int err = 0; 689 690 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 691 AMDGPU_UCODE_REQUIRED, 692 "amdgpu/%s_toc.bin", ucode_prefix); 693 if (err) 694 goto out; 695 696 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 697 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 698 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 699 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 700 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 701 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 702 return 0; 703 out: 704 amdgpu_ucode_release(&adev->psp.toc_fw); 705 return err; 706 } 707 708 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 709 { 710 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 711 case IP_VERSION(11, 0, 0): 712 case IP_VERSION(11, 0, 2): 713 case IP_VERSION(11, 0, 3): 714 if ((adev->gfx.me_fw_version >= 1505) && 715 (adev->gfx.pfp_fw_version >= 1600) && 716 (adev->gfx.mec_fw_version >= 512)) { 717 if (amdgpu_sriov_vf(adev)) 718 adev->gfx.cp_gfx_shadow = true; 719 else 720 adev->gfx.cp_gfx_shadow = false; 721 } 722 break; 723 default: 724 adev->gfx.cp_gfx_shadow = false; 725 break; 726 } 727 } 728 729 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 730 { 731 char ucode_prefix[25]; 732 int err; 733 const struct rlc_firmware_header_v2_0 *rlc_hdr; 734 uint16_t version_major; 735 uint16_t version_minor; 736 737 DRM_DEBUG("\n"); 738 739 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 740 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 741 AMDGPU_UCODE_REQUIRED, 742 "amdgpu/%s_pfp.bin", ucode_prefix); 743 if (err) 744 goto out; 745 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 746 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 747 (union amdgpu_firmware_header *) 748 adev->gfx.pfp_fw->data, 2, 0); 749 if (adev->gfx.rs64_enable) { 750 dev_info(adev->dev, "CP RS64 enable\n"); 751 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 752 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 753 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 754 } else { 755 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 756 } 757 758 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 759 AMDGPU_UCODE_REQUIRED, 760 "amdgpu/%s_me.bin", ucode_prefix); 761 if (err) 762 goto out; 763 if (adev->gfx.rs64_enable) { 764 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 765 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 766 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 767 } else { 768 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 769 } 770 771 if (!amdgpu_sriov_vf(adev)) { 772 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 773 adev->pdev->revision == 0xCE) 774 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 775 AMDGPU_UCODE_REQUIRED, 776 "amdgpu/gc_11_0_0_rlc_1.bin"); 777 else 778 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 779 AMDGPU_UCODE_REQUIRED, 780 "amdgpu/%s_rlc.bin", ucode_prefix); 781 if (err) 782 goto out; 783 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 784 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 785 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 786 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 787 if (err) 788 goto out; 789 } 790 791 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 792 AMDGPU_UCODE_REQUIRED, 793 "amdgpu/%s_mec.bin", ucode_prefix); 794 if (err) 795 goto out; 796 if (adev->gfx.rs64_enable) { 797 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 798 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 799 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 800 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 801 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 802 } else { 803 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 804 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 805 } 806 807 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 808 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 809 810 /* only one MEC for gfx 11.0.0. */ 811 adev->gfx.mec2_fw = NULL; 812 813 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 814 815 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 816 err = adev->gfx.imu.funcs->init_microcode(adev); 817 if (err) 818 DRM_ERROR("Failed to init imu firmware!\n"); 819 return err; 820 } 821 822 out: 823 if (err) { 824 amdgpu_ucode_release(&adev->gfx.pfp_fw); 825 amdgpu_ucode_release(&adev->gfx.me_fw); 826 amdgpu_ucode_release(&adev->gfx.rlc_fw); 827 amdgpu_ucode_release(&adev->gfx.mec_fw); 828 } 829 830 return err; 831 } 832 833 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 834 { 835 u32 count = 0; 836 const struct cs_section_def *sect = NULL; 837 const struct cs_extent_def *ext = NULL; 838 839 /* begin clear state */ 840 count += 2; 841 /* context control state */ 842 count += 3; 843 844 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 845 for (ext = sect->section; ext->extent != NULL; ++ext) { 846 if (sect->id == SECT_CONTEXT) 847 count += 2 + ext->reg_count; 848 else 849 return 0; 850 } 851 } 852 853 /* set PA_SC_TILE_STEERING_OVERRIDE */ 854 count += 3; 855 /* end clear state */ 856 count += 2; 857 /* clear state */ 858 count += 2; 859 860 return count; 861 } 862 863 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 864 volatile u32 *buffer) 865 { 866 u32 count = 0, i; 867 const struct cs_section_def *sect = NULL; 868 const struct cs_extent_def *ext = NULL; 869 int ctx_reg_offset; 870 871 if (adev->gfx.rlc.cs_data == NULL) 872 return; 873 if (buffer == NULL) 874 return; 875 876 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 877 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 878 879 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 880 buffer[count++] = cpu_to_le32(0x80000000); 881 buffer[count++] = cpu_to_le32(0x80000000); 882 883 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 884 for (ext = sect->section; ext->extent != NULL; ++ext) { 885 if (sect->id == SECT_CONTEXT) { 886 buffer[count++] = 887 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 888 buffer[count++] = cpu_to_le32(ext->reg_index - 889 PACKET3_SET_CONTEXT_REG_START); 890 for (i = 0; i < ext->reg_count; i++) 891 buffer[count++] = cpu_to_le32(ext->extent[i]); 892 } 893 } 894 } 895 896 ctx_reg_offset = 897 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 898 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 899 buffer[count++] = cpu_to_le32(ctx_reg_offset); 900 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 901 902 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 903 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 904 905 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 906 buffer[count++] = cpu_to_le32(0); 907 } 908 909 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 910 { 911 /* clear state block */ 912 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 913 &adev->gfx.rlc.clear_state_gpu_addr, 914 (void **)&adev->gfx.rlc.cs_ptr); 915 916 /* jump table block */ 917 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 918 &adev->gfx.rlc.cp_table_gpu_addr, 919 (void **)&adev->gfx.rlc.cp_table_ptr); 920 } 921 922 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 923 { 924 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 925 926 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 927 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 928 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 929 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 930 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 931 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 932 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 933 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 934 adev->gfx.rlc.rlcg_reg_access_supported = true; 935 } 936 937 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 938 { 939 const struct cs_section_def *cs_data; 940 int r; 941 942 adev->gfx.rlc.cs_data = gfx11_cs_data; 943 944 cs_data = adev->gfx.rlc.cs_data; 945 946 if (cs_data) { 947 /* init clear state block */ 948 r = amdgpu_gfx_rlc_init_csb(adev); 949 if (r) 950 return r; 951 } 952 953 /* init spm vmid with 0xf */ 954 if (adev->gfx.rlc.funcs->update_spm_vmid) 955 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 956 957 return 0; 958 } 959 960 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 961 { 962 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 963 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 964 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 965 } 966 967 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 968 { 969 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 970 971 amdgpu_gfx_graphics_queue_acquire(adev); 972 } 973 974 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 975 { 976 int r; 977 u32 *hpd; 978 size_t mec_hpd_size; 979 980 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 981 982 /* take ownership of the relevant compute queues */ 983 amdgpu_gfx_compute_queue_acquire(adev); 984 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 985 986 if (mec_hpd_size) { 987 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 988 AMDGPU_GEM_DOMAIN_GTT, 989 &adev->gfx.mec.hpd_eop_obj, 990 &adev->gfx.mec.hpd_eop_gpu_addr, 991 (void **)&hpd); 992 if (r) { 993 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 994 gfx_v11_0_mec_fini(adev); 995 return r; 996 } 997 998 memset(hpd, 0, mec_hpd_size); 999 1000 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1001 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1008 { 1009 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1010 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1011 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1012 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1013 } 1014 1015 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1016 uint32_t thread, uint32_t regno, 1017 uint32_t num, uint32_t *out) 1018 { 1019 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1020 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1021 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1022 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1023 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1024 while (num--) 1025 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1026 } 1027 1028 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1029 { 1030 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1031 * field when performing a select_se_sh so it should be 1032 * zero here */ 1033 WARN_ON(simd != 0); 1034 1035 /* type 3 wave data */ 1036 dst[(*no_fields)++] = 3; 1037 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1038 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1039 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1040 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1041 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1042 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1043 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1044 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1045 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1046 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1047 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1048 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1049 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1050 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1051 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1052 } 1053 1054 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1055 uint32_t wave, uint32_t start, 1056 uint32_t size, uint32_t *dst) 1057 { 1058 WARN_ON(simd != 0); 1059 1060 wave_read_regs( 1061 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1062 dst); 1063 } 1064 1065 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1066 uint32_t wave, uint32_t thread, 1067 uint32_t start, uint32_t size, 1068 uint32_t *dst) 1069 { 1070 wave_read_regs( 1071 adev, wave, thread, 1072 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1073 } 1074 1075 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1076 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1077 { 1078 soc21_grbm_select(adev, me, pipe, q, vm); 1079 } 1080 1081 /* all sizes are in bytes */ 1082 #define MQD_SHADOW_BASE_SIZE 73728 1083 #define MQD_SHADOW_BASE_ALIGNMENT 256 1084 #define MQD_FWWORKAREA_SIZE 484 1085 #define MQD_FWWORKAREA_ALIGNMENT 256 1086 1087 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1088 struct amdgpu_gfx_shadow_info *shadow_info) 1089 { 1090 if (adev->gfx.cp_gfx_shadow) { 1091 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1092 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1093 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1094 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1095 return 0; 1096 } else { 1097 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1098 return -ENOTSUPP; 1099 } 1100 } 1101 1102 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1103 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1104 .select_se_sh = &gfx_v11_0_select_se_sh, 1105 .read_wave_data = &gfx_v11_0_read_wave_data, 1106 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1107 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1108 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1109 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1110 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1111 }; 1112 1113 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1114 { 1115 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1116 case IP_VERSION(11, 0, 0): 1117 case IP_VERSION(11, 0, 2): 1118 adev->gfx.config.max_hw_contexts = 8; 1119 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1120 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1121 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1122 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1123 break; 1124 case IP_VERSION(11, 0, 3): 1125 adev->gfx.ras = &gfx_v11_0_3_ras; 1126 adev->gfx.config.max_hw_contexts = 8; 1127 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1128 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1129 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1130 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1131 break; 1132 case IP_VERSION(11, 0, 1): 1133 case IP_VERSION(11, 0, 4): 1134 case IP_VERSION(11, 5, 0): 1135 case IP_VERSION(11, 5, 1): 1136 case IP_VERSION(11, 5, 2): 1137 case IP_VERSION(11, 5, 3): 1138 adev->gfx.config.max_hw_contexts = 8; 1139 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1140 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1141 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1142 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1143 break; 1144 default: 1145 BUG(); 1146 break; 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1153 int me, int pipe, int queue) 1154 { 1155 struct amdgpu_ring *ring; 1156 unsigned int irq_type; 1157 unsigned int hw_prio; 1158 1159 ring = &adev->gfx.gfx_ring[ring_id]; 1160 1161 ring->me = me; 1162 ring->pipe = pipe; 1163 ring->queue = queue; 1164 1165 ring->ring_obj = NULL; 1166 ring->use_doorbell = true; 1167 1168 if (!ring_id) 1169 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1170 else 1171 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1172 ring->vm_hub = AMDGPU_GFXHUB(0); 1173 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1174 1175 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1176 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1177 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1178 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1179 hw_prio, NULL); 1180 } 1181 1182 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1183 int mec, int pipe, int queue) 1184 { 1185 int r; 1186 unsigned irq_type; 1187 struct amdgpu_ring *ring; 1188 unsigned int hw_prio; 1189 1190 ring = &adev->gfx.compute_ring[ring_id]; 1191 1192 /* mec0 is me1 */ 1193 ring->me = mec + 1; 1194 ring->pipe = pipe; 1195 ring->queue = queue; 1196 1197 ring->ring_obj = NULL; 1198 ring->use_doorbell = true; 1199 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1200 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1201 + (ring_id * GFX11_MEC_HPD_SIZE); 1202 ring->vm_hub = AMDGPU_GFXHUB(0); 1203 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1204 1205 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1206 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1207 + ring->pipe; 1208 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1209 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1210 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1211 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1212 hw_prio, NULL); 1213 if (r) 1214 return r; 1215 1216 return 0; 1217 } 1218 1219 static struct { 1220 SOC21_FIRMWARE_ID id; 1221 unsigned int offset; 1222 unsigned int size; 1223 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1224 1225 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1226 { 1227 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1228 1229 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1230 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1231 rlc_autoload_info[ucode->id].id = ucode->id; 1232 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1233 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1234 1235 ucode++; 1236 } 1237 } 1238 1239 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1240 { 1241 uint32_t total_size = 0; 1242 SOC21_FIRMWARE_ID id; 1243 1244 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1245 1246 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1247 total_size += rlc_autoload_info[id].size; 1248 1249 /* In case the offset in rlc toc ucode is aligned */ 1250 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1251 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1252 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1253 1254 return total_size; 1255 } 1256 1257 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1258 { 1259 int r; 1260 uint32_t total_size; 1261 1262 total_size = gfx_v11_0_calc_toc_total_size(adev); 1263 1264 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1265 AMDGPU_GEM_DOMAIN_VRAM | 1266 AMDGPU_GEM_DOMAIN_GTT, 1267 &adev->gfx.rlc.rlc_autoload_bo, 1268 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1269 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1270 1271 if (r) { 1272 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1273 return r; 1274 } 1275 1276 return 0; 1277 } 1278 1279 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1280 SOC21_FIRMWARE_ID id, 1281 const void *fw_data, 1282 uint32_t fw_size, 1283 uint32_t *fw_autoload_mask) 1284 { 1285 uint32_t toc_offset; 1286 uint32_t toc_fw_size; 1287 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1288 1289 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1290 return; 1291 1292 toc_offset = rlc_autoload_info[id].offset; 1293 toc_fw_size = rlc_autoload_info[id].size; 1294 1295 if (fw_size == 0) 1296 fw_size = toc_fw_size; 1297 1298 if (fw_size > toc_fw_size) 1299 fw_size = toc_fw_size; 1300 1301 memcpy(ptr + toc_offset, fw_data, fw_size); 1302 1303 if (fw_size < toc_fw_size) 1304 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1305 1306 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1307 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1308 } 1309 1310 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1311 uint32_t *fw_autoload_mask) 1312 { 1313 void *data; 1314 uint32_t size; 1315 uint64_t *toc_ptr; 1316 1317 *(uint64_t *)fw_autoload_mask |= 0x1; 1318 1319 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1320 1321 data = adev->psp.toc.start_addr; 1322 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1323 1324 toc_ptr = (uint64_t *)data + size / 8 - 1; 1325 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1326 1327 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1328 data, size, fw_autoload_mask); 1329 } 1330 1331 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1332 uint32_t *fw_autoload_mask) 1333 { 1334 const __le32 *fw_data; 1335 uint32_t fw_size; 1336 const struct gfx_firmware_header_v1_0 *cp_hdr; 1337 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1338 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1339 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1340 uint16_t version_major, version_minor; 1341 1342 if (adev->gfx.rs64_enable) { 1343 /* pfp ucode */ 1344 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1345 adev->gfx.pfp_fw->data; 1346 /* instruction */ 1347 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1348 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1349 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1350 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1351 fw_data, fw_size, fw_autoload_mask); 1352 /* data */ 1353 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1354 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1355 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1356 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1357 fw_data, fw_size, fw_autoload_mask); 1358 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1359 fw_data, fw_size, fw_autoload_mask); 1360 /* me ucode */ 1361 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1362 adev->gfx.me_fw->data; 1363 /* instruction */ 1364 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1365 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1366 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1367 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1368 fw_data, fw_size, fw_autoload_mask); 1369 /* data */ 1370 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1371 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1372 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1373 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1374 fw_data, fw_size, fw_autoload_mask); 1375 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1376 fw_data, fw_size, fw_autoload_mask); 1377 /* mec ucode */ 1378 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1379 adev->gfx.mec_fw->data; 1380 /* instruction */ 1381 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1382 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1383 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1384 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1385 fw_data, fw_size, fw_autoload_mask); 1386 /* data */ 1387 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1388 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1389 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1391 fw_data, fw_size, fw_autoload_mask); 1392 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1393 fw_data, fw_size, fw_autoload_mask); 1394 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1395 fw_data, fw_size, fw_autoload_mask); 1396 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1397 fw_data, fw_size, fw_autoload_mask); 1398 } else { 1399 /* pfp ucode */ 1400 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1401 adev->gfx.pfp_fw->data; 1402 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1403 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1404 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1405 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1406 fw_data, fw_size, fw_autoload_mask); 1407 1408 /* me ucode */ 1409 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1410 adev->gfx.me_fw->data; 1411 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1412 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1413 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1414 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1415 fw_data, fw_size, fw_autoload_mask); 1416 1417 /* mec ucode */ 1418 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1419 adev->gfx.mec_fw->data; 1420 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1421 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1422 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1423 cp_hdr->jt_size * 4; 1424 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1425 fw_data, fw_size, fw_autoload_mask); 1426 } 1427 1428 /* rlc ucode */ 1429 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1430 adev->gfx.rlc_fw->data; 1431 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1432 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1433 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1434 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1435 fw_data, fw_size, fw_autoload_mask); 1436 1437 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1438 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1439 if (version_major == 2) { 1440 if (version_minor >= 2) { 1441 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1442 1443 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1444 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1445 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1446 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1447 fw_data, fw_size, fw_autoload_mask); 1448 1449 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1450 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1451 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1452 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1453 fw_data, fw_size, fw_autoload_mask); 1454 } 1455 } 1456 } 1457 1458 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1459 uint32_t *fw_autoload_mask) 1460 { 1461 const __le32 *fw_data; 1462 uint32_t fw_size; 1463 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1464 1465 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1466 adev->sdma.instance[0].fw->data; 1467 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1468 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1469 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1470 1471 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1472 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1473 1474 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1475 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1476 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1477 1478 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1479 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1480 } 1481 1482 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1483 uint32_t *fw_autoload_mask) 1484 { 1485 const __le32 *fw_data; 1486 unsigned fw_size; 1487 const struct mes_firmware_header_v1_0 *mes_hdr; 1488 int pipe, ucode_id, data_id; 1489 1490 for (pipe = 0; pipe < 2; pipe++) { 1491 if (pipe==0) { 1492 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1493 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1494 } else { 1495 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1496 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1497 } 1498 1499 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1500 adev->mes.fw[pipe]->data; 1501 1502 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1503 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1504 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1505 1506 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1507 ucode_id, fw_data, fw_size, fw_autoload_mask); 1508 1509 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1510 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1511 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1512 1513 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1514 data_id, fw_data, fw_size, fw_autoload_mask); 1515 } 1516 } 1517 1518 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1519 { 1520 uint32_t rlc_g_offset, rlc_g_size; 1521 uint64_t gpu_addr; 1522 uint32_t autoload_fw_id[2]; 1523 1524 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1525 1526 /* RLC autoload sequence 2: copy ucode */ 1527 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1528 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1529 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1530 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1531 1532 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1533 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1534 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1535 1536 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1537 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1538 1539 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1540 1541 /* RLC autoload sequence 3: load IMU fw */ 1542 if (adev->gfx.imu.funcs->load_microcode) 1543 adev->gfx.imu.funcs->load_microcode(adev); 1544 /* RLC autoload sequence 4 init IMU fw */ 1545 if (adev->gfx.imu.funcs->setup_imu) 1546 adev->gfx.imu.funcs->setup_imu(adev); 1547 if (adev->gfx.imu.funcs->start_imu) 1548 adev->gfx.imu.funcs->start_imu(adev); 1549 1550 /* RLC autoload sequence 5 disable gpa mode */ 1551 gfx_v11_0_disable_gpa_mode(adev); 1552 1553 return 0; 1554 } 1555 1556 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1557 { 1558 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1559 uint32_t *ptr; 1560 uint32_t inst; 1561 1562 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1563 if (!ptr) { 1564 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1565 adev->gfx.ip_dump_core = NULL; 1566 } else { 1567 adev->gfx.ip_dump_core = ptr; 1568 } 1569 1570 /* Allocate memory for compute queue registers for all the instances */ 1571 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1572 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1573 adev->gfx.mec.num_queue_per_pipe; 1574 1575 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1576 if (!ptr) { 1577 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1578 adev->gfx.ip_dump_compute_queues = NULL; 1579 } else { 1580 adev->gfx.ip_dump_compute_queues = ptr; 1581 } 1582 1583 /* Allocate memory for gfx queue registers for all the instances */ 1584 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1585 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1586 adev->gfx.me.num_queue_per_pipe; 1587 1588 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1589 if (!ptr) { 1590 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1591 adev->gfx.ip_dump_gfx_queues = NULL; 1592 } else { 1593 adev->gfx.ip_dump_gfx_queues = ptr; 1594 } 1595 } 1596 1597 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1598 { 1599 int i, j, k, r, ring_id = 0; 1600 int xcc_id = 0; 1601 struct amdgpu_device *adev = ip_block->adev; 1602 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1603 1604 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1605 1606 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1607 case IP_VERSION(11, 0, 0): 1608 case IP_VERSION(11, 0, 2): 1609 case IP_VERSION(11, 0, 3): 1610 adev->gfx.me.num_me = 1; 1611 adev->gfx.me.num_pipe_per_me = 1; 1612 adev->gfx.me.num_queue_per_pipe = 2; 1613 adev->gfx.mec.num_mec = 1; 1614 adev->gfx.mec.num_pipe_per_mec = 4; 1615 adev->gfx.mec.num_queue_per_pipe = 4; 1616 break; 1617 case IP_VERSION(11, 0, 1): 1618 case IP_VERSION(11, 0, 4): 1619 case IP_VERSION(11, 5, 0): 1620 case IP_VERSION(11, 5, 1): 1621 case IP_VERSION(11, 5, 2): 1622 case IP_VERSION(11, 5, 3): 1623 adev->gfx.me.num_me = 1; 1624 adev->gfx.me.num_pipe_per_me = 1; 1625 adev->gfx.me.num_queue_per_pipe = 2; 1626 adev->gfx.mec.num_mec = 1; 1627 adev->gfx.mec.num_pipe_per_mec = 4; 1628 adev->gfx.mec.num_queue_per_pipe = 4; 1629 break; 1630 default: 1631 adev->gfx.me.num_me = 1; 1632 adev->gfx.me.num_pipe_per_me = 1; 1633 adev->gfx.me.num_queue_per_pipe = 1; 1634 adev->gfx.mec.num_mec = 1; 1635 adev->gfx.mec.num_pipe_per_mec = 4; 1636 adev->gfx.mec.num_queue_per_pipe = 8; 1637 break; 1638 } 1639 1640 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1641 case IP_VERSION(11, 0, 0): 1642 case IP_VERSION(11, 0, 2): 1643 case IP_VERSION(11, 0, 3): 1644 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1645 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1646 if (adev->gfx.me_fw_version >= 2280 && 1647 adev->gfx.pfp_fw_version >= 2370 && 1648 adev->gfx.mec_fw_version >= 2450 && 1649 adev->mes.fw_version[0] >= 99) { 1650 adev->gfx.enable_cleaner_shader = true; 1651 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1652 if (r) { 1653 adev->gfx.enable_cleaner_shader = false; 1654 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1655 } 1656 } 1657 break; 1658 case IP_VERSION(11, 5, 0): 1659 case IP_VERSION(11, 5, 1): 1660 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1661 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1662 if (adev->gfx.mec_fw_version >= 26 && 1663 adev->mes.fw_version[0] >= 114) { 1664 adev->gfx.enable_cleaner_shader = true; 1665 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1666 if (r) { 1667 adev->gfx.enable_cleaner_shader = false; 1668 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1669 } 1670 } 1671 break; 1672 default: 1673 adev->gfx.enable_cleaner_shader = false; 1674 break; 1675 } 1676 1677 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1678 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1679 amdgpu_sriov_is_pp_one_vf(adev)) 1680 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1681 1682 /* EOP Event */ 1683 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1684 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1685 &adev->gfx.eop_irq); 1686 if (r) 1687 return r; 1688 1689 /* Bad opcode Event */ 1690 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1691 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1692 &adev->gfx.bad_op_irq); 1693 if (r) 1694 return r; 1695 1696 /* Privileged reg */ 1697 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1698 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1699 &adev->gfx.priv_reg_irq); 1700 if (r) 1701 return r; 1702 1703 /* Privileged inst */ 1704 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1705 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1706 &adev->gfx.priv_inst_irq); 1707 if (r) 1708 return r; 1709 1710 /* FED error */ 1711 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1712 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1713 &adev->gfx.rlc_gc_fed_irq); 1714 if (r) 1715 return r; 1716 1717 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1718 1719 gfx_v11_0_me_init(adev); 1720 1721 r = gfx_v11_0_rlc_init(adev); 1722 if (r) { 1723 DRM_ERROR("Failed to init rlc BOs!\n"); 1724 return r; 1725 } 1726 1727 r = gfx_v11_0_mec_init(adev); 1728 if (r) { 1729 DRM_ERROR("Failed to init MEC BOs!\n"); 1730 return r; 1731 } 1732 1733 /* set up the gfx ring */ 1734 for (i = 0; i < adev->gfx.me.num_me; i++) { 1735 for (j = 0; j < num_queue_per_pipe; j++) { 1736 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1737 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1738 continue; 1739 1740 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1741 i, k, j); 1742 if (r) 1743 return r; 1744 ring_id++; 1745 } 1746 } 1747 } 1748 1749 ring_id = 0; 1750 /* set up the compute queues - allocate horizontally across pipes */ 1751 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1752 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1753 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1754 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1755 k, j)) 1756 continue; 1757 1758 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1759 i, k, j); 1760 if (r) 1761 return r; 1762 1763 ring_id++; 1764 } 1765 } 1766 } 1767 1768 adev->gfx.gfx_supported_reset = 1769 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1770 adev->gfx.compute_supported_reset = 1771 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1772 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1773 case IP_VERSION(11, 0, 0): 1774 case IP_VERSION(11, 0, 2): 1775 case IP_VERSION(11, 0, 3): 1776 if ((adev->gfx.me_fw_version >= 2280) && 1777 (adev->gfx.mec_fw_version >= 2410)) { 1778 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1779 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1780 } 1781 break; 1782 default: 1783 break; 1784 } 1785 1786 if (!adev->enable_mes_kiq) { 1787 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1788 if (r) { 1789 DRM_ERROR("Failed to init KIQ BOs!\n"); 1790 return r; 1791 } 1792 1793 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1794 if (r) 1795 return r; 1796 } 1797 1798 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1799 if (r) 1800 return r; 1801 1802 /* allocate visible FB for rlc auto-loading fw */ 1803 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1804 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1805 if (r) 1806 return r; 1807 } 1808 1809 r = gfx_v11_0_gpu_early_init(adev); 1810 if (r) 1811 return r; 1812 1813 if (amdgpu_gfx_ras_sw_init(adev)) { 1814 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1815 return -EINVAL; 1816 } 1817 1818 gfx_v11_0_alloc_ip_dump(adev); 1819 1820 r = amdgpu_gfx_sysfs_init(adev); 1821 if (r) 1822 return r; 1823 1824 return 0; 1825 } 1826 1827 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1828 { 1829 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1830 &adev->gfx.pfp.pfp_fw_gpu_addr, 1831 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1832 1833 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1834 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1835 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1836 } 1837 1838 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1839 { 1840 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1841 &adev->gfx.me.me_fw_gpu_addr, 1842 (void **)&adev->gfx.me.me_fw_ptr); 1843 1844 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1845 &adev->gfx.me.me_fw_data_gpu_addr, 1846 (void **)&adev->gfx.me.me_fw_data_ptr); 1847 } 1848 1849 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1850 { 1851 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1852 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1853 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1854 } 1855 1856 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1857 { 1858 int i; 1859 struct amdgpu_device *adev = ip_block->adev; 1860 1861 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1862 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1863 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1864 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1865 1866 amdgpu_gfx_mqd_sw_fini(adev, 0); 1867 1868 if (!adev->enable_mes_kiq) { 1869 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1870 amdgpu_gfx_kiq_fini(adev, 0); 1871 } 1872 1873 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1874 1875 gfx_v11_0_pfp_fini(adev); 1876 gfx_v11_0_me_fini(adev); 1877 gfx_v11_0_rlc_fini(adev); 1878 gfx_v11_0_mec_fini(adev); 1879 1880 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1881 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1882 1883 gfx_v11_0_free_microcode(adev); 1884 1885 amdgpu_gfx_sysfs_fini(adev); 1886 1887 kfree(adev->gfx.ip_dump_core); 1888 kfree(adev->gfx.ip_dump_compute_queues); 1889 kfree(adev->gfx.ip_dump_gfx_queues); 1890 1891 return 0; 1892 } 1893 1894 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1895 u32 sh_num, u32 instance, int xcc_id) 1896 { 1897 u32 data; 1898 1899 if (instance == 0xffffffff) 1900 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1901 INSTANCE_BROADCAST_WRITES, 1); 1902 else 1903 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1904 instance); 1905 1906 if (se_num == 0xffffffff) 1907 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1908 1); 1909 else 1910 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1911 1912 if (sh_num == 0xffffffff) 1913 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1914 1); 1915 else 1916 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1917 1918 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1919 } 1920 1921 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1922 { 1923 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1924 1925 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1926 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1927 CC_GC_SA_UNIT_DISABLE, 1928 SA_DISABLE); 1929 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1930 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1931 GC_USER_SA_UNIT_DISABLE, 1932 SA_DISABLE); 1933 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1934 adev->gfx.config.max_shader_engines); 1935 1936 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1937 } 1938 1939 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1940 { 1941 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1942 u32 rb_mask; 1943 1944 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1945 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1946 CC_RB_BACKEND_DISABLE, 1947 BACKEND_DISABLE); 1948 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1949 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1950 GC_USER_RB_BACKEND_DISABLE, 1951 BACKEND_DISABLE); 1952 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1953 adev->gfx.config.max_shader_engines); 1954 1955 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1956 } 1957 1958 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1959 { 1960 u32 rb_bitmap_per_sa; 1961 u32 rb_bitmap_width_per_sa; 1962 u32 max_sa; 1963 u32 active_sa_bitmap; 1964 u32 global_active_rb_bitmap; 1965 u32 active_rb_bitmap = 0; 1966 u32 i; 1967 1968 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1969 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1970 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1971 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1972 1973 /* generate active rb bitmap according to active sa bitmap */ 1974 max_sa = adev->gfx.config.max_shader_engines * 1975 adev->gfx.config.max_sh_per_se; 1976 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1977 adev->gfx.config.max_sh_per_se; 1978 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1979 1980 for (i = 0; i < max_sa; i++) { 1981 if (active_sa_bitmap & (1 << i)) 1982 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1983 } 1984 1985 active_rb_bitmap &= global_active_rb_bitmap; 1986 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1987 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1988 } 1989 1990 #define DEFAULT_SH_MEM_BASES (0x6000) 1991 #define LDS_APP_BASE 0x1 1992 #define SCRATCH_APP_BASE 0x2 1993 1994 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1995 { 1996 int i; 1997 uint32_t sh_mem_bases; 1998 uint32_t data; 1999 2000 /* 2001 * Configure apertures: 2002 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2003 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2004 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2005 */ 2006 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 2007 SCRATCH_APP_BASE; 2008 2009 mutex_lock(&adev->srbm_mutex); 2010 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2011 soc21_grbm_select(adev, 0, 0, 0, i); 2012 /* CP and shaders */ 2013 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2014 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 2015 2016 /* Enable trap for each kfd vmid. */ 2017 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 2018 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 2019 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 2020 } 2021 soc21_grbm_select(adev, 0, 0, 0, 0); 2022 mutex_unlock(&adev->srbm_mutex); 2023 2024 /* 2025 * Initialize all compute VMIDs to have no GDS, GWS, or OA 2026 * access. These should be enabled by FW for target VMIDs. 2027 */ 2028 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2029 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 2030 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 2031 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 2032 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 2033 } 2034 } 2035 2036 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 2037 { 2038 int vmid; 2039 2040 /* 2041 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2042 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2043 * the driver can enable them for graphics. VMID0 should maintain 2044 * access so that HWS firmware can save/restore entries. 2045 */ 2046 for (vmid = 1; vmid < 16; vmid++) { 2047 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 2048 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 2049 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 2050 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 2051 } 2052 } 2053 2054 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 2055 { 2056 /* TODO: harvest feature to be added later. */ 2057 } 2058 2059 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2060 { 2061 /* TCCs are global (not instanced). */ 2062 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2063 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2064 2065 adev->gfx.config.tcc_disabled_mask = 2066 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2067 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2068 } 2069 2070 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2071 { 2072 u32 tmp; 2073 int i; 2074 2075 if (!amdgpu_sriov_vf(adev)) 2076 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2077 2078 gfx_v11_0_setup_rb(adev); 2079 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2080 gfx_v11_0_get_tcc_info(adev); 2081 adev->gfx.config.pa_sc_tile_steering_override = 0; 2082 2083 /* Set whether texture coordinate truncation is conformant. */ 2084 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2085 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2086 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2087 2088 /* XXX SH_MEM regs */ 2089 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2090 mutex_lock(&adev->srbm_mutex); 2091 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2092 soc21_grbm_select(adev, 0, 0, 0, i); 2093 /* CP and shaders */ 2094 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2095 if (i != 0) { 2096 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2097 (adev->gmc.private_aperture_start >> 48)); 2098 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2099 (adev->gmc.shared_aperture_start >> 48)); 2100 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2101 } 2102 } 2103 soc21_grbm_select(adev, 0, 0, 0, 0); 2104 2105 mutex_unlock(&adev->srbm_mutex); 2106 2107 gfx_v11_0_init_compute_vmid(adev); 2108 gfx_v11_0_init_gds_vmid(adev); 2109 } 2110 2111 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2112 int me, int pipe) 2113 { 2114 if (me != 0) 2115 return 0; 2116 2117 switch (pipe) { 2118 case 0: 2119 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2120 case 1: 2121 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2122 default: 2123 return 0; 2124 } 2125 } 2126 2127 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2128 int me, int pipe) 2129 { 2130 /* 2131 * amdgpu controls only the first MEC. That's why this function only 2132 * handles the setting of interrupts for this specific MEC. All other 2133 * pipes' interrupts are set by amdkfd. 2134 */ 2135 if (me != 1) 2136 return 0; 2137 2138 switch (pipe) { 2139 case 0: 2140 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2141 case 1: 2142 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2143 case 2: 2144 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2145 case 3: 2146 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2147 default: 2148 return 0; 2149 } 2150 } 2151 2152 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2153 bool enable) 2154 { 2155 u32 tmp, cp_int_cntl_reg; 2156 int i, j; 2157 2158 if (amdgpu_sriov_vf(adev)) 2159 return; 2160 2161 for (i = 0; i < adev->gfx.me.num_me; i++) { 2162 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2163 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2164 2165 if (cp_int_cntl_reg) { 2166 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2168 enable ? 1 : 0); 2169 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2170 enable ? 1 : 0); 2171 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2172 enable ? 1 : 0); 2173 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2174 enable ? 1 : 0); 2175 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2176 } 2177 } 2178 } 2179 } 2180 2181 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2182 { 2183 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2184 2185 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2186 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2187 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2188 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2189 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2190 2191 return 0; 2192 } 2193 2194 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2195 { 2196 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2197 2198 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2199 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2200 } 2201 2202 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2203 { 2204 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2205 udelay(50); 2206 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2207 udelay(50); 2208 } 2209 2210 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2211 bool enable) 2212 { 2213 uint32_t rlc_pg_cntl; 2214 2215 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2216 2217 if (!enable) { 2218 /* RLC_PG_CNTL[23] = 0 (default) 2219 * RLC will wait for handshake acks with SMU 2220 * GFXOFF will be enabled 2221 * RLC_PG_CNTL[23] = 1 2222 * RLC will not issue any message to SMU 2223 * hence no handshake between SMU & RLC 2224 * GFXOFF will be disabled 2225 */ 2226 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2227 } else 2228 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2229 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2230 } 2231 2232 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2233 { 2234 /* TODO: enable rlc & smu handshake until smu 2235 * and gfxoff feature works as expected */ 2236 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2237 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2238 2239 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2240 udelay(50); 2241 } 2242 2243 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2244 { 2245 uint32_t tmp; 2246 2247 /* enable Save Restore Machine */ 2248 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2249 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2250 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2251 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2252 } 2253 2254 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2255 { 2256 const struct rlc_firmware_header_v2_0 *hdr; 2257 const __le32 *fw_data; 2258 unsigned i, fw_size; 2259 2260 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2261 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2262 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2263 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2264 2265 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2266 RLCG_UCODE_LOADING_START_ADDRESS); 2267 2268 for (i = 0; i < fw_size; i++) 2269 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2270 le32_to_cpup(fw_data++)); 2271 2272 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2273 } 2274 2275 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2276 { 2277 const struct rlc_firmware_header_v2_2 *hdr; 2278 const __le32 *fw_data; 2279 unsigned i, fw_size; 2280 u32 tmp; 2281 2282 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2283 2284 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2285 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2286 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2287 2288 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2289 2290 for (i = 0; i < fw_size; i++) { 2291 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2292 msleep(1); 2293 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2294 le32_to_cpup(fw_data++)); 2295 } 2296 2297 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2298 2299 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2300 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2301 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2302 2303 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2304 for (i = 0; i < fw_size; i++) { 2305 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2306 msleep(1); 2307 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2308 le32_to_cpup(fw_data++)); 2309 } 2310 2311 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2312 2313 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2314 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2315 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2316 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2317 } 2318 2319 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2320 { 2321 const struct rlc_firmware_header_v2_3 *hdr; 2322 const __le32 *fw_data; 2323 unsigned i, fw_size; 2324 u32 tmp; 2325 2326 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2327 2328 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2329 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2330 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2331 2332 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2333 2334 for (i = 0; i < fw_size; i++) { 2335 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2336 msleep(1); 2337 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2338 le32_to_cpup(fw_data++)); 2339 } 2340 2341 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2342 2343 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2344 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2345 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2346 2347 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2348 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2349 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2350 2351 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2352 2353 for (i = 0; i < fw_size; i++) { 2354 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2355 msleep(1); 2356 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2357 le32_to_cpup(fw_data++)); 2358 } 2359 2360 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2361 2362 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2363 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2364 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2365 } 2366 2367 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2368 { 2369 const struct rlc_firmware_header_v2_0 *hdr; 2370 uint16_t version_major; 2371 uint16_t version_minor; 2372 2373 if (!adev->gfx.rlc_fw) 2374 return -EINVAL; 2375 2376 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2377 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2378 2379 version_major = le16_to_cpu(hdr->header.header_version_major); 2380 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2381 2382 if (version_major == 2) { 2383 gfx_v11_0_load_rlcg_microcode(adev); 2384 if (amdgpu_dpm == 1) { 2385 if (version_minor >= 2) 2386 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2387 if (version_minor == 3) 2388 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2389 } 2390 2391 return 0; 2392 } 2393 2394 return -EINVAL; 2395 } 2396 2397 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2398 { 2399 int r; 2400 2401 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2402 gfx_v11_0_init_csb(adev); 2403 2404 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2405 gfx_v11_0_rlc_enable_srm(adev); 2406 } else { 2407 if (amdgpu_sriov_vf(adev)) { 2408 gfx_v11_0_init_csb(adev); 2409 return 0; 2410 } 2411 2412 adev->gfx.rlc.funcs->stop(adev); 2413 2414 /* disable CG */ 2415 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2416 2417 /* disable PG */ 2418 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2419 2420 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2421 /* legacy rlc firmware loading */ 2422 r = gfx_v11_0_rlc_load_microcode(adev); 2423 if (r) 2424 return r; 2425 } 2426 2427 gfx_v11_0_init_csb(adev); 2428 2429 adev->gfx.rlc.funcs->start(adev); 2430 } 2431 return 0; 2432 } 2433 2434 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2435 { 2436 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2437 uint32_t tmp; 2438 int i; 2439 2440 /* Trigger an invalidation of the L1 instruction caches */ 2441 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2442 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2443 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2444 2445 /* Wait for invalidation complete */ 2446 for (i = 0; i < usec_timeout; i++) { 2447 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2448 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2449 INVALIDATE_CACHE_COMPLETE)) 2450 break; 2451 udelay(1); 2452 } 2453 2454 if (i >= usec_timeout) { 2455 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2456 return -EINVAL; 2457 } 2458 2459 if (amdgpu_emu_mode == 1) 2460 adev->hdp.funcs->flush_hdp(adev, NULL); 2461 2462 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2463 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2464 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2465 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2466 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2467 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2468 2469 /* Program me ucode address into intruction cache address register */ 2470 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2471 lower_32_bits(addr) & 0xFFFFF000); 2472 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2473 upper_32_bits(addr)); 2474 2475 return 0; 2476 } 2477 2478 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2479 { 2480 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2481 uint32_t tmp; 2482 int i; 2483 2484 /* Trigger an invalidation of the L1 instruction caches */ 2485 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2486 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2487 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2488 2489 /* Wait for invalidation complete */ 2490 for (i = 0; i < usec_timeout; i++) { 2491 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2492 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2493 INVALIDATE_CACHE_COMPLETE)) 2494 break; 2495 udelay(1); 2496 } 2497 2498 if (i >= usec_timeout) { 2499 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2500 return -EINVAL; 2501 } 2502 2503 if (amdgpu_emu_mode == 1) 2504 adev->hdp.funcs->flush_hdp(adev, NULL); 2505 2506 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2507 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2508 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2509 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2510 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2511 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2512 2513 /* Program pfp ucode address into intruction cache address register */ 2514 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2515 lower_32_bits(addr) & 0xFFFFF000); 2516 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2517 upper_32_bits(addr)); 2518 2519 return 0; 2520 } 2521 2522 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2523 { 2524 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2525 uint32_t tmp; 2526 int i; 2527 2528 /* Trigger an invalidation of the L1 instruction caches */ 2529 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2530 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2531 2532 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2533 2534 /* Wait for invalidation complete */ 2535 for (i = 0; i < usec_timeout; i++) { 2536 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2537 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2538 INVALIDATE_CACHE_COMPLETE)) 2539 break; 2540 udelay(1); 2541 } 2542 2543 if (i >= usec_timeout) { 2544 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2545 return -EINVAL; 2546 } 2547 2548 if (amdgpu_emu_mode == 1) 2549 adev->hdp.funcs->flush_hdp(adev, NULL); 2550 2551 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2552 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2553 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2554 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2555 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2556 2557 /* Program mec1 ucode address into intruction cache address register */ 2558 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2559 lower_32_bits(addr) & 0xFFFFF000); 2560 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2561 upper_32_bits(addr)); 2562 2563 return 0; 2564 } 2565 2566 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2567 { 2568 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2569 uint32_t tmp; 2570 unsigned i, pipe_id; 2571 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2572 2573 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2574 adev->gfx.pfp_fw->data; 2575 2576 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2577 lower_32_bits(addr)); 2578 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2579 upper_32_bits(addr)); 2580 2581 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2582 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2583 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2584 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2585 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2586 2587 /* 2588 * Programming any of the CP_PFP_IC_BASE registers 2589 * forces invalidation of the ME L1 I$. Wait for the 2590 * invalidation complete 2591 */ 2592 for (i = 0; i < usec_timeout; i++) { 2593 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2594 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2595 INVALIDATE_CACHE_COMPLETE)) 2596 break; 2597 udelay(1); 2598 } 2599 2600 if (i >= usec_timeout) { 2601 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2602 return -EINVAL; 2603 } 2604 2605 /* Prime the L1 instruction caches */ 2606 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2607 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2608 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2609 /* Waiting for cache primed*/ 2610 for (i = 0; i < usec_timeout; i++) { 2611 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2612 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2613 ICACHE_PRIMED)) 2614 break; 2615 udelay(1); 2616 } 2617 2618 if (i >= usec_timeout) { 2619 dev_err(adev->dev, "failed to prime instruction cache\n"); 2620 return -EINVAL; 2621 } 2622 2623 mutex_lock(&adev->srbm_mutex); 2624 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2625 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2626 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2627 (pfp_hdr->ucode_start_addr_hi << 30) | 2628 (pfp_hdr->ucode_start_addr_lo >> 2)); 2629 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2630 pfp_hdr->ucode_start_addr_hi >> 2); 2631 2632 /* 2633 * Program CP_ME_CNTL to reset given PIPE to take 2634 * effect of CP_PFP_PRGRM_CNTR_START. 2635 */ 2636 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2637 if (pipe_id == 0) 2638 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2639 PFP_PIPE0_RESET, 1); 2640 else 2641 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2642 PFP_PIPE1_RESET, 1); 2643 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2644 2645 /* Clear pfp pipe0 reset bit. */ 2646 if (pipe_id == 0) 2647 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2648 PFP_PIPE0_RESET, 0); 2649 else 2650 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2651 PFP_PIPE1_RESET, 0); 2652 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2653 2654 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2655 lower_32_bits(addr2)); 2656 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2657 upper_32_bits(addr2)); 2658 } 2659 soc21_grbm_select(adev, 0, 0, 0, 0); 2660 mutex_unlock(&adev->srbm_mutex); 2661 2662 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2663 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2664 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2665 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2666 2667 /* Invalidate the data caches */ 2668 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2669 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2670 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2671 2672 for (i = 0; i < usec_timeout; i++) { 2673 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2674 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2675 INVALIDATE_DCACHE_COMPLETE)) 2676 break; 2677 udelay(1); 2678 } 2679 2680 if (i >= usec_timeout) { 2681 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2682 return -EINVAL; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2689 { 2690 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2691 uint32_t tmp; 2692 unsigned i, pipe_id; 2693 const struct gfx_firmware_header_v2_0 *me_hdr; 2694 2695 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2696 adev->gfx.me_fw->data; 2697 2698 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2699 lower_32_bits(addr)); 2700 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2701 upper_32_bits(addr)); 2702 2703 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2704 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2705 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2706 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2707 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2708 2709 /* 2710 * Programming any of the CP_ME_IC_BASE registers 2711 * forces invalidation of the ME L1 I$. Wait for the 2712 * invalidation complete 2713 */ 2714 for (i = 0; i < usec_timeout; i++) { 2715 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2716 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2717 INVALIDATE_CACHE_COMPLETE)) 2718 break; 2719 udelay(1); 2720 } 2721 2722 if (i >= usec_timeout) { 2723 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2724 return -EINVAL; 2725 } 2726 2727 /* Prime the instruction caches */ 2728 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2729 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2730 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2731 2732 /* Waiting for instruction cache primed*/ 2733 for (i = 0; i < usec_timeout; i++) { 2734 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2735 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2736 ICACHE_PRIMED)) 2737 break; 2738 udelay(1); 2739 } 2740 2741 if (i >= usec_timeout) { 2742 dev_err(adev->dev, "failed to prime instruction cache\n"); 2743 return -EINVAL; 2744 } 2745 2746 mutex_lock(&adev->srbm_mutex); 2747 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2748 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2749 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2750 (me_hdr->ucode_start_addr_hi << 30) | 2751 (me_hdr->ucode_start_addr_lo >> 2) ); 2752 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2753 me_hdr->ucode_start_addr_hi>>2); 2754 2755 /* 2756 * Program CP_ME_CNTL to reset given PIPE to take 2757 * effect of CP_PFP_PRGRM_CNTR_START. 2758 */ 2759 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2760 if (pipe_id == 0) 2761 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2762 ME_PIPE0_RESET, 1); 2763 else 2764 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2765 ME_PIPE1_RESET, 1); 2766 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2767 2768 /* Clear pfp pipe0 reset bit. */ 2769 if (pipe_id == 0) 2770 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2771 ME_PIPE0_RESET, 0); 2772 else 2773 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2774 ME_PIPE1_RESET, 0); 2775 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2776 2777 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2778 lower_32_bits(addr2)); 2779 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2780 upper_32_bits(addr2)); 2781 } 2782 soc21_grbm_select(adev, 0, 0, 0, 0); 2783 mutex_unlock(&adev->srbm_mutex); 2784 2785 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2786 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2787 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2788 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2789 2790 /* Invalidate the data caches */ 2791 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2792 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2793 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2794 2795 for (i = 0; i < usec_timeout; i++) { 2796 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2797 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2798 INVALIDATE_DCACHE_COMPLETE)) 2799 break; 2800 udelay(1); 2801 } 2802 2803 if (i >= usec_timeout) { 2804 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2805 return -EINVAL; 2806 } 2807 2808 return 0; 2809 } 2810 2811 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2812 { 2813 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2814 uint32_t tmp; 2815 unsigned i; 2816 const struct gfx_firmware_header_v2_0 *mec_hdr; 2817 2818 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2819 adev->gfx.mec_fw->data; 2820 2821 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2822 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2823 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2824 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2825 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2826 2827 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2828 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2829 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2830 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2831 2832 mutex_lock(&adev->srbm_mutex); 2833 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2834 soc21_grbm_select(adev, 1, i, 0, 0); 2835 2836 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2837 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2838 upper_32_bits(addr2)); 2839 2840 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2841 mec_hdr->ucode_start_addr_lo >> 2 | 2842 mec_hdr->ucode_start_addr_hi << 30); 2843 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2844 mec_hdr->ucode_start_addr_hi >> 2); 2845 2846 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2847 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2848 upper_32_bits(addr)); 2849 } 2850 mutex_unlock(&adev->srbm_mutex); 2851 soc21_grbm_select(adev, 0, 0, 0, 0); 2852 2853 /* Trigger an invalidation of the L1 instruction caches */ 2854 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2855 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2856 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2857 2858 /* Wait for invalidation complete */ 2859 for (i = 0; i < usec_timeout; i++) { 2860 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2861 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2862 INVALIDATE_DCACHE_COMPLETE)) 2863 break; 2864 udelay(1); 2865 } 2866 2867 if (i >= usec_timeout) { 2868 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2869 return -EINVAL; 2870 } 2871 2872 /* Trigger an invalidation of the L1 instruction caches */ 2873 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2874 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2875 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2876 2877 /* Wait for invalidation complete */ 2878 for (i = 0; i < usec_timeout; i++) { 2879 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2880 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2881 INVALIDATE_CACHE_COMPLETE)) 2882 break; 2883 udelay(1); 2884 } 2885 2886 if (i >= usec_timeout) { 2887 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2888 return -EINVAL; 2889 } 2890 2891 return 0; 2892 } 2893 2894 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2895 { 2896 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2897 const struct gfx_firmware_header_v2_0 *me_hdr; 2898 const struct gfx_firmware_header_v2_0 *mec_hdr; 2899 uint32_t pipe_id, tmp; 2900 2901 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2902 adev->gfx.mec_fw->data; 2903 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2904 adev->gfx.me_fw->data; 2905 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2906 adev->gfx.pfp_fw->data; 2907 2908 /* config pfp program start addr */ 2909 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2910 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2911 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2912 (pfp_hdr->ucode_start_addr_hi << 30) | 2913 (pfp_hdr->ucode_start_addr_lo >> 2)); 2914 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2915 pfp_hdr->ucode_start_addr_hi >> 2); 2916 } 2917 soc21_grbm_select(adev, 0, 0, 0, 0); 2918 2919 /* reset pfp pipe */ 2920 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2921 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2922 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2923 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2924 2925 /* clear pfp pipe reset */ 2926 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2927 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2928 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2929 2930 /* config me program start addr */ 2931 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2932 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2933 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2934 (me_hdr->ucode_start_addr_hi << 30) | 2935 (me_hdr->ucode_start_addr_lo >> 2) ); 2936 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2937 me_hdr->ucode_start_addr_hi>>2); 2938 } 2939 soc21_grbm_select(adev, 0, 0, 0, 0); 2940 2941 /* reset me pipe */ 2942 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2943 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2944 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2945 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2946 2947 /* clear me pipe reset */ 2948 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2949 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2950 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2951 2952 /* config mec program start addr */ 2953 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2954 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2955 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2956 mec_hdr->ucode_start_addr_lo >> 2 | 2957 mec_hdr->ucode_start_addr_hi << 30); 2958 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2959 mec_hdr->ucode_start_addr_hi >> 2); 2960 } 2961 soc21_grbm_select(adev, 0, 0, 0, 0); 2962 2963 /* reset mec pipe */ 2964 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2965 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2966 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2967 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2968 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2969 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2970 2971 /* clear mec pipe reset */ 2972 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2973 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2974 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2975 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2976 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2977 } 2978 2979 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2980 { 2981 uint32_t cp_status; 2982 uint32_t bootload_status; 2983 int i, r; 2984 uint64_t addr, addr2; 2985 2986 for (i = 0; i < adev->usec_timeout; i++) { 2987 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2988 2989 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2990 IP_VERSION(11, 0, 1) || 2991 amdgpu_ip_version(adev, GC_HWIP, 0) == 2992 IP_VERSION(11, 0, 4) || 2993 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 2994 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 2995 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 2996 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) 2997 bootload_status = RREG32_SOC15(GC, 0, 2998 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2999 else 3000 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 3001 3002 if ((cp_status == 0) && 3003 (REG_GET_FIELD(bootload_status, 3004 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 3005 break; 3006 } 3007 udelay(1); 3008 } 3009 3010 if (i >= adev->usec_timeout) { 3011 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 3012 return -ETIMEDOUT; 3013 } 3014 3015 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3016 if (adev->gfx.rs64_enable) { 3017 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3018 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 3019 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3020 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 3021 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 3022 if (r) 3023 return r; 3024 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3025 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 3026 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3027 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 3028 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 3029 if (r) 3030 return r; 3031 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3032 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 3033 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3034 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 3035 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 3036 if (r) 3037 return r; 3038 } else { 3039 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3040 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 3041 r = gfx_v11_0_config_me_cache(adev, addr); 3042 if (r) 3043 return r; 3044 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3045 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 3046 r = gfx_v11_0_config_pfp_cache(adev, addr); 3047 if (r) 3048 return r; 3049 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3050 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 3051 r = gfx_v11_0_config_mec_cache(adev, addr); 3052 if (r) 3053 return r; 3054 } 3055 } 3056 3057 return 0; 3058 } 3059 3060 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3061 { 3062 int i; 3063 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3064 3065 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3066 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3067 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3068 3069 for (i = 0; i < adev->usec_timeout; i++) { 3070 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3071 break; 3072 udelay(1); 3073 } 3074 3075 if (i >= adev->usec_timeout) 3076 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3077 3078 return 0; 3079 } 3080 3081 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3082 { 3083 int r; 3084 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3085 const __le32 *fw_data; 3086 unsigned i, fw_size; 3087 3088 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3089 adev->gfx.pfp_fw->data; 3090 3091 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3092 3093 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3094 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3095 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3096 3097 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3098 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3099 &adev->gfx.pfp.pfp_fw_obj, 3100 &adev->gfx.pfp.pfp_fw_gpu_addr, 3101 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3102 if (r) { 3103 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3104 gfx_v11_0_pfp_fini(adev); 3105 return r; 3106 } 3107 3108 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3109 3110 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3111 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3112 3113 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3114 3115 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3116 3117 for (i = 0; i < pfp_hdr->jt_size; i++) 3118 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3119 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3120 3121 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3122 3123 return 0; 3124 } 3125 3126 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3127 { 3128 int r; 3129 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3130 const __le32 *fw_ucode, *fw_data; 3131 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3132 uint32_t tmp; 3133 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3134 3135 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3136 adev->gfx.pfp_fw->data; 3137 3138 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3139 3140 /* instruction */ 3141 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3142 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3143 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3144 /* data */ 3145 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3146 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3147 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3148 3149 /* 64kb align */ 3150 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3151 64 * 1024, 3152 AMDGPU_GEM_DOMAIN_VRAM | 3153 AMDGPU_GEM_DOMAIN_GTT, 3154 &adev->gfx.pfp.pfp_fw_obj, 3155 &adev->gfx.pfp.pfp_fw_gpu_addr, 3156 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3157 if (r) { 3158 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3159 gfx_v11_0_pfp_fini(adev); 3160 return r; 3161 } 3162 3163 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3164 64 * 1024, 3165 AMDGPU_GEM_DOMAIN_VRAM | 3166 AMDGPU_GEM_DOMAIN_GTT, 3167 &adev->gfx.pfp.pfp_fw_data_obj, 3168 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3169 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3170 if (r) { 3171 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3172 gfx_v11_0_pfp_fini(adev); 3173 return r; 3174 } 3175 3176 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3177 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3178 3179 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3180 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3181 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3182 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3183 3184 if (amdgpu_emu_mode == 1) 3185 adev->hdp.funcs->flush_hdp(adev, NULL); 3186 3187 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3188 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3189 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3190 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3191 3192 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3193 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3194 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3195 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3196 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3197 3198 /* 3199 * Programming any of the CP_PFP_IC_BASE registers 3200 * forces invalidation of the ME L1 I$. Wait for the 3201 * invalidation complete 3202 */ 3203 for (i = 0; i < usec_timeout; i++) { 3204 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3205 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3206 INVALIDATE_CACHE_COMPLETE)) 3207 break; 3208 udelay(1); 3209 } 3210 3211 if (i >= usec_timeout) { 3212 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3213 return -EINVAL; 3214 } 3215 3216 /* Prime the L1 instruction caches */ 3217 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3218 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3219 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3220 /* Waiting for cache primed*/ 3221 for (i = 0; i < usec_timeout; i++) { 3222 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3223 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3224 ICACHE_PRIMED)) 3225 break; 3226 udelay(1); 3227 } 3228 3229 if (i >= usec_timeout) { 3230 dev_err(adev->dev, "failed to prime instruction cache\n"); 3231 return -EINVAL; 3232 } 3233 3234 mutex_lock(&adev->srbm_mutex); 3235 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3236 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3237 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3238 (pfp_hdr->ucode_start_addr_hi << 30) | 3239 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3240 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3241 pfp_hdr->ucode_start_addr_hi>>2); 3242 3243 /* 3244 * Program CP_ME_CNTL to reset given PIPE to take 3245 * effect of CP_PFP_PRGRM_CNTR_START. 3246 */ 3247 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3248 if (pipe_id == 0) 3249 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3250 PFP_PIPE0_RESET, 1); 3251 else 3252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3253 PFP_PIPE1_RESET, 1); 3254 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3255 3256 /* Clear pfp pipe0 reset bit. */ 3257 if (pipe_id == 0) 3258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3259 PFP_PIPE0_RESET, 0); 3260 else 3261 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3262 PFP_PIPE1_RESET, 0); 3263 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3264 3265 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3266 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3267 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3268 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3269 } 3270 soc21_grbm_select(adev, 0, 0, 0, 0); 3271 mutex_unlock(&adev->srbm_mutex); 3272 3273 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3274 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3275 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3276 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3277 3278 /* Invalidate the data caches */ 3279 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3280 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3281 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3282 3283 for (i = 0; i < usec_timeout; i++) { 3284 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3285 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3286 INVALIDATE_DCACHE_COMPLETE)) 3287 break; 3288 udelay(1); 3289 } 3290 3291 if (i >= usec_timeout) { 3292 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3293 return -EINVAL; 3294 } 3295 3296 return 0; 3297 } 3298 3299 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3300 { 3301 int r; 3302 const struct gfx_firmware_header_v1_0 *me_hdr; 3303 const __le32 *fw_data; 3304 unsigned i, fw_size; 3305 3306 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3307 adev->gfx.me_fw->data; 3308 3309 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3310 3311 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3312 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3313 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3314 3315 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3317 &adev->gfx.me.me_fw_obj, 3318 &adev->gfx.me.me_fw_gpu_addr, 3319 (void **)&adev->gfx.me.me_fw_ptr); 3320 if (r) { 3321 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3322 gfx_v11_0_me_fini(adev); 3323 return r; 3324 } 3325 3326 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3327 3328 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3329 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3330 3331 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3332 3333 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3334 3335 for (i = 0; i < me_hdr->jt_size; i++) 3336 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3337 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3338 3339 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3340 3341 return 0; 3342 } 3343 3344 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3345 { 3346 int r; 3347 const struct gfx_firmware_header_v2_0 *me_hdr; 3348 const __le32 *fw_ucode, *fw_data; 3349 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3350 uint32_t tmp; 3351 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3352 3353 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3354 adev->gfx.me_fw->data; 3355 3356 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3357 3358 /* instruction */ 3359 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3360 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3361 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3362 /* data */ 3363 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3364 le32_to_cpu(me_hdr->data_offset_bytes)); 3365 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3366 3367 /* 64kb align*/ 3368 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3369 64 * 1024, 3370 AMDGPU_GEM_DOMAIN_VRAM | 3371 AMDGPU_GEM_DOMAIN_GTT, 3372 &adev->gfx.me.me_fw_obj, 3373 &adev->gfx.me.me_fw_gpu_addr, 3374 (void **)&adev->gfx.me.me_fw_ptr); 3375 if (r) { 3376 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3377 gfx_v11_0_me_fini(adev); 3378 return r; 3379 } 3380 3381 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3382 64 * 1024, 3383 AMDGPU_GEM_DOMAIN_VRAM | 3384 AMDGPU_GEM_DOMAIN_GTT, 3385 &adev->gfx.me.me_fw_data_obj, 3386 &adev->gfx.me.me_fw_data_gpu_addr, 3387 (void **)&adev->gfx.me.me_fw_data_ptr); 3388 if (r) { 3389 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3390 gfx_v11_0_pfp_fini(adev); 3391 return r; 3392 } 3393 3394 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3395 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3396 3397 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3398 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3399 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3400 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3401 3402 if (amdgpu_emu_mode == 1) 3403 adev->hdp.funcs->flush_hdp(adev, NULL); 3404 3405 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3406 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3407 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3408 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3409 3410 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3411 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3412 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3413 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3414 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3415 3416 /* 3417 * Programming any of the CP_ME_IC_BASE registers 3418 * forces invalidation of the ME L1 I$. Wait for the 3419 * invalidation complete 3420 */ 3421 for (i = 0; i < usec_timeout; i++) { 3422 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3423 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3424 INVALIDATE_CACHE_COMPLETE)) 3425 break; 3426 udelay(1); 3427 } 3428 3429 if (i >= usec_timeout) { 3430 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3431 return -EINVAL; 3432 } 3433 3434 /* Prime the instruction caches */ 3435 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3436 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3437 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3438 3439 /* Waiting for instruction cache primed*/ 3440 for (i = 0; i < usec_timeout; i++) { 3441 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3442 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3443 ICACHE_PRIMED)) 3444 break; 3445 udelay(1); 3446 } 3447 3448 if (i >= usec_timeout) { 3449 dev_err(adev->dev, "failed to prime instruction cache\n"); 3450 return -EINVAL; 3451 } 3452 3453 mutex_lock(&adev->srbm_mutex); 3454 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3455 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3456 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3457 (me_hdr->ucode_start_addr_hi << 30) | 3458 (me_hdr->ucode_start_addr_lo >> 2) ); 3459 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3460 me_hdr->ucode_start_addr_hi>>2); 3461 3462 /* 3463 * Program CP_ME_CNTL to reset given PIPE to take 3464 * effect of CP_PFP_PRGRM_CNTR_START. 3465 */ 3466 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3467 if (pipe_id == 0) 3468 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3469 ME_PIPE0_RESET, 1); 3470 else 3471 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3472 ME_PIPE1_RESET, 1); 3473 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3474 3475 /* Clear pfp pipe0 reset bit. */ 3476 if (pipe_id == 0) 3477 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3478 ME_PIPE0_RESET, 0); 3479 else 3480 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3481 ME_PIPE1_RESET, 0); 3482 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3483 3484 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3485 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3486 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3487 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3488 } 3489 soc21_grbm_select(adev, 0, 0, 0, 0); 3490 mutex_unlock(&adev->srbm_mutex); 3491 3492 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3493 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3494 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3495 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3496 3497 /* Invalidate the data caches */ 3498 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3499 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3500 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3501 3502 for (i = 0; i < usec_timeout; i++) { 3503 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3504 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3505 INVALIDATE_DCACHE_COMPLETE)) 3506 break; 3507 udelay(1); 3508 } 3509 3510 if (i >= usec_timeout) { 3511 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3512 return -EINVAL; 3513 } 3514 3515 return 0; 3516 } 3517 3518 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3519 { 3520 int r; 3521 3522 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3523 return -EINVAL; 3524 3525 gfx_v11_0_cp_gfx_enable(adev, false); 3526 3527 if (adev->gfx.rs64_enable) 3528 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3529 else 3530 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3531 if (r) { 3532 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3533 return r; 3534 } 3535 3536 if (adev->gfx.rs64_enable) 3537 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3538 else 3539 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3540 if (r) { 3541 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3542 return r; 3543 } 3544 3545 return 0; 3546 } 3547 3548 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3549 { 3550 struct amdgpu_ring *ring; 3551 const struct cs_section_def *sect = NULL; 3552 const struct cs_extent_def *ext = NULL; 3553 int r, i; 3554 int ctx_reg_offset; 3555 3556 /* init the CP */ 3557 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3558 adev->gfx.config.max_hw_contexts - 1); 3559 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3560 3561 if (!amdgpu_async_gfx_ring) 3562 gfx_v11_0_cp_gfx_enable(adev, true); 3563 3564 ring = &adev->gfx.gfx_ring[0]; 3565 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3566 if (r) { 3567 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3568 return r; 3569 } 3570 3571 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3572 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3573 3574 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3575 amdgpu_ring_write(ring, 0x80000000); 3576 amdgpu_ring_write(ring, 0x80000000); 3577 3578 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3579 for (ext = sect->section; ext->extent != NULL; ++ext) { 3580 if (sect->id == SECT_CONTEXT) { 3581 amdgpu_ring_write(ring, 3582 PACKET3(PACKET3_SET_CONTEXT_REG, 3583 ext->reg_count)); 3584 amdgpu_ring_write(ring, ext->reg_index - 3585 PACKET3_SET_CONTEXT_REG_START); 3586 for (i = 0; i < ext->reg_count; i++) 3587 amdgpu_ring_write(ring, ext->extent[i]); 3588 } 3589 } 3590 } 3591 3592 ctx_reg_offset = 3593 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3594 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3595 amdgpu_ring_write(ring, ctx_reg_offset); 3596 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3597 3598 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3599 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3600 3601 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3602 amdgpu_ring_write(ring, 0); 3603 3604 amdgpu_ring_commit(ring); 3605 3606 /* submit cs packet to copy state 0 to next available state */ 3607 if (adev->gfx.num_gfx_rings > 1) { 3608 /* maximum supported gfx ring is 2 */ 3609 ring = &adev->gfx.gfx_ring[1]; 3610 r = amdgpu_ring_alloc(ring, 2); 3611 if (r) { 3612 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3613 return r; 3614 } 3615 3616 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3617 amdgpu_ring_write(ring, 0); 3618 3619 amdgpu_ring_commit(ring); 3620 } 3621 return 0; 3622 } 3623 3624 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3625 CP_PIPE_ID pipe) 3626 { 3627 u32 tmp; 3628 3629 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3630 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3631 3632 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3633 } 3634 3635 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3636 struct amdgpu_ring *ring) 3637 { 3638 u32 tmp; 3639 3640 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3641 if (ring->use_doorbell) { 3642 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3643 DOORBELL_OFFSET, ring->doorbell_index); 3644 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3645 DOORBELL_EN, 1); 3646 } else { 3647 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3648 DOORBELL_EN, 0); 3649 } 3650 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3651 3652 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3653 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3654 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3655 3656 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3657 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3658 } 3659 3660 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3661 { 3662 struct amdgpu_ring *ring; 3663 u32 tmp; 3664 u32 rb_bufsz; 3665 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3666 3667 /* Set the write pointer delay */ 3668 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3669 3670 /* set the RB to use vmid 0 */ 3671 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3672 3673 /* Init gfx ring 0 for pipe 0 */ 3674 mutex_lock(&adev->srbm_mutex); 3675 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3676 3677 /* Set ring buffer size */ 3678 ring = &adev->gfx.gfx_ring[0]; 3679 rb_bufsz = order_base_2(ring->ring_size / 8); 3680 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3681 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3682 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3683 3684 /* Initialize the ring buffer's write pointers */ 3685 ring->wptr = 0; 3686 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3687 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3688 3689 /* set the wb address whether it's enabled or not */ 3690 rptr_addr = ring->rptr_gpu_addr; 3691 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3692 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3693 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3694 3695 wptr_gpu_addr = ring->wptr_gpu_addr; 3696 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3697 lower_32_bits(wptr_gpu_addr)); 3698 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3699 upper_32_bits(wptr_gpu_addr)); 3700 3701 mdelay(1); 3702 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3703 3704 rb_addr = ring->gpu_addr >> 8; 3705 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3706 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3707 3708 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3709 3710 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3711 mutex_unlock(&adev->srbm_mutex); 3712 3713 /* Init gfx ring 1 for pipe 1 */ 3714 if (adev->gfx.num_gfx_rings > 1) { 3715 mutex_lock(&adev->srbm_mutex); 3716 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3717 /* maximum supported gfx ring is 2 */ 3718 ring = &adev->gfx.gfx_ring[1]; 3719 rb_bufsz = order_base_2(ring->ring_size / 8); 3720 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3721 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3722 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3723 /* Initialize the ring buffer's write pointers */ 3724 ring->wptr = 0; 3725 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3726 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3727 /* Set the wb address whether it's enabled or not */ 3728 rptr_addr = ring->rptr_gpu_addr; 3729 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3730 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3731 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3732 wptr_gpu_addr = ring->wptr_gpu_addr; 3733 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3734 lower_32_bits(wptr_gpu_addr)); 3735 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3736 upper_32_bits(wptr_gpu_addr)); 3737 3738 mdelay(1); 3739 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3740 3741 rb_addr = ring->gpu_addr >> 8; 3742 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3743 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3744 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3745 3746 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3747 mutex_unlock(&adev->srbm_mutex); 3748 } 3749 /* Switch to pipe 0 */ 3750 mutex_lock(&adev->srbm_mutex); 3751 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3752 mutex_unlock(&adev->srbm_mutex); 3753 3754 /* start the ring */ 3755 gfx_v11_0_cp_gfx_start(adev); 3756 3757 return 0; 3758 } 3759 3760 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3761 { 3762 u32 data; 3763 3764 if (adev->gfx.rs64_enable) { 3765 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3766 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3767 enable ? 0 : 1); 3768 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3769 enable ? 0 : 1); 3770 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3771 enable ? 0 : 1); 3772 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3773 enable ? 0 : 1); 3774 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3775 enable ? 0 : 1); 3776 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3777 enable ? 1 : 0); 3778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3779 enable ? 1 : 0); 3780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3781 enable ? 1 : 0); 3782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3783 enable ? 1 : 0); 3784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3785 enable ? 0 : 1); 3786 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3787 } else { 3788 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3789 3790 if (enable) { 3791 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3792 if (!adev->enable_mes_kiq) 3793 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3794 MEC_ME2_HALT, 0); 3795 } else { 3796 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3797 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3798 } 3799 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3800 } 3801 3802 udelay(50); 3803 } 3804 3805 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3806 { 3807 const struct gfx_firmware_header_v1_0 *mec_hdr; 3808 const __le32 *fw_data; 3809 unsigned i, fw_size; 3810 u32 *fw = NULL; 3811 int r; 3812 3813 if (!adev->gfx.mec_fw) 3814 return -EINVAL; 3815 3816 gfx_v11_0_cp_compute_enable(adev, false); 3817 3818 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3819 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3820 3821 fw_data = (const __le32 *) 3822 (adev->gfx.mec_fw->data + 3823 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3824 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3825 3826 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3827 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3828 &adev->gfx.mec.mec_fw_obj, 3829 &adev->gfx.mec.mec_fw_gpu_addr, 3830 (void **)&fw); 3831 if (r) { 3832 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3833 gfx_v11_0_mec_fini(adev); 3834 return r; 3835 } 3836 3837 memcpy(fw, fw_data, fw_size); 3838 3839 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3840 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3841 3842 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3843 3844 /* MEC1 */ 3845 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3846 3847 for (i = 0; i < mec_hdr->jt_size; i++) 3848 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3849 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3850 3851 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3852 3853 return 0; 3854 } 3855 3856 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3857 { 3858 const struct gfx_firmware_header_v2_0 *mec_hdr; 3859 const __le32 *fw_ucode, *fw_data; 3860 u32 tmp, fw_ucode_size, fw_data_size; 3861 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3862 u32 *fw_ucode_ptr, *fw_data_ptr; 3863 int r; 3864 3865 if (!adev->gfx.mec_fw) 3866 return -EINVAL; 3867 3868 gfx_v11_0_cp_compute_enable(adev, false); 3869 3870 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3871 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3872 3873 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3874 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3875 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3876 3877 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3878 le32_to_cpu(mec_hdr->data_offset_bytes)); 3879 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3880 3881 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3882 64 * 1024, 3883 AMDGPU_GEM_DOMAIN_VRAM | 3884 AMDGPU_GEM_DOMAIN_GTT, 3885 &adev->gfx.mec.mec_fw_obj, 3886 &adev->gfx.mec.mec_fw_gpu_addr, 3887 (void **)&fw_ucode_ptr); 3888 if (r) { 3889 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3890 gfx_v11_0_mec_fini(adev); 3891 return r; 3892 } 3893 3894 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3895 64 * 1024, 3896 AMDGPU_GEM_DOMAIN_VRAM | 3897 AMDGPU_GEM_DOMAIN_GTT, 3898 &adev->gfx.mec.mec_fw_data_obj, 3899 &adev->gfx.mec.mec_fw_data_gpu_addr, 3900 (void **)&fw_data_ptr); 3901 if (r) { 3902 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3903 gfx_v11_0_mec_fini(adev); 3904 return r; 3905 } 3906 3907 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3908 memcpy(fw_data_ptr, fw_data, fw_data_size); 3909 3910 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3911 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3912 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3913 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3914 3915 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3916 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3917 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3918 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3919 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3920 3921 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3922 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3923 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3924 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3925 3926 mutex_lock(&adev->srbm_mutex); 3927 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3928 soc21_grbm_select(adev, 1, i, 0, 0); 3929 3930 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3931 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3932 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3933 3934 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3935 mec_hdr->ucode_start_addr_lo >> 2 | 3936 mec_hdr->ucode_start_addr_hi << 30); 3937 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3938 mec_hdr->ucode_start_addr_hi >> 2); 3939 3940 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3941 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3942 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3943 } 3944 mutex_unlock(&adev->srbm_mutex); 3945 soc21_grbm_select(adev, 0, 0, 0, 0); 3946 3947 /* Trigger an invalidation of the L1 instruction caches */ 3948 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3949 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3950 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3951 3952 /* Wait for invalidation complete */ 3953 for (i = 0; i < usec_timeout; i++) { 3954 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3955 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3956 INVALIDATE_DCACHE_COMPLETE)) 3957 break; 3958 udelay(1); 3959 } 3960 3961 if (i >= usec_timeout) { 3962 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3963 return -EINVAL; 3964 } 3965 3966 /* Trigger an invalidation of the L1 instruction caches */ 3967 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3968 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3969 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3970 3971 /* Wait for invalidation complete */ 3972 for (i = 0; i < usec_timeout; i++) { 3973 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3974 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3975 INVALIDATE_CACHE_COMPLETE)) 3976 break; 3977 udelay(1); 3978 } 3979 3980 if (i >= usec_timeout) { 3981 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3982 return -EINVAL; 3983 } 3984 3985 return 0; 3986 } 3987 3988 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3989 { 3990 uint32_t tmp; 3991 struct amdgpu_device *adev = ring->adev; 3992 3993 /* tell RLC which is KIQ queue */ 3994 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3995 tmp &= 0xffffff00; 3996 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3997 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 3998 } 3999 4000 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 4001 { 4002 /* set graphics engine doorbell range */ 4003 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 4004 (adev->doorbell_index.gfx_ring0 * 2) << 2); 4005 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 4006 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 4007 4008 /* set compute engine doorbell range */ 4009 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4010 (adev->doorbell_index.kiq * 2) << 2); 4011 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4012 (adev->doorbell_index.userqueue_end * 2) << 2); 4013 } 4014 4015 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 4016 struct v11_gfx_mqd *mqd, 4017 struct amdgpu_mqd_prop *prop) 4018 { 4019 bool priority = 0; 4020 u32 tmp; 4021 4022 /* set up default queue priority level 4023 * 0x0 = low priority, 0x1 = high priority 4024 */ 4025 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 4026 priority = 1; 4027 4028 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 4029 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 4030 mqd->cp_gfx_hqd_queue_priority = tmp; 4031 } 4032 4033 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 4034 struct amdgpu_mqd_prop *prop) 4035 { 4036 struct v11_gfx_mqd *mqd = m; 4037 uint64_t hqd_gpu_addr, wb_gpu_addr; 4038 uint32_t tmp; 4039 uint32_t rb_bufsz; 4040 4041 /* set up gfx hqd wptr */ 4042 mqd->cp_gfx_hqd_wptr = 0; 4043 mqd->cp_gfx_hqd_wptr_hi = 0; 4044 4045 /* set the pointer to the MQD */ 4046 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 4047 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4048 4049 /* set up mqd control */ 4050 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4051 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4052 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4053 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4054 mqd->cp_gfx_mqd_control = tmp; 4055 4056 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4057 tmp = regCP_GFX_HQD_VMID_DEFAULT; 4058 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4059 mqd->cp_gfx_hqd_vmid = 0; 4060 4061 /* set up gfx queue priority */ 4062 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4063 4064 /* set up time quantum */ 4065 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4066 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4067 mqd->cp_gfx_hqd_quantum = tmp; 4068 4069 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4070 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4071 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4072 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4073 4074 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4075 wb_gpu_addr = prop->rptr_gpu_addr; 4076 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4077 mqd->cp_gfx_hqd_rptr_addr_hi = 4078 upper_32_bits(wb_gpu_addr) & 0xffff; 4079 4080 /* set up rb_wptr_poll addr */ 4081 wb_gpu_addr = prop->wptr_gpu_addr; 4082 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4083 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4084 4085 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4086 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4087 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4088 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4089 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4090 #ifdef __BIG_ENDIAN 4091 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4092 #endif 4093 mqd->cp_gfx_hqd_cntl = tmp; 4094 4095 /* set up cp_doorbell_control */ 4096 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4097 if (prop->use_doorbell) { 4098 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4099 DOORBELL_OFFSET, prop->doorbell_index); 4100 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4101 DOORBELL_EN, 1); 4102 } else 4103 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4104 DOORBELL_EN, 0); 4105 mqd->cp_rb_doorbell_control = tmp; 4106 4107 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4108 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4109 4110 /* active the queue */ 4111 mqd->cp_gfx_hqd_active = 1; 4112 4113 return 0; 4114 } 4115 4116 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 4117 { 4118 struct amdgpu_device *adev = ring->adev; 4119 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4120 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4121 4122 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4123 memset((void *)mqd, 0, sizeof(*mqd)); 4124 mutex_lock(&adev->srbm_mutex); 4125 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4126 amdgpu_ring_init_mqd(ring); 4127 soc21_grbm_select(adev, 0, 0, 0, 0); 4128 mutex_unlock(&adev->srbm_mutex); 4129 if (adev->gfx.me.mqd_backup[mqd_idx]) 4130 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4131 } else { 4132 /* restore mqd with the backup copy */ 4133 if (adev->gfx.me.mqd_backup[mqd_idx]) 4134 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4135 /* reset the ring */ 4136 ring->wptr = 0; 4137 *ring->wptr_cpu_addr = 0; 4138 amdgpu_ring_clear_ring(ring); 4139 } 4140 4141 return 0; 4142 } 4143 4144 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4145 { 4146 int r, i; 4147 4148 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4149 r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 4150 if (r) 4151 return r; 4152 } 4153 4154 r = amdgpu_gfx_enable_kgq(adev, 0); 4155 if (r) 4156 return r; 4157 4158 return gfx_v11_0_cp_gfx_start(adev); 4159 } 4160 4161 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4162 struct amdgpu_mqd_prop *prop) 4163 { 4164 struct v11_compute_mqd *mqd = m; 4165 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4166 uint32_t tmp; 4167 4168 mqd->header = 0xC0310800; 4169 mqd->compute_pipelinestat_enable = 0x00000001; 4170 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4171 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4172 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4173 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4174 mqd->compute_misc_reserved = 0x00000007; 4175 4176 eop_base_addr = prop->eop_gpu_addr >> 8; 4177 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4178 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4179 4180 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4181 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4182 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4183 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4184 4185 mqd->cp_hqd_eop_control = tmp; 4186 4187 /* enable doorbell? */ 4188 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4189 4190 if (prop->use_doorbell) { 4191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4192 DOORBELL_OFFSET, prop->doorbell_index); 4193 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4194 DOORBELL_EN, 1); 4195 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4196 DOORBELL_SOURCE, 0); 4197 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4198 DOORBELL_HIT, 0); 4199 } else { 4200 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4201 DOORBELL_EN, 0); 4202 } 4203 4204 mqd->cp_hqd_pq_doorbell_control = tmp; 4205 4206 /* disable the queue if it's active */ 4207 mqd->cp_hqd_dequeue_request = 0; 4208 mqd->cp_hqd_pq_rptr = 0; 4209 mqd->cp_hqd_pq_wptr_lo = 0; 4210 mqd->cp_hqd_pq_wptr_hi = 0; 4211 4212 /* set the pointer to the MQD */ 4213 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4214 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4215 4216 /* set MQD vmid to 0 */ 4217 tmp = regCP_MQD_CONTROL_DEFAULT; 4218 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4219 mqd->cp_mqd_control = tmp; 4220 4221 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4222 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4223 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4224 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4225 4226 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4227 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4228 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4229 (order_base_2(prop->queue_size / 4) - 1)); 4230 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4231 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4232 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4233 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4234 prop->allow_tunneling); 4235 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4236 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4237 mqd->cp_hqd_pq_control = tmp; 4238 4239 /* set the wb address whether it's enabled or not */ 4240 wb_gpu_addr = prop->rptr_gpu_addr; 4241 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4242 mqd->cp_hqd_pq_rptr_report_addr_hi = 4243 upper_32_bits(wb_gpu_addr) & 0xffff; 4244 4245 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4246 wb_gpu_addr = prop->wptr_gpu_addr; 4247 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4248 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4249 4250 tmp = 0; 4251 /* enable the doorbell if requested */ 4252 if (prop->use_doorbell) { 4253 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4254 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4255 DOORBELL_OFFSET, prop->doorbell_index); 4256 4257 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4258 DOORBELL_EN, 1); 4259 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4260 DOORBELL_SOURCE, 0); 4261 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4262 DOORBELL_HIT, 0); 4263 } 4264 4265 mqd->cp_hqd_pq_doorbell_control = tmp; 4266 4267 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4268 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4269 4270 /* set the vmid for the queue */ 4271 mqd->cp_hqd_vmid = 0; 4272 4273 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4274 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4275 mqd->cp_hqd_persistent_state = tmp; 4276 4277 /* set MIN_IB_AVAIL_SIZE */ 4278 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4279 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4280 mqd->cp_hqd_ib_control = tmp; 4281 4282 /* set static priority for a compute queue/ring */ 4283 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4284 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4285 4286 mqd->cp_hqd_active = prop->hqd_active; 4287 4288 return 0; 4289 } 4290 4291 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4292 { 4293 struct amdgpu_device *adev = ring->adev; 4294 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4295 int j; 4296 4297 /* inactivate the queue */ 4298 if (amdgpu_sriov_vf(adev)) 4299 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4300 4301 /* disable wptr polling */ 4302 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4303 4304 /* write the EOP addr */ 4305 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4306 mqd->cp_hqd_eop_base_addr_lo); 4307 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4308 mqd->cp_hqd_eop_base_addr_hi); 4309 4310 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4311 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4312 mqd->cp_hqd_eop_control); 4313 4314 /* enable doorbell? */ 4315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4316 mqd->cp_hqd_pq_doorbell_control); 4317 4318 /* disable the queue if it's active */ 4319 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4320 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4321 for (j = 0; j < adev->usec_timeout; j++) { 4322 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4323 break; 4324 udelay(1); 4325 } 4326 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4327 mqd->cp_hqd_dequeue_request); 4328 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4329 mqd->cp_hqd_pq_rptr); 4330 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4331 mqd->cp_hqd_pq_wptr_lo); 4332 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4333 mqd->cp_hqd_pq_wptr_hi); 4334 } 4335 4336 /* set the pointer to the MQD */ 4337 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4338 mqd->cp_mqd_base_addr_lo); 4339 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4340 mqd->cp_mqd_base_addr_hi); 4341 4342 /* set MQD vmid to 0 */ 4343 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4344 mqd->cp_mqd_control); 4345 4346 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4348 mqd->cp_hqd_pq_base_lo); 4349 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4350 mqd->cp_hqd_pq_base_hi); 4351 4352 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4353 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4354 mqd->cp_hqd_pq_control); 4355 4356 /* set the wb address whether it's enabled or not */ 4357 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4358 mqd->cp_hqd_pq_rptr_report_addr_lo); 4359 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4360 mqd->cp_hqd_pq_rptr_report_addr_hi); 4361 4362 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4363 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4364 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4365 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4366 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4367 4368 /* enable the doorbell if requested */ 4369 if (ring->use_doorbell) { 4370 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4371 (adev->doorbell_index.kiq * 2) << 2); 4372 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4373 (adev->doorbell_index.userqueue_end * 2) << 2); 4374 } 4375 4376 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4377 mqd->cp_hqd_pq_doorbell_control); 4378 4379 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4380 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4381 mqd->cp_hqd_pq_wptr_lo); 4382 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4383 mqd->cp_hqd_pq_wptr_hi); 4384 4385 /* set the vmid for the queue */ 4386 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4387 4388 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4389 mqd->cp_hqd_persistent_state); 4390 4391 /* activate the queue */ 4392 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4393 mqd->cp_hqd_active); 4394 4395 if (ring->use_doorbell) 4396 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4397 4398 return 0; 4399 } 4400 4401 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4402 { 4403 struct amdgpu_device *adev = ring->adev; 4404 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4405 4406 gfx_v11_0_kiq_setting(ring); 4407 4408 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4409 /* reset MQD to a clean status */ 4410 if (adev->gfx.kiq[0].mqd_backup) 4411 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4412 4413 /* reset ring buffer */ 4414 ring->wptr = 0; 4415 amdgpu_ring_clear_ring(ring); 4416 4417 mutex_lock(&adev->srbm_mutex); 4418 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4419 gfx_v11_0_kiq_init_register(ring); 4420 soc21_grbm_select(adev, 0, 0, 0, 0); 4421 mutex_unlock(&adev->srbm_mutex); 4422 } else { 4423 memset((void *)mqd, 0, sizeof(*mqd)); 4424 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4425 amdgpu_ring_clear_ring(ring); 4426 mutex_lock(&adev->srbm_mutex); 4427 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4428 amdgpu_ring_init_mqd(ring); 4429 gfx_v11_0_kiq_init_register(ring); 4430 soc21_grbm_select(adev, 0, 0, 0, 0); 4431 mutex_unlock(&adev->srbm_mutex); 4432 4433 if (adev->gfx.kiq[0].mqd_backup) 4434 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4435 } 4436 4437 return 0; 4438 } 4439 4440 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 4441 { 4442 struct amdgpu_device *adev = ring->adev; 4443 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4444 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4445 4446 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4447 memset((void *)mqd, 0, sizeof(*mqd)); 4448 mutex_lock(&adev->srbm_mutex); 4449 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4450 amdgpu_ring_init_mqd(ring); 4451 soc21_grbm_select(adev, 0, 0, 0, 0); 4452 mutex_unlock(&adev->srbm_mutex); 4453 4454 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4455 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4456 } else { 4457 /* restore MQD to a clean status */ 4458 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4459 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4460 /* reset ring buffer */ 4461 ring->wptr = 0; 4462 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4463 amdgpu_ring_clear_ring(ring); 4464 } 4465 4466 return 0; 4467 } 4468 4469 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4470 { 4471 gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 4472 return 0; 4473 } 4474 4475 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4476 { 4477 int i, r; 4478 4479 if (!amdgpu_async_gfx_ring) 4480 gfx_v11_0_cp_compute_enable(adev, true); 4481 4482 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4483 r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 4484 if (r) 4485 return r; 4486 } 4487 4488 return amdgpu_gfx_enable_kcq(adev, 0); 4489 } 4490 4491 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4492 { 4493 int r, i; 4494 struct amdgpu_ring *ring; 4495 4496 if (!(adev->flags & AMD_IS_APU)) 4497 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4498 4499 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4500 /* legacy firmware loading */ 4501 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4502 if (r) 4503 return r; 4504 4505 if (adev->gfx.rs64_enable) 4506 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4507 else 4508 r = gfx_v11_0_cp_compute_load_microcode(adev); 4509 if (r) 4510 return r; 4511 } 4512 4513 gfx_v11_0_cp_set_doorbell_range(adev); 4514 4515 if (amdgpu_async_gfx_ring) { 4516 gfx_v11_0_cp_compute_enable(adev, true); 4517 gfx_v11_0_cp_gfx_enable(adev, true); 4518 } 4519 4520 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4521 r = amdgpu_mes_kiq_hw_init(adev); 4522 else 4523 r = gfx_v11_0_kiq_resume(adev); 4524 if (r) 4525 return r; 4526 4527 r = gfx_v11_0_kcq_resume(adev); 4528 if (r) 4529 return r; 4530 4531 if (!amdgpu_async_gfx_ring) { 4532 r = gfx_v11_0_cp_gfx_resume(adev); 4533 if (r) 4534 return r; 4535 } else { 4536 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4537 if (r) 4538 return r; 4539 } 4540 4541 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4542 ring = &adev->gfx.gfx_ring[i]; 4543 r = amdgpu_ring_test_helper(ring); 4544 if (r) 4545 return r; 4546 } 4547 4548 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4549 ring = &adev->gfx.compute_ring[i]; 4550 r = amdgpu_ring_test_helper(ring); 4551 if (r) 4552 return r; 4553 } 4554 4555 return 0; 4556 } 4557 4558 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4559 { 4560 gfx_v11_0_cp_gfx_enable(adev, enable); 4561 gfx_v11_0_cp_compute_enable(adev, enable); 4562 } 4563 4564 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4565 { 4566 int r; 4567 bool value; 4568 4569 r = adev->gfxhub.funcs->gart_enable(adev); 4570 if (r) 4571 return r; 4572 4573 adev->hdp.funcs->flush_hdp(adev, NULL); 4574 4575 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4576 false : true; 4577 4578 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4579 /* TODO investigate why this and the hdp flush above is needed, 4580 * are we missing a flush somewhere else? */ 4581 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4582 4583 return 0; 4584 } 4585 4586 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4587 { 4588 u32 tmp; 4589 4590 /* select RS64 */ 4591 if (adev->gfx.rs64_enable) { 4592 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4593 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4594 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4595 4596 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4597 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4598 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4599 } 4600 4601 if (amdgpu_emu_mode == 1) 4602 msleep(100); 4603 } 4604 4605 static int get_gb_addr_config(struct amdgpu_device * adev) 4606 { 4607 u32 gb_addr_config; 4608 4609 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4610 if (gb_addr_config == 0) 4611 return -EINVAL; 4612 4613 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4614 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4615 4616 adev->gfx.config.gb_addr_config = gb_addr_config; 4617 4618 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4619 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4620 GB_ADDR_CONFIG, NUM_PIPES); 4621 4622 adev->gfx.config.max_tile_pipes = 4623 adev->gfx.config.gb_addr_config_fields.num_pipes; 4624 4625 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4626 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4627 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4628 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4629 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4630 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4631 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4632 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4633 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4634 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4635 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4636 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4637 4638 return 0; 4639 } 4640 4641 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4642 { 4643 uint32_t data; 4644 4645 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4646 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4647 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4648 4649 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4650 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4651 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4652 } 4653 4654 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4655 { 4656 int r; 4657 struct amdgpu_device *adev = ip_block->adev; 4658 4659 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4660 adev->gfx.cleaner_shader_ptr); 4661 4662 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4663 if (adev->gfx.imu.funcs) { 4664 /* RLC autoload sequence 1: Program rlc ram */ 4665 if (adev->gfx.imu.funcs->program_rlc_ram) 4666 adev->gfx.imu.funcs->program_rlc_ram(adev); 4667 /* rlc autoload firmware */ 4668 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4669 if (r) 4670 return r; 4671 } 4672 } else { 4673 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4674 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4675 if (adev->gfx.imu.funcs->load_microcode) 4676 adev->gfx.imu.funcs->load_microcode(adev); 4677 if (adev->gfx.imu.funcs->setup_imu) 4678 adev->gfx.imu.funcs->setup_imu(adev); 4679 if (adev->gfx.imu.funcs->start_imu) 4680 adev->gfx.imu.funcs->start_imu(adev); 4681 } 4682 4683 /* disable gpa mode in backdoor loading */ 4684 gfx_v11_0_disable_gpa_mode(adev); 4685 } 4686 } 4687 4688 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4689 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4690 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4691 if (r) { 4692 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4693 return r; 4694 } 4695 } 4696 4697 adev->gfx.is_poweron = true; 4698 4699 if(get_gb_addr_config(adev)) 4700 DRM_WARN("Invalid gb_addr_config !\n"); 4701 4702 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4703 adev->gfx.rs64_enable) 4704 gfx_v11_0_config_gfx_rs64(adev); 4705 4706 r = gfx_v11_0_gfxhub_enable(adev); 4707 if (r) 4708 return r; 4709 4710 if (!amdgpu_emu_mode) 4711 gfx_v11_0_init_golden_registers(adev); 4712 4713 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4714 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4715 /** 4716 * For gfx 11, rlc firmware loading relies on smu firmware is 4717 * loaded firstly, so in direct type, it has to load smc ucode 4718 * here before rlc. 4719 */ 4720 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4721 if (r) 4722 return r; 4723 } 4724 4725 gfx_v11_0_constants_init(adev); 4726 4727 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4728 gfx_v11_0_select_cp_fw_arch(adev); 4729 4730 if (adev->nbio.funcs->gc_doorbell_init) 4731 adev->nbio.funcs->gc_doorbell_init(adev); 4732 4733 r = gfx_v11_0_rlc_resume(adev); 4734 if (r) 4735 return r; 4736 4737 /* 4738 * init golden registers and rlc resume may override some registers, 4739 * reconfig them here 4740 */ 4741 gfx_v11_0_tcp_harvest(adev); 4742 4743 r = gfx_v11_0_cp_resume(adev); 4744 if (r) 4745 return r; 4746 4747 /* get IMU version from HW if it's not set */ 4748 if (!adev->gfx.imu_fw_version) 4749 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4750 4751 return r; 4752 } 4753 4754 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 4755 { 4756 struct amdgpu_device *adev = ip_block->adev; 4757 4758 cancel_delayed_work_sync(&adev->gfx.idle_work); 4759 4760 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4761 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4762 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4763 4764 if (!adev->no_hw_access) { 4765 if (amdgpu_async_gfx_ring) { 4766 if (amdgpu_gfx_disable_kgq(adev, 0)) 4767 DRM_ERROR("KGQ disable failed\n"); 4768 } 4769 4770 if (amdgpu_gfx_disable_kcq(adev, 0)) 4771 DRM_ERROR("KCQ disable failed\n"); 4772 4773 amdgpu_mes_kiq_hw_fini(adev); 4774 } 4775 4776 if (amdgpu_sriov_vf(adev)) 4777 /* Remove the steps disabling CPG and clearing KIQ position, 4778 * so that CP could perform IDLE-SAVE during switch. Those 4779 * steps are necessary to avoid a DMAR error in gfx9 but it is 4780 * not reproduced on gfx11. 4781 */ 4782 return 0; 4783 4784 gfx_v11_0_cp_enable(adev, false); 4785 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4786 4787 adev->gfxhub.funcs->gart_disable(adev); 4788 4789 adev->gfx.is_poweron = false; 4790 4791 return 0; 4792 } 4793 4794 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 4795 { 4796 return gfx_v11_0_hw_fini(ip_block); 4797 } 4798 4799 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 4800 { 4801 return gfx_v11_0_hw_init(ip_block); 4802 } 4803 4804 static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 4805 { 4806 struct amdgpu_device *adev = ip_block->adev; 4807 4808 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4809 GRBM_STATUS, GUI_ACTIVE)) 4810 return false; 4811 else 4812 return true; 4813 } 4814 4815 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4816 { 4817 unsigned i; 4818 u32 tmp; 4819 struct amdgpu_device *adev = ip_block->adev; 4820 4821 for (i = 0; i < adev->usec_timeout; i++) { 4822 /* read MC_STATUS */ 4823 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4824 GRBM_STATUS__GUI_ACTIVE_MASK; 4825 4826 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4827 return 0; 4828 udelay(1); 4829 } 4830 return -ETIMEDOUT; 4831 } 4832 4833 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4834 bool req) 4835 { 4836 u32 i, tmp, val; 4837 4838 for (i = 0; i < adev->usec_timeout; i++) { 4839 /* Request with MeId=2, PipeId=0 */ 4840 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4841 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4842 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4843 4844 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4845 if (req) { 4846 if (val == tmp) 4847 break; 4848 } else { 4849 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4850 REQUEST, 1); 4851 4852 /* unlocked or locked by firmware */ 4853 if (val != tmp) 4854 break; 4855 } 4856 udelay(1); 4857 } 4858 4859 if (i >= adev->usec_timeout) 4860 return -EINVAL; 4861 4862 return 0; 4863 } 4864 4865 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 4866 { 4867 u32 grbm_soft_reset = 0; 4868 u32 tmp; 4869 int r, i, j, k; 4870 struct amdgpu_device *adev = ip_block->adev; 4871 4872 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4873 4874 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4875 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4876 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4877 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4878 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4879 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4880 4881 mutex_lock(&adev->srbm_mutex); 4882 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4883 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4884 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4885 soc21_grbm_select(adev, i, k, j, 0); 4886 4887 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4888 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4889 } 4890 } 4891 } 4892 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4893 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4894 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4895 soc21_grbm_select(adev, i, k, j, 0); 4896 4897 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4898 } 4899 } 4900 } 4901 soc21_grbm_select(adev, 0, 0, 0, 0); 4902 mutex_unlock(&adev->srbm_mutex); 4903 4904 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4905 mutex_lock(&adev->gfx.reset_sem_mutex); 4906 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 4907 if (r) { 4908 mutex_unlock(&adev->gfx.reset_sem_mutex); 4909 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 4910 return r; 4911 } 4912 4913 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4914 4915 // Read CP_VMID_RESET register three times. 4916 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4917 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4918 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4919 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4920 4921 /* release the gfx mutex */ 4922 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 4923 mutex_unlock(&adev->gfx.reset_sem_mutex); 4924 if (r) { 4925 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 4926 return r; 4927 } 4928 4929 for (i = 0; i < adev->usec_timeout; i++) { 4930 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4931 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4932 break; 4933 udelay(1); 4934 } 4935 if (i >= adev->usec_timeout) { 4936 printk("Failed to wait all pipes clean\n"); 4937 return -EINVAL; 4938 } 4939 4940 /********** trigger soft reset ***********/ 4941 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4942 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4943 SOFT_RESET_CP, 1); 4944 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4945 SOFT_RESET_GFX, 1); 4946 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4947 SOFT_RESET_CPF, 1); 4948 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4949 SOFT_RESET_CPC, 1); 4950 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4951 SOFT_RESET_CPG, 1); 4952 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4953 /********** exit soft reset ***********/ 4954 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4955 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4956 SOFT_RESET_CP, 0); 4957 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4958 SOFT_RESET_GFX, 0); 4959 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4960 SOFT_RESET_CPF, 0); 4961 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4962 SOFT_RESET_CPC, 0); 4963 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4964 SOFT_RESET_CPG, 0); 4965 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4966 4967 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4968 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4969 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4970 4971 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4972 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4973 4974 for (i = 0; i < adev->usec_timeout; i++) { 4975 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4976 break; 4977 udelay(1); 4978 } 4979 if (i >= adev->usec_timeout) { 4980 printk("Failed to wait CP_VMID_RESET to 0\n"); 4981 return -EINVAL; 4982 } 4983 4984 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4985 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4986 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4987 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4988 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4989 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4990 4991 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4992 4993 return gfx_v11_0_cp_resume(adev); 4994 } 4995 4996 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 4997 { 4998 int i, r; 4999 struct amdgpu_device *adev = ip_block->adev; 5000 struct amdgpu_ring *ring; 5001 long tmo = msecs_to_jiffies(1000); 5002 5003 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5004 ring = &adev->gfx.gfx_ring[i]; 5005 r = amdgpu_ring_test_ib(ring, tmo); 5006 if (r) 5007 return true; 5008 } 5009 5010 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5011 ring = &adev->gfx.compute_ring[i]; 5012 r = amdgpu_ring_test_ib(ring, tmo); 5013 if (r) 5014 return true; 5015 } 5016 5017 return false; 5018 } 5019 5020 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5021 { 5022 struct amdgpu_device *adev = ip_block->adev; 5023 /** 5024 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 5025 */ 5026 return amdgpu_mes_resume(adev); 5027 } 5028 5029 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5030 { 5031 uint64_t clock; 5032 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5033 5034 if (amdgpu_sriov_vf(adev)) { 5035 amdgpu_gfx_off_ctrl(adev, false); 5036 mutex_lock(&adev->gfx.gpu_clock_mutex); 5037 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5038 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5039 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5040 if (clock_counter_hi_pre != clock_counter_hi_after) 5041 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5042 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5043 amdgpu_gfx_off_ctrl(adev, true); 5044 } else { 5045 preempt_disable(); 5046 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5047 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5048 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5049 if (clock_counter_hi_pre != clock_counter_hi_after) 5050 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5051 preempt_enable(); 5052 } 5053 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5054 5055 return clock; 5056 } 5057 5058 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5059 uint32_t vmid, 5060 uint32_t gds_base, uint32_t gds_size, 5061 uint32_t gws_base, uint32_t gws_size, 5062 uint32_t oa_base, uint32_t oa_size) 5063 { 5064 struct amdgpu_device *adev = ring->adev; 5065 5066 /* GDS Base */ 5067 gfx_v11_0_write_data_to_reg(ring, 0, false, 5068 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5069 gds_base); 5070 5071 /* GDS Size */ 5072 gfx_v11_0_write_data_to_reg(ring, 0, false, 5073 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5074 gds_size); 5075 5076 /* GWS */ 5077 gfx_v11_0_write_data_to_reg(ring, 0, false, 5078 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5079 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5080 5081 /* OA */ 5082 gfx_v11_0_write_data_to_reg(ring, 0, false, 5083 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5084 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5085 } 5086 5087 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5088 { 5089 struct amdgpu_device *adev = ip_block->adev; 5090 5091 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5092 5093 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5094 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5095 AMDGPU_MAX_COMPUTE_RINGS); 5096 5097 gfx_v11_0_set_kiq_pm4_funcs(adev); 5098 gfx_v11_0_set_ring_funcs(adev); 5099 gfx_v11_0_set_irq_funcs(adev); 5100 gfx_v11_0_set_gds_init(adev); 5101 gfx_v11_0_set_rlc_funcs(adev); 5102 gfx_v11_0_set_mqd_funcs(adev); 5103 gfx_v11_0_set_imu_funcs(adev); 5104 5105 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5106 5107 return gfx_v11_0_init_microcode(adev); 5108 } 5109 5110 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) 5111 { 5112 struct amdgpu_device *adev = ip_block->adev; 5113 int r; 5114 5115 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5116 if (r) 5117 return r; 5118 5119 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5120 if (r) 5121 return r; 5122 5123 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5124 if (r) 5125 return r; 5126 return 0; 5127 } 5128 5129 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5130 { 5131 uint32_t rlc_cntl; 5132 5133 /* if RLC is not enabled, do nothing */ 5134 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5135 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5136 } 5137 5138 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5139 { 5140 uint32_t data; 5141 unsigned i; 5142 5143 data = RLC_SAFE_MODE__CMD_MASK; 5144 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5145 5146 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5147 5148 /* wait for RLC_SAFE_MODE */ 5149 for (i = 0; i < adev->usec_timeout; i++) { 5150 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5151 RLC_SAFE_MODE, CMD)) 5152 break; 5153 udelay(1); 5154 } 5155 } 5156 5157 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5158 { 5159 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5160 } 5161 5162 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5163 bool enable) 5164 { 5165 uint32_t def, data; 5166 5167 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5168 return; 5169 5170 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5171 5172 if (enable) 5173 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5174 else 5175 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5176 5177 if (def != data) 5178 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5179 } 5180 5181 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5182 bool enable) 5183 { 5184 uint32_t def, data; 5185 5186 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5187 return; 5188 5189 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5190 5191 if (enable) 5192 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5193 else 5194 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5195 5196 if (def != data) 5197 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5198 } 5199 5200 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5201 bool enable) 5202 { 5203 uint32_t def, data; 5204 5205 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5206 return; 5207 5208 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5209 5210 if (enable) 5211 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5212 else 5213 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5214 5215 if (def != data) 5216 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5217 } 5218 5219 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5220 bool enable) 5221 { 5222 uint32_t data, def; 5223 5224 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5225 return; 5226 5227 /* It is disabled by HW by default */ 5228 if (enable) { 5229 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5230 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5231 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5232 5233 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5234 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5235 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5236 5237 if (def != data) 5238 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5239 } 5240 } else { 5241 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5242 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5243 5244 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5245 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5246 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5247 5248 if (def != data) 5249 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5250 } 5251 } 5252 } 5253 5254 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5255 bool enable) 5256 { 5257 uint32_t def, data; 5258 5259 if (!(adev->cg_flags & 5260 (AMD_CG_SUPPORT_GFX_CGCG | 5261 AMD_CG_SUPPORT_GFX_CGLS | 5262 AMD_CG_SUPPORT_GFX_3D_CGCG | 5263 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5264 return; 5265 5266 if (enable) { 5267 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5268 5269 /* unset CGCG override */ 5270 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5271 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5272 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5273 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5274 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5275 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5276 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5277 5278 /* update CGCG override bits */ 5279 if (def != data) 5280 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5281 5282 /* enable cgcg FSM(0x0000363F) */ 5283 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5284 5285 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5286 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5287 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5288 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5289 } 5290 5291 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5292 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5293 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5294 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5295 } 5296 5297 if (def != data) 5298 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5299 5300 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5301 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5302 5303 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5304 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5305 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5306 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5307 } 5308 5309 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5310 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5311 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5312 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5313 } 5314 5315 if (def != data) 5316 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5317 5318 /* set IDLE_POLL_COUNT(0x00900100) */ 5319 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5320 5321 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5322 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5323 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5324 5325 if (def != data) 5326 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5327 5328 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5329 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5330 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5331 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5332 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5333 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5334 5335 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5336 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5337 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5338 5339 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5340 if (adev->sdma.num_instances > 1) { 5341 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5342 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5343 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5344 } 5345 } else { 5346 /* Program RLC_CGCG_CGLS_CTRL */ 5347 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5348 5349 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5350 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5351 5352 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5353 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5354 5355 if (def != data) 5356 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5357 5358 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5359 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5360 5361 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5362 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5363 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5364 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5365 5366 if (def != data) 5367 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5368 5369 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5370 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5371 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5372 5373 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5374 if (adev->sdma.num_instances > 1) { 5375 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5376 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5377 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5378 } 5379 } 5380 } 5381 5382 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5383 bool enable) 5384 { 5385 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5386 5387 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5388 5389 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5390 5391 gfx_v11_0_update_repeater_fgcg(adev, enable); 5392 5393 gfx_v11_0_update_sram_fgcg(adev, enable); 5394 5395 gfx_v11_0_update_perf_clk(adev, enable); 5396 5397 if (adev->cg_flags & 5398 (AMD_CG_SUPPORT_GFX_MGCG | 5399 AMD_CG_SUPPORT_GFX_CGLS | 5400 AMD_CG_SUPPORT_GFX_CGCG | 5401 AMD_CG_SUPPORT_GFX_3D_CGCG | 5402 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5403 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5404 5405 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5406 5407 return 0; 5408 } 5409 5410 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5411 { 5412 u32 reg, pre_data, data; 5413 5414 amdgpu_gfx_off_ctrl(adev, false); 5415 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5416 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5417 pre_data = RREG32_NO_KIQ(reg); 5418 else 5419 pre_data = RREG32(reg); 5420 5421 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5422 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5423 5424 if (pre_data != data) { 5425 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5426 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5427 } else 5428 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5429 } 5430 amdgpu_gfx_off_ctrl(adev, true); 5431 5432 if (ring 5433 && amdgpu_sriov_is_pp_one_vf(adev) 5434 && (pre_data != data) 5435 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5436 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5437 amdgpu_ring_emit_wreg(ring, reg, data); 5438 } 5439 } 5440 5441 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5442 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5443 .set_safe_mode = gfx_v11_0_set_safe_mode, 5444 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5445 .init = gfx_v11_0_rlc_init, 5446 .get_csb_size = gfx_v11_0_get_csb_size, 5447 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5448 .resume = gfx_v11_0_rlc_resume, 5449 .stop = gfx_v11_0_rlc_stop, 5450 .reset = gfx_v11_0_rlc_reset, 5451 .start = gfx_v11_0_rlc_start, 5452 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5453 }; 5454 5455 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5456 { 5457 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5458 5459 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5460 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5461 else 5462 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5463 5464 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5465 5466 // Program RLC_PG_DELAY3 for CGPG hysteresis 5467 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5468 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5469 case IP_VERSION(11, 0, 1): 5470 case IP_VERSION(11, 0, 4): 5471 case IP_VERSION(11, 5, 0): 5472 case IP_VERSION(11, 5, 1): 5473 case IP_VERSION(11, 5, 2): 5474 case IP_VERSION(11, 5, 3): 5475 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5476 break; 5477 default: 5478 break; 5479 } 5480 } 5481 } 5482 5483 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5484 { 5485 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5486 5487 gfx_v11_cntl_power_gating(adev, enable); 5488 5489 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5490 } 5491 5492 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5493 enum amd_powergating_state state) 5494 { 5495 struct amdgpu_device *adev = ip_block->adev; 5496 bool enable = (state == AMD_PG_STATE_GATE); 5497 5498 if (amdgpu_sriov_vf(adev)) 5499 return 0; 5500 5501 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5502 case IP_VERSION(11, 0, 0): 5503 case IP_VERSION(11, 0, 2): 5504 case IP_VERSION(11, 0, 3): 5505 amdgpu_gfx_off_ctrl(adev, enable); 5506 break; 5507 case IP_VERSION(11, 0, 1): 5508 case IP_VERSION(11, 0, 4): 5509 case IP_VERSION(11, 5, 0): 5510 case IP_VERSION(11, 5, 1): 5511 case IP_VERSION(11, 5, 2): 5512 case IP_VERSION(11, 5, 3): 5513 if (!enable) 5514 amdgpu_gfx_off_ctrl(adev, false); 5515 5516 gfx_v11_cntl_pg(adev, enable); 5517 5518 if (enable) 5519 amdgpu_gfx_off_ctrl(adev, true); 5520 5521 break; 5522 default: 5523 break; 5524 } 5525 5526 return 0; 5527 } 5528 5529 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5530 enum amd_clockgating_state state) 5531 { 5532 struct amdgpu_device *adev = ip_block->adev; 5533 5534 if (amdgpu_sriov_vf(adev)) 5535 return 0; 5536 5537 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5538 case IP_VERSION(11, 0, 0): 5539 case IP_VERSION(11, 0, 1): 5540 case IP_VERSION(11, 0, 2): 5541 case IP_VERSION(11, 0, 3): 5542 case IP_VERSION(11, 0, 4): 5543 case IP_VERSION(11, 5, 0): 5544 case IP_VERSION(11, 5, 1): 5545 case IP_VERSION(11, 5, 2): 5546 case IP_VERSION(11, 5, 3): 5547 gfx_v11_0_update_gfx_clock_gating(adev, 5548 state == AMD_CG_STATE_GATE); 5549 break; 5550 default: 5551 break; 5552 } 5553 5554 return 0; 5555 } 5556 5557 static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 5558 { 5559 struct amdgpu_device *adev = ip_block->adev; 5560 int data; 5561 5562 /* AMD_CG_SUPPORT_GFX_MGCG */ 5563 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5564 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5565 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5566 5567 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5568 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5569 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5570 5571 /* AMD_CG_SUPPORT_GFX_FGCG */ 5572 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5573 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5574 5575 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5576 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5577 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5578 5579 /* AMD_CG_SUPPORT_GFX_CGCG */ 5580 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5581 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5582 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5583 5584 /* AMD_CG_SUPPORT_GFX_CGLS */ 5585 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5586 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5587 5588 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5589 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5590 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5591 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5592 5593 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5594 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5595 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5596 } 5597 5598 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5599 { 5600 /* gfx11 is 32bit rptr*/ 5601 return *(uint32_t *)ring->rptr_cpu_addr; 5602 } 5603 5604 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5605 { 5606 struct amdgpu_device *adev = ring->adev; 5607 u64 wptr; 5608 5609 /* XXX check if swapping is necessary on BE */ 5610 if (ring->use_doorbell) { 5611 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5612 } else { 5613 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5614 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5615 } 5616 5617 return wptr; 5618 } 5619 5620 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5621 { 5622 struct amdgpu_device *adev = ring->adev; 5623 5624 if (ring->use_doorbell) { 5625 /* XXX check if swapping is necessary on BE */ 5626 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5627 ring->wptr); 5628 WDOORBELL64(ring->doorbell_index, ring->wptr); 5629 } else { 5630 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5631 lower_32_bits(ring->wptr)); 5632 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5633 upper_32_bits(ring->wptr)); 5634 } 5635 } 5636 5637 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5638 { 5639 /* gfx11 hardware is 32bit rptr */ 5640 return *(uint32_t *)ring->rptr_cpu_addr; 5641 } 5642 5643 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5644 { 5645 u64 wptr; 5646 5647 /* XXX check if swapping is necessary on BE */ 5648 if (ring->use_doorbell) 5649 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5650 else 5651 BUG(); 5652 return wptr; 5653 } 5654 5655 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5656 { 5657 struct amdgpu_device *adev = ring->adev; 5658 5659 /* XXX check if swapping is necessary on BE */ 5660 if (ring->use_doorbell) { 5661 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5662 ring->wptr); 5663 WDOORBELL64(ring->doorbell_index, ring->wptr); 5664 } else { 5665 BUG(); /* only DOORBELL method supported on gfx11 now */ 5666 } 5667 } 5668 5669 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5670 { 5671 struct amdgpu_device *adev = ring->adev; 5672 u32 ref_and_mask, reg_mem_engine; 5673 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5674 5675 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5676 switch (ring->me) { 5677 case 1: 5678 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5679 break; 5680 case 2: 5681 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5682 break; 5683 default: 5684 return; 5685 } 5686 reg_mem_engine = 0; 5687 } else { 5688 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5689 reg_mem_engine = 1; /* pfp */ 5690 } 5691 5692 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5693 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5694 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5695 ref_and_mask, ref_and_mask, 0x20); 5696 } 5697 5698 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5699 struct amdgpu_job *job, 5700 struct amdgpu_ib *ib, 5701 uint32_t flags) 5702 { 5703 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5704 u32 header, control = 0; 5705 5706 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5707 5708 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5709 5710 control |= ib->length_dw | (vmid << 24); 5711 5712 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5713 control |= INDIRECT_BUFFER_PRE_ENB(1); 5714 5715 if (flags & AMDGPU_IB_PREEMPTED) 5716 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5717 5718 if (vmid) 5719 gfx_v11_0_ring_emit_de_meta(ring, 5720 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5721 } 5722 5723 if (ring->is_mes_queue) 5724 /* inherit vmid from mqd */ 5725 control |= 0x400000; 5726 5727 amdgpu_ring_write(ring, header); 5728 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5729 amdgpu_ring_write(ring, 5730 #ifdef __BIG_ENDIAN 5731 (2 << 0) | 5732 #endif 5733 lower_32_bits(ib->gpu_addr)); 5734 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5735 amdgpu_ring_write(ring, control); 5736 } 5737 5738 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5739 struct amdgpu_job *job, 5740 struct amdgpu_ib *ib, 5741 uint32_t flags) 5742 { 5743 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5744 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5745 5746 if (ring->is_mes_queue) 5747 /* inherit vmid from mqd */ 5748 control |= 0x40000000; 5749 5750 /* Currently, there is a high possibility to get wave ID mismatch 5751 * between ME and GDS, leading to a hw deadlock, because ME generates 5752 * different wave IDs than the GDS expects. This situation happens 5753 * randomly when at least 5 compute pipes use GDS ordered append. 5754 * The wave IDs generated by ME are also wrong after suspend/resume. 5755 * Those are probably bugs somewhere else in the kernel driver. 5756 * 5757 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5758 * GDS to 0 for this ring (me/pipe). 5759 */ 5760 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5761 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5762 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5763 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5764 } 5765 5766 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5767 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5768 amdgpu_ring_write(ring, 5769 #ifdef __BIG_ENDIAN 5770 (2 << 0) | 5771 #endif 5772 lower_32_bits(ib->gpu_addr)); 5773 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5774 amdgpu_ring_write(ring, control); 5775 } 5776 5777 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5778 u64 seq, unsigned flags) 5779 { 5780 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5781 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5782 5783 /* RELEASE_MEM - flush caches, send int */ 5784 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5785 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5786 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5787 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5788 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5789 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5790 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5791 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5792 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5793 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5794 5795 /* 5796 * the address should be Qword aligned if 64bit write, Dword 5797 * aligned if only send 32bit data low (discard data high) 5798 */ 5799 if (write64bit) 5800 BUG_ON(addr & 0x7); 5801 else 5802 BUG_ON(addr & 0x3); 5803 amdgpu_ring_write(ring, lower_32_bits(addr)); 5804 amdgpu_ring_write(ring, upper_32_bits(addr)); 5805 amdgpu_ring_write(ring, lower_32_bits(seq)); 5806 amdgpu_ring_write(ring, upper_32_bits(seq)); 5807 amdgpu_ring_write(ring, ring->is_mes_queue ? 5808 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5809 } 5810 5811 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5812 { 5813 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5814 uint32_t seq = ring->fence_drv.sync_seq; 5815 uint64_t addr = ring->fence_drv.gpu_addr; 5816 5817 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5818 upper_32_bits(addr), seq, 0xffffffff, 4); 5819 } 5820 5821 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5822 uint16_t pasid, uint32_t flush_type, 5823 bool all_hub, uint8_t dst_sel) 5824 { 5825 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5826 amdgpu_ring_write(ring, 5827 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5828 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5829 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5830 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5831 } 5832 5833 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5834 unsigned vmid, uint64_t pd_addr) 5835 { 5836 if (ring->is_mes_queue) 5837 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5838 else 5839 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5840 5841 /* compute doesn't have PFP */ 5842 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5843 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5844 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5845 amdgpu_ring_write(ring, 0x0); 5846 } 5847 5848 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5849 * changed in any way. 5850 */ 5851 ring->set_q_mode_offs = 0; 5852 ring->set_q_mode_ptr = NULL; 5853 } 5854 5855 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5856 u64 seq, unsigned int flags) 5857 { 5858 struct amdgpu_device *adev = ring->adev; 5859 5860 /* we only allocate 32bit for each seq wb address */ 5861 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5862 5863 /* write fence seq to the "addr" */ 5864 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5865 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5866 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5867 amdgpu_ring_write(ring, lower_32_bits(addr)); 5868 amdgpu_ring_write(ring, upper_32_bits(addr)); 5869 amdgpu_ring_write(ring, lower_32_bits(seq)); 5870 5871 if (flags & AMDGPU_FENCE_FLAG_INT) { 5872 /* set register to trigger INT */ 5873 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5874 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5875 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5876 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5877 amdgpu_ring_write(ring, 0); 5878 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5879 } 5880 } 5881 5882 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5883 uint32_t flags) 5884 { 5885 uint32_t dw2 = 0; 5886 5887 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5888 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5889 /* set load_global_config & load_global_uconfig */ 5890 dw2 |= 0x8001; 5891 /* set load_cs_sh_regs */ 5892 dw2 |= 0x01000000; 5893 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5894 dw2 |= 0x10002; 5895 } 5896 5897 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5898 amdgpu_ring_write(ring, dw2); 5899 amdgpu_ring_write(ring, 0); 5900 } 5901 5902 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5903 uint64_t addr) 5904 { 5905 unsigned ret; 5906 5907 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5908 amdgpu_ring_write(ring, lower_32_bits(addr)); 5909 amdgpu_ring_write(ring, upper_32_bits(addr)); 5910 /* discard following DWs if *cond_exec_gpu_addr==0 */ 5911 amdgpu_ring_write(ring, 0); 5912 ret = ring->wptr & ring->buf_mask; 5913 /* patch dummy value later */ 5914 amdgpu_ring_write(ring, 0); 5915 5916 return ret; 5917 } 5918 5919 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5920 u64 shadow_va, u64 csa_va, 5921 u64 gds_va, bool init_shadow, 5922 int vmid) 5923 { 5924 struct amdgpu_device *adev = ring->adev; 5925 unsigned int offs, end; 5926 5927 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 5928 return; 5929 5930 /* 5931 * The logic here isn't easy to understand because we need to keep state 5932 * accross multiple executions of the function as well as between the 5933 * CPU and GPU. The general idea is that the newly written GPU command 5934 * has a condition on the previous one and only executed if really 5935 * necessary. 5936 */ 5937 5938 /* 5939 * The dw in the NOP controls if the next SET_Q_MODE packet should be 5940 * executed or not. Reserve 64bits just to be on the save side. 5941 */ 5942 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 5943 offs = ring->wptr & ring->buf_mask; 5944 5945 /* 5946 * We start with skipping the prefix SET_Q_MODE and always executing 5947 * the postfix SET_Q_MODE packet. This is changed below with a 5948 * WRITE_DATA command when the postfix executed. 5949 */ 5950 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 5951 amdgpu_ring_write(ring, 0); 5952 5953 if (ring->set_q_mode_offs) { 5954 uint64_t addr; 5955 5956 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5957 addr += ring->set_q_mode_offs << 2; 5958 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 5959 } 5960 5961 /* 5962 * When the postfix SET_Q_MODE packet executes we need to make sure that the 5963 * next prefix SET_Q_MODE packet executes as well. 5964 */ 5965 if (!shadow_va) { 5966 uint64_t addr; 5967 5968 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5969 addr += offs << 2; 5970 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5971 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 5972 amdgpu_ring_write(ring, lower_32_bits(addr)); 5973 amdgpu_ring_write(ring, upper_32_bits(addr)); 5974 amdgpu_ring_write(ring, 0x1); 5975 } 5976 5977 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5978 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5979 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5980 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5981 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5982 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5983 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5984 amdgpu_ring_write(ring, shadow_va ? 5985 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5986 amdgpu_ring_write(ring, init_shadow ? 5987 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5988 5989 if (ring->set_q_mode_offs) 5990 amdgpu_ring_patch_cond_exec(ring, end); 5991 5992 if (shadow_va) { 5993 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 5994 5995 /* 5996 * If the tokens match try to skip the last postfix SET_Q_MODE 5997 * packet to avoid saving/restoring the state all the time. 5998 */ 5999 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 6000 *ring->set_q_mode_ptr = 0; 6001 6002 ring->set_q_mode_token = token; 6003 } else { 6004 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 6005 } 6006 6007 ring->set_q_mode_offs = offs; 6008 } 6009 6010 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 6011 { 6012 int i, r = 0; 6013 struct amdgpu_device *adev = ring->adev; 6014 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6015 struct amdgpu_ring *kiq_ring = &kiq->ring; 6016 unsigned long flags; 6017 6018 if (adev->enable_mes) 6019 return -EINVAL; 6020 6021 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6022 return -EINVAL; 6023 6024 spin_lock_irqsave(&kiq->ring_lock, flags); 6025 6026 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 6027 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6028 return -ENOMEM; 6029 } 6030 6031 /* assert preemption condition */ 6032 amdgpu_ring_set_preempt_cond_exec(ring, false); 6033 6034 /* assert IB preemption, emit the trailing fence */ 6035 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 6036 ring->trail_fence_gpu_addr, 6037 ++ring->trail_seq); 6038 amdgpu_ring_commit(kiq_ring); 6039 6040 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6041 6042 /* poll the trailing fence */ 6043 for (i = 0; i < adev->usec_timeout; i++) { 6044 if (ring->trail_seq == 6045 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 6046 break; 6047 udelay(1); 6048 } 6049 6050 if (i >= adev->usec_timeout) { 6051 r = -EINVAL; 6052 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 6053 } 6054 6055 /* deassert preemption condition */ 6056 amdgpu_ring_set_preempt_cond_exec(ring, true); 6057 return r; 6058 } 6059 6060 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6061 { 6062 struct amdgpu_device *adev = ring->adev; 6063 struct v10_de_ib_state de_payload = {0}; 6064 uint64_t offset, gds_addr, de_payload_gpu_addr; 6065 void *de_payload_cpu_addr; 6066 int cnt; 6067 6068 if (ring->is_mes_queue) { 6069 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 6070 gfx[0].gfx_meta_data) + 6071 offsetof(struct v10_gfx_meta_data, de_payload); 6072 de_payload_gpu_addr = 6073 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 6074 de_payload_cpu_addr = 6075 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 6076 6077 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 6078 gfx[0].gds_backup) + 6079 offsetof(struct v10_gfx_meta_data, de_payload); 6080 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 6081 } else { 6082 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6083 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6084 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6085 6086 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6087 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6088 PAGE_SIZE); 6089 } 6090 6091 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6092 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6093 6094 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6095 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6096 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6097 WRITE_DATA_DST_SEL(8) | 6098 WR_CONFIRM) | 6099 WRITE_DATA_CACHE_POLICY(0)); 6100 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6101 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6102 6103 if (resume) 6104 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6105 sizeof(de_payload) >> 2); 6106 else 6107 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6108 sizeof(de_payload) >> 2); 6109 } 6110 6111 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6112 bool secure) 6113 { 6114 uint32_t v = secure ? FRAME_TMZ : 0; 6115 6116 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6117 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6118 } 6119 6120 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6121 uint32_t reg_val_offs) 6122 { 6123 struct amdgpu_device *adev = ring->adev; 6124 6125 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6126 amdgpu_ring_write(ring, 0 | /* src: register*/ 6127 (5 << 8) | /* dst: memory */ 6128 (1 << 20)); /* write confirm */ 6129 amdgpu_ring_write(ring, reg); 6130 amdgpu_ring_write(ring, 0); 6131 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6132 reg_val_offs * 4)); 6133 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6134 reg_val_offs * 4)); 6135 } 6136 6137 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6138 uint32_t val) 6139 { 6140 uint32_t cmd = 0; 6141 6142 switch (ring->funcs->type) { 6143 case AMDGPU_RING_TYPE_GFX: 6144 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6145 break; 6146 case AMDGPU_RING_TYPE_KIQ: 6147 cmd = (1 << 16); /* no inc addr */ 6148 break; 6149 default: 6150 cmd = WR_CONFIRM; 6151 break; 6152 } 6153 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6154 amdgpu_ring_write(ring, cmd); 6155 amdgpu_ring_write(ring, reg); 6156 amdgpu_ring_write(ring, 0); 6157 amdgpu_ring_write(ring, val); 6158 } 6159 6160 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6161 uint32_t val, uint32_t mask) 6162 { 6163 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6164 } 6165 6166 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6167 uint32_t reg0, uint32_t reg1, 6168 uint32_t ref, uint32_t mask) 6169 { 6170 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6171 6172 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6173 ref, mask, 0x20); 6174 } 6175 6176 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 6177 unsigned vmid) 6178 { 6179 struct amdgpu_device *adev = ring->adev; 6180 uint32_t value = 0; 6181 6182 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6183 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6184 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6185 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6186 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 6187 WREG32_SOC15(GC, 0, regSQ_CMD, value); 6188 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 6189 } 6190 6191 static void 6192 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6193 uint32_t me, uint32_t pipe, 6194 enum amdgpu_interrupt_state state) 6195 { 6196 uint32_t cp_int_cntl, cp_int_cntl_reg; 6197 6198 if (!me) { 6199 switch (pipe) { 6200 case 0: 6201 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6202 break; 6203 case 1: 6204 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6205 break; 6206 default: 6207 DRM_DEBUG("invalid pipe %d\n", pipe); 6208 return; 6209 } 6210 } else { 6211 DRM_DEBUG("invalid me %d\n", me); 6212 return; 6213 } 6214 6215 switch (state) { 6216 case AMDGPU_IRQ_STATE_DISABLE: 6217 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6218 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6219 TIME_STAMP_INT_ENABLE, 0); 6220 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6221 GENERIC0_INT_ENABLE, 0); 6222 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6223 break; 6224 case AMDGPU_IRQ_STATE_ENABLE: 6225 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6226 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6227 TIME_STAMP_INT_ENABLE, 1); 6228 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6229 GENERIC0_INT_ENABLE, 1); 6230 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6231 break; 6232 default: 6233 break; 6234 } 6235 } 6236 6237 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6238 int me, int pipe, 6239 enum amdgpu_interrupt_state state) 6240 { 6241 u32 mec_int_cntl, mec_int_cntl_reg; 6242 6243 /* 6244 * amdgpu controls only the first MEC. That's why this function only 6245 * handles the setting of interrupts for this specific MEC. All other 6246 * pipes' interrupts are set by amdkfd. 6247 */ 6248 6249 if (me == 1) { 6250 switch (pipe) { 6251 case 0: 6252 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6253 break; 6254 case 1: 6255 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6256 break; 6257 case 2: 6258 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6259 break; 6260 case 3: 6261 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6262 break; 6263 default: 6264 DRM_DEBUG("invalid pipe %d\n", pipe); 6265 return; 6266 } 6267 } else { 6268 DRM_DEBUG("invalid me %d\n", me); 6269 return; 6270 } 6271 6272 switch (state) { 6273 case AMDGPU_IRQ_STATE_DISABLE: 6274 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6275 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6276 TIME_STAMP_INT_ENABLE, 0); 6277 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6278 GENERIC0_INT_ENABLE, 0); 6279 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6280 break; 6281 case AMDGPU_IRQ_STATE_ENABLE: 6282 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6283 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6284 TIME_STAMP_INT_ENABLE, 1); 6285 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6286 GENERIC0_INT_ENABLE, 1); 6287 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6288 break; 6289 default: 6290 break; 6291 } 6292 } 6293 6294 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6295 struct amdgpu_irq_src *src, 6296 unsigned type, 6297 enum amdgpu_interrupt_state state) 6298 { 6299 switch (type) { 6300 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6301 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6302 break; 6303 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6304 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6305 break; 6306 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6307 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6308 break; 6309 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6310 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6311 break; 6312 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6313 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6314 break; 6315 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6316 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6317 break; 6318 default: 6319 break; 6320 } 6321 return 0; 6322 } 6323 6324 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6325 struct amdgpu_irq_src *source, 6326 struct amdgpu_iv_entry *entry) 6327 { 6328 int i; 6329 u8 me_id, pipe_id, queue_id; 6330 struct amdgpu_ring *ring; 6331 uint32_t mes_queue_id = entry->src_data[0]; 6332 6333 DRM_DEBUG("IH: CP EOP\n"); 6334 6335 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6336 struct amdgpu_mes_queue *queue; 6337 6338 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6339 6340 spin_lock(&adev->mes.queue_id_lock); 6341 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6342 if (queue) { 6343 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6344 amdgpu_fence_process(queue->ring); 6345 } 6346 spin_unlock(&adev->mes.queue_id_lock); 6347 } else { 6348 me_id = (entry->ring_id & 0x0c) >> 2; 6349 pipe_id = (entry->ring_id & 0x03) >> 0; 6350 queue_id = (entry->ring_id & 0x70) >> 4; 6351 6352 switch (me_id) { 6353 case 0: 6354 if (pipe_id == 0) 6355 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6356 else 6357 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6358 break; 6359 case 1: 6360 case 2: 6361 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6362 ring = &adev->gfx.compute_ring[i]; 6363 /* Per-queue interrupt is supported for MEC starting from VI. 6364 * The interrupt can only be enabled/disabled per pipe instead 6365 * of per queue. 6366 */ 6367 if ((ring->me == me_id) && 6368 (ring->pipe == pipe_id) && 6369 (ring->queue == queue_id)) 6370 amdgpu_fence_process(ring); 6371 } 6372 break; 6373 } 6374 } 6375 6376 return 0; 6377 } 6378 6379 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6380 struct amdgpu_irq_src *source, 6381 unsigned int type, 6382 enum amdgpu_interrupt_state state) 6383 { 6384 u32 cp_int_cntl_reg, cp_int_cntl; 6385 int i, j; 6386 6387 switch (state) { 6388 case AMDGPU_IRQ_STATE_DISABLE: 6389 case AMDGPU_IRQ_STATE_ENABLE: 6390 for (i = 0; i < adev->gfx.me.num_me; i++) { 6391 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6392 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6393 6394 if (cp_int_cntl_reg) { 6395 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6396 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6397 PRIV_REG_INT_ENABLE, 6398 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6399 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6400 } 6401 } 6402 } 6403 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6404 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6405 /* MECs start at 1 */ 6406 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6407 6408 if (cp_int_cntl_reg) { 6409 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6410 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6411 PRIV_REG_INT_ENABLE, 6412 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6413 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6414 } 6415 } 6416 } 6417 break; 6418 default: 6419 break; 6420 } 6421 6422 return 0; 6423 } 6424 6425 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6426 struct amdgpu_irq_src *source, 6427 unsigned type, 6428 enum amdgpu_interrupt_state state) 6429 { 6430 u32 cp_int_cntl_reg, cp_int_cntl; 6431 int i, j; 6432 6433 switch (state) { 6434 case AMDGPU_IRQ_STATE_DISABLE: 6435 case AMDGPU_IRQ_STATE_ENABLE: 6436 for (i = 0; i < adev->gfx.me.num_me; i++) { 6437 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6438 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6439 6440 if (cp_int_cntl_reg) { 6441 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6442 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6443 OPCODE_ERROR_INT_ENABLE, 6444 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6445 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6446 } 6447 } 6448 } 6449 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6450 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6451 /* MECs start at 1 */ 6452 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6453 6454 if (cp_int_cntl_reg) { 6455 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6456 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6457 OPCODE_ERROR_INT_ENABLE, 6458 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6459 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6460 } 6461 } 6462 } 6463 break; 6464 default: 6465 break; 6466 } 6467 return 0; 6468 } 6469 6470 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6471 struct amdgpu_irq_src *source, 6472 unsigned int type, 6473 enum amdgpu_interrupt_state state) 6474 { 6475 u32 cp_int_cntl_reg, cp_int_cntl; 6476 int i, j; 6477 6478 switch (state) { 6479 case AMDGPU_IRQ_STATE_DISABLE: 6480 case AMDGPU_IRQ_STATE_ENABLE: 6481 for (i = 0; i < adev->gfx.me.num_me; i++) { 6482 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6483 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6484 6485 if (cp_int_cntl_reg) { 6486 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6487 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6488 PRIV_INSTR_INT_ENABLE, 6489 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6490 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6491 } 6492 } 6493 } 6494 break; 6495 default: 6496 break; 6497 } 6498 6499 return 0; 6500 } 6501 6502 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6503 struct amdgpu_iv_entry *entry) 6504 { 6505 u8 me_id, pipe_id, queue_id; 6506 struct amdgpu_ring *ring; 6507 int i; 6508 6509 me_id = (entry->ring_id & 0x0c) >> 2; 6510 pipe_id = (entry->ring_id & 0x03) >> 0; 6511 queue_id = (entry->ring_id & 0x70) >> 4; 6512 6513 switch (me_id) { 6514 case 0: 6515 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6516 ring = &adev->gfx.gfx_ring[i]; 6517 if (ring->me == me_id && ring->pipe == pipe_id && 6518 ring->queue == queue_id) 6519 drm_sched_fault(&ring->sched); 6520 } 6521 break; 6522 case 1: 6523 case 2: 6524 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6525 ring = &adev->gfx.compute_ring[i]; 6526 if (ring->me == me_id && ring->pipe == pipe_id && 6527 ring->queue == queue_id) 6528 drm_sched_fault(&ring->sched); 6529 } 6530 break; 6531 default: 6532 BUG(); 6533 break; 6534 } 6535 } 6536 6537 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6538 struct amdgpu_irq_src *source, 6539 struct amdgpu_iv_entry *entry) 6540 { 6541 DRM_ERROR("Illegal register access in command stream\n"); 6542 gfx_v11_0_handle_priv_fault(adev, entry); 6543 return 0; 6544 } 6545 6546 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6547 struct amdgpu_irq_src *source, 6548 struct amdgpu_iv_entry *entry) 6549 { 6550 DRM_ERROR("Illegal opcode in command stream \n"); 6551 gfx_v11_0_handle_priv_fault(adev, entry); 6552 return 0; 6553 } 6554 6555 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6556 struct amdgpu_irq_src *source, 6557 struct amdgpu_iv_entry *entry) 6558 { 6559 DRM_ERROR("Illegal instruction in command stream\n"); 6560 gfx_v11_0_handle_priv_fault(adev, entry); 6561 return 0; 6562 } 6563 6564 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6565 struct amdgpu_irq_src *source, 6566 struct amdgpu_iv_entry *entry) 6567 { 6568 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6569 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6570 6571 return 0; 6572 } 6573 6574 #if 0 6575 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6576 struct amdgpu_irq_src *src, 6577 unsigned int type, 6578 enum amdgpu_interrupt_state state) 6579 { 6580 uint32_t tmp, target; 6581 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6582 6583 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6584 target += ring->pipe; 6585 6586 switch (type) { 6587 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6588 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6589 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6590 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6591 GENERIC2_INT_ENABLE, 0); 6592 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6593 6594 tmp = RREG32_SOC15_IP(GC, target); 6595 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6596 GENERIC2_INT_ENABLE, 0); 6597 WREG32_SOC15_IP(GC, target, tmp); 6598 } else { 6599 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6600 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6601 GENERIC2_INT_ENABLE, 1); 6602 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6603 6604 tmp = RREG32_SOC15_IP(GC, target); 6605 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6606 GENERIC2_INT_ENABLE, 1); 6607 WREG32_SOC15_IP(GC, target, tmp); 6608 } 6609 break; 6610 default: 6611 BUG(); /* kiq only support GENERIC2_INT now */ 6612 break; 6613 } 6614 return 0; 6615 } 6616 #endif 6617 6618 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6619 { 6620 const unsigned int gcr_cntl = 6621 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6622 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6623 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6624 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6625 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6626 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6627 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6628 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6629 6630 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6631 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6632 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6633 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6634 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6635 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6636 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6637 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6638 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6639 } 6640 6641 static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev) 6642 { 6643 /* Disable the pipe reset until the CPFW fully support it.*/ 6644 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 6645 return false; 6646 } 6647 6648 6649 static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring) 6650 { 6651 struct amdgpu_device *adev = ring->adev; 6652 uint32_t reset_pipe = 0, clean_pipe = 0; 6653 int r; 6654 6655 if (!gfx_v11_pipe_reset_support(adev)) 6656 return -EOPNOTSUPP; 6657 6658 gfx_v11_0_set_safe_mode(adev, 0); 6659 mutex_lock(&adev->srbm_mutex); 6660 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6661 6662 switch (ring->pipe) { 6663 case 0: 6664 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6665 PFP_PIPE0_RESET, 1); 6666 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6667 ME_PIPE0_RESET, 1); 6668 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6669 PFP_PIPE0_RESET, 0); 6670 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6671 ME_PIPE0_RESET, 0); 6672 break; 6673 case 1: 6674 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6675 PFP_PIPE1_RESET, 1); 6676 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6677 ME_PIPE1_RESET, 1); 6678 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6679 PFP_PIPE1_RESET, 0); 6680 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6681 ME_PIPE1_RESET, 0); 6682 break; 6683 default: 6684 break; 6685 } 6686 6687 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 6688 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 6689 6690 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 6691 RS64_FW_UC_START_ADDR_LO; 6692 soc21_grbm_select(adev, 0, 0, 0, 0); 6693 mutex_unlock(&adev->srbm_mutex); 6694 gfx_v11_0_unset_safe_mode(adev, 0); 6695 6696 dev_info(adev->dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring->name, 6697 r == 0 ? "successfully" : "failed"); 6698 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 6699 * so the pipe reset status relies on the later gfx ring test result. 6700 */ 6701 return 0; 6702 } 6703 6704 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 6705 { 6706 struct amdgpu_device *adev = ring->adev; 6707 int r; 6708 6709 if (amdgpu_sriov_vf(adev)) 6710 return -EINVAL; 6711 6712 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 6713 if (r) { 6714 6715 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 6716 r = gfx_v11_reset_gfx_pipe(ring); 6717 if (r) 6718 return r; 6719 } 6720 6721 r = gfx_v11_0_kgq_init_queue(ring, true); 6722 if (r) { 6723 dev_err(adev->dev, "failed to init kgq\n"); 6724 return r; 6725 } 6726 6727 r = amdgpu_mes_map_legacy_queue(adev, ring); 6728 if (r) { 6729 dev_err(adev->dev, "failed to remap kgq\n"); 6730 return r; 6731 } 6732 6733 return amdgpu_ring_test_ring(ring); 6734 } 6735 6736 static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring) 6737 { 6738 6739 struct amdgpu_device *adev = ring->adev; 6740 uint32_t reset_pipe = 0, clean_pipe = 0; 6741 int r; 6742 6743 if (!gfx_v11_pipe_reset_support(adev)) 6744 return -EOPNOTSUPP; 6745 6746 gfx_v11_0_set_safe_mode(adev, 0); 6747 mutex_lock(&adev->srbm_mutex); 6748 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6749 6750 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 6751 clean_pipe = reset_pipe; 6752 6753 if (adev->gfx.rs64_enable) { 6754 6755 switch (ring->pipe) { 6756 case 0: 6757 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6758 MEC_PIPE0_RESET, 1); 6759 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6760 MEC_PIPE0_RESET, 0); 6761 break; 6762 case 1: 6763 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6764 MEC_PIPE1_RESET, 1); 6765 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6766 MEC_PIPE1_RESET, 0); 6767 break; 6768 case 2: 6769 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6770 MEC_PIPE2_RESET, 1); 6771 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6772 MEC_PIPE2_RESET, 0); 6773 break; 6774 case 3: 6775 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6776 MEC_PIPE3_RESET, 1); 6777 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6778 MEC_PIPE3_RESET, 0); 6779 break; 6780 default: 6781 break; 6782 } 6783 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 6784 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 6785 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 6786 RS64_FW_UC_START_ADDR_LO; 6787 } else { 6788 if (ring->me == 1) { 6789 switch (ring->pipe) { 6790 case 0: 6791 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6792 MEC_ME1_PIPE0_RESET, 1); 6793 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6794 MEC_ME1_PIPE0_RESET, 0); 6795 break; 6796 case 1: 6797 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6798 MEC_ME1_PIPE1_RESET, 1); 6799 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6800 MEC_ME1_PIPE1_RESET, 0); 6801 break; 6802 case 2: 6803 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6804 MEC_ME1_PIPE2_RESET, 1); 6805 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6806 MEC_ME1_PIPE2_RESET, 0); 6807 break; 6808 case 3: 6809 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6810 MEC_ME1_PIPE3_RESET, 1); 6811 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6812 MEC_ME1_PIPE3_RESET, 0); 6813 break; 6814 default: 6815 break; 6816 } 6817 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 6818 } else { 6819 switch (ring->pipe) { 6820 case 0: 6821 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6822 MEC_ME2_PIPE0_RESET, 1); 6823 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6824 MEC_ME2_PIPE0_RESET, 0); 6825 break; 6826 case 1: 6827 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6828 MEC_ME2_PIPE1_RESET, 1); 6829 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6830 MEC_ME2_PIPE1_RESET, 0); 6831 break; 6832 case 2: 6833 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6834 MEC_ME2_PIPE2_RESET, 1); 6835 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6836 MEC_ME2_PIPE2_RESET, 0); 6837 break; 6838 case 3: 6839 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6840 MEC_ME2_PIPE3_RESET, 1); 6841 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6842 MEC_ME2_PIPE3_RESET, 0); 6843 break; 6844 default: 6845 break; 6846 } 6847 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 6848 } 6849 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 6850 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 6851 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 6852 } 6853 6854 soc21_grbm_select(adev, 0, 0, 0, 0); 6855 mutex_unlock(&adev->srbm_mutex); 6856 gfx_v11_0_unset_safe_mode(adev, 0); 6857 6858 dev_info(adev->dev, "The ring %s pipe resets to MEC FW start PC: %s\n", ring->name, 6859 r == 0 ? "successfully" : "failed"); 6860 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 6861 * reset status relies on the compute ring test result. 6862 */ 6863 return 0; 6864 } 6865 6866 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 6867 { 6868 struct amdgpu_device *adev = ring->adev; 6869 int r = 0; 6870 6871 if (amdgpu_sriov_vf(adev)) 6872 return -EINVAL; 6873 6874 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 6875 if (r) { 6876 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 6877 r = gfx_v11_0_reset_compute_pipe(ring); 6878 if (r) 6879 return r; 6880 } 6881 6882 r = gfx_v11_0_kcq_init_queue(ring, true); 6883 if (r) { 6884 dev_err(adev->dev, "fail to init kcq\n"); 6885 return r; 6886 } 6887 r = amdgpu_mes_map_legacy_queue(adev, ring); 6888 if (r) { 6889 dev_err(adev->dev, "failed to remap kcq\n"); 6890 return r; 6891 } 6892 6893 return amdgpu_ring_test_ring(ring); 6894 } 6895 6896 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 6897 { 6898 struct amdgpu_device *adev = ip_block->adev; 6899 uint32_t i, j, k, reg, index = 0; 6900 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6901 6902 if (!adev->gfx.ip_dump_core) 6903 return; 6904 6905 for (i = 0; i < reg_count; i++) 6906 drm_printf(p, "%-50s \t 0x%08x\n", 6907 gc_reg_list_11_0[i].reg_name, 6908 adev->gfx.ip_dump_core[i]); 6909 6910 /* print compute queue registers for all instances */ 6911 if (!adev->gfx.ip_dump_compute_queues) 6912 return; 6913 6914 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6915 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6916 adev->gfx.mec.num_mec, 6917 adev->gfx.mec.num_pipe_per_mec, 6918 adev->gfx.mec.num_queue_per_pipe); 6919 6920 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6921 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6922 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6923 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 6924 for (reg = 0; reg < reg_count; reg++) { 6925 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 6926 drm_printf(p, "%-50s \t 0x%08x\n", 6927 "regCP_MEC_ME2_HEADER_DUMP", 6928 adev->gfx.ip_dump_compute_queues[index + reg]); 6929 else 6930 drm_printf(p, "%-50s \t 0x%08x\n", 6931 gc_cp_reg_list_11[reg].reg_name, 6932 adev->gfx.ip_dump_compute_queues[index + reg]); 6933 } 6934 index += reg_count; 6935 } 6936 } 6937 } 6938 6939 /* print gfx queue registers for all instances */ 6940 if (!adev->gfx.ip_dump_gfx_queues) 6941 return; 6942 6943 index = 0; 6944 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6945 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 6946 adev->gfx.me.num_me, 6947 adev->gfx.me.num_pipe_per_me, 6948 adev->gfx.me.num_queue_per_pipe); 6949 6950 for (i = 0; i < adev->gfx.me.num_me; i++) { 6951 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6952 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6953 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 6954 for (reg = 0; reg < reg_count; reg++) { 6955 drm_printf(p, "%-50s \t 0x%08x\n", 6956 gc_gfx_queue_reg_list_11[reg].reg_name, 6957 adev->gfx.ip_dump_gfx_queues[index + reg]); 6958 } 6959 index += reg_count; 6960 } 6961 } 6962 } 6963 } 6964 6965 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 6966 { 6967 struct amdgpu_device *adev = ip_block->adev; 6968 uint32_t i, j, k, reg, index = 0; 6969 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6970 6971 if (!adev->gfx.ip_dump_core) 6972 return; 6973 6974 amdgpu_gfx_off_ctrl(adev, false); 6975 for (i = 0; i < reg_count; i++) 6976 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 6977 amdgpu_gfx_off_ctrl(adev, true); 6978 6979 /* dump compute queue registers for all instances */ 6980 if (!adev->gfx.ip_dump_compute_queues) 6981 return; 6982 6983 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6984 amdgpu_gfx_off_ctrl(adev, false); 6985 mutex_lock(&adev->srbm_mutex); 6986 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6987 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6988 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6989 /* ME0 is for GFX so start from 1 for CP */ 6990 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 6991 for (reg = 0; reg < reg_count; reg++) { 6992 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 6993 adev->gfx.ip_dump_compute_queues[index + reg] = 6994 RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME2_HEADER_DUMP)); 6995 else 6996 adev->gfx.ip_dump_compute_queues[index + reg] = 6997 RREG32(SOC15_REG_ENTRY_OFFSET( 6998 gc_cp_reg_list_11[reg])); 6999 } 7000 index += reg_count; 7001 } 7002 } 7003 } 7004 soc21_grbm_select(adev, 0, 0, 0, 0); 7005 mutex_unlock(&adev->srbm_mutex); 7006 amdgpu_gfx_off_ctrl(adev, true); 7007 7008 /* dump gfx queue registers for all instances */ 7009 if (!adev->gfx.ip_dump_gfx_queues) 7010 return; 7011 7012 index = 0; 7013 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7014 amdgpu_gfx_off_ctrl(adev, false); 7015 mutex_lock(&adev->srbm_mutex); 7016 for (i = 0; i < adev->gfx.me.num_me; i++) { 7017 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7018 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7019 soc21_grbm_select(adev, i, j, k, 0); 7020 7021 for (reg = 0; reg < reg_count; reg++) { 7022 adev->gfx.ip_dump_gfx_queues[index + reg] = 7023 RREG32(SOC15_REG_ENTRY_OFFSET( 7024 gc_gfx_queue_reg_list_11[reg])); 7025 } 7026 index += reg_count; 7027 } 7028 } 7029 } 7030 soc21_grbm_select(adev, 0, 0, 0, 0); 7031 mutex_unlock(&adev->srbm_mutex); 7032 amdgpu_gfx_off_ctrl(adev, true); 7033 } 7034 7035 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 7036 { 7037 /* Emit the cleaner shader */ 7038 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 7039 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 7040 } 7041 7042 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 7043 { 7044 amdgpu_gfx_profile_ring_begin_use(ring); 7045 7046 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 7047 } 7048 7049 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 7050 { 7051 amdgpu_gfx_profile_ring_end_use(ring); 7052 7053 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 7054 } 7055 7056 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 7057 .name = "gfx_v11_0", 7058 .early_init = gfx_v11_0_early_init, 7059 .late_init = gfx_v11_0_late_init, 7060 .sw_init = gfx_v11_0_sw_init, 7061 .sw_fini = gfx_v11_0_sw_fini, 7062 .hw_init = gfx_v11_0_hw_init, 7063 .hw_fini = gfx_v11_0_hw_fini, 7064 .suspend = gfx_v11_0_suspend, 7065 .resume = gfx_v11_0_resume, 7066 .is_idle = gfx_v11_0_is_idle, 7067 .wait_for_idle = gfx_v11_0_wait_for_idle, 7068 .soft_reset = gfx_v11_0_soft_reset, 7069 .check_soft_reset = gfx_v11_0_check_soft_reset, 7070 .post_soft_reset = gfx_v11_0_post_soft_reset, 7071 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 7072 .set_powergating_state = gfx_v11_0_set_powergating_state, 7073 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 7074 .dump_ip_state = gfx_v11_ip_dump, 7075 .print_ip_state = gfx_v11_ip_print, 7076 }; 7077 7078 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 7079 .type = AMDGPU_RING_TYPE_GFX, 7080 .align_mask = 0xff, 7081 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7082 .support_64bit_ptrs = true, 7083 .secure_submission_supported = true, 7084 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 7085 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 7086 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 7087 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 7088 5 + /* update_spm_vmid */ 7089 5 + /* COND_EXEC */ 7090 22 + /* SET_Q_PREEMPTION_MODE */ 7091 7 + /* PIPELINE_SYNC */ 7092 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7093 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7094 4 + /* VM_FLUSH */ 7095 8 + /* FENCE for VM_FLUSH */ 7096 20 + /* GDS switch */ 7097 5 + /* COND_EXEC */ 7098 7 + /* HDP_flush */ 7099 4 + /* VGT_flush */ 7100 31 + /* DE_META */ 7101 3 + /* CNTX_CTRL */ 7102 5 + /* HDP_INVL */ 7103 22 + /* SET_Q_PREEMPTION_MODE */ 7104 8 + 8 + /* FENCE x2 */ 7105 8 + /* gfx_v11_0_emit_mem_sync */ 7106 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7107 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 7108 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 7109 .emit_fence = gfx_v11_0_ring_emit_fence, 7110 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7111 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7112 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7113 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7114 .test_ring = gfx_v11_0_ring_test_ring, 7115 .test_ib = gfx_v11_0_ring_test_ib, 7116 .insert_nop = gfx_v11_ring_insert_nop, 7117 .pad_ib = amdgpu_ring_generic_pad_ib, 7118 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 7119 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 7120 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 7121 .preempt_ib = gfx_v11_0_ring_preempt_ib, 7122 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 7123 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7124 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7125 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7126 .soft_recovery = gfx_v11_0_ring_soft_recovery, 7127 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7128 .reset = gfx_v11_0_reset_kgq, 7129 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7130 .begin_use = gfx_v11_0_ring_begin_use, 7131 .end_use = gfx_v11_0_ring_end_use, 7132 }; 7133 7134 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 7135 .type = AMDGPU_RING_TYPE_COMPUTE, 7136 .align_mask = 0xff, 7137 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7138 .support_64bit_ptrs = true, 7139 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7140 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7141 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7142 .emit_frame_size = 7143 5 + /* update_spm_vmid */ 7144 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7145 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7146 5 + /* hdp invalidate */ 7147 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7148 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7149 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7150 2 + /* gfx_v11_0_ring_emit_vm_flush */ 7151 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 7152 8 + /* gfx_v11_0_emit_mem_sync */ 7153 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7154 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7155 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7156 .emit_fence = gfx_v11_0_ring_emit_fence, 7157 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7158 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7159 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7160 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7161 .test_ring = gfx_v11_0_ring_test_ring, 7162 .test_ib = gfx_v11_0_ring_test_ib, 7163 .insert_nop = gfx_v11_ring_insert_nop, 7164 .pad_ib = amdgpu_ring_generic_pad_ib, 7165 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7166 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7167 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7168 .soft_recovery = gfx_v11_0_ring_soft_recovery, 7169 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7170 .reset = gfx_v11_0_reset_kcq, 7171 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7172 .begin_use = gfx_v11_0_ring_begin_use, 7173 .end_use = gfx_v11_0_ring_end_use, 7174 }; 7175 7176 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 7177 .type = AMDGPU_RING_TYPE_KIQ, 7178 .align_mask = 0xff, 7179 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7180 .support_64bit_ptrs = true, 7181 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7182 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7183 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7184 .emit_frame_size = 7185 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7186 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7187 5 + /*hdp invalidate */ 7188 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7189 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7190 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7191 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7192 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7193 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7194 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 7195 .test_ring = gfx_v11_0_ring_test_ring, 7196 .test_ib = gfx_v11_0_ring_test_ib, 7197 .insert_nop = amdgpu_ring_insert_nop, 7198 .pad_ib = amdgpu_ring_generic_pad_ib, 7199 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7200 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7201 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7202 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7203 }; 7204 7205 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7206 { 7207 int i; 7208 7209 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7210 7211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7212 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7213 7214 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7215 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7216 } 7217 7218 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7219 .set = gfx_v11_0_set_eop_interrupt_state, 7220 .process = gfx_v11_0_eop_irq, 7221 }; 7222 7223 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7224 .set = gfx_v11_0_set_priv_reg_fault_state, 7225 .process = gfx_v11_0_priv_reg_irq, 7226 }; 7227 7228 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7229 .set = gfx_v11_0_set_bad_op_fault_state, 7230 .process = gfx_v11_0_bad_op_irq, 7231 }; 7232 7233 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7234 .set = gfx_v11_0_set_priv_inst_fault_state, 7235 .process = gfx_v11_0_priv_inst_irq, 7236 }; 7237 7238 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7239 .process = gfx_v11_0_rlc_gc_fed_irq, 7240 }; 7241 7242 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7243 { 7244 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7245 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7246 7247 adev->gfx.priv_reg_irq.num_types = 1; 7248 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7249 7250 adev->gfx.bad_op_irq.num_types = 1; 7251 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7252 7253 adev->gfx.priv_inst_irq.num_types = 1; 7254 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7255 7256 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7257 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7258 7259 } 7260 7261 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7262 { 7263 if (adev->flags & AMD_IS_APU) 7264 adev->gfx.imu.mode = MISSION_MODE; 7265 else 7266 adev->gfx.imu.mode = DEBUG_MODE; 7267 7268 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7269 } 7270 7271 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7272 { 7273 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7274 } 7275 7276 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7277 { 7278 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7279 adev->gfx.config.max_sh_per_se * 7280 adev->gfx.config.max_shader_engines; 7281 7282 adev->gds.gds_size = 0x1000; 7283 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7284 adev->gds.gws_size = 64; 7285 adev->gds.oa_size = 16; 7286 } 7287 7288 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7289 { 7290 /* set gfx eng mqd */ 7291 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7292 sizeof(struct v11_gfx_mqd); 7293 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7294 gfx_v11_0_gfx_mqd_init; 7295 /* set compute eng mqd */ 7296 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7297 sizeof(struct v11_compute_mqd); 7298 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7299 gfx_v11_0_compute_mqd_init; 7300 } 7301 7302 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7303 u32 bitmap) 7304 { 7305 u32 data; 7306 7307 if (!bitmap) 7308 return; 7309 7310 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7311 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7312 7313 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7314 } 7315 7316 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7317 { 7318 u32 data, wgp_bitmask; 7319 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7320 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7321 7322 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7323 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7324 7325 wgp_bitmask = 7326 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7327 7328 return (~data) & wgp_bitmask; 7329 } 7330 7331 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7332 { 7333 u32 wgp_idx, wgp_active_bitmap; 7334 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7335 7336 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7337 cu_active_bitmap = 0; 7338 7339 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7340 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7341 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7342 if (wgp_active_bitmap & (1 << wgp_idx)) 7343 cu_active_bitmap |= cu_bitmap_per_wgp; 7344 } 7345 7346 return cu_active_bitmap; 7347 } 7348 7349 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7350 struct amdgpu_cu_info *cu_info) 7351 { 7352 int i, j, k, counter, active_cu_number = 0; 7353 u32 mask, bitmap; 7354 unsigned disable_masks[8 * 2]; 7355 7356 if (!adev || !cu_info) 7357 return -EINVAL; 7358 7359 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 7360 7361 mutex_lock(&adev->grbm_idx_mutex); 7362 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7363 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7364 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7365 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7366 continue; 7367 mask = 1; 7368 counter = 0; 7369 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7370 if (i < 8 && j < 2) 7371 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7372 adev, disable_masks[i * 2 + j]); 7373 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7374 7375 /** 7376 * GFX11 could support more than 4 SEs, while the bitmap 7377 * in cu_info struct is 4x4 and ioctl interface struct 7378 * drm_amdgpu_info_device should keep stable. 7379 * So we use last two columns of bitmap to store cu mask for 7380 * SEs 4 to 7, the layout of the bitmap is as below: 7381 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7382 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7383 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7384 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7385 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7386 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7387 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7388 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7389 */ 7390 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7391 7392 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7393 if (bitmap & mask) 7394 counter++; 7395 7396 mask <<= 1; 7397 } 7398 active_cu_number += counter; 7399 } 7400 } 7401 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7402 mutex_unlock(&adev->grbm_idx_mutex); 7403 7404 cu_info->number = active_cu_number; 7405 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7406 7407 return 0; 7408 } 7409 7410 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7411 { 7412 .type = AMD_IP_BLOCK_TYPE_GFX, 7413 .major = 11, 7414 .minor = 0, 7415 .rev = 0, 7416 .funcs = &gfx_v11_0_ip_funcs, 7417 }; 7418