1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v11_0.h" 33 #include "soc21.h" 34 #include "nvd.h" 35 36 #include "gc/gc_11_0_0_offset.h" 37 #include "gc/gc_11_0_0_sh_mask.h" 38 #include "smuio/smuio_13_0_6_offset.h" 39 #include "smuio/smuio_13_0_6_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx11.h" 45 #include "v11_structs.h" 46 #include "gfx_v11_0.h" 47 #include "gfx_v11_0_cleaner_shader.h" 48 #include "gfx_v11_0_3.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 #include "mes_userqueue.h" 52 #include "amdgpu_userq_fence.h" 53 54 #define GFX11_NUM_GFX_RINGS 1 55 #define GFX11_MEC_HPD_SIZE 2048 56 57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 59 60 #define regCGTT_WD_CLK_CTRL 0x5086 61 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 63 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 64 #define regPC_CONFIG_CNTL_1 0x194d 65 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 66 67 #define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0 0x0030 68 #define regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0_BASE_IDX 1 69 #define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0 0x0031 70 #define regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0_BASE_IDX 1 71 72 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 73 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 74 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 75 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 76 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 77 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 78 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 79 80 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 81 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 82 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 83 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 84 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 85 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 86 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 87 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 88 89 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_kicker.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 104 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 105 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 106 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 107 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 108 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 109 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 110 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 111 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 112 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 113 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 114 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 115 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 116 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 118 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 120 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 121 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 122 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 123 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 124 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 125 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 126 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 127 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 128 MODULE_FIRMWARE("amdgpu/gc_11_5_4_pfp.bin"); 129 MODULE_FIRMWARE("amdgpu/gc_11_5_4_me.bin"); 130 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mec.bin"); 131 MODULE_FIRMWARE("amdgpu/gc_11_5_4_rlc.bin"); 132 MODULE_FIRMWARE("amdgpu/gc_11_5_6_pfp.bin"); 133 MODULE_FIRMWARE("amdgpu/gc_11_5_6_me.bin"); 134 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mec.bin"); 135 MODULE_FIRMWARE("amdgpu/gc_11_5_6_rlc.bin"); 136 MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp.bin"); 137 MODULE_FIRMWARE("amdgpu/gc_11_7_0_me.bin"); 138 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec.bin"); 139 MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc.bin"); 140 MODULE_FIRMWARE("amdgpu/gc_11_7_1_pfp.bin"); 141 MODULE_FIRMWARE("amdgpu/gc_11_7_1_me.bin"); 142 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mec.bin"); 143 MODULE_FIRMWARE("amdgpu/gc_11_7_1_rlc.bin"); 144 145 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 146 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 147 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 148 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 179 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 181 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 182 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 183 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 184 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 185 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 186 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 187 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 188 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 189 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 190 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 191 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 192 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 193 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 203 /* cp header registers */ 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 212 /* SE status registers */ 213 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 214 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 215 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 216 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 217 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 218 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 219 }; 220 221 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 222 /* compute registers */ 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 251 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 252 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 253 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 254 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 255 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 256 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 257 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 258 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 259 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 260 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 261 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 262 /* cp header registers */ 263 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 264 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 265 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 266 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 267 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 268 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 269 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 270 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 271 }; 272 273 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 274 /* gfx queue registers */ 275 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 276 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 277 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 278 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 279 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 280 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 281 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 282 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 283 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 284 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 285 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 286 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 287 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 288 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 289 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 290 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 291 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 292 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 293 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 294 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 295 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 296 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 297 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 298 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 299 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 300 /* cp header registers */ 301 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 302 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 303 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 304 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 305 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 306 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 307 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 308 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 309 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 310 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 311 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 312 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 313 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 314 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 315 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 316 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 317 }; 318 319 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 320 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 321 }; 322 323 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 324 { 325 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 334 }; 335 336 #define DEFAULT_SH_MEM_CONFIG \ 337 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 338 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 339 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 340 341 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 342 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 343 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 344 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 345 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 346 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 347 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 348 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 349 struct amdgpu_cu_info *cu_info); 350 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 351 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 instance, int xcc_id); 353 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 354 355 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 356 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 357 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 358 uint32_t val); 359 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 360 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 361 uint16_t pasid, uint32_t flush_type, 362 bool all_hub, uint8_t dst_sel); 363 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 364 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 365 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 366 bool enable); 367 368 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 369 { 370 struct amdgpu_device *adev = kiq_ring->adev; 371 u64 shader_mc_addr; 372 373 /* Cleaner shader MC address */ 374 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 375 376 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 377 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 378 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 379 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 380 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 381 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 382 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 383 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 384 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 385 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 386 } 387 388 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 389 struct amdgpu_ring *ring) 390 { 391 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 392 uint64_t wptr_addr = ring->wptr_gpu_addr; 393 uint32_t me = 0, eng_sel = 0; 394 395 switch (ring->funcs->type) { 396 case AMDGPU_RING_TYPE_COMPUTE: 397 me = 1; 398 eng_sel = 0; 399 break; 400 case AMDGPU_RING_TYPE_GFX: 401 me = 0; 402 eng_sel = 4; 403 break; 404 case AMDGPU_RING_TYPE_MES: 405 me = 2; 406 eng_sel = 5; 407 break; 408 default: 409 WARN_ON(1); 410 } 411 412 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 413 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 414 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 415 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 416 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 417 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 418 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 419 PACKET3_MAP_QUEUES_ME((me)) | 420 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 421 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 422 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 423 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 424 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 425 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 426 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 427 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 428 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 429 } 430 431 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 432 struct amdgpu_ring *ring, 433 enum amdgpu_unmap_queues_action action, 434 u64 gpu_addr, u64 seq) 435 { 436 struct amdgpu_device *adev = kiq_ring->adev; 437 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 438 439 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 440 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 441 gpu_addr, seq, 0); 442 return; 443 } 444 445 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 446 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 447 PACKET3_UNMAP_QUEUES_ACTION(action) | 448 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 449 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 450 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 451 amdgpu_ring_write(kiq_ring, 452 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 453 454 if (action == PREEMPT_QUEUES_NO_UNMAP) { 455 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 456 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 457 amdgpu_ring_write(kiq_ring, seq); 458 } else { 459 amdgpu_ring_write(kiq_ring, 0); 460 amdgpu_ring_write(kiq_ring, 0); 461 amdgpu_ring_write(kiq_ring, 0); 462 } 463 } 464 465 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 466 struct amdgpu_ring *ring, 467 u64 addr, 468 u64 seq) 469 { 470 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 471 472 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 473 amdgpu_ring_write(kiq_ring, 474 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 475 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 476 PACKET3_QUERY_STATUS_COMMAND(2)); 477 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 478 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 479 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 480 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 481 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 482 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 483 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 484 } 485 486 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 487 uint16_t pasid, uint32_t flush_type, 488 bool all_hub) 489 { 490 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 491 } 492 493 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 494 .kiq_set_resources = gfx11_kiq_set_resources, 495 .kiq_map_queues = gfx11_kiq_map_queues, 496 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 497 .kiq_query_status = gfx11_kiq_query_status, 498 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 499 .set_resources_size = 8, 500 .map_queues_size = 7, 501 .unmap_queues_size = 6, 502 .query_status_size = 7, 503 .invalidate_tlbs_size = 2, 504 }; 505 506 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 507 { 508 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 509 } 510 511 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 512 { 513 if (amdgpu_sriov_vf(adev)) 514 return; 515 516 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 517 case IP_VERSION(11, 0, 1): 518 case IP_VERSION(11, 0, 4): 519 soc15_program_register_sequence(adev, 520 golden_settings_gc_11_0_1, 521 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 522 break; 523 default: 524 break; 525 } 526 soc15_program_register_sequence(adev, 527 golden_settings_gc_11_0, 528 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 529 530 } 531 532 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 533 bool wc, uint32_t reg, uint32_t val) 534 { 535 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 536 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 537 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 538 amdgpu_ring_write(ring, reg); 539 amdgpu_ring_write(ring, 0); 540 amdgpu_ring_write(ring, val); 541 } 542 543 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 544 int mem_space, int opt, uint32_t addr0, 545 uint32_t addr1, uint32_t ref, uint32_t mask, 546 uint32_t inv) 547 { 548 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 549 amdgpu_ring_write(ring, 550 /* memory (1) or register (0) */ 551 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 552 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 553 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 554 WAIT_REG_MEM_ENGINE(eng_sel))); 555 556 if (mem_space) 557 WARN_ON(addr0 & 0x3); /* Dword align */ 558 amdgpu_ring_write(ring, addr0); 559 amdgpu_ring_write(ring, addr1); 560 amdgpu_ring_write(ring, ref); 561 amdgpu_ring_write(ring, mask); 562 amdgpu_ring_write(ring, inv); /* poll interval */ 563 } 564 565 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 566 { 567 /* Header itself is a NOP packet */ 568 if (num_nop == 1) { 569 amdgpu_ring_write(ring, ring->funcs->nop); 570 return; 571 } 572 573 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 574 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 575 576 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 577 amdgpu_ring_insert_nop(ring, num_nop - 1); 578 } 579 580 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 581 { 582 struct amdgpu_device *adev = ring->adev; 583 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 584 uint32_t tmp = 0; 585 unsigned i; 586 int r; 587 588 WREG32(scratch, 0xCAFEDEAD); 589 r = amdgpu_ring_alloc(ring, 5); 590 if (r) { 591 drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", 592 ring->idx, r); 593 return r; 594 } 595 596 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 597 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 598 } else { 599 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 600 amdgpu_ring_write(ring, scratch - 601 PACKET3_SET_UCONFIG_REG_START); 602 amdgpu_ring_write(ring, 0xDEADBEEF); 603 } 604 amdgpu_ring_commit(ring); 605 606 for (i = 0; i < adev->usec_timeout; i++) { 607 tmp = RREG32(scratch); 608 if (tmp == 0xDEADBEEF) 609 break; 610 if (amdgpu_emu_mode == 1) 611 msleep(1); 612 else 613 udelay(1); 614 } 615 616 if (i >= adev->usec_timeout) 617 r = -ETIMEDOUT; 618 return r; 619 } 620 621 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 622 { 623 struct amdgpu_device *adev = ring->adev; 624 struct amdgpu_ib ib; 625 struct dma_fence *f = NULL; 626 unsigned index; 627 uint64_t gpu_addr; 628 uint32_t *cpu_ptr; 629 long r; 630 631 /* MES KIQ fw hasn't indirect buffer support for now */ 632 if (adev->enable_mes_kiq && 633 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 634 return 0; 635 636 memset(&ib, 0, sizeof(ib)); 637 638 r = amdgpu_device_wb_get(adev, &index); 639 if (r) 640 return r; 641 642 gpu_addr = adev->wb.gpu_addr + (index * 4); 643 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 644 cpu_ptr = &adev->wb.wb[index]; 645 646 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 647 if (r) { 648 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 649 goto err1; 650 } 651 652 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 653 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 654 ib.ptr[2] = lower_32_bits(gpu_addr); 655 ib.ptr[3] = upper_32_bits(gpu_addr); 656 ib.ptr[4] = 0xDEADBEEF; 657 ib.length_dw = 5; 658 659 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 660 if (r) 661 goto err2; 662 663 r = dma_fence_wait_timeout(f, false, timeout); 664 if (r == 0) { 665 r = -ETIMEDOUT; 666 goto err2; 667 } else if (r < 0) { 668 goto err2; 669 } 670 671 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 672 r = 0; 673 else 674 r = -EINVAL; 675 err2: 676 amdgpu_ib_free(&ib, NULL); 677 dma_fence_put(f); 678 err1: 679 amdgpu_device_wb_free(adev, index); 680 return r; 681 } 682 683 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 684 { 685 amdgpu_ucode_release(&adev->gfx.pfp_fw); 686 amdgpu_ucode_release(&adev->gfx.me_fw); 687 amdgpu_ucode_release(&adev->gfx.rlc_fw); 688 amdgpu_ucode_release(&adev->gfx.mec_fw); 689 690 kfree(adev->gfx.rlc.register_list_format); 691 } 692 693 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 694 { 695 const struct psp_firmware_header_v1_0 *toc_hdr; 696 int err = 0; 697 698 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 699 AMDGPU_UCODE_REQUIRED, 700 "amdgpu/%s_toc.bin", ucode_prefix); 701 if (err) 702 goto out; 703 704 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 705 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 706 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 707 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 708 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 709 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 710 return 0; 711 out: 712 amdgpu_ucode_release(&adev->psp.toc_fw); 713 return err; 714 } 715 716 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 717 { 718 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 719 case IP_VERSION(11, 0, 0): 720 case IP_VERSION(11, 0, 2): 721 case IP_VERSION(11, 0, 3): 722 if ((adev->gfx.me_fw_version >= 1505) && 723 (adev->gfx.pfp_fw_version >= 1600) && 724 (adev->gfx.mec_fw_version >= 512)) { 725 if (amdgpu_sriov_vf(adev)) 726 adev->gfx.cp_gfx_shadow = true; 727 else 728 adev->gfx.cp_gfx_shadow = false; 729 } 730 break; 731 default: 732 adev->gfx.cp_gfx_shadow = false; 733 break; 734 } 735 } 736 737 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 738 { 739 char ucode_prefix[25]; 740 int err; 741 const struct rlc_firmware_header_v2_0 *rlc_hdr; 742 uint16_t version_major; 743 uint16_t version_minor; 744 745 DRM_DEBUG("\n"); 746 747 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 748 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 749 AMDGPU_UCODE_REQUIRED, 750 "amdgpu/%s_pfp.bin", ucode_prefix); 751 if (err) 752 goto out; 753 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 754 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 755 (union amdgpu_firmware_header *) 756 adev->gfx.pfp_fw->data, 2, 0); 757 if (adev->gfx.rs64_enable) { 758 dev_info(adev->dev, "CP RS64 enable\n"); 759 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 760 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 761 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 762 } else { 763 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 764 } 765 766 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 767 AMDGPU_UCODE_REQUIRED, 768 "amdgpu/%s_me.bin", ucode_prefix); 769 if (err) 770 goto out; 771 if (adev->gfx.rs64_enable) { 772 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 773 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 774 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 775 } else { 776 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 777 } 778 779 if (!amdgpu_sriov_vf(adev)) { 780 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 781 adev->pdev->revision == 0xCE) 782 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 783 AMDGPU_UCODE_REQUIRED, 784 "amdgpu/gc_11_0_0_rlc_1.bin"); 785 else if (amdgpu_is_kicker_fw(adev)) 786 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 787 AMDGPU_UCODE_REQUIRED, 788 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 789 else 790 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 791 AMDGPU_UCODE_REQUIRED, 792 "amdgpu/%s_rlc.bin", ucode_prefix); 793 if (err) 794 goto out; 795 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 796 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 797 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 798 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 799 if (err) 800 goto out; 801 } 802 803 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 804 AMDGPU_UCODE_REQUIRED, 805 "amdgpu/%s_mec.bin", ucode_prefix); 806 if (err) 807 goto out; 808 if (adev->gfx.rs64_enable) { 809 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 810 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 811 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 812 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 813 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 814 } else { 815 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 816 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 817 } 818 819 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 820 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 821 822 /* only one MEC for gfx 11.0.0. */ 823 adev->gfx.mec2_fw = NULL; 824 825 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 826 827 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 828 err = adev->gfx.imu.funcs->init_microcode(adev); 829 if (err) 830 DRM_ERROR("Failed to init imu firmware!\n"); 831 return err; 832 } 833 834 out: 835 if (err) { 836 amdgpu_ucode_release(&adev->gfx.pfp_fw); 837 amdgpu_ucode_release(&adev->gfx.me_fw); 838 amdgpu_ucode_release(&adev->gfx.rlc_fw); 839 amdgpu_ucode_release(&adev->gfx.mec_fw); 840 } 841 842 return err; 843 } 844 845 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 846 { 847 u32 count = 0; 848 const struct cs_section_def *sect = NULL; 849 const struct cs_extent_def *ext = NULL; 850 851 /* begin clear state */ 852 count += 2; 853 /* context control state */ 854 count += 3; 855 856 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 857 for (ext = sect->section; ext->extent != NULL; ++ext) { 858 if (sect->id == SECT_CONTEXT) 859 count += 2 + ext->reg_count; 860 else 861 return 0; 862 } 863 } 864 865 /* set PA_SC_TILE_STEERING_OVERRIDE */ 866 count += 3; 867 /* end clear state */ 868 count += 2; 869 /* clear state */ 870 count += 2; 871 872 return count; 873 } 874 875 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 876 { 877 u32 count = 0; 878 int ctx_reg_offset; 879 880 if (adev->gfx.rlc.cs_data == NULL) 881 return; 882 if (buffer == NULL) 883 return; 884 885 count = amdgpu_gfx_csb_preamble_start(buffer); 886 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 887 888 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 889 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 890 buffer[count++] = cpu_to_le32(ctx_reg_offset); 891 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 892 893 amdgpu_gfx_csb_preamble_end(buffer, count); 894 } 895 896 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 897 { 898 /* clear state block */ 899 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 900 &adev->gfx.rlc.clear_state_gpu_addr, 901 (void **)&adev->gfx.rlc.cs_ptr); 902 903 /* jump table block */ 904 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 905 &adev->gfx.rlc.cp_table_gpu_addr, 906 (void **)&adev->gfx.rlc.cp_table_ptr); 907 } 908 909 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 910 { 911 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 912 913 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 914 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 915 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 916 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 917 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 918 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 919 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 920 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 921 adev->gfx.rlc.rlcg_reg_access_supported = true; 922 } 923 924 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 925 { 926 const struct cs_section_def *cs_data; 927 int r; 928 929 adev->gfx.rlc.cs_data = gfx11_cs_data; 930 931 cs_data = adev->gfx.rlc.cs_data; 932 933 if (cs_data) { 934 /* init clear state block */ 935 r = amdgpu_gfx_rlc_init_csb(adev); 936 if (r) 937 return r; 938 } 939 940 /* init spm vmid with 0xf */ 941 if (adev->gfx.rlc.funcs->update_spm_vmid) 942 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 943 944 return 0; 945 } 946 947 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 948 { 949 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 950 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 951 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 952 } 953 954 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 955 { 956 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 957 958 amdgpu_gfx_graphics_queue_acquire(adev); 959 } 960 961 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 962 { 963 int r; 964 u32 *hpd; 965 size_t mec_hpd_size; 966 967 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 968 969 /* take ownership of the relevant compute queues */ 970 amdgpu_gfx_compute_queue_acquire(adev); 971 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 972 973 if (mec_hpd_size) { 974 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 975 AMDGPU_GEM_DOMAIN_GTT, 976 &adev->gfx.mec.hpd_eop_obj, 977 &adev->gfx.mec.hpd_eop_gpu_addr, 978 (void **)&hpd); 979 if (r) { 980 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 981 gfx_v11_0_mec_fini(adev); 982 return r; 983 } 984 985 memset(hpd, 0, mec_hpd_size); 986 987 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 988 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 989 } 990 991 return 0; 992 } 993 994 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 995 { 996 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 997 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 998 (address << SQ_IND_INDEX__INDEX__SHIFT)); 999 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1000 } 1001 1002 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1003 uint32_t thread, uint32_t regno, 1004 uint32_t num, uint32_t *out) 1005 { 1006 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1007 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1008 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1009 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1010 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1011 while (num--) 1012 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1013 } 1014 1015 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1016 { 1017 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1018 * field when performing a select_se_sh so it should be 1019 * zero here */ 1020 WARN_ON(simd != 0); 1021 1022 /* type 3 wave data */ 1023 dst[(*no_fields)++] = 3; 1024 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1025 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1026 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1027 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1028 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1029 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1030 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1031 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1032 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1033 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1034 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1035 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1036 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1037 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1038 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1039 } 1040 1041 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1042 uint32_t wave, uint32_t start, 1043 uint32_t size, uint32_t *dst) 1044 { 1045 WARN_ON(simd != 0); 1046 1047 wave_read_regs( 1048 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1049 dst); 1050 } 1051 1052 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1053 uint32_t wave, uint32_t thread, 1054 uint32_t start, uint32_t size, 1055 uint32_t *dst) 1056 { 1057 wave_read_regs( 1058 adev, wave, thread, 1059 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1060 } 1061 1062 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1063 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1064 { 1065 soc21_grbm_select(adev, me, pipe, q, vm); 1066 } 1067 1068 /* all sizes are in bytes */ 1069 #define MQD_SHADOW_BASE_SIZE 73728 1070 #define MQD_SHADOW_BASE_ALIGNMENT 256 1071 #define MQD_FWWORKAREA_SIZE 484 1072 #define MQD_FWWORKAREA_ALIGNMENT 256 1073 1074 static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 1075 struct amdgpu_gfx_shadow_info *shadow_info) 1076 { 1077 /* for gfx */ 1078 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1079 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1080 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1081 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1082 /* for compute */ 1083 shadow_info->eop_size = GFX11_MEC_HPD_SIZE; 1084 shadow_info->eop_alignment = 256; 1085 } 1086 1087 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1088 struct amdgpu_gfx_shadow_info *shadow_info, 1089 bool skip_check) 1090 { 1091 if (adev->gfx.cp_gfx_shadow || skip_check) { 1092 gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 1093 return 0; 1094 } else { 1095 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1096 return -ENOTSUPP; 1097 } 1098 } 1099 1100 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1101 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1102 .select_se_sh = &gfx_v11_0_select_se_sh, 1103 .read_wave_data = &gfx_v11_0_read_wave_data, 1104 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1105 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1106 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1107 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1108 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1109 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 1110 }; 1111 1112 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1113 { 1114 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1115 case IP_VERSION(11, 0, 0): 1116 case IP_VERSION(11, 0, 2): 1117 adev->gfx.config.max_hw_contexts = 8; 1118 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1119 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1120 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1121 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1122 break; 1123 case IP_VERSION(11, 0, 3): 1124 adev->gfx.ras = &gfx_v11_0_3_ras; 1125 adev->gfx.config.max_hw_contexts = 8; 1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1130 break; 1131 case IP_VERSION(11, 0, 1): 1132 case IP_VERSION(11, 0, 4): 1133 case IP_VERSION(11, 5, 0): 1134 case IP_VERSION(11, 5, 1): 1135 case IP_VERSION(11, 5, 2): 1136 case IP_VERSION(11, 5, 3): 1137 case IP_VERSION(11, 5, 4): 1138 case IP_VERSION(11, 5, 6): 1139 case IP_VERSION(11, 7, 0): 1140 case IP_VERSION(11, 7, 1): 1141 adev->gfx.config.max_hw_contexts = 8; 1142 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1143 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1144 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1145 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1146 break; 1147 default: 1148 BUG(); 1149 break; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1156 int me, int pipe, int queue) 1157 { 1158 struct amdgpu_ring *ring; 1159 unsigned int irq_type; 1160 unsigned int hw_prio; 1161 1162 ring = &adev->gfx.gfx_ring[ring_id]; 1163 1164 ring->me = me; 1165 ring->pipe = pipe; 1166 ring->queue = queue; 1167 1168 ring->ring_obj = NULL; 1169 ring->use_doorbell = true; 1170 if (adev->gfx.disable_kq) { 1171 ring->no_scheduler = true; 1172 ring->no_user_submission = true; 1173 } 1174 1175 if (!ring_id) 1176 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1177 else 1178 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1179 ring->vm_hub = AMDGPU_GFXHUB(0); 1180 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1181 1182 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1183 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1184 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1185 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1186 hw_prio, NULL); 1187 } 1188 1189 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1190 int mec, int pipe, int queue) 1191 { 1192 int r; 1193 unsigned irq_type; 1194 struct amdgpu_ring *ring; 1195 unsigned int hw_prio; 1196 1197 ring = &adev->gfx.compute_ring[ring_id]; 1198 1199 /* mec0 is me1 */ 1200 ring->me = mec + 1; 1201 ring->pipe = pipe; 1202 ring->queue = queue; 1203 1204 ring->ring_obj = NULL; 1205 ring->use_doorbell = true; 1206 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1207 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1208 + (ring_id * GFX11_MEC_HPD_SIZE); 1209 ring->vm_hub = AMDGPU_GFXHUB(0); 1210 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1211 1212 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1213 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1214 + ring->pipe; 1215 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1216 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1217 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1218 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1219 hw_prio, NULL); 1220 if (r) 1221 return r; 1222 1223 return 0; 1224 } 1225 1226 static struct { 1227 SOC21_FIRMWARE_ID id; 1228 unsigned int offset; 1229 unsigned int size; 1230 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1231 1232 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1233 { 1234 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1235 1236 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1237 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1238 rlc_autoload_info[ucode->id].id = ucode->id; 1239 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1240 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1241 1242 ucode++; 1243 } 1244 } 1245 1246 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1247 { 1248 uint32_t total_size = 0; 1249 SOC21_FIRMWARE_ID id; 1250 1251 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1252 1253 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1254 total_size += rlc_autoload_info[id].size; 1255 1256 /* In case the offset in rlc toc ucode is aligned */ 1257 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1258 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1259 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1260 1261 return total_size; 1262 } 1263 1264 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1265 { 1266 int r; 1267 uint32_t total_size; 1268 1269 total_size = gfx_v11_0_calc_toc_total_size(adev); 1270 1271 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1272 AMDGPU_GEM_DOMAIN_VRAM | 1273 AMDGPU_GEM_DOMAIN_GTT, 1274 &adev->gfx.rlc.rlc_autoload_bo, 1275 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1276 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1277 1278 if (r) { 1279 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1280 return r; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1287 SOC21_FIRMWARE_ID id, 1288 const void *fw_data, 1289 uint32_t fw_size, 1290 uint32_t *fw_autoload_mask) 1291 { 1292 uint32_t toc_offset; 1293 uint32_t toc_fw_size; 1294 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1295 1296 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1297 return; 1298 1299 toc_offset = rlc_autoload_info[id].offset; 1300 toc_fw_size = rlc_autoload_info[id].size; 1301 1302 if (fw_size == 0) 1303 fw_size = toc_fw_size; 1304 1305 if (fw_size > toc_fw_size) 1306 fw_size = toc_fw_size; 1307 1308 memcpy(ptr + toc_offset, fw_data, fw_size); 1309 1310 if (fw_size < toc_fw_size) 1311 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1312 1313 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1314 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1315 } 1316 1317 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1318 uint32_t *fw_autoload_mask) 1319 { 1320 void *data; 1321 uint32_t size; 1322 uint64_t *toc_ptr; 1323 1324 *(uint64_t *)fw_autoload_mask |= 0x1; 1325 1326 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1327 1328 data = adev->psp.toc.start_addr; 1329 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1330 1331 toc_ptr = (uint64_t *)data + size / 8 - 1; 1332 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1333 1334 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1335 data, size, fw_autoload_mask); 1336 } 1337 1338 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1339 uint32_t *fw_autoload_mask) 1340 { 1341 const __le32 *fw_data; 1342 uint32_t fw_size; 1343 const struct gfx_firmware_header_v1_0 *cp_hdr; 1344 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1345 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1346 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1347 uint16_t version_major, version_minor; 1348 1349 if (adev->gfx.rs64_enable) { 1350 /* pfp ucode */ 1351 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1352 adev->gfx.pfp_fw->data; 1353 /* instruction */ 1354 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1355 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1356 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1357 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1358 fw_data, fw_size, fw_autoload_mask); 1359 /* data */ 1360 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1361 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1362 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1363 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1364 fw_data, fw_size, fw_autoload_mask); 1365 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1366 fw_data, fw_size, fw_autoload_mask); 1367 /* me ucode */ 1368 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1369 adev->gfx.me_fw->data; 1370 /* instruction */ 1371 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1372 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1373 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1374 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1375 fw_data, fw_size, fw_autoload_mask); 1376 /* data */ 1377 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1378 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1379 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1380 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1381 fw_data, fw_size, fw_autoload_mask); 1382 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1383 fw_data, fw_size, fw_autoload_mask); 1384 /* mec ucode */ 1385 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1386 adev->gfx.mec_fw->data; 1387 /* instruction */ 1388 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1389 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1390 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1391 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1392 fw_data, fw_size, fw_autoload_mask); 1393 /* data */ 1394 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1395 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1396 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1397 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1398 fw_data, fw_size, fw_autoload_mask); 1399 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1400 fw_data, fw_size, fw_autoload_mask); 1401 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1402 fw_data, fw_size, fw_autoload_mask); 1403 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1404 fw_data, fw_size, fw_autoload_mask); 1405 } else { 1406 /* pfp ucode */ 1407 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1408 adev->gfx.pfp_fw->data; 1409 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1410 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1411 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1412 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1413 fw_data, fw_size, fw_autoload_mask); 1414 1415 /* me ucode */ 1416 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1417 adev->gfx.me_fw->data; 1418 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1419 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1420 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1421 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1422 fw_data, fw_size, fw_autoload_mask); 1423 1424 /* mec ucode */ 1425 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1426 adev->gfx.mec_fw->data; 1427 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1428 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1429 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1430 cp_hdr->jt_size * 4; 1431 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1432 fw_data, fw_size, fw_autoload_mask); 1433 } 1434 1435 /* rlc ucode */ 1436 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1437 adev->gfx.rlc_fw->data; 1438 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1439 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1440 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1441 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1442 fw_data, fw_size, fw_autoload_mask); 1443 1444 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1445 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1446 if (version_major == 2) { 1447 if (version_minor >= 2) { 1448 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1449 1450 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1451 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1452 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1453 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1454 fw_data, fw_size, fw_autoload_mask); 1455 1456 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1457 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1458 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1459 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1460 fw_data, fw_size, fw_autoload_mask); 1461 } 1462 } 1463 } 1464 1465 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1466 uint32_t *fw_autoload_mask) 1467 { 1468 const __le32 *fw_data; 1469 uint32_t fw_size; 1470 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1471 1472 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1473 adev->sdma.instance[0].fw->data; 1474 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1475 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1476 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1477 1478 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1479 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1480 1481 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1482 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1483 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1484 1485 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1486 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1487 } 1488 1489 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1490 uint32_t *fw_autoload_mask) 1491 { 1492 const __le32 *fw_data; 1493 unsigned fw_size; 1494 const struct mes_firmware_header_v1_0 *mes_hdr; 1495 int pipe, ucode_id, data_id; 1496 1497 for (pipe = 0; pipe < 2; pipe++) { 1498 if (pipe==0) { 1499 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1500 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1501 } else { 1502 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1503 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1504 } 1505 1506 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1507 adev->mes.fw[pipe]->data; 1508 1509 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1510 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1511 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1512 1513 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1514 ucode_id, fw_data, fw_size, fw_autoload_mask); 1515 1516 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1517 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1518 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1519 1520 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1521 data_id, fw_data, fw_size, fw_autoload_mask); 1522 } 1523 } 1524 1525 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1526 { 1527 uint32_t rlc_g_offset, rlc_g_size; 1528 uint64_t gpu_addr; 1529 uint32_t autoload_fw_id[2]; 1530 1531 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1532 1533 /* RLC autoload sequence 2: copy ucode */ 1534 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1535 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1536 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1537 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1538 1539 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1540 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1541 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1542 1543 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1544 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1545 1546 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1547 1548 /* RLC autoload sequence 3: load IMU fw */ 1549 if (adev->gfx.imu.funcs->load_microcode) 1550 adev->gfx.imu.funcs->load_microcode(adev); 1551 /* RLC autoload sequence 4 init IMU fw */ 1552 if (adev->gfx.imu.funcs->setup_imu) 1553 adev->gfx.imu.funcs->setup_imu(adev); 1554 if (adev->gfx.imu.funcs->start_imu) 1555 adev->gfx.imu.funcs->start_imu(adev); 1556 1557 /* RLC autoload sequence 5 disable gpa mode */ 1558 gfx_v11_0_disable_gpa_mode(adev); 1559 1560 return 0; 1561 } 1562 1563 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1564 { 1565 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1566 uint32_t *ptr; 1567 uint32_t inst; 1568 1569 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1570 if (!ptr) { 1571 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1572 adev->gfx.ip_dump_core = NULL; 1573 } else { 1574 adev->gfx.ip_dump_core = ptr; 1575 } 1576 1577 /* Allocate memory for compute queue registers for all the instances */ 1578 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1579 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1580 adev->gfx.mec.num_queue_per_pipe; 1581 1582 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1583 if (!ptr) { 1584 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1585 adev->gfx.ip_dump_compute_queues = NULL; 1586 } else { 1587 adev->gfx.ip_dump_compute_queues = ptr; 1588 } 1589 1590 /* Allocate memory for gfx queue registers for all the instances */ 1591 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1592 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1593 adev->gfx.me.num_queue_per_pipe; 1594 1595 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1596 if (!ptr) { 1597 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1598 adev->gfx.ip_dump_gfx_queues = NULL; 1599 } else { 1600 adev->gfx.ip_dump_gfx_queues = ptr; 1601 } 1602 } 1603 1604 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1605 { 1606 int i, j, k, r, ring_id; 1607 int xcc_id = 0; 1608 struct amdgpu_device *adev = ip_block->adev; 1609 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1610 1611 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1612 1613 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1614 case IP_VERSION(11, 0, 0): 1615 case IP_VERSION(11, 0, 1): 1616 case IP_VERSION(11, 0, 2): 1617 case IP_VERSION(11, 0, 3): 1618 case IP_VERSION(11, 0, 4): 1619 case IP_VERSION(11, 5, 0): 1620 case IP_VERSION(11, 5, 1): 1621 case IP_VERSION(11, 5, 2): 1622 case IP_VERSION(11, 5, 3): 1623 case IP_VERSION(11, 5, 4): 1624 case IP_VERSION(11, 5, 6): 1625 case IP_VERSION(11, 7, 0): 1626 case IP_VERSION(11, 7, 1): 1627 adev->gfx.me.num_me = 1; 1628 adev->gfx.me.num_pipe_per_me = 1; 1629 adev->gfx.me.num_queue_per_pipe = 2; 1630 adev->gfx.mec.num_mec = 1; 1631 adev->gfx.mec.num_pipe_per_mec = 4; 1632 adev->gfx.mec.num_queue_per_pipe = 4; 1633 break; 1634 default: 1635 adev->gfx.me.num_me = 1; 1636 adev->gfx.me.num_pipe_per_me = 1; 1637 adev->gfx.me.num_queue_per_pipe = 1; 1638 adev->gfx.mec.num_mec = 1; 1639 adev->gfx.mec.num_pipe_per_mec = 4; 1640 adev->gfx.mec.num_queue_per_pipe = 8; 1641 break; 1642 } 1643 1644 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1645 case IP_VERSION(11, 0, 0): 1646 case IP_VERSION(11, 0, 2): 1647 case IP_VERSION(11, 0, 3): 1648 if (!adev->gfx.disable_uq && 1649 adev->gfx.me_fw_version >= 2420 && 1650 adev->gfx.pfp_fw_version >= 2580 && 1651 adev->gfx.mec_fw_version >= 2650 && 1652 adev->mes.fw_version[0] >= 120) { 1653 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1654 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1655 } 1656 break; 1657 case IP_VERSION(11, 0, 1): 1658 case IP_VERSION(11, 0, 4): 1659 case IP_VERSION(11, 5, 0): 1660 case IP_VERSION(11, 5, 1): 1661 case IP_VERSION(11, 5, 2): 1662 case IP_VERSION(11, 5, 3): 1663 /* add firmware version checks here */ 1664 if (0 && !adev->gfx.disable_uq) { 1665 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1666 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1667 } 1668 break; 1669 default: 1670 break; 1671 } 1672 1673 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1674 case IP_VERSION(11, 0, 0): 1675 case IP_VERSION(11, 0, 2): 1676 case IP_VERSION(11, 0, 3): 1677 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1678 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1679 if (adev->gfx.me_fw_version >= 2280 && 1680 adev->gfx.pfp_fw_version >= 2370 && 1681 adev->gfx.mec_fw_version >= 2450 && 1682 adev->mes.fw_version[0] >= 99) { 1683 adev->gfx.enable_cleaner_shader = true; 1684 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1685 if (r) { 1686 adev->gfx.enable_cleaner_shader = false; 1687 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1688 } 1689 } 1690 break; 1691 case IP_VERSION(11, 0, 1): 1692 case IP_VERSION(11, 0, 4): 1693 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1694 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1695 if (adev->gfx.pfp_fw_version >= 102 && 1696 adev->gfx.mec_fw_version >= 66 && 1697 adev->mes.fw_version[0] >= 128) { 1698 adev->gfx.enable_cleaner_shader = true; 1699 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1700 if (r) { 1701 adev->gfx.enable_cleaner_shader = false; 1702 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1703 } 1704 } 1705 break; 1706 case IP_VERSION(11, 5, 0): 1707 case IP_VERSION(11, 5, 1): 1708 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1709 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1710 if (adev->gfx.mec_fw_version >= 26 && 1711 adev->mes.fw_version[0] >= 114) { 1712 adev->gfx.enable_cleaner_shader = true; 1713 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1714 if (r) { 1715 adev->gfx.enable_cleaner_shader = false; 1716 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1717 } 1718 } 1719 break; 1720 case IP_VERSION(11, 5, 2): 1721 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1722 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1723 if (adev->gfx.me_fw_version >= 12 && 1724 adev->gfx.pfp_fw_version >= 15 && 1725 adev->gfx.mec_fw_version >= 15) { 1726 adev->gfx.enable_cleaner_shader = true; 1727 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1728 if (r) { 1729 adev->gfx.enable_cleaner_shader = false; 1730 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1731 } 1732 } 1733 break; 1734 case IP_VERSION(11, 5, 3): 1735 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1736 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1737 if (adev->gfx.me_fw_version >= 7 && 1738 adev->gfx.pfp_fw_version >= 8 && 1739 adev->gfx.mec_fw_version >= 8) { 1740 adev->gfx.enable_cleaner_shader = true; 1741 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1742 if (r) { 1743 adev->gfx.enable_cleaner_shader = false; 1744 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1745 } 1746 } 1747 break; 1748 case IP_VERSION(11, 5, 4): 1749 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1750 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1751 if (adev->gfx.me_fw_version >= 4 && 1752 adev->gfx.pfp_fw_version >= 7 && 1753 adev->gfx.mec_fw_version >= 5) { 1754 adev->gfx.enable_cleaner_shader = true; 1755 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1756 if (r) { 1757 adev->gfx.enable_cleaner_shader = false; 1758 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1759 } 1760 } 1761 break; 1762 default: 1763 adev->gfx.enable_cleaner_shader = false; 1764 break; 1765 } 1766 1767 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1768 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1769 amdgpu_sriov_is_pp_one_vf(adev)) 1770 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1771 1772 /* EOP Event */ 1773 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1774 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1775 &adev->gfx.eop_irq); 1776 if (r) 1777 return r; 1778 1779 /* Bad opcode Event */ 1780 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1781 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1782 &adev->gfx.bad_op_irq); 1783 if (r) 1784 return r; 1785 1786 /* Privileged reg */ 1787 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1788 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1789 &adev->gfx.priv_reg_irq); 1790 if (r) 1791 return r; 1792 1793 /* Privileged inst */ 1794 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1795 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1796 &adev->gfx.priv_inst_irq); 1797 if (r) 1798 return r; 1799 1800 /* FED error */ 1801 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1802 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1803 &adev->gfx.rlc_gc_fed_irq); 1804 if (r) 1805 return r; 1806 1807 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1808 1809 gfx_v11_0_me_init(adev); 1810 1811 r = gfx_v11_0_rlc_init(adev); 1812 if (r) { 1813 DRM_ERROR("Failed to init rlc BOs!\n"); 1814 return r; 1815 } 1816 1817 r = gfx_v11_0_mec_init(adev); 1818 if (r) { 1819 DRM_ERROR("Failed to init MEC BOs!\n"); 1820 return r; 1821 } 1822 1823 if (adev->gfx.num_gfx_rings) { 1824 ring_id = 0; 1825 /* set up the gfx ring */ 1826 for (i = 0; i < adev->gfx.me.num_me; i++) { 1827 for (j = 0; j < num_queue_per_pipe; j++) { 1828 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1829 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1830 continue; 1831 1832 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1833 i, k, j); 1834 if (r) 1835 return r; 1836 ring_id++; 1837 } 1838 } 1839 } 1840 } 1841 1842 if (adev->gfx.num_compute_rings) { 1843 ring_id = 0; 1844 /* set up the compute queues - allocate horizontally across pipes */ 1845 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1846 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1847 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1848 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1849 k, j)) 1850 continue; 1851 1852 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1853 i, k, j); 1854 if (r) 1855 return r; 1856 1857 ring_id++; 1858 } 1859 } 1860 } 1861 } 1862 1863 adev->gfx.gfx_supported_reset = 1864 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1865 adev->gfx.compute_supported_reset = 1866 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1867 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1868 case IP_VERSION(11, 0, 0): 1869 case IP_VERSION(11, 0, 2): 1870 case IP_VERSION(11, 0, 3): 1871 if ((adev->gfx.me_fw_version >= 2280) && 1872 (adev->gfx.mec_fw_version >= 2410) && 1873 !amdgpu_sriov_vf(adev) && 1874 !adev->debug_disable_gpu_ring_reset) { 1875 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1876 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1877 } 1878 break; 1879 default: 1880 if (!amdgpu_sriov_vf(adev) && 1881 !adev->debug_disable_gpu_ring_reset) { 1882 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1883 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1884 } 1885 break; 1886 } 1887 1888 if (!adev->enable_mes_kiq) { 1889 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1890 if (r) { 1891 DRM_ERROR("Failed to init KIQ BOs!\n"); 1892 return r; 1893 } 1894 1895 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1896 if (r) 1897 return r; 1898 } 1899 1900 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1901 if (r) 1902 return r; 1903 1904 /* allocate visible FB for rlc auto-loading fw */ 1905 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1906 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1907 if (r) 1908 return r; 1909 } 1910 1911 r = gfx_v11_0_gpu_early_init(adev); 1912 if (r) 1913 return r; 1914 1915 if (amdgpu_gfx_ras_sw_init(adev)) { 1916 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1917 return -EINVAL; 1918 } 1919 1920 gfx_v11_0_alloc_ip_dump(adev); 1921 1922 r = amdgpu_gfx_sysfs_init(adev); 1923 if (r) 1924 return r; 1925 1926 adev->gfx.me.use_mmio_for_reset = false; 1927 adev->gfx.mec.use_mmio_for_reset = true; 1928 1929 mutex_init(&adev->gfx.mec.reset_mutex); 1930 1931 return 0; 1932 } 1933 1934 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1935 { 1936 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1937 &adev->gfx.pfp.pfp_fw_gpu_addr, 1938 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1939 1940 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1941 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1942 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1943 } 1944 1945 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1946 { 1947 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1948 &adev->gfx.me.me_fw_gpu_addr, 1949 (void **)&adev->gfx.me.me_fw_ptr); 1950 1951 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1952 &adev->gfx.me.me_fw_data_gpu_addr, 1953 (void **)&adev->gfx.me.me_fw_data_ptr); 1954 } 1955 1956 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1957 { 1958 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1959 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1960 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1961 } 1962 1963 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1964 { 1965 int i; 1966 struct amdgpu_device *adev = ip_block->adev; 1967 1968 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1969 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1970 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1971 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1972 1973 amdgpu_gfx_mqd_sw_fini(adev, 0); 1974 1975 if (!adev->enable_mes_kiq) { 1976 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1977 amdgpu_gfx_kiq_fini(adev, 0); 1978 } 1979 1980 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1981 1982 gfx_v11_0_pfp_fini(adev); 1983 gfx_v11_0_me_fini(adev); 1984 gfx_v11_0_rlc_fini(adev); 1985 gfx_v11_0_mec_fini(adev); 1986 1987 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1988 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1989 1990 gfx_v11_0_free_microcode(adev); 1991 1992 amdgpu_gfx_sysfs_fini(adev); 1993 1994 kfree(adev->gfx.ip_dump_core); 1995 kfree(adev->gfx.ip_dump_compute_queues); 1996 kfree(adev->gfx.ip_dump_gfx_queues); 1997 1998 return 0; 1999 } 2000 2001 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 2002 u32 sh_num, u32 instance, int xcc_id) 2003 { 2004 u32 data; 2005 2006 if (instance == 0xffffffff) 2007 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 2008 INSTANCE_BROADCAST_WRITES, 1); 2009 else 2010 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 2011 instance); 2012 2013 if (se_num == 0xffffffff) 2014 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 2015 1); 2016 else 2017 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2018 2019 if (sh_num == 0xffffffff) 2020 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 2021 1); 2022 else 2023 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 2024 2025 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 2026 } 2027 2028 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 2029 { 2030 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 2031 2032 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 2033 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 2034 CC_GC_SA_UNIT_DISABLE, 2035 SA_DISABLE); 2036 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 2037 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 2038 GC_USER_SA_UNIT_DISABLE, 2039 SA_DISABLE); 2040 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 2041 adev->gfx.config.max_shader_engines); 2042 2043 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 2044 } 2045 2046 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2047 { 2048 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 2049 u32 rb_mask; 2050 2051 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 2052 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 2053 CC_RB_BACKEND_DISABLE, 2054 BACKEND_DISABLE); 2055 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 2056 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 2057 GC_USER_RB_BACKEND_DISABLE, 2058 BACKEND_DISABLE); 2059 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 2060 adev->gfx.config.max_shader_engines); 2061 2062 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 2063 } 2064 2065 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 2066 { 2067 u32 rb_bitmap_per_sa; 2068 u32 rb_bitmap_width_per_sa; 2069 u32 max_sa; 2070 u32 active_sa_bitmap; 2071 u32 global_active_rb_bitmap; 2072 u32 active_rb_bitmap = 0; 2073 u32 i; 2074 2075 /* query sa bitmap from SA_UNIT_DISABLE registers */ 2076 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 2077 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 2078 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 2079 2080 /* generate active rb bitmap according to active sa bitmap */ 2081 max_sa = adev->gfx.config.max_shader_engines * 2082 adev->gfx.config.max_sh_per_se; 2083 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 2084 adev->gfx.config.max_sh_per_se; 2085 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 2086 2087 for (i = 0; i < max_sa; i++) { 2088 if (active_sa_bitmap & (1 << i)) 2089 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 2090 } 2091 2092 active_rb_bitmap &= global_active_rb_bitmap; 2093 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 2094 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 2095 } 2096 2097 #define DEFAULT_SH_MEM_BASES (0x6000) 2098 #define LDS_APP_BASE 0x1 2099 #define SCRATCH_APP_BASE 0x2 2100 2101 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 2102 { 2103 int i; 2104 uint32_t sh_mem_bases; 2105 uint32_t data; 2106 2107 /* 2108 * Configure apertures: 2109 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2110 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2111 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2112 */ 2113 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 2114 SCRATCH_APP_BASE; 2115 2116 mutex_lock(&adev->srbm_mutex); 2117 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2118 soc21_grbm_select(adev, 0, 0, 0, i); 2119 /* CP and shaders */ 2120 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2121 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 2122 2123 /* Enable trap for each kfd vmid. */ 2124 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 2125 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 2126 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 2127 } 2128 soc21_grbm_select(adev, 0, 0, 0, 0); 2129 mutex_unlock(&adev->srbm_mutex); 2130 2131 /* 2132 * Initialize all compute VMIDs to have no GDS, GWS, or OA 2133 * access. These should be enabled by FW for target VMIDs. 2134 */ 2135 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2136 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 2137 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 2138 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 2139 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 2140 } 2141 } 2142 2143 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 2144 { 2145 int vmid; 2146 2147 /* 2148 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2149 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2150 * the driver can enable them for graphics. VMID0 should maintain 2151 * access so that HWS firmware can save/restore entries. 2152 */ 2153 for (vmid = 1; vmid < 16; vmid++) { 2154 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 2155 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 2156 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 2157 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 2158 } 2159 } 2160 2161 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 2162 { 2163 /* TODO: harvest feature to be added later. */ 2164 } 2165 2166 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2167 { 2168 /* TCCs are global (not instanced). */ 2169 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2170 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2171 2172 adev->gfx.config.tcc_disabled_mask = 2173 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2174 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2175 } 2176 2177 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2178 { 2179 u32 tmp; 2180 int i; 2181 2182 if (!amdgpu_sriov_vf(adev)) 2183 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2184 2185 gfx_v11_0_setup_rb(adev); 2186 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2187 gfx_v11_0_get_tcc_info(adev); 2188 adev->gfx.config.pa_sc_tile_steering_override = 0; 2189 2190 /* Set whether texture coordinate truncation is conformant. */ 2191 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2192 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2193 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2194 2195 /* XXX SH_MEM regs */ 2196 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2197 mutex_lock(&adev->srbm_mutex); 2198 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2199 soc21_grbm_select(adev, 0, 0, 0, i); 2200 /* CP and shaders */ 2201 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2202 if (i != 0) { 2203 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2204 (adev->gmc.private_aperture_start >> 48)); 2205 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2206 (adev->gmc.shared_aperture_start >> 48)); 2207 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2208 } 2209 } 2210 soc21_grbm_select(adev, 0, 0, 0, 0); 2211 2212 mutex_unlock(&adev->srbm_mutex); 2213 2214 gfx_v11_0_init_compute_vmid(adev); 2215 gfx_v11_0_init_gds_vmid(adev); 2216 } 2217 2218 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2219 int me, int pipe) 2220 { 2221 if (me != 0) 2222 return 0; 2223 2224 switch (pipe) { 2225 case 0: 2226 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2227 case 1: 2228 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2229 default: 2230 return 0; 2231 } 2232 } 2233 2234 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2235 int me, int pipe) 2236 { 2237 /* 2238 * amdgpu controls only the first MEC. That's why this function only 2239 * handles the setting of interrupts for this specific MEC. All other 2240 * pipes' interrupts are set by amdkfd. 2241 */ 2242 if (me != 1) 2243 return 0; 2244 2245 switch (pipe) { 2246 case 0: 2247 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2248 case 1: 2249 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2250 case 2: 2251 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2252 case 3: 2253 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2254 default: 2255 return 0; 2256 } 2257 } 2258 2259 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2260 bool enable) 2261 { 2262 u32 tmp, cp_int_cntl_reg; 2263 int i, j; 2264 2265 if (amdgpu_sriov_vf(adev)) 2266 return; 2267 2268 for (i = 0; i < adev->gfx.me.num_me; i++) { 2269 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2270 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2271 2272 if (cp_int_cntl_reg) { 2273 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2274 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2275 enable ? 1 : 0); 2276 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2277 enable ? 1 : 0); 2278 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2279 enable ? 1 : 0); 2280 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2281 enable ? 1 : 0); 2282 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2283 } 2284 } 2285 } 2286 } 2287 2288 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2289 { 2290 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2291 2292 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2293 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2294 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2295 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2296 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2297 2298 return 0; 2299 } 2300 2301 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2302 { 2303 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2304 2305 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2306 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2307 } 2308 2309 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2310 { 2311 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2312 udelay(50); 2313 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2314 udelay(50); 2315 } 2316 2317 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2318 bool enable) 2319 { 2320 uint32_t rlc_pg_cntl; 2321 2322 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2323 2324 if (!enable) { 2325 /* RLC_PG_CNTL[23] = 0 (default) 2326 * RLC will wait for handshake acks with SMU 2327 * GFXOFF will be enabled 2328 * RLC_PG_CNTL[23] = 1 2329 * RLC will not issue any message to SMU 2330 * hence no handshake between SMU & RLC 2331 * GFXOFF will be disabled 2332 */ 2333 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2334 } else 2335 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2336 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2337 } 2338 2339 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2340 { 2341 /* TODO: enable rlc & smu handshake until smu 2342 * and gfxoff feature works as expected */ 2343 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2344 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2345 2346 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2347 udelay(50); 2348 } 2349 2350 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2351 { 2352 uint32_t tmp; 2353 2354 /* enable Save Restore Machine */ 2355 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2356 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2357 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2358 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2359 } 2360 2361 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2362 { 2363 const struct rlc_firmware_header_v2_0 *hdr; 2364 const __le32 *fw_data; 2365 unsigned i, fw_size; 2366 2367 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2368 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2369 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2370 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2371 2372 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2373 RLCG_UCODE_LOADING_START_ADDRESS); 2374 2375 for (i = 0; i < fw_size; i++) 2376 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2377 le32_to_cpup(fw_data++)); 2378 2379 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2380 } 2381 2382 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2383 { 2384 const struct rlc_firmware_header_v2_2 *hdr; 2385 const __le32 *fw_data; 2386 unsigned i, fw_size; 2387 u32 tmp; 2388 2389 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2390 2391 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2392 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2393 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2394 2395 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2396 2397 for (i = 0; i < fw_size; i++) { 2398 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2399 msleep(1); 2400 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2401 le32_to_cpup(fw_data++)); 2402 } 2403 2404 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2405 2406 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2407 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2408 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2409 2410 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2411 for (i = 0; i < fw_size; i++) { 2412 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2413 msleep(1); 2414 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2415 le32_to_cpup(fw_data++)); 2416 } 2417 2418 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2419 2420 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2421 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2422 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2423 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2424 } 2425 2426 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2427 { 2428 const struct rlc_firmware_header_v2_3 *hdr; 2429 const __le32 *fw_data; 2430 unsigned i, fw_size; 2431 u32 tmp; 2432 2433 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2434 2435 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2436 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2437 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2438 2439 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2440 2441 for (i = 0; i < fw_size; i++) { 2442 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2443 msleep(1); 2444 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2445 le32_to_cpup(fw_data++)); 2446 } 2447 2448 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2449 2450 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2451 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2452 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2453 2454 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2455 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2456 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2457 2458 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2459 2460 for (i = 0; i < fw_size; i++) { 2461 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2462 msleep(1); 2463 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2464 le32_to_cpup(fw_data++)); 2465 } 2466 2467 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2468 2469 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2470 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2471 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2472 } 2473 2474 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2475 { 2476 const struct rlc_firmware_header_v2_0 *hdr; 2477 uint16_t version_major; 2478 uint16_t version_minor; 2479 2480 if (!adev->gfx.rlc_fw) 2481 return -EINVAL; 2482 2483 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2484 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2485 2486 version_major = le16_to_cpu(hdr->header.header_version_major); 2487 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2488 2489 if (version_major == 2) { 2490 gfx_v11_0_load_rlcg_microcode(adev); 2491 if (amdgpu_dpm == 1) { 2492 if (version_minor >= 2) 2493 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2494 if (version_minor == 3) 2495 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2496 } 2497 2498 return 0; 2499 } 2500 2501 return -EINVAL; 2502 } 2503 2504 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2505 { 2506 int r; 2507 2508 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2509 gfx_v11_0_init_csb(adev); 2510 2511 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2512 gfx_v11_0_rlc_enable_srm(adev); 2513 } else { 2514 if (amdgpu_sriov_vf(adev)) { 2515 gfx_v11_0_init_csb(adev); 2516 return 0; 2517 } 2518 2519 adev->gfx.rlc.funcs->stop(adev); 2520 2521 /* disable CG */ 2522 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2523 2524 /* disable PG */ 2525 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2526 2527 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2528 /* legacy rlc firmware loading */ 2529 r = gfx_v11_0_rlc_load_microcode(adev); 2530 if (r) 2531 return r; 2532 } 2533 2534 gfx_v11_0_init_csb(adev); 2535 2536 adev->gfx.rlc.funcs->start(adev); 2537 } 2538 return 0; 2539 } 2540 2541 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2542 { 2543 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2544 uint32_t tmp; 2545 int i; 2546 2547 /* Trigger an invalidation of the L1 instruction caches */ 2548 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2549 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2550 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2551 2552 /* Wait for invalidation complete */ 2553 for (i = 0; i < usec_timeout; i++) { 2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2555 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2556 INVALIDATE_CACHE_COMPLETE)) 2557 break; 2558 udelay(1); 2559 } 2560 2561 if (i >= usec_timeout) { 2562 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2563 return -EINVAL; 2564 } 2565 2566 if (amdgpu_emu_mode == 1) 2567 amdgpu_device_flush_hdp(adev, NULL); 2568 2569 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2570 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2571 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2572 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2573 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2574 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2575 2576 /* Program me ucode address into intruction cache address register */ 2577 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2578 lower_32_bits(addr) & 0xFFFFF000); 2579 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2580 upper_32_bits(addr)); 2581 2582 return 0; 2583 } 2584 2585 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2586 { 2587 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2588 uint32_t tmp; 2589 int i; 2590 2591 /* Trigger an invalidation of the L1 instruction caches */ 2592 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2593 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2594 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2595 2596 /* Wait for invalidation complete */ 2597 for (i = 0; i < usec_timeout; i++) { 2598 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2599 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2600 INVALIDATE_CACHE_COMPLETE)) 2601 break; 2602 udelay(1); 2603 } 2604 2605 if (i >= usec_timeout) { 2606 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2607 return -EINVAL; 2608 } 2609 2610 if (amdgpu_emu_mode == 1) 2611 amdgpu_device_flush_hdp(adev, NULL); 2612 2613 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2614 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2615 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2616 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2617 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2618 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2619 2620 /* Program pfp ucode address into intruction cache address register */ 2621 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2622 lower_32_bits(addr) & 0xFFFFF000); 2623 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2624 upper_32_bits(addr)); 2625 2626 return 0; 2627 } 2628 2629 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2630 { 2631 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2632 uint32_t tmp; 2633 int i; 2634 2635 /* Trigger an invalidation of the L1 instruction caches */ 2636 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2637 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2638 2639 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2640 2641 /* Wait for invalidation complete */ 2642 for (i = 0; i < usec_timeout; i++) { 2643 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2644 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2645 INVALIDATE_CACHE_COMPLETE)) 2646 break; 2647 udelay(1); 2648 } 2649 2650 if (i >= usec_timeout) { 2651 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2652 return -EINVAL; 2653 } 2654 2655 if (amdgpu_emu_mode == 1) 2656 amdgpu_device_flush_hdp(adev, NULL); 2657 2658 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2659 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2660 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2661 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2662 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2663 2664 /* Program mec1 ucode address into intruction cache address register */ 2665 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2666 lower_32_bits(addr) & 0xFFFFF000); 2667 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2668 upper_32_bits(addr)); 2669 2670 return 0; 2671 } 2672 2673 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2674 { 2675 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2676 uint32_t tmp; 2677 unsigned i, pipe_id; 2678 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2679 2680 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2681 adev->gfx.pfp_fw->data; 2682 2683 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2684 lower_32_bits(addr)); 2685 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2686 upper_32_bits(addr)); 2687 2688 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2689 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2690 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2691 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2692 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2693 2694 /* 2695 * Programming any of the CP_PFP_IC_BASE registers 2696 * forces invalidation of the ME L1 I$. Wait for the 2697 * invalidation complete 2698 */ 2699 for (i = 0; i < usec_timeout; i++) { 2700 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2701 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2702 INVALIDATE_CACHE_COMPLETE)) 2703 break; 2704 udelay(1); 2705 } 2706 2707 if (i >= usec_timeout) { 2708 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2709 return -EINVAL; 2710 } 2711 2712 /* Prime the L1 instruction caches */ 2713 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2714 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2715 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2716 /* Waiting for cache primed*/ 2717 for (i = 0; i < usec_timeout; i++) { 2718 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2719 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2720 ICACHE_PRIMED)) 2721 break; 2722 udelay(1); 2723 } 2724 2725 if (i >= usec_timeout) { 2726 dev_err(adev->dev, "failed to prime instruction cache\n"); 2727 return -EINVAL; 2728 } 2729 2730 mutex_lock(&adev->srbm_mutex); 2731 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2732 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2733 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2734 (pfp_hdr->ucode_start_addr_hi << 30) | 2735 (pfp_hdr->ucode_start_addr_lo >> 2)); 2736 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2737 pfp_hdr->ucode_start_addr_hi >> 2); 2738 2739 /* 2740 * Program CP_ME_CNTL to reset given PIPE to take 2741 * effect of CP_PFP_PRGRM_CNTR_START. 2742 */ 2743 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2744 if (pipe_id == 0) 2745 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2746 PFP_PIPE0_RESET, 1); 2747 else 2748 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2749 PFP_PIPE1_RESET, 1); 2750 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2751 2752 /* Clear pfp pipe0 reset bit. */ 2753 if (pipe_id == 0) 2754 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2755 PFP_PIPE0_RESET, 0); 2756 else 2757 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2758 PFP_PIPE1_RESET, 0); 2759 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2760 2761 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2762 lower_32_bits(addr2)); 2763 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2764 upper_32_bits(addr2)); 2765 } 2766 soc21_grbm_select(adev, 0, 0, 0, 0); 2767 mutex_unlock(&adev->srbm_mutex); 2768 2769 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2770 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2771 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2772 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2773 2774 /* Invalidate the data caches */ 2775 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2776 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2777 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2778 2779 for (i = 0; i < usec_timeout; i++) { 2780 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2781 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2782 INVALIDATE_DCACHE_COMPLETE)) 2783 break; 2784 udelay(1); 2785 } 2786 2787 if (i >= usec_timeout) { 2788 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2789 return -EINVAL; 2790 } 2791 2792 return 0; 2793 } 2794 2795 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2796 { 2797 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2798 uint32_t tmp; 2799 unsigned i, pipe_id; 2800 const struct gfx_firmware_header_v2_0 *me_hdr; 2801 2802 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2803 adev->gfx.me_fw->data; 2804 2805 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2806 lower_32_bits(addr)); 2807 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2808 upper_32_bits(addr)); 2809 2810 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2811 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2812 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2813 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2814 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2815 2816 /* 2817 * Programming any of the CP_ME_IC_BASE registers 2818 * forces invalidation of the ME L1 I$. Wait for the 2819 * invalidation complete 2820 */ 2821 for (i = 0; i < usec_timeout; i++) { 2822 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2823 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2824 INVALIDATE_CACHE_COMPLETE)) 2825 break; 2826 udelay(1); 2827 } 2828 2829 if (i >= usec_timeout) { 2830 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2831 return -EINVAL; 2832 } 2833 2834 /* Prime the instruction caches */ 2835 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2836 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2837 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2838 2839 /* Waiting for instruction cache primed*/ 2840 for (i = 0; i < usec_timeout; i++) { 2841 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2842 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2843 ICACHE_PRIMED)) 2844 break; 2845 udelay(1); 2846 } 2847 2848 if (i >= usec_timeout) { 2849 dev_err(adev->dev, "failed to prime instruction cache\n"); 2850 return -EINVAL; 2851 } 2852 2853 mutex_lock(&adev->srbm_mutex); 2854 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2855 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2856 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2857 (me_hdr->ucode_start_addr_hi << 30) | 2858 (me_hdr->ucode_start_addr_lo >> 2) ); 2859 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2860 me_hdr->ucode_start_addr_hi>>2); 2861 2862 /* 2863 * Program CP_ME_CNTL to reset given PIPE to take 2864 * effect of CP_PFP_PRGRM_CNTR_START. 2865 */ 2866 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2867 if (pipe_id == 0) 2868 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2869 ME_PIPE0_RESET, 1); 2870 else 2871 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2872 ME_PIPE1_RESET, 1); 2873 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2874 2875 /* Clear pfp pipe0 reset bit. */ 2876 if (pipe_id == 0) 2877 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2878 ME_PIPE0_RESET, 0); 2879 else 2880 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2881 ME_PIPE1_RESET, 0); 2882 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2883 2884 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2885 lower_32_bits(addr2)); 2886 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2887 upper_32_bits(addr2)); 2888 } 2889 soc21_grbm_select(adev, 0, 0, 0, 0); 2890 mutex_unlock(&adev->srbm_mutex); 2891 2892 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2893 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2894 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2895 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2896 2897 /* Invalidate the data caches */ 2898 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2899 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2900 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2901 2902 for (i = 0; i < usec_timeout; i++) { 2903 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2904 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2905 INVALIDATE_DCACHE_COMPLETE)) 2906 break; 2907 udelay(1); 2908 } 2909 2910 if (i >= usec_timeout) { 2911 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2912 return -EINVAL; 2913 } 2914 2915 return 0; 2916 } 2917 2918 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2919 { 2920 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2921 uint32_t tmp; 2922 unsigned i; 2923 const struct gfx_firmware_header_v2_0 *mec_hdr; 2924 2925 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2926 adev->gfx.mec_fw->data; 2927 2928 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2929 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2930 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2931 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2932 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2933 2934 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2935 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2936 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2937 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2938 2939 mutex_lock(&adev->srbm_mutex); 2940 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2941 soc21_grbm_select(adev, 1, i, 0, 0); 2942 2943 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2944 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2945 upper_32_bits(addr2)); 2946 2947 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2948 mec_hdr->ucode_start_addr_lo >> 2 | 2949 mec_hdr->ucode_start_addr_hi << 30); 2950 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2951 mec_hdr->ucode_start_addr_hi >> 2); 2952 2953 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2954 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2955 upper_32_bits(addr)); 2956 } 2957 mutex_unlock(&adev->srbm_mutex); 2958 soc21_grbm_select(adev, 0, 0, 0, 0); 2959 2960 /* Trigger an invalidation of the L1 instruction caches */ 2961 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2962 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2963 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2964 2965 /* Wait for invalidation complete */ 2966 for (i = 0; i < usec_timeout; i++) { 2967 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2968 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2969 INVALIDATE_DCACHE_COMPLETE)) 2970 break; 2971 udelay(1); 2972 } 2973 2974 if (i >= usec_timeout) { 2975 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2976 return -EINVAL; 2977 } 2978 2979 /* Trigger an invalidation of the L1 instruction caches */ 2980 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2981 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2982 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2983 2984 /* Wait for invalidation complete */ 2985 for (i = 0; i < usec_timeout; i++) { 2986 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2987 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2988 INVALIDATE_CACHE_COMPLETE)) 2989 break; 2990 udelay(1); 2991 } 2992 2993 if (i >= usec_timeout) { 2994 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2995 return -EINVAL; 2996 } 2997 2998 return 0; 2999 } 3000 3001 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 3002 { 3003 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3004 const struct gfx_firmware_header_v2_0 *me_hdr; 3005 const struct gfx_firmware_header_v2_0 *mec_hdr; 3006 uint32_t pipe_id, tmp; 3007 3008 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 3009 adev->gfx.mec_fw->data; 3010 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3011 adev->gfx.me_fw->data; 3012 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3013 adev->gfx.pfp_fw->data; 3014 3015 /* config pfp program start addr */ 3016 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 3017 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3018 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3019 (pfp_hdr->ucode_start_addr_hi << 30) | 3020 (pfp_hdr->ucode_start_addr_lo >> 2)); 3021 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3022 pfp_hdr->ucode_start_addr_hi >> 2); 3023 } 3024 soc21_grbm_select(adev, 0, 0, 0, 0); 3025 3026 /* reset pfp pipe */ 3027 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3028 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 3029 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 3030 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3031 3032 /* clear pfp pipe reset */ 3033 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 3034 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 3035 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3036 3037 /* config me program start addr */ 3038 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 3039 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3040 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3041 (me_hdr->ucode_start_addr_hi << 30) | 3042 (me_hdr->ucode_start_addr_lo >> 2) ); 3043 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3044 me_hdr->ucode_start_addr_hi>>2); 3045 } 3046 soc21_grbm_select(adev, 0, 0, 0, 0); 3047 3048 /* reset me pipe */ 3049 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3050 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 3051 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 3052 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3053 3054 /* clear me pipe reset */ 3055 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 3056 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 3057 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3058 3059 /* config mec program start addr */ 3060 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 3061 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 3062 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3063 mec_hdr->ucode_start_addr_lo >> 2 | 3064 mec_hdr->ucode_start_addr_hi << 30); 3065 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3066 mec_hdr->ucode_start_addr_hi >> 2); 3067 } 3068 soc21_grbm_select(adev, 0, 0, 0, 0); 3069 3070 /* reset mec pipe */ 3071 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3072 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 3073 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 3074 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 3075 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 3076 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3077 3078 /* clear mec pipe reset */ 3079 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 3080 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 3081 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 3082 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 3083 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3084 } 3085 3086 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 3087 { 3088 uint32_t cp_status; 3089 uint32_t bootload_status; 3090 int i, r; 3091 uint64_t addr, addr2; 3092 3093 for (i = 0; i < adev->usec_timeout; i++) { 3094 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 3095 3096 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 3097 IP_VERSION(11, 0, 1) || 3098 amdgpu_ip_version(adev, GC_HWIP, 0) == 3099 IP_VERSION(11, 0, 4) || 3100 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 3101 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 3102 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 3103 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) || 3104 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4) || 3105 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 6) || 3106 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 0) || 3107 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 1)) 3108 bootload_status = RREG32_SOC15(GC, 0, 3109 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 3110 else 3111 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 3112 3113 if ((cp_status == 0) && 3114 (REG_GET_FIELD(bootload_status, 3115 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 3116 break; 3117 } 3118 udelay(1); 3119 } 3120 3121 if (i >= adev->usec_timeout) { 3122 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 3123 return -ETIMEDOUT; 3124 } 3125 3126 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3127 if (adev->gfx.rs64_enable) { 3128 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3129 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 3130 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3131 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 3132 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 3133 if (r) 3134 return r; 3135 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3136 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 3137 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3138 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 3139 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 3140 if (r) 3141 return r; 3142 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3143 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 3144 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3145 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 3146 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 3147 if (r) 3148 return r; 3149 } else { 3150 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3151 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 3152 r = gfx_v11_0_config_me_cache(adev, addr); 3153 if (r) 3154 return r; 3155 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3156 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 3157 r = gfx_v11_0_config_pfp_cache(adev, addr); 3158 if (r) 3159 return r; 3160 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3161 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 3162 r = gfx_v11_0_config_mec_cache(adev, addr); 3163 if (r) 3164 return r; 3165 } 3166 } 3167 3168 return 0; 3169 } 3170 3171 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3172 { 3173 int i; 3174 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3175 3176 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3177 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3178 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3179 3180 for (i = 0; i < adev->usec_timeout; i++) { 3181 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3182 break; 3183 udelay(1); 3184 } 3185 3186 if (i >= adev->usec_timeout) 3187 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3193 { 3194 int r; 3195 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3196 const __le32 *fw_data; 3197 unsigned i, fw_size; 3198 3199 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3200 adev->gfx.pfp_fw->data; 3201 3202 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3203 3204 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3205 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3206 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3207 3208 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3209 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3210 &adev->gfx.pfp.pfp_fw_obj, 3211 &adev->gfx.pfp.pfp_fw_gpu_addr, 3212 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3213 if (r) { 3214 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3215 gfx_v11_0_pfp_fini(adev); 3216 return r; 3217 } 3218 3219 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3220 3221 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3222 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3223 3224 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3225 3226 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3227 3228 for (i = 0; i < pfp_hdr->jt_size; i++) 3229 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3230 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3231 3232 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3233 3234 return 0; 3235 } 3236 3237 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3238 { 3239 int r; 3240 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3241 const __le32 *fw_ucode, *fw_data; 3242 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3243 uint32_t tmp; 3244 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3245 3246 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3247 adev->gfx.pfp_fw->data; 3248 3249 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3250 3251 /* instruction */ 3252 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3253 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3254 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3255 /* data */ 3256 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3257 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3258 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3259 3260 /* 64kb align */ 3261 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3262 64 * 1024, 3263 AMDGPU_GEM_DOMAIN_VRAM | 3264 AMDGPU_GEM_DOMAIN_GTT, 3265 &adev->gfx.pfp.pfp_fw_obj, 3266 &adev->gfx.pfp.pfp_fw_gpu_addr, 3267 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3268 if (r) { 3269 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3270 gfx_v11_0_pfp_fini(adev); 3271 return r; 3272 } 3273 3274 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3275 64 * 1024, 3276 AMDGPU_GEM_DOMAIN_VRAM | 3277 AMDGPU_GEM_DOMAIN_GTT, 3278 &adev->gfx.pfp.pfp_fw_data_obj, 3279 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3280 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3281 if (r) { 3282 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3283 gfx_v11_0_pfp_fini(adev); 3284 return r; 3285 } 3286 3287 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3288 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3289 3290 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3291 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3292 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3293 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3294 3295 if (amdgpu_emu_mode == 1) 3296 amdgpu_device_flush_hdp(adev, NULL); 3297 3298 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3299 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3300 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3301 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3302 3303 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3304 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3305 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3306 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3307 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3308 3309 /* 3310 * Programming any of the CP_PFP_IC_BASE registers 3311 * forces invalidation of the ME L1 I$. Wait for the 3312 * invalidation complete 3313 */ 3314 for (i = 0; i < usec_timeout; i++) { 3315 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3316 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3317 INVALIDATE_CACHE_COMPLETE)) 3318 break; 3319 udelay(1); 3320 } 3321 3322 if (i >= usec_timeout) { 3323 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3324 return -EINVAL; 3325 } 3326 3327 /* Prime the L1 instruction caches */ 3328 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3329 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3330 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3331 /* Waiting for cache primed*/ 3332 for (i = 0; i < usec_timeout; i++) { 3333 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3334 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3335 ICACHE_PRIMED)) 3336 break; 3337 udelay(1); 3338 } 3339 3340 if (i >= usec_timeout) { 3341 dev_err(adev->dev, "failed to prime instruction cache\n"); 3342 return -EINVAL; 3343 } 3344 3345 mutex_lock(&adev->srbm_mutex); 3346 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3347 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3348 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3349 (pfp_hdr->ucode_start_addr_hi << 30) | 3350 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3351 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3352 pfp_hdr->ucode_start_addr_hi>>2); 3353 3354 /* 3355 * Program CP_ME_CNTL to reset given PIPE to take 3356 * effect of CP_PFP_PRGRM_CNTR_START. 3357 */ 3358 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3359 if (pipe_id == 0) 3360 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3361 PFP_PIPE0_RESET, 1); 3362 else 3363 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3364 PFP_PIPE1_RESET, 1); 3365 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3366 3367 /* Clear pfp pipe0 reset bit. */ 3368 if (pipe_id == 0) 3369 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3370 PFP_PIPE0_RESET, 0); 3371 else 3372 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3373 PFP_PIPE1_RESET, 0); 3374 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3375 3376 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3377 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3378 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3379 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3380 } 3381 soc21_grbm_select(adev, 0, 0, 0, 0); 3382 mutex_unlock(&adev->srbm_mutex); 3383 3384 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3385 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3386 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3387 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3388 3389 /* Invalidate the data caches */ 3390 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3391 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3392 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3393 3394 for (i = 0; i < usec_timeout; i++) { 3395 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3396 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3397 INVALIDATE_DCACHE_COMPLETE)) 3398 break; 3399 udelay(1); 3400 } 3401 3402 if (i >= usec_timeout) { 3403 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3404 return -EINVAL; 3405 } 3406 3407 return 0; 3408 } 3409 3410 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3411 { 3412 int r; 3413 const struct gfx_firmware_header_v1_0 *me_hdr; 3414 const __le32 *fw_data; 3415 unsigned i, fw_size; 3416 3417 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3418 adev->gfx.me_fw->data; 3419 3420 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3421 3422 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3423 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3424 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3425 3426 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3427 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3428 &adev->gfx.me.me_fw_obj, 3429 &adev->gfx.me.me_fw_gpu_addr, 3430 (void **)&adev->gfx.me.me_fw_ptr); 3431 if (r) { 3432 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3433 gfx_v11_0_me_fini(adev); 3434 return r; 3435 } 3436 3437 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3438 3439 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3440 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3441 3442 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3443 3444 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3445 3446 for (i = 0; i < me_hdr->jt_size; i++) 3447 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3448 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3449 3450 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3451 3452 return 0; 3453 } 3454 3455 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3456 { 3457 int r; 3458 const struct gfx_firmware_header_v2_0 *me_hdr; 3459 const __le32 *fw_ucode, *fw_data; 3460 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3461 uint32_t tmp; 3462 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3463 3464 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3465 adev->gfx.me_fw->data; 3466 3467 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3468 3469 /* instruction */ 3470 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3471 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3472 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3473 /* data */ 3474 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3475 le32_to_cpu(me_hdr->data_offset_bytes)); 3476 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3477 3478 /* 64kb align*/ 3479 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3480 64 * 1024, 3481 AMDGPU_GEM_DOMAIN_VRAM | 3482 AMDGPU_GEM_DOMAIN_GTT, 3483 &adev->gfx.me.me_fw_obj, 3484 &adev->gfx.me.me_fw_gpu_addr, 3485 (void **)&adev->gfx.me.me_fw_ptr); 3486 if (r) { 3487 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3488 gfx_v11_0_me_fini(adev); 3489 return r; 3490 } 3491 3492 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3493 64 * 1024, 3494 AMDGPU_GEM_DOMAIN_VRAM | 3495 AMDGPU_GEM_DOMAIN_GTT, 3496 &adev->gfx.me.me_fw_data_obj, 3497 &adev->gfx.me.me_fw_data_gpu_addr, 3498 (void **)&adev->gfx.me.me_fw_data_ptr); 3499 if (r) { 3500 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3501 gfx_v11_0_pfp_fini(adev); 3502 return r; 3503 } 3504 3505 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3506 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3507 3508 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3509 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3510 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3511 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3512 3513 if (amdgpu_emu_mode == 1) 3514 amdgpu_device_flush_hdp(adev, NULL); 3515 3516 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3517 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3518 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3519 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3520 3521 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3522 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3523 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3524 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3525 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3526 3527 /* 3528 * Programming any of the CP_ME_IC_BASE registers 3529 * forces invalidation of the ME L1 I$. Wait for the 3530 * invalidation complete 3531 */ 3532 for (i = 0; i < usec_timeout; i++) { 3533 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3534 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3535 INVALIDATE_CACHE_COMPLETE)) 3536 break; 3537 udelay(1); 3538 } 3539 3540 if (i >= usec_timeout) { 3541 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3542 return -EINVAL; 3543 } 3544 3545 /* Prime the instruction caches */ 3546 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3547 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3548 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3549 3550 /* Waiting for instruction cache primed*/ 3551 for (i = 0; i < usec_timeout; i++) { 3552 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3553 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3554 ICACHE_PRIMED)) 3555 break; 3556 udelay(1); 3557 } 3558 3559 if (i >= usec_timeout) { 3560 dev_err(adev->dev, "failed to prime instruction cache\n"); 3561 return -EINVAL; 3562 } 3563 3564 mutex_lock(&adev->srbm_mutex); 3565 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3566 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3567 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3568 (me_hdr->ucode_start_addr_hi << 30) | 3569 (me_hdr->ucode_start_addr_lo >> 2) ); 3570 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3571 me_hdr->ucode_start_addr_hi>>2); 3572 3573 /* 3574 * Program CP_ME_CNTL to reset given PIPE to take 3575 * effect of CP_PFP_PRGRM_CNTR_START. 3576 */ 3577 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3578 if (pipe_id == 0) 3579 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3580 ME_PIPE0_RESET, 1); 3581 else 3582 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3583 ME_PIPE1_RESET, 1); 3584 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3585 3586 /* Clear pfp pipe0 reset bit. */ 3587 if (pipe_id == 0) 3588 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3589 ME_PIPE0_RESET, 0); 3590 else 3591 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3592 ME_PIPE1_RESET, 0); 3593 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3594 3595 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3596 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3597 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3598 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3599 } 3600 soc21_grbm_select(adev, 0, 0, 0, 0); 3601 mutex_unlock(&adev->srbm_mutex); 3602 3603 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3604 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3605 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3607 3608 /* Invalidate the data caches */ 3609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3611 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3612 3613 for (i = 0; i < usec_timeout; i++) { 3614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3615 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3616 INVALIDATE_DCACHE_COMPLETE)) 3617 break; 3618 udelay(1); 3619 } 3620 3621 if (i >= usec_timeout) { 3622 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3623 return -EINVAL; 3624 } 3625 3626 return 0; 3627 } 3628 3629 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3630 { 3631 int r; 3632 3633 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3634 return -EINVAL; 3635 3636 gfx_v11_0_cp_gfx_enable(adev, false); 3637 3638 if (adev->gfx.rs64_enable) 3639 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3640 else 3641 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3642 if (r) { 3643 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3644 return r; 3645 } 3646 3647 if (adev->gfx.rs64_enable) 3648 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3649 else 3650 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3651 if (r) { 3652 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3653 return r; 3654 } 3655 3656 return 0; 3657 } 3658 3659 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3660 { 3661 struct amdgpu_ring *ring; 3662 const struct cs_section_def *sect = NULL; 3663 const struct cs_extent_def *ext = NULL; 3664 int r, i; 3665 int ctx_reg_offset; 3666 3667 /* init the CP */ 3668 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3669 adev->gfx.config.max_hw_contexts - 1); 3670 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3671 3672 if (!amdgpu_async_gfx_ring) 3673 gfx_v11_0_cp_gfx_enable(adev, true); 3674 3675 ring = &adev->gfx.gfx_ring[0]; 3676 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3677 if (r) { 3678 drm_err(&adev->ddev, "cp failed to lock ring (%d).\n", r); 3679 return r; 3680 } 3681 3682 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3683 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3684 3685 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3686 amdgpu_ring_write(ring, 0x80000000); 3687 amdgpu_ring_write(ring, 0x80000000); 3688 3689 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3690 for (ext = sect->section; ext->extent != NULL; ++ext) { 3691 if (sect->id == SECT_CONTEXT) { 3692 amdgpu_ring_write(ring, 3693 PACKET3(PACKET3_SET_CONTEXT_REG, 3694 ext->reg_count)); 3695 amdgpu_ring_write(ring, ext->reg_index - 3696 PACKET3_SET_CONTEXT_REG_START); 3697 for (i = 0; i < ext->reg_count; i++) 3698 amdgpu_ring_write(ring, ext->extent[i]); 3699 } 3700 } 3701 } 3702 3703 ctx_reg_offset = 3704 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3706 amdgpu_ring_write(ring, ctx_reg_offset); 3707 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3708 3709 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3710 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3711 3712 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3713 amdgpu_ring_write(ring, 0); 3714 3715 amdgpu_ring_commit(ring); 3716 3717 /* submit cs packet to copy state 0 to next available state */ 3718 if (adev->gfx.num_gfx_rings > 1) { 3719 /* maximum supported gfx ring is 2 */ 3720 ring = &adev->gfx.gfx_ring[1]; 3721 r = amdgpu_ring_alloc(ring, 2); 3722 if (r) { 3723 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 3724 return r; 3725 } 3726 3727 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3728 amdgpu_ring_write(ring, 0); 3729 3730 amdgpu_ring_commit(ring); 3731 } 3732 return 0; 3733 } 3734 3735 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3736 CP_PIPE_ID pipe) 3737 { 3738 u32 tmp; 3739 3740 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3741 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3742 3743 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3744 } 3745 3746 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3747 struct amdgpu_ring *ring) 3748 { 3749 u32 tmp; 3750 3751 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3752 if (ring->use_doorbell) { 3753 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3754 DOORBELL_OFFSET, ring->doorbell_index); 3755 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3756 DOORBELL_EN, 1); 3757 } else { 3758 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3759 DOORBELL_EN, 0); 3760 } 3761 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3762 3763 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3764 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3765 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3766 3767 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3768 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3769 } 3770 3771 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3772 { 3773 struct amdgpu_ring *ring; 3774 u32 tmp; 3775 u32 rb_bufsz; 3776 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3777 3778 /* Set the write pointer delay */ 3779 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3780 3781 /* set the RB to use vmid 0 */ 3782 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3783 3784 /* Init gfx ring 0 for pipe 0 */ 3785 mutex_lock(&adev->srbm_mutex); 3786 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3787 3788 /* Set ring buffer size */ 3789 ring = &adev->gfx.gfx_ring[0]; 3790 rb_bufsz = order_base_2(ring->ring_size / 8); 3791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3793 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3794 3795 /* Initialize the ring buffer's write pointers */ 3796 ring->wptr = 0; 3797 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3798 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3799 3800 /* set the wb address whether it's enabled or not */ 3801 rptr_addr = ring->rptr_gpu_addr; 3802 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3803 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3804 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3805 3806 wptr_gpu_addr = ring->wptr_gpu_addr; 3807 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3808 lower_32_bits(wptr_gpu_addr)); 3809 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3810 upper_32_bits(wptr_gpu_addr)); 3811 3812 mdelay(1); 3813 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3814 3815 rb_addr = ring->gpu_addr >> 8; 3816 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3817 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3818 3819 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3820 3821 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3822 mutex_unlock(&adev->srbm_mutex); 3823 3824 /* Init gfx ring 1 for pipe 1 */ 3825 if (adev->gfx.num_gfx_rings > 1) { 3826 mutex_lock(&adev->srbm_mutex); 3827 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3828 /* maximum supported gfx ring is 2 */ 3829 ring = &adev->gfx.gfx_ring[1]; 3830 rb_bufsz = order_base_2(ring->ring_size / 8); 3831 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3832 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3833 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3834 /* Initialize the ring buffer's write pointers */ 3835 ring->wptr = 0; 3836 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3837 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3838 /* Set the wb address whether it's enabled or not */ 3839 rptr_addr = ring->rptr_gpu_addr; 3840 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3841 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3842 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3843 wptr_gpu_addr = ring->wptr_gpu_addr; 3844 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3845 lower_32_bits(wptr_gpu_addr)); 3846 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3847 upper_32_bits(wptr_gpu_addr)); 3848 3849 mdelay(1); 3850 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3851 3852 rb_addr = ring->gpu_addr >> 8; 3853 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3854 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3855 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3856 3857 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3858 mutex_unlock(&adev->srbm_mutex); 3859 } 3860 /* Switch to pipe 0 */ 3861 mutex_lock(&adev->srbm_mutex); 3862 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3863 mutex_unlock(&adev->srbm_mutex); 3864 3865 /* start the ring */ 3866 gfx_v11_0_cp_gfx_start(adev); 3867 3868 return 0; 3869 } 3870 3871 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3872 { 3873 u32 data; 3874 3875 if (adev->gfx.rs64_enable) { 3876 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3877 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3878 enable ? 0 : 1); 3879 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3880 enable ? 0 : 1); 3881 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3882 enable ? 0 : 1); 3883 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3884 enable ? 0 : 1); 3885 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3886 enable ? 0 : 1); 3887 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3888 enable ? 1 : 0); 3889 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3890 enable ? 1 : 0); 3891 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3892 enable ? 1 : 0); 3893 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3894 enable ? 1 : 0); 3895 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3896 enable ? 0 : 1); 3897 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3898 } else { 3899 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3900 3901 if (enable) { 3902 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3903 if (!adev->enable_mes_kiq) 3904 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3905 MEC_ME2_HALT, 0); 3906 } else { 3907 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3908 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3909 } 3910 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3911 } 3912 3913 udelay(50); 3914 } 3915 3916 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3917 { 3918 const struct gfx_firmware_header_v1_0 *mec_hdr; 3919 const __le32 *fw_data; 3920 unsigned i, fw_size; 3921 u32 *fw = NULL; 3922 int r; 3923 3924 if (!adev->gfx.mec_fw) 3925 return -EINVAL; 3926 3927 gfx_v11_0_cp_compute_enable(adev, false); 3928 3929 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3930 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3931 3932 fw_data = (const __le32 *) 3933 (adev->gfx.mec_fw->data + 3934 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3935 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3936 3937 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3938 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3939 &adev->gfx.mec.mec_fw_obj, 3940 &adev->gfx.mec.mec_fw_gpu_addr, 3941 (void **)&fw); 3942 if (r) { 3943 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3944 gfx_v11_0_mec_fini(adev); 3945 return r; 3946 } 3947 3948 memcpy(fw, fw_data, fw_size); 3949 3950 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3951 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3952 3953 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3954 3955 /* MEC1 */ 3956 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3957 3958 for (i = 0; i < mec_hdr->jt_size; i++) 3959 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3960 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3961 3962 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3963 3964 return 0; 3965 } 3966 3967 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3968 { 3969 const struct gfx_firmware_header_v2_0 *mec_hdr; 3970 const __le32 *fw_ucode, *fw_data; 3971 u32 tmp, fw_ucode_size, fw_data_size; 3972 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3973 u32 *fw_ucode_ptr, *fw_data_ptr; 3974 int r; 3975 3976 if (!adev->gfx.mec_fw) 3977 return -EINVAL; 3978 3979 gfx_v11_0_cp_compute_enable(adev, false); 3980 3981 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3982 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3983 3984 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3985 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3986 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3987 3988 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3989 le32_to_cpu(mec_hdr->data_offset_bytes)); 3990 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3991 3992 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3993 64 * 1024, 3994 AMDGPU_GEM_DOMAIN_VRAM | 3995 AMDGPU_GEM_DOMAIN_GTT, 3996 &adev->gfx.mec.mec_fw_obj, 3997 &adev->gfx.mec.mec_fw_gpu_addr, 3998 (void **)&fw_ucode_ptr); 3999 if (r) { 4000 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 4001 gfx_v11_0_mec_fini(adev); 4002 return r; 4003 } 4004 4005 r = amdgpu_bo_create_reserved(adev, fw_data_size, 4006 64 * 1024, 4007 AMDGPU_GEM_DOMAIN_VRAM | 4008 AMDGPU_GEM_DOMAIN_GTT, 4009 &adev->gfx.mec.mec_fw_data_obj, 4010 &adev->gfx.mec.mec_fw_data_gpu_addr, 4011 (void **)&fw_data_ptr); 4012 if (r) { 4013 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 4014 gfx_v11_0_mec_fini(adev); 4015 return r; 4016 } 4017 4018 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 4019 memcpy(fw_data_ptr, fw_data, fw_data_size); 4020 4021 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4022 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 4023 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4024 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 4025 4026 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 4027 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 4028 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 4029 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 4030 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 4031 4032 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 4033 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 4034 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 4035 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 4036 4037 mutex_lock(&adev->srbm_mutex); 4038 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 4039 soc21_grbm_select(adev, 1, i, 0, 0); 4040 4041 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 4042 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 4043 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 4044 4045 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 4046 mec_hdr->ucode_start_addr_lo >> 2 | 4047 mec_hdr->ucode_start_addr_hi << 30); 4048 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 4049 mec_hdr->ucode_start_addr_hi >> 2); 4050 4051 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 4052 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 4053 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 4054 } 4055 mutex_unlock(&adev->srbm_mutex); 4056 soc21_grbm_select(adev, 0, 0, 0, 0); 4057 4058 /* Trigger an invalidation of the L1 instruction caches */ 4059 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 4060 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 4061 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 4062 4063 /* Wait for invalidation complete */ 4064 for (i = 0; i < usec_timeout; i++) { 4065 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 4066 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 4067 INVALIDATE_DCACHE_COMPLETE)) 4068 break; 4069 udelay(1); 4070 } 4071 4072 if (i >= usec_timeout) { 4073 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4074 return -EINVAL; 4075 } 4076 4077 /* Trigger an invalidation of the L1 instruction caches */ 4078 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4079 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 4080 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 4081 4082 /* Wait for invalidation complete */ 4083 for (i = 0; i < usec_timeout; i++) { 4084 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4085 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 4086 INVALIDATE_CACHE_COMPLETE)) 4087 break; 4088 udelay(1); 4089 } 4090 4091 if (i >= usec_timeout) { 4092 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4093 return -EINVAL; 4094 } 4095 4096 return 0; 4097 } 4098 4099 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 4100 { 4101 uint32_t tmp; 4102 struct amdgpu_device *adev = ring->adev; 4103 4104 /* tell RLC which is KIQ queue */ 4105 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4106 tmp &= 0xffffff00; 4107 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4108 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 4109 } 4110 4111 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 4112 { 4113 /* set graphics engine doorbell range */ 4114 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 4115 (adev->doorbell_index.gfx_ring0 * 2) << 2); 4116 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 4117 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 4118 4119 /* set compute engine doorbell range */ 4120 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4121 (adev->doorbell_index.kiq * 2) << 2); 4122 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4123 (adev->doorbell_index.userqueue_end * 2) << 2); 4124 } 4125 4126 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 4127 struct v11_gfx_mqd *mqd, 4128 struct amdgpu_mqd_prop *prop) 4129 { 4130 bool priority = 0; 4131 u32 tmp; 4132 4133 /* set up default queue priority level 4134 * 0x0 = low priority, 0x1 = high priority 4135 */ 4136 if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) 4137 priority = 1; 4138 4139 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 4140 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 4141 mqd->cp_gfx_hqd_queue_priority = tmp; 4142 } 4143 4144 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 4145 struct amdgpu_mqd_prop *prop) 4146 { 4147 struct v11_gfx_mqd *mqd = m; 4148 uint64_t hqd_gpu_addr, wb_gpu_addr; 4149 uint32_t tmp; 4150 uint32_t rb_bufsz; 4151 4152 /* set up gfx hqd wptr */ 4153 mqd->cp_gfx_hqd_wptr = 0; 4154 mqd->cp_gfx_hqd_wptr_hi = 0; 4155 4156 /* set the pointer to the MQD */ 4157 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 4158 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4159 4160 /* set up mqd control */ 4161 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4162 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4163 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4164 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4165 mqd->cp_gfx_mqd_control = tmp; 4166 4167 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4168 tmp = regCP_GFX_HQD_VMID_DEFAULT; 4169 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4170 mqd->cp_gfx_hqd_vmid = 0; 4171 4172 /* set up gfx queue priority */ 4173 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4174 4175 /* set up time quantum */ 4176 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4177 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4178 mqd->cp_gfx_hqd_quantum = tmp; 4179 4180 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4181 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4182 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4183 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4184 4185 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4186 wb_gpu_addr = prop->rptr_gpu_addr; 4187 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4188 mqd->cp_gfx_hqd_rptr_addr_hi = 4189 upper_32_bits(wb_gpu_addr) & 0xffff; 4190 4191 /* set up rb_wptr_poll addr */ 4192 wb_gpu_addr = prop->wptr_gpu_addr; 4193 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4194 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4195 4196 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4197 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4198 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4199 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4200 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4201 #ifdef __BIG_ENDIAN 4202 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4203 #endif 4204 if (prop->tmz_queue) 4205 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 4206 if (!prop->kernel_queue) 4207 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 4208 mqd->cp_gfx_hqd_cntl = tmp; 4209 4210 /* set up cp_doorbell_control */ 4211 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4212 if (prop->use_doorbell) { 4213 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4214 DOORBELL_OFFSET, prop->doorbell_index); 4215 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4216 DOORBELL_EN, 1); 4217 } else 4218 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4219 DOORBELL_EN, 0); 4220 mqd->cp_rb_doorbell_control = tmp; 4221 4222 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4223 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4224 4225 /* active the queue */ 4226 mqd->cp_gfx_hqd_active = 1; 4227 4228 /* set gfx UQ items */ 4229 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 4230 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 4231 mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr); 4232 mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr); 4233 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 4234 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 4235 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4236 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4237 4238 return 0; 4239 } 4240 4241 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring) 4242 { 4243 struct amdgpu_device *adev = ring->adev; 4244 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4245 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4246 4247 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4248 memset((void *)mqd, 0, sizeof(*mqd)); 4249 mutex_lock(&adev->srbm_mutex); 4250 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4251 amdgpu_ring_init_mqd(ring); 4252 soc21_grbm_select(adev, 0, 0, 0, 0); 4253 mutex_unlock(&adev->srbm_mutex); 4254 if (adev->gfx.me.mqd_backup[mqd_idx]) 4255 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4256 } else { 4257 /* restore mqd with the backup copy */ 4258 if (adev->gfx.me.mqd_backup[mqd_idx]) 4259 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4260 /* reset the ring */ 4261 ring->wptr = 0; 4262 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4263 amdgpu_ring_clear_ring(ring); 4264 } 4265 4266 return 0; 4267 } 4268 4269 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4270 { 4271 int r, i; 4272 4273 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4274 r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i]); 4275 if (r) 4276 return r; 4277 } 4278 4279 r = amdgpu_gfx_enable_kgq(adev, 0); 4280 if (r) 4281 return r; 4282 4283 return gfx_v11_0_cp_gfx_start(adev); 4284 } 4285 4286 static void gfx_v11_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 4287 struct v11_compute_mqd *mqd, 4288 struct amdgpu_mqd_prop *prop) 4289 { 4290 uint32_t se_mask[8] = {0}; 4291 uint32_t wa_mask; 4292 bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 4293 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 4294 4295 if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 4296 return; 4297 4298 if (has_wa_flag) { 4299 wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 4300 0xffff : 0xffffffff; 4301 mqd->compute_static_thread_mgmt_se0 = wa_mask; 4302 mqd->compute_static_thread_mgmt_se1 = wa_mask; 4303 mqd->compute_static_thread_mgmt_se2 = wa_mask; 4304 mqd->compute_static_thread_mgmt_se3 = wa_mask; 4305 return; 4306 } 4307 4308 amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 4309 prop->cu_mask_count, se_mask); 4310 4311 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 4312 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 4313 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 4314 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 4315 } 4316 4317 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4318 struct amdgpu_mqd_prop *prop) 4319 { 4320 struct v11_compute_mqd *mqd = m; 4321 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4322 uint32_t tmp; 4323 4324 mqd->header = 0xC0310800; 4325 mqd->compute_pipelinestat_enable = 0x00000001; 4326 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4327 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4328 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4329 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4330 mqd->compute_misc_reserved = 0x00000007; 4331 4332 eop_base_addr = prop->eop_gpu_addr >> 8; 4333 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4334 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4335 4336 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4337 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4338 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4339 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4340 4341 mqd->cp_hqd_eop_control = tmp; 4342 4343 /* enable doorbell? */ 4344 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4345 4346 if (prop->use_doorbell) { 4347 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4348 DOORBELL_OFFSET, prop->doorbell_index); 4349 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4350 DOORBELL_EN, 1); 4351 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4352 DOORBELL_SOURCE, 0); 4353 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4354 DOORBELL_HIT, 0); 4355 } else { 4356 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4357 DOORBELL_EN, 0); 4358 } 4359 4360 mqd->cp_hqd_pq_doorbell_control = tmp; 4361 4362 /* disable the queue if it's active */ 4363 mqd->cp_hqd_dequeue_request = 0; 4364 mqd->cp_hqd_pq_rptr = 0; 4365 mqd->cp_hqd_pq_wptr_lo = 0; 4366 mqd->cp_hqd_pq_wptr_hi = 0; 4367 4368 /* set the pointer to the MQD */ 4369 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4370 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4371 4372 /* set MQD vmid to 0 */ 4373 tmp = regCP_MQD_CONTROL_DEFAULT; 4374 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4375 mqd->cp_mqd_control = tmp; 4376 4377 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4378 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4379 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4380 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4381 4382 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4383 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4384 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4385 (order_base_2(prop->queue_size / 4) - 1)); 4386 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4387 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4388 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4389 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4390 prop->allow_tunneling); 4391 if (prop->kernel_queue) { 4392 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4393 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4394 } 4395 if (prop->tmz_queue) 4396 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 4397 mqd->cp_hqd_pq_control = tmp; 4398 4399 /* set the wb address whether it's enabled or not */ 4400 wb_gpu_addr = prop->rptr_gpu_addr; 4401 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4402 mqd->cp_hqd_pq_rptr_report_addr_hi = 4403 upper_32_bits(wb_gpu_addr) & 0xffff; 4404 4405 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4406 wb_gpu_addr = prop->wptr_gpu_addr; 4407 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4408 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4409 4410 tmp = 0; 4411 /* enable the doorbell if requested */ 4412 if (prop->use_doorbell) { 4413 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4414 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4415 DOORBELL_OFFSET, prop->doorbell_index); 4416 4417 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4418 DOORBELL_EN, 1); 4419 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4420 DOORBELL_SOURCE, 0); 4421 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4422 DOORBELL_HIT, 0); 4423 } 4424 4425 mqd->cp_hqd_pq_doorbell_control = tmp; 4426 4427 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4428 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4429 4430 /* set the vmid for the queue */ 4431 mqd->cp_hqd_vmid = 0; 4432 4433 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4434 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4435 mqd->cp_hqd_persistent_state = tmp; 4436 4437 /* set MIN_IB_AVAIL_SIZE */ 4438 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4439 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4440 mqd->cp_hqd_ib_control = tmp; 4441 4442 /* set static priority for a compute queue/ring */ 4443 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4444 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4445 4446 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 4447 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 4448 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 4449 mqd->cp_hqd_quantum = tmp; 4450 4451 mqd->cp_hqd_active = prop->hqd_active; 4452 4453 /* set UQ fenceaddress */ 4454 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4455 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4456 /* set CU mask */ 4457 gfx_v11_0_compute_mqd_set_cu_mask(adev, mqd, prop); 4458 4459 return 0; 4460 } 4461 4462 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4463 { 4464 struct amdgpu_device *adev = ring->adev; 4465 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4466 int j; 4467 4468 /* inactivate the queue */ 4469 if (amdgpu_sriov_vf(adev)) 4470 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4471 4472 /* disable wptr polling */ 4473 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4474 4475 /* write the EOP addr */ 4476 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4477 mqd->cp_hqd_eop_base_addr_lo); 4478 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4479 mqd->cp_hqd_eop_base_addr_hi); 4480 4481 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4482 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4483 mqd->cp_hqd_eop_control); 4484 4485 /* enable doorbell? */ 4486 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4487 mqd->cp_hqd_pq_doorbell_control); 4488 4489 /* disable the queue if it's active */ 4490 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4491 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4492 for (j = 0; j < adev->usec_timeout; j++) { 4493 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4494 break; 4495 udelay(1); 4496 } 4497 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4498 mqd->cp_hqd_dequeue_request); 4499 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4500 mqd->cp_hqd_pq_rptr); 4501 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4502 mqd->cp_hqd_pq_wptr_lo); 4503 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4504 mqd->cp_hqd_pq_wptr_hi); 4505 } 4506 4507 /* set the pointer to the MQD */ 4508 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4509 mqd->cp_mqd_base_addr_lo); 4510 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4511 mqd->cp_mqd_base_addr_hi); 4512 4513 /* set MQD vmid to 0 */ 4514 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4515 mqd->cp_mqd_control); 4516 4517 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4518 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4519 mqd->cp_hqd_pq_base_lo); 4520 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4521 mqd->cp_hqd_pq_base_hi); 4522 4523 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4524 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4525 mqd->cp_hqd_pq_control); 4526 4527 /* set the wb address whether it's enabled or not */ 4528 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4529 mqd->cp_hqd_pq_rptr_report_addr_lo); 4530 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4531 mqd->cp_hqd_pq_rptr_report_addr_hi); 4532 4533 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4534 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4535 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4536 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4537 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4538 4539 /* enable the doorbell if requested */ 4540 if (ring->use_doorbell) { 4541 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4542 (adev->doorbell_index.kiq * 2) << 2); 4543 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4544 (adev->doorbell_index.userqueue_end * 2) << 2); 4545 } 4546 4547 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4548 mqd->cp_hqd_pq_doorbell_control); 4549 4550 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4551 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4552 mqd->cp_hqd_pq_wptr_lo); 4553 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4554 mqd->cp_hqd_pq_wptr_hi); 4555 4556 /* set the vmid for the queue */ 4557 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4558 4559 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4560 mqd->cp_hqd_persistent_state); 4561 4562 /* activate the queue */ 4563 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4564 mqd->cp_hqd_active); 4565 4566 if (ring->use_doorbell) 4567 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4568 4569 return 0; 4570 } 4571 4572 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4573 { 4574 struct amdgpu_device *adev = ring->adev; 4575 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4576 4577 gfx_v11_0_kiq_setting(ring); 4578 4579 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4580 /* reset MQD to a clean status */ 4581 if (adev->gfx.kiq[0].mqd_backup) 4582 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4583 4584 /* reset ring buffer */ 4585 ring->wptr = 0; 4586 amdgpu_ring_clear_ring(ring); 4587 4588 mutex_lock(&adev->srbm_mutex); 4589 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4590 gfx_v11_0_kiq_init_register(ring); 4591 soc21_grbm_select(adev, 0, 0, 0, 0); 4592 mutex_unlock(&adev->srbm_mutex); 4593 } else { 4594 memset((void *)mqd, 0, sizeof(*mqd)); 4595 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4596 amdgpu_ring_clear_ring(ring); 4597 mutex_lock(&adev->srbm_mutex); 4598 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4599 amdgpu_ring_init_mqd(ring); 4600 gfx_v11_0_kiq_init_register(ring); 4601 soc21_grbm_select(adev, 0, 0, 0, 0); 4602 mutex_unlock(&adev->srbm_mutex); 4603 4604 if (adev->gfx.kiq[0].mqd_backup) 4605 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4606 } 4607 4608 return 0; 4609 } 4610 4611 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4612 { 4613 struct amdgpu_device *adev = ring->adev; 4614 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4615 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4616 4617 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4618 memset((void *)mqd, 0, sizeof(*mqd)); 4619 mutex_lock(&adev->srbm_mutex); 4620 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4621 amdgpu_ring_init_mqd(ring); 4622 soc21_grbm_select(adev, 0, 0, 0, 0); 4623 mutex_unlock(&adev->srbm_mutex); 4624 4625 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4626 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4627 } else { 4628 /* restore MQD to a clean status */ 4629 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4630 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4631 /* reset ring buffer */ 4632 ring->wptr = 0; 4633 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4634 amdgpu_ring_clear_ring(ring); 4635 } 4636 4637 return 0; 4638 } 4639 4640 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4641 { 4642 gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 4643 return 0; 4644 } 4645 4646 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4647 { 4648 int i, r; 4649 4650 if (!amdgpu_async_gfx_ring) 4651 gfx_v11_0_cp_compute_enable(adev, true); 4652 4653 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4654 r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i]); 4655 if (r) 4656 return r; 4657 } 4658 4659 return amdgpu_gfx_enable_kcq(adev, 0); 4660 } 4661 4662 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4663 { 4664 int r, i; 4665 struct amdgpu_ring *ring; 4666 4667 if (!(adev->flags & AMD_IS_APU)) 4668 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4669 4670 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4671 /* legacy firmware loading */ 4672 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4673 if (r) 4674 return r; 4675 4676 if (adev->gfx.rs64_enable) 4677 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4678 else 4679 r = gfx_v11_0_cp_compute_load_microcode(adev); 4680 if (r) 4681 return r; 4682 } 4683 4684 gfx_v11_0_cp_set_doorbell_range(adev); 4685 4686 if (amdgpu_async_gfx_ring) { 4687 gfx_v11_0_cp_compute_enable(adev, true); 4688 gfx_v11_0_cp_gfx_enable(adev, true); 4689 } 4690 4691 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4692 r = amdgpu_mes_kiq_hw_init(adev, 0); 4693 else 4694 r = gfx_v11_0_kiq_resume(adev); 4695 if (r) 4696 return r; 4697 4698 r = gfx_v11_0_kcq_resume(adev); 4699 if (r) 4700 return r; 4701 4702 if (!amdgpu_async_gfx_ring) { 4703 r = gfx_v11_0_cp_gfx_resume(adev); 4704 if (r) 4705 return r; 4706 } else { 4707 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4708 if (r) 4709 return r; 4710 } 4711 4712 if (adev->gfx.disable_kq) { 4713 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4714 ring = &adev->gfx.gfx_ring[i]; 4715 /* we don't want to set ring->ready */ 4716 r = amdgpu_ring_test_ring(ring); 4717 if (r) 4718 return r; 4719 } 4720 if (amdgpu_async_gfx_ring) 4721 amdgpu_gfx_disable_kgq(adev, 0); 4722 } else { 4723 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4724 ring = &adev->gfx.gfx_ring[i]; 4725 r = amdgpu_ring_test_helper(ring); 4726 if (r) 4727 return r; 4728 } 4729 } 4730 4731 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4732 ring = &adev->gfx.compute_ring[i]; 4733 r = amdgpu_ring_test_helper(ring); 4734 if (r) 4735 return r; 4736 } 4737 4738 return 0; 4739 } 4740 4741 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4742 { 4743 gfx_v11_0_cp_gfx_enable(adev, enable); 4744 gfx_v11_0_cp_compute_enable(adev, enable); 4745 } 4746 4747 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4748 { 4749 int r; 4750 bool value; 4751 4752 r = adev->gfxhub.funcs->gart_enable(adev); 4753 if (r) 4754 return r; 4755 4756 amdgpu_device_flush_hdp(adev, NULL); 4757 4758 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 4759 4760 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4761 /* TODO investigate why this and the hdp flush above is needed, 4762 * are we missing a flush somewhere else? */ 4763 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4764 4765 return 0; 4766 } 4767 4768 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4769 { 4770 u32 tmp; 4771 4772 /* select RS64 */ 4773 if (adev->gfx.rs64_enable) { 4774 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4775 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4776 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4777 4778 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4779 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4780 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4781 } 4782 4783 if (amdgpu_emu_mode == 1) 4784 msleep(100); 4785 } 4786 4787 static int get_gb_addr_config(struct amdgpu_device * adev) 4788 { 4789 u32 gb_addr_config; 4790 4791 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4792 if (gb_addr_config == 0) 4793 return -EINVAL; 4794 4795 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4796 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4797 4798 adev->gfx.config.gb_addr_config = gb_addr_config; 4799 4800 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4801 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4802 GB_ADDR_CONFIG, NUM_PIPES); 4803 4804 adev->gfx.config.max_tile_pipes = 4805 adev->gfx.config.gb_addr_config_fields.num_pipes; 4806 4807 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4808 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4809 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4810 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4811 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4812 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4813 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4814 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4815 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4816 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4817 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4818 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4819 4820 return 0; 4821 } 4822 4823 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4824 { 4825 uint32_t data; 4826 4827 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4828 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4829 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4830 4831 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4832 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4833 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4834 } 4835 4836 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 4837 bool enable) 4838 { 4839 unsigned int irq_type; 4840 int m, p, r; 4841 4842 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 4843 for (m = 0; m < adev->gfx.me.num_me; m++) { 4844 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 4845 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4846 if (enable) 4847 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 4848 else 4849 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4850 if (r) { 4851 if (!enable) 4852 return r; 4853 goto err_gfx; 4854 } 4855 } 4856 } 4857 } 4858 4859 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 4860 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 4861 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 4862 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4863 + (m * adev->gfx.mec.num_pipe_per_mec) 4864 + p; 4865 if (enable) 4866 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 4867 else 4868 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4869 if (r) { 4870 if (!enable) 4871 return r; 4872 goto err_compute; 4873 } 4874 } 4875 } 4876 } 4877 4878 return 0; 4879 4880 err_compute: 4881 for (p--; p >= 0; p--) { 4882 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4883 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 4884 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4885 } 4886 for (m--; m >= 0; m--) { 4887 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 4888 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4889 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 4890 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4891 } 4892 } 4893 m = adev->gfx.me.num_me; 4894 err_gfx: 4895 for (p--; p >= 0; p--) { 4896 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4897 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4898 } 4899 for (m--; m >= 0; m--) { 4900 for (p = adev->gfx.me.num_pipe_per_me - 1; p >= 0; p--) { 4901 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4902 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 4903 } 4904 } 4905 return r; 4906 } 4907 4908 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4909 { 4910 int r; 4911 struct amdgpu_device *adev = ip_block->adev; 4912 4913 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4914 adev->gfx.cleaner_shader_ptr); 4915 4916 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4917 if (adev->gfx.imu.funcs) { 4918 /* RLC autoload sequence 1: Program rlc ram */ 4919 if (adev->gfx.imu.funcs->program_rlc_ram) 4920 adev->gfx.imu.funcs->program_rlc_ram(adev); 4921 /* rlc autoload firmware */ 4922 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4923 if (r) 4924 return r; 4925 } 4926 } else { 4927 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4928 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4929 if (adev->gfx.imu.funcs->load_microcode) 4930 adev->gfx.imu.funcs->load_microcode(adev); 4931 if (adev->gfx.imu.funcs->setup_imu) 4932 adev->gfx.imu.funcs->setup_imu(adev); 4933 if (adev->gfx.imu.funcs->start_imu) 4934 adev->gfx.imu.funcs->start_imu(adev); 4935 } 4936 4937 /* disable gpa mode in backdoor loading */ 4938 gfx_v11_0_disable_gpa_mode(adev); 4939 } 4940 } 4941 4942 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4943 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4944 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4945 if (r) { 4946 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4947 return r; 4948 } 4949 } 4950 4951 adev->gfx.is_poweron = true; 4952 4953 if(get_gb_addr_config(adev)) 4954 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 4955 4956 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4957 adev->gfx.rs64_enable) 4958 gfx_v11_0_config_gfx_rs64(adev); 4959 4960 r = gfx_v11_0_gfxhub_enable(adev); 4961 if (r) 4962 return r; 4963 4964 if (!amdgpu_emu_mode) 4965 gfx_v11_0_init_golden_registers(adev); 4966 4967 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4968 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4969 /** 4970 * For gfx 11, rlc firmware loading relies on smu firmware is 4971 * loaded firstly, so in direct type, it has to load smc ucode 4972 * here before rlc. 4973 */ 4974 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4975 if (r) 4976 return r; 4977 } 4978 4979 gfx_v11_0_constants_init(adev); 4980 4981 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4982 gfx_v11_0_select_cp_fw_arch(adev); 4983 4984 if (adev->nbio.funcs->gc_doorbell_init) 4985 adev->nbio.funcs->gc_doorbell_init(adev); 4986 4987 r = gfx_v11_0_rlc_resume(adev); 4988 if (r) 4989 return r; 4990 4991 /* 4992 * init golden registers and rlc resume may override some registers, 4993 * reconfig them here 4994 */ 4995 gfx_v11_0_tcp_harvest(adev); 4996 4997 r = gfx_v11_0_cp_resume(adev); 4998 if (r) 4999 return r; 5000 5001 /* get IMU version from HW if it's not set */ 5002 if (!adev->gfx.imu_fw_version) 5003 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 5004 5005 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5006 if (r) 5007 return r; 5008 5009 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5010 if (r) 5011 goto err_priv_inst; 5012 5013 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5014 if (r) 5015 goto err_bad_op; 5016 5017 r = gfx_v11_0_set_userq_eop_interrupts(adev, true); 5018 if (r) 5019 goto err_userq_eop; 5020 5021 return 0; 5022 5023 err_userq_eop: 5024 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 5025 err_bad_op: 5026 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 5027 err_priv_inst: 5028 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 5029 return r; 5030 } 5031 5032 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 5033 { 5034 struct amdgpu_device *adev = ip_block->adev; 5035 5036 cancel_delayed_work_sync(&adev->gfx.idle_work); 5037 5038 gfx_v11_0_set_userq_eop_interrupts(adev, false); 5039 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 5040 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 5041 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 5042 5043 if (!adev->no_hw_access) { 5044 if (amdgpu_async_gfx_ring && 5045 !adev->gfx.disable_kq) { 5046 if (amdgpu_gfx_disable_kgq(adev, 0)) 5047 DRM_ERROR("KGQ disable failed\n"); 5048 } 5049 5050 if (amdgpu_gfx_disable_kcq(adev, 0)) 5051 DRM_ERROR("KCQ disable failed\n"); 5052 5053 amdgpu_mes_kiq_hw_fini(adev, 0); 5054 } 5055 5056 if (amdgpu_sriov_vf(adev)) 5057 /* Remove the steps disabling CPG and clearing KIQ position, 5058 * so that CP could perform IDLE-SAVE during switch. Those 5059 * steps are necessary to avoid a DMAR error in gfx9 but it is 5060 * not reproduced on gfx11. 5061 */ 5062 return 0; 5063 5064 gfx_v11_0_cp_enable(adev, false); 5065 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 5066 5067 adev->gfxhub.funcs->gart_disable(adev); 5068 5069 adev->gfx.is_poweron = false; 5070 5071 return 0; 5072 } 5073 5074 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 5075 { 5076 return gfx_v11_0_hw_fini(ip_block); 5077 } 5078 5079 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 5080 { 5081 return gfx_v11_0_hw_init(ip_block); 5082 } 5083 5084 static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 5085 { 5086 struct amdgpu_device *adev = ip_block->adev; 5087 5088 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 5089 GRBM_STATUS, GUI_ACTIVE)) 5090 return false; 5091 else 5092 return true; 5093 } 5094 5095 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 5096 { 5097 unsigned i; 5098 u32 tmp; 5099 struct amdgpu_device *adev = ip_block->adev; 5100 5101 for (i = 0; i < adev->usec_timeout; i++) { 5102 /* read MC_STATUS */ 5103 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 5104 GRBM_STATUS__GUI_ACTIVE_MASK; 5105 5106 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 5107 return 0; 5108 udelay(1); 5109 } 5110 return -ETIMEDOUT; 5111 } 5112 5113 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 5114 bool req) 5115 { 5116 u32 i, tmp, val; 5117 5118 for (i = 0; i < adev->usec_timeout; i++) { 5119 /* Request with MeId=2, PipeId=0 */ 5120 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 5121 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 5122 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 5123 5124 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 5125 if (req) { 5126 if (val == tmp) 5127 break; 5128 } else { 5129 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 5130 REQUEST, 1); 5131 5132 /* unlocked or locked by firmware */ 5133 if (val != tmp) 5134 break; 5135 } 5136 udelay(1); 5137 } 5138 5139 if (i >= adev->usec_timeout) 5140 return -EINVAL; 5141 5142 return 0; 5143 } 5144 5145 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 5146 { 5147 u32 grbm_soft_reset = 0; 5148 u32 tmp; 5149 int r, i, j, k; 5150 struct amdgpu_device *adev = ip_block->adev; 5151 5152 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5153 5154 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5155 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 5156 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 5157 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 5158 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 5159 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5160 5161 mutex_lock(&adev->srbm_mutex); 5162 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 5163 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 5164 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 5165 soc21_grbm_select(adev, i, k, j, 0); 5166 5167 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 5168 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 5169 } 5170 } 5171 } 5172 for (i = 0; i < adev->gfx.me.num_me; ++i) { 5173 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 5174 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 5175 soc21_grbm_select(adev, i, k, j, 0); 5176 5177 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 5178 } 5179 } 5180 } 5181 soc21_grbm_select(adev, 0, 0, 0, 0); 5182 mutex_unlock(&adev->srbm_mutex); 5183 5184 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 5185 mutex_lock(&adev->gfx.reset_sem_mutex); 5186 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 5187 if (r) { 5188 mutex_unlock(&adev->gfx.reset_sem_mutex); 5189 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 5190 return r; 5191 } 5192 5193 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 5194 5195 // Read CP_VMID_RESET register three times. 5196 // to get sufficient time for GFX_HQD_ACTIVE reach 0 5197 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5198 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5199 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5200 5201 /* release the gfx mutex */ 5202 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 5203 mutex_unlock(&adev->gfx.reset_sem_mutex); 5204 if (r) { 5205 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 5206 return r; 5207 } 5208 5209 for (i = 0; i < adev->usec_timeout; i++) { 5210 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 5211 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 5212 break; 5213 udelay(1); 5214 } 5215 if (i >= adev->usec_timeout) { 5216 printk("Failed to wait all pipes clean\n"); 5217 return -EINVAL; 5218 } 5219 5220 /********** trigger soft reset ***********/ 5221 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5222 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5223 SOFT_RESET_CP, 1); 5224 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5225 SOFT_RESET_GFX, 1); 5226 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5227 SOFT_RESET_CPF, 1); 5228 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5229 SOFT_RESET_CPC, 1); 5230 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5231 SOFT_RESET_CPG, 1); 5232 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5233 /********** exit soft reset ***********/ 5234 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5235 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5236 SOFT_RESET_CP, 0); 5237 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5238 SOFT_RESET_GFX, 0); 5239 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5240 SOFT_RESET_CPF, 0); 5241 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5242 SOFT_RESET_CPC, 0); 5243 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5244 SOFT_RESET_CPG, 0); 5245 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5246 5247 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 5248 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 5249 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 5250 5251 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 5252 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 5253 5254 for (i = 0; i < adev->usec_timeout; i++) { 5255 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 5256 break; 5257 udelay(1); 5258 } 5259 if (i >= adev->usec_timeout) { 5260 printk("Failed to wait CP_VMID_RESET to 0\n"); 5261 return -EINVAL; 5262 } 5263 5264 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5265 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5266 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5267 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5268 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5269 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5270 5271 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5272 5273 r = gfx_v11_0_cp_resume(adev); 5274 if (r) 5275 return r; 5276 5277 /** 5278 * GFX soft reset impacts MES, resume MES after GFX soft reset is finished 5279 */ 5280 return amdgpu_mes_resume(adev, 0); 5281 } 5282 5283 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5284 { 5285 uint64_t clock; 5286 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5287 5288 if (amdgpu_sriov_vf(adev)) { 5289 amdgpu_gfx_off_ctrl(adev, false); 5290 mutex_lock(&adev->gfx.gpu_clock_mutex); 5291 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5292 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5293 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5294 if (clock_counter_hi_pre != clock_counter_hi_after) 5295 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5296 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5297 amdgpu_gfx_off_ctrl(adev, true); 5298 } else { 5299 preempt_disable(); 5300 if (amdgpu_ip_version(adev, SMUIO_HWIP, 0) < IP_VERSION(15, 0, 0)) { 5301 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, 5302 regGOLDEN_TSC_COUNT_UPPER); 5303 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5304 regGOLDEN_TSC_COUNT_LOWER); 5305 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, 5306 regGOLDEN_TSC_COUNT_UPPER); 5307 if (clock_counter_hi_pre != clock_counter_hi_after) 5308 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5309 regGOLDEN_TSC_COUNT_LOWER); 5310 } else { 5311 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, 5312 regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); 5313 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5314 regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); 5315 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, 5316 regGOLDEN_TSC_COUNT_UPPER_smu_15_0_0); 5317 if (clock_counter_hi_pre != clock_counter_hi_after) 5318 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, 5319 regGOLDEN_TSC_COUNT_LOWER_smu_15_0_0); 5320 } 5321 preempt_enable(); 5322 } 5323 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5324 5325 return clock; 5326 } 5327 5328 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5329 uint32_t vmid, 5330 uint32_t gds_base, uint32_t gds_size, 5331 uint32_t gws_base, uint32_t gws_size, 5332 uint32_t oa_base, uint32_t oa_size) 5333 { 5334 struct amdgpu_device *adev = ring->adev; 5335 5336 /* GDS Base */ 5337 gfx_v11_0_write_data_to_reg(ring, 0, false, 5338 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5339 gds_base); 5340 5341 /* GDS Size */ 5342 gfx_v11_0_write_data_to_reg(ring, 0, false, 5343 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5344 gds_size); 5345 5346 /* GWS */ 5347 gfx_v11_0_write_data_to_reg(ring, 0, false, 5348 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5349 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5350 5351 /* OA */ 5352 gfx_v11_0_write_data_to_reg(ring, 0, false, 5353 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5354 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5355 } 5356 5357 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5358 { 5359 struct amdgpu_device *adev = ip_block->adev; 5360 5361 switch (amdgpu_user_queue) { 5362 case -1: 5363 case 0: 5364 default: 5365 adev->gfx.disable_kq = false; 5366 adev->gfx.disable_uq = true; 5367 break; 5368 case 1: 5369 adev->gfx.disable_kq = false; 5370 adev->gfx.disable_uq = false; 5371 break; 5372 case 2: 5373 adev->gfx.disable_kq = true; 5374 adev->gfx.disable_uq = false; 5375 break; 5376 } 5377 5378 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5379 5380 if (adev->gfx.disable_kq) { 5381 /* We need one GFX ring temporarily to set up 5382 * the clear state. 5383 */ 5384 adev->gfx.num_gfx_rings = 1; 5385 adev->gfx.num_compute_rings = 0; 5386 } else { 5387 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5388 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5389 AMDGPU_MAX_COMPUTE_RINGS); 5390 } 5391 5392 gfx_v11_0_set_kiq_pm4_funcs(adev); 5393 gfx_v11_0_set_ring_funcs(adev); 5394 gfx_v11_0_set_irq_funcs(adev); 5395 gfx_v11_0_set_gds_init(adev); 5396 gfx_v11_0_set_rlc_funcs(adev); 5397 gfx_v11_0_set_mqd_funcs(adev); 5398 gfx_v11_0_set_imu_funcs(adev); 5399 5400 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5401 5402 amdgpu_init_rlc_reg_funcs(adev); 5403 5404 return gfx_v11_0_init_microcode(adev); 5405 } 5406 5407 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5408 { 5409 uint32_t rlc_cntl; 5410 5411 /* if RLC is not enabled, do nothing */ 5412 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5413 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5414 } 5415 5416 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5417 { 5418 uint32_t data; 5419 unsigned i; 5420 5421 data = RLC_SAFE_MODE__CMD_MASK; 5422 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5423 5424 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5425 5426 /* wait for RLC_SAFE_MODE */ 5427 for (i = 0; i < adev->usec_timeout; i++) { 5428 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5429 RLC_SAFE_MODE, CMD)) 5430 break; 5431 udelay(1); 5432 } 5433 } 5434 5435 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5436 { 5437 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5438 } 5439 5440 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5441 bool enable) 5442 { 5443 uint32_t def, data; 5444 5445 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5446 return; 5447 5448 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5449 5450 if (enable) 5451 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5452 else 5453 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5454 5455 if (def != data) 5456 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5457 } 5458 5459 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5460 bool enable) 5461 { 5462 uint32_t def, data; 5463 5464 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5465 return; 5466 5467 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5468 5469 if (enable) 5470 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5471 else 5472 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5473 5474 if (def != data) 5475 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5476 } 5477 5478 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5479 bool enable) 5480 { 5481 uint32_t def, data; 5482 5483 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5484 return; 5485 5486 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5487 5488 if (enable) 5489 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5490 else 5491 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5492 5493 if (def != data) 5494 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5495 } 5496 5497 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5498 bool enable) 5499 { 5500 uint32_t data, def; 5501 5502 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5503 return; 5504 5505 /* It is disabled by HW by default */ 5506 if (enable) { 5507 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5508 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5509 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5510 5511 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5512 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5513 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5514 5515 if (def != data) 5516 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5517 } 5518 } else { 5519 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5520 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5521 5522 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5523 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5524 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5525 5526 if (def != data) 5527 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5528 } 5529 } 5530 } 5531 5532 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5533 bool enable) 5534 { 5535 uint32_t def, data; 5536 5537 if (!(adev->cg_flags & 5538 (AMD_CG_SUPPORT_GFX_CGCG | 5539 AMD_CG_SUPPORT_GFX_CGLS | 5540 AMD_CG_SUPPORT_GFX_3D_CGCG | 5541 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5542 return; 5543 5544 if (enable) { 5545 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5546 5547 /* unset CGCG override */ 5548 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5549 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5550 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5551 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5552 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5553 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5554 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5555 5556 /* update CGCG override bits */ 5557 if (def != data) 5558 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5559 5560 /* enable cgcg FSM(0x0000363F) */ 5561 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5562 5563 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5564 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5565 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5566 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5567 } 5568 5569 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5570 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5571 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5572 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5573 } 5574 5575 if (def != data) 5576 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5577 5578 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5579 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5580 5581 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5582 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5583 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5584 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5585 } 5586 5587 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5588 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5589 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5590 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5591 } 5592 5593 if (def != data) 5594 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5595 5596 /* set IDLE_POLL_COUNT(0x00900100) */ 5597 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5598 5599 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5600 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5601 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5602 5603 if (def != data) 5604 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5605 5606 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5607 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5608 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5609 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5610 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5611 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5612 5613 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5614 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5615 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5616 5617 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5618 if (adev->sdma.num_instances > 1) { 5619 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5620 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5621 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5622 } 5623 } else { 5624 /* Program RLC_CGCG_CGLS_CTRL */ 5625 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5626 5627 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5628 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5629 5630 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5631 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5632 5633 if (def != data) 5634 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5635 5636 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5637 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5638 5639 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5640 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5641 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5642 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5643 5644 if (def != data) 5645 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5646 5647 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5648 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5649 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5650 5651 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5652 if (adev->sdma.num_instances > 1) { 5653 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5654 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5655 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5656 } 5657 } 5658 } 5659 5660 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5661 bool enable) 5662 { 5663 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5664 5665 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5666 5667 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5668 5669 gfx_v11_0_update_repeater_fgcg(adev, enable); 5670 5671 gfx_v11_0_update_sram_fgcg(adev, enable); 5672 5673 gfx_v11_0_update_perf_clk(adev, enable); 5674 5675 if (adev->cg_flags & 5676 (AMD_CG_SUPPORT_GFX_MGCG | 5677 AMD_CG_SUPPORT_GFX_CGLS | 5678 AMD_CG_SUPPORT_GFX_CGCG | 5679 AMD_CG_SUPPORT_GFX_3D_CGCG | 5680 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5681 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5682 5683 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5684 5685 return 0; 5686 } 5687 5688 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 5689 struct amdgpu_ring *ring, unsigned vmid) 5690 { 5691 u32 reg, pre_data, data; 5692 5693 amdgpu_gfx_off_ctrl(adev, false); 5694 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5695 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5696 pre_data = RREG32_NO_KIQ(reg); 5697 else 5698 pre_data = RREG32(reg); 5699 5700 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5701 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5702 5703 if (pre_data != data) { 5704 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5705 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5706 } else 5707 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5708 } 5709 amdgpu_gfx_off_ctrl(adev, true); 5710 5711 if (ring 5712 && amdgpu_sriov_is_pp_one_vf(adev) 5713 && (pre_data != data) 5714 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5715 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5716 amdgpu_ring_emit_wreg(ring, reg, data); 5717 } 5718 } 5719 5720 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5721 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5722 .set_safe_mode = gfx_v11_0_set_safe_mode, 5723 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5724 .init = gfx_v11_0_rlc_init, 5725 .get_csb_size = gfx_v11_0_get_csb_size, 5726 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5727 .resume = gfx_v11_0_rlc_resume, 5728 .stop = gfx_v11_0_rlc_stop, 5729 .reset = gfx_v11_0_rlc_reset, 5730 .start = gfx_v11_0_rlc_start, 5731 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5732 }; 5733 5734 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5735 { 5736 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5737 5738 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5739 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5740 else 5741 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5742 5743 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5744 5745 // Program RLC_PG_DELAY3 for CGPG hysteresis 5746 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5747 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5748 case IP_VERSION(11, 0, 1): 5749 case IP_VERSION(11, 0, 4): 5750 case IP_VERSION(11, 5, 0): 5751 case IP_VERSION(11, 5, 1): 5752 case IP_VERSION(11, 5, 2): 5753 case IP_VERSION(11, 5, 3): 5754 case IP_VERSION(11, 5, 4): 5755 case IP_VERSION(11, 5, 6): 5756 case IP_VERSION(11, 7, 0): 5757 case IP_VERSION(11, 7, 1): 5758 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5759 break; 5760 default: 5761 break; 5762 } 5763 } 5764 } 5765 5766 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5767 { 5768 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5769 5770 gfx_v11_cntl_power_gating(adev, enable); 5771 5772 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5773 } 5774 5775 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5776 enum amd_powergating_state state) 5777 { 5778 struct amdgpu_device *adev = ip_block->adev; 5779 bool enable = (state == AMD_PG_STATE_GATE); 5780 5781 if (amdgpu_sriov_vf(adev)) 5782 return 0; 5783 5784 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5785 case IP_VERSION(11, 0, 0): 5786 case IP_VERSION(11, 0, 2): 5787 case IP_VERSION(11, 0, 3): 5788 amdgpu_gfx_off_ctrl(adev, enable); 5789 break; 5790 case IP_VERSION(11, 0, 1): 5791 case IP_VERSION(11, 0, 4): 5792 case IP_VERSION(11, 5, 0): 5793 case IP_VERSION(11, 5, 1): 5794 case IP_VERSION(11, 5, 2): 5795 case IP_VERSION(11, 5, 3): 5796 case IP_VERSION(11, 5, 4): 5797 case IP_VERSION(11, 5, 6): 5798 case IP_VERSION(11, 7, 0): 5799 case IP_VERSION(11, 7, 1): 5800 if (!enable) 5801 amdgpu_gfx_off_ctrl(adev, false); 5802 5803 gfx_v11_cntl_pg(adev, enable); 5804 5805 if (enable) 5806 amdgpu_gfx_off_ctrl(adev, true); 5807 5808 break; 5809 default: 5810 break; 5811 } 5812 5813 return 0; 5814 } 5815 5816 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5817 enum amd_clockgating_state state) 5818 { 5819 struct amdgpu_device *adev = ip_block->adev; 5820 5821 if (amdgpu_sriov_vf(adev)) 5822 return 0; 5823 5824 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5825 case IP_VERSION(11, 0, 0): 5826 case IP_VERSION(11, 0, 1): 5827 case IP_VERSION(11, 0, 2): 5828 case IP_VERSION(11, 0, 3): 5829 case IP_VERSION(11, 0, 4): 5830 case IP_VERSION(11, 5, 0): 5831 case IP_VERSION(11, 5, 1): 5832 case IP_VERSION(11, 5, 2): 5833 case IP_VERSION(11, 5, 3): 5834 case IP_VERSION(11, 5, 4): 5835 case IP_VERSION(11, 5, 6): 5836 case IP_VERSION(11, 7, 0): 5837 case IP_VERSION(11, 7, 1): 5838 gfx_v11_0_update_gfx_clock_gating(adev, 5839 state == AMD_CG_STATE_GATE); 5840 break; 5841 default: 5842 break; 5843 } 5844 5845 return 0; 5846 } 5847 5848 static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 5849 { 5850 struct amdgpu_device *adev = ip_block->adev; 5851 int data; 5852 5853 /* AMD_CG_SUPPORT_GFX_MGCG */ 5854 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5855 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5856 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5857 5858 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5859 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5860 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5861 5862 /* AMD_CG_SUPPORT_GFX_FGCG */ 5863 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5864 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5865 5866 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5867 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5868 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5869 5870 /* AMD_CG_SUPPORT_GFX_CGCG */ 5871 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5872 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5873 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5874 5875 /* AMD_CG_SUPPORT_GFX_CGLS */ 5876 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5877 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5878 5879 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5880 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5881 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5882 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5883 5884 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5885 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5886 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5887 } 5888 5889 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5890 { 5891 /* gfx11 is 32bit rptr*/ 5892 return *(uint32_t *)ring->rptr_cpu_addr; 5893 } 5894 5895 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5896 { 5897 struct amdgpu_device *adev = ring->adev; 5898 u64 wptr; 5899 5900 /* XXX check if swapping is necessary on BE */ 5901 if (ring->use_doorbell) { 5902 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5903 } else { 5904 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5905 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5906 } 5907 5908 return wptr; 5909 } 5910 5911 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5912 { 5913 struct amdgpu_device *adev = ring->adev; 5914 5915 if (ring->use_doorbell) { 5916 /* XXX check if swapping is necessary on BE */ 5917 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5918 ring->wptr); 5919 WDOORBELL64(ring->doorbell_index, ring->wptr); 5920 } else { 5921 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5922 lower_32_bits(ring->wptr)); 5923 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5924 upper_32_bits(ring->wptr)); 5925 } 5926 } 5927 5928 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5929 { 5930 /* gfx11 hardware is 32bit rptr */ 5931 return *(uint32_t *)ring->rptr_cpu_addr; 5932 } 5933 5934 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5935 { 5936 u64 wptr; 5937 5938 /* XXX check if swapping is necessary on BE */ 5939 if (ring->use_doorbell) 5940 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5941 else 5942 BUG(); 5943 return wptr; 5944 } 5945 5946 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5947 { 5948 struct amdgpu_device *adev = ring->adev; 5949 5950 /* XXX check if swapping is necessary on BE */ 5951 if (ring->use_doorbell) { 5952 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5953 ring->wptr); 5954 WDOORBELL64(ring->doorbell_index, ring->wptr); 5955 } else { 5956 BUG(); /* only DOORBELL method supported on gfx11 now */ 5957 } 5958 } 5959 5960 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5961 { 5962 struct amdgpu_device *adev = ring->adev; 5963 u32 ref_and_mask, reg_mem_engine; 5964 5965 if (!adev->gfx.funcs->get_hdp_flush_mask) { 5966 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 5967 return; 5968 } 5969 5970 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 5971 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5972 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5973 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5974 ref_and_mask, ref_and_mask, 0x20); 5975 } 5976 5977 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5978 struct amdgpu_job *job, 5979 struct amdgpu_ib *ib, 5980 uint32_t flags) 5981 { 5982 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5983 u32 header, control = 0; 5984 5985 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5986 5987 control |= ib->length_dw | (vmid << 24); 5988 5989 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5990 control |= INDIRECT_BUFFER_PRE_ENB(1); 5991 5992 if (flags & AMDGPU_IB_PREEMPTED) 5993 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5994 5995 if (vmid && !ring->adev->gfx.rs64_enable) 5996 gfx_v11_0_ring_emit_de_meta(ring, 5997 !amdgpu_sriov_vf(ring->adev) && (flags & AMDGPU_IB_PREEMPTED)); 5998 } 5999 6000 amdgpu_ring_write(ring, header); 6001 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 6002 amdgpu_ring_write(ring, 6003 #ifdef __BIG_ENDIAN 6004 (2 << 0) | 6005 #endif 6006 lower_32_bits(ib->gpu_addr)); 6007 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 6008 amdgpu_ring_write(ring, control); 6009 } 6010 6011 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 6012 struct amdgpu_job *job, 6013 struct amdgpu_ib *ib, 6014 uint32_t flags) 6015 { 6016 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 6017 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 6018 6019 /* Currently, there is a high possibility to get wave ID mismatch 6020 * between ME and GDS, leading to a hw deadlock, because ME generates 6021 * different wave IDs than the GDS expects. This situation happens 6022 * randomly when at least 5 compute pipes use GDS ordered append. 6023 * The wave IDs generated by ME are also wrong after suspend/resume. 6024 * Those are probably bugs somewhere else in the kernel driver. 6025 * 6026 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 6027 * GDS to 0 for this ring (me/pipe). 6028 */ 6029 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 6030 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 6031 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 6032 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 6033 } 6034 6035 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 6036 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 6037 amdgpu_ring_write(ring, 6038 #ifdef __BIG_ENDIAN 6039 (2 << 0) | 6040 #endif 6041 lower_32_bits(ib->gpu_addr)); 6042 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 6043 amdgpu_ring_write(ring, control); 6044 } 6045 6046 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 6047 u64 seq, unsigned flags) 6048 { 6049 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 6050 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 6051 6052 /* RELEASE_MEM - flush caches, send int */ 6053 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 6054 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 6055 PACKET3_RELEASE_MEM_GCR_GL2_WB | 6056 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 6057 PACKET3_RELEASE_MEM_GCR_GLM_WB | 6058 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 6059 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6060 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 6061 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 6062 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 6063 6064 /* 6065 * the address should be Qword aligned if 64bit write, Dword 6066 * aligned if only send 32bit data low (discard data high) 6067 */ 6068 if (write64bit) 6069 WARN_ON(addr & 0x7); 6070 else 6071 WARN_ON(addr & 0x3); 6072 amdgpu_ring_write(ring, lower_32_bits(addr)); 6073 amdgpu_ring_write(ring, upper_32_bits(addr)); 6074 amdgpu_ring_write(ring, lower_32_bits(seq)); 6075 amdgpu_ring_write(ring, upper_32_bits(seq)); 6076 amdgpu_ring_write(ring, 0); 6077 } 6078 6079 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 6080 { 6081 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6082 uint32_t seq = ring->fence_drv.sync_seq; 6083 uint64_t addr = ring->fence_drv.gpu_addr; 6084 6085 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 6086 upper_32_bits(addr), seq, 0xffffffff, 4); 6087 } 6088 6089 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 6090 uint16_t pasid, uint32_t flush_type, 6091 bool all_hub, uint8_t dst_sel) 6092 { 6093 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 6094 amdgpu_ring_write(ring, 6095 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 6096 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 6097 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 6098 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 6099 } 6100 6101 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 6102 unsigned vmid, uint64_t pd_addr) 6103 { 6104 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 6105 6106 /* compute doesn't have PFP */ 6107 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 6108 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 6109 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 6110 amdgpu_ring_write(ring, 0x0); 6111 } 6112 6113 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 6114 * changed in any way. 6115 */ 6116 ring->set_q_mode_offs = 0; 6117 ring->set_q_mode_ptr = NULL; 6118 } 6119 6120 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 6121 u64 seq, unsigned int flags) 6122 { 6123 struct amdgpu_device *adev = ring->adev; 6124 6125 /* write fence seq to the "addr" */ 6126 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6127 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6128 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 6129 amdgpu_ring_write(ring, lower_32_bits(addr)); 6130 amdgpu_ring_write(ring, upper_32_bits(addr)); 6131 amdgpu_ring_write(ring, lower_32_bits(seq)); 6132 6133 if (flags & AMDGPU_FENCE_FLAG_INT) { 6134 /* set register to trigger INT */ 6135 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6136 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6137 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 6138 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 6139 amdgpu_ring_write(ring, 0); 6140 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 6141 } 6142 } 6143 6144 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 6145 uint32_t flags) 6146 { 6147 uint32_t dw2 = 0; 6148 6149 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6150 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6151 /* set load_global_config & load_global_uconfig */ 6152 dw2 |= 0x8001; 6153 /* set load_cs_sh_regs */ 6154 dw2 |= 0x01000000; 6155 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 6156 dw2 |= 0x10002; 6157 } 6158 6159 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6160 amdgpu_ring_write(ring, dw2); 6161 amdgpu_ring_write(ring, 0); 6162 } 6163 6164 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 6165 uint64_t addr) 6166 { 6167 unsigned ret; 6168 6169 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6170 amdgpu_ring_write(ring, lower_32_bits(addr)); 6171 amdgpu_ring_write(ring, upper_32_bits(addr)); 6172 /* discard following DWs if *cond_exec_gpu_addr==0 */ 6173 amdgpu_ring_write(ring, 0); 6174 ret = ring->wptr & ring->buf_mask; 6175 /* patch dummy value later */ 6176 amdgpu_ring_write(ring, 0); 6177 6178 return ret; 6179 } 6180 6181 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 6182 u64 shadow_va, u64 csa_va, 6183 u64 gds_va, bool init_shadow, 6184 int vmid) 6185 { 6186 struct amdgpu_device *adev = ring->adev; 6187 unsigned int offs, end; 6188 6189 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 6190 return; 6191 6192 /* 6193 * The logic here isn't easy to understand because we need to keep state 6194 * accross multiple executions of the function as well as between the 6195 * CPU and GPU. The general idea is that the newly written GPU command 6196 * has a condition on the previous one and only executed if really 6197 * necessary. 6198 */ 6199 6200 /* 6201 * The dw in the NOP controls if the next SET_Q_MODE packet should be 6202 * executed or not. Reserve 64bits just to be on the save side. 6203 */ 6204 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 6205 offs = ring->wptr & ring->buf_mask; 6206 6207 /* 6208 * We start with skipping the prefix SET_Q_MODE and always executing 6209 * the postfix SET_Q_MODE packet. This is changed below with a 6210 * WRITE_DATA command when the postfix executed. 6211 */ 6212 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 6213 amdgpu_ring_write(ring, 0); 6214 6215 if (ring->set_q_mode_offs) { 6216 uint64_t addr; 6217 6218 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6219 addr += ring->set_q_mode_offs << 2; 6220 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 6221 } 6222 6223 /* 6224 * When the postfix SET_Q_MODE packet executes we need to make sure that the 6225 * next prefix SET_Q_MODE packet executes as well. 6226 */ 6227 if (!shadow_va) { 6228 uint64_t addr; 6229 6230 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6231 addr += offs << 2; 6232 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6233 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 6234 amdgpu_ring_write(ring, lower_32_bits(addr)); 6235 amdgpu_ring_write(ring, upper_32_bits(addr)); 6236 amdgpu_ring_write(ring, 0x1); 6237 } 6238 6239 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 6240 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 6241 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 6242 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 6243 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 6244 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 6245 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 6246 amdgpu_ring_write(ring, shadow_va ? 6247 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 6248 amdgpu_ring_write(ring, init_shadow ? 6249 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 6250 6251 if (ring->set_q_mode_offs) 6252 amdgpu_ring_patch_cond_exec(ring, end); 6253 6254 if (shadow_va) { 6255 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 6256 6257 /* 6258 * If the tokens match try to skip the last postfix SET_Q_MODE 6259 * packet to avoid saving/restoring the state all the time. 6260 */ 6261 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 6262 *ring->set_q_mode_ptr = 0; 6263 6264 ring->set_q_mode_token = token; 6265 } else { 6266 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 6267 } 6268 6269 ring->set_q_mode_offs = offs; 6270 } 6271 6272 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6273 { 6274 struct amdgpu_device *adev = ring->adev; 6275 struct v10_de_ib_state de_payload = {0}; 6276 uint64_t offset, gds_addr, de_payload_gpu_addr; 6277 void *de_payload_cpu_addr; 6278 int cnt; 6279 6280 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6281 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6282 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6283 6284 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6285 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6286 PAGE_SIZE); 6287 6288 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6289 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6290 6291 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6292 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6293 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6294 WRITE_DATA_DST_SEL(8) | 6295 WR_CONFIRM) | 6296 WRITE_DATA_CACHE_POLICY(0)); 6297 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6298 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6299 6300 if (resume) 6301 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6302 sizeof(de_payload) >> 2); 6303 else 6304 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6305 sizeof(de_payload) >> 2); 6306 } 6307 6308 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6309 bool secure) 6310 { 6311 uint32_t v = secure ? FRAME_TMZ : 0; 6312 6313 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6314 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6315 } 6316 6317 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6318 uint32_t reg_val_offs) 6319 { 6320 struct amdgpu_device *adev = ring->adev; 6321 6322 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6323 amdgpu_ring_write(ring, 0 | /* src: register*/ 6324 (5 << 8) | /* dst: memory */ 6325 (1 << 20)); /* write confirm */ 6326 amdgpu_ring_write(ring, reg); 6327 amdgpu_ring_write(ring, 0); 6328 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6329 reg_val_offs * 4)); 6330 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6331 reg_val_offs * 4)); 6332 } 6333 6334 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6335 uint32_t val) 6336 { 6337 uint32_t cmd = 0; 6338 6339 switch (ring->funcs->type) { 6340 case AMDGPU_RING_TYPE_GFX: 6341 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6342 break; 6343 case AMDGPU_RING_TYPE_KIQ: 6344 cmd = (1 << 16); /* no inc addr */ 6345 break; 6346 default: 6347 cmd = WR_CONFIRM; 6348 break; 6349 } 6350 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6351 amdgpu_ring_write(ring, cmd); 6352 amdgpu_ring_write(ring, reg); 6353 amdgpu_ring_write(ring, 0); 6354 amdgpu_ring_write(ring, val); 6355 } 6356 6357 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6358 uint32_t val, uint32_t mask) 6359 { 6360 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6361 } 6362 6363 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6364 uint32_t reg0, uint32_t reg1, 6365 uint32_t ref, uint32_t mask) 6366 { 6367 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6368 6369 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6370 ref, mask, 0x20); 6371 } 6372 6373 static void 6374 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6375 uint32_t me, uint32_t pipe, 6376 enum amdgpu_interrupt_state state) 6377 { 6378 uint32_t cp_int_cntl, cp_int_cntl_reg; 6379 6380 if (!me) { 6381 switch (pipe) { 6382 case 0: 6383 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6384 break; 6385 case 1: 6386 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6387 break; 6388 default: 6389 DRM_DEBUG("invalid pipe %d\n", pipe); 6390 return; 6391 } 6392 } else { 6393 DRM_DEBUG("invalid me %d\n", me); 6394 return; 6395 } 6396 6397 switch (state) { 6398 case AMDGPU_IRQ_STATE_DISABLE: 6399 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6400 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6401 TIME_STAMP_INT_ENABLE, 0); 6402 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6403 GENERIC0_INT_ENABLE, 0); 6404 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6405 break; 6406 case AMDGPU_IRQ_STATE_ENABLE: 6407 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6408 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6409 TIME_STAMP_INT_ENABLE, 1); 6410 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6411 GENERIC0_INT_ENABLE, 1); 6412 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6413 break; 6414 default: 6415 break; 6416 } 6417 } 6418 6419 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6420 int me, int pipe, 6421 enum amdgpu_interrupt_state state) 6422 { 6423 u32 mec_int_cntl, mec_int_cntl_reg; 6424 6425 /* 6426 * amdgpu controls only the first MEC. That's why this function only 6427 * handles the setting of interrupts for this specific MEC. All other 6428 * pipes' interrupts are set by amdkfd. 6429 */ 6430 6431 if (me == 1) { 6432 switch (pipe) { 6433 case 0: 6434 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6435 break; 6436 case 1: 6437 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6438 break; 6439 case 2: 6440 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6441 break; 6442 case 3: 6443 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6444 break; 6445 default: 6446 DRM_DEBUG("invalid pipe %d\n", pipe); 6447 return; 6448 } 6449 } else { 6450 DRM_DEBUG("invalid me %d\n", me); 6451 return; 6452 } 6453 6454 switch (state) { 6455 case AMDGPU_IRQ_STATE_DISABLE: 6456 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6457 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6458 TIME_STAMP_INT_ENABLE, 0); 6459 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6460 GENERIC0_INT_ENABLE, 0); 6461 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6462 break; 6463 case AMDGPU_IRQ_STATE_ENABLE: 6464 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6465 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6466 TIME_STAMP_INT_ENABLE, 1); 6467 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6468 GENERIC0_INT_ENABLE, 1); 6469 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6470 break; 6471 default: 6472 break; 6473 } 6474 } 6475 6476 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6477 struct amdgpu_irq_src *src, 6478 unsigned type, 6479 enum amdgpu_interrupt_state state) 6480 { 6481 switch (type) { 6482 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6483 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6484 break; 6485 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6486 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6487 break; 6488 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6489 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6490 break; 6491 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6492 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6493 break; 6494 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6495 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6496 break; 6497 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6498 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6499 break; 6500 default: 6501 break; 6502 } 6503 return 0; 6504 } 6505 6506 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6507 struct amdgpu_irq_src *source, 6508 struct amdgpu_iv_entry *entry) 6509 { 6510 u32 doorbell_offset = entry->src_data[0]; 6511 6512 DRM_DEBUG("IH: CP EOP\n"); 6513 6514 if (!adev->gfx.disable_kq) { 6515 u8 me_id = (entry->ring_id & 0x0c) >> 2; 6516 u8 pipe_id = (entry->ring_id & 0x03) >> 0; 6517 u8 queue_id = (entry->ring_id & 0x70) >> 4; 6518 struct amdgpu_ring *ring; 6519 int i; 6520 6521 switch (me_id) { 6522 case 0: 6523 /* 6524 * MES splits gfx HQDs per (me,pipe): KGQ owns queue=0, 6525 * userq gfx owns queue>=1 (see amdgpu_mes_get_hqd_mask). 6526 * Require a strict (me,pipe,queue) match so userq gfx 6527 * EOPs fall through to amdgpu_userq_process_fence_irq(). 6528 */ 6529 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6530 ring = &adev->gfx.gfx_ring[i]; 6531 if ((ring->me == me_id) && 6532 (ring->pipe == pipe_id) && 6533 (ring->queue == queue_id)) { 6534 amdgpu_fence_process(ring); 6535 return 0; 6536 } 6537 } 6538 break; 6539 case 1: 6540 case 2: 6541 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6542 ring = &adev->gfx.compute_ring[i]; 6543 /* Per-queue interrupt is supported for MEC starting from VI. 6544 * The interrupt can only be enabled/disabled per pipe instead 6545 * of per queue. 6546 */ 6547 if ((ring->me == me_id) && 6548 (ring->pipe == pipe_id) && 6549 (ring->queue == queue_id)) { 6550 amdgpu_fence_process(ring); 6551 return 0; 6552 } 6553 } 6554 break; 6555 default: 6556 break; 6557 } 6558 } 6559 6560 if (adev->enable_mes && doorbell_offset) 6561 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 6562 6563 return 0; 6564 } 6565 6566 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6567 struct amdgpu_irq_src *source, 6568 unsigned int type, 6569 enum amdgpu_interrupt_state state) 6570 { 6571 u32 cp_int_cntl_reg, cp_int_cntl; 6572 int i, j; 6573 6574 switch (state) { 6575 case AMDGPU_IRQ_STATE_DISABLE: 6576 case AMDGPU_IRQ_STATE_ENABLE: 6577 for (i = 0; i < adev->gfx.me.num_me; i++) { 6578 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6579 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6580 6581 if (cp_int_cntl_reg) { 6582 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6583 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6584 PRIV_REG_INT_ENABLE, 6585 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6586 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6587 } 6588 } 6589 } 6590 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6591 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6592 /* MECs start at 1 */ 6593 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6594 6595 if (cp_int_cntl_reg) { 6596 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6597 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6598 PRIV_REG_INT_ENABLE, 6599 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6600 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6601 } 6602 } 6603 } 6604 break; 6605 default: 6606 break; 6607 } 6608 6609 return 0; 6610 } 6611 6612 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6613 struct amdgpu_irq_src *source, 6614 unsigned type, 6615 enum amdgpu_interrupt_state state) 6616 { 6617 u32 cp_int_cntl_reg, cp_int_cntl; 6618 int i, j; 6619 6620 switch (state) { 6621 case AMDGPU_IRQ_STATE_DISABLE: 6622 case AMDGPU_IRQ_STATE_ENABLE: 6623 for (i = 0; i < adev->gfx.me.num_me; i++) { 6624 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6625 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6626 6627 if (cp_int_cntl_reg) { 6628 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6629 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6630 OPCODE_ERROR_INT_ENABLE, 6631 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6632 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6633 } 6634 } 6635 } 6636 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6637 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6638 /* MECs start at 1 */ 6639 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6640 6641 if (cp_int_cntl_reg) { 6642 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6643 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6644 OPCODE_ERROR_INT_ENABLE, 6645 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6646 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6647 } 6648 } 6649 } 6650 break; 6651 default: 6652 break; 6653 } 6654 return 0; 6655 } 6656 6657 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6658 struct amdgpu_irq_src *source, 6659 unsigned int type, 6660 enum amdgpu_interrupt_state state) 6661 { 6662 u32 cp_int_cntl_reg, cp_int_cntl; 6663 int i, j; 6664 6665 switch (state) { 6666 case AMDGPU_IRQ_STATE_DISABLE: 6667 case AMDGPU_IRQ_STATE_ENABLE: 6668 for (i = 0; i < adev->gfx.me.num_me; i++) { 6669 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6670 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6671 6672 if (cp_int_cntl_reg) { 6673 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6674 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6675 PRIV_INSTR_INT_ENABLE, 6676 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6677 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6678 } 6679 } 6680 } 6681 break; 6682 default: 6683 break; 6684 } 6685 6686 return 0; 6687 } 6688 6689 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6690 struct amdgpu_iv_entry *entry) 6691 { 6692 u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK; 6693 6694 /* 6695 * Try KQ first by ring_id (HW slot is authoritative). The 6696 * KMD compute_hqd_mask contract guarantees KCQ and user queues 6697 * never share a HW slot. 6698 */ 6699 if (!adev->gfx.disable_kq) { 6700 u8 me_id = (entry->ring_id & 0x0c) >> 2; 6701 u8 pipe_id = (entry->ring_id & 0x03) >> 0; 6702 u8 queue_id = (entry->ring_id & 0x70) >> 4; 6703 struct amdgpu_ring *ring; 6704 int i; 6705 6706 switch (me_id) { 6707 case 0: 6708 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6709 ring = &adev->gfx.gfx_ring[i]; 6710 if (ring->me == me_id && ring->pipe == pipe_id && 6711 ring->queue == queue_id) { 6712 drm_sched_fault(&ring->sched); 6713 return; 6714 } 6715 } 6716 break; 6717 case 1: 6718 case 2: 6719 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6720 ring = &adev->gfx.compute_ring[i]; 6721 if (ring->me == me_id && ring->pipe == pipe_id && 6722 ring->queue == queue_id) { 6723 drm_sched_fault(&ring->sched); 6724 return; 6725 } 6726 } 6727 break; 6728 default: 6729 BUG(); 6730 break; 6731 } 6732 } 6733 6734 /* No KQ matched: HW slot is a MES-scheduled user queue. */ 6735 if (adev->enable_mes && doorbell_offset) 6736 amdgpu_userq_process_reset_irq(adev, entry->pasid, 6737 doorbell_offset); 6738 } 6739 6740 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6741 struct amdgpu_irq_src *source, 6742 struct amdgpu_iv_entry *entry) 6743 { 6744 DRM_ERROR("Illegal register access in command stream\n"); 6745 gfx_v11_0_handle_priv_fault(adev, entry); 6746 return 0; 6747 } 6748 6749 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6750 struct amdgpu_irq_src *source, 6751 struct amdgpu_iv_entry *entry) 6752 { 6753 DRM_ERROR("Illegal opcode in command stream\n"); 6754 gfx_v11_0_handle_priv_fault(adev, entry); 6755 return 0; 6756 } 6757 6758 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6759 struct amdgpu_irq_src *source, 6760 struct amdgpu_iv_entry *entry) 6761 { 6762 DRM_ERROR("Illegal instruction in command stream\n"); 6763 gfx_v11_0_handle_priv_fault(adev, entry); 6764 return 0; 6765 } 6766 6767 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6768 struct amdgpu_irq_src *source, 6769 struct amdgpu_iv_entry *entry) 6770 { 6771 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6772 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6773 6774 return 0; 6775 } 6776 6777 #if 0 6778 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6779 struct amdgpu_irq_src *src, 6780 unsigned int type, 6781 enum amdgpu_interrupt_state state) 6782 { 6783 uint32_t tmp, target; 6784 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6785 6786 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6787 target += ring->pipe; 6788 6789 switch (type) { 6790 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6791 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6792 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6793 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6794 GENERIC2_INT_ENABLE, 0); 6795 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6796 6797 tmp = RREG32_SOC15_IP(GC, target); 6798 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6799 GENERIC2_INT_ENABLE, 0); 6800 WREG32_SOC15_IP(GC, target, tmp); 6801 } else { 6802 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6803 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6804 GENERIC2_INT_ENABLE, 1); 6805 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6806 6807 tmp = RREG32_SOC15_IP(GC, target); 6808 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6809 GENERIC2_INT_ENABLE, 1); 6810 WREG32_SOC15_IP(GC, target, tmp); 6811 } 6812 break; 6813 default: 6814 BUG(); /* kiq only support GENERIC2_INT now */ 6815 break; 6816 } 6817 return 0; 6818 } 6819 #endif 6820 6821 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6822 { 6823 const unsigned int gcr_cntl = 6824 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6825 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6826 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6827 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6828 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6829 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6830 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6831 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6832 6833 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6834 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6835 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6836 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6837 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6838 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6839 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6840 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6841 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6842 } 6843 6844 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, 6845 unsigned int vmid, 6846 struct amdgpu_fence *timedout_fence) 6847 { 6848 struct amdgpu_device *adev = ring->adev; 6849 bool use_mmio = adev->gfx.me.use_mmio_for_reset; 6850 6851 return amdgpu_gfx_mes_reset_queue(ring, vmid, timedout_fence, use_mmio); 6852 } 6853 6854 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, 6855 unsigned int vmid, 6856 struct amdgpu_fence *timedout_fence) 6857 { 6858 struct amdgpu_device *adev = ring->adev; 6859 6860 return amdgpu_gfx_reset_mes_compute(adev, ring, timedout_fence, NULL, NULL, NULL); 6861 } 6862 6863 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 6864 { 6865 struct amdgpu_device *adev = ip_block->adev; 6866 uint32_t i, j, k, reg, index = 0; 6867 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6868 6869 if (!adev->gfx.ip_dump_core) 6870 return; 6871 6872 for (i = 0; i < reg_count; i++) 6873 drm_printf(p, "%-50s \t 0x%08x\n", 6874 gc_reg_list_11_0[i].reg_name, 6875 adev->gfx.ip_dump_core[i]); 6876 6877 /* print compute queue registers for all instances */ 6878 if (!adev->gfx.ip_dump_compute_queues) 6879 return; 6880 6881 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6882 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6883 adev->gfx.mec.num_mec, 6884 adev->gfx.mec.num_pipe_per_mec, 6885 adev->gfx.mec.num_queue_per_pipe); 6886 6887 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6888 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6889 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6890 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 6891 for (reg = 0; reg < reg_count; reg++) { 6892 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 6893 drm_printf(p, "%-50s \t 0x%08x\n", 6894 "regCP_MEC_ME2_HEADER_DUMP", 6895 adev->gfx.ip_dump_compute_queues[index + reg]); 6896 else 6897 drm_printf(p, "%-50s \t 0x%08x\n", 6898 gc_cp_reg_list_11[reg].reg_name, 6899 adev->gfx.ip_dump_compute_queues[index + reg]); 6900 } 6901 index += reg_count; 6902 } 6903 } 6904 } 6905 6906 /* print gfx queue registers for all instances */ 6907 if (!adev->gfx.ip_dump_gfx_queues) 6908 return; 6909 6910 index = 0; 6911 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6912 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 6913 adev->gfx.me.num_me, 6914 adev->gfx.me.num_pipe_per_me, 6915 adev->gfx.me.num_queue_per_pipe); 6916 6917 for (i = 0; i < adev->gfx.me.num_me; i++) { 6918 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6919 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6920 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 6921 for (reg = 0; reg < reg_count; reg++) { 6922 drm_printf(p, "%-50s \t 0x%08x\n", 6923 gc_gfx_queue_reg_list_11[reg].reg_name, 6924 adev->gfx.ip_dump_gfx_queues[index + reg]); 6925 } 6926 index += reg_count; 6927 } 6928 } 6929 } 6930 } 6931 6932 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 6933 { 6934 struct amdgpu_device *adev = ip_block->adev; 6935 uint32_t i, j, k, reg, index = 0; 6936 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6937 6938 if (!adev->gfx.ip_dump_core) 6939 return; 6940 6941 amdgpu_gfx_off_ctrl(adev, false); 6942 for (i = 0; i < reg_count; i++) 6943 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 6944 amdgpu_gfx_off_ctrl(adev, true); 6945 6946 /* dump compute queue registers for all instances */ 6947 if (!adev->gfx.ip_dump_compute_queues) 6948 return; 6949 6950 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6951 amdgpu_gfx_off_ctrl(adev, false); 6952 mutex_lock(&adev->srbm_mutex); 6953 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6954 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6955 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6956 /* ME0 is for GFX so start from 1 for CP */ 6957 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 6958 for (reg = 0; reg < reg_count; reg++) { 6959 if (i && 6960 gc_cp_reg_list_11[reg].reg_offset == 6961 regCP_MEC_ME1_HEADER_DUMP) 6962 adev->gfx.ip_dump_compute_queues[index + reg] = 6963 RREG32(SOC15_REG_OFFSET(GC, 0, 6964 regCP_MEC_ME2_HEADER_DUMP)); 6965 else 6966 adev->gfx.ip_dump_compute_queues[index + reg] = 6967 RREG32(SOC15_REG_ENTRY_OFFSET( 6968 gc_cp_reg_list_11[reg])); 6969 } 6970 index += reg_count; 6971 } 6972 } 6973 } 6974 soc21_grbm_select(adev, 0, 0, 0, 0); 6975 mutex_unlock(&adev->srbm_mutex); 6976 amdgpu_gfx_off_ctrl(adev, true); 6977 6978 /* dump gfx queue registers for all instances */ 6979 if (!adev->gfx.ip_dump_gfx_queues) 6980 return; 6981 6982 index = 0; 6983 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6984 amdgpu_gfx_off_ctrl(adev, false); 6985 mutex_lock(&adev->srbm_mutex); 6986 for (i = 0; i < adev->gfx.me.num_me; i++) { 6987 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6988 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6989 soc21_grbm_select(adev, i, j, k, 0); 6990 6991 for (reg = 0; reg < reg_count; reg++) { 6992 adev->gfx.ip_dump_gfx_queues[index + reg] = 6993 RREG32(SOC15_REG_ENTRY_OFFSET( 6994 gc_gfx_queue_reg_list_11[reg])); 6995 } 6996 index += reg_count; 6997 } 6998 } 6999 } 7000 soc21_grbm_select(adev, 0, 0, 0, 0); 7001 mutex_unlock(&adev->srbm_mutex); 7002 amdgpu_gfx_off_ctrl(adev, true); 7003 } 7004 7005 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 7006 { 7007 /* Emit the cleaner shader */ 7008 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 7009 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 7010 } 7011 7012 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 7013 { 7014 amdgpu_gfx_profile_ring_begin_use(ring); 7015 7016 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 7017 } 7018 7019 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 7020 { 7021 amdgpu_gfx_profile_ring_end_use(ring); 7022 7023 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 7024 } 7025 7026 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 7027 .name = "gfx_v11_0", 7028 .early_init = gfx_v11_0_early_init, 7029 .sw_init = gfx_v11_0_sw_init, 7030 .sw_fini = gfx_v11_0_sw_fini, 7031 .hw_init = gfx_v11_0_hw_init, 7032 .hw_fini = gfx_v11_0_hw_fini, 7033 .suspend = gfx_v11_0_suspend, 7034 .resume = gfx_v11_0_resume, 7035 .is_idle = gfx_v11_0_is_idle, 7036 .wait_for_idle = gfx_v11_0_wait_for_idle, 7037 .soft_reset = gfx_v11_0_soft_reset, 7038 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 7039 .set_powergating_state = gfx_v11_0_set_powergating_state, 7040 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 7041 .dump_ip_state = gfx_v11_ip_dump, 7042 .print_ip_state = gfx_v11_ip_print, 7043 }; 7044 7045 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 7046 .type = AMDGPU_RING_TYPE_GFX, 7047 .align_mask = 0xff, 7048 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7049 .support_64bit_ptrs = true, 7050 .secure_submission_supported = true, 7051 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 7052 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 7053 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 7054 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 7055 5 + /* update_spm_vmid */ 7056 5 + /* COND_EXEC */ 7057 22 + /* SET_Q_PREEMPTION_MODE */ 7058 7 + /* PIPELINE_SYNC */ 7059 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7060 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7061 4 + /* VM_FLUSH */ 7062 8 + /* FENCE for VM_FLUSH */ 7063 20 + /* GDS switch */ 7064 5 + /* COND_EXEC */ 7065 7 + /* HDP_flush */ 7066 4 + /* VGT_flush */ 7067 31 + /* DE_META */ 7068 3 + /* CNTX_CTRL */ 7069 5 + /* HDP_INVL */ 7070 22 + /* SET_Q_PREEMPTION_MODE */ 7071 8 + 8 + /* FENCE x2 */ 7072 8 + /* gfx_v11_0_emit_mem_sync */ 7073 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7074 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 7075 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 7076 .emit_fence = gfx_v11_0_ring_emit_fence, 7077 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7078 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7079 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7080 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7081 .test_ring = gfx_v11_0_ring_test_ring, 7082 .test_ib = gfx_v11_0_ring_test_ib, 7083 .insert_nop = gfx_v11_ring_insert_nop, 7084 .pad_ib = amdgpu_ring_generic_pad_ib, 7085 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 7086 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 7087 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 7088 .preempt_ib = amdgpu_gfx_ring_preempt_ib, 7089 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 7090 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7091 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7092 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7093 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7094 .reset = gfx_v11_0_reset_kgq, 7095 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7096 .begin_use = gfx_v11_0_ring_begin_use, 7097 .end_use = gfx_v11_0_ring_end_use, 7098 }; 7099 7100 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 7101 .type = AMDGPU_RING_TYPE_COMPUTE, 7102 .align_mask = 0xff, 7103 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7104 .support_64bit_ptrs = true, 7105 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7106 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7107 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7108 .emit_frame_size = 7109 5 + /* update_spm_vmid */ 7110 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7111 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7112 5 + /* hdp invalidate */ 7113 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7114 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7115 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7116 2 + /* gfx_v11_0_ring_emit_vm_flush */ 7117 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 7118 8 + /* gfx_v11_0_emit_mem_sync */ 7119 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7120 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7121 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7122 .emit_fence = gfx_v11_0_ring_emit_fence, 7123 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7124 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7125 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7126 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7127 .test_ring = gfx_v11_0_ring_test_ring, 7128 .test_ib = gfx_v11_0_ring_test_ib, 7129 .insert_nop = gfx_v11_ring_insert_nop, 7130 .pad_ib = amdgpu_ring_generic_pad_ib, 7131 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7132 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7133 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7134 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7135 .reset = gfx_v11_0_reset_kcq, 7136 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7137 .begin_use = gfx_v11_0_ring_begin_use, 7138 .end_use = gfx_v11_0_ring_end_use, 7139 }; 7140 7141 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 7142 .type = AMDGPU_RING_TYPE_KIQ, 7143 .align_mask = 0xff, 7144 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7145 .support_64bit_ptrs = true, 7146 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7147 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7148 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7149 .emit_frame_size = 7150 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7151 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7152 5 + /*hdp invalidate */ 7153 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7154 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7155 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7156 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7157 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7158 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7159 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 7160 .test_ring = gfx_v11_0_ring_test_ring, 7161 .test_ib = gfx_v11_0_ring_test_ib, 7162 .insert_nop = amdgpu_ring_insert_nop, 7163 .pad_ib = amdgpu_ring_generic_pad_ib, 7164 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7165 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7166 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7167 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7168 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7169 }; 7170 7171 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7172 { 7173 int i; 7174 7175 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7176 7177 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7178 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7179 7180 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7181 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7182 } 7183 7184 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7185 .set = gfx_v11_0_set_eop_interrupt_state, 7186 .process = gfx_v11_0_eop_irq, 7187 }; 7188 7189 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7190 .set = gfx_v11_0_set_priv_reg_fault_state, 7191 .process = gfx_v11_0_priv_reg_irq, 7192 }; 7193 7194 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7195 .set = gfx_v11_0_set_bad_op_fault_state, 7196 .process = gfx_v11_0_bad_op_irq, 7197 }; 7198 7199 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7200 .set = gfx_v11_0_set_priv_inst_fault_state, 7201 .process = gfx_v11_0_priv_inst_irq, 7202 }; 7203 7204 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7205 .process = gfx_v11_0_rlc_gc_fed_irq, 7206 }; 7207 7208 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7209 { 7210 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7211 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7212 7213 adev->gfx.priv_reg_irq.num_types = 1; 7214 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7215 7216 adev->gfx.bad_op_irq.num_types = 1; 7217 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7218 7219 adev->gfx.priv_inst_irq.num_types = 1; 7220 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7221 7222 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7223 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7224 7225 } 7226 7227 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7228 { 7229 if (adev->flags & AMD_IS_APU) 7230 adev->gfx.imu.mode = MISSION_MODE; 7231 else 7232 adev->gfx.imu.mode = DEBUG_MODE; 7233 7234 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7235 } 7236 7237 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7238 { 7239 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7240 } 7241 7242 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7243 { 7244 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7245 adev->gfx.config.max_sh_per_se * 7246 adev->gfx.config.max_shader_engines; 7247 7248 adev->gds.gds_size = 0x1000; 7249 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7250 adev->gds.gws_size = 64; 7251 adev->gds.oa_size = 16; 7252 } 7253 7254 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7255 { 7256 /* set gfx eng mqd */ 7257 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7258 sizeof(struct v11_gfx_mqd); 7259 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7260 gfx_v11_0_gfx_mqd_init; 7261 /* set compute eng mqd */ 7262 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7263 sizeof(struct v11_compute_mqd); 7264 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7265 gfx_v11_0_compute_mqd_init; 7266 } 7267 7268 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7269 u32 bitmap) 7270 { 7271 u32 data; 7272 7273 if (!bitmap) 7274 return; 7275 7276 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7277 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7278 7279 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7280 } 7281 7282 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7283 { 7284 u32 data, wgp_bitmask; 7285 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7286 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7287 7288 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7289 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7290 7291 wgp_bitmask = 7292 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7293 7294 return (~data) & wgp_bitmask; 7295 } 7296 7297 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7298 { 7299 u32 wgp_idx, wgp_active_bitmap; 7300 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7301 7302 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7303 cu_active_bitmap = 0; 7304 7305 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7306 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7307 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7308 if (wgp_active_bitmap & (1 << wgp_idx)) 7309 cu_active_bitmap |= cu_bitmap_per_wgp; 7310 } 7311 7312 return cu_active_bitmap; 7313 } 7314 7315 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7316 struct amdgpu_cu_info *cu_info) 7317 { 7318 int i, j, k, counter, active_cu_number = 0; 7319 u32 mask, bitmap; 7320 unsigned disable_masks[8 * 2]; 7321 7322 if (!adev || !cu_info) 7323 return -EINVAL; 7324 7325 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 7326 7327 mutex_lock(&adev->grbm_idx_mutex); 7328 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7329 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7330 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7331 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7332 continue; 7333 mask = 1; 7334 counter = 0; 7335 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7336 if (i < 8 && j < 2) 7337 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7338 adev, disable_masks[i * 2 + j]); 7339 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7340 7341 /** 7342 * GFX11 could support more than 4 SEs, while the bitmap 7343 * in cu_info struct is 4x4 and ioctl interface struct 7344 * drm_amdgpu_info_device should keep stable. 7345 * So we use last two columns of bitmap to store cu mask for 7346 * SEs 4 to 7, the layout of the bitmap is as below: 7347 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7348 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7349 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7350 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7351 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7352 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7353 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7354 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7355 */ 7356 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7357 7358 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7359 if (bitmap & mask) 7360 counter++; 7361 7362 mask <<= 1; 7363 } 7364 active_cu_number += counter; 7365 } 7366 } 7367 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7368 mutex_unlock(&adev->grbm_idx_mutex); 7369 7370 cu_info->number = active_cu_number; 7371 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7372 7373 return 0; 7374 } 7375 7376 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7377 { 7378 .type = AMD_IP_BLOCK_TYPE_GFX, 7379 .major = 11, 7380 .minor = 0, 7381 .rev = 0, 7382 .funcs = &gfx_v11_0_ip_funcs, 7383 }; 7384