1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 #define regPC_CONFIG_CNTL_1 0x194d 64 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 100 101 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 102 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 135 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 137 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 138 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 139 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 140 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 141 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 142 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 143 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 144 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 145 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 146 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 147 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 148 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 149 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 159 /* cp header registers */ 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 164 /* SE status registers */ 165 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 166 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 167 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 168 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 169 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 170 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 171 }; 172 173 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 174 /* compute registers */ 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 214 }; 215 216 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 217 /* gfx queue registers */ 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 243 }; 244 245 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 246 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 247 }; 248 249 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 250 { 251 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 260 }; 261 262 #define DEFAULT_SH_MEM_CONFIG \ 263 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 264 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 265 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 266 267 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 268 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 269 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 270 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 271 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 282 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 283 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 284 uint32_t val); 285 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 286 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 287 uint16_t pasid, uint32_t flush_type, 288 bool all_hub, uint8_t dst_sel); 289 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 290 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 291 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 292 bool enable); 293 294 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 295 { 296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 298 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 299 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 300 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 301 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 303 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 304 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 305 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 306 } 307 308 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 309 struct amdgpu_ring *ring) 310 { 311 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 312 uint64_t wptr_addr = ring->wptr_gpu_addr; 313 uint32_t me = 0, eng_sel = 0; 314 315 switch (ring->funcs->type) { 316 case AMDGPU_RING_TYPE_COMPUTE: 317 me = 1; 318 eng_sel = 0; 319 break; 320 case AMDGPU_RING_TYPE_GFX: 321 me = 0; 322 eng_sel = 4; 323 break; 324 case AMDGPU_RING_TYPE_MES: 325 me = 2; 326 eng_sel = 5; 327 break; 328 default: 329 WARN_ON(1); 330 } 331 332 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 333 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 334 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 335 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 336 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 337 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 338 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 339 PACKET3_MAP_QUEUES_ME((me)) | 340 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 341 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 342 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 343 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 344 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 347 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 348 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 349 } 350 351 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 352 struct amdgpu_ring *ring, 353 enum amdgpu_unmap_queues_action action, 354 u64 gpu_addr, u64 seq) 355 { 356 struct amdgpu_device *adev = kiq_ring->adev; 357 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 358 359 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 360 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 361 return; 362 } 363 364 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 366 PACKET3_UNMAP_QUEUES_ACTION(action) | 367 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 368 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 369 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 370 amdgpu_ring_write(kiq_ring, 371 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 372 373 if (action == PREEMPT_QUEUES_NO_UNMAP) { 374 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 376 amdgpu_ring_write(kiq_ring, seq); 377 } else { 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 amdgpu_ring_write(kiq_ring, 0); 381 } 382 } 383 384 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 385 struct amdgpu_ring *ring, 386 u64 addr, 387 u64 seq) 388 { 389 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 390 391 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 392 amdgpu_ring_write(kiq_ring, 393 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 394 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 395 PACKET3_QUERY_STATUS_COMMAND(2)); 396 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 397 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 398 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 401 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 402 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 403 } 404 405 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 406 uint16_t pasid, uint32_t flush_type, 407 bool all_hub) 408 { 409 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 410 } 411 412 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 413 .kiq_set_resources = gfx11_kiq_set_resources, 414 .kiq_map_queues = gfx11_kiq_map_queues, 415 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 416 .kiq_query_status = gfx11_kiq_query_status, 417 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 418 .set_resources_size = 8, 419 .map_queues_size = 7, 420 .unmap_queues_size = 6, 421 .query_status_size = 7, 422 .invalidate_tlbs_size = 2, 423 }; 424 425 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 426 { 427 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 428 } 429 430 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 431 { 432 if (amdgpu_sriov_vf(adev)) 433 return; 434 435 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 436 case IP_VERSION(11, 0, 1): 437 case IP_VERSION(11, 0, 4): 438 soc15_program_register_sequence(adev, 439 golden_settings_gc_11_0_1, 440 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 441 break; 442 default: 443 break; 444 } 445 soc15_program_register_sequence(adev, 446 golden_settings_gc_11_0, 447 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 448 449 } 450 451 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 452 bool wc, uint32_t reg, uint32_t val) 453 { 454 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 455 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 456 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 457 amdgpu_ring_write(ring, reg); 458 amdgpu_ring_write(ring, 0); 459 amdgpu_ring_write(ring, val); 460 } 461 462 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 463 int mem_space, int opt, uint32_t addr0, 464 uint32_t addr1, uint32_t ref, uint32_t mask, 465 uint32_t inv) 466 { 467 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 468 amdgpu_ring_write(ring, 469 /* memory (1) or register (0) */ 470 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 471 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 472 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 473 WAIT_REG_MEM_ENGINE(eng_sel))); 474 475 if (mem_space) 476 BUG_ON(addr0 & 0x3); /* Dword align */ 477 amdgpu_ring_write(ring, addr0); 478 amdgpu_ring_write(ring, addr1); 479 amdgpu_ring_write(ring, ref); 480 amdgpu_ring_write(ring, mask); 481 amdgpu_ring_write(ring, inv); /* poll interval */ 482 } 483 484 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 485 { 486 struct amdgpu_device *adev = ring->adev; 487 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 488 uint32_t tmp = 0; 489 unsigned i; 490 int r; 491 492 WREG32(scratch, 0xCAFEDEAD); 493 r = amdgpu_ring_alloc(ring, 5); 494 if (r) { 495 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 496 ring->idx, r); 497 return r; 498 } 499 500 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 501 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 502 } else { 503 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 504 amdgpu_ring_write(ring, scratch - 505 PACKET3_SET_UCONFIG_REG_START); 506 amdgpu_ring_write(ring, 0xDEADBEEF); 507 } 508 amdgpu_ring_commit(ring); 509 510 for (i = 0; i < adev->usec_timeout; i++) { 511 tmp = RREG32(scratch); 512 if (tmp == 0xDEADBEEF) 513 break; 514 if (amdgpu_emu_mode == 1) 515 msleep(1); 516 else 517 udelay(1); 518 } 519 520 if (i >= adev->usec_timeout) 521 r = -ETIMEDOUT; 522 return r; 523 } 524 525 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 526 { 527 struct amdgpu_device *adev = ring->adev; 528 struct amdgpu_ib ib; 529 struct dma_fence *f = NULL; 530 unsigned index; 531 uint64_t gpu_addr; 532 volatile uint32_t *cpu_ptr; 533 long r; 534 535 /* MES KIQ fw hasn't indirect buffer support for now */ 536 if (adev->enable_mes_kiq && 537 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 538 return 0; 539 540 memset(&ib, 0, sizeof(ib)); 541 542 if (ring->is_mes_queue) { 543 uint32_t padding, offset; 544 545 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 546 padding = amdgpu_mes_ctx_get_offs(ring, 547 AMDGPU_MES_CTX_PADDING_OFFS); 548 549 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 550 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 551 552 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 553 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 554 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 555 } else { 556 r = amdgpu_device_wb_get(adev, &index); 557 if (r) 558 return r; 559 560 gpu_addr = adev->wb.gpu_addr + (index * 4); 561 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 562 cpu_ptr = &adev->wb.wb[index]; 563 564 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 565 if (r) { 566 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 567 goto err1; 568 } 569 } 570 571 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 572 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 573 ib.ptr[2] = lower_32_bits(gpu_addr); 574 ib.ptr[3] = upper_32_bits(gpu_addr); 575 ib.ptr[4] = 0xDEADBEEF; 576 ib.length_dw = 5; 577 578 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 579 if (r) 580 goto err2; 581 582 r = dma_fence_wait_timeout(f, false, timeout); 583 if (r == 0) { 584 r = -ETIMEDOUT; 585 goto err2; 586 } else if (r < 0) { 587 goto err2; 588 } 589 590 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 591 r = 0; 592 else 593 r = -EINVAL; 594 err2: 595 if (!ring->is_mes_queue) 596 amdgpu_ib_free(adev, &ib, NULL); 597 dma_fence_put(f); 598 err1: 599 if (!ring->is_mes_queue) 600 amdgpu_device_wb_free(adev, index); 601 return r; 602 } 603 604 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 605 { 606 amdgpu_ucode_release(&adev->gfx.pfp_fw); 607 amdgpu_ucode_release(&adev->gfx.me_fw); 608 amdgpu_ucode_release(&adev->gfx.rlc_fw); 609 amdgpu_ucode_release(&adev->gfx.mec_fw); 610 611 kfree(adev->gfx.rlc.register_list_format); 612 } 613 614 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 615 { 616 const struct psp_firmware_header_v1_0 *toc_hdr; 617 int err = 0; 618 619 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 620 "amdgpu/%s_toc.bin", ucode_prefix); 621 if (err) 622 goto out; 623 624 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 625 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 626 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 627 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 628 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 629 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 630 return 0; 631 out: 632 amdgpu_ucode_release(&adev->psp.toc_fw); 633 return err; 634 } 635 636 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 637 { 638 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 639 case IP_VERSION(11, 0, 0): 640 case IP_VERSION(11, 0, 2): 641 case IP_VERSION(11, 0, 3): 642 if ((adev->gfx.me_fw_version >= 1505) && 643 (adev->gfx.pfp_fw_version >= 1600) && 644 (adev->gfx.mec_fw_version >= 512)) { 645 if (amdgpu_sriov_vf(adev)) 646 adev->gfx.cp_gfx_shadow = true; 647 else 648 adev->gfx.cp_gfx_shadow = false; 649 } 650 break; 651 default: 652 adev->gfx.cp_gfx_shadow = false; 653 break; 654 } 655 } 656 657 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 658 { 659 char ucode_prefix[25]; 660 int err; 661 const struct rlc_firmware_header_v2_0 *rlc_hdr; 662 uint16_t version_major; 663 uint16_t version_minor; 664 665 DRM_DEBUG("\n"); 666 667 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 668 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 669 "amdgpu/%s_pfp.bin", ucode_prefix); 670 if (err) 671 goto out; 672 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 673 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 674 (union amdgpu_firmware_header *) 675 adev->gfx.pfp_fw->data, 2, 0); 676 if (adev->gfx.rs64_enable) { 677 dev_info(adev->dev, "CP RS64 enable\n"); 678 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 679 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 680 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 681 } else { 682 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 683 } 684 685 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 686 "amdgpu/%s_me.bin", ucode_prefix); 687 if (err) 688 goto out; 689 if (adev->gfx.rs64_enable) { 690 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 691 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 692 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 693 } else { 694 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 695 } 696 697 if (!amdgpu_sriov_vf(adev)) { 698 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 699 adev->pdev->revision == 0xCE) 700 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 701 "amdgpu/gc_11_0_0_rlc_1.bin"); 702 else 703 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 704 "amdgpu/%s_rlc.bin", ucode_prefix); 705 if (err) 706 goto out; 707 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 708 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 709 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 710 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 711 if (err) 712 goto out; 713 } 714 715 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 716 "amdgpu/%s_mec.bin", ucode_prefix); 717 if (err) 718 goto out; 719 if (adev->gfx.rs64_enable) { 720 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 721 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 722 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 723 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 724 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 725 } else { 726 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 727 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 728 } 729 730 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 731 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 732 733 /* only one MEC for gfx 11.0.0. */ 734 adev->gfx.mec2_fw = NULL; 735 736 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 737 738 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 739 err = adev->gfx.imu.funcs->init_microcode(adev); 740 if (err) 741 DRM_ERROR("Failed to init imu firmware!\n"); 742 return err; 743 } 744 745 out: 746 if (err) { 747 amdgpu_ucode_release(&adev->gfx.pfp_fw); 748 amdgpu_ucode_release(&adev->gfx.me_fw); 749 amdgpu_ucode_release(&adev->gfx.rlc_fw); 750 amdgpu_ucode_release(&adev->gfx.mec_fw); 751 } 752 753 return err; 754 } 755 756 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 757 { 758 u32 count = 0; 759 const struct cs_section_def *sect = NULL; 760 const struct cs_extent_def *ext = NULL; 761 762 /* begin clear state */ 763 count += 2; 764 /* context control state */ 765 count += 3; 766 767 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 768 for (ext = sect->section; ext->extent != NULL; ++ext) { 769 if (sect->id == SECT_CONTEXT) 770 count += 2 + ext->reg_count; 771 else 772 return 0; 773 } 774 } 775 776 /* set PA_SC_TILE_STEERING_OVERRIDE */ 777 count += 3; 778 /* end clear state */ 779 count += 2; 780 /* clear state */ 781 count += 2; 782 783 return count; 784 } 785 786 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 787 volatile u32 *buffer) 788 { 789 u32 count = 0, i; 790 const struct cs_section_def *sect = NULL; 791 const struct cs_extent_def *ext = NULL; 792 int ctx_reg_offset; 793 794 if (adev->gfx.rlc.cs_data == NULL) 795 return; 796 if (buffer == NULL) 797 return; 798 799 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 800 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 801 802 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 803 buffer[count++] = cpu_to_le32(0x80000000); 804 buffer[count++] = cpu_to_le32(0x80000000); 805 806 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 807 for (ext = sect->section; ext->extent != NULL; ++ext) { 808 if (sect->id == SECT_CONTEXT) { 809 buffer[count++] = 810 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 811 buffer[count++] = cpu_to_le32(ext->reg_index - 812 PACKET3_SET_CONTEXT_REG_START); 813 for (i = 0; i < ext->reg_count; i++) 814 buffer[count++] = cpu_to_le32(ext->extent[i]); 815 } else { 816 return; 817 } 818 } 819 } 820 821 ctx_reg_offset = 822 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 823 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 824 buffer[count++] = cpu_to_le32(ctx_reg_offset); 825 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 826 827 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 828 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 829 830 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 831 buffer[count++] = cpu_to_le32(0); 832 } 833 834 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 835 { 836 /* clear state block */ 837 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 838 &adev->gfx.rlc.clear_state_gpu_addr, 839 (void **)&adev->gfx.rlc.cs_ptr); 840 841 /* jump table block */ 842 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 843 &adev->gfx.rlc.cp_table_gpu_addr, 844 (void **)&adev->gfx.rlc.cp_table_ptr); 845 } 846 847 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 848 { 849 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 850 851 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 852 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 853 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 854 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 855 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 856 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 857 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 858 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 859 adev->gfx.rlc.rlcg_reg_access_supported = true; 860 } 861 862 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 863 { 864 const struct cs_section_def *cs_data; 865 int r; 866 867 adev->gfx.rlc.cs_data = gfx11_cs_data; 868 869 cs_data = adev->gfx.rlc.cs_data; 870 871 if (cs_data) { 872 /* init clear state block */ 873 r = amdgpu_gfx_rlc_init_csb(adev); 874 if (r) 875 return r; 876 } 877 878 /* init spm vmid with 0xf */ 879 if (adev->gfx.rlc.funcs->update_spm_vmid) 880 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 881 882 return 0; 883 } 884 885 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 886 { 887 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 888 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 889 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 890 } 891 892 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 893 { 894 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 895 896 amdgpu_gfx_graphics_queue_acquire(adev); 897 } 898 899 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 900 { 901 int r; 902 u32 *hpd; 903 size_t mec_hpd_size; 904 905 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 906 907 /* take ownership of the relevant compute queues */ 908 amdgpu_gfx_compute_queue_acquire(adev); 909 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 910 911 if (mec_hpd_size) { 912 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 913 AMDGPU_GEM_DOMAIN_GTT, 914 &adev->gfx.mec.hpd_eop_obj, 915 &adev->gfx.mec.hpd_eop_gpu_addr, 916 (void **)&hpd); 917 if (r) { 918 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 919 gfx_v11_0_mec_fini(adev); 920 return r; 921 } 922 923 memset(hpd, 0, mec_hpd_size); 924 925 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 926 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 927 } 928 929 return 0; 930 } 931 932 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 933 { 934 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 935 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 936 (address << SQ_IND_INDEX__INDEX__SHIFT)); 937 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 938 } 939 940 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 941 uint32_t thread, uint32_t regno, 942 uint32_t num, uint32_t *out) 943 { 944 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 945 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 946 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 947 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 948 (SQ_IND_INDEX__AUTO_INCR_MASK)); 949 while (num--) 950 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 951 } 952 953 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 954 { 955 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 956 * field when performing a select_se_sh so it should be 957 * zero here */ 958 WARN_ON(simd != 0); 959 960 /* type 3 wave data */ 961 dst[(*no_fields)++] = 3; 962 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 963 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 964 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 965 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 966 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 967 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 968 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 969 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 970 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 971 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 972 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 973 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 974 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 975 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 976 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 977 } 978 979 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 980 uint32_t wave, uint32_t start, 981 uint32_t size, uint32_t *dst) 982 { 983 WARN_ON(simd != 0); 984 985 wave_read_regs( 986 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 987 dst); 988 } 989 990 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 991 uint32_t wave, uint32_t thread, 992 uint32_t start, uint32_t size, 993 uint32_t *dst) 994 { 995 wave_read_regs( 996 adev, wave, thread, 997 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 998 } 999 1000 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1001 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1002 { 1003 soc21_grbm_select(adev, me, pipe, q, vm); 1004 } 1005 1006 /* all sizes are in bytes */ 1007 #define MQD_SHADOW_BASE_SIZE 73728 1008 #define MQD_SHADOW_BASE_ALIGNMENT 256 1009 #define MQD_FWWORKAREA_SIZE 484 1010 #define MQD_FWWORKAREA_ALIGNMENT 256 1011 1012 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1013 struct amdgpu_gfx_shadow_info *shadow_info) 1014 { 1015 if (adev->gfx.cp_gfx_shadow) { 1016 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1017 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1018 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1019 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1020 return 0; 1021 } else { 1022 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1023 return -ENOTSUPP; 1024 } 1025 } 1026 1027 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1028 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1029 .select_se_sh = &gfx_v11_0_select_se_sh, 1030 .read_wave_data = &gfx_v11_0_read_wave_data, 1031 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1032 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1033 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1034 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1035 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1036 }; 1037 1038 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1039 { 1040 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1041 case IP_VERSION(11, 0, 0): 1042 case IP_VERSION(11, 0, 2): 1043 adev->gfx.config.max_hw_contexts = 8; 1044 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1045 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1046 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1047 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1048 break; 1049 case IP_VERSION(11, 0, 3): 1050 adev->gfx.ras = &gfx_v11_0_3_ras; 1051 adev->gfx.config.max_hw_contexts = 8; 1052 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1053 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1054 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1055 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1056 break; 1057 case IP_VERSION(11, 0, 1): 1058 case IP_VERSION(11, 0, 4): 1059 case IP_VERSION(11, 5, 0): 1060 case IP_VERSION(11, 5, 1): 1061 case IP_VERSION(11, 5, 2): 1062 adev->gfx.config.max_hw_contexts = 8; 1063 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1064 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1065 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1066 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1067 break; 1068 default: 1069 BUG(); 1070 break; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1077 int me, int pipe, int queue) 1078 { 1079 struct amdgpu_ring *ring; 1080 unsigned int irq_type; 1081 unsigned int hw_prio; 1082 1083 ring = &adev->gfx.gfx_ring[ring_id]; 1084 1085 ring->me = me; 1086 ring->pipe = pipe; 1087 ring->queue = queue; 1088 1089 ring->ring_obj = NULL; 1090 ring->use_doorbell = true; 1091 1092 if (!ring_id) 1093 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1094 else 1095 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1096 ring->vm_hub = AMDGPU_GFXHUB(0); 1097 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1098 1099 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1100 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1101 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1102 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1103 hw_prio, NULL); 1104 } 1105 1106 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1107 int mec, int pipe, int queue) 1108 { 1109 int r; 1110 unsigned irq_type; 1111 struct amdgpu_ring *ring; 1112 unsigned int hw_prio; 1113 1114 ring = &adev->gfx.compute_ring[ring_id]; 1115 1116 /* mec0 is me1 */ 1117 ring->me = mec + 1; 1118 ring->pipe = pipe; 1119 ring->queue = queue; 1120 1121 ring->ring_obj = NULL; 1122 ring->use_doorbell = true; 1123 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1124 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1125 + (ring_id * GFX11_MEC_HPD_SIZE); 1126 ring->vm_hub = AMDGPU_GFXHUB(0); 1127 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1128 1129 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1130 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1131 + ring->pipe; 1132 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1133 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1134 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1135 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1136 hw_prio, NULL); 1137 if (r) 1138 return r; 1139 1140 return 0; 1141 } 1142 1143 static struct { 1144 SOC21_FIRMWARE_ID id; 1145 unsigned int offset; 1146 unsigned int size; 1147 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1148 1149 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1150 { 1151 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1152 1153 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1154 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1155 rlc_autoload_info[ucode->id].id = ucode->id; 1156 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1157 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1158 1159 ucode++; 1160 } 1161 } 1162 1163 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1164 { 1165 uint32_t total_size = 0; 1166 SOC21_FIRMWARE_ID id; 1167 1168 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1169 1170 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1171 total_size += rlc_autoload_info[id].size; 1172 1173 /* In case the offset in rlc toc ucode is aligned */ 1174 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1175 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1176 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1177 1178 return total_size; 1179 } 1180 1181 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1182 { 1183 int r; 1184 uint32_t total_size; 1185 1186 total_size = gfx_v11_0_calc_toc_total_size(adev); 1187 1188 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1189 AMDGPU_GEM_DOMAIN_VRAM | 1190 AMDGPU_GEM_DOMAIN_GTT, 1191 &adev->gfx.rlc.rlc_autoload_bo, 1192 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1193 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1194 1195 if (r) { 1196 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1197 return r; 1198 } 1199 1200 return 0; 1201 } 1202 1203 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1204 SOC21_FIRMWARE_ID id, 1205 const void *fw_data, 1206 uint32_t fw_size, 1207 uint32_t *fw_autoload_mask) 1208 { 1209 uint32_t toc_offset; 1210 uint32_t toc_fw_size; 1211 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1212 1213 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1214 return; 1215 1216 toc_offset = rlc_autoload_info[id].offset; 1217 toc_fw_size = rlc_autoload_info[id].size; 1218 1219 if (fw_size == 0) 1220 fw_size = toc_fw_size; 1221 1222 if (fw_size > toc_fw_size) 1223 fw_size = toc_fw_size; 1224 1225 memcpy(ptr + toc_offset, fw_data, fw_size); 1226 1227 if (fw_size < toc_fw_size) 1228 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1229 1230 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1231 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1232 } 1233 1234 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1235 uint32_t *fw_autoload_mask) 1236 { 1237 void *data; 1238 uint32_t size; 1239 uint64_t *toc_ptr; 1240 1241 *(uint64_t *)fw_autoload_mask |= 0x1; 1242 1243 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1244 1245 data = adev->psp.toc.start_addr; 1246 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1247 1248 toc_ptr = (uint64_t *)data + size / 8 - 1; 1249 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1250 1251 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1252 data, size, fw_autoload_mask); 1253 } 1254 1255 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1256 uint32_t *fw_autoload_mask) 1257 { 1258 const __le32 *fw_data; 1259 uint32_t fw_size; 1260 const struct gfx_firmware_header_v1_0 *cp_hdr; 1261 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1262 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1263 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1264 uint16_t version_major, version_minor; 1265 1266 if (adev->gfx.rs64_enable) { 1267 /* pfp ucode */ 1268 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1269 adev->gfx.pfp_fw->data; 1270 /* instruction */ 1271 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1272 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1273 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1274 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1275 fw_data, fw_size, fw_autoload_mask); 1276 /* data */ 1277 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1278 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1279 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1280 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1281 fw_data, fw_size, fw_autoload_mask); 1282 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1283 fw_data, fw_size, fw_autoload_mask); 1284 /* me ucode */ 1285 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1286 adev->gfx.me_fw->data; 1287 /* instruction */ 1288 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1289 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1290 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1291 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1292 fw_data, fw_size, fw_autoload_mask); 1293 /* data */ 1294 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1295 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1296 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1297 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1298 fw_data, fw_size, fw_autoload_mask); 1299 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1300 fw_data, fw_size, fw_autoload_mask); 1301 /* mec ucode */ 1302 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1303 adev->gfx.mec_fw->data; 1304 /* instruction */ 1305 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1306 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1307 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1308 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1309 fw_data, fw_size, fw_autoload_mask); 1310 /* data */ 1311 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1312 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1313 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1314 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1315 fw_data, fw_size, fw_autoload_mask); 1316 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1317 fw_data, fw_size, fw_autoload_mask); 1318 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1319 fw_data, fw_size, fw_autoload_mask); 1320 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1321 fw_data, fw_size, fw_autoload_mask); 1322 } else { 1323 /* pfp ucode */ 1324 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1325 adev->gfx.pfp_fw->data; 1326 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1327 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1328 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1329 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1330 fw_data, fw_size, fw_autoload_mask); 1331 1332 /* me ucode */ 1333 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1334 adev->gfx.me_fw->data; 1335 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1336 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1337 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1338 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1339 fw_data, fw_size, fw_autoload_mask); 1340 1341 /* mec ucode */ 1342 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1343 adev->gfx.mec_fw->data; 1344 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1345 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1346 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1347 cp_hdr->jt_size * 4; 1348 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1349 fw_data, fw_size, fw_autoload_mask); 1350 } 1351 1352 /* rlc ucode */ 1353 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1354 adev->gfx.rlc_fw->data; 1355 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1356 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1357 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1358 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1359 fw_data, fw_size, fw_autoload_mask); 1360 1361 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1362 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1363 if (version_major == 2) { 1364 if (version_minor >= 2) { 1365 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1366 1367 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1368 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1369 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1370 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1371 fw_data, fw_size, fw_autoload_mask); 1372 1373 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1374 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1375 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1376 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1377 fw_data, fw_size, fw_autoload_mask); 1378 } 1379 } 1380 } 1381 1382 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1383 uint32_t *fw_autoload_mask) 1384 { 1385 const __le32 *fw_data; 1386 uint32_t fw_size; 1387 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1388 1389 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1390 adev->sdma.instance[0].fw->data; 1391 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1392 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1393 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1394 1395 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1396 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1397 1398 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1399 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1400 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1401 1402 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1403 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1404 } 1405 1406 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1407 uint32_t *fw_autoload_mask) 1408 { 1409 const __le32 *fw_data; 1410 unsigned fw_size; 1411 const struct mes_firmware_header_v1_0 *mes_hdr; 1412 int pipe, ucode_id, data_id; 1413 1414 for (pipe = 0; pipe < 2; pipe++) { 1415 if (pipe==0) { 1416 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1417 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1418 } else { 1419 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1420 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1421 } 1422 1423 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1424 adev->mes.fw[pipe]->data; 1425 1426 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1427 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1428 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1429 1430 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1431 ucode_id, fw_data, fw_size, fw_autoload_mask); 1432 1433 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1434 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1435 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1436 1437 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1438 data_id, fw_data, fw_size, fw_autoload_mask); 1439 } 1440 } 1441 1442 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1443 { 1444 uint32_t rlc_g_offset, rlc_g_size; 1445 uint64_t gpu_addr; 1446 uint32_t autoload_fw_id[2]; 1447 1448 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1449 1450 /* RLC autoload sequence 2: copy ucode */ 1451 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1452 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1453 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1454 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1455 1456 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1457 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1458 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1459 1460 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1461 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1462 1463 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1464 1465 /* RLC autoload sequence 3: load IMU fw */ 1466 if (adev->gfx.imu.funcs->load_microcode) 1467 adev->gfx.imu.funcs->load_microcode(adev); 1468 /* RLC autoload sequence 4 init IMU fw */ 1469 if (adev->gfx.imu.funcs->setup_imu) 1470 adev->gfx.imu.funcs->setup_imu(adev); 1471 if (adev->gfx.imu.funcs->start_imu) 1472 adev->gfx.imu.funcs->start_imu(adev); 1473 1474 /* RLC autoload sequence 5 disable gpa mode */ 1475 gfx_v11_0_disable_gpa_mode(adev); 1476 1477 return 0; 1478 } 1479 1480 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1481 { 1482 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1483 uint32_t *ptr; 1484 uint32_t inst; 1485 1486 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1487 if (ptr == NULL) { 1488 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1489 adev->gfx.ip_dump_core = NULL; 1490 } else { 1491 adev->gfx.ip_dump_core = ptr; 1492 } 1493 1494 /* Allocate memory for compute queue registers for all the instances */ 1495 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1496 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1497 adev->gfx.mec.num_queue_per_pipe; 1498 1499 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1500 if (ptr == NULL) { 1501 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1502 adev->gfx.ip_dump_compute_queues = NULL; 1503 } else { 1504 adev->gfx.ip_dump_compute_queues = ptr; 1505 } 1506 1507 /* Allocate memory for gfx queue registers for all the instances */ 1508 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1509 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1510 adev->gfx.me.num_queue_per_pipe; 1511 1512 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1513 if (ptr == NULL) { 1514 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1515 adev->gfx.ip_dump_gfx_queues = NULL; 1516 } else { 1517 adev->gfx.ip_dump_gfx_queues = ptr; 1518 } 1519 } 1520 1521 static int gfx_v11_0_sw_init(void *handle) 1522 { 1523 int i, j, k, r, ring_id = 0; 1524 int xcc_id = 0; 1525 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1526 1527 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1528 case IP_VERSION(11, 0, 0): 1529 case IP_VERSION(11, 0, 2): 1530 case IP_VERSION(11, 0, 3): 1531 adev->gfx.me.num_me = 1; 1532 adev->gfx.me.num_pipe_per_me = 1; 1533 adev->gfx.me.num_queue_per_pipe = 1; 1534 adev->gfx.mec.num_mec = 2; 1535 adev->gfx.mec.num_pipe_per_mec = 4; 1536 adev->gfx.mec.num_queue_per_pipe = 4; 1537 break; 1538 case IP_VERSION(11, 0, 1): 1539 case IP_VERSION(11, 0, 4): 1540 case IP_VERSION(11, 5, 0): 1541 case IP_VERSION(11, 5, 1): 1542 case IP_VERSION(11, 5, 2): 1543 adev->gfx.me.num_me = 1; 1544 adev->gfx.me.num_pipe_per_me = 1; 1545 adev->gfx.me.num_queue_per_pipe = 1; 1546 adev->gfx.mec.num_mec = 1; 1547 adev->gfx.mec.num_pipe_per_mec = 4; 1548 adev->gfx.mec.num_queue_per_pipe = 4; 1549 break; 1550 default: 1551 adev->gfx.me.num_me = 1; 1552 adev->gfx.me.num_pipe_per_me = 1; 1553 adev->gfx.me.num_queue_per_pipe = 1; 1554 adev->gfx.mec.num_mec = 1; 1555 adev->gfx.mec.num_pipe_per_mec = 4; 1556 adev->gfx.mec.num_queue_per_pipe = 8; 1557 break; 1558 } 1559 1560 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1561 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1562 amdgpu_sriov_is_pp_one_vf(adev)) 1563 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1564 1565 /* EOP Event */ 1566 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1567 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1568 &adev->gfx.eop_irq); 1569 if (r) 1570 return r; 1571 1572 /* Bad opcode Event */ 1573 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1574 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1575 &adev->gfx.bad_op_irq); 1576 if (r) 1577 return r; 1578 1579 /* Privileged reg */ 1580 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1581 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1582 &adev->gfx.priv_reg_irq); 1583 if (r) 1584 return r; 1585 1586 /* Privileged inst */ 1587 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1588 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1589 &adev->gfx.priv_inst_irq); 1590 if (r) 1591 return r; 1592 1593 /* FED error */ 1594 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1595 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1596 &adev->gfx.rlc_gc_fed_irq); 1597 if (r) 1598 return r; 1599 1600 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1601 1602 gfx_v11_0_me_init(adev); 1603 1604 r = gfx_v11_0_rlc_init(adev); 1605 if (r) { 1606 DRM_ERROR("Failed to init rlc BOs!\n"); 1607 return r; 1608 } 1609 1610 r = gfx_v11_0_mec_init(adev); 1611 if (r) { 1612 DRM_ERROR("Failed to init MEC BOs!\n"); 1613 return r; 1614 } 1615 1616 /* set up the gfx ring */ 1617 for (i = 0; i < adev->gfx.me.num_me; i++) { 1618 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1619 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1620 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1621 continue; 1622 1623 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1624 i, k, j); 1625 if (r) 1626 return r; 1627 ring_id++; 1628 } 1629 } 1630 } 1631 1632 ring_id = 0; 1633 /* set up the compute queues - allocate horizontally across pipes */ 1634 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1635 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1636 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1637 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1638 k, j)) 1639 continue; 1640 1641 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1642 i, k, j); 1643 if (r) 1644 return r; 1645 1646 ring_id++; 1647 } 1648 } 1649 } 1650 1651 if (!adev->enable_mes_kiq) { 1652 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1653 if (r) { 1654 DRM_ERROR("Failed to init KIQ BOs!\n"); 1655 return r; 1656 } 1657 1658 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1659 if (r) 1660 return r; 1661 } 1662 1663 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1664 if (r) 1665 return r; 1666 1667 /* allocate visible FB for rlc auto-loading fw */ 1668 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1669 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1670 if (r) 1671 return r; 1672 } 1673 1674 r = gfx_v11_0_gpu_early_init(adev); 1675 if (r) 1676 return r; 1677 1678 if (amdgpu_gfx_ras_sw_init(adev)) { 1679 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1680 return -EINVAL; 1681 } 1682 1683 gfx_v11_0_alloc_ip_dump(adev); 1684 1685 return 0; 1686 } 1687 1688 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1689 { 1690 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1691 &adev->gfx.pfp.pfp_fw_gpu_addr, 1692 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1693 1694 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1695 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1696 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1697 } 1698 1699 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1700 { 1701 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1702 &adev->gfx.me.me_fw_gpu_addr, 1703 (void **)&adev->gfx.me.me_fw_ptr); 1704 1705 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1706 &adev->gfx.me.me_fw_data_gpu_addr, 1707 (void **)&adev->gfx.me.me_fw_data_ptr); 1708 } 1709 1710 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1711 { 1712 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1713 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1714 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1715 } 1716 1717 static int gfx_v11_0_sw_fini(void *handle) 1718 { 1719 int i; 1720 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1721 1722 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1723 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1724 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1725 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1726 1727 amdgpu_gfx_mqd_sw_fini(adev, 0); 1728 1729 if (!adev->enable_mes_kiq) { 1730 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1731 amdgpu_gfx_kiq_fini(adev, 0); 1732 } 1733 1734 gfx_v11_0_pfp_fini(adev); 1735 gfx_v11_0_me_fini(adev); 1736 gfx_v11_0_rlc_fini(adev); 1737 gfx_v11_0_mec_fini(adev); 1738 1739 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1740 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1741 1742 gfx_v11_0_free_microcode(adev); 1743 1744 kfree(adev->gfx.ip_dump_core); 1745 kfree(adev->gfx.ip_dump_compute_queues); 1746 kfree(adev->gfx.ip_dump_gfx_queues); 1747 1748 return 0; 1749 } 1750 1751 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1752 u32 sh_num, u32 instance, int xcc_id) 1753 { 1754 u32 data; 1755 1756 if (instance == 0xffffffff) 1757 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1758 INSTANCE_BROADCAST_WRITES, 1); 1759 else 1760 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1761 instance); 1762 1763 if (se_num == 0xffffffff) 1764 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1765 1); 1766 else 1767 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1768 1769 if (sh_num == 0xffffffff) 1770 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1771 1); 1772 else 1773 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1774 1775 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1776 } 1777 1778 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1779 { 1780 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1781 1782 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1783 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1784 CC_GC_SA_UNIT_DISABLE, 1785 SA_DISABLE); 1786 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1787 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1788 GC_USER_SA_UNIT_DISABLE, 1789 SA_DISABLE); 1790 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1791 adev->gfx.config.max_shader_engines); 1792 1793 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1794 } 1795 1796 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1797 { 1798 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1799 u32 rb_mask; 1800 1801 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1802 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1803 CC_RB_BACKEND_DISABLE, 1804 BACKEND_DISABLE); 1805 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1806 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1807 GC_USER_RB_BACKEND_DISABLE, 1808 BACKEND_DISABLE); 1809 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1810 adev->gfx.config.max_shader_engines); 1811 1812 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1813 } 1814 1815 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1816 { 1817 u32 rb_bitmap_width_per_sa; 1818 u32 max_sa; 1819 u32 active_sa_bitmap; 1820 u32 global_active_rb_bitmap; 1821 u32 active_rb_bitmap = 0; 1822 u32 i; 1823 1824 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1825 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1826 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1827 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1828 1829 /* generate active rb bitmap according to active sa bitmap */ 1830 max_sa = adev->gfx.config.max_shader_engines * 1831 adev->gfx.config.max_sh_per_se; 1832 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1833 adev->gfx.config.max_sh_per_se; 1834 for (i = 0; i < max_sa; i++) { 1835 if (active_sa_bitmap & (1 << i)) 1836 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1837 } 1838 1839 active_rb_bitmap &= global_active_rb_bitmap; 1840 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1841 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1842 } 1843 1844 #define DEFAULT_SH_MEM_BASES (0x6000) 1845 #define LDS_APP_BASE 0x1 1846 #define SCRATCH_APP_BASE 0x2 1847 1848 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1849 { 1850 int i; 1851 uint32_t sh_mem_bases; 1852 uint32_t data; 1853 1854 /* 1855 * Configure apertures: 1856 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1857 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1858 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1859 */ 1860 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1861 SCRATCH_APP_BASE; 1862 1863 mutex_lock(&adev->srbm_mutex); 1864 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1865 soc21_grbm_select(adev, 0, 0, 0, i); 1866 /* CP and shaders */ 1867 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1868 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1869 1870 /* Enable trap for each kfd vmid. */ 1871 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1872 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1873 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1874 } 1875 soc21_grbm_select(adev, 0, 0, 0, 0); 1876 mutex_unlock(&adev->srbm_mutex); 1877 1878 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1879 acccess. These should be enabled by FW for target VMIDs. */ 1880 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1881 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1882 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1883 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1884 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1885 } 1886 } 1887 1888 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1889 { 1890 int vmid; 1891 1892 /* 1893 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1894 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1895 * the driver can enable them for graphics. VMID0 should maintain 1896 * access so that HWS firmware can save/restore entries. 1897 */ 1898 for (vmid = 1; vmid < 16; vmid++) { 1899 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1900 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1901 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1902 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1903 } 1904 } 1905 1906 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1907 { 1908 /* TODO: harvest feature to be added later. */ 1909 } 1910 1911 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1912 { 1913 /* TCCs are global (not instanced). */ 1914 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1915 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1916 1917 adev->gfx.config.tcc_disabled_mask = 1918 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1919 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1920 } 1921 1922 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1923 { 1924 u32 tmp; 1925 int i; 1926 1927 if (!amdgpu_sriov_vf(adev)) 1928 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1929 1930 gfx_v11_0_setup_rb(adev); 1931 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1932 gfx_v11_0_get_tcc_info(adev); 1933 adev->gfx.config.pa_sc_tile_steering_override = 0; 1934 1935 /* Set whether texture coordinate truncation is conformant. */ 1936 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1937 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1938 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1939 1940 /* XXX SH_MEM regs */ 1941 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1942 mutex_lock(&adev->srbm_mutex); 1943 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1944 soc21_grbm_select(adev, 0, 0, 0, i); 1945 /* CP and shaders */ 1946 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1947 if (i != 0) { 1948 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1949 (adev->gmc.private_aperture_start >> 48)); 1950 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1951 (adev->gmc.shared_aperture_start >> 48)); 1952 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1953 } 1954 } 1955 soc21_grbm_select(adev, 0, 0, 0, 0); 1956 1957 mutex_unlock(&adev->srbm_mutex); 1958 1959 gfx_v11_0_init_compute_vmid(adev); 1960 gfx_v11_0_init_gds_vmid(adev); 1961 } 1962 1963 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1964 int me, int pipe) 1965 { 1966 if (me != 0) 1967 return 0; 1968 1969 switch (pipe) { 1970 case 0: 1971 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1972 case 1: 1973 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 1974 default: 1975 return 0; 1976 } 1977 } 1978 1979 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1980 int me, int pipe) 1981 { 1982 /* 1983 * amdgpu controls only the first MEC. That's why this function only 1984 * handles the setting of interrupts for this specific MEC. All other 1985 * pipes' interrupts are set by amdkfd. 1986 */ 1987 if (me != 1) 1988 return 0; 1989 1990 switch (pipe) { 1991 case 0: 1992 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1993 case 1: 1994 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1995 case 2: 1996 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 1997 case 3: 1998 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 1999 default: 2000 return 0; 2001 } 2002 } 2003 2004 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2005 bool enable) 2006 { 2007 u32 tmp, cp_int_cntl_reg; 2008 int i, j; 2009 2010 if (amdgpu_sriov_vf(adev)) 2011 return; 2012 2013 for (i = 0; i < adev->gfx.me.num_me; i++) { 2014 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2015 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2016 2017 if (cp_int_cntl_reg) { 2018 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2019 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2020 enable ? 1 : 0); 2021 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2022 enable ? 1 : 0); 2023 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2024 enable ? 1 : 0); 2025 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2026 enable ? 1 : 0); 2027 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2028 } 2029 } 2030 } 2031 } 2032 2033 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2034 { 2035 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2036 2037 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2038 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2039 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2040 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2041 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2042 2043 return 0; 2044 } 2045 2046 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2047 { 2048 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2049 2050 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2051 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2052 } 2053 2054 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2055 { 2056 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2057 udelay(50); 2058 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2059 udelay(50); 2060 } 2061 2062 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2063 bool enable) 2064 { 2065 uint32_t rlc_pg_cntl; 2066 2067 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2068 2069 if (!enable) { 2070 /* RLC_PG_CNTL[23] = 0 (default) 2071 * RLC will wait for handshake acks with SMU 2072 * GFXOFF will be enabled 2073 * RLC_PG_CNTL[23] = 1 2074 * RLC will not issue any message to SMU 2075 * hence no handshake between SMU & RLC 2076 * GFXOFF will be disabled 2077 */ 2078 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2079 } else 2080 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2081 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2082 } 2083 2084 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2085 { 2086 /* TODO: enable rlc & smu handshake until smu 2087 * and gfxoff feature works as expected */ 2088 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2089 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2090 2091 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2092 udelay(50); 2093 } 2094 2095 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2096 { 2097 uint32_t tmp; 2098 2099 /* enable Save Restore Machine */ 2100 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2101 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2102 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2103 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2104 } 2105 2106 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2107 { 2108 const struct rlc_firmware_header_v2_0 *hdr; 2109 const __le32 *fw_data; 2110 unsigned i, fw_size; 2111 2112 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2113 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2114 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2115 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2116 2117 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2118 RLCG_UCODE_LOADING_START_ADDRESS); 2119 2120 for (i = 0; i < fw_size; i++) 2121 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2122 le32_to_cpup(fw_data++)); 2123 2124 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2125 } 2126 2127 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2128 { 2129 const struct rlc_firmware_header_v2_2 *hdr; 2130 const __le32 *fw_data; 2131 unsigned i, fw_size; 2132 u32 tmp; 2133 2134 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2135 2136 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2137 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2138 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2139 2140 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2141 2142 for (i = 0; i < fw_size; i++) { 2143 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2144 msleep(1); 2145 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2146 le32_to_cpup(fw_data++)); 2147 } 2148 2149 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2150 2151 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2152 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2153 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2154 2155 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2156 for (i = 0; i < fw_size; i++) { 2157 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2158 msleep(1); 2159 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2160 le32_to_cpup(fw_data++)); 2161 } 2162 2163 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2164 2165 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2166 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2167 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2168 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2169 } 2170 2171 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2172 { 2173 const struct rlc_firmware_header_v2_3 *hdr; 2174 const __le32 *fw_data; 2175 unsigned i, fw_size; 2176 u32 tmp; 2177 2178 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2179 2180 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2181 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2182 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2183 2184 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2185 2186 for (i = 0; i < fw_size; i++) { 2187 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2188 msleep(1); 2189 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2190 le32_to_cpup(fw_data++)); 2191 } 2192 2193 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2194 2195 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2196 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2197 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2198 2199 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2200 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2201 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2202 2203 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2204 2205 for (i = 0; i < fw_size; i++) { 2206 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2207 msleep(1); 2208 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2209 le32_to_cpup(fw_data++)); 2210 } 2211 2212 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2213 2214 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2215 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2216 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2217 } 2218 2219 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2220 { 2221 const struct rlc_firmware_header_v2_0 *hdr; 2222 uint16_t version_major; 2223 uint16_t version_minor; 2224 2225 if (!adev->gfx.rlc_fw) 2226 return -EINVAL; 2227 2228 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2229 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2230 2231 version_major = le16_to_cpu(hdr->header.header_version_major); 2232 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2233 2234 if (version_major == 2) { 2235 gfx_v11_0_load_rlcg_microcode(adev); 2236 if (amdgpu_dpm == 1) { 2237 if (version_minor >= 2) 2238 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2239 if (version_minor == 3) 2240 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2241 } 2242 2243 return 0; 2244 } 2245 2246 return -EINVAL; 2247 } 2248 2249 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2250 { 2251 int r; 2252 2253 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2254 gfx_v11_0_init_csb(adev); 2255 2256 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2257 gfx_v11_0_rlc_enable_srm(adev); 2258 } else { 2259 if (amdgpu_sriov_vf(adev)) { 2260 gfx_v11_0_init_csb(adev); 2261 return 0; 2262 } 2263 2264 adev->gfx.rlc.funcs->stop(adev); 2265 2266 /* disable CG */ 2267 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2268 2269 /* disable PG */ 2270 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2271 2272 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2273 /* legacy rlc firmware loading */ 2274 r = gfx_v11_0_rlc_load_microcode(adev); 2275 if (r) 2276 return r; 2277 } 2278 2279 gfx_v11_0_init_csb(adev); 2280 2281 adev->gfx.rlc.funcs->start(adev); 2282 } 2283 return 0; 2284 } 2285 2286 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2287 { 2288 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2289 uint32_t tmp; 2290 int i; 2291 2292 /* Trigger an invalidation of the L1 instruction caches */ 2293 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2294 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2295 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2296 2297 /* Wait for invalidation complete */ 2298 for (i = 0; i < usec_timeout; i++) { 2299 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2300 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2301 INVALIDATE_CACHE_COMPLETE)) 2302 break; 2303 udelay(1); 2304 } 2305 2306 if (i >= usec_timeout) { 2307 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2308 return -EINVAL; 2309 } 2310 2311 if (amdgpu_emu_mode == 1) 2312 adev->hdp.funcs->flush_hdp(adev, NULL); 2313 2314 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2315 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2316 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2317 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2318 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2319 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2320 2321 /* Program me ucode address into intruction cache address register */ 2322 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2323 lower_32_bits(addr) & 0xFFFFF000); 2324 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2325 upper_32_bits(addr)); 2326 2327 return 0; 2328 } 2329 2330 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2331 { 2332 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2333 uint32_t tmp; 2334 int i; 2335 2336 /* Trigger an invalidation of the L1 instruction caches */ 2337 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2338 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2339 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2340 2341 /* Wait for invalidation complete */ 2342 for (i = 0; i < usec_timeout; i++) { 2343 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2344 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2345 INVALIDATE_CACHE_COMPLETE)) 2346 break; 2347 udelay(1); 2348 } 2349 2350 if (i >= usec_timeout) { 2351 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2352 return -EINVAL; 2353 } 2354 2355 if (amdgpu_emu_mode == 1) 2356 adev->hdp.funcs->flush_hdp(adev, NULL); 2357 2358 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2359 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2360 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2361 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2362 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2363 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2364 2365 /* Program pfp ucode address into intruction cache address register */ 2366 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2367 lower_32_bits(addr) & 0xFFFFF000); 2368 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2369 upper_32_bits(addr)); 2370 2371 return 0; 2372 } 2373 2374 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2375 { 2376 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2377 uint32_t tmp; 2378 int i; 2379 2380 /* Trigger an invalidation of the L1 instruction caches */ 2381 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2382 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2383 2384 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2385 2386 /* Wait for invalidation complete */ 2387 for (i = 0; i < usec_timeout; i++) { 2388 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2389 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2390 INVALIDATE_CACHE_COMPLETE)) 2391 break; 2392 udelay(1); 2393 } 2394 2395 if (i >= usec_timeout) { 2396 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2397 return -EINVAL; 2398 } 2399 2400 if (amdgpu_emu_mode == 1) 2401 adev->hdp.funcs->flush_hdp(adev, NULL); 2402 2403 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2404 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2405 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2406 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2407 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2408 2409 /* Program mec1 ucode address into intruction cache address register */ 2410 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2411 lower_32_bits(addr) & 0xFFFFF000); 2412 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2413 upper_32_bits(addr)); 2414 2415 return 0; 2416 } 2417 2418 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2419 { 2420 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2421 uint32_t tmp; 2422 unsigned i, pipe_id; 2423 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2424 2425 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2426 adev->gfx.pfp_fw->data; 2427 2428 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2429 lower_32_bits(addr)); 2430 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2431 upper_32_bits(addr)); 2432 2433 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2434 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2435 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2436 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2437 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2438 2439 /* 2440 * Programming any of the CP_PFP_IC_BASE registers 2441 * forces invalidation of the ME L1 I$. Wait for the 2442 * invalidation complete 2443 */ 2444 for (i = 0; i < usec_timeout; i++) { 2445 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2446 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2447 INVALIDATE_CACHE_COMPLETE)) 2448 break; 2449 udelay(1); 2450 } 2451 2452 if (i >= usec_timeout) { 2453 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2454 return -EINVAL; 2455 } 2456 2457 /* Prime the L1 instruction caches */ 2458 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2459 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2460 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2461 /* Waiting for cache primed*/ 2462 for (i = 0; i < usec_timeout; i++) { 2463 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2464 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2465 ICACHE_PRIMED)) 2466 break; 2467 udelay(1); 2468 } 2469 2470 if (i >= usec_timeout) { 2471 dev_err(adev->dev, "failed to prime instruction cache\n"); 2472 return -EINVAL; 2473 } 2474 2475 mutex_lock(&adev->srbm_mutex); 2476 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2477 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2478 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2479 (pfp_hdr->ucode_start_addr_hi << 30) | 2480 (pfp_hdr->ucode_start_addr_lo >> 2)); 2481 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2482 pfp_hdr->ucode_start_addr_hi >> 2); 2483 2484 /* 2485 * Program CP_ME_CNTL to reset given PIPE to take 2486 * effect of CP_PFP_PRGRM_CNTR_START. 2487 */ 2488 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2489 if (pipe_id == 0) 2490 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2491 PFP_PIPE0_RESET, 1); 2492 else 2493 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2494 PFP_PIPE1_RESET, 1); 2495 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2496 2497 /* Clear pfp pipe0 reset bit. */ 2498 if (pipe_id == 0) 2499 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2500 PFP_PIPE0_RESET, 0); 2501 else 2502 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2503 PFP_PIPE1_RESET, 0); 2504 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2505 2506 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2507 lower_32_bits(addr2)); 2508 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2509 upper_32_bits(addr2)); 2510 } 2511 soc21_grbm_select(adev, 0, 0, 0, 0); 2512 mutex_unlock(&adev->srbm_mutex); 2513 2514 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2515 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2516 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2517 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2518 2519 /* Invalidate the data caches */ 2520 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2521 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2522 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2523 2524 for (i = 0; i < usec_timeout; i++) { 2525 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2526 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2527 INVALIDATE_DCACHE_COMPLETE)) 2528 break; 2529 udelay(1); 2530 } 2531 2532 if (i >= usec_timeout) { 2533 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2534 return -EINVAL; 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2541 { 2542 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2543 uint32_t tmp; 2544 unsigned i, pipe_id; 2545 const struct gfx_firmware_header_v2_0 *me_hdr; 2546 2547 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2548 adev->gfx.me_fw->data; 2549 2550 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2551 lower_32_bits(addr)); 2552 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2553 upper_32_bits(addr)); 2554 2555 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2557 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2558 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2559 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2560 2561 /* 2562 * Programming any of the CP_ME_IC_BASE registers 2563 * forces invalidation of the ME L1 I$. Wait for the 2564 * invalidation complete 2565 */ 2566 for (i = 0; i < usec_timeout; i++) { 2567 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2568 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2569 INVALIDATE_CACHE_COMPLETE)) 2570 break; 2571 udelay(1); 2572 } 2573 2574 if (i >= usec_timeout) { 2575 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2576 return -EINVAL; 2577 } 2578 2579 /* Prime the instruction caches */ 2580 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2581 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2582 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2583 2584 /* Waiting for instruction cache primed*/ 2585 for (i = 0; i < usec_timeout; i++) { 2586 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2587 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2588 ICACHE_PRIMED)) 2589 break; 2590 udelay(1); 2591 } 2592 2593 if (i >= usec_timeout) { 2594 dev_err(adev->dev, "failed to prime instruction cache\n"); 2595 return -EINVAL; 2596 } 2597 2598 mutex_lock(&adev->srbm_mutex); 2599 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2600 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2601 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2602 (me_hdr->ucode_start_addr_hi << 30) | 2603 (me_hdr->ucode_start_addr_lo >> 2) ); 2604 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2605 me_hdr->ucode_start_addr_hi>>2); 2606 2607 /* 2608 * Program CP_ME_CNTL to reset given PIPE to take 2609 * effect of CP_PFP_PRGRM_CNTR_START. 2610 */ 2611 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2612 if (pipe_id == 0) 2613 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2614 ME_PIPE0_RESET, 1); 2615 else 2616 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2617 ME_PIPE1_RESET, 1); 2618 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2619 2620 /* Clear pfp pipe0 reset bit. */ 2621 if (pipe_id == 0) 2622 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2623 ME_PIPE0_RESET, 0); 2624 else 2625 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2626 ME_PIPE1_RESET, 0); 2627 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2628 2629 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2630 lower_32_bits(addr2)); 2631 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2632 upper_32_bits(addr2)); 2633 } 2634 soc21_grbm_select(adev, 0, 0, 0, 0); 2635 mutex_unlock(&adev->srbm_mutex); 2636 2637 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2638 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2639 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2640 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2641 2642 /* Invalidate the data caches */ 2643 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2644 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2645 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2646 2647 for (i = 0; i < usec_timeout; i++) { 2648 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2649 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2650 INVALIDATE_DCACHE_COMPLETE)) 2651 break; 2652 udelay(1); 2653 } 2654 2655 if (i >= usec_timeout) { 2656 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2657 return -EINVAL; 2658 } 2659 2660 return 0; 2661 } 2662 2663 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2664 { 2665 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2666 uint32_t tmp; 2667 unsigned i; 2668 const struct gfx_firmware_header_v2_0 *mec_hdr; 2669 2670 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2671 adev->gfx.mec_fw->data; 2672 2673 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2674 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2675 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2676 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2677 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2678 2679 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2680 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2681 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2682 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2683 2684 mutex_lock(&adev->srbm_mutex); 2685 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2686 soc21_grbm_select(adev, 1, i, 0, 0); 2687 2688 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2689 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2690 upper_32_bits(addr2)); 2691 2692 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2693 mec_hdr->ucode_start_addr_lo >> 2 | 2694 mec_hdr->ucode_start_addr_hi << 30); 2695 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2696 mec_hdr->ucode_start_addr_hi >> 2); 2697 2698 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2699 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2700 upper_32_bits(addr)); 2701 } 2702 mutex_unlock(&adev->srbm_mutex); 2703 soc21_grbm_select(adev, 0, 0, 0, 0); 2704 2705 /* Trigger an invalidation of the L1 instruction caches */ 2706 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2707 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2708 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2709 2710 /* Wait for invalidation complete */ 2711 for (i = 0; i < usec_timeout; i++) { 2712 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2713 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2714 INVALIDATE_DCACHE_COMPLETE)) 2715 break; 2716 udelay(1); 2717 } 2718 2719 if (i >= usec_timeout) { 2720 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2721 return -EINVAL; 2722 } 2723 2724 /* Trigger an invalidation of the L1 instruction caches */ 2725 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2726 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2727 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2728 2729 /* Wait for invalidation complete */ 2730 for (i = 0; i < usec_timeout; i++) { 2731 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2732 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2733 INVALIDATE_CACHE_COMPLETE)) 2734 break; 2735 udelay(1); 2736 } 2737 2738 if (i >= usec_timeout) { 2739 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2740 return -EINVAL; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2747 { 2748 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2749 const struct gfx_firmware_header_v2_0 *me_hdr; 2750 const struct gfx_firmware_header_v2_0 *mec_hdr; 2751 uint32_t pipe_id, tmp; 2752 2753 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2754 adev->gfx.mec_fw->data; 2755 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2756 adev->gfx.me_fw->data; 2757 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2758 adev->gfx.pfp_fw->data; 2759 2760 /* config pfp program start addr */ 2761 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2762 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2763 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2764 (pfp_hdr->ucode_start_addr_hi << 30) | 2765 (pfp_hdr->ucode_start_addr_lo >> 2)); 2766 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2767 pfp_hdr->ucode_start_addr_hi >> 2); 2768 } 2769 soc21_grbm_select(adev, 0, 0, 0, 0); 2770 2771 /* reset pfp pipe */ 2772 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2773 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2774 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2775 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2776 2777 /* clear pfp pipe reset */ 2778 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2779 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2780 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2781 2782 /* config me program start addr */ 2783 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2784 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2785 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2786 (me_hdr->ucode_start_addr_hi << 30) | 2787 (me_hdr->ucode_start_addr_lo >> 2) ); 2788 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2789 me_hdr->ucode_start_addr_hi>>2); 2790 } 2791 soc21_grbm_select(adev, 0, 0, 0, 0); 2792 2793 /* reset me pipe */ 2794 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2795 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2796 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2797 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2798 2799 /* clear me pipe reset */ 2800 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2801 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2802 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2803 2804 /* config mec program start addr */ 2805 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2806 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2807 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2808 mec_hdr->ucode_start_addr_lo >> 2 | 2809 mec_hdr->ucode_start_addr_hi << 30); 2810 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2811 mec_hdr->ucode_start_addr_hi >> 2); 2812 } 2813 soc21_grbm_select(adev, 0, 0, 0, 0); 2814 2815 /* reset mec pipe */ 2816 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2817 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2818 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2819 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2820 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2821 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2822 2823 /* clear mec pipe reset */ 2824 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2825 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2826 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2827 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2828 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2829 } 2830 2831 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2832 { 2833 uint32_t cp_status; 2834 uint32_t bootload_status; 2835 int i, r; 2836 uint64_t addr, addr2; 2837 2838 for (i = 0; i < adev->usec_timeout; i++) { 2839 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2840 2841 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2842 IP_VERSION(11, 0, 1) || 2843 amdgpu_ip_version(adev, GC_HWIP, 0) == 2844 IP_VERSION(11, 0, 4) || 2845 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 2846 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 2847 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2)) 2848 bootload_status = RREG32_SOC15(GC, 0, 2849 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2850 else 2851 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2852 2853 if ((cp_status == 0) && 2854 (REG_GET_FIELD(bootload_status, 2855 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2856 break; 2857 } 2858 udelay(1); 2859 } 2860 2861 if (i >= adev->usec_timeout) { 2862 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2863 return -ETIMEDOUT; 2864 } 2865 2866 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2867 if (adev->gfx.rs64_enable) { 2868 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2869 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2870 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2871 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2872 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2873 if (r) 2874 return r; 2875 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2876 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2877 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2878 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2879 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2880 if (r) 2881 return r; 2882 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2883 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2884 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2885 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2886 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2887 if (r) 2888 return r; 2889 } else { 2890 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2891 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2892 r = gfx_v11_0_config_me_cache(adev, addr); 2893 if (r) 2894 return r; 2895 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2896 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2897 r = gfx_v11_0_config_pfp_cache(adev, addr); 2898 if (r) 2899 return r; 2900 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2901 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2902 r = gfx_v11_0_config_mec_cache(adev, addr); 2903 if (r) 2904 return r; 2905 } 2906 } 2907 2908 return 0; 2909 } 2910 2911 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2912 { 2913 int i; 2914 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2915 2916 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2917 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2918 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2919 2920 for (i = 0; i < adev->usec_timeout; i++) { 2921 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2922 break; 2923 udelay(1); 2924 } 2925 2926 if (i >= adev->usec_timeout) 2927 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2928 2929 return 0; 2930 } 2931 2932 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2933 { 2934 int r; 2935 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2936 const __le32 *fw_data; 2937 unsigned i, fw_size; 2938 2939 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2940 adev->gfx.pfp_fw->data; 2941 2942 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2943 2944 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2945 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2946 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2947 2948 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2949 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2950 &adev->gfx.pfp.pfp_fw_obj, 2951 &adev->gfx.pfp.pfp_fw_gpu_addr, 2952 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2953 if (r) { 2954 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2955 gfx_v11_0_pfp_fini(adev); 2956 return r; 2957 } 2958 2959 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2960 2961 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2962 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2963 2964 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2965 2966 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2967 2968 for (i = 0; i < pfp_hdr->jt_size; i++) 2969 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2970 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2971 2972 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2973 2974 return 0; 2975 } 2976 2977 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2978 { 2979 int r; 2980 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2981 const __le32 *fw_ucode, *fw_data; 2982 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2983 uint32_t tmp; 2984 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2985 2986 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2987 adev->gfx.pfp_fw->data; 2988 2989 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2990 2991 /* instruction */ 2992 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2993 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2994 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2995 /* data */ 2996 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2997 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2998 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2999 3000 /* 64kb align */ 3001 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3002 64 * 1024, 3003 AMDGPU_GEM_DOMAIN_VRAM | 3004 AMDGPU_GEM_DOMAIN_GTT, 3005 &adev->gfx.pfp.pfp_fw_obj, 3006 &adev->gfx.pfp.pfp_fw_gpu_addr, 3007 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3008 if (r) { 3009 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3010 gfx_v11_0_pfp_fini(adev); 3011 return r; 3012 } 3013 3014 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3015 64 * 1024, 3016 AMDGPU_GEM_DOMAIN_VRAM | 3017 AMDGPU_GEM_DOMAIN_GTT, 3018 &adev->gfx.pfp.pfp_fw_data_obj, 3019 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3020 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3021 if (r) { 3022 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3023 gfx_v11_0_pfp_fini(adev); 3024 return r; 3025 } 3026 3027 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3028 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3029 3030 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3031 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3032 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3033 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3034 3035 if (amdgpu_emu_mode == 1) 3036 adev->hdp.funcs->flush_hdp(adev, NULL); 3037 3038 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3039 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3040 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3041 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3042 3043 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3044 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3045 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3046 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3047 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3048 3049 /* 3050 * Programming any of the CP_PFP_IC_BASE registers 3051 * forces invalidation of the ME L1 I$. Wait for the 3052 * invalidation complete 3053 */ 3054 for (i = 0; i < usec_timeout; i++) { 3055 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3056 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3057 INVALIDATE_CACHE_COMPLETE)) 3058 break; 3059 udelay(1); 3060 } 3061 3062 if (i >= usec_timeout) { 3063 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3064 return -EINVAL; 3065 } 3066 3067 /* Prime the L1 instruction caches */ 3068 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3069 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3070 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3071 /* Waiting for cache primed*/ 3072 for (i = 0; i < usec_timeout; i++) { 3073 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3074 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3075 ICACHE_PRIMED)) 3076 break; 3077 udelay(1); 3078 } 3079 3080 if (i >= usec_timeout) { 3081 dev_err(adev->dev, "failed to prime instruction cache\n"); 3082 return -EINVAL; 3083 } 3084 3085 mutex_lock(&adev->srbm_mutex); 3086 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3087 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3088 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3089 (pfp_hdr->ucode_start_addr_hi << 30) | 3090 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3091 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3092 pfp_hdr->ucode_start_addr_hi>>2); 3093 3094 /* 3095 * Program CP_ME_CNTL to reset given PIPE to take 3096 * effect of CP_PFP_PRGRM_CNTR_START. 3097 */ 3098 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3099 if (pipe_id == 0) 3100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3101 PFP_PIPE0_RESET, 1); 3102 else 3103 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3104 PFP_PIPE1_RESET, 1); 3105 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3106 3107 /* Clear pfp pipe0 reset bit. */ 3108 if (pipe_id == 0) 3109 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3110 PFP_PIPE0_RESET, 0); 3111 else 3112 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3113 PFP_PIPE1_RESET, 0); 3114 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3115 3116 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3117 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3118 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3119 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3120 } 3121 soc21_grbm_select(adev, 0, 0, 0, 0); 3122 mutex_unlock(&adev->srbm_mutex); 3123 3124 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3125 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3126 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3127 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3128 3129 /* Invalidate the data caches */ 3130 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3131 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3132 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3133 3134 for (i = 0; i < usec_timeout; i++) { 3135 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3136 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3137 INVALIDATE_DCACHE_COMPLETE)) 3138 break; 3139 udelay(1); 3140 } 3141 3142 if (i >= usec_timeout) { 3143 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3144 return -EINVAL; 3145 } 3146 3147 return 0; 3148 } 3149 3150 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3151 { 3152 int r; 3153 const struct gfx_firmware_header_v1_0 *me_hdr; 3154 const __le32 *fw_data; 3155 unsigned i, fw_size; 3156 3157 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3158 adev->gfx.me_fw->data; 3159 3160 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3161 3162 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3163 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3164 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3165 3166 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3167 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3168 &adev->gfx.me.me_fw_obj, 3169 &adev->gfx.me.me_fw_gpu_addr, 3170 (void **)&adev->gfx.me.me_fw_ptr); 3171 if (r) { 3172 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3173 gfx_v11_0_me_fini(adev); 3174 return r; 3175 } 3176 3177 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3178 3179 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3180 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3181 3182 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3183 3184 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3185 3186 for (i = 0; i < me_hdr->jt_size; i++) 3187 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3188 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3189 3190 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3191 3192 return 0; 3193 } 3194 3195 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3196 { 3197 int r; 3198 const struct gfx_firmware_header_v2_0 *me_hdr; 3199 const __le32 *fw_ucode, *fw_data; 3200 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3201 uint32_t tmp; 3202 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3203 3204 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3205 adev->gfx.me_fw->data; 3206 3207 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3208 3209 /* instruction */ 3210 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3211 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3212 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3213 /* data */ 3214 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3215 le32_to_cpu(me_hdr->data_offset_bytes)); 3216 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3217 3218 /* 64kb align*/ 3219 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3220 64 * 1024, 3221 AMDGPU_GEM_DOMAIN_VRAM | 3222 AMDGPU_GEM_DOMAIN_GTT, 3223 &adev->gfx.me.me_fw_obj, 3224 &adev->gfx.me.me_fw_gpu_addr, 3225 (void **)&adev->gfx.me.me_fw_ptr); 3226 if (r) { 3227 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3228 gfx_v11_0_me_fini(adev); 3229 return r; 3230 } 3231 3232 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3233 64 * 1024, 3234 AMDGPU_GEM_DOMAIN_VRAM | 3235 AMDGPU_GEM_DOMAIN_GTT, 3236 &adev->gfx.me.me_fw_data_obj, 3237 &adev->gfx.me.me_fw_data_gpu_addr, 3238 (void **)&adev->gfx.me.me_fw_data_ptr); 3239 if (r) { 3240 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3241 gfx_v11_0_pfp_fini(adev); 3242 return r; 3243 } 3244 3245 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3246 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3247 3248 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3249 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3250 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3251 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3252 3253 if (amdgpu_emu_mode == 1) 3254 adev->hdp.funcs->flush_hdp(adev, NULL); 3255 3256 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3257 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3258 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3259 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3260 3261 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3262 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3263 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3264 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3265 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3266 3267 /* 3268 * Programming any of the CP_ME_IC_BASE registers 3269 * forces invalidation of the ME L1 I$. Wait for the 3270 * invalidation complete 3271 */ 3272 for (i = 0; i < usec_timeout; i++) { 3273 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3274 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3275 INVALIDATE_CACHE_COMPLETE)) 3276 break; 3277 udelay(1); 3278 } 3279 3280 if (i >= usec_timeout) { 3281 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3282 return -EINVAL; 3283 } 3284 3285 /* Prime the instruction caches */ 3286 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3287 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3288 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3289 3290 /* Waiting for instruction cache primed*/ 3291 for (i = 0; i < usec_timeout; i++) { 3292 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3293 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3294 ICACHE_PRIMED)) 3295 break; 3296 udelay(1); 3297 } 3298 3299 if (i >= usec_timeout) { 3300 dev_err(adev->dev, "failed to prime instruction cache\n"); 3301 return -EINVAL; 3302 } 3303 3304 mutex_lock(&adev->srbm_mutex); 3305 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3306 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3307 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3308 (me_hdr->ucode_start_addr_hi << 30) | 3309 (me_hdr->ucode_start_addr_lo >> 2) ); 3310 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3311 me_hdr->ucode_start_addr_hi>>2); 3312 3313 /* 3314 * Program CP_ME_CNTL to reset given PIPE to take 3315 * effect of CP_PFP_PRGRM_CNTR_START. 3316 */ 3317 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3318 if (pipe_id == 0) 3319 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3320 ME_PIPE0_RESET, 1); 3321 else 3322 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3323 ME_PIPE1_RESET, 1); 3324 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3325 3326 /* Clear pfp pipe0 reset bit. */ 3327 if (pipe_id == 0) 3328 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3329 ME_PIPE0_RESET, 0); 3330 else 3331 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3332 ME_PIPE1_RESET, 0); 3333 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3334 3335 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3336 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3337 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3338 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3339 } 3340 soc21_grbm_select(adev, 0, 0, 0, 0); 3341 mutex_unlock(&adev->srbm_mutex); 3342 3343 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3344 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3345 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3346 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3347 3348 /* Invalidate the data caches */ 3349 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3350 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3351 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3352 3353 for (i = 0; i < usec_timeout; i++) { 3354 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3355 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3356 INVALIDATE_DCACHE_COMPLETE)) 3357 break; 3358 udelay(1); 3359 } 3360 3361 if (i >= usec_timeout) { 3362 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3363 return -EINVAL; 3364 } 3365 3366 return 0; 3367 } 3368 3369 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3370 { 3371 int r; 3372 3373 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3374 return -EINVAL; 3375 3376 gfx_v11_0_cp_gfx_enable(adev, false); 3377 3378 if (adev->gfx.rs64_enable) 3379 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3380 else 3381 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3382 if (r) { 3383 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3384 return r; 3385 } 3386 3387 if (adev->gfx.rs64_enable) 3388 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3389 else 3390 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3391 if (r) { 3392 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3393 return r; 3394 } 3395 3396 return 0; 3397 } 3398 3399 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3400 { 3401 struct amdgpu_ring *ring; 3402 const struct cs_section_def *sect = NULL; 3403 const struct cs_extent_def *ext = NULL; 3404 int r, i; 3405 int ctx_reg_offset; 3406 3407 /* init the CP */ 3408 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3409 adev->gfx.config.max_hw_contexts - 1); 3410 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3411 3412 if (!amdgpu_async_gfx_ring) 3413 gfx_v11_0_cp_gfx_enable(adev, true); 3414 3415 ring = &adev->gfx.gfx_ring[0]; 3416 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3417 if (r) { 3418 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3419 return r; 3420 } 3421 3422 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3423 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3424 3425 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3426 amdgpu_ring_write(ring, 0x80000000); 3427 amdgpu_ring_write(ring, 0x80000000); 3428 3429 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3430 for (ext = sect->section; ext->extent != NULL; ++ext) { 3431 if (sect->id == SECT_CONTEXT) { 3432 amdgpu_ring_write(ring, 3433 PACKET3(PACKET3_SET_CONTEXT_REG, 3434 ext->reg_count)); 3435 amdgpu_ring_write(ring, ext->reg_index - 3436 PACKET3_SET_CONTEXT_REG_START); 3437 for (i = 0; i < ext->reg_count; i++) 3438 amdgpu_ring_write(ring, ext->extent[i]); 3439 } 3440 } 3441 } 3442 3443 ctx_reg_offset = 3444 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3445 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3446 amdgpu_ring_write(ring, ctx_reg_offset); 3447 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3448 3449 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3450 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3451 3452 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3453 amdgpu_ring_write(ring, 0); 3454 3455 amdgpu_ring_commit(ring); 3456 3457 /* submit cs packet to copy state 0 to next available state */ 3458 if (adev->gfx.num_gfx_rings > 1) { 3459 /* maximum supported gfx ring is 2 */ 3460 ring = &adev->gfx.gfx_ring[1]; 3461 r = amdgpu_ring_alloc(ring, 2); 3462 if (r) { 3463 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3464 return r; 3465 } 3466 3467 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3468 amdgpu_ring_write(ring, 0); 3469 3470 amdgpu_ring_commit(ring); 3471 } 3472 return 0; 3473 } 3474 3475 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3476 CP_PIPE_ID pipe) 3477 { 3478 u32 tmp; 3479 3480 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3481 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3482 3483 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3484 } 3485 3486 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3487 struct amdgpu_ring *ring) 3488 { 3489 u32 tmp; 3490 3491 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3492 if (ring->use_doorbell) { 3493 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3494 DOORBELL_OFFSET, ring->doorbell_index); 3495 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3496 DOORBELL_EN, 1); 3497 } else { 3498 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3499 DOORBELL_EN, 0); 3500 } 3501 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3502 3503 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3504 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3505 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3506 3507 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3508 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3509 } 3510 3511 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3512 { 3513 struct amdgpu_ring *ring; 3514 u32 tmp; 3515 u32 rb_bufsz; 3516 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3517 3518 /* Set the write pointer delay */ 3519 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3520 3521 /* set the RB to use vmid 0 */ 3522 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3523 3524 /* Init gfx ring 0 for pipe 0 */ 3525 mutex_lock(&adev->srbm_mutex); 3526 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3527 3528 /* Set ring buffer size */ 3529 ring = &adev->gfx.gfx_ring[0]; 3530 rb_bufsz = order_base_2(ring->ring_size / 8); 3531 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3532 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3533 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3534 3535 /* Initialize the ring buffer's write pointers */ 3536 ring->wptr = 0; 3537 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3538 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3539 3540 /* set the wb address wether it's enabled or not */ 3541 rptr_addr = ring->rptr_gpu_addr; 3542 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3543 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3544 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3545 3546 wptr_gpu_addr = ring->wptr_gpu_addr; 3547 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3548 lower_32_bits(wptr_gpu_addr)); 3549 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3550 upper_32_bits(wptr_gpu_addr)); 3551 3552 mdelay(1); 3553 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3554 3555 rb_addr = ring->gpu_addr >> 8; 3556 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3557 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3558 3559 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3560 3561 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3562 mutex_unlock(&adev->srbm_mutex); 3563 3564 /* Init gfx ring 1 for pipe 1 */ 3565 if (adev->gfx.num_gfx_rings > 1) { 3566 mutex_lock(&adev->srbm_mutex); 3567 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3568 /* maximum supported gfx ring is 2 */ 3569 ring = &adev->gfx.gfx_ring[1]; 3570 rb_bufsz = order_base_2(ring->ring_size / 8); 3571 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3572 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3573 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3574 /* Initialize the ring buffer's write pointers */ 3575 ring->wptr = 0; 3576 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3577 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3578 /* Set the wb address wether it's enabled or not */ 3579 rptr_addr = ring->rptr_gpu_addr; 3580 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3581 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3582 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3583 wptr_gpu_addr = ring->wptr_gpu_addr; 3584 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3585 lower_32_bits(wptr_gpu_addr)); 3586 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3587 upper_32_bits(wptr_gpu_addr)); 3588 3589 mdelay(1); 3590 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3591 3592 rb_addr = ring->gpu_addr >> 8; 3593 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3594 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3595 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3596 3597 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3598 mutex_unlock(&adev->srbm_mutex); 3599 } 3600 /* Switch to pipe 0 */ 3601 mutex_lock(&adev->srbm_mutex); 3602 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3603 mutex_unlock(&adev->srbm_mutex); 3604 3605 /* start the ring */ 3606 gfx_v11_0_cp_gfx_start(adev); 3607 3608 return 0; 3609 } 3610 3611 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3612 { 3613 u32 data; 3614 3615 if (adev->gfx.rs64_enable) { 3616 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3617 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3618 enable ? 0 : 1); 3619 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3620 enable ? 0 : 1); 3621 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3622 enable ? 0 : 1); 3623 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3624 enable ? 0 : 1); 3625 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3626 enable ? 0 : 1); 3627 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3628 enable ? 1 : 0); 3629 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3630 enable ? 1 : 0); 3631 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3632 enable ? 1 : 0); 3633 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3634 enable ? 1 : 0); 3635 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3636 enable ? 0 : 1); 3637 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3638 } else { 3639 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3640 3641 if (enable) { 3642 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3643 if (!adev->enable_mes_kiq) 3644 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3645 MEC_ME2_HALT, 0); 3646 } else { 3647 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3648 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3649 } 3650 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3651 } 3652 3653 udelay(50); 3654 } 3655 3656 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3657 { 3658 const struct gfx_firmware_header_v1_0 *mec_hdr; 3659 const __le32 *fw_data; 3660 unsigned i, fw_size; 3661 u32 *fw = NULL; 3662 int r; 3663 3664 if (!adev->gfx.mec_fw) 3665 return -EINVAL; 3666 3667 gfx_v11_0_cp_compute_enable(adev, false); 3668 3669 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3670 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3671 3672 fw_data = (const __le32 *) 3673 (adev->gfx.mec_fw->data + 3674 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3675 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3676 3677 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3678 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3679 &adev->gfx.mec.mec_fw_obj, 3680 &adev->gfx.mec.mec_fw_gpu_addr, 3681 (void **)&fw); 3682 if (r) { 3683 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3684 gfx_v11_0_mec_fini(adev); 3685 return r; 3686 } 3687 3688 memcpy(fw, fw_data, fw_size); 3689 3690 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3691 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3692 3693 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3694 3695 /* MEC1 */ 3696 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3697 3698 for (i = 0; i < mec_hdr->jt_size; i++) 3699 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3700 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3701 3702 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3703 3704 return 0; 3705 } 3706 3707 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3708 { 3709 const struct gfx_firmware_header_v2_0 *mec_hdr; 3710 const __le32 *fw_ucode, *fw_data; 3711 u32 tmp, fw_ucode_size, fw_data_size; 3712 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3713 u32 *fw_ucode_ptr, *fw_data_ptr; 3714 int r; 3715 3716 if (!adev->gfx.mec_fw) 3717 return -EINVAL; 3718 3719 gfx_v11_0_cp_compute_enable(adev, false); 3720 3721 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3722 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3723 3724 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3725 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3726 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3727 3728 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3729 le32_to_cpu(mec_hdr->data_offset_bytes)); 3730 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3731 3732 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3733 64 * 1024, 3734 AMDGPU_GEM_DOMAIN_VRAM | 3735 AMDGPU_GEM_DOMAIN_GTT, 3736 &adev->gfx.mec.mec_fw_obj, 3737 &adev->gfx.mec.mec_fw_gpu_addr, 3738 (void **)&fw_ucode_ptr); 3739 if (r) { 3740 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3741 gfx_v11_0_mec_fini(adev); 3742 return r; 3743 } 3744 3745 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3746 64 * 1024, 3747 AMDGPU_GEM_DOMAIN_VRAM | 3748 AMDGPU_GEM_DOMAIN_GTT, 3749 &adev->gfx.mec.mec_fw_data_obj, 3750 &adev->gfx.mec.mec_fw_data_gpu_addr, 3751 (void **)&fw_data_ptr); 3752 if (r) { 3753 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3754 gfx_v11_0_mec_fini(adev); 3755 return r; 3756 } 3757 3758 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3759 memcpy(fw_data_ptr, fw_data, fw_data_size); 3760 3761 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3762 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3763 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3764 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3765 3766 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3767 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3768 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3769 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3770 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3771 3772 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3773 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3774 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3775 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3776 3777 mutex_lock(&adev->srbm_mutex); 3778 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3779 soc21_grbm_select(adev, 1, i, 0, 0); 3780 3781 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3782 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3783 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3784 3785 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3786 mec_hdr->ucode_start_addr_lo >> 2 | 3787 mec_hdr->ucode_start_addr_hi << 30); 3788 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3789 mec_hdr->ucode_start_addr_hi >> 2); 3790 3791 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3792 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3793 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3794 } 3795 mutex_unlock(&adev->srbm_mutex); 3796 soc21_grbm_select(adev, 0, 0, 0, 0); 3797 3798 /* Trigger an invalidation of the L1 instruction caches */ 3799 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3800 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3801 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3802 3803 /* Wait for invalidation complete */ 3804 for (i = 0; i < usec_timeout; i++) { 3805 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3806 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3807 INVALIDATE_DCACHE_COMPLETE)) 3808 break; 3809 udelay(1); 3810 } 3811 3812 if (i >= usec_timeout) { 3813 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3814 return -EINVAL; 3815 } 3816 3817 /* Trigger an invalidation of the L1 instruction caches */ 3818 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3819 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3820 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3821 3822 /* Wait for invalidation complete */ 3823 for (i = 0; i < usec_timeout; i++) { 3824 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3825 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3826 INVALIDATE_CACHE_COMPLETE)) 3827 break; 3828 udelay(1); 3829 } 3830 3831 if (i >= usec_timeout) { 3832 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3833 return -EINVAL; 3834 } 3835 3836 return 0; 3837 } 3838 3839 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3840 { 3841 uint32_t tmp; 3842 struct amdgpu_device *adev = ring->adev; 3843 3844 /* tell RLC which is KIQ queue */ 3845 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3846 tmp &= 0xffffff00; 3847 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3848 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3849 tmp |= 0x80; 3850 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3851 } 3852 3853 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3854 { 3855 /* set graphics engine doorbell range */ 3856 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3857 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3858 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3859 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3860 3861 /* set compute engine doorbell range */ 3862 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3863 (adev->doorbell_index.kiq * 2) << 2); 3864 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3865 (adev->doorbell_index.userqueue_end * 2) << 2); 3866 } 3867 3868 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 3869 struct v11_gfx_mqd *mqd, 3870 struct amdgpu_mqd_prop *prop) 3871 { 3872 bool priority = 0; 3873 u32 tmp; 3874 3875 /* set up default queue priority level 3876 * 0x0 = low priority, 0x1 = high priority 3877 */ 3878 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 3879 priority = 1; 3880 3881 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3882 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 3883 mqd->cp_gfx_hqd_queue_priority = tmp; 3884 } 3885 3886 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3887 struct amdgpu_mqd_prop *prop) 3888 { 3889 struct v11_gfx_mqd *mqd = m; 3890 uint64_t hqd_gpu_addr, wb_gpu_addr; 3891 uint32_t tmp; 3892 uint32_t rb_bufsz; 3893 3894 /* set up gfx hqd wptr */ 3895 mqd->cp_gfx_hqd_wptr = 0; 3896 mqd->cp_gfx_hqd_wptr_hi = 0; 3897 3898 /* set the pointer to the MQD */ 3899 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3900 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3901 3902 /* set up mqd control */ 3903 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3904 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3905 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3906 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3907 mqd->cp_gfx_mqd_control = tmp; 3908 3909 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3910 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3911 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3912 mqd->cp_gfx_hqd_vmid = 0; 3913 3914 /* set up gfx queue priority */ 3915 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 3916 3917 /* set up time quantum */ 3918 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3919 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3920 mqd->cp_gfx_hqd_quantum = tmp; 3921 3922 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3923 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3924 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3925 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3926 3927 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3928 wb_gpu_addr = prop->rptr_gpu_addr; 3929 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3930 mqd->cp_gfx_hqd_rptr_addr_hi = 3931 upper_32_bits(wb_gpu_addr) & 0xffff; 3932 3933 /* set up rb_wptr_poll addr */ 3934 wb_gpu_addr = prop->wptr_gpu_addr; 3935 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3936 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3937 3938 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3939 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3940 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3941 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3942 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3943 #ifdef __BIG_ENDIAN 3944 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3945 #endif 3946 mqd->cp_gfx_hqd_cntl = tmp; 3947 3948 /* set up cp_doorbell_control */ 3949 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3950 if (prop->use_doorbell) { 3951 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3952 DOORBELL_OFFSET, prop->doorbell_index); 3953 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3954 DOORBELL_EN, 1); 3955 } else 3956 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3957 DOORBELL_EN, 0); 3958 mqd->cp_rb_doorbell_control = tmp; 3959 3960 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3961 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3962 3963 /* active the queue */ 3964 mqd->cp_gfx_hqd_active = 1; 3965 3966 return 0; 3967 } 3968 3969 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3970 { 3971 struct amdgpu_device *adev = ring->adev; 3972 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3973 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3974 3975 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3976 memset((void *)mqd, 0, sizeof(*mqd)); 3977 mutex_lock(&adev->srbm_mutex); 3978 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3979 amdgpu_ring_init_mqd(ring); 3980 soc21_grbm_select(adev, 0, 0, 0, 0); 3981 mutex_unlock(&adev->srbm_mutex); 3982 if (adev->gfx.me.mqd_backup[mqd_idx]) 3983 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3984 } else { 3985 /* restore mqd with the backup copy */ 3986 if (adev->gfx.me.mqd_backup[mqd_idx]) 3987 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3988 /* reset the ring */ 3989 ring->wptr = 0; 3990 *ring->wptr_cpu_addr = 0; 3991 amdgpu_ring_clear_ring(ring); 3992 } 3993 3994 return 0; 3995 } 3996 3997 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3998 { 3999 int r, i; 4000 struct amdgpu_ring *ring; 4001 4002 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4003 ring = &adev->gfx.gfx_ring[i]; 4004 4005 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4006 if (unlikely(r != 0)) 4007 return r; 4008 4009 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4010 if (!r) { 4011 r = gfx_v11_0_gfx_init_queue(ring); 4012 amdgpu_bo_kunmap(ring->mqd_obj); 4013 ring->mqd_ptr = NULL; 4014 } 4015 amdgpu_bo_unreserve(ring->mqd_obj); 4016 if (r) 4017 return r; 4018 } 4019 4020 r = amdgpu_gfx_enable_kgq(adev, 0); 4021 if (r) 4022 return r; 4023 4024 return gfx_v11_0_cp_gfx_start(adev); 4025 } 4026 4027 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4028 struct amdgpu_mqd_prop *prop) 4029 { 4030 struct v11_compute_mqd *mqd = m; 4031 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4032 uint32_t tmp; 4033 4034 mqd->header = 0xC0310800; 4035 mqd->compute_pipelinestat_enable = 0x00000001; 4036 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4037 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4038 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4039 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4040 mqd->compute_misc_reserved = 0x00000007; 4041 4042 eop_base_addr = prop->eop_gpu_addr >> 8; 4043 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4044 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4045 4046 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4047 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4048 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4049 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4050 4051 mqd->cp_hqd_eop_control = tmp; 4052 4053 /* enable doorbell? */ 4054 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4055 4056 if (prop->use_doorbell) { 4057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4058 DOORBELL_OFFSET, prop->doorbell_index); 4059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4060 DOORBELL_EN, 1); 4061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4062 DOORBELL_SOURCE, 0); 4063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4064 DOORBELL_HIT, 0); 4065 } else { 4066 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4067 DOORBELL_EN, 0); 4068 } 4069 4070 mqd->cp_hqd_pq_doorbell_control = tmp; 4071 4072 /* disable the queue if it's active */ 4073 mqd->cp_hqd_dequeue_request = 0; 4074 mqd->cp_hqd_pq_rptr = 0; 4075 mqd->cp_hqd_pq_wptr_lo = 0; 4076 mqd->cp_hqd_pq_wptr_hi = 0; 4077 4078 /* set the pointer to the MQD */ 4079 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4080 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4081 4082 /* set MQD vmid to 0 */ 4083 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4084 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4085 mqd->cp_mqd_control = tmp; 4086 4087 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4088 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4089 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4090 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4091 4092 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4093 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4094 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4095 (order_base_2(prop->queue_size / 4) - 1)); 4096 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4097 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4098 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4100 prop->allow_tunneling); 4101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4102 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4103 mqd->cp_hqd_pq_control = tmp; 4104 4105 /* set the wb address whether it's enabled or not */ 4106 wb_gpu_addr = prop->rptr_gpu_addr; 4107 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4108 mqd->cp_hqd_pq_rptr_report_addr_hi = 4109 upper_32_bits(wb_gpu_addr) & 0xffff; 4110 4111 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4112 wb_gpu_addr = prop->wptr_gpu_addr; 4113 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4114 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4115 4116 tmp = 0; 4117 /* enable the doorbell if requested */ 4118 if (prop->use_doorbell) { 4119 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4120 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4121 DOORBELL_OFFSET, prop->doorbell_index); 4122 4123 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4124 DOORBELL_EN, 1); 4125 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4126 DOORBELL_SOURCE, 0); 4127 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4128 DOORBELL_HIT, 0); 4129 } 4130 4131 mqd->cp_hqd_pq_doorbell_control = tmp; 4132 4133 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4134 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4135 4136 /* set the vmid for the queue */ 4137 mqd->cp_hqd_vmid = 0; 4138 4139 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4140 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4141 mqd->cp_hqd_persistent_state = tmp; 4142 4143 /* set MIN_IB_AVAIL_SIZE */ 4144 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4145 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4146 mqd->cp_hqd_ib_control = tmp; 4147 4148 /* set static priority for a compute queue/ring */ 4149 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4150 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4151 4152 mqd->cp_hqd_active = prop->hqd_active; 4153 4154 return 0; 4155 } 4156 4157 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4158 { 4159 struct amdgpu_device *adev = ring->adev; 4160 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4161 int j; 4162 4163 /* inactivate the queue */ 4164 if (amdgpu_sriov_vf(adev)) 4165 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4166 4167 /* disable wptr polling */ 4168 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4169 4170 /* write the EOP addr */ 4171 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4172 mqd->cp_hqd_eop_base_addr_lo); 4173 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4174 mqd->cp_hqd_eop_base_addr_hi); 4175 4176 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4177 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4178 mqd->cp_hqd_eop_control); 4179 4180 /* enable doorbell? */ 4181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4182 mqd->cp_hqd_pq_doorbell_control); 4183 4184 /* disable the queue if it's active */ 4185 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4186 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4187 for (j = 0; j < adev->usec_timeout; j++) { 4188 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4189 break; 4190 udelay(1); 4191 } 4192 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4193 mqd->cp_hqd_dequeue_request); 4194 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4195 mqd->cp_hqd_pq_rptr); 4196 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4197 mqd->cp_hqd_pq_wptr_lo); 4198 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4199 mqd->cp_hqd_pq_wptr_hi); 4200 } 4201 4202 /* set the pointer to the MQD */ 4203 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4204 mqd->cp_mqd_base_addr_lo); 4205 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4206 mqd->cp_mqd_base_addr_hi); 4207 4208 /* set MQD vmid to 0 */ 4209 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4210 mqd->cp_mqd_control); 4211 4212 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4213 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4214 mqd->cp_hqd_pq_base_lo); 4215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4216 mqd->cp_hqd_pq_base_hi); 4217 4218 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4220 mqd->cp_hqd_pq_control); 4221 4222 /* set the wb address whether it's enabled or not */ 4223 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4224 mqd->cp_hqd_pq_rptr_report_addr_lo); 4225 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4226 mqd->cp_hqd_pq_rptr_report_addr_hi); 4227 4228 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4229 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4230 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4231 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4232 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4233 4234 /* enable the doorbell if requested */ 4235 if (ring->use_doorbell) { 4236 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4237 (adev->doorbell_index.kiq * 2) << 2); 4238 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4239 (adev->doorbell_index.userqueue_end * 2) << 2); 4240 } 4241 4242 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4243 mqd->cp_hqd_pq_doorbell_control); 4244 4245 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4246 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4247 mqd->cp_hqd_pq_wptr_lo); 4248 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4249 mqd->cp_hqd_pq_wptr_hi); 4250 4251 /* set the vmid for the queue */ 4252 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4253 4254 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4255 mqd->cp_hqd_persistent_state); 4256 4257 /* activate the queue */ 4258 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4259 mqd->cp_hqd_active); 4260 4261 if (ring->use_doorbell) 4262 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4263 4264 return 0; 4265 } 4266 4267 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4268 { 4269 struct amdgpu_device *adev = ring->adev; 4270 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4271 4272 gfx_v11_0_kiq_setting(ring); 4273 4274 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4275 /* reset MQD to a clean status */ 4276 if (adev->gfx.kiq[0].mqd_backup) 4277 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4278 4279 /* reset ring buffer */ 4280 ring->wptr = 0; 4281 amdgpu_ring_clear_ring(ring); 4282 4283 mutex_lock(&adev->srbm_mutex); 4284 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4285 gfx_v11_0_kiq_init_register(ring); 4286 soc21_grbm_select(adev, 0, 0, 0, 0); 4287 mutex_unlock(&adev->srbm_mutex); 4288 } else { 4289 memset((void *)mqd, 0, sizeof(*mqd)); 4290 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4291 amdgpu_ring_clear_ring(ring); 4292 mutex_lock(&adev->srbm_mutex); 4293 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4294 amdgpu_ring_init_mqd(ring); 4295 gfx_v11_0_kiq_init_register(ring); 4296 soc21_grbm_select(adev, 0, 0, 0, 0); 4297 mutex_unlock(&adev->srbm_mutex); 4298 4299 if (adev->gfx.kiq[0].mqd_backup) 4300 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4301 } 4302 4303 return 0; 4304 } 4305 4306 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4307 { 4308 struct amdgpu_device *adev = ring->adev; 4309 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4310 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4311 4312 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4313 memset((void *)mqd, 0, sizeof(*mqd)); 4314 mutex_lock(&adev->srbm_mutex); 4315 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4316 amdgpu_ring_init_mqd(ring); 4317 soc21_grbm_select(adev, 0, 0, 0, 0); 4318 mutex_unlock(&adev->srbm_mutex); 4319 4320 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4321 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4322 } else { 4323 /* restore MQD to a clean status */ 4324 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4325 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4326 /* reset ring buffer */ 4327 ring->wptr = 0; 4328 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4329 amdgpu_ring_clear_ring(ring); 4330 } 4331 4332 return 0; 4333 } 4334 4335 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4336 { 4337 struct amdgpu_ring *ring; 4338 int r; 4339 4340 ring = &adev->gfx.kiq[0].ring; 4341 4342 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4343 if (unlikely(r != 0)) 4344 return r; 4345 4346 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4347 if (unlikely(r != 0)) { 4348 amdgpu_bo_unreserve(ring->mqd_obj); 4349 return r; 4350 } 4351 4352 gfx_v11_0_kiq_init_queue(ring); 4353 amdgpu_bo_kunmap(ring->mqd_obj); 4354 ring->mqd_ptr = NULL; 4355 amdgpu_bo_unreserve(ring->mqd_obj); 4356 ring->sched.ready = true; 4357 return 0; 4358 } 4359 4360 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4361 { 4362 struct amdgpu_ring *ring = NULL; 4363 int r = 0, i; 4364 4365 if (!amdgpu_async_gfx_ring) 4366 gfx_v11_0_cp_compute_enable(adev, true); 4367 4368 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4369 ring = &adev->gfx.compute_ring[i]; 4370 4371 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4372 if (unlikely(r != 0)) 4373 goto done; 4374 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4375 if (!r) { 4376 r = gfx_v11_0_kcq_init_queue(ring); 4377 amdgpu_bo_kunmap(ring->mqd_obj); 4378 ring->mqd_ptr = NULL; 4379 } 4380 amdgpu_bo_unreserve(ring->mqd_obj); 4381 if (r) 4382 goto done; 4383 } 4384 4385 r = amdgpu_gfx_enable_kcq(adev, 0); 4386 done: 4387 return r; 4388 } 4389 4390 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4391 { 4392 int r, i; 4393 struct amdgpu_ring *ring; 4394 4395 if (!(adev->flags & AMD_IS_APU)) 4396 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4397 4398 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4399 /* legacy firmware loading */ 4400 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4401 if (r) 4402 return r; 4403 4404 if (adev->gfx.rs64_enable) 4405 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4406 else 4407 r = gfx_v11_0_cp_compute_load_microcode(adev); 4408 if (r) 4409 return r; 4410 } 4411 4412 gfx_v11_0_cp_set_doorbell_range(adev); 4413 4414 if (amdgpu_async_gfx_ring) { 4415 gfx_v11_0_cp_compute_enable(adev, true); 4416 gfx_v11_0_cp_gfx_enable(adev, true); 4417 } 4418 4419 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4420 r = amdgpu_mes_kiq_hw_init(adev); 4421 else 4422 r = gfx_v11_0_kiq_resume(adev); 4423 if (r) 4424 return r; 4425 4426 r = gfx_v11_0_kcq_resume(adev); 4427 if (r) 4428 return r; 4429 4430 if (!amdgpu_async_gfx_ring) { 4431 r = gfx_v11_0_cp_gfx_resume(adev); 4432 if (r) 4433 return r; 4434 } else { 4435 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4436 if (r) 4437 return r; 4438 } 4439 4440 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4441 ring = &adev->gfx.gfx_ring[i]; 4442 r = amdgpu_ring_test_helper(ring); 4443 if (r) 4444 return r; 4445 } 4446 4447 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4448 ring = &adev->gfx.compute_ring[i]; 4449 r = amdgpu_ring_test_helper(ring); 4450 if (r) 4451 return r; 4452 } 4453 4454 return 0; 4455 } 4456 4457 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4458 { 4459 gfx_v11_0_cp_gfx_enable(adev, enable); 4460 gfx_v11_0_cp_compute_enable(adev, enable); 4461 } 4462 4463 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4464 { 4465 int r; 4466 bool value; 4467 4468 r = adev->gfxhub.funcs->gart_enable(adev); 4469 if (r) 4470 return r; 4471 4472 adev->hdp.funcs->flush_hdp(adev, NULL); 4473 4474 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4475 false : true; 4476 4477 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4478 /* TODO investigate why this and the hdp flush above is needed, 4479 * are we missing a flush somewhere else? */ 4480 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4481 4482 return 0; 4483 } 4484 4485 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4486 { 4487 u32 tmp; 4488 4489 /* select RS64 */ 4490 if (adev->gfx.rs64_enable) { 4491 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4492 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4493 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4494 4495 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4496 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4497 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4498 } 4499 4500 if (amdgpu_emu_mode == 1) 4501 msleep(100); 4502 } 4503 4504 static int get_gb_addr_config(struct amdgpu_device * adev) 4505 { 4506 u32 gb_addr_config; 4507 4508 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4509 if (gb_addr_config == 0) 4510 return -EINVAL; 4511 4512 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4513 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4514 4515 adev->gfx.config.gb_addr_config = gb_addr_config; 4516 4517 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4518 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4519 GB_ADDR_CONFIG, NUM_PIPES); 4520 4521 adev->gfx.config.max_tile_pipes = 4522 adev->gfx.config.gb_addr_config_fields.num_pipes; 4523 4524 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4525 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4526 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4527 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4528 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4529 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4530 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4531 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4532 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4533 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4534 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4535 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4536 4537 return 0; 4538 } 4539 4540 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4541 { 4542 uint32_t data; 4543 4544 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4545 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4546 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4547 4548 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4549 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4550 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4551 } 4552 4553 static int gfx_v11_0_hw_init(void *handle) 4554 { 4555 int r; 4556 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4557 4558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4559 if (adev->gfx.imu.funcs) { 4560 /* RLC autoload sequence 1: Program rlc ram */ 4561 if (adev->gfx.imu.funcs->program_rlc_ram) 4562 adev->gfx.imu.funcs->program_rlc_ram(adev); 4563 /* rlc autoload firmware */ 4564 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4565 if (r) 4566 return r; 4567 } 4568 } else { 4569 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4570 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4571 if (adev->gfx.imu.funcs->load_microcode) 4572 adev->gfx.imu.funcs->load_microcode(adev); 4573 if (adev->gfx.imu.funcs->setup_imu) 4574 adev->gfx.imu.funcs->setup_imu(adev); 4575 if (adev->gfx.imu.funcs->start_imu) 4576 adev->gfx.imu.funcs->start_imu(adev); 4577 } 4578 4579 /* disable gpa mode in backdoor loading */ 4580 gfx_v11_0_disable_gpa_mode(adev); 4581 } 4582 } 4583 4584 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4585 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4586 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4587 if (r) { 4588 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4589 return r; 4590 } 4591 } 4592 4593 adev->gfx.is_poweron = true; 4594 4595 if(get_gb_addr_config(adev)) 4596 DRM_WARN("Invalid gb_addr_config !\n"); 4597 4598 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4599 adev->gfx.rs64_enable) 4600 gfx_v11_0_config_gfx_rs64(adev); 4601 4602 r = gfx_v11_0_gfxhub_enable(adev); 4603 if (r) 4604 return r; 4605 4606 if (!amdgpu_emu_mode) 4607 gfx_v11_0_init_golden_registers(adev); 4608 4609 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4610 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4611 /** 4612 * For gfx 11, rlc firmware loading relies on smu firmware is 4613 * loaded firstly, so in direct type, it has to load smc ucode 4614 * here before rlc. 4615 */ 4616 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4617 if (r) 4618 return r; 4619 } 4620 4621 gfx_v11_0_constants_init(adev); 4622 4623 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4624 gfx_v11_0_select_cp_fw_arch(adev); 4625 4626 if (adev->nbio.funcs->gc_doorbell_init) 4627 adev->nbio.funcs->gc_doorbell_init(adev); 4628 4629 r = gfx_v11_0_rlc_resume(adev); 4630 if (r) 4631 return r; 4632 4633 /* 4634 * init golden registers and rlc resume may override some registers, 4635 * reconfig them here 4636 */ 4637 gfx_v11_0_tcp_harvest(adev); 4638 4639 r = gfx_v11_0_cp_resume(adev); 4640 if (r) 4641 return r; 4642 4643 /* get IMU version from HW if it's not set */ 4644 if (!adev->gfx.imu_fw_version) 4645 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4646 4647 return r; 4648 } 4649 4650 static int gfx_v11_0_hw_fini(void *handle) 4651 { 4652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4653 4654 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4655 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4656 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4657 4658 if (!adev->no_hw_access) { 4659 if (amdgpu_async_gfx_ring) { 4660 if (amdgpu_gfx_disable_kgq(adev, 0)) 4661 DRM_ERROR("KGQ disable failed\n"); 4662 } 4663 4664 if (amdgpu_gfx_disable_kcq(adev, 0)) 4665 DRM_ERROR("KCQ disable failed\n"); 4666 4667 amdgpu_mes_kiq_hw_fini(adev); 4668 } 4669 4670 if (amdgpu_sriov_vf(adev)) 4671 /* Remove the steps disabling CPG and clearing KIQ position, 4672 * so that CP could perform IDLE-SAVE during switch. Those 4673 * steps are necessary to avoid a DMAR error in gfx9 but it is 4674 * not reproduced on gfx11. 4675 */ 4676 return 0; 4677 4678 gfx_v11_0_cp_enable(adev, false); 4679 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4680 4681 adev->gfxhub.funcs->gart_disable(adev); 4682 4683 adev->gfx.is_poweron = false; 4684 4685 return 0; 4686 } 4687 4688 static int gfx_v11_0_suspend(void *handle) 4689 { 4690 return gfx_v11_0_hw_fini(handle); 4691 } 4692 4693 static int gfx_v11_0_resume(void *handle) 4694 { 4695 return gfx_v11_0_hw_init(handle); 4696 } 4697 4698 static bool gfx_v11_0_is_idle(void *handle) 4699 { 4700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4701 4702 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4703 GRBM_STATUS, GUI_ACTIVE)) 4704 return false; 4705 else 4706 return true; 4707 } 4708 4709 static int gfx_v11_0_wait_for_idle(void *handle) 4710 { 4711 unsigned i; 4712 u32 tmp; 4713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4714 4715 for (i = 0; i < adev->usec_timeout; i++) { 4716 /* read MC_STATUS */ 4717 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4718 GRBM_STATUS__GUI_ACTIVE_MASK; 4719 4720 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4721 return 0; 4722 udelay(1); 4723 } 4724 return -ETIMEDOUT; 4725 } 4726 4727 static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4728 int req) 4729 { 4730 u32 i, tmp, val; 4731 4732 for (i = 0; i < adev->usec_timeout; i++) { 4733 /* Request with MeId=2, PipeId=0 */ 4734 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4735 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4736 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4737 4738 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4739 if (req) { 4740 if (val == tmp) 4741 break; 4742 } else { 4743 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4744 REQUEST, 1); 4745 4746 /* unlocked or locked by firmware */ 4747 if (val != tmp) 4748 break; 4749 } 4750 udelay(1); 4751 } 4752 4753 if (i >= adev->usec_timeout) 4754 return -EINVAL; 4755 4756 return 0; 4757 } 4758 4759 static int gfx_v11_0_soft_reset(void *handle) 4760 { 4761 u32 grbm_soft_reset = 0; 4762 u32 tmp; 4763 int r, i, j, k; 4764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4765 4766 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4767 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4768 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4769 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4770 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4771 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4772 4773 gfx_v11_0_set_safe_mode(adev, 0); 4774 4775 mutex_lock(&adev->srbm_mutex); 4776 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4777 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4778 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4779 soc21_grbm_select(adev, i, k, j, 0); 4780 4781 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4782 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4783 } 4784 } 4785 } 4786 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4787 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4788 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4789 soc21_grbm_select(adev, i, k, j, 0); 4790 4791 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4792 } 4793 } 4794 } 4795 soc21_grbm_select(adev, 0, 0, 0, 0); 4796 mutex_unlock(&adev->srbm_mutex); 4797 4798 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4799 r = gfx_v11_0_request_gfx_index_mutex(adev, 1); 4800 if (r) { 4801 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 4802 return r; 4803 } 4804 4805 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4806 4807 // Read CP_VMID_RESET register three times. 4808 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4809 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4810 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4811 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4812 4813 /* release the gfx mutex */ 4814 r = gfx_v11_0_request_gfx_index_mutex(adev, 0); 4815 if (r) { 4816 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 4817 return r; 4818 } 4819 4820 for (i = 0; i < adev->usec_timeout; i++) { 4821 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4822 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4823 break; 4824 udelay(1); 4825 } 4826 if (i >= adev->usec_timeout) { 4827 printk("Failed to wait all pipes clean\n"); 4828 return -EINVAL; 4829 } 4830 4831 /********** trigger soft reset ***********/ 4832 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4833 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4834 SOFT_RESET_CP, 1); 4835 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4836 SOFT_RESET_GFX, 1); 4837 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4838 SOFT_RESET_CPF, 1); 4839 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4840 SOFT_RESET_CPC, 1); 4841 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4842 SOFT_RESET_CPG, 1); 4843 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4844 /********** exit soft reset ***********/ 4845 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4846 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4847 SOFT_RESET_CP, 0); 4848 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4849 SOFT_RESET_GFX, 0); 4850 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4851 SOFT_RESET_CPF, 0); 4852 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4853 SOFT_RESET_CPC, 0); 4854 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4855 SOFT_RESET_CPG, 0); 4856 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4857 4858 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4859 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4860 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4861 4862 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4863 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4864 4865 for (i = 0; i < adev->usec_timeout; i++) { 4866 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4867 break; 4868 udelay(1); 4869 } 4870 if (i >= adev->usec_timeout) { 4871 printk("Failed to wait CP_VMID_RESET to 0\n"); 4872 return -EINVAL; 4873 } 4874 4875 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4876 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4877 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4878 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4879 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4880 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4881 4882 gfx_v11_0_unset_safe_mode(adev, 0); 4883 4884 return gfx_v11_0_cp_resume(adev); 4885 } 4886 4887 static bool gfx_v11_0_check_soft_reset(void *handle) 4888 { 4889 int i, r; 4890 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4891 struct amdgpu_ring *ring; 4892 long tmo = msecs_to_jiffies(1000); 4893 4894 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4895 ring = &adev->gfx.gfx_ring[i]; 4896 r = amdgpu_ring_test_ib(ring, tmo); 4897 if (r) 4898 return true; 4899 } 4900 4901 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4902 ring = &adev->gfx.compute_ring[i]; 4903 r = amdgpu_ring_test_ib(ring, tmo); 4904 if (r) 4905 return true; 4906 } 4907 4908 return false; 4909 } 4910 4911 static int gfx_v11_0_post_soft_reset(void *handle) 4912 { 4913 /** 4914 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4915 */ 4916 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4917 } 4918 4919 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4920 { 4921 uint64_t clock; 4922 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4923 4924 if (amdgpu_sriov_vf(adev)) { 4925 amdgpu_gfx_off_ctrl(adev, false); 4926 mutex_lock(&adev->gfx.gpu_clock_mutex); 4927 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4928 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4929 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4930 if (clock_counter_hi_pre != clock_counter_hi_after) 4931 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4932 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4933 amdgpu_gfx_off_ctrl(adev, true); 4934 } else { 4935 preempt_disable(); 4936 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4937 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4938 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4939 if (clock_counter_hi_pre != clock_counter_hi_after) 4940 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4941 preempt_enable(); 4942 } 4943 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4944 4945 return clock; 4946 } 4947 4948 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4949 uint32_t vmid, 4950 uint32_t gds_base, uint32_t gds_size, 4951 uint32_t gws_base, uint32_t gws_size, 4952 uint32_t oa_base, uint32_t oa_size) 4953 { 4954 struct amdgpu_device *adev = ring->adev; 4955 4956 /* GDS Base */ 4957 gfx_v11_0_write_data_to_reg(ring, 0, false, 4958 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4959 gds_base); 4960 4961 /* GDS Size */ 4962 gfx_v11_0_write_data_to_reg(ring, 0, false, 4963 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4964 gds_size); 4965 4966 /* GWS */ 4967 gfx_v11_0_write_data_to_reg(ring, 0, false, 4968 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4969 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4970 4971 /* OA */ 4972 gfx_v11_0_write_data_to_reg(ring, 0, false, 4973 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4974 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4975 } 4976 4977 static int gfx_v11_0_early_init(void *handle) 4978 { 4979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4980 4981 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4982 4983 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4984 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4985 AMDGPU_MAX_COMPUTE_RINGS); 4986 4987 gfx_v11_0_set_kiq_pm4_funcs(adev); 4988 gfx_v11_0_set_ring_funcs(adev); 4989 gfx_v11_0_set_irq_funcs(adev); 4990 gfx_v11_0_set_gds_init(adev); 4991 gfx_v11_0_set_rlc_funcs(adev); 4992 gfx_v11_0_set_mqd_funcs(adev); 4993 gfx_v11_0_set_imu_funcs(adev); 4994 4995 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4996 4997 return gfx_v11_0_init_microcode(adev); 4998 } 4999 5000 static int gfx_v11_0_late_init(void *handle) 5001 { 5002 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5003 int r; 5004 5005 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5006 if (r) 5007 return r; 5008 5009 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5010 if (r) 5011 return r; 5012 5013 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5014 if (r) 5015 return r; 5016 return 0; 5017 } 5018 5019 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5020 { 5021 uint32_t rlc_cntl; 5022 5023 /* if RLC is not enabled, do nothing */ 5024 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5025 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5026 } 5027 5028 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5029 { 5030 uint32_t data; 5031 unsigned i; 5032 5033 data = RLC_SAFE_MODE__CMD_MASK; 5034 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5035 5036 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5037 5038 /* wait for RLC_SAFE_MODE */ 5039 for (i = 0; i < adev->usec_timeout; i++) { 5040 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5041 RLC_SAFE_MODE, CMD)) 5042 break; 5043 udelay(1); 5044 } 5045 } 5046 5047 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5048 { 5049 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5050 } 5051 5052 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5053 bool enable) 5054 { 5055 uint32_t def, data; 5056 5057 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5058 return; 5059 5060 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5061 5062 if (enable) 5063 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5064 else 5065 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5066 5067 if (def != data) 5068 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5069 } 5070 5071 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5072 bool enable) 5073 { 5074 uint32_t def, data; 5075 5076 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5077 return; 5078 5079 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5080 5081 if (enable) 5082 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5083 else 5084 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5085 5086 if (def != data) 5087 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5088 } 5089 5090 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5091 bool enable) 5092 { 5093 uint32_t def, data; 5094 5095 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5096 return; 5097 5098 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5099 5100 if (enable) 5101 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5102 else 5103 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5104 5105 if (def != data) 5106 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5107 } 5108 5109 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5110 bool enable) 5111 { 5112 uint32_t data, def; 5113 5114 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5115 return; 5116 5117 /* It is disabled by HW by default */ 5118 if (enable) { 5119 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5120 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5121 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5122 5123 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5124 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5125 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5126 5127 if (def != data) 5128 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5129 } 5130 } else { 5131 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5132 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5133 5134 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5135 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5136 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5137 5138 if (def != data) 5139 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5140 } 5141 } 5142 } 5143 5144 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5145 bool enable) 5146 { 5147 uint32_t def, data; 5148 5149 if (!(adev->cg_flags & 5150 (AMD_CG_SUPPORT_GFX_CGCG | 5151 AMD_CG_SUPPORT_GFX_CGLS | 5152 AMD_CG_SUPPORT_GFX_3D_CGCG | 5153 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5154 return; 5155 5156 if (enable) { 5157 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5158 5159 /* unset CGCG override */ 5160 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5161 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5162 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5163 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5164 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5165 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5166 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5167 5168 /* update CGCG override bits */ 5169 if (def != data) 5170 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5171 5172 /* enable cgcg FSM(0x0000363F) */ 5173 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5174 5175 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5176 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5177 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5178 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5179 } 5180 5181 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5182 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5183 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5184 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5185 } 5186 5187 if (def != data) 5188 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5189 5190 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5191 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5192 5193 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5194 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5195 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5196 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5197 } 5198 5199 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5200 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5201 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5202 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5203 } 5204 5205 if (def != data) 5206 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5207 5208 /* set IDLE_POLL_COUNT(0x00900100) */ 5209 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5210 5211 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5212 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5213 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5214 5215 if (def != data) 5216 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5217 5218 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5219 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5220 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5221 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5222 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5223 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5224 5225 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5226 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5227 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5228 5229 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5230 if (adev->sdma.num_instances > 1) { 5231 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5232 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5233 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5234 } 5235 } else { 5236 /* Program RLC_CGCG_CGLS_CTRL */ 5237 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5238 5239 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5240 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5241 5242 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5243 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5244 5245 if (def != data) 5246 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5247 5248 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5249 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5250 5251 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5252 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5253 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5254 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5255 5256 if (def != data) 5257 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5258 5259 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5260 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5261 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5262 5263 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5264 if (adev->sdma.num_instances > 1) { 5265 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5266 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5267 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5268 } 5269 } 5270 } 5271 5272 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5273 bool enable) 5274 { 5275 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5276 5277 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5278 5279 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5280 5281 gfx_v11_0_update_repeater_fgcg(adev, enable); 5282 5283 gfx_v11_0_update_sram_fgcg(adev, enable); 5284 5285 gfx_v11_0_update_perf_clk(adev, enable); 5286 5287 if (adev->cg_flags & 5288 (AMD_CG_SUPPORT_GFX_MGCG | 5289 AMD_CG_SUPPORT_GFX_CGLS | 5290 AMD_CG_SUPPORT_GFX_CGCG | 5291 AMD_CG_SUPPORT_GFX_3D_CGCG | 5292 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5293 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5294 5295 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5296 5297 return 0; 5298 } 5299 5300 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5301 { 5302 u32 reg, pre_data, data; 5303 5304 amdgpu_gfx_off_ctrl(adev, false); 5305 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5306 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5307 pre_data = RREG32_NO_KIQ(reg); 5308 else 5309 pre_data = RREG32(reg); 5310 5311 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5312 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5313 5314 if (pre_data != data) { 5315 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5316 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5317 } else 5318 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5319 } 5320 amdgpu_gfx_off_ctrl(adev, true); 5321 5322 if (ring 5323 && amdgpu_sriov_is_pp_one_vf(adev) 5324 && (pre_data != data) 5325 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5326 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5327 amdgpu_ring_emit_wreg(ring, reg, data); 5328 } 5329 } 5330 5331 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5332 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5333 .set_safe_mode = gfx_v11_0_set_safe_mode, 5334 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5335 .init = gfx_v11_0_rlc_init, 5336 .get_csb_size = gfx_v11_0_get_csb_size, 5337 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5338 .resume = gfx_v11_0_rlc_resume, 5339 .stop = gfx_v11_0_rlc_stop, 5340 .reset = gfx_v11_0_rlc_reset, 5341 .start = gfx_v11_0_rlc_start, 5342 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5343 }; 5344 5345 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5346 { 5347 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5348 5349 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5350 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5351 else 5352 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5353 5354 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5355 5356 // Program RLC_PG_DELAY3 for CGPG hysteresis 5357 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5358 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5359 case IP_VERSION(11, 0, 1): 5360 case IP_VERSION(11, 0, 4): 5361 case IP_VERSION(11, 5, 0): 5362 case IP_VERSION(11, 5, 1): 5363 case IP_VERSION(11, 5, 2): 5364 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5365 break; 5366 default: 5367 break; 5368 } 5369 } 5370 } 5371 5372 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5373 { 5374 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5375 5376 gfx_v11_cntl_power_gating(adev, enable); 5377 5378 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5379 } 5380 5381 static int gfx_v11_0_set_powergating_state(void *handle, 5382 enum amd_powergating_state state) 5383 { 5384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5385 bool enable = (state == AMD_PG_STATE_GATE); 5386 5387 if (amdgpu_sriov_vf(adev)) 5388 return 0; 5389 5390 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5391 case IP_VERSION(11, 0, 0): 5392 case IP_VERSION(11, 0, 2): 5393 case IP_VERSION(11, 0, 3): 5394 amdgpu_gfx_off_ctrl(adev, enable); 5395 break; 5396 case IP_VERSION(11, 0, 1): 5397 case IP_VERSION(11, 0, 4): 5398 case IP_VERSION(11, 5, 0): 5399 case IP_VERSION(11, 5, 1): 5400 case IP_VERSION(11, 5, 2): 5401 if (!enable) 5402 amdgpu_gfx_off_ctrl(adev, false); 5403 5404 gfx_v11_cntl_pg(adev, enable); 5405 5406 if (enable) 5407 amdgpu_gfx_off_ctrl(adev, true); 5408 5409 break; 5410 default: 5411 break; 5412 } 5413 5414 return 0; 5415 } 5416 5417 static int gfx_v11_0_set_clockgating_state(void *handle, 5418 enum amd_clockgating_state state) 5419 { 5420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5421 5422 if (amdgpu_sriov_vf(adev)) 5423 return 0; 5424 5425 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5426 case IP_VERSION(11, 0, 0): 5427 case IP_VERSION(11, 0, 1): 5428 case IP_VERSION(11, 0, 2): 5429 case IP_VERSION(11, 0, 3): 5430 case IP_VERSION(11, 0, 4): 5431 case IP_VERSION(11, 5, 0): 5432 case IP_VERSION(11, 5, 1): 5433 case IP_VERSION(11, 5, 2): 5434 gfx_v11_0_update_gfx_clock_gating(adev, 5435 state == AMD_CG_STATE_GATE); 5436 break; 5437 default: 5438 break; 5439 } 5440 5441 return 0; 5442 } 5443 5444 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5445 { 5446 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5447 int data; 5448 5449 /* AMD_CG_SUPPORT_GFX_MGCG */ 5450 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5451 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5452 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5453 5454 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5455 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5456 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5457 5458 /* AMD_CG_SUPPORT_GFX_FGCG */ 5459 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5460 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5461 5462 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5463 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5464 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5465 5466 /* AMD_CG_SUPPORT_GFX_CGCG */ 5467 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5468 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5469 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5470 5471 /* AMD_CG_SUPPORT_GFX_CGLS */ 5472 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5473 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5474 5475 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5476 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5477 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5478 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5479 5480 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5481 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5482 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5483 } 5484 5485 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5486 { 5487 /* gfx11 is 32bit rptr*/ 5488 return *(uint32_t *)ring->rptr_cpu_addr; 5489 } 5490 5491 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5492 { 5493 struct amdgpu_device *adev = ring->adev; 5494 u64 wptr; 5495 5496 /* XXX check if swapping is necessary on BE */ 5497 if (ring->use_doorbell) { 5498 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5499 } else { 5500 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5501 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5502 } 5503 5504 return wptr; 5505 } 5506 5507 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5508 { 5509 struct amdgpu_device *adev = ring->adev; 5510 5511 if (ring->use_doorbell) { 5512 /* XXX check if swapping is necessary on BE */ 5513 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5514 ring->wptr); 5515 WDOORBELL64(ring->doorbell_index, ring->wptr); 5516 } else { 5517 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5518 lower_32_bits(ring->wptr)); 5519 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5520 upper_32_bits(ring->wptr)); 5521 } 5522 } 5523 5524 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5525 { 5526 /* gfx11 hardware is 32bit rptr */ 5527 return *(uint32_t *)ring->rptr_cpu_addr; 5528 } 5529 5530 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5531 { 5532 u64 wptr; 5533 5534 /* XXX check if swapping is necessary on BE */ 5535 if (ring->use_doorbell) 5536 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5537 else 5538 BUG(); 5539 return wptr; 5540 } 5541 5542 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5543 { 5544 struct amdgpu_device *adev = ring->adev; 5545 5546 /* XXX check if swapping is necessary on BE */ 5547 if (ring->use_doorbell) { 5548 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5549 ring->wptr); 5550 WDOORBELL64(ring->doorbell_index, ring->wptr); 5551 } else { 5552 BUG(); /* only DOORBELL method supported on gfx11 now */ 5553 } 5554 } 5555 5556 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5557 { 5558 struct amdgpu_device *adev = ring->adev; 5559 u32 ref_and_mask, reg_mem_engine; 5560 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5561 5562 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5563 switch (ring->me) { 5564 case 1: 5565 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5566 break; 5567 case 2: 5568 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5569 break; 5570 default: 5571 return; 5572 } 5573 reg_mem_engine = 0; 5574 } else { 5575 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5576 reg_mem_engine = 1; /* pfp */ 5577 } 5578 5579 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5580 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5581 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5582 ref_and_mask, ref_and_mask, 0x20); 5583 } 5584 5585 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5586 struct amdgpu_job *job, 5587 struct amdgpu_ib *ib, 5588 uint32_t flags) 5589 { 5590 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5591 u32 header, control = 0; 5592 5593 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5594 5595 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5596 5597 control |= ib->length_dw | (vmid << 24); 5598 5599 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5600 control |= INDIRECT_BUFFER_PRE_ENB(1); 5601 5602 if (flags & AMDGPU_IB_PREEMPTED) 5603 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5604 5605 if (vmid) 5606 gfx_v11_0_ring_emit_de_meta(ring, 5607 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5608 } 5609 5610 if (ring->is_mes_queue) 5611 /* inherit vmid from mqd */ 5612 control |= 0x400000; 5613 5614 amdgpu_ring_write(ring, header); 5615 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5616 amdgpu_ring_write(ring, 5617 #ifdef __BIG_ENDIAN 5618 (2 << 0) | 5619 #endif 5620 lower_32_bits(ib->gpu_addr)); 5621 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5622 amdgpu_ring_write(ring, control); 5623 } 5624 5625 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5626 struct amdgpu_job *job, 5627 struct amdgpu_ib *ib, 5628 uint32_t flags) 5629 { 5630 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5631 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5632 5633 if (ring->is_mes_queue) 5634 /* inherit vmid from mqd */ 5635 control |= 0x40000000; 5636 5637 /* Currently, there is a high possibility to get wave ID mismatch 5638 * between ME and GDS, leading to a hw deadlock, because ME generates 5639 * different wave IDs than the GDS expects. This situation happens 5640 * randomly when at least 5 compute pipes use GDS ordered append. 5641 * The wave IDs generated by ME are also wrong after suspend/resume. 5642 * Those are probably bugs somewhere else in the kernel driver. 5643 * 5644 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5645 * GDS to 0 for this ring (me/pipe). 5646 */ 5647 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5648 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5649 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5650 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5651 } 5652 5653 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5654 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5655 amdgpu_ring_write(ring, 5656 #ifdef __BIG_ENDIAN 5657 (2 << 0) | 5658 #endif 5659 lower_32_bits(ib->gpu_addr)); 5660 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5661 amdgpu_ring_write(ring, control); 5662 } 5663 5664 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5665 u64 seq, unsigned flags) 5666 { 5667 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5668 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5669 5670 /* RELEASE_MEM - flush caches, send int */ 5671 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5672 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5673 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5674 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5675 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5676 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5677 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5678 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5679 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5680 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5681 5682 /* 5683 * the address should be Qword aligned if 64bit write, Dword 5684 * aligned if only send 32bit data low (discard data high) 5685 */ 5686 if (write64bit) 5687 BUG_ON(addr & 0x7); 5688 else 5689 BUG_ON(addr & 0x3); 5690 amdgpu_ring_write(ring, lower_32_bits(addr)); 5691 amdgpu_ring_write(ring, upper_32_bits(addr)); 5692 amdgpu_ring_write(ring, lower_32_bits(seq)); 5693 amdgpu_ring_write(ring, upper_32_bits(seq)); 5694 amdgpu_ring_write(ring, ring->is_mes_queue ? 5695 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5696 } 5697 5698 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5699 { 5700 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5701 uint32_t seq = ring->fence_drv.sync_seq; 5702 uint64_t addr = ring->fence_drv.gpu_addr; 5703 5704 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5705 upper_32_bits(addr), seq, 0xffffffff, 4); 5706 } 5707 5708 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5709 uint16_t pasid, uint32_t flush_type, 5710 bool all_hub, uint8_t dst_sel) 5711 { 5712 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5713 amdgpu_ring_write(ring, 5714 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5715 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5716 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5717 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5718 } 5719 5720 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5721 unsigned vmid, uint64_t pd_addr) 5722 { 5723 if (ring->is_mes_queue) 5724 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5725 else 5726 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5727 5728 /* compute doesn't have PFP */ 5729 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5730 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5731 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5732 amdgpu_ring_write(ring, 0x0); 5733 } 5734 5735 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5736 * changed in any way. 5737 */ 5738 ring->set_q_mode_offs = 0; 5739 ring->set_q_mode_ptr = NULL; 5740 } 5741 5742 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5743 u64 seq, unsigned int flags) 5744 { 5745 struct amdgpu_device *adev = ring->adev; 5746 5747 /* we only allocate 32bit for each seq wb address */ 5748 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5749 5750 /* write fence seq to the "addr" */ 5751 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5752 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5753 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5754 amdgpu_ring_write(ring, lower_32_bits(addr)); 5755 amdgpu_ring_write(ring, upper_32_bits(addr)); 5756 amdgpu_ring_write(ring, lower_32_bits(seq)); 5757 5758 if (flags & AMDGPU_FENCE_FLAG_INT) { 5759 /* set register to trigger INT */ 5760 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5761 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5762 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5763 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5764 amdgpu_ring_write(ring, 0); 5765 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5766 } 5767 } 5768 5769 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5770 uint32_t flags) 5771 { 5772 uint32_t dw2 = 0; 5773 5774 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5775 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5776 /* set load_global_config & load_global_uconfig */ 5777 dw2 |= 0x8001; 5778 /* set load_cs_sh_regs */ 5779 dw2 |= 0x01000000; 5780 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5781 dw2 |= 0x10002; 5782 } 5783 5784 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5785 amdgpu_ring_write(ring, dw2); 5786 amdgpu_ring_write(ring, 0); 5787 } 5788 5789 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5790 uint64_t addr) 5791 { 5792 unsigned ret; 5793 5794 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5795 amdgpu_ring_write(ring, lower_32_bits(addr)); 5796 amdgpu_ring_write(ring, upper_32_bits(addr)); 5797 /* discard following DWs if *cond_exec_gpu_addr==0 */ 5798 amdgpu_ring_write(ring, 0); 5799 ret = ring->wptr & ring->buf_mask; 5800 /* patch dummy value later */ 5801 amdgpu_ring_write(ring, 0); 5802 5803 return ret; 5804 } 5805 5806 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5807 u64 shadow_va, u64 csa_va, 5808 u64 gds_va, bool init_shadow, 5809 int vmid) 5810 { 5811 struct amdgpu_device *adev = ring->adev; 5812 unsigned int offs, end; 5813 5814 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 5815 return; 5816 5817 /* 5818 * The logic here isn't easy to understand because we need to keep state 5819 * accross multiple executions of the function as well as between the 5820 * CPU and GPU. The general idea is that the newly written GPU command 5821 * has a condition on the previous one and only executed if really 5822 * necessary. 5823 */ 5824 5825 /* 5826 * The dw in the NOP controls if the next SET_Q_MODE packet should be 5827 * executed or not. Reserve 64bits just to be on the save side. 5828 */ 5829 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 5830 offs = ring->wptr & ring->buf_mask; 5831 5832 /* 5833 * We start with skipping the prefix SET_Q_MODE and always executing 5834 * the postfix SET_Q_MODE packet. This is changed below with a 5835 * WRITE_DATA command when the postfix executed. 5836 */ 5837 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 5838 amdgpu_ring_write(ring, 0); 5839 5840 if (ring->set_q_mode_offs) { 5841 uint64_t addr; 5842 5843 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5844 addr += ring->set_q_mode_offs << 2; 5845 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 5846 } 5847 5848 /* 5849 * When the postfix SET_Q_MODE packet executes we need to make sure that the 5850 * next prefix SET_Q_MODE packet executes as well. 5851 */ 5852 if (!shadow_va) { 5853 uint64_t addr; 5854 5855 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5856 addr += offs << 2; 5857 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5858 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 5859 amdgpu_ring_write(ring, lower_32_bits(addr)); 5860 amdgpu_ring_write(ring, upper_32_bits(addr)); 5861 amdgpu_ring_write(ring, 0x1); 5862 } 5863 5864 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5865 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5866 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5867 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5868 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5869 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5870 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5871 amdgpu_ring_write(ring, shadow_va ? 5872 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5873 amdgpu_ring_write(ring, init_shadow ? 5874 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5875 5876 if (ring->set_q_mode_offs) 5877 amdgpu_ring_patch_cond_exec(ring, end); 5878 5879 if (shadow_va) { 5880 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 5881 5882 /* 5883 * If the tokens match try to skip the last postfix SET_Q_MODE 5884 * packet to avoid saving/restoring the state all the time. 5885 */ 5886 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 5887 *ring->set_q_mode_ptr = 0; 5888 5889 ring->set_q_mode_token = token; 5890 } else { 5891 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 5892 } 5893 5894 ring->set_q_mode_offs = offs; 5895 } 5896 5897 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5898 { 5899 int i, r = 0; 5900 struct amdgpu_device *adev = ring->adev; 5901 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5902 struct amdgpu_ring *kiq_ring = &kiq->ring; 5903 unsigned long flags; 5904 5905 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5906 return -EINVAL; 5907 5908 spin_lock_irqsave(&kiq->ring_lock, flags); 5909 5910 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5911 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5912 return -ENOMEM; 5913 } 5914 5915 /* assert preemption condition */ 5916 amdgpu_ring_set_preempt_cond_exec(ring, false); 5917 5918 /* assert IB preemption, emit the trailing fence */ 5919 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5920 ring->trail_fence_gpu_addr, 5921 ++ring->trail_seq); 5922 amdgpu_ring_commit(kiq_ring); 5923 5924 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5925 5926 /* poll the trailing fence */ 5927 for (i = 0; i < adev->usec_timeout; i++) { 5928 if (ring->trail_seq == 5929 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5930 break; 5931 udelay(1); 5932 } 5933 5934 if (i >= adev->usec_timeout) { 5935 r = -EINVAL; 5936 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5937 } 5938 5939 /* deassert preemption condition */ 5940 amdgpu_ring_set_preempt_cond_exec(ring, true); 5941 return r; 5942 } 5943 5944 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5945 { 5946 struct amdgpu_device *adev = ring->adev; 5947 struct v10_de_ib_state de_payload = {0}; 5948 uint64_t offset, gds_addr, de_payload_gpu_addr; 5949 void *de_payload_cpu_addr; 5950 int cnt; 5951 5952 if (ring->is_mes_queue) { 5953 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5954 gfx[0].gfx_meta_data) + 5955 offsetof(struct v10_gfx_meta_data, de_payload); 5956 de_payload_gpu_addr = 5957 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5958 de_payload_cpu_addr = 5959 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5960 5961 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5962 gfx[0].gds_backup) + 5963 offsetof(struct v10_gfx_meta_data, de_payload); 5964 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5965 } else { 5966 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5967 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5968 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5969 5970 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5971 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5972 PAGE_SIZE); 5973 } 5974 5975 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5976 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5977 5978 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5979 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5980 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5981 WRITE_DATA_DST_SEL(8) | 5982 WR_CONFIRM) | 5983 WRITE_DATA_CACHE_POLICY(0)); 5984 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5985 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5986 5987 if (resume) 5988 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5989 sizeof(de_payload) >> 2); 5990 else 5991 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5992 sizeof(de_payload) >> 2); 5993 } 5994 5995 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5996 bool secure) 5997 { 5998 uint32_t v = secure ? FRAME_TMZ : 0; 5999 6000 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6001 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6002 } 6003 6004 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6005 uint32_t reg_val_offs) 6006 { 6007 struct amdgpu_device *adev = ring->adev; 6008 6009 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6010 amdgpu_ring_write(ring, 0 | /* src: register*/ 6011 (5 << 8) | /* dst: memory */ 6012 (1 << 20)); /* write confirm */ 6013 amdgpu_ring_write(ring, reg); 6014 amdgpu_ring_write(ring, 0); 6015 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6016 reg_val_offs * 4)); 6017 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6018 reg_val_offs * 4)); 6019 } 6020 6021 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6022 uint32_t val) 6023 { 6024 uint32_t cmd = 0; 6025 6026 switch (ring->funcs->type) { 6027 case AMDGPU_RING_TYPE_GFX: 6028 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6029 break; 6030 case AMDGPU_RING_TYPE_KIQ: 6031 cmd = (1 << 16); /* no inc addr */ 6032 break; 6033 default: 6034 cmd = WR_CONFIRM; 6035 break; 6036 } 6037 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6038 amdgpu_ring_write(ring, cmd); 6039 amdgpu_ring_write(ring, reg); 6040 amdgpu_ring_write(ring, 0); 6041 amdgpu_ring_write(ring, val); 6042 } 6043 6044 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6045 uint32_t val, uint32_t mask) 6046 { 6047 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6048 } 6049 6050 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6051 uint32_t reg0, uint32_t reg1, 6052 uint32_t ref, uint32_t mask) 6053 { 6054 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6055 6056 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6057 ref, mask, 0x20); 6058 } 6059 6060 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 6061 unsigned vmid) 6062 { 6063 struct amdgpu_device *adev = ring->adev; 6064 uint32_t value = 0; 6065 6066 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6067 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6068 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6069 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6070 WREG32_SOC15(GC, 0, regSQ_CMD, value); 6071 } 6072 6073 static void 6074 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6075 uint32_t me, uint32_t pipe, 6076 enum amdgpu_interrupt_state state) 6077 { 6078 uint32_t cp_int_cntl, cp_int_cntl_reg; 6079 6080 if (!me) { 6081 switch (pipe) { 6082 case 0: 6083 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6084 break; 6085 case 1: 6086 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6087 break; 6088 default: 6089 DRM_DEBUG("invalid pipe %d\n", pipe); 6090 return; 6091 } 6092 } else { 6093 DRM_DEBUG("invalid me %d\n", me); 6094 return; 6095 } 6096 6097 switch (state) { 6098 case AMDGPU_IRQ_STATE_DISABLE: 6099 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6100 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6101 TIME_STAMP_INT_ENABLE, 0); 6102 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6103 GENERIC0_INT_ENABLE, 0); 6104 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6105 break; 6106 case AMDGPU_IRQ_STATE_ENABLE: 6107 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6108 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6109 TIME_STAMP_INT_ENABLE, 1); 6110 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6111 GENERIC0_INT_ENABLE, 1); 6112 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6113 break; 6114 default: 6115 break; 6116 } 6117 } 6118 6119 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6120 int me, int pipe, 6121 enum amdgpu_interrupt_state state) 6122 { 6123 u32 mec_int_cntl, mec_int_cntl_reg; 6124 6125 /* 6126 * amdgpu controls only the first MEC. That's why this function only 6127 * handles the setting of interrupts for this specific MEC. All other 6128 * pipes' interrupts are set by amdkfd. 6129 */ 6130 6131 if (me == 1) { 6132 switch (pipe) { 6133 case 0: 6134 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6135 break; 6136 case 1: 6137 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6138 break; 6139 case 2: 6140 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6141 break; 6142 case 3: 6143 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6144 break; 6145 default: 6146 DRM_DEBUG("invalid pipe %d\n", pipe); 6147 return; 6148 } 6149 } else { 6150 DRM_DEBUG("invalid me %d\n", me); 6151 return; 6152 } 6153 6154 switch (state) { 6155 case AMDGPU_IRQ_STATE_DISABLE: 6156 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6157 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6158 TIME_STAMP_INT_ENABLE, 0); 6159 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6160 GENERIC0_INT_ENABLE, 0); 6161 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6162 break; 6163 case AMDGPU_IRQ_STATE_ENABLE: 6164 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6165 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6166 TIME_STAMP_INT_ENABLE, 1); 6167 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6168 GENERIC0_INT_ENABLE, 1); 6169 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6170 break; 6171 default: 6172 break; 6173 } 6174 } 6175 6176 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6177 struct amdgpu_irq_src *src, 6178 unsigned type, 6179 enum amdgpu_interrupt_state state) 6180 { 6181 switch (type) { 6182 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6183 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6184 break; 6185 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6186 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6187 break; 6188 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6189 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6190 break; 6191 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6192 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6193 break; 6194 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6195 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6196 break; 6197 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6198 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6199 break; 6200 default: 6201 break; 6202 } 6203 return 0; 6204 } 6205 6206 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6207 struct amdgpu_irq_src *source, 6208 struct amdgpu_iv_entry *entry) 6209 { 6210 int i; 6211 u8 me_id, pipe_id, queue_id; 6212 struct amdgpu_ring *ring; 6213 uint32_t mes_queue_id = entry->src_data[0]; 6214 6215 DRM_DEBUG("IH: CP EOP\n"); 6216 6217 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6218 struct amdgpu_mes_queue *queue; 6219 6220 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6221 6222 spin_lock(&adev->mes.queue_id_lock); 6223 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6224 if (queue) { 6225 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6226 amdgpu_fence_process(queue->ring); 6227 } 6228 spin_unlock(&adev->mes.queue_id_lock); 6229 } else { 6230 me_id = (entry->ring_id & 0x0c) >> 2; 6231 pipe_id = (entry->ring_id & 0x03) >> 0; 6232 queue_id = (entry->ring_id & 0x70) >> 4; 6233 6234 switch (me_id) { 6235 case 0: 6236 if (pipe_id == 0) 6237 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6238 else 6239 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6240 break; 6241 case 1: 6242 case 2: 6243 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6244 ring = &adev->gfx.compute_ring[i]; 6245 /* Per-queue interrupt is supported for MEC starting from VI. 6246 * The interrupt can only be enabled/disabled per pipe instead 6247 * of per queue. 6248 */ 6249 if ((ring->me == me_id) && 6250 (ring->pipe == pipe_id) && 6251 (ring->queue == queue_id)) 6252 amdgpu_fence_process(ring); 6253 } 6254 break; 6255 } 6256 } 6257 6258 return 0; 6259 } 6260 6261 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6262 struct amdgpu_irq_src *source, 6263 unsigned int type, 6264 enum amdgpu_interrupt_state state) 6265 { 6266 u32 cp_int_cntl_reg, cp_int_cntl; 6267 int i, j; 6268 6269 switch (state) { 6270 case AMDGPU_IRQ_STATE_DISABLE: 6271 case AMDGPU_IRQ_STATE_ENABLE: 6272 for (i = 0; i < adev->gfx.me.num_me; i++) { 6273 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6274 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6275 6276 if (cp_int_cntl_reg) { 6277 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6278 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6279 PRIV_REG_INT_ENABLE, 6280 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6281 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6282 } 6283 } 6284 } 6285 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6286 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6287 /* MECs start at 1 */ 6288 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6289 6290 if (cp_int_cntl_reg) { 6291 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6292 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6293 PRIV_REG_INT_ENABLE, 6294 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6295 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6296 } 6297 } 6298 } 6299 break; 6300 default: 6301 break; 6302 } 6303 6304 return 0; 6305 } 6306 6307 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6308 struct amdgpu_irq_src *source, 6309 unsigned type, 6310 enum amdgpu_interrupt_state state) 6311 { 6312 u32 cp_int_cntl_reg, cp_int_cntl; 6313 int i, j; 6314 6315 switch (state) { 6316 case AMDGPU_IRQ_STATE_DISABLE: 6317 case AMDGPU_IRQ_STATE_ENABLE: 6318 for (i = 0; i < adev->gfx.me.num_me; i++) { 6319 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6320 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6321 6322 if (cp_int_cntl_reg) { 6323 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6324 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6325 OPCODE_ERROR_INT_ENABLE, 6326 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6327 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6328 } 6329 } 6330 } 6331 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6332 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6333 /* MECs start at 1 */ 6334 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6335 6336 if (cp_int_cntl_reg) { 6337 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6338 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6339 OPCODE_ERROR_INT_ENABLE, 6340 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6341 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6342 } 6343 } 6344 } 6345 break; 6346 default: 6347 break; 6348 } 6349 return 0; 6350 } 6351 6352 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6353 struct amdgpu_irq_src *source, 6354 unsigned int type, 6355 enum amdgpu_interrupt_state state) 6356 { 6357 u32 cp_int_cntl_reg, cp_int_cntl; 6358 int i, j; 6359 6360 switch (state) { 6361 case AMDGPU_IRQ_STATE_DISABLE: 6362 case AMDGPU_IRQ_STATE_ENABLE: 6363 for (i = 0; i < adev->gfx.me.num_me; i++) { 6364 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6365 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6366 6367 if (cp_int_cntl_reg) { 6368 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6369 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6370 PRIV_INSTR_INT_ENABLE, 6371 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6372 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6373 } 6374 } 6375 } 6376 break; 6377 default: 6378 break; 6379 } 6380 6381 return 0; 6382 } 6383 6384 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6385 struct amdgpu_iv_entry *entry) 6386 { 6387 u8 me_id, pipe_id, queue_id; 6388 struct amdgpu_ring *ring; 6389 int i; 6390 6391 me_id = (entry->ring_id & 0x0c) >> 2; 6392 pipe_id = (entry->ring_id & 0x03) >> 0; 6393 queue_id = (entry->ring_id & 0x70) >> 4; 6394 6395 switch (me_id) { 6396 case 0: 6397 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6398 ring = &adev->gfx.gfx_ring[i]; 6399 if (ring->me == me_id && ring->pipe == pipe_id && 6400 ring->queue == queue_id) 6401 drm_sched_fault(&ring->sched); 6402 } 6403 break; 6404 case 1: 6405 case 2: 6406 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6407 ring = &adev->gfx.compute_ring[i]; 6408 if (ring->me == me_id && ring->pipe == pipe_id && 6409 ring->queue == queue_id) 6410 drm_sched_fault(&ring->sched); 6411 } 6412 break; 6413 default: 6414 BUG(); 6415 break; 6416 } 6417 } 6418 6419 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6420 struct amdgpu_irq_src *source, 6421 struct amdgpu_iv_entry *entry) 6422 { 6423 DRM_ERROR("Illegal register access in command stream\n"); 6424 gfx_v11_0_handle_priv_fault(adev, entry); 6425 return 0; 6426 } 6427 6428 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6429 struct amdgpu_irq_src *source, 6430 struct amdgpu_iv_entry *entry) 6431 { 6432 DRM_ERROR("Illegal opcode in command stream \n"); 6433 gfx_v11_0_handle_priv_fault(adev, entry); 6434 return 0; 6435 } 6436 6437 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6438 struct amdgpu_irq_src *source, 6439 struct amdgpu_iv_entry *entry) 6440 { 6441 DRM_ERROR("Illegal instruction in command stream\n"); 6442 gfx_v11_0_handle_priv_fault(adev, entry); 6443 return 0; 6444 } 6445 6446 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6447 struct amdgpu_irq_src *source, 6448 struct amdgpu_iv_entry *entry) 6449 { 6450 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6451 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6452 6453 return 0; 6454 } 6455 6456 #if 0 6457 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6458 struct amdgpu_irq_src *src, 6459 unsigned int type, 6460 enum amdgpu_interrupt_state state) 6461 { 6462 uint32_t tmp, target; 6463 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6464 6465 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6466 target += ring->pipe; 6467 6468 switch (type) { 6469 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6470 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6471 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6472 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6473 GENERIC2_INT_ENABLE, 0); 6474 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6475 6476 tmp = RREG32_SOC15_IP(GC, target); 6477 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6478 GENERIC2_INT_ENABLE, 0); 6479 WREG32_SOC15_IP(GC, target, tmp); 6480 } else { 6481 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6482 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6483 GENERIC2_INT_ENABLE, 1); 6484 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6485 6486 tmp = RREG32_SOC15_IP(GC, target); 6487 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6488 GENERIC2_INT_ENABLE, 1); 6489 WREG32_SOC15_IP(GC, target, tmp); 6490 } 6491 break; 6492 default: 6493 BUG(); /* kiq only support GENERIC2_INT now */ 6494 break; 6495 } 6496 return 0; 6497 } 6498 #endif 6499 6500 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6501 { 6502 const unsigned int gcr_cntl = 6503 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6504 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6505 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6506 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6507 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6508 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6509 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6510 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6511 6512 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6513 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6514 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6515 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6516 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6517 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6518 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6519 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6520 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6521 } 6522 6523 static void gfx_v11_ip_print(void *handle, struct drm_printer *p) 6524 { 6525 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6526 uint32_t i, j, k, reg, index = 0; 6527 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6528 6529 if (!adev->gfx.ip_dump_core) 6530 return; 6531 6532 for (i = 0; i < reg_count; i++) 6533 drm_printf(p, "%-50s \t 0x%08x\n", 6534 gc_reg_list_11_0[i].reg_name, 6535 adev->gfx.ip_dump_core[i]); 6536 6537 /* print compute queue registers for all instances */ 6538 if (!adev->gfx.ip_dump_compute_queues) 6539 return; 6540 6541 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6542 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6543 adev->gfx.mec.num_mec, 6544 adev->gfx.mec.num_pipe_per_mec, 6545 adev->gfx.mec.num_queue_per_pipe); 6546 6547 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6548 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6549 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6550 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 6551 for (reg = 0; reg < reg_count; reg++) { 6552 drm_printf(p, "%-50s \t 0x%08x\n", 6553 gc_cp_reg_list_11[reg].reg_name, 6554 adev->gfx.ip_dump_compute_queues[index + reg]); 6555 } 6556 index += reg_count; 6557 } 6558 } 6559 } 6560 6561 /* print gfx queue registers for all instances */ 6562 if (!adev->gfx.ip_dump_gfx_queues) 6563 return; 6564 6565 index = 0; 6566 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6567 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 6568 adev->gfx.me.num_me, 6569 adev->gfx.me.num_pipe_per_me, 6570 adev->gfx.me.num_queue_per_pipe); 6571 6572 for (i = 0; i < adev->gfx.me.num_me; i++) { 6573 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6574 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6575 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 6576 for (reg = 0; reg < reg_count; reg++) { 6577 drm_printf(p, "%-50s \t 0x%08x\n", 6578 gc_gfx_queue_reg_list_11[reg].reg_name, 6579 adev->gfx.ip_dump_gfx_queues[index + reg]); 6580 } 6581 index += reg_count; 6582 } 6583 } 6584 } 6585 } 6586 6587 static void gfx_v11_ip_dump(void *handle) 6588 { 6589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6590 uint32_t i, j, k, reg, index = 0; 6591 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6592 6593 if (!adev->gfx.ip_dump_core) 6594 return; 6595 6596 amdgpu_gfx_off_ctrl(adev, false); 6597 for (i = 0; i < reg_count; i++) 6598 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 6599 amdgpu_gfx_off_ctrl(adev, true); 6600 6601 /* dump compute queue registers for all instances */ 6602 if (!adev->gfx.ip_dump_compute_queues) 6603 return; 6604 6605 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6606 amdgpu_gfx_off_ctrl(adev, false); 6607 mutex_lock(&adev->srbm_mutex); 6608 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6609 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6610 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6611 /* ME0 is for GFX so start from 1 for CP */ 6612 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 6613 for (reg = 0; reg < reg_count; reg++) { 6614 adev->gfx.ip_dump_compute_queues[index + reg] = 6615 RREG32(SOC15_REG_ENTRY_OFFSET( 6616 gc_cp_reg_list_11[reg])); 6617 } 6618 index += reg_count; 6619 } 6620 } 6621 } 6622 soc21_grbm_select(adev, 0, 0, 0, 0); 6623 mutex_unlock(&adev->srbm_mutex); 6624 amdgpu_gfx_off_ctrl(adev, true); 6625 6626 /* dump gfx queue registers for all instances */ 6627 if (!adev->gfx.ip_dump_gfx_queues) 6628 return; 6629 6630 index = 0; 6631 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6632 amdgpu_gfx_off_ctrl(adev, false); 6633 mutex_lock(&adev->srbm_mutex); 6634 for (i = 0; i < adev->gfx.me.num_me; i++) { 6635 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6636 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6637 soc21_grbm_select(adev, i, j, k, 0); 6638 6639 for (reg = 0; reg < reg_count; reg++) { 6640 adev->gfx.ip_dump_gfx_queues[index + reg] = 6641 RREG32(SOC15_REG_ENTRY_OFFSET( 6642 gc_gfx_queue_reg_list_11[reg])); 6643 } 6644 index += reg_count; 6645 } 6646 } 6647 } 6648 soc21_grbm_select(adev, 0, 0, 0, 0); 6649 mutex_unlock(&adev->srbm_mutex); 6650 amdgpu_gfx_off_ctrl(adev, true); 6651 } 6652 6653 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6654 .name = "gfx_v11_0", 6655 .early_init = gfx_v11_0_early_init, 6656 .late_init = gfx_v11_0_late_init, 6657 .sw_init = gfx_v11_0_sw_init, 6658 .sw_fini = gfx_v11_0_sw_fini, 6659 .hw_init = gfx_v11_0_hw_init, 6660 .hw_fini = gfx_v11_0_hw_fini, 6661 .suspend = gfx_v11_0_suspend, 6662 .resume = gfx_v11_0_resume, 6663 .is_idle = gfx_v11_0_is_idle, 6664 .wait_for_idle = gfx_v11_0_wait_for_idle, 6665 .soft_reset = gfx_v11_0_soft_reset, 6666 .check_soft_reset = gfx_v11_0_check_soft_reset, 6667 .post_soft_reset = gfx_v11_0_post_soft_reset, 6668 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6669 .set_powergating_state = gfx_v11_0_set_powergating_state, 6670 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6671 .dump_ip_state = gfx_v11_ip_dump, 6672 .print_ip_state = gfx_v11_ip_print, 6673 }; 6674 6675 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6676 .type = AMDGPU_RING_TYPE_GFX, 6677 .align_mask = 0xff, 6678 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6679 .support_64bit_ptrs = true, 6680 .secure_submission_supported = true, 6681 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6682 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6683 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6684 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 6685 5 + /* update_spm_vmid */ 6686 5 + /* COND_EXEC */ 6687 22 + /* SET_Q_PREEMPTION_MODE */ 6688 7 + /* PIPELINE_SYNC */ 6689 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6690 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6691 4 + /* VM_FLUSH */ 6692 8 + /* FENCE for VM_FLUSH */ 6693 20 + /* GDS switch */ 6694 5 + /* COND_EXEC */ 6695 7 + /* HDP_flush */ 6696 4 + /* VGT_flush */ 6697 31 + /* DE_META */ 6698 3 + /* CNTX_CTRL */ 6699 5 + /* HDP_INVL */ 6700 22 + /* SET_Q_PREEMPTION_MODE */ 6701 8 + 8 + /* FENCE x2 */ 6702 8, /* gfx_v11_0_emit_mem_sync */ 6703 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6704 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6705 .emit_fence = gfx_v11_0_ring_emit_fence, 6706 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6707 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6708 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6709 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6710 .test_ring = gfx_v11_0_ring_test_ring, 6711 .test_ib = gfx_v11_0_ring_test_ib, 6712 .insert_nop = amdgpu_ring_insert_nop, 6713 .pad_ib = amdgpu_ring_generic_pad_ib, 6714 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6715 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6716 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6717 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6718 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6719 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6720 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6721 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6722 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6723 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6724 }; 6725 6726 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6727 .type = AMDGPU_RING_TYPE_COMPUTE, 6728 .align_mask = 0xff, 6729 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6730 .support_64bit_ptrs = true, 6731 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6732 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6733 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6734 .emit_frame_size = 6735 5 + /* update_spm_vmid */ 6736 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6737 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6738 5 + /* hdp invalidate */ 6739 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6740 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6741 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6742 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6743 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6744 8, /* gfx_v11_0_emit_mem_sync */ 6745 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6746 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6747 .emit_fence = gfx_v11_0_ring_emit_fence, 6748 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6749 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6750 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6751 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6752 .test_ring = gfx_v11_0_ring_test_ring, 6753 .test_ib = gfx_v11_0_ring_test_ib, 6754 .insert_nop = amdgpu_ring_insert_nop, 6755 .pad_ib = amdgpu_ring_generic_pad_ib, 6756 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6757 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6758 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6759 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6760 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6761 }; 6762 6763 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6764 .type = AMDGPU_RING_TYPE_KIQ, 6765 .align_mask = 0xff, 6766 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6767 .support_64bit_ptrs = true, 6768 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6769 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6770 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6771 .emit_frame_size = 6772 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6773 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6774 5 + /*hdp invalidate */ 6775 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6776 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6777 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6778 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6779 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6780 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6781 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6782 .test_ring = gfx_v11_0_ring_test_ring, 6783 .test_ib = gfx_v11_0_ring_test_ib, 6784 .insert_nop = amdgpu_ring_insert_nop, 6785 .pad_ib = amdgpu_ring_generic_pad_ib, 6786 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6787 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6788 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6789 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6790 }; 6791 6792 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6793 { 6794 int i; 6795 6796 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6797 6798 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6799 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6800 6801 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6802 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6803 } 6804 6805 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6806 .set = gfx_v11_0_set_eop_interrupt_state, 6807 .process = gfx_v11_0_eop_irq, 6808 }; 6809 6810 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6811 .set = gfx_v11_0_set_priv_reg_fault_state, 6812 .process = gfx_v11_0_priv_reg_irq, 6813 }; 6814 6815 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 6816 .set = gfx_v11_0_set_bad_op_fault_state, 6817 .process = gfx_v11_0_bad_op_irq, 6818 }; 6819 6820 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6821 .set = gfx_v11_0_set_priv_inst_fault_state, 6822 .process = gfx_v11_0_priv_inst_irq, 6823 }; 6824 6825 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6826 .process = gfx_v11_0_rlc_gc_fed_irq, 6827 }; 6828 6829 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6830 { 6831 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6832 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6833 6834 adev->gfx.priv_reg_irq.num_types = 1; 6835 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6836 6837 adev->gfx.bad_op_irq.num_types = 1; 6838 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 6839 6840 adev->gfx.priv_inst_irq.num_types = 1; 6841 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6842 6843 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6844 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6845 6846 } 6847 6848 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6849 { 6850 if (adev->flags & AMD_IS_APU) 6851 adev->gfx.imu.mode = MISSION_MODE; 6852 else 6853 adev->gfx.imu.mode = DEBUG_MODE; 6854 6855 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6856 } 6857 6858 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6859 { 6860 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6861 } 6862 6863 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6864 { 6865 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6866 adev->gfx.config.max_sh_per_se * 6867 adev->gfx.config.max_shader_engines; 6868 6869 adev->gds.gds_size = 0x1000; 6870 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6871 adev->gds.gws_size = 64; 6872 adev->gds.oa_size = 16; 6873 } 6874 6875 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6876 { 6877 /* set gfx eng mqd */ 6878 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6879 sizeof(struct v11_gfx_mqd); 6880 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6881 gfx_v11_0_gfx_mqd_init; 6882 /* set compute eng mqd */ 6883 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6884 sizeof(struct v11_compute_mqd); 6885 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6886 gfx_v11_0_compute_mqd_init; 6887 } 6888 6889 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6890 u32 bitmap) 6891 { 6892 u32 data; 6893 6894 if (!bitmap) 6895 return; 6896 6897 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6898 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6899 6900 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6901 } 6902 6903 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6904 { 6905 u32 data, wgp_bitmask; 6906 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6907 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6908 6909 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6910 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6911 6912 wgp_bitmask = 6913 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6914 6915 return (~data) & wgp_bitmask; 6916 } 6917 6918 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6919 { 6920 u32 wgp_idx, wgp_active_bitmap; 6921 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6922 6923 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6924 cu_active_bitmap = 0; 6925 6926 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6927 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6928 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6929 if (wgp_active_bitmap & (1 << wgp_idx)) 6930 cu_active_bitmap |= cu_bitmap_per_wgp; 6931 } 6932 6933 return cu_active_bitmap; 6934 } 6935 6936 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6937 struct amdgpu_cu_info *cu_info) 6938 { 6939 int i, j, k, counter, active_cu_number = 0; 6940 u32 mask, bitmap; 6941 unsigned disable_masks[8 * 2]; 6942 6943 if (!adev || !cu_info) 6944 return -EINVAL; 6945 6946 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6947 6948 mutex_lock(&adev->grbm_idx_mutex); 6949 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6950 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6951 bitmap = i * adev->gfx.config.max_sh_per_se + j; 6952 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 6953 continue; 6954 mask = 1; 6955 counter = 0; 6956 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6957 if (i < 8 && j < 2) 6958 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6959 adev, disable_masks[i * 2 + j]); 6960 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6961 6962 /** 6963 * GFX11 could support more than 4 SEs, while the bitmap 6964 * in cu_info struct is 4x4 and ioctl interface struct 6965 * drm_amdgpu_info_device should keep stable. 6966 * So we use last two columns of bitmap to store cu mask for 6967 * SEs 4 to 7, the layout of the bitmap is as below: 6968 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6969 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6970 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6971 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6972 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6973 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6974 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6975 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6976 */ 6977 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 6978 6979 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6980 if (bitmap & mask) 6981 counter++; 6982 6983 mask <<= 1; 6984 } 6985 active_cu_number += counter; 6986 } 6987 } 6988 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6989 mutex_unlock(&adev->grbm_idx_mutex); 6990 6991 cu_info->number = active_cu_number; 6992 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6993 6994 return 0; 6995 } 6996 6997 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6998 { 6999 .type = AMD_IP_BLOCK_TYPE_GFX, 7000 .major = 11, 7001 .minor = 0, 7002 .rev = 0, 7003 .funcs = &gfx_v11_0_ip_funcs, 7004 }; 7005