1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 57 #define regCGTT_WD_CLK_CTRL 0x5086 58 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 59 60 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 73 74 static const struct soc15_reg_golden golden_settings_gc_11_0[] = 75 { 76 /* Pending on emulation bring up */ 77 }; 78 79 static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = 80 { 81 /* Pending on emulation bring up */ 82 }; 83 84 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = 85 { 86 /* Pending on emulation bring up */ 87 }; 88 89 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 90 { 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 100 }; 101 102 #define DEFAULT_SH_MEM_CONFIG \ 103 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 104 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 105 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 106 107 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 111 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 112 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 113 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 114 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 115 struct amdgpu_cu_info *cu_info); 116 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 117 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 118 u32 sh_num, u32 instance); 119 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 120 121 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 122 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 123 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 124 uint32_t val); 125 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 126 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 127 uint16_t pasid, uint32_t flush_type, 128 bool all_hub, uint8_t dst_sel); 129 130 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 131 { 132 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 133 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 134 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 135 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 136 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 137 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 139 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 140 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 141 } 142 143 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 144 struct amdgpu_ring *ring) 145 { 146 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 147 uint64_t wptr_addr = ring->wptr_gpu_addr; 148 uint32_t eng_sel = 0; 149 150 switch (ring->funcs->type) { 151 case AMDGPU_RING_TYPE_COMPUTE: 152 eng_sel = 0; 153 break; 154 case AMDGPU_RING_TYPE_GFX: 155 eng_sel = 4; 156 break; 157 case AMDGPU_RING_TYPE_MES: 158 eng_sel = 5; 159 break; 160 default: 161 WARN_ON(1); 162 } 163 164 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 165 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 166 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 167 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 168 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 169 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 170 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 171 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 172 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 173 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 174 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 175 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 176 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 177 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 178 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 179 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 180 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 181 } 182 183 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 184 struct amdgpu_ring *ring, 185 enum amdgpu_unmap_queues_action action, 186 u64 gpu_addr, u64 seq) 187 { 188 struct amdgpu_device *adev = kiq_ring->adev; 189 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 190 191 if (!adev->gfx.kiq.ring.sched.ready) { 192 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 193 return; 194 } 195 196 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 197 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 198 PACKET3_UNMAP_QUEUES_ACTION(action) | 199 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 200 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 201 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 202 amdgpu_ring_write(kiq_ring, 203 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 204 205 if (action == PREEMPT_QUEUES_NO_UNMAP) { 206 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 207 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 208 amdgpu_ring_write(kiq_ring, seq); 209 } else { 210 amdgpu_ring_write(kiq_ring, 0); 211 amdgpu_ring_write(kiq_ring, 0); 212 amdgpu_ring_write(kiq_ring, 0); 213 } 214 } 215 216 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 217 struct amdgpu_ring *ring, 218 u64 addr, 219 u64 seq) 220 { 221 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 222 223 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 224 amdgpu_ring_write(kiq_ring, 225 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 226 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 227 PACKET3_QUERY_STATUS_COMMAND(2)); 228 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 229 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 230 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 231 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 232 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 233 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 234 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 235 } 236 237 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 238 uint16_t pasid, uint32_t flush_type, 239 bool all_hub) 240 { 241 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 242 } 243 244 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 245 .kiq_set_resources = gfx11_kiq_set_resources, 246 .kiq_map_queues = gfx11_kiq_map_queues, 247 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 248 .kiq_query_status = gfx11_kiq_query_status, 249 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 250 .set_resources_size = 8, 251 .map_queues_size = 7, 252 .unmap_queues_size = 6, 253 .query_status_size = 7, 254 .invalidate_tlbs_size = 2, 255 }; 256 257 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 258 { 259 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 260 } 261 262 static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) 263 { 264 switch (adev->ip_versions[GC_HWIP][0]) { 265 case IP_VERSION(11, 0, 0): 266 soc15_program_register_sequence(adev, 267 golden_settings_gc_rlc_spm_11_0, 268 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); 269 break; 270 default: 271 break; 272 } 273 } 274 275 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 276 { 277 switch (adev->ip_versions[GC_HWIP][0]) { 278 case IP_VERSION(11, 0, 0): 279 soc15_program_register_sequence(adev, 280 golden_settings_gc_11_0, 281 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 282 soc15_program_register_sequence(adev, 283 golden_settings_gc_11_0_0, 284 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); 285 break; 286 case IP_VERSION(11, 0, 1): 287 soc15_program_register_sequence(adev, 288 golden_settings_gc_11_0, 289 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 290 soc15_program_register_sequence(adev, 291 golden_settings_gc_11_0_1, 292 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 293 break; 294 default: 295 break; 296 } 297 gfx_v11_0_init_spm_golden_registers(adev); 298 } 299 300 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 301 bool wc, uint32_t reg, uint32_t val) 302 { 303 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 304 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 305 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 306 amdgpu_ring_write(ring, reg); 307 amdgpu_ring_write(ring, 0); 308 amdgpu_ring_write(ring, val); 309 } 310 311 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 312 int mem_space, int opt, uint32_t addr0, 313 uint32_t addr1, uint32_t ref, uint32_t mask, 314 uint32_t inv) 315 { 316 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 317 amdgpu_ring_write(ring, 318 /* memory (1) or register (0) */ 319 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 320 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 321 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 322 WAIT_REG_MEM_ENGINE(eng_sel))); 323 324 if (mem_space) 325 BUG_ON(addr0 & 0x3); /* Dword align */ 326 amdgpu_ring_write(ring, addr0); 327 amdgpu_ring_write(ring, addr1); 328 amdgpu_ring_write(ring, ref); 329 amdgpu_ring_write(ring, mask); 330 amdgpu_ring_write(ring, inv); /* poll interval */ 331 } 332 333 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 334 { 335 struct amdgpu_device *adev = ring->adev; 336 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 337 uint32_t tmp = 0; 338 unsigned i; 339 int r; 340 341 WREG32(scratch, 0xCAFEDEAD); 342 r = amdgpu_ring_alloc(ring, 5); 343 if (r) { 344 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 345 ring->idx, r); 346 return r; 347 } 348 349 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 350 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 351 } else { 352 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 353 amdgpu_ring_write(ring, scratch - 354 PACKET3_SET_UCONFIG_REG_START); 355 amdgpu_ring_write(ring, 0xDEADBEEF); 356 } 357 amdgpu_ring_commit(ring); 358 359 for (i = 0; i < adev->usec_timeout; i++) { 360 tmp = RREG32(scratch); 361 if (tmp == 0xDEADBEEF) 362 break; 363 if (amdgpu_emu_mode == 1) 364 msleep(1); 365 else 366 udelay(1); 367 } 368 369 if (i >= adev->usec_timeout) 370 r = -ETIMEDOUT; 371 return r; 372 } 373 374 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 375 { 376 struct amdgpu_device *adev = ring->adev; 377 struct amdgpu_ib ib; 378 struct dma_fence *f = NULL; 379 unsigned index; 380 uint64_t gpu_addr; 381 volatile uint32_t *cpu_ptr; 382 long r; 383 384 /* MES KIQ fw hasn't indirect buffer support for now */ 385 if (adev->enable_mes_kiq && 386 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 387 return 0; 388 389 memset(&ib, 0, sizeof(ib)); 390 391 if (ring->is_mes_queue) { 392 uint32_t padding, offset; 393 394 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 395 padding = amdgpu_mes_ctx_get_offs(ring, 396 AMDGPU_MES_CTX_PADDING_OFFS); 397 398 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 399 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 400 401 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 402 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 403 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 404 } else { 405 r = amdgpu_device_wb_get(adev, &index); 406 if (r) 407 return r; 408 409 gpu_addr = adev->wb.gpu_addr + (index * 4); 410 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 411 cpu_ptr = &adev->wb.wb[index]; 412 413 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 414 if (r) { 415 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 416 goto err1; 417 } 418 } 419 420 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 421 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 422 ib.ptr[2] = lower_32_bits(gpu_addr); 423 ib.ptr[3] = upper_32_bits(gpu_addr); 424 ib.ptr[4] = 0xDEADBEEF; 425 ib.length_dw = 5; 426 427 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 428 if (r) 429 goto err2; 430 431 r = dma_fence_wait_timeout(f, false, timeout); 432 if (r == 0) { 433 r = -ETIMEDOUT; 434 goto err2; 435 } else if (r < 0) { 436 goto err2; 437 } 438 439 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 440 r = 0; 441 else 442 r = -EINVAL; 443 err2: 444 if (!ring->is_mes_queue) 445 amdgpu_ib_free(adev, &ib, NULL); 446 dma_fence_put(f); 447 err1: 448 if (!ring->is_mes_queue) 449 amdgpu_device_wb_free(adev, index); 450 return r; 451 } 452 453 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 454 { 455 release_firmware(adev->gfx.pfp_fw); 456 adev->gfx.pfp_fw = NULL; 457 release_firmware(adev->gfx.me_fw); 458 adev->gfx.me_fw = NULL; 459 release_firmware(adev->gfx.rlc_fw); 460 adev->gfx.rlc_fw = NULL; 461 release_firmware(adev->gfx.mec_fw); 462 adev->gfx.mec_fw = NULL; 463 464 kfree(adev->gfx.rlc.register_list_format); 465 } 466 467 static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 468 { 469 const struct rlc_firmware_header_v2_1 *rlc_hdr; 470 471 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 472 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 473 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 474 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 475 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 476 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 477 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 478 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 479 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 480 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 481 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 482 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 483 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 484 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 485 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 486 } 487 488 static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 489 { 490 const struct rlc_firmware_header_v2_2 *rlc_hdr; 491 492 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 493 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 494 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 495 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 496 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 497 } 498 499 static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 500 { 501 const struct rlc_firmware_header_v2_3 *rlc_hdr; 502 503 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 504 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 505 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 506 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 507 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 508 } 509 510 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 511 { 512 char fw_name[40]; 513 char ucode_prefix[30]; 514 int err; 515 struct amdgpu_firmware_info *info = NULL; 516 const struct common_firmware_header *header = NULL; 517 const struct gfx_firmware_header_v1_0 *cp_hdr; 518 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 519 const struct rlc_firmware_header_v2_0 *rlc_hdr; 520 unsigned int *tmp = NULL; 521 unsigned int i = 0; 522 uint16_t version_major; 523 uint16_t version_minor; 524 525 DRM_DEBUG("\n"); 526 527 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 528 529 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 530 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 531 if (err) 532 goto out; 533 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 534 if (err) 535 goto out; 536 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 537 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 538 (union amdgpu_firmware_header *) 539 adev->gfx.pfp_fw->data, 2, 0); 540 if (adev->gfx.rs64_enable) { 541 dev_info(adev->dev, "CP RS64 enable\n"); 542 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 543 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 544 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 545 546 } else { 547 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 548 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 549 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 550 } 551 552 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 553 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 554 if (err) 555 goto out; 556 err = amdgpu_ucode_validate(adev->gfx.me_fw); 557 if (err) 558 goto out; 559 if (adev->gfx.rs64_enable) { 560 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 561 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 562 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 563 564 } else { 565 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 566 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 567 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 568 } 569 570 if (!amdgpu_sriov_vf(adev)) { 571 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 572 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 573 if (err) 574 goto out; 575 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 576 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 577 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 578 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 579 580 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 581 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 582 adev->gfx.rlc.save_and_restore_offset = 583 le32_to_cpu(rlc_hdr->save_and_restore_offset); 584 adev->gfx.rlc.clear_state_descriptor_offset = 585 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 586 adev->gfx.rlc.avail_scratch_ram_locations = 587 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 588 adev->gfx.rlc.reg_restore_list_size = 589 le32_to_cpu(rlc_hdr->reg_restore_list_size); 590 adev->gfx.rlc.reg_list_format_start = 591 le32_to_cpu(rlc_hdr->reg_list_format_start); 592 adev->gfx.rlc.reg_list_format_separate_start = 593 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 594 adev->gfx.rlc.starting_offsets_start = 595 le32_to_cpu(rlc_hdr->starting_offsets_start); 596 adev->gfx.rlc.reg_list_format_size_bytes = 597 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 598 adev->gfx.rlc.reg_list_size_bytes = 599 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 600 adev->gfx.rlc.register_list_format = 601 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 602 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 603 if (!adev->gfx.rlc.register_list_format) { 604 err = -ENOMEM; 605 goto out; 606 } 607 608 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 609 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 610 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 611 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 612 613 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 614 615 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 616 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 617 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 618 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 619 620 if (version_major == 2) { 621 if (version_minor >= 1) 622 gfx_v11_0_init_rlc_ext_microcode(adev); 623 if (version_minor >= 2) 624 gfx_v11_0_init_rlc_iram_dram_microcode(adev); 625 if (version_minor == 3) 626 gfx_v11_0_init_rlcp_rlcv_microcode(adev); 627 } 628 } 629 630 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 631 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 632 if (err) 633 goto out; 634 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 635 if (err) 636 goto out; 637 if (adev->gfx.rs64_enable) { 638 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 639 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 640 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 641 642 } else { 643 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 644 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 645 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 646 } 647 648 /* only one MEC for gfx 11.0.0. */ 649 adev->gfx.mec2_fw = NULL; 650 651 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 652 if (adev->gfx.rs64_enable) { 653 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 654 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; 655 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; 656 info->fw = adev->gfx.pfp_fw; 657 header = (const struct common_firmware_header *)info->fw->data; 658 adev->firmware.fw_size += 659 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 660 661 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; 662 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; 663 info->fw = adev->gfx.pfp_fw; 664 header = (const struct common_firmware_header *)info->fw->data; 665 adev->firmware.fw_size += 666 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 667 668 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; 669 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; 670 info->fw = adev->gfx.pfp_fw; 671 header = (const struct common_firmware_header *)info->fw->data; 672 adev->firmware.fw_size += 673 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 674 675 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 676 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; 677 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; 678 info->fw = adev->gfx.me_fw; 679 header = (const struct common_firmware_header *)info->fw->data; 680 adev->firmware.fw_size += 681 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 682 683 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; 684 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; 685 info->fw = adev->gfx.me_fw; 686 header = (const struct common_firmware_header *)info->fw->data; 687 adev->firmware.fw_size += 688 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 689 690 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; 691 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; 692 info->fw = adev->gfx.me_fw; 693 header = (const struct common_firmware_header *)info->fw->data; 694 adev->firmware.fw_size += 695 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 696 697 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 698 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; 699 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; 700 info->fw = adev->gfx.mec_fw; 701 header = (const struct common_firmware_header *)info->fw->data; 702 adev->firmware.fw_size += 703 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 704 705 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; 706 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; 707 info->fw = adev->gfx.mec_fw; 708 header = (const struct common_firmware_header *)info->fw->data; 709 adev->firmware.fw_size += 710 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 711 712 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; 713 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; 714 info->fw = adev->gfx.mec_fw; 715 header = (const struct common_firmware_header *)info->fw->data; 716 adev->firmware.fw_size += 717 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 718 719 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; 720 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; 721 info->fw = adev->gfx.mec_fw; 722 header = (const struct common_firmware_header *)info->fw->data; 723 adev->firmware.fw_size += 724 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 725 726 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; 727 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; 728 info->fw = adev->gfx.mec_fw; 729 header = (const struct common_firmware_header *)info->fw->data; 730 adev->firmware.fw_size += 731 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 732 } else { 733 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 734 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 735 info->fw = adev->gfx.pfp_fw; 736 header = (const struct common_firmware_header *)info->fw->data; 737 adev->firmware.fw_size += 738 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 739 740 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 741 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 742 info->fw = adev->gfx.me_fw; 743 header = (const struct common_firmware_header *)info->fw->data; 744 adev->firmware.fw_size += 745 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 746 747 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 748 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 749 info->fw = adev->gfx.mec_fw; 750 header = (const struct common_firmware_header *)info->fw->data; 751 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 752 adev->firmware.fw_size += 753 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 754 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 755 756 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 757 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 758 info->fw = adev->gfx.mec_fw; 759 adev->firmware.fw_size += 760 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 761 } 762 763 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 764 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 765 info->fw = adev->gfx.rlc_fw; 766 if (info->fw) { 767 header = (const struct common_firmware_header *)info->fw->data; 768 adev->firmware.fw_size += 769 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 770 } 771 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 772 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 773 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 774 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 775 info->fw = adev->gfx.rlc_fw; 776 adev->firmware.fw_size += 777 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 778 779 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 780 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 781 info->fw = adev->gfx.rlc_fw; 782 adev->firmware.fw_size += 783 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 784 } 785 786 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 787 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 788 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 789 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 790 info->fw = adev->gfx.rlc_fw; 791 adev->firmware.fw_size += 792 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 793 794 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 795 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 796 info->fw = adev->gfx.rlc_fw; 797 adev->firmware.fw_size += 798 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 799 } 800 801 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 802 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 803 info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 804 info->fw = adev->gfx.rlc_fw; 805 adev->firmware.fw_size += 806 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 807 } 808 809 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 810 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 811 info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 812 info->fw = adev->gfx.rlc_fw; 813 adev->firmware.fw_size += 814 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 815 } 816 } 817 818 out: 819 if (err) { 820 dev_err(adev->dev, 821 "gfx11: Failed to load firmware \"%s\"\n", 822 fw_name); 823 release_firmware(adev->gfx.pfp_fw); 824 adev->gfx.pfp_fw = NULL; 825 release_firmware(adev->gfx.me_fw); 826 adev->gfx.me_fw = NULL; 827 release_firmware(adev->gfx.rlc_fw); 828 adev->gfx.rlc_fw = NULL; 829 release_firmware(adev->gfx.mec_fw); 830 adev->gfx.mec_fw = NULL; 831 } 832 833 return err; 834 } 835 836 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 837 { 838 const struct psp_firmware_header_v1_0 *toc_hdr; 839 int err = 0; 840 char fw_name[40]; 841 char ucode_prefix[30]; 842 843 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 844 845 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 846 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 847 if (err) 848 goto out; 849 850 err = amdgpu_ucode_validate(adev->psp.toc_fw); 851 if (err) 852 goto out; 853 854 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 855 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 856 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 857 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 858 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 859 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 860 return 0; 861 out: 862 dev_err(adev->dev, "Failed to load TOC microcode\n"); 863 release_firmware(adev->psp.toc_fw); 864 adev->psp.toc_fw = NULL; 865 return err; 866 } 867 868 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 869 { 870 u32 count = 0; 871 const struct cs_section_def *sect = NULL; 872 const struct cs_extent_def *ext = NULL; 873 874 /* begin clear state */ 875 count += 2; 876 /* context control state */ 877 count += 3; 878 879 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 880 for (ext = sect->section; ext->extent != NULL; ++ext) { 881 if (sect->id == SECT_CONTEXT) 882 count += 2 + ext->reg_count; 883 else 884 return 0; 885 } 886 } 887 888 /* set PA_SC_TILE_STEERING_OVERRIDE */ 889 count += 3; 890 /* end clear state */ 891 count += 2; 892 /* clear state */ 893 count += 2; 894 895 return count; 896 } 897 898 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 899 volatile u32 *buffer) 900 { 901 u32 count = 0, i; 902 const struct cs_section_def *sect = NULL; 903 const struct cs_extent_def *ext = NULL; 904 int ctx_reg_offset; 905 906 if (adev->gfx.rlc.cs_data == NULL) 907 return; 908 if (buffer == NULL) 909 return; 910 911 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 912 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 913 914 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 915 buffer[count++] = cpu_to_le32(0x80000000); 916 buffer[count++] = cpu_to_le32(0x80000000); 917 918 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 919 for (ext = sect->section; ext->extent != NULL; ++ext) { 920 if (sect->id == SECT_CONTEXT) { 921 buffer[count++] = 922 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 923 buffer[count++] = cpu_to_le32(ext->reg_index - 924 PACKET3_SET_CONTEXT_REG_START); 925 for (i = 0; i < ext->reg_count; i++) 926 buffer[count++] = cpu_to_le32(ext->extent[i]); 927 } else { 928 return; 929 } 930 } 931 } 932 933 ctx_reg_offset = 934 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 935 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 936 buffer[count++] = cpu_to_le32(ctx_reg_offset); 937 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 938 939 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 940 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 941 942 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 943 buffer[count++] = cpu_to_le32(0); 944 } 945 946 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 947 { 948 /* clear state block */ 949 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 950 &adev->gfx.rlc.clear_state_gpu_addr, 951 (void **)&adev->gfx.rlc.cs_ptr); 952 953 /* jump table block */ 954 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 955 &adev->gfx.rlc.cp_table_gpu_addr, 956 (void **)&adev->gfx.rlc.cp_table_ptr); 957 } 958 959 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 960 { 961 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 962 963 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 964 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 965 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 966 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 967 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 968 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 969 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 970 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 971 adev->gfx.rlc.rlcg_reg_access_supported = true; 972 } 973 974 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 975 { 976 const struct cs_section_def *cs_data; 977 int r; 978 979 adev->gfx.rlc.cs_data = gfx11_cs_data; 980 981 cs_data = adev->gfx.rlc.cs_data; 982 983 if (cs_data) { 984 /* init clear state block */ 985 r = amdgpu_gfx_rlc_init_csb(adev); 986 if (r) 987 return r; 988 } 989 990 /* init spm vmid with 0xf */ 991 if (adev->gfx.rlc.funcs->update_spm_vmid) 992 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 993 994 return 0; 995 } 996 997 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 998 { 999 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1000 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1001 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 1002 } 1003 1004 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 1005 { 1006 int r; 1007 1008 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1009 1010 amdgpu_gfx_graphics_queue_acquire(adev); 1011 1012 r = gfx_v11_0_init_microcode(adev); 1013 if (r) 1014 DRM_ERROR("Failed to load gfx firmware!\n"); 1015 1016 return r; 1017 } 1018 1019 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 1020 { 1021 int r; 1022 u32 *hpd; 1023 size_t mec_hpd_size; 1024 1025 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1026 1027 /* take ownership of the relevant compute queues */ 1028 amdgpu_gfx_compute_queue_acquire(adev); 1029 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 1030 1031 if (mec_hpd_size) { 1032 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1033 AMDGPU_GEM_DOMAIN_GTT, 1034 &adev->gfx.mec.hpd_eop_obj, 1035 &adev->gfx.mec.hpd_eop_gpu_addr, 1036 (void **)&hpd); 1037 if (r) { 1038 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1039 gfx_v11_0_mec_fini(adev); 1040 return r; 1041 } 1042 1043 memset(hpd, 0, mec_hpd_size); 1044 1045 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1046 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1047 } 1048 1049 return 0; 1050 } 1051 1052 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1053 { 1054 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1055 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1056 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1057 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1058 } 1059 1060 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1061 uint32_t thread, uint32_t regno, 1062 uint32_t num, uint32_t *out) 1063 { 1064 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1065 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1066 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1067 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1068 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1069 while (num--) 1070 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1071 } 1072 1073 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1074 { 1075 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1076 * field when performing a select_se_sh so it should be 1077 * zero here */ 1078 WARN_ON(simd != 0); 1079 1080 /* type 2 wave data */ 1081 dst[(*no_fields)++] = 2; 1082 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1083 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1084 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1085 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1086 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1087 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1088 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1089 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1090 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1091 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1092 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1093 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1094 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1095 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1096 } 1097 1098 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1099 uint32_t wave, uint32_t start, 1100 uint32_t size, uint32_t *dst) 1101 { 1102 WARN_ON(simd != 0); 1103 1104 wave_read_regs( 1105 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1106 dst); 1107 } 1108 1109 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1110 uint32_t wave, uint32_t thread, 1111 uint32_t start, uint32_t size, 1112 uint32_t *dst) 1113 { 1114 wave_read_regs( 1115 adev, wave, thread, 1116 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1117 } 1118 1119 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1120 u32 me, u32 pipe, u32 q, u32 vm) 1121 { 1122 soc21_grbm_select(adev, me, pipe, q, vm); 1123 } 1124 1125 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1126 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1127 .select_se_sh = &gfx_v11_0_select_se_sh, 1128 .read_wave_data = &gfx_v11_0_read_wave_data, 1129 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1130 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1131 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1132 .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, 1133 }; 1134 1135 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1136 { 1137 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 1138 1139 switch (adev->ip_versions[GC_HWIP][0]) { 1140 case IP_VERSION(11, 0, 0): 1141 case IP_VERSION(11, 0, 2): 1142 adev->gfx.config.max_hw_contexts = 8; 1143 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1144 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1145 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1146 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1147 break; 1148 case IP_VERSION(11, 0, 1): 1149 adev->gfx.config.max_hw_contexts = 8; 1150 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1151 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1152 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1153 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1154 break; 1155 default: 1156 BUG(); 1157 break; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1164 int me, int pipe, int queue) 1165 { 1166 int r; 1167 struct amdgpu_ring *ring; 1168 unsigned int irq_type; 1169 1170 ring = &adev->gfx.gfx_ring[ring_id]; 1171 1172 ring->me = me; 1173 ring->pipe = pipe; 1174 ring->queue = queue; 1175 1176 ring->ring_obj = NULL; 1177 ring->use_doorbell = true; 1178 1179 if (!ring_id) 1180 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1181 else 1182 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1183 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1184 1185 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1186 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1187 AMDGPU_RING_PRIO_DEFAULT, NULL); 1188 if (r) 1189 return r; 1190 return 0; 1191 } 1192 1193 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1194 int mec, int pipe, int queue) 1195 { 1196 int r; 1197 unsigned irq_type; 1198 struct amdgpu_ring *ring; 1199 unsigned int hw_prio; 1200 1201 ring = &adev->gfx.compute_ring[ring_id]; 1202 1203 /* mec0 is me1 */ 1204 ring->me = mec + 1; 1205 ring->pipe = pipe; 1206 ring->queue = queue; 1207 1208 ring->ring_obj = NULL; 1209 ring->use_doorbell = true; 1210 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1211 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1212 + (ring_id * GFX11_MEC_HPD_SIZE); 1213 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1214 1215 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1216 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1217 + ring->pipe; 1218 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1219 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1220 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1221 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1222 hw_prio, NULL); 1223 if (r) 1224 return r; 1225 1226 return 0; 1227 } 1228 1229 static struct { 1230 SOC21_FIRMWARE_ID id; 1231 unsigned int offset; 1232 unsigned int size; 1233 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1234 1235 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1236 { 1237 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1238 1239 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1240 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1241 rlc_autoload_info[ucode->id].id = ucode->id; 1242 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1243 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1244 1245 ucode++; 1246 } 1247 } 1248 1249 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1250 { 1251 uint32_t total_size = 0; 1252 SOC21_FIRMWARE_ID id; 1253 1254 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1255 1256 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1257 total_size += rlc_autoload_info[id].size; 1258 1259 /* In case the offset in rlc toc ucode is aligned */ 1260 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1261 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1262 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1263 1264 return total_size; 1265 } 1266 1267 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1268 { 1269 int r; 1270 uint32_t total_size; 1271 1272 total_size = gfx_v11_0_calc_toc_total_size(adev); 1273 1274 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1275 AMDGPU_GEM_DOMAIN_VRAM, 1276 &adev->gfx.rlc.rlc_autoload_bo, 1277 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1278 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1279 1280 if (r) { 1281 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1282 return r; 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1289 SOC21_FIRMWARE_ID id, 1290 const void *fw_data, 1291 uint32_t fw_size, 1292 uint32_t *fw_autoload_mask) 1293 { 1294 uint32_t toc_offset; 1295 uint32_t toc_fw_size; 1296 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1297 1298 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1299 return; 1300 1301 toc_offset = rlc_autoload_info[id].offset; 1302 toc_fw_size = rlc_autoload_info[id].size; 1303 1304 if (fw_size == 0) 1305 fw_size = toc_fw_size; 1306 1307 if (fw_size > toc_fw_size) 1308 fw_size = toc_fw_size; 1309 1310 memcpy(ptr + toc_offset, fw_data, fw_size); 1311 1312 if (fw_size < toc_fw_size) 1313 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1314 1315 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1316 *(uint64_t *)fw_autoload_mask |= 1 << id; 1317 } 1318 1319 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1320 uint32_t *fw_autoload_mask) 1321 { 1322 void *data; 1323 uint32_t size; 1324 uint64_t *toc_ptr; 1325 1326 *(uint64_t *)fw_autoload_mask |= 0x1; 1327 1328 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1329 1330 data = adev->psp.toc.start_addr; 1331 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1332 1333 toc_ptr = (uint64_t *)data + size / 8 - 1; 1334 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1335 1336 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1337 data, size, fw_autoload_mask); 1338 } 1339 1340 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1341 uint32_t *fw_autoload_mask) 1342 { 1343 const __le32 *fw_data; 1344 uint32_t fw_size; 1345 const struct gfx_firmware_header_v1_0 *cp_hdr; 1346 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1347 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1348 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1349 uint16_t version_major, version_minor; 1350 1351 if (adev->gfx.rs64_enable) { 1352 /* pfp ucode */ 1353 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1354 adev->gfx.pfp_fw->data; 1355 /* instruction */ 1356 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1357 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1358 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1359 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1360 fw_data, fw_size, fw_autoload_mask); 1361 /* data */ 1362 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1363 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1364 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1365 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1366 fw_data, fw_size, fw_autoload_mask); 1367 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1368 fw_data, fw_size, fw_autoload_mask); 1369 /* me ucode */ 1370 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1371 adev->gfx.me_fw->data; 1372 /* instruction */ 1373 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1374 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1375 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1376 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1377 fw_data, fw_size, fw_autoload_mask); 1378 /* data */ 1379 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1380 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1381 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1382 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1383 fw_data, fw_size, fw_autoload_mask); 1384 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1385 fw_data, fw_size, fw_autoload_mask); 1386 /* mec ucode */ 1387 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1388 adev->gfx.mec_fw->data; 1389 /* instruction */ 1390 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1391 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1392 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1393 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1394 fw_data, fw_size, fw_autoload_mask); 1395 /* data */ 1396 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1397 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1398 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1399 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1400 fw_data, fw_size, fw_autoload_mask); 1401 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1402 fw_data, fw_size, fw_autoload_mask); 1403 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1404 fw_data, fw_size, fw_autoload_mask); 1405 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1406 fw_data, fw_size, fw_autoload_mask); 1407 } else { 1408 /* pfp ucode */ 1409 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1410 adev->gfx.pfp_fw->data; 1411 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1412 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1413 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1414 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1415 fw_data, fw_size, fw_autoload_mask); 1416 1417 /* me ucode */ 1418 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1419 adev->gfx.me_fw->data; 1420 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1421 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1422 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1423 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1424 fw_data, fw_size, fw_autoload_mask); 1425 1426 /* mec ucode */ 1427 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1428 adev->gfx.mec_fw->data; 1429 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1430 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1431 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1432 cp_hdr->jt_size * 4; 1433 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1434 fw_data, fw_size, fw_autoload_mask); 1435 } 1436 1437 /* rlc ucode */ 1438 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1439 adev->gfx.rlc_fw->data; 1440 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1441 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1442 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1443 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1444 fw_data, fw_size, fw_autoload_mask); 1445 1446 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1447 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1448 if (version_major == 2) { 1449 if (version_minor >= 2) { 1450 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1451 1452 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1453 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1454 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1455 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1456 fw_data, fw_size, fw_autoload_mask); 1457 1458 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1459 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1460 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1461 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1462 fw_data, fw_size, fw_autoload_mask); 1463 } 1464 } 1465 } 1466 1467 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1468 uint32_t *fw_autoload_mask) 1469 { 1470 const __le32 *fw_data; 1471 uint32_t fw_size; 1472 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1473 1474 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1475 adev->sdma.instance[0].fw->data; 1476 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1477 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1478 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1479 1480 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1481 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1482 1483 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1484 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1485 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1486 1487 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1488 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1489 } 1490 1491 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1492 uint32_t *fw_autoload_mask) 1493 { 1494 const __le32 *fw_data; 1495 unsigned fw_size; 1496 const struct mes_firmware_header_v1_0 *mes_hdr; 1497 int pipe, ucode_id, data_id; 1498 1499 for (pipe = 0; pipe < 2; pipe++) { 1500 if (pipe==0) { 1501 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1502 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1503 } else { 1504 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1505 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1506 } 1507 1508 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1509 adev->mes.fw[pipe]->data; 1510 1511 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1512 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1513 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1514 1515 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1516 ucode_id, fw_data, fw_size, fw_autoload_mask); 1517 1518 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1519 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1520 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1521 1522 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1523 data_id, fw_data, fw_size, fw_autoload_mask); 1524 } 1525 } 1526 1527 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1528 { 1529 uint32_t rlc_g_offset, rlc_g_size; 1530 uint64_t gpu_addr; 1531 uint32_t autoload_fw_id[2]; 1532 1533 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1534 1535 /* RLC autoload sequence 2: copy ucode */ 1536 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1537 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1538 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1539 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1540 1541 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1542 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1543 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1544 1545 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1546 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1547 1548 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1549 1550 /* RLC autoload sequence 3: load IMU fw */ 1551 if (adev->gfx.imu.funcs->load_microcode) 1552 adev->gfx.imu.funcs->load_microcode(adev); 1553 /* RLC autoload sequence 4 init IMU fw */ 1554 if (adev->gfx.imu.funcs->setup_imu) 1555 adev->gfx.imu.funcs->setup_imu(adev); 1556 if (adev->gfx.imu.funcs->start_imu) 1557 adev->gfx.imu.funcs->start_imu(adev); 1558 1559 /* RLC autoload sequence 5 disable gpa mode */ 1560 gfx_v11_0_disable_gpa_mode(adev); 1561 1562 return 0; 1563 } 1564 1565 static int gfx_v11_0_sw_init(void *handle) 1566 { 1567 int i, j, k, r, ring_id = 0; 1568 struct amdgpu_kiq *kiq; 1569 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1570 1571 adev->gfxhub.funcs->init(adev); 1572 1573 switch (adev->ip_versions[GC_HWIP][0]) { 1574 case IP_VERSION(11, 0, 0): 1575 case IP_VERSION(11, 0, 1): 1576 case IP_VERSION(11, 0, 2): 1577 adev->gfx.me.num_me = 1; 1578 adev->gfx.me.num_pipe_per_me = 1; 1579 adev->gfx.me.num_queue_per_pipe = 1; 1580 adev->gfx.mec.num_mec = 2; 1581 adev->gfx.mec.num_pipe_per_mec = 4; 1582 adev->gfx.mec.num_queue_per_pipe = 4; 1583 break; 1584 default: 1585 adev->gfx.me.num_me = 1; 1586 adev->gfx.me.num_pipe_per_me = 1; 1587 adev->gfx.me.num_queue_per_pipe = 1; 1588 adev->gfx.mec.num_mec = 1; 1589 adev->gfx.mec.num_pipe_per_mec = 4; 1590 adev->gfx.mec.num_queue_per_pipe = 8; 1591 break; 1592 } 1593 1594 /* EOP Event */ 1595 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1596 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1597 &adev->gfx.eop_irq); 1598 if (r) 1599 return r; 1600 1601 /* Privileged reg */ 1602 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1603 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1604 &adev->gfx.priv_reg_irq); 1605 if (r) 1606 return r; 1607 1608 /* Privileged inst */ 1609 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1610 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1611 &adev->gfx.priv_inst_irq); 1612 if (r) 1613 return r; 1614 1615 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1616 1617 if (adev->gfx.imu.funcs) { 1618 if (adev->gfx.imu.funcs->init_microcode) { 1619 r = adev->gfx.imu.funcs->init_microcode(adev); 1620 if (r) 1621 DRM_ERROR("Failed to load imu firmware!\n"); 1622 } 1623 } 1624 1625 r = gfx_v11_0_me_init(adev); 1626 if (r) 1627 return r; 1628 1629 r = gfx_v11_0_rlc_init(adev); 1630 if (r) { 1631 DRM_ERROR("Failed to init rlc BOs!\n"); 1632 return r; 1633 } 1634 1635 r = gfx_v11_0_mec_init(adev); 1636 if (r) { 1637 DRM_ERROR("Failed to init MEC BOs!\n"); 1638 return r; 1639 } 1640 1641 /* set up the gfx ring */ 1642 for (i = 0; i < adev->gfx.me.num_me; i++) { 1643 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1644 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1645 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1646 continue; 1647 1648 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1649 i, k, j); 1650 if (r) 1651 return r; 1652 ring_id++; 1653 } 1654 } 1655 } 1656 1657 ring_id = 0; 1658 /* set up the compute queues - allocate horizontally across pipes */ 1659 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1660 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1661 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1662 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1663 j)) 1664 continue; 1665 1666 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1667 i, k, j); 1668 if (r) 1669 return r; 1670 1671 ring_id++; 1672 } 1673 } 1674 } 1675 1676 if (!adev->enable_mes_kiq) { 1677 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1678 if (r) { 1679 DRM_ERROR("Failed to init KIQ BOs!\n"); 1680 return r; 1681 } 1682 1683 kiq = &adev->gfx.kiq; 1684 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1685 if (r) 1686 return r; 1687 } 1688 1689 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1690 if (r) 1691 return r; 1692 1693 /* allocate visible FB for rlc auto-loading fw */ 1694 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1695 r = gfx_v11_0_init_toc_microcode(adev); 1696 if (r) 1697 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1698 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1699 if (r) 1700 return r; 1701 } 1702 1703 r = gfx_v11_0_gpu_early_init(adev); 1704 if (r) 1705 return r; 1706 1707 return 0; 1708 } 1709 1710 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1711 { 1712 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1713 &adev->gfx.pfp.pfp_fw_gpu_addr, 1714 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1715 1716 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1717 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1718 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1719 } 1720 1721 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1722 { 1723 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1724 &adev->gfx.me.me_fw_gpu_addr, 1725 (void **)&adev->gfx.me.me_fw_ptr); 1726 1727 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1728 &adev->gfx.me.me_fw_data_gpu_addr, 1729 (void **)&adev->gfx.me.me_fw_data_ptr); 1730 } 1731 1732 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1733 { 1734 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1735 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1736 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1737 } 1738 1739 static int gfx_v11_0_sw_fini(void *handle) 1740 { 1741 int i; 1742 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1743 1744 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1745 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1746 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1747 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1748 1749 amdgpu_gfx_mqd_sw_fini(adev); 1750 1751 if (!adev->enable_mes_kiq) { 1752 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1753 amdgpu_gfx_kiq_fini(adev); 1754 } 1755 1756 gfx_v11_0_pfp_fini(adev); 1757 gfx_v11_0_me_fini(adev); 1758 gfx_v11_0_rlc_fini(adev); 1759 gfx_v11_0_mec_fini(adev); 1760 1761 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1762 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1763 1764 gfx_v11_0_free_microcode(adev); 1765 1766 return 0; 1767 } 1768 1769 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1770 u32 sh_num, u32 instance) 1771 { 1772 u32 data; 1773 1774 if (instance == 0xffffffff) 1775 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1776 INSTANCE_BROADCAST_WRITES, 1); 1777 else 1778 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1779 instance); 1780 1781 if (se_num == 0xffffffff) 1782 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1783 1); 1784 else 1785 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1786 1787 if (sh_num == 0xffffffff) 1788 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1789 1); 1790 else 1791 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1792 1793 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1794 } 1795 1796 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1797 { 1798 u32 data, mask; 1799 1800 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1801 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1802 1803 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1804 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1805 1806 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1807 adev->gfx.config.max_sh_per_se); 1808 1809 return (~data) & mask; 1810 } 1811 1812 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1813 { 1814 int i, j; 1815 u32 data; 1816 u32 active_rbs = 0; 1817 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1818 adev->gfx.config.max_sh_per_se; 1819 1820 mutex_lock(&adev->grbm_idx_mutex); 1821 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1822 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1823 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1824 data = gfx_v11_0_get_rb_active_bitmap(adev); 1825 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1826 rb_bitmap_width_per_sh); 1827 } 1828 } 1829 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1830 mutex_unlock(&adev->grbm_idx_mutex); 1831 1832 adev->gfx.config.backend_enable_mask = active_rbs; 1833 adev->gfx.config.num_rbs = hweight32(active_rbs); 1834 } 1835 1836 #define DEFAULT_SH_MEM_BASES (0x6000) 1837 #define LDS_APP_BASE 0x1 1838 #define SCRATCH_APP_BASE 0x2 1839 1840 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1841 { 1842 int i; 1843 uint32_t sh_mem_bases; 1844 uint32_t data; 1845 1846 /* 1847 * Configure apertures: 1848 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1849 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1850 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1851 */ 1852 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1853 SCRATCH_APP_BASE; 1854 1855 mutex_lock(&adev->srbm_mutex); 1856 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1857 soc21_grbm_select(adev, 0, 0, 0, i); 1858 /* CP and shaders */ 1859 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1860 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1861 1862 /* Enable trap for each kfd vmid. */ 1863 data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL)); 1864 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1865 } 1866 soc21_grbm_select(adev, 0, 0, 0, 0); 1867 mutex_unlock(&adev->srbm_mutex); 1868 1869 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1870 acccess. These should be enabled by FW for target VMIDs. */ 1871 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1872 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1873 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1874 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1875 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1876 } 1877 } 1878 1879 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1880 { 1881 int vmid; 1882 1883 /* 1884 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1885 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1886 * the driver can enable them for graphics. VMID0 should maintain 1887 * access so that HWS firmware can save/restore entries. 1888 */ 1889 for (vmid = 1; vmid < 16; vmid++) { 1890 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1891 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1892 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1893 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1894 } 1895 } 1896 1897 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1898 { 1899 /* TODO: harvest feature to be added later. */ 1900 } 1901 1902 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1903 { 1904 /* TCCs are global (not instanced). */ 1905 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1906 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1907 1908 adev->gfx.config.tcc_disabled_mask = 1909 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1910 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1911 } 1912 1913 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1914 { 1915 u32 tmp; 1916 int i; 1917 1918 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1919 1920 gfx_v11_0_setup_rb(adev); 1921 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1922 gfx_v11_0_get_tcc_info(adev); 1923 adev->gfx.config.pa_sc_tile_steering_override = 0; 1924 1925 /* XXX SH_MEM regs */ 1926 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1927 mutex_lock(&adev->srbm_mutex); 1928 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1929 soc21_grbm_select(adev, 0, 0, 0, i); 1930 /* CP and shaders */ 1931 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1932 if (i != 0) { 1933 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1934 (adev->gmc.private_aperture_start >> 48)); 1935 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1936 (adev->gmc.shared_aperture_start >> 48)); 1937 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1938 } 1939 } 1940 soc21_grbm_select(adev, 0, 0, 0, 0); 1941 1942 mutex_unlock(&adev->srbm_mutex); 1943 1944 gfx_v11_0_init_compute_vmid(adev); 1945 gfx_v11_0_init_gds_vmid(adev); 1946 } 1947 1948 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1949 bool enable) 1950 { 1951 u32 tmp; 1952 1953 if (amdgpu_sriov_vf(adev)) 1954 return; 1955 1956 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1957 1958 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1959 enable ? 1 : 0); 1960 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1961 enable ? 1 : 0); 1962 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1963 enable ? 1 : 0); 1964 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1965 enable ? 1 : 0); 1966 1967 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1968 } 1969 1970 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1971 { 1972 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1973 1974 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1975 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1976 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1977 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1978 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1979 1980 return 0; 1981 } 1982 1983 void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1984 { 1985 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1986 1987 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1988 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1989 } 1990 1991 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1992 { 1993 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1994 udelay(50); 1995 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1996 udelay(50); 1997 } 1998 1999 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2000 bool enable) 2001 { 2002 uint32_t rlc_pg_cntl; 2003 2004 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2005 2006 if (!enable) { 2007 /* RLC_PG_CNTL[23] = 0 (default) 2008 * RLC will wait for handshake acks with SMU 2009 * GFXOFF will be enabled 2010 * RLC_PG_CNTL[23] = 1 2011 * RLC will not issue any message to SMU 2012 * hence no handshake between SMU & RLC 2013 * GFXOFF will be disabled 2014 */ 2015 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2016 } else 2017 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2018 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2019 } 2020 2021 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2022 { 2023 /* TODO: enable rlc & smu handshake until smu 2024 * and gfxoff feature works as expected */ 2025 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2026 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2027 2028 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2029 udelay(50); 2030 } 2031 2032 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2033 { 2034 uint32_t tmp; 2035 2036 /* enable Save Restore Machine */ 2037 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2038 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2039 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2040 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2041 } 2042 2043 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2044 { 2045 const struct rlc_firmware_header_v2_0 *hdr; 2046 const __le32 *fw_data; 2047 unsigned i, fw_size; 2048 2049 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2050 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2051 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2052 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2053 2054 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2055 RLCG_UCODE_LOADING_START_ADDRESS); 2056 2057 for (i = 0; i < fw_size; i++) 2058 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2059 le32_to_cpup(fw_data++)); 2060 2061 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2062 } 2063 2064 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2065 { 2066 const struct rlc_firmware_header_v2_2 *hdr; 2067 const __le32 *fw_data; 2068 unsigned i, fw_size; 2069 u32 tmp; 2070 2071 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2072 2073 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2074 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2075 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2076 2077 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2078 2079 for (i = 0; i < fw_size; i++) { 2080 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2081 msleep(1); 2082 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2083 le32_to_cpup(fw_data++)); 2084 } 2085 2086 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2087 2088 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2089 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2090 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2091 2092 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2093 for (i = 0; i < fw_size; i++) { 2094 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2095 msleep(1); 2096 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2097 le32_to_cpup(fw_data++)); 2098 } 2099 2100 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2101 2102 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2103 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2104 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2105 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2106 } 2107 2108 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2109 { 2110 const struct rlc_firmware_header_v2_3 *hdr; 2111 const __le32 *fw_data; 2112 unsigned i, fw_size; 2113 u32 tmp; 2114 2115 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2116 2117 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2118 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2119 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2120 2121 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2122 2123 for (i = 0; i < fw_size; i++) { 2124 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2125 msleep(1); 2126 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2127 le32_to_cpup(fw_data++)); 2128 } 2129 2130 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2131 2132 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2133 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2134 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2135 2136 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2137 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2138 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2139 2140 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2141 2142 for (i = 0; i < fw_size; i++) { 2143 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2144 msleep(1); 2145 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2146 le32_to_cpup(fw_data++)); 2147 } 2148 2149 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2150 2151 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2152 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2153 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2154 } 2155 2156 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2157 { 2158 const struct rlc_firmware_header_v2_0 *hdr; 2159 uint16_t version_major; 2160 uint16_t version_minor; 2161 2162 if (!adev->gfx.rlc_fw) 2163 return -EINVAL; 2164 2165 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2166 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2167 2168 version_major = le16_to_cpu(hdr->header.header_version_major); 2169 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2170 2171 if (version_major == 2) { 2172 gfx_v11_0_load_rlcg_microcode(adev); 2173 if (amdgpu_dpm == 1) { 2174 if (version_minor >= 2) 2175 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2176 if (version_minor == 3) 2177 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2178 } 2179 2180 return 0; 2181 } 2182 2183 return -EINVAL; 2184 } 2185 2186 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2187 { 2188 int r; 2189 2190 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2191 gfx_v11_0_init_csb(adev); 2192 2193 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2194 gfx_v11_0_rlc_enable_srm(adev); 2195 } else { 2196 if (amdgpu_sriov_vf(adev)) { 2197 gfx_v11_0_init_csb(adev); 2198 return 0; 2199 } 2200 2201 adev->gfx.rlc.funcs->stop(adev); 2202 2203 /* disable CG */ 2204 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2205 2206 /* disable PG */ 2207 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2208 2209 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2210 /* legacy rlc firmware loading */ 2211 r = gfx_v11_0_rlc_load_microcode(adev); 2212 if (r) 2213 return r; 2214 } 2215 2216 gfx_v11_0_init_csb(adev); 2217 2218 adev->gfx.rlc.funcs->start(adev); 2219 } 2220 return 0; 2221 } 2222 2223 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2224 { 2225 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2226 uint32_t tmp; 2227 int i; 2228 2229 /* Trigger an invalidation of the L1 instruction caches */ 2230 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2231 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2232 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2233 2234 /* Wait for invalidation complete */ 2235 for (i = 0; i < usec_timeout; i++) { 2236 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2237 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2238 INVALIDATE_CACHE_COMPLETE)) 2239 break; 2240 udelay(1); 2241 } 2242 2243 if (i >= usec_timeout) { 2244 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2245 return -EINVAL; 2246 } 2247 2248 if (amdgpu_emu_mode == 1) 2249 adev->hdp.funcs->flush_hdp(adev, NULL); 2250 2251 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2252 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2253 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2254 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2255 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2256 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2257 2258 /* Program me ucode address into intruction cache address register */ 2259 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2260 lower_32_bits(addr) & 0xFFFFF000); 2261 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2262 upper_32_bits(addr)); 2263 2264 return 0; 2265 } 2266 2267 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2268 { 2269 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2270 uint32_t tmp; 2271 int i; 2272 2273 /* Trigger an invalidation of the L1 instruction caches */ 2274 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2275 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2276 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2277 2278 /* Wait for invalidation complete */ 2279 for (i = 0; i < usec_timeout; i++) { 2280 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2281 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2282 INVALIDATE_CACHE_COMPLETE)) 2283 break; 2284 udelay(1); 2285 } 2286 2287 if (i >= usec_timeout) { 2288 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2289 return -EINVAL; 2290 } 2291 2292 if (amdgpu_emu_mode == 1) 2293 adev->hdp.funcs->flush_hdp(adev, NULL); 2294 2295 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2296 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2297 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2298 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2299 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2300 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2301 2302 /* Program pfp ucode address into intruction cache address register */ 2303 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2304 lower_32_bits(addr) & 0xFFFFF000); 2305 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2306 upper_32_bits(addr)); 2307 2308 return 0; 2309 } 2310 2311 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2312 { 2313 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2314 uint32_t tmp; 2315 int i; 2316 2317 /* Trigger an invalidation of the L1 instruction caches */ 2318 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2319 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2320 2321 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2322 2323 /* Wait for invalidation complete */ 2324 for (i = 0; i < usec_timeout; i++) { 2325 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2326 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2327 INVALIDATE_CACHE_COMPLETE)) 2328 break; 2329 udelay(1); 2330 } 2331 2332 if (i >= usec_timeout) { 2333 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2334 return -EINVAL; 2335 } 2336 2337 if (amdgpu_emu_mode == 1) 2338 adev->hdp.funcs->flush_hdp(adev, NULL); 2339 2340 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2341 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2342 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2343 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2344 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2345 2346 /* Program mec1 ucode address into intruction cache address register */ 2347 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2348 lower_32_bits(addr) & 0xFFFFF000); 2349 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2350 upper_32_bits(addr)); 2351 2352 return 0; 2353 } 2354 2355 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2356 { 2357 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2358 uint32_t tmp; 2359 unsigned i, pipe_id; 2360 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2361 2362 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2363 adev->gfx.pfp_fw->data; 2364 2365 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2366 lower_32_bits(addr)); 2367 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2368 upper_32_bits(addr)); 2369 2370 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2371 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2372 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2373 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2374 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2375 2376 /* 2377 * Programming any of the CP_PFP_IC_BASE registers 2378 * forces invalidation of the ME L1 I$. Wait for the 2379 * invalidation complete 2380 */ 2381 for (i = 0; i < usec_timeout; i++) { 2382 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2383 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2384 INVALIDATE_CACHE_COMPLETE)) 2385 break; 2386 udelay(1); 2387 } 2388 2389 if (i >= usec_timeout) { 2390 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2391 return -EINVAL; 2392 } 2393 2394 /* Prime the L1 instruction caches */ 2395 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2396 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2397 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2398 /* Waiting for cache primed*/ 2399 for (i = 0; i < usec_timeout; i++) { 2400 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2401 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2402 ICACHE_PRIMED)) 2403 break; 2404 udelay(1); 2405 } 2406 2407 if (i >= usec_timeout) { 2408 dev_err(adev->dev, "failed to prime instruction cache\n"); 2409 return -EINVAL; 2410 } 2411 2412 mutex_lock(&adev->srbm_mutex); 2413 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2414 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2415 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2416 (pfp_hdr->ucode_start_addr_hi << 30) | 2417 (pfp_hdr->ucode_start_addr_lo >> 2)); 2418 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2419 pfp_hdr->ucode_start_addr_hi >> 2); 2420 2421 /* 2422 * Program CP_ME_CNTL to reset given PIPE to take 2423 * effect of CP_PFP_PRGRM_CNTR_START. 2424 */ 2425 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2426 if (pipe_id == 0) 2427 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2428 PFP_PIPE0_RESET, 1); 2429 else 2430 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2431 PFP_PIPE1_RESET, 1); 2432 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2433 2434 /* Clear pfp pipe0 reset bit. */ 2435 if (pipe_id == 0) 2436 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2437 PFP_PIPE0_RESET, 0); 2438 else 2439 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2440 PFP_PIPE1_RESET, 0); 2441 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2442 2443 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2444 lower_32_bits(addr2)); 2445 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2446 upper_32_bits(addr2)); 2447 } 2448 soc21_grbm_select(adev, 0, 0, 0, 0); 2449 mutex_unlock(&adev->srbm_mutex); 2450 2451 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2452 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2453 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2454 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2455 2456 /* Invalidate the data caches */ 2457 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2458 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2459 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2460 2461 for (i = 0; i < usec_timeout; i++) { 2462 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2463 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2464 INVALIDATE_DCACHE_COMPLETE)) 2465 break; 2466 udelay(1); 2467 } 2468 2469 if (i >= usec_timeout) { 2470 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2471 return -EINVAL; 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2478 { 2479 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2480 uint32_t tmp; 2481 unsigned i, pipe_id; 2482 const struct gfx_firmware_header_v2_0 *me_hdr; 2483 2484 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2485 adev->gfx.me_fw->data; 2486 2487 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2488 lower_32_bits(addr)); 2489 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2490 upper_32_bits(addr)); 2491 2492 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2493 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2494 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2495 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2496 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2497 2498 /* 2499 * Programming any of the CP_ME_IC_BASE registers 2500 * forces invalidation of the ME L1 I$. Wait for the 2501 * invalidation complete 2502 */ 2503 for (i = 0; i < usec_timeout; i++) { 2504 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2505 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2506 INVALIDATE_CACHE_COMPLETE)) 2507 break; 2508 udelay(1); 2509 } 2510 2511 if (i >= usec_timeout) { 2512 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2513 return -EINVAL; 2514 } 2515 2516 /* Prime the instruction caches */ 2517 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2518 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2519 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2520 2521 /* Waiting for instruction cache primed*/ 2522 for (i = 0; i < usec_timeout; i++) { 2523 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2524 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2525 ICACHE_PRIMED)) 2526 break; 2527 udelay(1); 2528 } 2529 2530 if (i >= usec_timeout) { 2531 dev_err(adev->dev, "failed to prime instruction cache\n"); 2532 return -EINVAL; 2533 } 2534 2535 mutex_lock(&adev->srbm_mutex); 2536 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2537 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2538 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2539 (me_hdr->ucode_start_addr_hi << 30) | 2540 (me_hdr->ucode_start_addr_lo >> 2) ); 2541 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2542 me_hdr->ucode_start_addr_hi>>2); 2543 2544 /* 2545 * Program CP_ME_CNTL to reset given PIPE to take 2546 * effect of CP_PFP_PRGRM_CNTR_START. 2547 */ 2548 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2549 if (pipe_id == 0) 2550 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2551 ME_PIPE0_RESET, 1); 2552 else 2553 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2554 ME_PIPE1_RESET, 1); 2555 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2556 2557 /* Clear pfp pipe0 reset bit. */ 2558 if (pipe_id == 0) 2559 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2560 ME_PIPE0_RESET, 0); 2561 else 2562 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2563 ME_PIPE1_RESET, 0); 2564 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2565 2566 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2567 lower_32_bits(addr2)); 2568 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2569 upper_32_bits(addr2)); 2570 } 2571 soc21_grbm_select(adev, 0, 0, 0, 0); 2572 mutex_unlock(&adev->srbm_mutex); 2573 2574 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2575 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2576 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2577 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2578 2579 /* Invalidate the data caches */ 2580 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2581 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2582 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2583 2584 for (i = 0; i < usec_timeout; i++) { 2585 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2586 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2587 INVALIDATE_DCACHE_COMPLETE)) 2588 break; 2589 udelay(1); 2590 } 2591 2592 if (i >= usec_timeout) { 2593 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2594 return -EINVAL; 2595 } 2596 2597 return 0; 2598 } 2599 2600 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2601 { 2602 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2603 uint32_t tmp; 2604 unsigned i; 2605 const struct gfx_firmware_header_v2_0 *mec_hdr; 2606 2607 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2608 adev->gfx.mec_fw->data; 2609 2610 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2611 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2612 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2613 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2614 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2615 2616 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2617 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2618 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2619 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2620 2621 mutex_lock(&adev->srbm_mutex); 2622 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2623 soc21_grbm_select(adev, 1, i, 0, 0); 2624 2625 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2626 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2627 upper_32_bits(addr2)); 2628 2629 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2630 mec_hdr->ucode_start_addr_lo >> 2 | 2631 mec_hdr->ucode_start_addr_hi << 30); 2632 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2633 mec_hdr->ucode_start_addr_hi >> 2); 2634 2635 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2636 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2637 upper_32_bits(addr)); 2638 } 2639 mutex_unlock(&adev->srbm_mutex); 2640 soc21_grbm_select(adev, 0, 0, 0, 0); 2641 2642 /* Trigger an invalidation of the L1 instruction caches */ 2643 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2644 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2645 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2646 2647 /* Wait for invalidation complete */ 2648 for (i = 0; i < usec_timeout; i++) { 2649 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2650 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2651 INVALIDATE_DCACHE_COMPLETE)) 2652 break; 2653 udelay(1); 2654 } 2655 2656 if (i >= usec_timeout) { 2657 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2658 return -EINVAL; 2659 } 2660 2661 /* Trigger an invalidation of the L1 instruction caches */ 2662 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2663 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2664 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2665 2666 /* Wait for invalidation complete */ 2667 for (i = 0; i < usec_timeout; i++) { 2668 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2669 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2670 INVALIDATE_CACHE_COMPLETE)) 2671 break; 2672 udelay(1); 2673 } 2674 2675 if (i >= usec_timeout) { 2676 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2677 return -EINVAL; 2678 } 2679 2680 return 0; 2681 } 2682 2683 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2684 { 2685 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2686 const struct gfx_firmware_header_v2_0 *me_hdr; 2687 const struct gfx_firmware_header_v2_0 *mec_hdr; 2688 uint32_t pipe_id, tmp; 2689 2690 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2691 adev->gfx.mec_fw->data; 2692 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2693 adev->gfx.me_fw->data; 2694 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2695 adev->gfx.pfp_fw->data; 2696 2697 /* config pfp program start addr */ 2698 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2699 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2700 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2701 (pfp_hdr->ucode_start_addr_hi << 30) | 2702 (pfp_hdr->ucode_start_addr_lo >> 2)); 2703 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2704 pfp_hdr->ucode_start_addr_hi >> 2); 2705 } 2706 soc21_grbm_select(adev, 0, 0, 0, 0); 2707 2708 /* reset pfp pipe */ 2709 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2710 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2711 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2712 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2713 2714 /* clear pfp pipe reset */ 2715 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2716 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2717 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2718 2719 /* config me program start addr */ 2720 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2721 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2722 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2723 (me_hdr->ucode_start_addr_hi << 30) | 2724 (me_hdr->ucode_start_addr_lo >> 2) ); 2725 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2726 me_hdr->ucode_start_addr_hi>>2); 2727 } 2728 soc21_grbm_select(adev, 0, 0, 0, 0); 2729 2730 /* reset me pipe */ 2731 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2732 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2733 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2734 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2735 2736 /* clear me pipe reset */ 2737 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2738 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2739 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2740 2741 /* config mec program start addr */ 2742 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2743 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2744 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2745 mec_hdr->ucode_start_addr_lo >> 2 | 2746 mec_hdr->ucode_start_addr_hi << 30); 2747 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2748 mec_hdr->ucode_start_addr_hi >> 2); 2749 } 2750 soc21_grbm_select(adev, 0, 0, 0, 0); 2751 } 2752 2753 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2754 { 2755 uint32_t cp_status; 2756 uint32_t bootload_status; 2757 int i, r; 2758 uint64_t addr, addr2; 2759 2760 for (i = 0; i < adev->usec_timeout; i++) { 2761 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2762 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2763 if ((cp_status == 0) && 2764 (REG_GET_FIELD(bootload_status, 2765 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2766 break; 2767 } 2768 udelay(1); 2769 } 2770 2771 if (i >= adev->usec_timeout) { 2772 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2773 return -ETIMEDOUT; 2774 } 2775 2776 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2777 if (adev->gfx.rs64_enable) { 2778 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2779 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2780 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2781 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2782 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2783 if (r) 2784 return r; 2785 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2786 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2787 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2788 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2789 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2790 if (r) 2791 return r; 2792 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2793 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2794 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2795 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2796 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2797 if (r) 2798 return r; 2799 } else { 2800 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2801 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2802 r = gfx_v11_0_config_me_cache(adev, addr); 2803 if (r) 2804 return r; 2805 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2806 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2807 r = gfx_v11_0_config_pfp_cache(adev, addr); 2808 if (r) 2809 return r; 2810 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2811 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2812 r = gfx_v11_0_config_mec_cache(adev, addr); 2813 if (r) 2814 return r; 2815 } 2816 } 2817 2818 return 0; 2819 } 2820 2821 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2822 { 2823 int i; 2824 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2825 2826 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2827 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2828 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2829 2830 for (i = 0; i < adev->usec_timeout; i++) { 2831 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2832 break; 2833 udelay(1); 2834 } 2835 2836 if (i >= adev->usec_timeout) 2837 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2838 2839 return 0; 2840 } 2841 2842 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2843 { 2844 int r; 2845 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2846 const __le32 *fw_data; 2847 unsigned i, fw_size; 2848 2849 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2850 adev->gfx.pfp_fw->data; 2851 2852 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2853 2854 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2855 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2856 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2857 2858 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2859 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2860 &adev->gfx.pfp.pfp_fw_obj, 2861 &adev->gfx.pfp.pfp_fw_gpu_addr, 2862 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2863 if (r) { 2864 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2865 gfx_v11_0_pfp_fini(adev); 2866 return r; 2867 } 2868 2869 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2870 2871 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2872 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2873 2874 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2875 2876 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2877 2878 for (i = 0; i < pfp_hdr->jt_size; i++) 2879 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2880 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2881 2882 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2883 2884 return 0; 2885 } 2886 2887 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2888 { 2889 int r; 2890 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2891 const __le32 *fw_ucode, *fw_data; 2892 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2893 uint32_t tmp; 2894 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2895 2896 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2897 adev->gfx.pfp_fw->data; 2898 2899 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2900 2901 /* instruction */ 2902 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2903 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2904 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2905 /* data */ 2906 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2907 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2908 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2909 2910 /* 64kb align */ 2911 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2912 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2913 &adev->gfx.pfp.pfp_fw_obj, 2914 &adev->gfx.pfp.pfp_fw_gpu_addr, 2915 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2916 if (r) { 2917 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2918 gfx_v11_0_pfp_fini(adev); 2919 return r; 2920 } 2921 2922 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2923 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2924 &adev->gfx.pfp.pfp_fw_data_obj, 2925 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2926 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2927 if (r) { 2928 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2929 gfx_v11_0_pfp_fini(adev); 2930 return r; 2931 } 2932 2933 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2934 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2935 2936 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2937 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2938 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2939 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2940 2941 if (amdgpu_emu_mode == 1) 2942 adev->hdp.funcs->flush_hdp(adev, NULL); 2943 2944 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2945 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2946 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2947 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2948 2949 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2950 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2951 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2952 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2953 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2954 2955 /* 2956 * Programming any of the CP_PFP_IC_BASE registers 2957 * forces invalidation of the ME L1 I$. Wait for the 2958 * invalidation complete 2959 */ 2960 for (i = 0; i < usec_timeout; i++) { 2961 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2962 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2963 INVALIDATE_CACHE_COMPLETE)) 2964 break; 2965 udelay(1); 2966 } 2967 2968 if (i >= usec_timeout) { 2969 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2970 return -EINVAL; 2971 } 2972 2973 /* Prime the L1 instruction caches */ 2974 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2975 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2976 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2977 /* Waiting for cache primed*/ 2978 for (i = 0; i < usec_timeout; i++) { 2979 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2980 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2981 ICACHE_PRIMED)) 2982 break; 2983 udelay(1); 2984 } 2985 2986 if (i >= usec_timeout) { 2987 dev_err(adev->dev, "failed to prime instruction cache\n"); 2988 return -EINVAL; 2989 } 2990 2991 mutex_lock(&adev->srbm_mutex); 2992 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2993 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2994 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2995 (pfp_hdr->ucode_start_addr_hi << 30) | 2996 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2997 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2998 pfp_hdr->ucode_start_addr_hi>>2); 2999 3000 /* 3001 * Program CP_ME_CNTL to reset given PIPE to take 3002 * effect of CP_PFP_PRGRM_CNTR_START. 3003 */ 3004 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3005 if (pipe_id == 0) 3006 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3007 PFP_PIPE0_RESET, 1); 3008 else 3009 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3010 PFP_PIPE1_RESET, 1); 3011 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3012 3013 /* Clear pfp pipe0 reset bit. */ 3014 if (pipe_id == 0) 3015 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3016 PFP_PIPE0_RESET, 0); 3017 else 3018 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3019 PFP_PIPE1_RESET, 0); 3020 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3021 3022 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3023 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3024 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3025 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3026 } 3027 soc21_grbm_select(adev, 0, 0, 0, 0); 3028 mutex_unlock(&adev->srbm_mutex); 3029 3030 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3031 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3032 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3033 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3034 3035 /* Invalidate the data caches */ 3036 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3037 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3038 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3039 3040 for (i = 0; i < usec_timeout; i++) { 3041 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3042 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3043 INVALIDATE_DCACHE_COMPLETE)) 3044 break; 3045 udelay(1); 3046 } 3047 3048 if (i >= usec_timeout) { 3049 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3050 return -EINVAL; 3051 } 3052 3053 return 0; 3054 } 3055 3056 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3057 { 3058 int r; 3059 const struct gfx_firmware_header_v1_0 *me_hdr; 3060 const __le32 *fw_data; 3061 unsigned i, fw_size; 3062 3063 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3064 adev->gfx.me_fw->data; 3065 3066 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3067 3068 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3069 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3070 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3071 3072 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3073 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3074 &adev->gfx.me.me_fw_obj, 3075 &adev->gfx.me.me_fw_gpu_addr, 3076 (void **)&adev->gfx.me.me_fw_ptr); 3077 if (r) { 3078 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3079 gfx_v11_0_me_fini(adev); 3080 return r; 3081 } 3082 3083 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3084 3085 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3086 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3087 3088 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3089 3090 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3091 3092 for (i = 0; i < me_hdr->jt_size; i++) 3093 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3094 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3095 3096 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3097 3098 return 0; 3099 } 3100 3101 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3102 { 3103 int r; 3104 const struct gfx_firmware_header_v2_0 *me_hdr; 3105 const __le32 *fw_ucode, *fw_data; 3106 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3107 uint32_t tmp; 3108 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3109 3110 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3111 adev->gfx.me_fw->data; 3112 3113 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3114 3115 /* instruction */ 3116 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3117 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3118 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3119 /* data */ 3120 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3121 le32_to_cpu(me_hdr->data_offset_bytes)); 3122 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3123 3124 /* 64kb align*/ 3125 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3126 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3127 &adev->gfx.me.me_fw_obj, 3128 &adev->gfx.me.me_fw_gpu_addr, 3129 (void **)&adev->gfx.me.me_fw_ptr); 3130 if (r) { 3131 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3132 gfx_v11_0_me_fini(adev); 3133 return r; 3134 } 3135 3136 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3137 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3138 &adev->gfx.me.me_fw_data_obj, 3139 &adev->gfx.me.me_fw_data_gpu_addr, 3140 (void **)&adev->gfx.me.me_fw_data_ptr); 3141 if (r) { 3142 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3143 gfx_v11_0_pfp_fini(adev); 3144 return r; 3145 } 3146 3147 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3148 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3149 3150 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3151 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3152 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3153 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3154 3155 if (amdgpu_emu_mode == 1) 3156 adev->hdp.funcs->flush_hdp(adev, NULL); 3157 3158 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3159 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3160 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3161 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3162 3163 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3164 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3165 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3166 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3167 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3168 3169 /* 3170 * Programming any of the CP_ME_IC_BASE registers 3171 * forces invalidation of the ME L1 I$. Wait for the 3172 * invalidation complete 3173 */ 3174 for (i = 0; i < usec_timeout; i++) { 3175 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3176 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3177 INVALIDATE_CACHE_COMPLETE)) 3178 break; 3179 udelay(1); 3180 } 3181 3182 if (i >= usec_timeout) { 3183 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3184 return -EINVAL; 3185 } 3186 3187 /* Prime the instruction caches */ 3188 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3189 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3190 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3191 3192 /* Waiting for instruction cache primed*/ 3193 for (i = 0; i < usec_timeout; i++) { 3194 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3195 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3196 ICACHE_PRIMED)) 3197 break; 3198 udelay(1); 3199 } 3200 3201 if (i >= usec_timeout) { 3202 dev_err(adev->dev, "failed to prime instruction cache\n"); 3203 return -EINVAL; 3204 } 3205 3206 mutex_lock(&adev->srbm_mutex); 3207 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3208 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3209 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3210 (me_hdr->ucode_start_addr_hi << 30) | 3211 (me_hdr->ucode_start_addr_lo >> 2) ); 3212 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3213 me_hdr->ucode_start_addr_hi>>2); 3214 3215 /* 3216 * Program CP_ME_CNTL to reset given PIPE to take 3217 * effect of CP_PFP_PRGRM_CNTR_START. 3218 */ 3219 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3220 if (pipe_id == 0) 3221 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3222 ME_PIPE0_RESET, 1); 3223 else 3224 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3225 ME_PIPE1_RESET, 1); 3226 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3227 3228 /* Clear pfp pipe0 reset bit. */ 3229 if (pipe_id == 0) 3230 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3231 ME_PIPE0_RESET, 0); 3232 else 3233 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3234 ME_PIPE1_RESET, 0); 3235 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3236 3237 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3238 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3239 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3240 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3241 } 3242 soc21_grbm_select(adev, 0, 0, 0, 0); 3243 mutex_unlock(&adev->srbm_mutex); 3244 3245 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3246 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3247 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3248 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3249 3250 /* Invalidate the data caches */ 3251 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3252 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3253 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3254 3255 for (i = 0; i < usec_timeout; i++) { 3256 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3257 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3258 INVALIDATE_DCACHE_COMPLETE)) 3259 break; 3260 udelay(1); 3261 } 3262 3263 if (i >= usec_timeout) { 3264 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3265 return -EINVAL; 3266 } 3267 3268 return 0; 3269 } 3270 3271 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3272 { 3273 int r; 3274 3275 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3276 return -EINVAL; 3277 3278 gfx_v11_0_cp_gfx_enable(adev, false); 3279 3280 if (adev->gfx.rs64_enable) 3281 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3282 else 3283 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3284 if (r) { 3285 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3286 return r; 3287 } 3288 3289 if (adev->gfx.rs64_enable) 3290 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3291 else 3292 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3293 if (r) { 3294 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3295 return r; 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3302 { 3303 struct amdgpu_ring *ring; 3304 const struct cs_section_def *sect = NULL; 3305 const struct cs_extent_def *ext = NULL; 3306 int r, i; 3307 int ctx_reg_offset; 3308 3309 /* init the CP */ 3310 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3311 adev->gfx.config.max_hw_contexts - 1); 3312 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3313 3314 if (!amdgpu_async_gfx_ring) 3315 gfx_v11_0_cp_gfx_enable(adev, true); 3316 3317 ring = &adev->gfx.gfx_ring[0]; 3318 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3319 if (r) { 3320 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3321 return r; 3322 } 3323 3324 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3325 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3326 3327 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3328 amdgpu_ring_write(ring, 0x80000000); 3329 amdgpu_ring_write(ring, 0x80000000); 3330 3331 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3332 for (ext = sect->section; ext->extent != NULL; ++ext) { 3333 if (sect->id == SECT_CONTEXT) { 3334 amdgpu_ring_write(ring, 3335 PACKET3(PACKET3_SET_CONTEXT_REG, 3336 ext->reg_count)); 3337 amdgpu_ring_write(ring, ext->reg_index - 3338 PACKET3_SET_CONTEXT_REG_START); 3339 for (i = 0; i < ext->reg_count; i++) 3340 amdgpu_ring_write(ring, ext->extent[i]); 3341 } 3342 } 3343 } 3344 3345 ctx_reg_offset = 3346 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3347 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3348 amdgpu_ring_write(ring, ctx_reg_offset); 3349 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3350 3351 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3352 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3353 3354 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3355 amdgpu_ring_write(ring, 0); 3356 3357 amdgpu_ring_commit(ring); 3358 3359 /* submit cs packet to copy state 0 to next available state */ 3360 if (adev->gfx.num_gfx_rings > 1) { 3361 /* maximum supported gfx ring is 2 */ 3362 ring = &adev->gfx.gfx_ring[1]; 3363 r = amdgpu_ring_alloc(ring, 2); 3364 if (r) { 3365 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3366 return r; 3367 } 3368 3369 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3370 amdgpu_ring_write(ring, 0); 3371 3372 amdgpu_ring_commit(ring); 3373 } 3374 return 0; 3375 } 3376 3377 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3378 CP_PIPE_ID pipe) 3379 { 3380 u32 tmp; 3381 3382 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3383 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3384 3385 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3386 } 3387 3388 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3389 struct amdgpu_ring *ring) 3390 { 3391 u32 tmp; 3392 3393 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3394 if (ring->use_doorbell) { 3395 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3396 DOORBELL_OFFSET, ring->doorbell_index); 3397 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3398 DOORBELL_EN, 1); 3399 } else { 3400 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3401 DOORBELL_EN, 0); 3402 } 3403 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3404 3405 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3406 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3407 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3408 3409 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3410 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3411 } 3412 3413 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3414 { 3415 struct amdgpu_ring *ring; 3416 u32 tmp; 3417 u32 rb_bufsz; 3418 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3419 u32 i; 3420 3421 /* Set the write pointer delay */ 3422 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3423 3424 /* set the RB to use vmid 0 */ 3425 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3426 3427 /* Init gfx ring 0 for pipe 0 */ 3428 mutex_lock(&adev->srbm_mutex); 3429 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3430 3431 /* Set ring buffer size */ 3432 ring = &adev->gfx.gfx_ring[0]; 3433 rb_bufsz = order_base_2(ring->ring_size / 8); 3434 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3435 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3436 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3437 3438 /* Initialize the ring buffer's write pointers */ 3439 ring->wptr = 0; 3440 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3441 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3442 3443 /* set the wb address wether it's enabled or not */ 3444 rptr_addr = ring->rptr_gpu_addr; 3445 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3446 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3447 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3448 3449 wptr_gpu_addr = ring->wptr_gpu_addr; 3450 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3451 lower_32_bits(wptr_gpu_addr)); 3452 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3453 upper_32_bits(wptr_gpu_addr)); 3454 3455 mdelay(1); 3456 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3457 3458 rb_addr = ring->gpu_addr >> 8; 3459 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3460 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3461 3462 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3463 3464 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3465 mutex_unlock(&adev->srbm_mutex); 3466 3467 /* Init gfx ring 1 for pipe 1 */ 3468 if (adev->gfx.num_gfx_rings > 1) { 3469 mutex_lock(&adev->srbm_mutex); 3470 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3471 /* maximum supported gfx ring is 2 */ 3472 ring = &adev->gfx.gfx_ring[1]; 3473 rb_bufsz = order_base_2(ring->ring_size / 8); 3474 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3475 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3476 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3477 /* Initialize the ring buffer's write pointers */ 3478 ring->wptr = 0; 3479 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3480 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3481 /* Set the wb address wether it's enabled or not */ 3482 rptr_addr = ring->rptr_gpu_addr; 3483 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3484 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3485 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3486 wptr_gpu_addr = ring->wptr_gpu_addr; 3487 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3488 lower_32_bits(wptr_gpu_addr)); 3489 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3490 upper_32_bits(wptr_gpu_addr)); 3491 3492 mdelay(1); 3493 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3494 3495 rb_addr = ring->gpu_addr >> 8; 3496 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3497 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3498 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3499 3500 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3501 mutex_unlock(&adev->srbm_mutex); 3502 } 3503 /* Switch to pipe 0 */ 3504 mutex_lock(&adev->srbm_mutex); 3505 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3506 mutex_unlock(&adev->srbm_mutex); 3507 3508 /* start the ring */ 3509 gfx_v11_0_cp_gfx_start(adev); 3510 3511 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3512 ring = &adev->gfx.gfx_ring[i]; 3513 ring->sched.ready = true; 3514 } 3515 3516 return 0; 3517 } 3518 3519 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3520 { 3521 u32 data; 3522 3523 if (adev->gfx.rs64_enable) { 3524 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3525 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3526 enable ? 0 : 1); 3527 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3528 enable ? 0 : 1); 3529 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3530 enable ? 0 : 1); 3531 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3532 enable ? 0 : 1); 3533 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3534 enable ? 0 : 1); 3535 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3536 enable ? 1 : 0); 3537 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3538 enable ? 1 : 0); 3539 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3540 enable ? 1 : 0); 3541 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3542 enable ? 1 : 0); 3543 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3544 enable ? 0 : 1); 3545 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3546 } else { 3547 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3548 3549 if (enable) { 3550 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3551 if (!adev->enable_mes_kiq) 3552 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3553 MEC_ME2_HALT, 0); 3554 } else { 3555 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3556 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3557 } 3558 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3559 } 3560 3561 adev->gfx.kiq.ring.sched.ready = enable; 3562 3563 udelay(50); 3564 } 3565 3566 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3567 { 3568 const struct gfx_firmware_header_v1_0 *mec_hdr; 3569 const __le32 *fw_data; 3570 unsigned i, fw_size; 3571 u32 *fw = NULL; 3572 int r; 3573 3574 if (!adev->gfx.mec_fw) 3575 return -EINVAL; 3576 3577 gfx_v11_0_cp_compute_enable(adev, false); 3578 3579 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3580 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3581 3582 fw_data = (const __le32 *) 3583 (adev->gfx.mec_fw->data + 3584 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3585 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3586 3587 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3588 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3589 &adev->gfx.mec.mec_fw_obj, 3590 &adev->gfx.mec.mec_fw_gpu_addr, 3591 (void **)&fw); 3592 if (r) { 3593 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3594 gfx_v11_0_mec_fini(adev); 3595 return r; 3596 } 3597 3598 memcpy(fw, fw_data, fw_size); 3599 3600 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3601 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3602 3603 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3604 3605 /* MEC1 */ 3606 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3607 3608 for (i = 0; i < mec_hdr->jt_size; i++) 3609 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3610 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3611 3612 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3613 3614 return 0; 3615 } 3616 3617 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3618 { 3619 const struct gfx_firmware_header_v2_0 *mec_hdr; 3620 const __le32 *fw_ucode, *fw_data; 3621 u32 tmp, fw_ucode_size, fw_data_size; 3622 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3623 u32 *fw_ucode_ptr, *fw_data_ptr; 3624 int r; 3625 3626 if (!adev->gfx.mec_fw) 3627 return -EINVAL; 3628 3629 gfx_v11_0_cp_compute_enable(adev, false); 3630 3631 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3632 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3633 3634 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3635 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3636 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3637 3638 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3639 le32_to_cpu(mec_hdr->data_offset_bytes)); 3640 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3641 3642 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3643 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3644 &adev->gfx.mec.mec_fw_obj, 3645 &adev->gfx.mec.mec_fw_gpu_addr, 3646 (void **)&fw_ucode_ptr); 3647 if (r) { 3648 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3649 gfx_v11_0_mec_fini(adev); 3650 return r; 3651 } 3652 3653 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3654 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3655 &adev->gfx.mec.mec_fw_data_obj, 3656 &adev->gfx.mec.mec_fw_data_gpu_addr, 3657 (void **)&fw_data_ptr); 3658 if (r) { 3659 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3660 gfx_v11_0_mec_fini(adev); 3661 return r; 3662 } 3663 3664 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3665 memcpy(fw_data_ptr, fw_data, fw_data_size); 3666 3667 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3668 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3669 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3670 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3671 3672 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3673 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3674 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3675 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3676 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3677 3678 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3679 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3680 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3681 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3682 3683 mutex_lock(&adev->srbm_mutex); 3684 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3685 soc21_grbm_select(adev, 1, i, 0, 0); 3686 3687 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3688 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3689 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3690 3691 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3692 mec_hdr->ucode_start_addr_lo >> 2 | 3693 mec_hdr->ucode_start_addr_hi << 30); 3694 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3695 mec_hdr->ucode_start_addr_hi >> 2); 3696 3697 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3698 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3699 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3700 } 3701 mutex_unlock(&adev->srbm_mutex); 3702 soc21_grbm_select(adev, 0, 0, 0, 0); 3703 3704 /* Trigger an invalidation of the L1 instruction caches */ 3705 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3706 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3707 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3708 3709 /* Wait for invalidation complete */ 3710 for (i = 0; i < usec_timeout; i++) { 3711 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3712 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3713 INVALIDATE_DCACHE_COMPLETE)) 3714 break; 3715 udelay(1); 3716 } 3717 3718 if (i >= usec_timeout) { 3719 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3720 return -EINVAL; 3721 } 3722 3723 /* Trigger an invalidation of the L1 instruction caches */ 3724 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3725 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3726 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3727 3728 /* Wait for invalidation complete */ 3729 for (i = 0; i < usec_timeout; i++) { 3730 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3731 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3732 INVALIDATE_CACHE_COMPLETE)) 3733 break; 3734 udelay(1); 3735 } 3736 3737 if (i >= usec_timeout) { 3738 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3739 return -EINVAL; 3740 } 3741 3742 return 0; 3743 } 3744 3745 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3746 { 3747 uint32_t tmp; 3748 struct amdgpu_device *adev = ring->adev; 3749 3750 /* tell RLC which is KIQ queue */ 3751 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3752 tmp &= 0xffffff00; 3753 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3754 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3755 tmp |= 0x80; 3756 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3757 } 3758 3759 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3760 { 3761 /* set graphics engine doorbell range */ 3762 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3763 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3764 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3765 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3766 3767 /* set compute engine doorbell range */ 3768 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3769 (adev->doorbell_index.kiq * 2) << 2); 3770 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3771 (adev->doorbell_index.userqueue_end * 2) << 2); 3772 } 3773 3774 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3775 struct amdgpu_mqd_prop *prop) 3776 { 3777 struct v11_gfx_mqd *mqd = m; 3778 uint64_t hqd_gpu_addr, wb_gpu_addr; 3779 uint32_t tmp; 3780 uint32_t rb_bufsz; 3781 3782 /* set up gfx hqd wptr */ 3783 mqd->cp_gfx_hqd_wptr = 0; 3784 mqd->cp_gfx_hqd_wptr_hi = 0; 3785 3786 /* set the pointer to the MQD */ 3787 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3788 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3789 3790 /* set up mqd control */ 3791 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3792 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3793 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3794 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3795 mqd->cp_gfx_mqd_control = tmp; 3796 3797 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3798 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3799 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3800 mqd->cp_gfx_hqd_vmid = 0; 3801 3802 /* set up default queue priority level 3803 * 0x0 = low priority, 0x1 = high priority */ 3804 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3805 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3806 mqd->cp_gfx_hqd_queue_priority = tmp; 3807 3808 /* set up time quantum */ 3809 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3810 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3811 mqd->cp_gfx_hqd_quantum = tmp; 3812 3813 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3814 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3815 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3816 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3817 3818 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3819 wb_gpu_addr = prop->rptr_gpu_addr; 3820 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3821 mqd->cp_gfx_hqd_rptr_addr_hi = 3822 upper_32_bits(wb_gpu_addr) & 0xffff; 3823 3824 /* set up rb_wptr_poll addr */ 3825 wb_gpu_addr = prop->wptr_gpu_addr; 3826 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3827 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3828 3829 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3830 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3831 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3832 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3833 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3834 #ifdef __BIG_ENDIAN 3835 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3836 #endif 3837 mqd->cp_gfx_hqd_cntl = tmp; 3838 3839 /* set up cp_doorbell_control */ 3840 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3841 if (prop->use_doorbell) { 3842 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3843 DOORBELL_OFFSET, prop->doorbell_index); 3844 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3845 DOORBELL_EN, 1); 3846 } else 3847 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3848 DOORBELL_EN, 0); 3849 mqd->cp_rb_doorbell_control = tmp; 3850 3851 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3852 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3853 3854 /* active the queue */ 3855 mqd->cp_gfx_hqd_active = 1; 3856 3857 return 0; 3858 } 3859 3860 #ifdef BRING_UP_DEBUG 3861 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3862 { 3863 struct amdgpu_device *adev = ring->adev; 3864 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3865 3866 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3867 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3868 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3869 3870 /* set GFX_MQD_BASE */ 3871 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3872 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3873 3874 /* set GFX_MQD_CONTROL */ 3875 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3876 3877 /* set GFX_HQD_VMID to 0 */ 3878 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3879 3880 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3881 mqd->cp_gfx_hqd_queue_priority); 3882 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3883 3884 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3885 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3886 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3887 3888 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3889 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3890 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3891 3892 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3893 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3894 3895 /* set RB_WPTR_POLL_ADDR */ 3896 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3897 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3898 3899 /* set RB_DOORBELL_CONTROL */ 3900 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3901 3902 /* active the queue */ 3903 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3904 3905 return 0; 3906 } 3907 #endif 3908 3909 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3910 { 3911 struct amdgpu_device *adev = ring->adev; 3912 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3913 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3914 3915 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3916 memset((void *)mqd, 0, sizeof(*mqd)); 3917 mutex_lock(&adev->srbm_mutex); 3918 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3919 amdgpu_ring_init_mqd(ring); 3920 #ifdef BRING_UP_DEBUG 3921 gfx_v11_0_gfx_queue_init_register(ring); 3922 #endif 3923 soc21_grbm_select(adev, 0, 0, 0, 0); 3924 mutex_unlock(&adev->srbm_mutex); 3925 if (adev->gfx.me.mqd_backup[mqd_idx]) 3926 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3927 } else if (amdgpu_in_reset(adev)) { 3928 /* reset mqd with the backup copy */ 3929 if (adev->gfx.me.mqd_backup[mqd_idx]) 3930 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3931 /* reset the ring */ 3932 ring->wptr = 0; 3933 *ring->wptr_cpu_addr = 0; 3934 amdgpu_ring_clear_ring(ring); 3935 #ifdef BRING_UP_DEBUG 3936 mutex_lock(&adev->srbm_mutex); 3937 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3938 gfx_v11_0_gfx_queue_init_register(ring); 3939 soc21_grbm_select(adev, 0, 0, 0, 0); 3940 mutex_unlock(&adev->srbm_mutex); 3941 #endif 3942 } else { 3943 amdgpu_ring_clear_ring(ring); 3944 } 3945 3946 return 0; 3947 } 3948 3949 #ifndef BRING_UP_DEBUG 3950 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3951 { 3952 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3953 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3954 int r, i; 3955 3956 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3957 return -EINVAL; 3958 3959 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3960 adev->gfx.num_gfx_rings); 3961 if (r) { 3962 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3963 return r; 3964 } 3965 3966 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3967 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3968 3969 return amdgpu_ring_test_helper(kiq_ring); 3970 } 3971 #endif 3972 3973 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3974 { 3975 int r, i; 3976 struct amdgpu_ring *ring; 3977 3978 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3979 ring = &adev->gfx.gfx_ring[i]; 3980 3981 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3982 if (unlikely(r != 0)) 3983 goto done; 3984 3985 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3986 if (!r) { 3987 r = gfx_v11_0_gfx_init_queue(ring); 3988 amdgpu_bo_kunmap(ring->mqd_obj); 3989 ring->mqd_ptr = NULL; 3990 } 3991 amdgpu_bo_unreserve(ring->mqd_obj); 3992 if (r) 3993 goto done; 3994 } 3995 #ifndef BRING_UP_DEBUG 3996 r = gfx_v11_0_kiq_enable_kgq(adev); 3997 if (r) 3998 goto done; 3999 #endif 4000 r = gfx_v11_0_cp_gfx_start(adev); 4001 if (r) 4002 goto done; 4003 4004 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4005 ring = &adev->gfx.gfx_ring[i]; 4006 ring->sched.ready = true; 4007 } 4008 done: 4009 return r; 4010 } 4011 4012 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4013 struct amdgpu_mqd_prop *prop) 4014 { 4015 struct v11_compute_mqd *mqd = m; 4016 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4017 uint32_t tmp; 4018 4019 mqd->header = 0xC0310800; 4020 mqd->compute_pipelinestat_enable = 0x00000001; 4021 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4022 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4023 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4024 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4025 mqd->compute_misc_reserved = 0x00000007; 4026 4027 eop_base_addr = prop->eop_gpu_addr >> 8; 4028 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4029 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4030 4031 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4032 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4033 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4034 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4035 4036 mqd->cp_hqd_eop_control = tmp; 4037 4038 /* enable doorbell? */ 4039 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4040 4041 if (prop->use_doorbell) { 4042 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4043 DOORBELL_OFFSET, prop->doorbell_index); 4044 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4045 DOORBELL_EN, 1); 4046 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4047 DOORBELL_SOURCE, 0); 4048 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4049 DOORBELL_HIT, 0); 4050 } else { 4051 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4052 DOORBELL_EN, 0); 4053 } 4054 4055 mqd->cp_hqd_pq_doorbell_control = tmp; 4056 4057 /* disable the queue if it's active */ 4058 mqd->cp_hqd_dequeue_request = 0; 4059 mqd->cp_hqd_pq_rptr = 0; 4060 mqd->cp_hqd_pq_wptr_lo = 0; 4061 mqd->cp_hqd_pq_wptr_hi = 0; 4062 4063 /* set the pointer to the MQD */ 4064 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4065 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4066 4067 /* set MQD vmid to 0 */ 4068 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4069 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4070 mqd->cp_mqd_control = tmp; 4071 4072 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4073 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4074 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4075 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4076 4077 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4078 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4079 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4080 (order_base_2(prop->queue_size / 4) - 1)); 4081 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4082 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4083 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4084 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4085 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4086 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4087 mqd->cp_hqd_pq_control = tmp; 4088 4089 /* set the wb address whether it's enabled or not */ 4090 wb_gpu_addr = prop->rptr_gpu_addr; 4091 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4092 mqd->cp_hqd_pq_rptr_report_addr_hi = 4093 upper_32_bits(wb_gpu_addr) & 0xffff; 4094 4095 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4096 wb_gpu_addr = prop->wptr_gpu_addr; 4097 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4098 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4099 4100 tmp = 0; 4101 /* enable the doorbell if requested */ 4102 if (prop->use_doorbell) { 4103 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4104 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4105 DOORBELL_OFFSET, prop->doorbell_index); 4106 4107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4108 DOORBELL_EN, 1); 4109 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4110 DOORBELL_SOURCE, 0); 4111 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4112 DOORBELL_HIT, 0); 4113 } 4114 4115 mqd->cp_hqd_pq_doorbell_control = tmp; 4116 4117 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4118 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4119 4120 /* set the vmid for the queue */ 4121 mqd->cp_hqd_vmid = 0; 4122 4123 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4124 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4125 mqd->cp_hqd_persistent_state = tmp; 4126 4127 /* set MIN_IB_AVAIL_SIZE */ 4128 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4129 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4130 mqd->cp_hqd_ib_control = tmp; 4131 4132 /* set static priority for a compute queue/ring */ 4133 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4134 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4135 4136 mqd->cp_hqd_active = prop->hqd_active; 4137 4138 return 0; 4139 } 4140 4141 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4142 { 4143 struct amdgpu_device *adev = ring->adev; 4144 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4145 int j; 4146 4147 /* inactivate the queue */ 4148 if (amdgpu_sriov_vf(adev)) 4149 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4150 4151 /* disable wptr polling */ 4152 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4153 4154 /* write the EOP addr */ 4155 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4156 mqd->cp_hqd_eop_base_addr_lo); 4157 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4158 mqd->cp_hqd_eop_base_addr_hi); 4159 4160 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4161 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4162 mqd->cp_hqd_eop_control); 4163 4164 /* enable doorbell? */ 4165 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4166 mqd->cp_hqd_pq_doorbell_control); 4167 4168 /* disable the queue if it's active */ 4169 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4170 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4171 for (j = 0; j < adev->usec_timeout; j++) { 4172 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4173 break; 4174 udelay(1); 4175 } 4176 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4177 mqd->cp_hqd_dequeue_request); 4178 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4179 mqd->cp_hqd_pq_rptr); 4180 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4181 mqd->cp_hqd_pq_wptr_lo); 4182 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4183 mqd->cp_hqd_pq_wptr_hi); 4184 } 4185 4186 /* set the pointer to the MQD */ 4187 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4188 mqd->cp_mqd_base_addr_lo); 4189 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4190 mqd->cp_mqd_base_addr_hi); 4191 4192 /* set MQD vmid to 0 */ 4193 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4194 mqd->cp_mqd_control); 4195 4196 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4197 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4198 mqd->cp_hqd_pq_base_lo); 4199 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4200 mqd->cp_hqd_pq_base_hi); 4201 4202 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4203 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4204 mqd->cp_hqd_pq_control); 4205 4206 /* set the wb address whether it's enabled or not */ 4207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4208 mqd->cp_hqd_pq_rptr_report_addr_lo); 4209 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4210 mqd->cp_hqd_pq_rptr_report_addr_hi); 4211 4212 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4213 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4214 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4216 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4217 4218 /* enable the doorbell if requested */ 4219 if (ring->use_doorbell) { 4220 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4221 (adev->doorbell_index.kiq * 2) << 2); 4222 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4223 (adev->doorbell_index.userqueue_end * 2) << 2); 4224 } 4225 4226 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4227 mqd->cp_hqd_pq_doorbell_control); 4228 4229 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4230 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4231 mqd->cp_hqd_pq_wptr_lo); 4232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4233 mqd->cp_hqd_pq_wptr_hi); 4234 4235 /* set the vmid for the queue */ 4236 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4237 4238 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4239 mqd->cp_hqd_persistent_state); 4240 4241 /* activate the queue */ 4242 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4243 mqd->cp_hqd_active); 4244 4245 if (ring->use_doorbell) 4246 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4247 4248 return 0; 4249 } 4250 4251 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4252 { 4253 struct amdgpu_device *adev = ring->adev; 4254 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4255 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4256 4257 gfx_v11_0_kiq_setting(ring); 4258 4259 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4260 /* reset MQD to a clean status */ 4261 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4262 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4263 4264 /* reset ring buffer */ 4265 ring->wptr = 0; 4266 amdgpu_ring_clear_ring(ring); 4267 4268 mutex_lock(&adev->srbm_mutex); 4269 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4270 gfx_v11_0_kiq_init_register(ring); 4271 soc21_grbm_select(adev, 0, 0, 0, 0); 4272 mutex_unlock(&adev->srbm_mutex); 4273 } else { 4274 memset((void *)mqd, 0, sizeof(*mqd)); 4275 mutex_lock(&adev->srbm_mutex); 4276 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4277 amdgpu_ring_init_mqd(ring); 4278 gfx_v11_0_kiq_init_register(ring); 4279 soc21_grbm_select(adev, 0, 0, 0, 0); 4280 mutex_unlock(&adev->srbm_mutex); 4281 4282 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4283 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4284 } 4285 4286 return 0; 4287 } 4288 4289 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4290 { 4291 struct amdgpu_device *adev = ring->adev; 4292 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4293 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4294 4295 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4296 memset((void *)mqd, 0, sizeof(*mqd)); 4297 mutex_lock(&adev->srbm_mutex); 4298 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4299 amdgpu_ring_init_mqd(ring); 4300 soc21_grbm_select(adev, 0, 0, 0, 0); 4301 mutex_unlock(&adev->srbm_mutex); 4302 4303 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4304 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4305 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4306 /* reset MQD to a clean status */ 4307 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4308 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4309 4310 /* reset ring buffer */ 4311 ring->wptr = 0; 4312 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4313 amdgpu_ring_clear_ring(ring); 4314 } else { 4315 amdgpu_ring_clear_ring(ring); 4316 } 4317 4318 return 0; 4319 } 4320 4321 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4322 { 4323 struct amdgpu_ring *ring; 4324 int r; 4325 4326 ring = &adev->gfx.kiq.ring; 4327 4328 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4329 if (unlikely(r != 0)) 4330 return r; 4331 4332 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4333 if (unlikely(r != 0)) 4334 return r; 4335 4336 gfx_v11_0_kiq_init_queue(ring); 4337 amdgpu_bo_kunmap(ring->mqd_obj); 4338 ring->mqd_ptr = NULL; 4339 amdgpu_bo_unreserve(ring->mqd_obj); 4340 ring->sched.ready = true; 4341 return 0; 4342 } 4343 4344 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4345 { 4346 struct amdgpu_ring *ring = NULL; 4347 int r = 0, i; 4348 4349 if (!amdgpu_async_gfx_ring) 4350 gfx_v11_0_cp_compute_enable(adev, true); 4351 4352 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4353 ring = &adev->gfx.compute_ring[i]; 4354 4355 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4356 if (unlikely(r != 0)) 4357 goto done; 4358 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4359 if (!r) { 4360 r = gfx_v11_0_kcq_init_queue(ring); 4361 amdgpu_bo_kunmap(ring->mqd_obj); 4362 ring->mqd_ptr = NULL; 4363 } 4364 amdgpu_bo_unreserve(ring->mqd_obj); 4365 if (r) 4366 goto done; 4367 } 4368 4369 r = amdgpu_gfx_enable_kcq(adev); 4370 done: 4371 return r; 4372 } 4373 4374 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4375 { 4376 int r, i; 4377 struct amdgpu_ring *ring; 4378 4379 if (!(adev->flags & AMD_IS_APU)) 4380 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4381 4382 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4383 /* legacy firmware loading */ 4384 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4385 if (r) 4386 return r; 4387 4388 if (adev->gfx.rs64_enable) 4389 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4390 else 4391 r = gfx_v11_0_cp_compute_load_microcode(adev); 4392 if (r) 4393 return r; 4394 } 4395 4396 gfx_v11_0_cp_set_doorbell_range(adev); 4397 4398 if (amdgpu_async_gfx_ring) { 4399 gfx_v11_0_cp_compute_enable(adev, true); 4400 gfx_v11_0_cp_gfx_enable(adev, true); 4401 } 4402 4403 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4404 r = amdgpu_mes_kiq_hw_init(adev); 4405 else 4406 r = gfx_v11_0_kiq_resume(adev); 4407 if (r) 4408 return r; 4409 4410 r = gfx_v11_0_kcq_resume(adev); 4411 if (r) 4412 return r; 4413 4414 if (!amdgpu_async_gfx_ring) { 4415 r = gfx_v11_0_cp_gfx_resume(adev); 4416 if (r) 4417 return r; 4418 } else { 4419 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4420 if (r) 4421 return r; 4422 } 4423 4424 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4425 ring = &adev->gfx.gfx_ring[i]; 4426 r = amdgpu_ring_test_helper(ring); 4427 if (r) 4428 return r; 4429 } 4430 4431 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4432 ring = &adev->gfx.compute_ring[i]; 4433 r = amdgpu_ring_test_helper(ring); 4434 if (r) 4435 return r; 4436 } 4437 4438 return 0; 4439 } 4440 4441 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4442 { 4443 gfx_v11_0_cp_gfx_enable(adev, enable); 4444 gfx_v11_0_cp_compute_enable(adev, enable); 4445 } 4446 4447 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4448 { 4449 int r; 4450 bool value; 4451 4452 r = adev->gfxhub.funcs->gart_enable(adev); 4453 if (r) 4454 return r; 4455 4456 adev->hdp.funcs->flush_hdp(adev, NULL); 4457 4458 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4459 false : true; 4460 4461 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4462 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4463 4464 return 0; 4465 } 4466 4467 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4468 { 4469 u32 tmp; 4470 4471 /* select RS64 */ 4472 if (adev->gfx.rs64_enable) { 4473 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4474 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4475 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4476 4477 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4478 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4479 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4480 } 4481 4482 if (amdgpu_emu_mode == 1) 4483 msleep(100); 4484 } 4485 4486 static int get_gb_addr_config(struct amdgpu_device * adev) 4487 { 4488 u32 gb_addr_config; 4489 4490 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4491 if (gb_addr_config == 0) 4492 return -EINVAL; 4493 4494 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4495 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4496 4497 adev->gfx.config.gb_addr_config = gb_addr_config; 4498 4499 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4500 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4501 GB_ADDR_CONFIG, NUM_PIPES); 4502 4503 adev->gfx.config.max_tile_pipes = 4504 adev->gfx.config.gb_addr_config_fields.num_pipes; 4505 4506 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4507 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4508 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4509 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4510 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4511 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4512 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4513 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4514 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4515 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4516 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4517 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4518 4519 return 0; 4520 } 4521 4522 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4523 { 4524 uint32_t data; 4525 4526 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4527 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4528 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4529 4530 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4531 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4532 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4533 } 4534 4535 static int gfx_v11_0_hw_init(void *handle) 4536 { 4537 int r; 4538 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4539 4540 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4541 if (adev->gfx.imu.funcs) { 4542 /* RLC autoload sequence 1: Program rlc ram */ 4543 if (adev->gfx.imu.funcs->program_rlc_ram) 4544 adev->gfx.imu.funcs->program_rlc_ram(adev); 4545 } 4546 /* rlc autoload firmware */ 4547 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4548 if (r) 4549 return r; 4550 } else { 4551 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4552 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4553 if (adev->gfx.imu.funcs->load_microcode) 4554 adev->gfx.imu.funcs->load_microcode(adev); 4555 if (adev->gfx.imu.funcs->setup_imu) 4556 adev->gfx.imu.funcs->setup_imu(adev); 4557 if (adev->gfx.imu.funcs->start_imu) 4558 adev->gfx.imu.funcs->start_imu(adev); 4559 } 4560 } 4561 } 4562 4563 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4564 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4565 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4566 if (r) { 4567 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4568 return r; 4569 } 4570 } 4571 4572 adev->gfx.is_poweron = true; 4573 4574 if(get_gb_addr_config(adev)) 4575 DRM_WARN("Invalid gb_addr_config !\n"); 4576 4577 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4578 adev->gfx.rs64_enable) 4579 gfx_v11_0_config_gfx_rs64(adev); 4580 4581 r = gfx_v11_0_gfxhub_enable(adev); 4582 if (r) 4583 return r; 4584 4585 if (!amdgpu_emu_mode) 4586 gfx_v11_0_init_golden_registers(adev); 4587 4588 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4589 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4590 /** 4591 * For gfx 11, rlc firmware loading relies on smu firmware is 4592 * loaded firstly, so in direct type, it has to load smc ucode 4593 * here before rlc. 4594 */ 4595 if (!(adev->flags & AMD_IS_APU)) { 4596 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4597 if (r) 4598 return r; 4599 } 4600 } 4601 4602 gfx_v11_0_constants_init(adev); 4603 4604 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4605 gfx_v11_0_select_cp_fw_arch(adev); 4606 4607 if (adev->nbio.funcs->gc_doorbell_init) 4608 adev->nbio.funcs->gc_doorbell_init(adev); 4609 4610 r = gfx_v11_0_rlc_resume(adev); 4611 if (r) 4612 return r; 4613 4614 /* 4615 * init golden registers and rlc resume may override some registers, 4616 * reconfig them here 4617 */ 4618 gfx_v11_0_tcp_harvest(adev); 4619 4620 r = gfx_v11_0_cp_resume(adev); 4621 if (r) 4622 return r; 4623 4624 return r; 4625 } 4626 4627 #ifndef BRING_UP_DEBUG 4628 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4629 { 4630 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4631 struct amdgpu_ring *kiq_ring = &kiq->ring; 4632 int i, r = 0; 4633 4634 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4635 return -EINVAL; 4636 4637 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4638 adev->gfx.num_gfx_rings)) 4639 return -ENOMEM; 4640 4641 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4642 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4643 PREEMPT_QUEUES, 0, 0); 4644 4645 if (adev->gfx.kiq.ring.sched.ready) 4646 r = amdgpu_ring_test_helper(kiq_ring); 4647 4648 return r; 4649 } 4650 #endif 4651 4652 static int gfx_v11_0_hw_fini(void *handle) 4653 { 4654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4655 int r; 4656 uint32_t tmp; 4657 4658 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4659 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4660 4661 if (!adev->no_hw_access) { 4662 #ifndef BRING_UP_DEBUG 4663 if (amdgpu_async_gfx_ring) { 4664 r = gfx_v11_0_kiq_disable_kgq(adev); 4665 if (r) 4666 DRM_ERROR("KGQ disable failed\n"); 4667 } 4668 #endif 4669 if (amdgpu_gfx_disable_kcq(adev)) 4670 DRM_ERROR("KCQ disable failed\n"); 4671 4672 amdgpu_mes_kiq_hw_fini(adev); 4673 } 4674 4675 if (amdgpu_sriov_vf(adev)) { 4676 gfx_v11_0_cp_gfx_enable(adev, false); 4677 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 4678 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4679 tmp &= 0xffffff00; 4680 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 4681 4682 return 0; 4683 } 4684 gfx_v11_0_cp_enable(adev, false); 4685 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4686 4687 adev->gfxhub.funcs->gart_disable(adev); 4688 4689 adev->gfx.is_poweron = false; 4690 4691 return 0; 4692 } 4693 4694 static int gfx_v11_0_suspend(void *handle) 4695 { 4696 return gfx_v11_0_hw_fini(handle); 4697 } 4698 4699 static int gfx_v11_0_resume(void *handle) 4700 { 4701 return gfx_v11_0_hw_init(handle); 4702 } 4703 4704 static bool gfx_v11_0_is_idle(void *handle) 4705 { 4706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4707 4708 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4709 GRBM_STATUS, GUI_ACTIVE)) 4710 return false; 4711 else 4712 return true; 4713 } 4714 4715 static int gfx_v11_0_wait_for_idle(void *handle) 4716 { 4717 unsigned i; 4718 u32 tmp; 4719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4720 4721 for (i = 0; i < adev->usec_timeout; i++) { 4722 /* read MC_STATUS */ 4723 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4724 GRBM_STATUS__GUI_ACTIVE_MASK; 4725 4726 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4727 return 0; 4728 udelay(1); 4729 } 4730 return -ETIMEDOUT; 4731 } 4732 4733 static int gfx_v11_0_soft_reset(void *handle) 4734 { 4735 u32 grbm_soft_reset = 0; 4736 u32 tmp; 4737 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4738 4739 /* GRBM_STATUS */ 4740 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS); 4741 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4742 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4743 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 4744 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 4745 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 4746 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4747 GRBM_SOFT_RESET, SOFT_RESET_CP, 4748 1); 4749 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4750 GRBM_SOFT_RESET, SOFT_RESET_GFX, 4751 1); 4752 } 4753 4754 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4755 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4756 GRBM_SOFT_RESET, SOFT_RESET_CP, 4757 1); 4758 } 4759 4760 /* GRBM_STATUS2 */ 4761 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2); 4762 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4763 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4764 GRBM_SOFT_RESET, 4765 SOFT_RESET_RLC, 4766 1); 4767 4768 if (grbm_soft_reset) { 4769 /* stop the rlc */ 4770 gfx_v11_0_rlc_stop(adev); 4771 4772 /* Disable GFX parsing/prefetching */ 4773 gfx_v11_0_cp_gfx_enable(adev, false); 4774 4775 /* Disable MEC parsing/prefetching */ 4776 gfx_v11_0_cp_compute_enable(adev, false); 4777 4778 if (grbm_soft_reset) { 4779 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4780 tmp |= grbm_soft_reset; 4781 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4782 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4783 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4784 4785 udelay(50); 4786 4787 tmp &= ~grbm_soft_reset; 4788 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4789 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4790 } 4791 4792 /* Wait a little for things to settle down */ 4793 udelay(50); 4794 } 4795 return 0; 4796 } 4797 4798 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4799 { 4800 uint64_t clock; 4801 4802 amdgpu_gfx_off_ctrl(adev, false); 4803 mutex_lock(&adev->gfx.gpu_clock_mutex); 4804 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4805 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4806 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4807 amdgpu_gfx_off_ctrl(adev, true); 4808 return clock; 4809 } 4810 4811 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4812 uint32_t vmid, 4813 uint32_t gds_base, uint32_t gds_size, 4814 uint32_t gws_base, uint32_t gws_size, 4815 uint32_t oa_base, uint32_t oa_size) 4816 { 4817 struct amdgpu_device *adev = ring->adev; 4818 4819 /* GDS Base */ 4820 gfx_v11_0_write_data_to_reg(ring, 0, false, 4821 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4822 gds_base); 4823 4824 /* GDS Size */ 4825 gfx_v11_0_write_data_to_reg(ring, 0, false, 4826 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4827 gds_size); 4828 4829 /* GWS */ 4830 gfx_v11_0_write_data_to_reg(ring, 0, false, 4831 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4832 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4833 4834 /* OA */ 4835 gfx_v11_0_write_data_to_reg(ring, 0, false, 4836 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4837 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4838 } 4839 4840 static int gfx_v11_0_early_init(void *handle) 4841 { 4842 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4843 4844 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4845 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4846 AMDGPU_MAX_COMPUTE_RINGS); 4847 4848 gfx_v11_0_set_kiq_pm4_funcs(adev); 4849 gfx_v11_0_set_ring_funcs(adev); 4850 gfx_v11_0_set_irq_funcs(adev); 4851 gfx_v11_0_set_gds_init(adev); 4852 gfx_v11_0_set_rlc_funcs(adev); 4853 gfx_v11_0_set_mqd_funcs(adev); 4854 gfx_v11_0_set_imu_funcs(adev); 4855 4856 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4857 4858 return 0; 4859 } 4860 4861 static int gfx_v11_0_late_init(void *handle) 4862 { 4863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4864 int r; 4865 4866 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4867 if (r) 4868 return r; 4869 4870 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4871 if (r) 4872 return r; 4873 4874 return 0; 4875 } 4876 4877 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4878 { 4879 uint32_t rlc_cntl; 4880 4881 /* if RLC is not enabled, do nothing */ 4882 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4883 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4884 } 4885 4886 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4887 { 4888 uint32_t data; 4889 unsigned i; 4890 4891 data = RLC_SAFE_MODE__CMD_MASK; 4892 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4893 4894 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4895 4896 /* wait for RLC_SAFE_MODE */ 4897 for (i = 0; i < adev->usec_timeout; i++) { 4898 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4899 RLC_SAFE_MODE, CMD)) 4900 break; 4901 udelay(1); 4902 } 4903 } 4904 4905 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4906 { 4907 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4908 } 4909 4910 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4911 bool enable) 4912 { 4913 uint32_t def, data; 4914 4915 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4916 return; 4917 4918 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4919 4920 if (enable) 4921 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4922 else 4923 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4924 4925 if (def != data) 4926 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4927 } 4928 4929 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4930 bool enable) 4931 { 4932 uint32_t def, data; 4933 4934 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4935 return; 4936 4937 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4938 4939 if (enable) 4940 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4941 else 4942 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4943 4944 if (def != data) 4945 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4946 } 4947 4948 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4949 bool enable) 4950 { 4951 uint32_t def, data; 4952 4953 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4954 return; 4955 4956 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4957 4958 if (enable) 4959 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4960 else 4961 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4962 4963 if (def != data) 4964 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4965 } 4966 4967 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4968 bool enable) 4969 { 4970 uint32_t data, def; 4971 4972 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4973 return; 4974 4975 /* It is disabled by HW by default */ 4976 if (enable) { 4977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4978 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4979 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4980 4981 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4982 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4983 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4984 4985 if (def != data) 4986 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4987 } 4988 } else { 4989 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4990 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4991 4992 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4993 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4994 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4995 4996 if (def != data) 4997 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4998 } 4999 } 5000 } 5001 5002 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5003 bool enable) 5004 { 5005 uint32_t def, data; 5006 5007 if (!(adev->cg_flags & 5008 (AMD_CG_SUPPORT_GFX_CGCG | 5009 AMD_CG_SUPPORT_GFX_CGLS | 5010 AMD_CG_SUPPORT_GFX_3D_CGCG | 5011 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5012 return; 5013 5014 if (enable) { 5015 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5016 5017 /* unset CGCG override */ 5018 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5019 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5020 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5021 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5022 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5023 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5024 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5025 5026 /* update CGCG override bits */ 5027 if (def != data) 5028 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5029 5030 /* enable cgcg FSM(0x0000363F) */ 5031 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5032 5033 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5034 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5035 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5036 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5037 } 5038 5039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5040 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5041 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5042 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5043 } 5044 5045 if (def != data) 5046 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5047 5048 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5049 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5050 5051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5052 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5053 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5054 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5055 } 5056 5057 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5058 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5059 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5060 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5061 } 5062 5063 if (def != data) 5064 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5065 5066 /* set IDLE_POLL_COUNT(0x00900100) */ 5067 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5068 5069 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5070 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5071 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5072 5073 if (def != data) 5074 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5075 5076 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5077 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5078 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5079 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5080 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5081 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5082 5083 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5084 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5085 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5086 5087 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5088 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5089 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5090 } else { 5091 /* Program RLC_CGCG_CGLS_CTRL */ 5092 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5093 5094 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5095 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5096 5097 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5098 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5099 5100 if (def != data) 5101 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5102 5103 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5104 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5105 5106 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5107 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5108 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5109 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5110 5111 if (def != data) 5112 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5113 5114 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5115 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5116 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5117 5118 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5119 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5120 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5121 } 5122 } 5123 5124 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5125 bool enable) 5126 { 5127 amdgpu_gfx_rlc_enter_safe_mode(adev); 5128 5129 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5130 5131 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5132 5133 gfx_v11_0_update_repeater_fgcg(adev, enable); 5134 5135 gfx_v11_0_update_sram_fgcg(adev, enable); 5136 5137 gfx_v11_0_update_perf_clk(adev, enable); 5138 5139 if (adev->cg_flags & 5140 (AMD_CG_SUPPORT_GFX_MGCG | 5141 AMD_CG_SUPPORT_GFX_CGLS | 5142 AMD_CG_SUPPORT_GFX_CGCG | 5143 AMD_CG_SUPPORT_GFX_3D_CGCG | 5144 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5145 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5146 5147 amdgpu_gfx_rlc_exit_safe_mode(adev); 5148 5149 return 0; 5150 } 5151 5152 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5153 { 5154 u32 reg, data; 5155 5156 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5157 if (amdgpu_sriov_is_pp_one_vf(adev)) 5158 data = RREG32_NO_KIQ(reg); 5159 else 5160 data = RREG32(reg); 5161 5162 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5163 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5164 5165 if (amdgpu_sriov_is_pp_one_vf(adev)) 5166 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5167 else 5168 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5169 } 5170 5171 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5172 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5173 .set_safe_mode = gfx_v11_0_set_safe_mode, 5174 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5175 .init = gfx_v11_0_rlc_init, 5176 .get_csb_size = gfx_v11_0_get_csb_size, 5177 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5178 .resume = gfx_v11_0_rlc_resume, 5179 .stop = gfx_v11_0_rlc_stop, 5180 .reset = gfx_v11_0_rlc_reset, 5181 .start = gfx_v11_0_rlc_start, 5182 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5183 }; 5184 5185 static int gfx_v11_0_set_powergating_state(void *handle, 5186 enum amd_powergating_state state) 5187 { 5188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5189 bool enable = (state == AMD_PG_STATE_GATE); 5190 5191 if (amdgpu_sriov_vf(adev)) 5192 return 0; 5193 5194 switch (adev->ip_versions[GC_HWIP][0]) { 5195 case IP_VERSION(11, 0, 0): 5196 amdgpu_gfx_off_ctrl(adev, enable); 5197 break; 5198 default: 5199 break; 5200 } 5201 5202 return 0; 5203 } 5204 5205 static int gfx_v11_0_set_clockgating_state(void *handle, 5206 enum amd_clockgating_state state) 5207 { 5208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5209 5210 if (amdgpu_sriov_vf(adev)) 5211 return 0; 5212 5213 switch (adev->ip_versions[GC_HWIP][0]) { 5214 case IP_VERSION(11, 0, 0): 5215 case IP_VERSION(11, 0, 2): 5216 gfx_v11_0_update_gfx_clock_gating(adev, 5217 state == AMD_CG_STATE_GATE); 5218 break; 5219 default: 5220 break; 5221 } 5222 5223 return 0; 5224 } 5225 5226 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5227 { 5228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5229 int data; 5230 5231 /* AMD_CG_SUPPORT_GFX_MGCG */ 5232 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5233 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5234 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5235 5236 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5237 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5238 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5239 5240 /* AMD_CG_SUPPORT_GFX_FGCG */ 5241 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5242 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5243 5244 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5245 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5246 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5247 5248 /* AMD_CG_SUPPORT_GFX_CGCG */ 5249 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5250 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5251 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5252 5253 /* AMD_CG_SUPPORT_GFX_CGLS */ 5254 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5255 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5256 5257 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5258 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5259 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5260 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5261 5262 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5263 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5264 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5265 } 5266 5267 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5268 { 5269 /* gfx11 is 32bit rptr*/ 5270 return *(uint32_t *)ring->rptr_cpu_addr; 5271 } 5272 5273 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5274 { 5275 struct amdgpu_device *adev = ring->adev; 5276 u64 wptr; 5277 5278 /* XXX check if swapping is necessary on BE */ 5279 if (ring->use_doorbell) { 5280 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5281 } else { 5282 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5283 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5284 } 5285 5286 return wptr; 5287 } 5288 5289 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5290 { 5291 struct amdgpu_device *adev = ring->adev; 5292 5293 if (ring->use_doorbell) { 5294 /* XXX check if swapping is necessary on BE */ 5295 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5296 WDOORBELL64(ring->doorbell_index, ring->wptr); 5297 } else { 5298 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5299 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5300 } 5301 } 5302 5303 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5304 { 5305 /* gfx11 hardware is 32bit rptr */ 5306 return *(uint32_t *)ring->rptr_cpu_addr; 5307 } 5308 5309 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5310 { 5311 u64 wptr; 5312 5313 /* XXX check if swapping is necessary on BE */ 5314 if (ring->use_doorbell) 5315 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5316 else 5317 BUG(); 5318 return wptr; 5319 } 5320 5321 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5322 { 5323 struct amdgpu_device *adev = ring->adev; 5324 5325 /* XXX check if swapping is necessary on BE */ 5326 if (ring->use_doorbell) { 5327 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5328 WDOORBELL64(ring->doorbell_index, ring->wptr); 5329 } else { 5330 BUG(); /* only DOORBELL method supported on gfx11 now */ 5331 } 5332 } 5333 5334 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5335 { 5336 struct amdgpu_device *adev = ring->adev; 5337 u32 ref_and_mask, reg_mem_engine; 5338 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5339 5340 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5341 switch (ring->me) { 5342 case 1: 5343 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5344 break; 5345 case 2: 5346 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5347 break; 5348 default: 5349 return; 5350 } 5351 reg_mem_engine = 0; 5352 } else { 5353 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5354 reg_mem_engine = 1; /* pfp */ 5355 } 5356 5357 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5358 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5359 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5360 ref_and_mask, ref_and_mask, 0x20); 5361 } 5362 5363 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5364 struct amdgpu_job *job, 5365 struct amdgpu_ib *ib, 5366 uint32_t flags) 5367 { 5368 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5369 u32 header, control = 0; 5370 5371 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5372 5373 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5374 5375 control |= ib->length_dw | (vmid << 24); 5376 5377 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5378 control |= INDIRECT_BUFFER_PRE_ENB(1); 5379 5380 if (flags & AMDGPU_IB_PREEMPTED) 5381 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5382 5383 if (vmid) 5384 gfx_v11_0_ring_emit_de_meta(ring, 5385 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5386 } 5387 5388 if (ring->is_mes_queue) 5389 /* inherit vmid from mqd */ 5390 control |= 0x400000; 5391 5392 amdgpu_ring_write(ring, header); 5393 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5394 amdgpu_ring_write(ring, 5395 #ifdef __BIG_ENDIAN 5396 (2 << 0) | 5397 #endif 5398 lower_32_bits(ib->gpu_addr)); 5399 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5400 amdgpu_ring_write(ring, control); 5401 } 5402 5403 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5404 struct amdgpu_job *job, 5405 struct amdgpu_ib *ib, 5406 uint32_t flags) 5407 { 5408 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5409 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5410 5411 if (ring->is_mes_queue) 5412 /* inherit vmid from mqd */ 5413 control |= 0x40000000; 5414 5415 /* Currently, there is a high possibility to get wave ID mismatch 5416 * between ME and GDS, leading to a hw deadlock, because ME generates 5417 * different wave IDs than the GDS expects. This situation happens 5418 * randomly when at least 5 compute pipes use GDS ordered append. 5419 * The wave IDs generated by ME are also wrong after suspend/resume. 5420 * Those are probably bugs somewhere else in the kernel driver. 5421 * 5422 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5423 * GDS to 0 for this ring (me/pipe). 5424 */ 5425 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5426 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5427 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5428 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5429 } 5430 5431 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5432 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5433 amdgpu_ring_write(ring, 5434 #ifdef __BIG_ENDIAN 5435 (2 << 0) | 5436 #endif 5437 lower_32_bits(ib->gpu_addr)); 5438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5439 amdgpu_ring_write(ring, control); 5440 } 5441 5442 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5443 u64 seq, unsigned flags) 5444 { 5445 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5446 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5447 5448 /* RELEASE_MEM - flush caches, send int */ 5449 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5450 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5451 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5452 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5453 PACKET3_RELEASE_MEM_GCR_GL2_US | 5454 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5455 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5456 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5457 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5458 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5459 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5460 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5461 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5462 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5463 5464 /* 5465 * the address should be Qword aligned if 64bit write, Dword 5466 * aligned if only send 32bit data low (discard data high) 5467 */ 5468 if (write64bit) 5469 BUG_ON(addr & 0x7); 5470 else 5471 BUG_ON(addr & 0x3); 5472 amdgpu_ring_write(ring, lower_32_bits(addr)); 5473 amdgpu_ring_write(ring, upper_32_bits(addr)); 5474 amdgpu_ring_write(ring, lower_32_bits(seq)); 5475 amdgpu_ring_write(ring, upper_32_bits(seq)); 5476 amdgpu_ring_write(ring, ring->is_mes_queue ? 5477 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5478 } 5479 5480 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5481 { 5482 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5483 uint32_t seq = ring->fence_drv.sync_seq; 5484 uint64_t addr = ring->fence_drv.gpu_addr; 5485 5486 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5487 upper_32_bits(addr), seq, 0xffffffff, 4); 5488 } 5489 5490 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5491 uint16_t pasid, uint32_t flush_type, 5492 bool all_hub, uint8_t dst_sel) 5493 { 5494 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5495 amdgpu_ring_write(ring, 5496 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5497 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5498 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5499 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5500 } 5501 5502 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5503 unsigned vmid, uint64_t pd_addr) 5504 { 5505 if (ring->is_mes_queue) 5506 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5507 else 5508 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5509 5510 /* compute doesn't have PFP */ 5511 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5512 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5513 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5514 amdgpu_ring_write(ring, 0x0); 5515 } 5516 } 5517 5518 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5519 u64 seq, unsigned int flags) 5520 { 5521 struct amdgpu_device *adev = ring->adev; 5522 5523 /* we only allocate 32bit for each seq wb address */ 5524 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5525 5526 /* write fence seq to the "addr" */ 5527 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5528 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5529 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5530 amdgpu_ring_write(ring, lower_32_bits(addr)); 5531 amdgpu_ring_write(ring, upper_32_bits(addr)); 5532 amdgpu_ring_write(ring, lower_32_bits(seq)); 5533 5534 if (flags & AMDGPU_FENCE_FLAG_INT) { 5535 /* set register to trigger INT */ 5536 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5537 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5538 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5539 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5540 amdgpu_ring_write(ring, 0); 5541 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5542 } 5543 } 5544 5545 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5546 uint32_t flags) 5547 { 5548 uint32_t dw2 = 0; 5549 5550 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5551 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5552 /* set load_global_config & load_global_uconfig */ 5553 dw2 |= 0x8001; 5554 /* set load_cs_sh_regs */ 5555 dw2 |= 0x01000000; 5556 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5557 dw2 |= 0x10002; 5558 } 5559 5560 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5561 amdgpu_ring_write(ring, dw2); 5562 amdgpu_ring_write(ring, 0); 5563 } 5564 5565 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5566 { 5567 unsigned ret; 5568 5569 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5570 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5571 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5572 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5573 ret = ring->wptr & ring->buf_mask; 5574 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5575 5576 return ret; 5577 } 5578 5579 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5580 { 5581 unsigned cur; 5582 BUG_ON(offset > ring->buf_mask); 5583 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5584 5585 cur = (ring->wptr - 1) & ring->buf_mask; 5586 if (likely(cur > offset)) 5587 ring->ring[offset] = cur - offset; 5588 else 5589 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5590 } 5591 5592 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5593 { 5594 int i, r = 0; 5595 struct amdgpu_device *adev = ring->adev; 5596 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5597 struct amdgpu_ring *kiq_ring = &kiq->ring; 5598 unsigned long flags; 5599 5600 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5601 return -EINVAL; 5602 5603 spin_lock_irqsave(&kiq->ring_lock, flags); 5604 5605 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5606 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5607 return -ENOMEM; 5608 } 5609 5610 /* assert preemption condition */ 5611 amdgpu_ring_set_preempt_cond_exec(ring, false); 5612 5613 /* assert IB preemption, emit the trailing fence */ 5614 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5615 ring->trail_fence_gpu_addr, 5616 ++ring->trail_seq); 5617 amdgpu_ring_commit(kiq_ring); 5618 5619 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5620 5621 /* poll the trailing fence */ 5622 for (i = 0; i < adev->usec_timeout; i++) { 5623 if (ring->trail_seq == 5624 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5625 break; 5626 udelay(1); 5627 } 5628 5629 if (i >= adev->usec_timeout) { 5630 r = -EINVAL; 5631 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5632 } 5633 5634 /* deassert preemption condition */ 5635 amdgpu_ring_set_preempt_cond_exec(ring, true); 5636 return r; 5637 } 5638 5639 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5640 { 5641 struct amdgpu_device *adev = ring->adev; 5642 struct v10_de_ib_state de_payload = {0}; 5643 uint64_t offset, gds_addr, de_payload_gpu_addr; 5644 void *de_payload_cpu_addr; 5645 int cnt; 5646 5647 if (ring->is_mes_queue) { 5648 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5649 gfx[0].gfx_meta_data) + 5650 offsetof(struct v10_gfx_meta_data, de_payload); 5651 de_payload_gpu_addr = 5652 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5653 de_payload_cpu_addr = 5654 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5655 5656 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5657 gfx[0].gds_backup) + 5658 offsetof(struct v10_gfx_meta_data, de_payload); 5659 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5660 } else { 5661 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5662 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5663 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5664 5665 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5666 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5667 PAGE_SIZE); 5668 } 5669 5670 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5671 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5672 5673 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5674 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5675 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5676 WRITE_DATA_DST_SEL(8) | 5677 WR_CONFIRM) | 5678 WRITE_DATA_CACHE_POLICY(0)); 5679 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5680 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5681 5682 if (resume) 5683 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5684 sizeof(de_payload) >> 2); 5685 else 5686 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5687 sizeof(de_payload) >> 2); 5688 } 5689 5690 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5691 bool secure) 5692 { 5693 uint32_t v = secure ? FRAME_TMZ : 0; 5694 5695 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5696 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5697 } 5698 5699 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5700 uint32_t reg_val_offs) 5701 { 5702 struct amdgpu_device *adev = ring->adev; 5703 5704 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5705 amdgpu_ring_write(ring, 0 | /* src: register*/ 5706 (5 << 8) | /* dst: memory */ 5707 (1 << 20)); /* write confirm */ 5708 amdgpu_ring_write(ring, reg); 5709 amdgpu_ring_write(ring, 0); 5710 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5711 reg_val_offs * 4)); 5712 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5713 reg_val_offs * 4)); 5714 } 5715 5716 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5717 uint32_t val) 5718 { 5719 uint32_t cmd = 0; 5720 5721 switch (ring->funcs->type) { 5722 case AMDGPU_RING_TYPE_GFX: 5723 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5724 break; 5725 case AMDGPU_RING_TYPE_KIQ: 5726 cmd = (1 << 16); /* no inc addr */ 5727 break; 5728 default: 5729 cmd = WR_CONFIRM; 5730 break; 5731 } 5732 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5733 amdgpu_ring_write(ring, cmd); 5734 amdgpu_ring_write(ring, reg); 5735 amdgpu_ring_write(ring, 0); 5736 amdgpu_ring_write(ring, val); 5737 } 5738 5739 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5740 uint32_t val, uint32_t mask) 5741 { 5742 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5743 } 5744 5745 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5746 uint32_t reg0, uint32_t reg1, 5747 uint32_t ref, uint32_t mask) 5748 { 5749 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5750 5751 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5752 ref, mask, 0x20); 5753 } 5754 5755 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5756 unsigned vmid) 5757 { 5758 struct amdgpu_device *adev = ring->adev; 5759 uint32_t value = 0; 5760 5761 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5762 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5763 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5764 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5765 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5766 } 5767 5768 static void 5769 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5770 uint32_t me, uint32_t pipe, 5771 enum amdgpu_interrupt_state state) 5772 { 5773 uint32_t cp_int_cntl, cp_int_cntl_reg; 5774 5775 if (!me) { 5776 switch (pipe) { 5777 case 0: 5778 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5779 break; 5780 case 1: 5781 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5782 break; 5783 default: 5784 DRM_DEBUG("invalid pipe %d\n", pipe); 5785 return; 5786 } 5787 } else { 5788 DRM_DEBUG("invalid me %d\n", me); 5789 return; 5790 } 5791 5792 switch (state) { 5793 case AMDGPU_IRQ_STATE_DISABLE: 5794 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5795 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5796 TIME_STAMP_INT_ENABLE, 0); 5797 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5798 GENERIC0_INT_ENABLE, 0); 5799 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5800 break; 5801 case AMDGPU_IRQ_STATE_ENABLE: 5802 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5803 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5804 TIME_STAMP_INT_ENABLE, 1); 5805 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5806 GENERIC0_INT_ENABLE, 1); 5807 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5808 break; 5809 default: 5810 break; 5811 } 5812 } 5813 5814 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5815 int me, int pipe, 5816 enum amdgpu_interrupt_state state) 5817 { 5818 u32 mec_int_cntl, mec_int_cntl_reg; 5819 5820 /* 5821 * amdgpu controls only the first MEC. That's why this function only 5822 * handles the setting of interrupts for this specific MEC. All other 5823 * pipes' interrupts are set by amdkfd. 5824 */ 5825 5826 if (me == 1) { 5827 switch (pipe) { 5828 case 0: 5829 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5830 break; 5831 case 1: 5832 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5833 break; 5834 case 2: 5835 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5836 break; 5837 case 3: 5838 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5839 break; 5840 default: 5841 DRM_DEBUG("invalid pipe %d\n", pipe); 5842 return; 5843 } 5844 } else { 5845 DRM_DEBUG("invalid me %d\n", me); 5846 return; 5847 } 5848 5849 switch (state) { 5850 case AMDGPU_IRQ_STATE_DISABLE: 5851 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5852 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5853 TIME_STAMP_INT_ENABLE, 0); 5854 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5855 GENERIC0_INT_ENABLE, 0); 5856 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5857 break; 5858 case AMDGPU_IRQ_STATE_ENABLE: 5859 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5860 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5861 TIME_STAMP_INT_ENABLE, 1); 5862 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5863 GENERIC0_INT_ENABLE, 1); 5864 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5865 break; 5866 default: 5867 break; 5868 } 5869 } 5870 5871 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5872 struct amdgpu_irq_src *src, 5873 unsigned type, 5874 enum amdgpu_interrupt_state state) 5875 { 5876 switch (type) { 5877 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5878 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5879 break; 5880 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5881 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5882 break; 5883 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5884 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5885 break; 5886 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5887 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5888 break; 5889 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5890 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5891 break; 5892 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5893 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5894 break; 5895 default: 5896 break; 5897 } 5898 return 0; 5899 } 5900 5901 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5902 struct amdgpu_irq_src *source, 5903 struct amdgpu_iv_entry *entry) 5904 { 5905 int i; 5906 u8 me_id, pipe_id, queue_id; 5907 struct amdgpu_ring *ring; 5908 uint32_t mes_queue_id = entry->src_data[0]; 5909 5910 DRM_DEBUG("IH: CP EOP\n"); 5911 5912 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5913 struct amdgpu_mes_queue *queue; 5914 5915 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5916 5917 spin_lock(&adev->mes.queue_id_lock); 5918 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5919 if (queue) { 5920 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5921 amdgpu_fence_process(queue->ring); 5922 } 5923 spin_unlock(&adev->mes.queue_id_lock); 5924 } else { 5925 me_id = (entry->ring_id & 0x0c) >> 2; 5926 pipe_id = (entry->ring_id & 0x03) >> 0; 5927 queue_id = (entry->ring_id & 0x70) >> 4; 5928 5929 switch (me_id) { 5930 case 0: 5931 if (pipe_id == 0) 5932 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5933 else 5934 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5935 break; 5936 case 1: 5937 case 2: 5938 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5939 ring = &adev->gfx.compute_ring[i]; 5940 /* Per-queue interrupt is supported for MEC starting from VI. 5941 * The interrupt can only be enabled/disabled per pipe instead 5942 * of per queue. 5943 */ 5944 if ((ring->me == me_id) && 5945 (ring->pipe == pipe_id) && 5946 (ring->queue == queue_id)) 5947 amdgpu_fence_process(ring); 5948 } 5949 break; 5950 } 5951 } 5952 5953 return 0; 5954 } 5955 5956 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5957 struct amdgpu_irq_src *source, 5958 unsigned type, 5959 enum amdgpu_interrupt_state state) 5960 { 5961 switch (state) { 5962 case AMDGPU_IRQ_STATE_DISABLE: 5963 case AMDGPU_IRQ_STATE_ENABLE: 5964 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5965 PRIV_REG_INT_ENABLE, 5966 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5967 break; 5968 default: 5969 break; 5970 } 5971 5972 return 0; 5973 } 5974 5975 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5976 struct amdgpu_irq_src *source, 5977 unsigned type, 5978 enum amdgpu_interrupt_state state) 5979 { 5980 switch (state) { 5981 case AMDGPU_IRQ_STATE_DISABLE: 5982 case AMDGPU_IRQ_STATE_ENABLE: 5983 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5984 PRIV_INSTR_INT_ENABLE, 5985 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5986 break; 5987 default: 5988 break; 5989 } 5990 5991 return 0; 5992 } 5993 5994 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5995 struct amdgpu_iv_entry *entry) 5996 { 5997 u8 me_id, pipe_id, queue_id; 5998 struct amdgpu_ring *ring; 5999 int i; 6000 6001 me_id = (entry->ring_id & 0x0c) >> 2; 6002 pipe_id = (entry->ring_id & 0x03) >> 0; 6003 queue_id = (entry->ring_id & 0x70) >> 4; 6004 6005 switch (me_id) { 6006 case 0: 6007 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6008 ring = &adev->gfx.gfx_ring[i]; 6009 /* we only enabled 1 gfx queue per pipe for now */ 6010 if (ring->me == me_id && ring->pipe == pipe_id) 6011 drm_sched_fault(&ring->sched); 6012 } 6013 break; 6014 case 1: 6015 case 2: 6016 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6017 ring = &adev->gfx.compute_ring[i]; 6018 if (ring->me == me_id && ring->pipe == pipe_id && 6019 ring->queue == queue_id) 6020 drm_sched_fault(&ring->sched); 6021 } 6022 break; 6023 default: 6024 BUG(); 6025 } 6026 } 6027 6028 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6029 struct amdgpu_irq_src *source, 6030 struct amdgpu_iv_entry *entry) 6031 { 6032 DRM_ERROR("Illegal register access in command stream\n"); 6033 gfx_v11_0_handle_priv_fault(adev, entry); 6034 return 0; 6035 } 6036 6037 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6038 struct amdgpu_irq_src *source, 6039 struct amdgpu_iv_entry *entry) 6040 { 6041 DRM_ERROR("Illegal instruction in command stream\n"); 6042 gfx_v11_0_handle_priv_fault(adev, entry); 6043 return 0; 6044 } 6045 6046 #if 0 6047 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6048 struct amdgpu_irq_src *src, 6049 unsigned int type, 6050 enum amdgpu_interrupt_state state) 6051 { 6052 uint32_t tmp, target; 6053 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6054 6055 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6056 target += ring->pipe; 6057 6058 switch (type) { 6059 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6060 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6061 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6062 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6063 GENERIC2_INT_ENABLE, 0); 6064 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6065 6066 tmp = RREG32_SOC15_IP(GC, target); 6067 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6068 GENERIC2_INT_ENABLE, 0); 6069 WREG32_SOC15_IP(GC, target, tmp); 6070 } else { 6071 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6072 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6073 GENERIC2_INT_ENABLE, 1); 6074 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6075 6076 tmp = RREG32_SOC15_IP(GC, target); 6077 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6078 GENERIC2_INT_ENABLE, 1); 6079 WREG32_SOC15_IP(GC, target, tmp); 6080 } 6081 break; 6082 default: 6083 BUG(); /* kiq only support GENERIC2_INT now */ 6084 break; 6085 } 6086 return 0; 6087 } 6088 #endif 6089 6090 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6091 { 6092 const unsigned int gcr_cntl = 6093 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6094 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6095 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6096 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6097 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6098 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6099 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6100 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6101 6102 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6103 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6104 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6105 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6106 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6107 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6108 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6109 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6110 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6111 } 6112 6113 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6114 .name = "gfx_v11_0", 6115 .early_init = gfx_v11_0_early_init, 6116 .late_init = gfx_v11_0_late_init, 6117 .sw_init = gfx_v11_0_sw_init, 6118 .sw_fini = gfx_v11_0_sw_fini, 6119 .hw_init = gfx_v11_0_hw_init, 6120 .hw_fini = gfx_v11_0_hw_fini, 6121 .suspend = gfx_v11_0_suspend, 6122 .resume = gfx_v11_0_resume, 6123 .is_idle = gfx_v11_0_is_idle, 6124 .wait_for_idle = gfx_v11_0_wait_for_idle, 6125 .soft_reset = gfx_v11_0_soft_reset, 6126 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6127 .set_powergating_state = gfx_v11_0_set_powergating_state, 6128 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6129 }; 6130 6131 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6132 .type = AMDGPU_RING_TYPE_GFX, 6133 .align_mask = 0xff, 6134 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6135 .support_64bit_ptrs = true, 6136 .vmhub = AMDGPU_GFXHUB_0, 6137 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6138 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6139 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6140 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6141 5 + /* COND_EXEC */ 6142 7 + /* PIPELINE_SYNC */ 6143 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6144 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6145 2 + /* VM_FLUSH */ 6146 8 + /* FENCE for VM_FLUSH */ 6147 20 + /* GDS switch */ 6148 5 + /* COND_EXEC */ 6149 7 + /* HDP_flush */ 6150 4 + /* VGT_flush */ 6151 31 + /* DE_META */ 6152 3 + /* CNTX_CTRL */ 6153 5 + /* HDP_INVL */ 6154 8 + 8 + /* FENCE x2 */ 6155 8, /* gfx_v11_0_emit_mem_sync */ 6156 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6157 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6158 .emit_fence = gfx_v11_0_ring_emit_fence, 6159 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6160 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6161 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6162 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6163 .test_ring = gfx_v11_0_ring_test_ring, 6164 .test_ib = gfx_v11_0_ring_test_ib, 6165 .insert_nop = amdgpu_ring_insert_nop, 6166 .pad_ib = amdgpu_ring_generic_pad_ib, 6167 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6168 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6169 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6170 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6171 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6172 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6173 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6174 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6175 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6176 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6177 }; 6178 6179 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6180 .type = AMDGPU_RING_TYPE_COMPUTE, 6181 .align_mask = 0xff, 6182 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6183 .support_64bit_ptrs = true, 6184 .vmhub = AMDGPU_GFXHUB_0, 6185 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6186 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6187 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6188 .emit_frame_size = 6189 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6190 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6191 5 + /* hdp invalidate */ 6192 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6193 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6194 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6195 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6196 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6197 8, /* gfx_v11_0_emit_mem_sync */ 6198 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6199 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6200 .emit_fence = gfx_v11_0_ring_emit_fence, 6201 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6202 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6203 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6204 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6205 .test_ring = gfx_v11_0_ring_test_ring, 6206 .test_ib = gfx_v11_0_ring_test_ib, 6207 .insert_nop = amdgpu_ring_insert_nop, 6208 .pad_ib = amdgpu_ring_generic_pad_ib, 6209 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6210 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6211 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6212 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6213 }; 6214 6215 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6216 .type = AMDGPU_RING_TYPE_KIQ, 6217 .align_mask = 0xff, 6218 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6219 .support_64bit_ptrs = true, 6220 .vmhub = AMDGPU_GFXHUB_0, 6221 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6222 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6223 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6224 .emit_frame_size = 6225 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6226 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6227 5 + /*hdp invalidate */ 6228 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6229 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6230 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6231 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6232 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6233 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6234 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6235 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6236 .test_ring = gfx_v11_0_ring_test_ring, 6237 .test_ib = gfx_v11_0_ring_test_ib, 6238 .insert_nop = amdgpu_ring_insert_nop, 6239 .pad_ib = amdgpu_ring_generic_pad_ib, 6240 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6241 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6242 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6243 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6244 }; 6245 6246 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6247 { 6248 int i; 6249 6250 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6251 6252 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6253 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6254 6255 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6256 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6257 } 6258 6259 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6260 .set = gfx_v11_0_set_eop_interrupt_state, 6261 .process = gfx_v11_0_eop_irq, 6262 }; 6263 6264 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6265 .set = gfx_v11_0_set_priv_reg_fault_state, 6266 .process = gfx_v11_0_priv_reg_irq, 6267 }; 6268 6269 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6270 .set = gfx_v11_0_set_priv_inst_fault_state, 6271 .process = gfx_v11_0_priv_inst_irq, 6272 }; 6273 6274 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6275 { 6276 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6277 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6278 6279 adev->gfx.priv_reg_irq.num_types = 1; 6280 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6281 6282 adev->gfx.priv_inst_irq.num_types = 1; 6283 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6284 } 6285 6286 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6287 { 6288 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6289 } 6290 6291 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6292 { 6293 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6294 } 6295 6296 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6297 { 6298 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6299 adev->gfx.config.max_sh_per_se * 6300 adev->gfx.config.max_shader_engines; 6301 6302 adev->gds.gds_size = 0x1000; 6303 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6304 adev->gds.gws_size = 64; 6305 adev->gds.oa_size = 16; 6306 } 6307 6308 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6309 { 6310 /* set gfx eng mqd */ 6311 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6312 sizeof(struct v11_gfx_mqd); 6313 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6314 gfx_v11_0_gfx_mqd_init; 6315 /* set compute eng mqd */ 6316 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6317 sizeof(struct v11_compute_mqd); 6318 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6319 gfx_v11_0_compute_mqd_init; 6320 } 6321 6322 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6323 u32 bitmap) 6324 { 6325 u32 data; 6326 6327 if (!bitmap) 6328 return; 6329 6330 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6331 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6332 6333 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6334 } 6335 6336 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6337 { 6338 u32 data, wgp_bitmask; 6339 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6340 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6341 6342 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6343 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6344 6345 wgp_bitmask = 6346 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6347 6348 return (~data) & wgp_bitmask; 6349 } 6350 6351 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6352 { 6353 u32 wgp_idx, wgp_active_bitmap; 6354 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6355 6356 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6357 cu_active_bitmap = 0; 6358 6359 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6360 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6361 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6362 if (wgp_active_bitmap & (1 << wgp_idx)) 6363 cu_active_bitmap |= cu_bitmap_per_wgp; 6364 } 6365 6366 return cu_active_bitmap; 6367 } 6368 6369 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6370 struct amdgpu_cu_info *cu_info) 6371 { 6372 int i, j, k, counter, active_cu_number = 0; 6373 u32 mask, bitmap; 6374 unsigned disable_masks[8 * 2]; 6375 6376 if (!adev || !cu_info) 6377 return -EINVAL; 6378 6379 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6380 6381 mutex_lock(&adev->grbm_idx_mutex); 6382 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6383 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6384 mask = 1; 6385 counter = 0; 6386 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6387 if (i < 8 && j < 2) 6388 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6389 adev, disable_masks[i * 2 + j]); 6390 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6391 6392 /** 6393 * GFX11 could support more than 4 SEs, while the bitmap 6394 * in cu_info struct is 4x4 and ioctl interface struct 6395 * drm_amdgpu_info_device should keep stable. 6396 * So we use last two columns of bitmap to store cu mask for 6397 * SEs 4 to 7, the layout of the bitmap is as below: 6398 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6399 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6400 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6401 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6402 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6403 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6404 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6405 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6406 */ 6407 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6408 6409 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6410 if (bitmap & mask) 6411 counter++; 6412 6413 mask <<= 1; 6414 } 6415 active_cu_number += counter; 6416 } 6417 } 6418 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6419 mutex_unlock(&adev->grbm_idx_mutex); 6420 6421 cu_info->number = active_cu_number; 6422 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6423 6424 return 0; 6425 } 6426 6427 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6428 { 6429 .type = AMD_IP_BLOCK_TYPE_GFX, 6430 .major = 11, 6431 .minor = 0, 6432 .rev = 0, 6433 .funcs = &gfx_v11_0_ip_funcs, 6434 }; 6435