1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v11_0.h" 33 #include "soc21.h" 34 #include "nvd.h" 35 36 #include "gc/gc_11_0_0_offset.h" 37 #include "gc/gc_11_0_0_sh_mask.h" 38 #include "smuio/smuio_13_0_6_offset.h" 39 #include "smuio/smuio_13_0_6_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx11.h" 45 #include "v11_structs.h" 46 #include "gfx_v11_0.h" 47 #include "gfx_v11_0_cleaner_shader.h" 48 #include "gfx_v11_0_3.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 #include "mes_userqueue.h" 52 #include "amdgpu_userq_fence.h" 53 54 #define GFX11_NUM_GFX_RINGS 1 55 #define GFX11_MEC_HPD_SIZE 2048 56 57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 59 60 #define regCGTT_WD_CLK_CTRL 0x5086 61 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 63 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 64 #define regPC_CONFIG_CNTL_1 0x194d 65 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 66 67 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 68 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 69 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 70 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 71 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 72 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 73 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 74 75 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 76 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 77 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 78 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 79 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 80 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 81 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 82 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 83 84 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 104 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 105 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 106 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 107 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 108 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 109 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 111 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 112 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 114 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 115 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 116 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 117 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 118 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 119 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 120 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 121 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 122 123 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 124 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 126 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 157 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 158 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 159 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 160 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 161 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 162 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 163 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 164 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 165 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 166 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 167 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 168 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 169 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 170 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 171 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 181 /* cp header registers */ 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 190 /* SE status registers */ 191 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 192 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 193 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 194 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 195 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 196 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 197 }; 198 199 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 200 /* compute registers */ 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 240 /* cp header registers */ 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 }; 250 251 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 252 /* gfx queue registers */ 253 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 254 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 255 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 256 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 257 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 258 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 259 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 260 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 261 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 262 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 263 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 264 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 265 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 266 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 267 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 268 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 269 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 270 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 271 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 272 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 273 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 274 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 275 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 276 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 277 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 278 /* cp header registers */ 279 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 280 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 281 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 282 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 283 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 284 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 285 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 286 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 287 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 288 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 289 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 290 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 291 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 292 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 293 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 294 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 295 }; 296 297 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 298 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 299 }; 300 301 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 302 { 303 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 312 }; 313 314 #define DEFAULT_SH_MEM_CONFIG \ 315 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 316 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 317 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 318 319 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 320 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 321 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 322 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 323 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 324 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 325 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 326 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 327 struct amdgpu_cu_info *cu_info); 328 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 329 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 330 u32 sh_num, u32 instance, int xcc_id); 331 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 332 333 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 334 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 335 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 336 uint32_t val); 337 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 338 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 339 uint16_t pasid, uint32_t flush_type, 340 bool all_hub, uint8_t dst_sel); 341 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 342 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 343 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 344 bool enable); 345 346 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 347 { 348 struct amdgpu_device *adev = kiq_ring->adev; 349 u64 shader_mc_addr; 350 351 /* Cleaner shader MC address */ 352 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 353 354 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 355 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 356 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 357 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 358 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 359 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 360 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 361 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 362 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 363 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 364 } 365 366 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 367 struct amdgpu_ring *ring) 368 { 369 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 370 uint64_t wptr_addr = ring->wptr_gpu_addr; 371 uint32_t me = 0, eng_sel = 0; 372 373 switch (ring->funcs->type) { 374 case AMDGPU_RING_TYPE_COMPUTE: 375 me = 1; 376 eng_sel = 0; 377 break; 378 case AMDGPU_RING_TYPE_GFX: 379 me = 0; 380 eng_sel = 4; 381 break; 382 case AMDGPU_RING_TYPE_MES: 383 me = 2; 384 eng_sel = 5; 385 break; 386 default: 387 WARN_ON(1); 388 } 389 390 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 391 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 392 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 393 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 394 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 395 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 396 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 397 PACKET3_MAP_QUEUES_ME((me)) | 398 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 399 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 400 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 401 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 402 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 403 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 404 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 405 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 406 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 407 } 408 409 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 410 struct amdgpu_ring *ring, 411 enum amdgpu_unmap_queues_action action, 412 u64 gpu_addr, u64 seq) 413 { 414 struct amdgpu_device *adev = kiq_ring->adev; 415 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 416 417 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 418 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 419 return; 420 } 421 422 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 423 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 424 PACKET3_UNMAP_QUEUES_ACTION(action) | 425 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 426 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 427 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 428 amdgpu_ring_write(kiq_ring, 429 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 430 431 if (action == PREEMPT_QUEUES_NO_UNMAP) { 432 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 433 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 434 amdgpu_ring_write(kiq_ring, seq); 435 } else { 436 amdgpu_ring_write(kiq_ring, 0); 437 amdgpu_ring_write(kiq_ring, 0); 438 amdgpu_ring_write(kiq_ring, 0); 439 } 440 } 441 442 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 443 struct amdgpu_ring *ring, 444 u64 addr, 445 u64 seq) 446 { 447 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 448 449 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 450 amdgpu_ring_write(kiq_ring, 451 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 452 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 453 PACKET3_QUERY_STATUS_COMMAND(2)); 454 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 455 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 456 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 457 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 458 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 459 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 460 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 461 } 462 463 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 464 uint16_t pasid, uint32_t flush_type, 465 bool all_hub) 466 { 467 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 468 } 469 470 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 471 .kiq_set_resources = gfx11_kiq_set_resources, 472 .kiq_map_queues = gfx11_kiq_map_queues, 473 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 474 .kiq_query_status = gfx11_kiq_query_status, 475 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 476 .set_resources_size = 8, 477 .map_queues_size = 7, 478 .unmap_queues_size = 6, 479 .query_status_size = 7, 480 .invalidate_tlbs_size = 2, 481 }; 482 483 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 484 { 485 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 486 } 487 488 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 489 { 490 if (amdgpu_sriov_vf(adev)) 491 return; 492 493 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 494 case IP_VERSION(11, 0, 1): 495 case IP_VERSION(11, 0, 4): 496 soc15_program_register_sequence(adev, 497 golden_settings_gc_11_0_1, 498 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 499 break; 500 default: 501 break; 502 } 503 soc15_program_register_sequence(adev, 504 golden_settings_gc_11_0, 505 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 506 507 } 508 509 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 510 bool wc, uint32_t reg, uint32_t val) 511 { 512 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 513 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 514 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 515 amdgpu_ring_write(ring, reg); 516 amdgpu_ring_write(ring, 0); 517 amdgpu_ring_write(ring, val); 518 } 519 520 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 521 int mem_space, int opt, uint32_t addr0, 522 uint32_t addr1, uint32_t ref, uint32_t mask, 523 uint32_t inv) 524 { 525 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 526 amdgpu_ring_write(ring, 527 /* memory (1) or register (0) */ 528 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 529 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 530 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 531 WAIT_REG_MEM_ENGINE(eng_sel))); 532 533 if (mem_space) 534 BUG_ON(addr0 & 0x3); /* Dword align */ 535 amdgpu_ring_write(ring, addr0); 536 amdgpu_ring_write(ring, addr1); 537 amdgpu_ring_write(ring, ref); 538 amdgpu_ring_write(ring, mask); 539 amdgpu_ring_write(ring, inv); /* poll interval */ 540 } 541 542 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 543 { 544 /* Header itself is a NOP packet */ 545 if (num_nop == 1) { 546 amdgpu_ring_write(ring, ring->funcs->nop); 547 return; 548 } 549 550 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 551 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 552 553 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 554 amdgpu_ring_insert_nop(ring, num_nop - 1); 555 } 556 557 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 558 { 559 struct amdgpu_device *adev = ring->adev; 560 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 561 uint32_t tmp = 0; 562 unsigned i; 563 int r; 564 565 WREG32(scratch, 0xCAFEDEAD); 566 r = amdgpu_ring_alloc(ring, 5); 567 if (r) { 568 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 569 ring->idx, r); 570 return r; 571 } 572 573 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 574 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 575 } else { 576 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 577 amdgpu_ring_write(ring, scratch - 578 PACKET3_SET_UCONFIG_REG_START); 579 amdgpu_ring_write(ring, 0xDEADBEEF); 580 } 581 amdgpu_ring_commit(ring); 582 583 for (i = 0; i < adev->usec_timeout; i++) { 584 tmp = RREG32(scratch); 585 if (tmp == 0xDEADBEEF) 586 break; 587 if (amdgpu_emu_mode == 1) 588 msleep(1); 589 else 590 udelay(1); 591 } 592 593 if (i >= adev->usec_timeout) 594 r = -ETIMEDOUT; 595 return r; 596 } 597 598 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 599 { 600 struct amdgpu_device *adev = ring->adev; 601 struct amdgpu_ib ib; 602 struct dma_fence *f = NULL; 603 unsigned index; 604 uint64_t gpu_addr; 605 volatile uint32_t *cpu_ptr; 606 long r; 607 608 /* MES KIQ fw hasn't indirect buffer support for now */ 609 if (adev->enable_mes_kiq && 610 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 611 return 0; 612 613 memset(&ib, 0, sizeof(ib)); 614 615 r = amdgpu_device_wb_get(adev, &index); 616 if (r) 617 return r; 618 619 gpu_addr = adev->wb.gpu_addr + (index * 4); 620 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 621 cpu_ptr = &adev->wb.wb[index]; 622 623 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 624 if (r) { 625 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 626 goto err1; 627 } 628 629 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 630 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 631 ib.ptr[2] = lower_32_bits(gpu_addr); 632 ib.ptr[3] = upper_32_bits(gpu_addr); 633 ib.ptr[4] = 0xDEADBEEF; 634 ib.length_dw = 5; 635 636 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 637 if (r) 638 goto err2; 639 640 r = dma_fence_wait_timeout(f, false, timeout); 641 if (r == 0) { 642 r = -ETIMEDOUT; 643 goto err2; 644 } else if (r < 0) { 645 goto err2; 646 } 647 648 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 649 r = 0; 650 else 651 r = -EINVAL; 652 err2: 653 amdgpu_ib_free(&ib, NULL); 654 dma_fence_put(f); 655 err1: 656 amdgpu_device_wb_free(adev, index); 657 return r; 658 } 659 660 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 661 { 662 amdgpu_ucode_release(&adev->gfx.pfp_fw); 663 amdgpu_ucode_release(&adev->gfx.me_fw); 664 amdgpu_ucode_release(&adev->gfx.rlc_fw); 665 amdgpu_ucode_release(&adev->gfx.mec_fw); 666 667 kfree(adev->gfx.rlc.register_list_format); 668 } 669 670 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 671 { 672 const struct psp_firmware_header_v1_0 *toc_hdr; 673 int err = 0; 674 675 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 676 AMDGPU_UCODE_REQUIRED, 677 "amdgpu/%s_toc.bin", ucode_prefix); 678 if (err) 679 goto out; 680 681 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 682 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 683 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 684 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 685 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 686 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 687 return 0; 688 out: 689 amdgpu_ucode_release(&adev->psp.toc_fw); 690 return err; 691 } 692 693 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 694 { 695 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 696 case IP_VERSION(11, 0, 0): 697 case IP_VERSION(11, 0, 2): 698 case IP_VERSION(11, 0, 3): 699 if ((adev->gfx.me_fw_version >= 1505) && 700 (adev->gfx.pfp_fw_version >= 1600) && 701 (adev->gfx.mec_fw_version >= 512)) { 702 if (amdgpu_sriov_vf(adev)) 703 adev->gfx.cp_gfx_shadow = true; 704 else 705 adev->gfx.cp_gfx_shadow = false; 706 } 707 break; 708 default: 709 adev->gfx.cp_gfx_shadow = false; 710 break; 711 } 712 } 713 714 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 715 { 716 char ucode_prefix[25]; 717 int err; 718 const struct rlc_firmware_header_v2_0 *rlc_hdr; 719 uint16_t version_major; 720 uint16_t version_minor; 721 722 DRM_DEBUG("\n"); 723 724 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 725 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 726 AMDGPU_UCODE_REQUIRED, 727 "amdgpu/%s_pfp.bin", ucode_prefix); 728 if (err) 729 goto out; 730 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 731 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 732 (union amdgpu_firmware_header *) 733 adev->gfx.pfp_fw->data, 2, 0); 734 if (adev->gfx.rs64_enable) { 735 dev_info(adev->dev, "CP RS64 enable\n"); 736 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 737 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 738 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 739 } else { 740 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 741 } 742 743 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 744 AMDGPU_UCODE_REQUIRED, 745 "amdgpu/%s_me.bin", ucode_prefix); 746 if (err) 747 goto out; 748 if (adev->gfx.rs64_enable) { 749 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 750 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 751 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 752 } else { 753 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 754 } 755 756 if (!amdgpu_sriov_vf(adev)) { 757 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 758 adev->pdev->revision == 0xCE) 759 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 760 AMDGPU_UCODE_REQUIRED, 761 "amdgpu/gc_11_0_0_rlc_1.bin"); 762 else 763 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 764 AMDGPU_UCODE_REQUIRED, 765 "amdgpu/%s_rlc.bin", ucode_prefix); 766 if (err) 767 goto out; 768 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 769 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 770 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 771 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 772 if (err) 773 goto out; 774 } 775 776 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 777 AMDGPU_UCODE_REQUIRED, 778 "amdgpu/%s_mec.bin", ucode_prefix); 779 if (err) 780 goto out; 781 if (adev->gfx.rs64_enable) { 782 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 783 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 784 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 785 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 786 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 787 } else { 788 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 789 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 790 } 791 792 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 793 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 794 795 /* only one MEC for gfx 11.0.0. */ 796 adev->gfx.mec2_fw = NULL; 797 798 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 799 800 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 801 err = adev->gfx.imu.funcs->init_microcode(adev); 802 if (err) 803 DRM_ERROR("Failed to init imu firmware!\n"); 804 return err; 805 } 806 807 out: 808 if (err) { 809 amdgpu_ucode_release(&adev->gfx.pfp_fw); 810 amdgpu_ucode_release(&adev->gfx.me_fw); 811 amdgpu_ucode_release(&adev->gfx.rlc_fw); 812 amdgpu_ucode_release(&adev->gfx.mec_fw); 813 } 814 815 return err; 816 } 817 818 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 819 { 820 u32 count = 0; 821 const struct cs_section_def *sect = NULL; 822 const struct cs_extent_def *ext = NULL; 823 824 /* begin clear state */ 825 count += 2; 826 /* context control state */ 827 count += 3; 828 829 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 830 for (ext = sect->section; ext->extent != NULL; ++ext) { 831 if (sect->id == SECT_CONTEXT) 832 count += 2 + ext->reg_count; 833 else 834 return 0; 835 } 836 } 837 838 /* set PA_SC_TILE_STEERING_OVERRIDE */ 839 count += 3; 840 /* end clear state */ 841 count += 2; 842 /* clear state */ 843 count += 2; 844 845 return count; 846 } 847 848 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 849 volatile u32 *buffer) 850 { 851 u32 count = 0, i; 852 const struct cs_section_def *sect = NULL; 853 const struct cs_extent_def *ext = NULL; 854 int ctx_reg_offset; 855 856 if (adev->gfx.rlc.cs_data == NULL) 857 return; 858 if (buffer == NULL) 859 return; 860 861 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 862 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 863 864 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 865 buffer[count++] = cpu_to_le32(0x80000000); 866 buffer[count++] = cpu_to_le32(0x80000000); 867 868 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 869 for (ext = sect->section; ext->extent != NULL; ++ext) { 870 if (sect->id == SECT_CONTEXT) { 871 buffer[count++] = 872 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 873 buffer[count++] = cpu_to_le32(ext->reg_index - 874 PACKET3_SET_CONTEXT_REG_START); 875 for (i = 0; i < ext->reg_count; i++) 876 buffer[count++] = cpu_to_le32(ext->extent[i]); 877 } 878 } 879 } 880 881 ctx_reg_offset = 882 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 883 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 884 buffer[count++] = cpu_to_le32(ctx_reg_offset); 885 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 886 887 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 888 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 889 890 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 891 buffer[count++] = cpu_to_le32(0); 892 } 893 894 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 895 { 896 /* clear state block */ 897 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 898 &adev->gfx.rlc.clear_state_gpu_addr, 899 (void **)&adev->gfx.rlc.cs_ptr); 900 901 /* jump table block */ 902 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 903 &adev->gfx.rlc.cp_table_gpu_addr, 904 (void **)&adev->gfx.rlc.cp_table_ptr); 905 } 906 907 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 908 { 909 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 910 911 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 912 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 913 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 914 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 915 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 916 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 917 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 918 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 919 adev->gfx.rlc.rlcg_reg_access_supported = true; 920 } 921 922 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 923 { 924 const struct cs_section_def *cs_data; 925 int r; 926 927 adev->gfx.rlc.cs_data = gfx11_cs_data; 928 929 cs_data = adev->gfx.rlc.cs_data; 930 931 if (cs_data) { 932 /* init clear state block */ 933 r = amdgpu_gfx_rlc_init_csb(adev); 934 if (r) 935 return r; 936 } 937 938 /* init spm vmid with 0xf */ 939 if (adev->gfx.rlc.funcs->update_spm_vmid) 940 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 941 942 return 0; 943 } 944 945 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 946 { 947 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 948 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 949 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 950 } 951 952 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 953 { 954 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 955 956 amdgpu_gfx_graphics_queue_acquire(adev); 957 } 958 959 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 960 { 961 int r; 962 u32 *hpd; 963 size_t mec_hpd_size; 964 965 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 966 967 /* take ownership of the relevant compute queues */ 968 amdgpu_gfx_compute_queue_acquire(adev); 969 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 970 971 if (mec_hpd_size) { 972 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 973 AMDGPU_GEM_DOMAIN_GTT, 974 &adev->gfx.mec.hpd_eop_obj, 975 &adev->gfx.mec.hpd_eop_gpu_addr, 976 (void **)&hpd); 977 if (r) { 978 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 979 gfx_v11_0_mec_fini(adev); 980 return r; 981 } 982 983 memset(hpd, 0, mec_hpd_size); 984 985 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 986 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 987 } 988 989 return 0; 990 } 991 992 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 993 { 994 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 995 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 996 (address << SQ_IND_INDEX__INDEX__SHIFT)); 997 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 998 } 999 1000 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1001 uint32_t thread, uint32_t regno, 1002 uint32_t num, uint32_t *out) 1003 { 1004 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1005 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1006 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1007 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1008 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1009 while (num--) 1010 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1011 } 1012 1013 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1014 { 1015 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1016 * field when performing a select_se_sh so it should be 1017 * zero here */ 1018 WARN_ON(simd != 0); 1019 1020 /* type 3 wave data */ 1021 dst[(*no_fields)++] = 3; 1022 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1023 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1024 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1025 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1026 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1027 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1028 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1029 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1030 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1031 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1032 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1033 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1034 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1035 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1036 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1037 } 1038 1039 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1040 uint32_t wave, uint32_t start, 1041 uint32_t size, uint32_t *dst) 1042 { 1043 WARN_ON(simd != 0); 1044 1045 wave_read_regs( 1046 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1047 dst); 1048 } 1049 1050 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1051 uint32_t wave, uint32_t thread, 1052 uint32_t start, uint32_t size, 1053 uint32_t *dst) 1054 { 1055 wave_read_regs( 1056 adev, wave, thread, 1057 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1058 } 1059 1060 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1061 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1062 { 1063 soc21_grbm_select(adev, me, pipe, q, vm); 1064 } 1065 1066 /* all sizes are in bytes */ 1067 #define MQD_SHADOW_BASE_SIZE 73728 1068 #define MQD_SHADOW_BASE_ALIGNMENT 256 1069 #define MQD_FWWORKAREA_SIZE 484 1070 #define MQD_FWWORKAREA_ALIGNMENT 256 1071 1072 static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 1073 struct amdgpu_gfx_shadow_info *shadow_info) 1074 { 1075 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1076 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1077 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1078 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1079 } 1080 1081 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1082 struct amdgpu_gfx_shadow_info *shadow_info, 1083 bool skip_check) 1084 { 1085 if (adev->gfx.cp_gfx_shadow || skip_check) { 1086 gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 1087 return 0; 1088 } else { 1089 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1090 return -ENOTSUPP; 1091 } 1092 } 1093 1094 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1095 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1096 .select_se_sh = &gfx_v11_0_select_se_sh, 1097 .read_wave_data = &gfx_v11_0_read_wave_data, 1098 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1099 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1100 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1101 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1102 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1103 }; 1104 1105 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1106 { 1107 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1108 case IP_VERSION(11, 0, 0): 1109 case IP_VERSION(11, 0, 2): 1110 adev->gfx.config.max_hw_contexts = 8; 1111 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1112 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1113 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1114 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1115 break; 1116 case IP_VERSION(11, 0, 3): 1117 adev->gfx.ras = &gfx_v11_0_3_ras; 1118 adev->gfx.config.max_hw_contexts = 8; 1119 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1120 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1121 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1122 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1123 break; 1124 case IP_VERSION(11, 0, 1): 1125 case IP_VERSION(11, 0, 4): 1126 case IP_VERSION(11, 5, 0): 1127 case IP_VERSION(11, 5, 1): 1128 case IP_VERSION(11, 5, 2): 1129 case IP_VERSION(11, 5, 3): 1130 adev->gfx.config.max_hw_contexts = 8; 1131 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1132 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1133 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1134 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1135 break; 1136 default: 1137 BUG(); 1138 break; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1145 int me, int pipe, int queue) 1146 { 1147 struct amdgpu_ring *ring; 1148 unsigned int irq_type; 1149 unsigned int hw_prio; 1150 1151 ring = &adev->gfx.gfx_ring[ring_id]; 1152 1153 ring->me = me; 1154 ring->pipe = pipe; 1155 ring->queue = queue; 1156 1157 ring->ring_obj = NULL; 1158 ring->use_doorbell = true; 1159 if (adev->gfx.disable_kq) { 1160 ring->no_scheduler = true; 1161 ring->no_user_submission = true; 1162 } 1163 1164 if (!ring_id) 1165 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1166 else 1167 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1168 ring->vm_hub = AMDGPU_GFXHUB(0); 1169 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1170 1171 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1172 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1173 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1174 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1175 hw_prio, NULL); 1176 } 1177 1178 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1179 int mec, int pipe, int queue) 1180 { 1181 int r; 1182 unsigned irq_type; 1183 struct amdgpu_ring *ring; 1184 unsigned int hw_prio; 1185 1186 ring = &adev->gfx.compute_ring[ring_id]; 1187 1188 /* mec0 is me1 */ 1189 ring->me = mec + 1; 1190 ring->pipe = pipe; 1191 ring->queue = queue; 1192 1193 ring->ring_obj = NULL; 1194 ring->use_doorbell = true; 1195 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1196 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1197 + (ring_id * GFX11_MEC_HPD_SIZE); 1198 ring->vm_hub = AMDGPU_GFXHUB(0); 1199 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1200 1201 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1202 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1203 + ring->pipe; 1204 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1205 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1206 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1207 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1208 hw_prio, NULL); 1209 if (r) 1210 return r; 1211 1212 return 0; 1213 } 1214 1215 static struct { 1216 SOC21_FIRMWARE_ID id; 1217 unsigned int offset; 1218 unsigned int size; 1219 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1220 1221 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1222 { 1223 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1224 1225 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1226 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1227 rlc_autoload_info[ucode->id].id = ucode->id; 1228 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1229 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1230 1231 ucode++; 1232 } 1233 } 1234 1235 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1236 { 1237 uint32_t total_size = 0; 1238 SOC21_FIRMWARE_ID id; 1239 1240 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1241 1242 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1243 total_size += rlc_autoload_info[id].size; 1244 1245 /* In case the offset in rlc toc ucode is aligned */ 1246 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1247 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1248 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1249 1250 return total_size; 1251 } 1252 1253 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1254 { 1255 int r; 1256 uint32_t total_size; 1257 1258 total_size = gfx_v11_0_calc_toc_total_size(adev); 1259 1260 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1261 AMDGPU_GEM_DOMAIN_VRAM | 1262 AMDGPU_GEM_DOMAIN_GTT, 1263 &adev->gfx.rlc.rlc_autoload_bo, 1264 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1265 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1266 1267 if (r) { 1268 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1269 return r; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1276 SOC21_FIRMWARE_ID id, 1277 const void *fw_data, 1278 uint32_t fw_size, 1279 uint32_t *fw_autoload_mask) 1280 { 1281 uint32_t toc_offset; 1282 uint32_t toc_fw_size; 1283 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1284 1285 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1286 return; 1287 1288 toc_offset = rlc_autoload_info[id].offset; 1289 toc_fw_size = rlc_autoload_info[id].size; 1290 1291 if (fw_size == 0) 1292 fw_size = toc_fw_size; 1293 1294 if (fw_size > toc_fw_size) 1295 fw_size = toc_fw_size; 1296 1297 memcpy(ptr + toc_offset, fw_data, fw_size); 1298 1299 if (fw_size < toc_fw_size) 1300 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1301 1302 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1303 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1304 } 1305 1306 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1307 uint32_t *fw_autoload_mask) 1308 { 1309 void *data; 1310 uint32_t size; 1311 uint64_t *toc_ptr; 1312 1313 *(uint64_t *)fw_autoload_mask |= 0x1; 1314 1315 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1316 1317 data = adev->psp.toc.start_addr; 1318 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1319 1320 toc_ptr = (uint64_t *)data + size / 8 - 1; 1321 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1322 1323 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1324 data, size, fw_autoload_mask); 1325 } 1326 1327 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1328 uint32_t *fw_autoload_mask) 1329 { 1330 const __le32 *fw_data; 1331 uint32_t fw_size; 1332 const struct gfx_firmware_header_v1_0 *cp_hdr; 1333 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1334 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1335 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1336 uint16_t version_major, version_minor; 1337 1338 if (adev->gfx.rs64_enable) { 1339 /* pfp ucode */ 1340 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1341 adev->gfx.pfp_fw->data; 1342 /* instruction */ 1343 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1344 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1345 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1346 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1347 fw_data, fw_size, fw_autoload_mask); 1348 /* data */ 1349 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1350 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1351 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1352 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1353 fw_data, fw_size, fw_autoload_mask); 1354 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1355 fw_data, fw_size, fw_autoload_mask); 1356 /* me ucode */ 1357 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1358 adev->gfx.me_fw->data; 1359 /* instruction */ 1360 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1361 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1362 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1363 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1364 fw_data, fw_size, fw_autoload_mask); 1365 /* data */ 1366 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1367 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1368 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1369 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1370 fw_data, fw_size, fw_autoload_mask); 1371 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1372 fw_data, fw_size, fw_autoload_mask); 1373 /* mec ucode */ 1374 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1375 adev->gfx.mec_fw->data; 1376 /* instruction */ 1377 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1378 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1379 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1380 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1381 fw_data, fw_size, fw_autoload_mask); 1382 /* data */ 1383 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1384 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1385 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1386 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1387 fw_data, fw_size, fw_autoload_mask); 1388 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1389 fw_data, fw_size, fw_autoload_mask); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1391 fw_data, fw_size, fw_autoload_mask); 1392 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1393 fw_data, fw_size, fw_autoload_mask); 1394 } else { 1395 /* pfp ucode */ 1396 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1397 adev->gfx.pfp_fw->data; 1398 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1399 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1400 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1401 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1402 fw_data, fw_size, fw_autoload_mask); 1403 1404 /* me ucode */ 1405 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1406 adev->gfx.me_fw->data; 1407 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1408 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1409 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1410 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1411 fw_data, fw_size, fw_autoload_mask); 1412 1413 /* mec ucode */ 1414 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1415 adev->gfx.mec_fw->data; 1416 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1417 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1418 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1419 cp_hdr->jt_size * 4; 1420 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1421 fw_data, fw_size, fw_autoload_mask); 1422 } 1423 1424 /* rlc ucode */ 1425 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1426 adev->gfx.rlc_fw->data; 1427 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1428 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1429 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1430 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1431 fw_data, fw_size, fw_autoload_mask); 1432 1433 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1434 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1435 if (version_major == 2) { 1436 if (version_minor >= 2) { 1437 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1438 1439 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1440 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1441 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1442 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1443 fw_data, fw_size, fw_autoload_mask); 1444 1445 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1446 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1447 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1448 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1449 fw_data, fw_size, fw_autoload_mask); 1450 } 1451 } 1452 } 1453 1454 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1455 uint32_t *fw_autoload_mask) 1456 { 1457 const __le32 *fw_data; 1458 uint32_t fw_size; 1459 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1460 1461 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1462 adev->sdma.instance[0].fw->data; 1463 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1464 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1465 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1466 1467 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1468 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1469 1470 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1471 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1472 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1473 1474 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1475 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1476 } 1477 1478 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1479 uint32_t *fw_autoload_mask) 1480 { 1481 const __le32 *fw_data; 1482 unsigned fw_size; 1483 const struct mes_firmware_header_v1_0 *mes_hdr; 1484 int pipe, ucode_id, data_id; 1485 1486 for (pipe = 0; pipe < 2; pipe++) { 1487 if (pipe==0) { 1488 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1489 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1490 } else { 1491 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1492 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1493 } 1494 1495 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1496 adev->mes.fw[pipe]->data; 1497 1498 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1499 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1500 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1501 1502 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1503 ucode_id, fw_data, fw_size, fw_autoload_mask); 1504 1505 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1506 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1507 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1508 1509 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1510 data_id, fw_data, fw_size, fw_autoload_mask); 1511 } 1512 } 1513 1514 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1515 { 1516 uint32_t rlc_g_offset, rlc_g_size; 1517 uint64_t gpu_addr; 1518 uint32_t autoload_fw_id[2]; 1519 1520 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1521 1522 /* RLC autoload sequence 2: copy ucode */ 1523 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1524 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1525 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1526 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1527 1528 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1529 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1530 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1531 1532 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1533 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1534 1535 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1536 1537 /* RLC autoload sequence 3: load IMU fw */ 1538 if (adev->gfx.imu.funcs->load_microcode) 1539 adev->gfx.imu.funcs->load_microcode(adev); 1540 /* RLC autoload sequence 4 init IMU fw */ 1541 if (adev->gfx.imu.funcs->setup_imu) 1542 adev->gfx.imu.funcs->setup_imu(adev); 1543 if (adev->gfx.imu.funcs->start_imu) 1544 adev->gfx.imu.funcs->start_imu(adev); 1545 1546 /* RLC autoload sequence 5 disable gpa mode */ 1547 gfx_v11_0_disable_gpa_mode(adev); 1548 1549 return 0; 1550 } 1551 1552 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1553 { 1554 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1555 uint32_t *ptr; 1556 uint32_t inst; 1557 1558 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1559 if (!ptr) { 1560 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1561 adev->gfx.ip_dump_core = NULL; 1562 } else { 1563 adev->gfx.ip_dump_core = ptr; 1564 } 1565 1566 /* Allocate memory for compute queue registers for all the instances */ 1567 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1568 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1569 adev->gfx.mec.num_queue_per_pipe; 1570 1571 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1572 if (!ptr) { 1573 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1574 adev->gfx.ip_dump_compute_queues = NULL; 1575 } else { 1576 adev->gfx.ip_dump_compute_queues = ptr; 1577 } 1578 1579 /* Allocate memory for gfx queue registers for all the instances */ 1580 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1581 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1582 adev->gfx.me.num_queue_per_pipe; 1583 1584 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1585 if (!ptr) { 1586 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1587 adev->gfx.ip_dump_gfx_queues = NULL; 1588 } else { 1589 adev->gfx.ip_dump_gfx_queues = ptr; 1590 } 1591 } 1592 1593 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1594 { 1595 int i, j, k, r, ring_id; 1596 int xcc_id = 0; 1597 struct amdgpu_device *adev = ip_block->adev; 1598 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1599 1600 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1601 1602 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1603 case IP_VERSION(11, 0, 0): 1604 case IP_VERSION(11, 0, 1): 1605 case IP_VERSION(11, 0, 2): 1606 case IP_VERSION(11, 0, 3): 1607 case IP_VERSION(11, 0, 4): 1608 case IP_VERSION(11, 5, 0): 1609 case IP_VERSION(11, 5, 1): 1610 case IP_VERSION(11, 5, 2): 1611 case IP_VERSION(11, 5, 3): 1612 adev->gfx.me.num_me = 1; 1613 adev->gfx.me.num_pipe_per_me = 1; 1614 adev->gfx.me.num_queue_per_pipe = 2; 1615 adev->gfx.mec.num_mec = 1; 1616 adev->gfx.mec.num_pipe_per_mec = 4; 1617 adev->gfx.mec.num_queue_per_pipe = 4; 1618 break; 1619 default: 1620 adev->gfx.me.num_me = 1; 1621 adev->gfx.me.num_pipe_per_me = 1; 1622 adev->gfx.me.num_queue_per_pipe = 1; 1623 adev->gfx.mec.num_mec = 1; 1624 adev->gfx.mec.num_pipe_per_mec = 4; 1625 adev->gfx.mec.num_queue_per_pipe = 8; 1626 break; 1627 } 1628 1629 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1630 case IP_VERSION(11, 0, 0): 1631 case IP_VERSION(11, 0, 2): 1632 case IP_VERSION(11, 0, 3): 1633 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ 1634 /* add firmware version checks here */ 1635 if (0) { 1636 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1637 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1638 } 1639 #endif 1640 break; 1641 case IP_VERSION(11, 0, 1): 1642 case IP_VERSION(11, 0, 4): 1643 case IP_VERSION(11, 5, 0): 1644 case IP_VERSION(11, 5, 1): 1645 case IP_VERSION(11, 5, 2): 1646 case IP_VERSION(11, 5, 3): 1647 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ 1648 /* add firmware version checks here */ 1649 if (0) { 1650 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1651 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1652 } 1653 #endif 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1660 case IP_VERSION(11, 0, 0): 1661 case IP_VERSION(11, 0, 2): 1662 case IP_VERSION(11, 0, 3): 1663 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1664 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1665 if (adev->gfx.me_fw_version >= 2280 && 1666 adev->gfx.pfp_fw_version >= 2370 && 1667 adev->gfx.mec_fw_version >= 2450 && 1668 adev->mes.fw_version[0] >= 99) { 1669 adev->gfx.enable_cleaner_shader = true; 1670 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1671 if (r) { 1672 adev->gfx.enable_cleaner_shader = false; 1673 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1674 } 1675 } 1676 break; 1677 case IP_VERSION(11, 5, 0): 1678 case IP_VERSION(11, 5, 1): 1679 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1680 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1681 if (adev->gfx.mec_fw_version >= 26 && 1682 adev->mes.fw_version[0] >= 114) { 1683 adev->gfx.enable_cleaner_shader = true; 1684 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1685 if (r) { 1686 adev->gfx.enable_cleaner_shader = false; 1687 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1688 } 1689 } 1690 break; 1691 default: 1692 adev->gfx.enable_cleaner_shader = false; 1693 break; 1694 } 1695 1696 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1697 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1698 amdgpu_sriov_is_pp_one_vf(adev)) 1699 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1700 1701 /* EOP Event */ 1702 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1703 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1704 &adev->gfx.eop_irq); 1705 if (r) 1706 return r; 1707 1708 /* Bad opcode Event */ 1709 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1710 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1711 &adev->gfx.bad_op_irq); 1712 if (r) 1713 return r; 1714 1715 /* Privileged reg */ 1716 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1717 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1718 &adev->gfx.priv_reg_irq); 1719 if (r) 1720 return r; 1721 1722 /* Privileged inst */ 1723 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1724 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1725 &adev->gfx.priv_inst_irq); 1726 if (r) 1727 return r; 1728 1729 /* FED error */ 1730 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1731 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1732 &adev->gfx.rlc_gc_fed_irq); 1733 if (r) 1734 return r; 1735 1736 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1737 1738 gfx_v11_0_me_init(adev); 1739 1740 r = gfx_v11_0_rlc_init(adev); 1741 if (r) { 1742 DRM_ERROR("Failed to init rlc BOs!\n"); 1743 return r; 1744 } 1745 1746 r = gfx_v11_0_mec_init(adev); 1747 if (r) { 1748 DRM_ERROR("Failed to init MEC BOs!\n"); 1749 return r; 1750 } 1751 1752 if (adev->gfx.num_gfx_rings) { 1753 ring_id = 0; 1754 /* set up the gfx ring */ 1755 for (i = 0; i < adev->gfx.me.num_me; i++) { 1756 for (j = 0; j < num_queue_per_pipe; j++) { 1757 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1758 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1759 continue; 1760 1761 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1762 i, k, j); 1763 if (r) 1764 return r; 1765 ring_id++; 1766 } 1767 } 1768 } 1769 } 1770 1771 if (adev->gfx.num_compute_rings) { 1772 ring_id = 0; 1773 /* set up the compute queues - allocate horizontally across pipes */ 1774 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1775 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1776 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1777 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1778 k, j)) 1779 continue; 1780 1781 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1782 i, k, j); 1783 if (r) 1784 return r; 1785 1786 ring_id++; 1787 } 1788 } 1789 } 1790 } 1791 1792 adev->gfx.gfx_supported_reset = 1793 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1794 adev->gfx.compute_supported_reset = 1795 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1796 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1797 case IP_VERSION(11, 0, 0): 1798 case IP_VERSION(11, 0, 2): 1799 case IP_VERSION(11, 0, 3): 1800 if ((adev->gfx.me_fw_version >= 2280) && 1801 (adev->gfx.mec_fw_version >= 2410)) { 1802 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1803 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1804 } 1805 break; 1806 default: 1807 break; 1808 } 1809 1810 if (!adev->enable_mes_kiq) { 1811 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1812 if (r) { 1813 DRM_ERROR("Failed to init KIQ BOs!\n"); 1814 return r; 1815 } 1816 1817 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1818 if (r) 1819 return r; 1820 } 1821 1822 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1823 if (r) 1824 return r; 1825 1826 /* allocate visible FB for rlc auto-loading fw */ 1827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1828 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1829 if (r) 1830 return r; 1831 } 1832 1833 r = gfx_v11_0_gpu_early_init(adev); 1834 if (r) 1835 return r; 1836 1837 if (amdgpu_gfx_ras_sw_init(adev)) { 1838 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1839 return -EINVAL; 1840 } 1841 1842 gfx_v11_0_alloc_ip_dump(adev); 1843 1844 r = amdgpu_gfx_sysfs_init(adev); 1845 if (r) 1846 return r; 1847 1848 return 0; 1849 } 1850 1851 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1852 { 1853 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1854 &adev->gfx.pfp.pfp_fw_gpu_addr, 1855 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1856 1857 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1858 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1859 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1860 } 1861 1862 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1863 { 1864 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1865 &adev->gfx.me.me_fw_gpu_addr, 1866 (void **)&adev->gfx.me.me_fw_ptr); 1867 1868 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1869 &adev->gfx.me.me_fw_data_gpu_addr, 1870 (void **)&adev->gfx.me.me_fw_data_ptr); 1871 } 1872 1873 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1874 { 1875 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1876 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1877 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1878 } 1879 1880 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1881 { 1882 int i; 1883 struct amdgpu_device *adev = ip_block->adev; 1884 1885 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1886 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1887 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1888 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1889 1890 amdgpu_gfx_mqd_sw_fini(adev, 0); 1891 1892 if (!adev->enable_mes_kiq) { 1893 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1894 amdgpu_gfx_kiq_fini(adev, 0); 1895 } 1896 1897 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1898 1899 gfx_v11_0_pfp_fini(adev); 1900 gfx_v11_0_me_fini(adev); 1901 gfx_v11_0_rlc_fini(adev); 1902 gfx_v11_0_mec_fini(adev); 1903 1904 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1905 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1906 1907 gfx_v11_0_free_microcode(adev); 1908 1909 amdgpu_gfx_sysfs_fini(adev); 1910 1911 kfree(adev->gfx.ip_dump_core); 1912 kfree(adev->gfx.ip_dump_compute_queues); 1913 kfree(adev->gfx.ip_dump_gfx_queues); 1914 1915 return 0; 1916 } 1917 1918 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1919 u32 sh_num, u32 instance, int xcc_id) 1920 { 1921 u32 data; 1922 1923 if (instance == 0xffffffff) 1924 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1925 INSTANCE_BROADCAST_WRITES, 1); 1926 else 1927 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1928 instance); 1929 1930 if (se_num == 0xffffffff) 1931 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1932 1); 1933 else 1934 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1935 1936 if (sh_num == 0xffffffff) 1937 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1938 1); 1939 else 1940 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1941 1942 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1943 } 1944 1945 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1946 { 1947 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1948 1949 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1950 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1951 CC_GC_SA_UNIT_DISABLE, 1952 SA_DISABLE); 1953 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1954 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1955 GC_USER_SA_UNIT_DISABLE, 1956 SA_DISABLE); 1957 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1958 adev->gfx.config.max_shader_engines); 1959 1960 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1961 } 1962 1963 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1964 { 1965 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1966 u32 rb_mask; 1967 1968 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1969 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1970 CC_RB_BACKEND_DISABLE, 1971 BACKEND_DISABLE); 1972 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1973 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1974 GC_USER_RB_BACKEND_DISABLE, 1975 BACKEND_DISABLE); 1976 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1977 adev->gfx.config.max_shader_engines); 1978 1979 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1980 } 1981 1982 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1983 { 1984 u32 rb_bitmap_per_sa; 1985 u32 rb_bitmap_width_per_sa; 1986 u32 max_sa; 1987 u32 active_sa_bitmap; 1988 u32 global_active_rb_bitmap; 1989 u32 active_rb_bitmap = 0; 1990 u32 i; 1991 1992 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1993 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1994 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1995 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1996 1997 /* generate active rb bitmap according to active sa bitmap */ 1998 max_sa = adev->gfx.config.max_shader_engines * 1999 adev->gfx.config.max_sh_per_se; 2000 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 2001 adev->gfx.config.max_sh_per_se; 2002 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 2003 2004 for (i = 0; i < max_sa; i++) { 2005 if (active_sa_bitmap & (1 << i)) 2006 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 2007 } 2008 2009 active_rb_bitmap &= global_active_rb_bitmap; 2010 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 2011 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 2012 } 2013 2014 #define DEFAULT_SH_MEM_BASES (0x6000) 2015 #define LDS_APP_BASE 0x1 2016 #define SCRATCH_APP_BASE 0x2 2017 2018 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 2019 { 2020 int i; 2021 uint32_t sh_mem_bases; 2022 uint32_t data; 2023 2024 /* 2025 * Configure apertures: 2026 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2027 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2028 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2029 */ 2030 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 2031 SCRATCH_APP_BASE; 2032 2033 mutex_lock(&adev->srbm_mutex); 2034 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2035 soc21_grbm_select(adev, 0, 0, 0, i); 2036 /* CP and shaders */ 2037 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2038 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 2039 2040 /* Enable trap for each kfd vmid. */ 2041 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 2042 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 2043 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 2044 } 2045 soc21_grbm_select(adev, 0, 0, 0, 0); 2046 mutex_unlock(&adev->srbm_mutex); 2047 2048 /* 2049 * Initialize all compute VMIDs to have no GDS, GWS, or OA 2050 * access. These should be enabled by FW for target VMIDs. 2051 */ 2052 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2053 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 2054 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 2055 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 2056 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 2057 } 2058 } 2059 2060 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 2061 { 2062 int vmid; 2063 2064 /* 2065 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2066 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2067 * the driver can enable them for graphics. VMID0 should maintain 2068 * access so that HWS firmware can save/restore entries. 2069 */ 2070 for (vmid = 1; vmid < 16; vmid++) { 2071 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 2072 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 2073 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 2074 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 2075 } 2076 } 2077 2078 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 2079 { 2080 /* TODO: harvest feature to be added later. */ 2081 } 2082 2083 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2084 { 2085 /* TCCs are global (not instanced). */ 2086 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2087 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2088 2089 adev->gfx.config.tcc_disabled_mask = 2090 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2091 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2092 } 2093 2094 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2095 { 2096 u32 tmp; 2097 int i; 2098 2099 if (!amdgpu_sriov_vf(adev)) 2100 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2101 2102 gfx_v11_0_setup_rb(adev); 2103 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2104 gfx_v11_0_get_tcc_info(adev); 2105 adev->gfx.config.pa_sc_tile_steering_override = 0; 2106 2107 /* Set whether texture coordinate truncation is conformant. */ 2108 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2109 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2110 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2111 2112 /* XXX SH_MEM regs */ 2113 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2114 mutex_lock(&adev->srbm_mutex); 2115 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2116 soc21_grbm_select(adev, 0, 0, 0, i); 2117 /* CP and shaders */ 2118 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2119 if (i != 0) { 2120 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2121 (adev->gmc.private_aperture_start >> 48)); 2122 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2123 (adev->gmc.shared_aperture_start >> 48)); 2124 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2125 } 2126 } 2127 soc21_grbm_select(adev, 0, 0, 0, 0); 2128 2129 mutex_unlock(&adev->srbm_mutex); 2130 2131 gfx_v11_0_init_compute_vmid(adev); 2132 gfx_v11_0_init_gds_vmid(adev); 2133 } 2134 2135 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2136 int me, int pipe) 2137 { 2138 if (me != 0) 2139 return 0; 2140 2141 switch (pipe) { 2142 case 0: 2143 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2144 case 1: 2145 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2146 default: 2147 return 0; 2148 } 2149 } 2150 2151 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2152 int me, int pipe) 2153 { 2154 /* 2155 * amdgpu controls only the first MEC. That's why this function only 2156 * handles the setting of interrupts for this specific MEC. All other 2157 * pipes' interrupts are set by amdkfd. 2158 */ 2159 if (me != 1) 2160 return 0; 2161 2162 switch (pipe) { 2163 case 0: 2164 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2165 case 1: 2166 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2167 case 2: 2168 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2169 case 3: 2170 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2171 default: 2172 return 0; 2173 } 2174 } 2175 2176 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2177 bool enable) 2178 { 2179 u32 tmp, cp_int_cntl_reg; 2180 int i, j; 2181 2182 if (amdgpu_sriov_vf(adev)) 2183 return; 2184 2185 for (i = 0; i < adev->gfx.me.num_me; i++) { 2186 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2187 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2188 2189 if (cp_int_cntl_reg) { 2190 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2191 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2192 enable ? 1 : 0); 2193 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2194 enable ? 1 : 0); 2195 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2196 enable ? 1 : 0); 2197 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2198 enable ? 1 : 0); 2199 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2200 } 2201 } 2202 } 2203 } 2204 2205 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2206 { 2207 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2208 2209 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2210 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2211 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2212 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2213 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2214 2215 return 0; 2216 } 2217 2218 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2219 { 2220 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2221 2222 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2223 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2224 } 2225 2226 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2227 { 2228 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2229 udelay(50); 2230 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2231 udelay(50); 2232 } 2233 2234 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2235 bool enable) 2236 { 2237 uint32_t rlc_pg_cntl; 2238 2239 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2240 2241 if (!enable) { 2242 /* RLC_PG_CNTL[23] = 0 (default) 2243 * RLC will wait for handshake acks with SMU 2244 * GFXOFF will be enabled 2245 * RLC_PG_CNTL[23] = 1 2246 * RLC will not issue any message to SMU 2247 * hence no handshake between SMU & RLC 2248 * GFXOFF will be disabled 2249 */ 2250 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2251 } else 2252 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2253 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2254 } 2255 2256 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2257 { 2258 /* TODO: enable rlc & smu handshake until smu 2259 * and gfxoff feature works as expected */ 2260 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2261 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2262 2263 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2264 udelay(50); 2265 } 2266 2267 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2268 { 2269 uint32_t tmp; 2270 2271 /* enable Save Restore Machine */ 2272 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2273 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2274 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2275 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2276 } 2277 2278 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2279 { 2280 const struct rlc_firmware_header_v2_0 *hdr; 2281 const __le32 *fw_data; 2282 unsigned i, fw_size; 2283 2284 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2285 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2286 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2287 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2288 2289 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2290 RLCG_UCODE_LOADING_START_ADDRESS); 2291 2292 for (i = 0; i < fw_size; i++) 2293 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2294 le32_to_cpup(fw_data++)); 2295 2296 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2297 } 2298 2299 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2300 { 2301 const struct rlc_firmware_header_v2_2 *hdr; 2302 const __le32 *fw_data; 2303 unsigned i, fw_size; 2304 u32 tmp; 2305 2306 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2307 2308 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2309 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2310 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2311 2312 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2313 2314 for (i = 0; i < fw_size; i++) { 2315 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2316 msleep(1); 2317 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2318 le32_to_cpup(fw_data++)); 2319 } 2320 2321 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2322 2323 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2324 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2325 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2326 2327 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2328 for (i = 0; i < fw_size; i++) { 2329 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2330 msleep(1); 2331 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2332 le32_to_cpup(fw_data++)); 2333 } 2334 2335 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2336 2337 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2338 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2339 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2340 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2341 } 2342 2343 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2344 { 2345 const struct rlc_firmware_header_v2_3 *hdr; 2346 const __le32 *fw_data; 2347 unsigned i, fw_size; 2348 u32 tmp; 2349 2350 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2351 2352 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2353 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2354 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2355 2356 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2357 2358 for (i = 0; i < fw_size; i++) { 2359 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2360 msleep(1); 2361 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2362 le32_to_cpup(fw_data++)); 2363 } 2364 2365 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2366 2367 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2368 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2369 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2370 2371 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2372 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2373 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2374 2375 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2376 2377 for (i = 0; i < fw_size; i++) { 2378 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2379 msleep(1); 2380 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2381 le32_to_cpup(fw_data++)); 2382 } 2383 2384 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2385 2386 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2387 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2388 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2389 } 2390 2391 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2392 { 2393 const struct rlc_firmware_header_v2_0 *hdr; 2394 uint16_t version_major; 2395 uint16_t version_minor; 2396 2397 if (!adev->gfx.rlc_fw) 2398 return -EINVAL; 2399 2400 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2401 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2402 2403 version_major = le16_to_cpu(hdr->header.header_version_major); 2404 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2405 2406 if (version_major == 2) { 2407 gfx_v11_0_load_rlcg_microcode(adev); 2408 if (amdgpu_dpm == 1) { 2409 if (version_minor >= 2) 2410 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2411 if (version_minor == 3) 2412 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2413 } 2414 2415 return 0; 2416 } 2417 2418 return -EINVAL; 2419 } 2420 2421 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2422 { 2423 int r; 2424 2425 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2426 gfx_v11_0_init_csb(adev); 2427 2428 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2429 gfx_v11_0_rlc_enable_srm(adev); 2430 } else { 2431 if (amdgpu_sriov_vf(adev)) { 2432 gfx_v11_0_init_csb(adev); 2433 return 0; 2434 } 2435 2436 adev->gfx.rlc.funcs->stop(adev); 2437 2438 /* disable CG */ 2439 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2440 2441 /* disable PG */ 2442 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2443 2444 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2445 /* legacy rlc firmware loading */ 2446 r = gfx_v11_0_rlc_load_microcode(adev); 2447 if (r) 2448 return r; 2449 } 2450 2451 gfx_v11_0_init_csb(adev); 2452 2453 adev->gfx.rlc.funcs->start(adev); 2454 } 2455 return 0; 2456 } 2457 2458 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2459 { 2460 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2461 uint32_t tmp; 2462 int i; 2463 2464 /* Trigger an invalidation of the L1 instruction caches */ 2465 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2466 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2467 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2468 2469 /* Wait for invalidation complete */ 2470 for (i = 0; i < usec_timeout; i++) { 2471 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2472 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2473 INVALIDATE_CACHE_COMPLETE)) 2474 break; 2475 udelay(1); 2476 } 2477 2478 if (i >= usec_timeout) { 2479 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2480 return -EINVAL; 2481 } 2482 2483 if (amdgpu_emu_mode == 1) 2484 adev->hdp.funcs->flush_hdp(adev, NULL); 2485 2486 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2487 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2488 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2489 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2490 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2491 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2492 2493 /* Program me ucode address into intruction cache address register */ 2494 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2495 lower_32_bits(addr) & 0xFFFFF000); 2496 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2497 upper_32_bits(addr)); 2498 2499 return 0; 2500 } 2501 2502 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2503 { 2504 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2505 uint32_t tmp; 2506 int i; 2507 2508 /* Trigger an invalidation of the L1 instruction caches */ 2509 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2510 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2511 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2512 2513 /* Wait for invalidation complete */ 2514 for (i = 0; i < usec_timeout; i++) { 2515 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2516 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2517 INVALIDATE_CACHE_COMPLETE)) 2518 break; 2519 udelay(1); 2520 } 2521 2522 if (i >= usec_timeout) { 2523 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2524 return -EINVAL; 2525 } 2526 2527 if (amdgpu_emu_mode == 1) 2528 adev->hdp.funcs->flush_hdp(adev, NULL); 2529 2530 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2531 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2532 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2533 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2534 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2535 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2536 2537 /* Program pfp ucode address into intruction cache address register */ 2538 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2539 lower_32_bits(addr) & 0xFFFFF000); 2540 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2541 upper_32_bits(addr)); 2542 2543 return 0; 2544 } 2545 2546 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2547 { 2548 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2549 uint32_t tmp; 2550 int i; 2551 2552 /* Trigger an invalidation of the L1 instruction caches */ 2553 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2554 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2555 2556 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2557 2558 /* Wait for invalidation complete */ 2559 for (i = 0; i < usec_timeout; i++) { 2560 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2561 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2562 INVALIDATE_CACHE_COMPLETE)) 2563 break; 2564 udelay(1); 2565 } 2566 2567 if (i >= usec_timeout) { 2568 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2569 return -EINVAL; 2570 } 2571 2572 if (amdgpu_emu_mode == 1) 2573 adev->hdp.funcs->flush_hdp(adev, NULL); 2574 2575 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2576 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2577 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2578 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2579 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2580 2581 /* Program mec1 ucode address into intruction cache address register */ 2582 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2583 lower_32_bits(addr) & 0xFFFFF000); 2584 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2585 upper_32_bits(addr)); 2586 2587 return 0; 2588 } 2589 2590 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2591 { 2592 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2593 uint32_t tmp; 2594 unsigned i, pipe_id; 2595 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2596 2597 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2598 adev->gfx.pfp_fw->data; 2599 2600 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2601 lower_32_bits(addr)); 2602 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2603 upper_32_bits(addr)); 2604 2605 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2606 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2607 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2608 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2609 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2610 2611 /* 2612 * Programming any of the CP_PFP_IC_BASE registers 2613 * forces invalidation of the ME L1 I$. Wait for the 2614 * invalidation complete 2615 */ 2616 for (i = 0; i < usec_timeout; i++) { 2617 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2618 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2619 INVALIDATE_CACHE_COMPLETE)) 2620 break; 2621 udelay(1); 2622 } 2623 2624 if (i >= usec_timeout) { 2625 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2626 return -EINVAL; 2627 } 2628 2629 /* Prime the L1 instruction caches */ 2630 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2631 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2632 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2633 /* Waiting for cache primed*/ 2634 for (i = 0; i < usec_timeout; i++) { 2635 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2636 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2637 ICACHE_PRIMED)) 2638 break; 2639 udelay(1); 2640 } 2641 2642 if (i >= usec_timeout) { 2643 dev_err(adev->dev, "failed to prime instruction cache\n"); 2644 return -EINVAL; 2645 } 2646 2647 mutex_lock(&adev->srbm_mutex); 2648 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2649 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2650 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2651 (pfp_hdr->ucode_start_addr_hi << 30) | 2652 (pfp_hdr->ucode_start_addr_lo >> 2)); 2653 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2654 pfp_hdr->ucode_start_addr_hi >> 2); 2655 2656 /* 2657 * Program CP_ME_CNTL to reset given PIPE to take 2658 * effect of CP_PFP_PRGRM_CNTR_START. 2659 */ 2660 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2661 if (pipe_id == 0) 2662 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2663 PFP_PIPE0_RESET, 1); 2664 else 2665 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2666 PFP_PIPE1_RESET, 1); 2667 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2668 2669 /* Clear pfp pipe0 reset bit. */ 2670 if (pipe_id == 0) 2671 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2672 PFP_PIPE0_RESET, 0); 2673 else 2674 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2675 PFP_PIPE1_RESET, 0); 2676 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2677 2678 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2679 lower_32_bits(addr2)); 2680 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2681 upper_32_bits(addr2)); 2682 } 2683 soc21_grbm_select(adev, 0, 0, 0, 0); 2684 mutex_unlock(&adev->srbm_mutex); 2685 2686 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2687 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2688 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2689 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2690 2691 /* Invalidate the data caches */ 2692 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2693 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2694 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2695 2696 for (i = 0; i < usec_timeout; i++) { 2697 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2698 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2699 INVALIDATE_DCACHE_COMPLETE)) 2700 break; 2701 udelay(1); 2702 } 2703 2704 if (i >= usec_timeout) { 2705 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2706 return -EINVAL; 2707 } 2708 2709 return 0; 2710 } 2711 2712 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2713 { 2714 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2715 uint32_t tmp; 2716 unsigned i, pipe_id; 2717 const struct gfx_firmware_header_v2_0 *me_hdr; 2718 2719 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2720 adev->gfx.me_fw->data; 2721 2722 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2723 lower_32_bits(addr)); 2724 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2725 upper_32_bits(addr)); 2726 2727 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2728 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2729 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2730 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2731 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2732 2733 /* 2734 * Programming any of the CP_ME_IC_BASE registers 2735 * forces invalidation of the ME L1 I$. Wait for the 2736 * invalidation complete 2737 */ 2738 for (i = 0; i < usec_timeout; i++) { 2739 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2740 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2741 INVALIDATE_CACHE_COMPLETE)) 2742 break; 2743 udelay(1); 2744 } 2745 2746 if (i >= usec_timeout) { 2747 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2748 return -EINVAL; 2749 } 2750 2751 /* Prime the instruction caches */ 2752 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2753 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2754 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2755 2756 /* Waiting for instruction cache primed*/ 2757 for (i = 0; i < usec_timeout; i++) { 2758 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2759 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2760 ICACHE_PRIMED)) 2761 break; 2762 udelay(1); 2763 } 2764 2765 if (i >= usec_timeout) { 2766 dev_err(adev->dev, "failed to prime instruction cache\n"); 2767 return -EINVAL; 2768 } 2769 2770 mutex_lock(&adev->srbm_mutex); 2771 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2772 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2773 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2774 (me_hdr->ucode_start_addr_hi << 30) | 2775 (me_hdr->ucode_start_addr_lo >> 2) ); 2776 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2777 me_hdr->ucode_start_addr_hi>>2); 2778 2779 /* 2780 * Program CP_ME_CNTL to reset given PIPE to take 2781 * effect of CP_PFP_PRGRM_CNTR_START. 2782 */ 2783 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2784 if (pipe_id == 0) 2785 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2786 ME_PIPE0_RESET, 1); 2787 else 2788 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2789 ME_PIPE1_RESET, 1); 2790 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2791 2792 /* Clear pfp pipe0 reset bit. */ 2793 if (pipe_id == 0) 2794 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2795 ME_PIPE0_RESET, 0); 2796 else 2797 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2798 ME_PIPE1_RESET, 0); 2799 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2800 2801 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2802 lower_32_bits(addr2)); 2803 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2804 upper_32_bits(addr2)); 2805 } 2806 soc21_grbm_select(adev, 0, 0, 0, 0); 2807 mutex_unlock(&adev->srbm_mutex); 2808 2809 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2810 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2811 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2812 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2813 2814 /* Invalidate the data caches */ 2815 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2816 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2817 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2818 2819 for (i = 0; i < usec_timeout; i++) { 2820 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2821 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2822 INVALIDATE_DCACHE_COMPLETE)) 2823 break; 2824 udelay(1); 2825 } 2826 2827 if (i >= usec_timeout) { 2828 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2829 return -EINVAL; 2830 } 2831 2832 return 0; 2833 } 2834 2835 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2836 { 2837 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2838 uint32_t tmp; 2839 unsigned i; 2840 const struct gfx_firmware_header_v2_0 *mec_hdr; 2841 2842 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2843 adev->gfx.mec_fw->data; 2844 2845 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2846 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2847 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2848 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2849 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2850 2851 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2852 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2853 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2854 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2855 2856 mutex_lock(&adev->srbm_mutex); 2857 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2858 soc21_grbm_select(adev, 1, i, 0, 0); 2859 2860 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2861 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2862 upper_32_bits(addr2)); 2863 2864 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2865 mec_hdr->ucode_start_addr_lo >> 2 | 2866 mec_hdr->ucode_start_addr_hi << 30); 2867 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2868 mec_hdr->ucode_start_addr_hi >> 2); 2869 2870 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2871 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2872 upper_32_bits(addr)); 2873 } 2874 mutex_unlock(&adev->srbm_mutex); 2875 soc21_grbm_select(adev, 0, 0, 0, 0); 2876 2877 /* Trigger an invalidation of the L1 instruction caches */ 2878 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2879 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2880 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2881 2882 /* Wait for invalidation complete */ 2883 for (i = 0; i < usec_timeout; i++) { 2884 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2885 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2886 INVALIDATE_DCACHE_COMPLETE)) 2887 break; 2888 udelay(1); 2889 } 2890 2891 if (i >= usec_timeout) { 2892 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2893 return -EINVAL; 2894 } 2895 2896 /* Trigger an invalidation of the L1 instruction caches */ 2897 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2898 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2899 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2900 2901 /* Wait for invalidation complete */ 2902 for (i = 0; i < usec_timeout; i++) { 2903 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2904 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2905 INVALIDATE_CACHE_COMPLETE)) 2906 break; 2907 udelay(1); 2908 } 2909 2910 if (i >= usec_timeout) { 2911 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2912 return -EINVAL; 2913 } 2914 2915 return 0; 2916 } 2917 2918 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2919 { 2920 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2921 const struct gfx_firmware_header_v2_0 *me_hdr; 2922 const struct gfx_firmware_header_v2_0 *mec_hdr; 2923 uint32_t pipe_id, tmp; 2924 2925 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2926 adev->gfx.mec_fw->data; 2927 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2928 adev->gfx.me_fw->data; 2929 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2930 adev->gfx.pfp_fw->data; 2931 2932 /* config pfp program start addr */ 2933 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2934 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2935 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2936 (pfp_hdr->ucode_start_addr_hi << 30) | 2937 (pfp_hdr->ucode_start_addr_lo >> 2)); 2938 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2939 pfp_hdr->ucode_start_addr_hi >> 2); 2940 } 2941 soc21_grbm_select(adev, 0, 0, 0, 0); 2942 2943 /* reset pfp pipe */ 2944 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2945 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2946 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2947 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2948 2949 /* clear pfp pipe reset */ 2950 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2951 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2952 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2953 2954 /* config me program start addr */ 2955 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2956 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2957 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2958 (me_hdr->ucode_start_addr_hi << 30) | 2959 (me_hdr->ucode_start_addr_lo >> 2) ); 2960 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2961 me_hdr->ucode_start_addr_hi>>2); 2962 } 2963 soc21_grbm_select(adev, 0, 0, 0, 0); 2964 2965 /* reset me pipe */ 2966 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2967 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2968 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2969 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2970 2971 /* clear me pipe reset */ 2972 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2973 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2974 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2975 2976 /* config mec program start addr */ 2977 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2978 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2979 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2980 mec_hdr->ucode_start_addr_lo >> 2 | 2981 mec_hdr->ucode_start_addr_hi << 30); 2982 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2983 mec_hdr->ucode_start_addr_hi >> 2); 2984 } 2985 soc21_grbm_select(adev, 0, 0, 0, 0); 2986 2987 /* reset mec pipe */ 2988 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2989 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2990 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2991 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2992 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2993 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2994 2995 /* clear mec pipe reset */ 2996 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2997 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2998 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2999 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 3000 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3001 } 3002 3003 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 3004 { 3005 uint32_t cp_status; 3006 uint32_t bootload_status; 3007 int i, r; 3008 uint64_t addr, addr2; 3009 3010 for (i = 0; i < adev->usec_timeout; i++) { 3011 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 3012 3013 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 3014 IP_VERSION(11, 0, 1) || 3015 amdgpu_ip_version(adev, GC_HWIP, 0) == 3016 IP_VERSION(11, 0, 4) || 3017 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 3018 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 3019 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 3020 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) 3021 bootload_status = RREG32_SOC15(GC, 0, 3022 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 3023 else 3024 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 3025 3026 if ((cp_status == 0) && 3027 (REG_GET_FIELD(bootload_status, 3028 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 3029 break; 3030 } 3031 udelay(1); 3032 } 3033 3034 if (i >= adev->usec_timeout) { 3035 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 3036 return -ETIMEDOUT; 3037 } 3038 3039 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3040 if (adev->gfx.rs64_enable) { 3041 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3042 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 3043 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3044 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 3045 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 3046 if (r) 3047 return r; 3048 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3049 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 3050 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3051 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 3052 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 3053 if (r) 3054 return r; 3055 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3056 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 3057 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3058 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 3059 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 3060 if (r) 3061 return r; 3062 } else { 3063 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3064 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 3065 r = gfx_v11_0_config_me_cache(adev, addr); 3066 if (r) 3067 return r; 3068 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3069 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 3070 r = gfx_v11_0_config_pfp_cache(adev, addr); 3071 if (r) 3072 return r; 3073 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3074 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 3075 r = gfx_v11_0_config_mec_cache(adev, addr); 3076 if (r) 3077 return r; 3078 } 3079 } 3080 3081 return 0; 3082 } 3083 3084 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3085 { 3086 int i; 3087 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3088 3089 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3091 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3092 3093 for (i = 0; i < adev->usec_timeout; i++) { 3094 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3095 break; 3096 udelay(1); 3097 } 3098 3099 if (i >= adev->usec_timeout) 3100 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3101 3102 return 0; 3103 } 3104 3105 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3106 { 3107 int r; 3108 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3109 const __le32 *fw_data; 3110 unsigned i, fw_size; 3111 3112 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3113 adev->gfx.pfp_fw->data; 3114 3115 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3116 3117 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3118 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3119 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3120 3121 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3122 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3123 &adev->gfx.pfp.pfp_fw_obj, 3124 &adev->gfx.pfp.pfp_fw_gpu_addr, 3125 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3126 if (r) { 3127 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3128 gfx_v11_0_pfp_fini(adev); 3129 return r; 3130 } 3131 3132 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3133 3134 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3135 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3136 3137 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3138 3139 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3140 3141 for (i = 0; i < pfp_hdr->jt_size; i++) 3142 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3143 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3144 3145 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3146 3147 return 0; 3148 } 3149 3150 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3151 { 3152 int r; 3153 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3154 const __le32 *fw_ucode, *fw_data; 3155 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3156 uint32_t tmp; 3157 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3158 3159 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3160 adev->gfx.pfp_fw->data; 3161 3162 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3163 3164 /* instruction */ 3165 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3166 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3167 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3168 /* data */ 3169 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3170 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3171 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3172 3173 /* 64kb align */ 3174 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3175 64 * 1024, 3176 AMDGPU_GEM_DOMAIN_VRAM | 3177 AMDGPU_GEM_DOMAIN_GTT, 3178 &adev->gfx.pfp.pfp_fw_obj, 3179 &adev->gfx.pfp.pfp_fw_gpu_addr, 3180 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3181 if (r) { 3182 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3183 gfx_v11_0_pfp_fini(adev); 3184 return r; 3185 } 3186 3187 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3188 64 * 1024, 3189 AMDGPU_GEM_DOMAIN_VRAM | 3190 AMDGPU_GEM_DOMAIN_GTT, 3191 &adev->gfx.pfp.pfp_fw_data_obj, 3192 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3193 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3194 if (r) { 3195 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3196 gfx_v11_0_pfp_fini(adev); 3197 return r; 3198 } 3199 3200 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3201 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3202 3203 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3204 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3205 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3206 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3207 3208 if (amdgpu_emu_mode == 1) 3209 adev->hdp.funcs->flush_hdp(adev, NULL); 3210 3211 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3212 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3213 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3214 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3215 3216 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3217 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3218 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3219 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3220 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3221 3222 /* 3223 * Programming any of the CP_PFP_IC_BASE registers 3224 * forces invalidation of the ME L1 I$. Wait for the 3225 * invalidation complete 3226 */ 3227 for (i = 0; i < usec_timeout; i++) { 3228 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3229 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3230 INVALIDATE_CACHE_COMPLETE)) 3231 break; 3232 udelay(1); 3233 } 3234 3235 if (i >= usec_timeout) { 3236 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3237 return -EINVAL; 3238 } 3239 3240 /* Prime the L1 instruction caches */ 3241 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3242 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3243 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3244 /* Waiting for cache primed*/ 3245 for (i = 0; i < usec_timeout; i++) { 3246 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3247 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3248 ICACHE_PRIMED)) 3249 break; 3250 udelay(1); 3251 } 3252 3253 if (i >= usec_timeout) { 3254 dev_err(adev->dev, "failed to prime instruction cache\n"); 3255 return -EINVAL; 3256 } 3257 3258 mutex_lock(&adev->srbm_mutex); 3259 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3260 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3261 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3262 (pfp_hdr->ucode_start_addr_hi << 30) | 3263 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3264 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3265 pfp_hdr->ucode_start_addr_hi>>2); 3266 3267 /* 3268 * Program CP_ME_CNTL to reset given PIPE to take 3269 * effect of CP_PFP_PRGRM_CNTR_START. 3270 */ 3271 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3272 if (pipe_id == 0) 3273 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3274 PFP_PIPE0_RESET, 1); 3275 else 3276 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3277 PFP_PIPE1_RESET, 1); 3278 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3279 3280 /* Clear pfp pipe0 reset bit. */ 3281 if (pipe_id == 0) 3282 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3283 PFP_PIPE0_RESET, 0); 3284 else 3285 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3286 PFP_PIPE1_RESET, 0); 3287 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3288 3289 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3290 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3291 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3292 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3293 } 3294 soc21_grbm_select(adev, 0, 0, 0, 0); 3295 mutex_unlock(&adev->srbm_mutex); 3296 3297 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3298 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3299 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3300 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3301 3302 /* Invalidate the data caches */ 3303 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3304 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3305 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3306 3307 for (i = 0; i < usec_timeout; i++) { 3308 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3309 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3310 INVALIDATE_DCACHE_COMPLETE)) 3311 break; 3312 udelay(1); 3313 } 3314 3315 if (i >= usec_timeout) { 3316 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3317 return -EINVAL; 3318 } 3319 3320 return 0; 3321 } 3322 3323 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3324 { 3325 int r; 3326 const struct gfx_firmware_header_v1_0 *me_hdr; 3327 const __le32 *fw_data; 3328 unsigned i, fw_size; 3329 3330 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3331 adev->gfx.me_fw->data; 3332 3333 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3334 3335 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3336 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3337 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3338 3339 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3340 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3341 &adev->gfx.me.me_fw_obj, 3342 &adev->gfx.me.me_fw_gpu_addr, 3343 (void **)&adev->gfx.me.me_fw_ptr); 3344 if (r) { 3345 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3346 gfx_v11_0_me_fini(adev); 3347 return r; 3348 } 3349 3350 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3351 3352 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3353 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3354 3355 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3356 3357 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3358 3359 for (i = 0; i < me_hdr->jt_size; i++) 3360 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3361 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3362 3363 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3364 3365 return 0; 3366 } 3367 3368 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3369 { 3370 int r; 3371 const struct gfx_firmware_header_v2_0 *me_hdr; 3372 const __le32 *fw_ucode, *fw_data; 3373 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3374 uint32_t tmp; 3375 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3376 3377 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3378 adev->gfx.me_fw->data; 3379 3380 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3381 3382 /* instruction */ 3383 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3384 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3385 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3386 /* data */ 3387 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3388 le32_to_cpu(me_hdr->data_offset_bytes)); 3389 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3390 3391 /* 64kb align*/ 3392 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3393 64 * 1024, 3394 AMDGPU_GEM_DOMAIN_VRAM | 3395 AMDGPU_GEM_DOMAIN_GTT, 3396 &adev->gfx.me.me_fw_obj, 3397 &adev->gfx.me.me_fw_gpu_addr, 3398 (void **)&adev->gfx.me.me_fw_ptr); 3399 if (r) { 3400 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3401 gfx_v11_0_me_fini(adev); 3402 return r; 3403 } 3404 3405 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3406 64 * 1024, 3407 AMDGPU_GEM_DOMAIN_VRAM | 3408 AMDGPU_GEM_DOMAIN_GTT, 3409 &adev->gfx.me.me_fw_data_obj, 3410 &adev->gfx.me.me_fw_data_gpu_addr, 3411 (void **)&adev->gfx.me.me_fw_data_ptr); 3412 if (r) { 3413 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3414 gfx_v11_0_pfp_fini(adev); 3415 return r; 3416 } 3417 3418 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3419 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3420 3421 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3422 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3423 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3424 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3425 3426 if (amdgpu_emu_mode == 1) 3427 adev->hdp.funcs->flush_hdp(adev, NULL); 3428 3429 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3430 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3431 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3432 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3433 3434 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3435 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3436 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3437 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3438 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3439 3440 /* 3441 * Programming any of the CP_ME_IC_BASE registers 3442 * forces invalidation of the ME L1 I$. Wait for the 3443 * invalidation complete 3444 */ 3445 for (i = 0; i < usec_timeout; i++) { 3446 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3447 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3448 INVALIDATE_CACHE_COMPLETE)) 3449 break; 3450 udelay(1); 3451 } 3452 3453 if (i >= usec_timeout) { 3454 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3455 return -EINVAL; 3456 } 3457 3458 /* Prime the instruction caches */ 3459 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3460 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3461 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3462 3463 /* Waiting for instruction cache primed*/ 3464 for (i = 0; i < usec_timeout; i++) { 3465 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3466 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3467 ICACHE_PRIMED)) 3468 break; 3469 udelay(1); 3470 } 3471 3472 if (i >= usec_timeout) { 3473 dev_err(adev->dev, "failed to prime instruction cache\n"); 3474 return -EINVAL; 3475 } 3476 3477 mutex_lock(&adev->srbm_mutex); 3478 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3479 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3480 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3481 (me_hdr->ucode_start_addr_hi << 30) | 3482 (me_hdr->ucode_start_addr_lo >> 2) ); 3483 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3484 me_hdr->ucode_start_addr_hi>>2); 3485 3486 /* 3487 * Program CP_ME_CNTL to reset given PIPE to take 3488 * effect of CP_PFP_PRGRM_CNTR_START. 3489 */ 3490 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3491 if (pipe_id == 0) 3492 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3493 ME_PIPE0_RESET, 1); 3494 else 3495 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3496 ME_PIPE1_RESET, 1); 3497 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3498 3499 /* Clear pfp pipe0 reset bit. */ 3500 if (pipe_id == 0) 3501 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3502 ME_PIPE0_RESET, 0); 3503 else 3504 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3505 ME_PIPE1_RESET, 0); 3506 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3507 3508 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3509 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3510 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3511 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3512 } 3513 soc21_grbm_select(adev, 0, 0, 0, 0); 3514 mutex_unlock(&adev->srbm_mutex); 3515 3516 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3517 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3518 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3519 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3520 3521 /* Invalidate the data caches */ 3522 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3523 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3524 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3525 3526 for (i = 0; i < usec_timeout; i++) { 3527 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3528 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3529 INVALIDATE_DCACHE_COMPLETE)) 3530 break; 3531 udelay(1); 3532 } 3533 3534 if (i >= usec_timeout) { 3535 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3536 return -EINVAL; 3537 } 3538 3539 return 0; 3540 } 3541 3542 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3543 { 3544 int r; 3545 3546 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3547 return -EINVAL; 3548 3549 gfx_v11_0_cp_gfx_enable(adev, false); 3550 3551 if (adev->gfx.rs64_enable) 3552 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3553 else 3554 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3555 if (r) { 3556 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3557 return r; 3558 } 3559 3560 if (adev->gfx.rs64_enable) 3561 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3562 else 3563 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3564 if (r) { 3565 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3566 return r; 3567 } 3568 3569 return 0; 3570 } 3571 3572 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3573 { 3574 struct amdgpu_ring *ring; 3575 const struct cs_section_def *sect = NULL; 3576 const struct cs_extent_def *ext = NULL; 3577 int r, i; 3578 int ctx_reg_offset; 3579 3580 /* init the CP */ 3581 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3582 adev->gfx.config.max_hw_contexts - 1); 3583 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3584 3585 if (!amdgpu_async_gfx_ring) 3586 gfx_v11_0_cp_gfx_enable(adev, true); 3587 3588 ring = &adev->gfx.gfx_ring[0]; 3589 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3590 if (r) { 3591 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3592 return r; 3593 } 3594 3595 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3596 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3597 3598 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3599 amdgpu_ring_write(ring, 0x80000000); 3600 amdgpu_ring_write(ring, 0x80000000); 3601 3602 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3603 for (ext = sect->section; ext->extent != NULL; ++ext) { 3604 if (sect->id == SECT_CONTEXT) { 3605 amdgpu_ring_write(ring, 3606 PACKET3(PACKET3_SET_CONTEXT_REG, 3607 ext->reg_count)); 3608 amdgpu_ring_write(ring, ext->reg_index - 3609 PACKET3_SET_CONTEXT_REG_START); 3610 for (i = 0; i < ext->reg_count; i++) 3611 amdgpu_ring_write(ring, ext->extent[i]); 3612 } 3613 } 3614 } 3615 3616 ctx_reg_offset = 3617 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3618 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3619 amdgpu_ring_write(ring, ctx_reg_offset); 3620 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3621 3622 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3623 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3624 3625 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3626 amdgpu_ring_write(ring, 0); 3627 3628 amdgpu_ring_commit(ring); 3629 3630 /* submit cs packet to copy state 0 to next available state */ 3631 if (adev->gfx.num_gfx_rings > 1) { 3632 /* maximum supported gfx ring is 2 */ 3633 ring = &adev->gfx.gfx_ring[1]; 3634 r = amdgpu_ring_alloc(ring, 2); 3635 if (r) { 3636 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3637 return r; 3638 } 3639 3640 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3641 amdgpu_ring_write(ring, 0); 3642 3643 amdgpu_ring_commit(ring); 3644 } 3645 return 0; 3646 } 3647 3648 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3649 CP_PIPE_ID pipe) 3650 { 3651 u32 tmp; 3652 3653 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3654 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3655 3656 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3657 } 3658 3659 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3660 struct amdgpu_ring *ring) 3661 { 3662 u32 tmp; 3663 3664 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3665 if (ring->use_doorbell) { 3666 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3667 DOORBELL_OFFSET, ring->doorbell_index); 3668 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3669 DOORBELL_EN, 1); 3670 } else { 3671 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3672 DOORBELL_EN, 0); 3673 } 3674 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3675 3676 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3677 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3678 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3679 3680 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3681 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3682 } 3683 3684 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3685 { 3686 struct amdgpu_ring *ring; 3687 u32 tmp; 3688 u32 rb_bufsz; 3689 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3690 3691 /* Set the write pointer delay */ 3692 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3693 3694 /* set the RB to use vmid 0 */ 3695 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3696 3697 /* Init gfx ring 0 for pipe 0 */ 3698 mutex_lock(&adev->srbm_mutex); 3699 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3700 3701 /* Set ring buffer size */ 3702 ring = &adev->gfx.gfx_ring[0]; 3703 rb_bufsz = order_base_2(ring->ring_size / 8); 3704 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3705 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3706 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3707 3708 /* Initialize the ring buffer's write pointers */ 3709 ring->wptr = 0; 3710 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3711 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3712 3713 /* set the wb address whether it's enabled or not */ 3714 rptr_addr = ring->rptr_gpu_addr; 3715 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3716 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3717 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3718 3719 wptr_gpu_addr = ring->wptr_gpu_addr; 3720 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3721 lower_32_bits(wptr_gpu_addr)); 3722 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3723 upper_32_bits(wptr_gpu_addr)); 3724 3725 mdelay(1); 3726 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3727 3728 rb_addr = ring->gpu_addr >> 8; 3729 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3730 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3731 3732 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3733 3734 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3735 mutex_unlock(&adev->srbm_mutex); 3736 3737 /* Init gfx ring 1 for pipe 1 */ 3738 if (adev->gfx.num_gfx_rings > 1) { 3739 mutex_lock(&adev->srbm_mutex); 3740 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3741 /* maximum supported gfx ring is 2 */ 3742 ring = &adev->gfx.gfx_ring[1]; 3743 rb_bufsz = order_base_2(ring->ring_size / 8); 3744 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3745 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3746 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3747 /* Initialize the ring buffer's write pointers */ 3748 ring->wptr = 0; 3749 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3750 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3751 /* Set the wb address whether it's enabled or not */ 3752 rptr_addr = ring->rptr_gpu_addr; 3753 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3754 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3755 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3756 wptr_gpu_addr = ring->wptr_gpu_addr; 3757 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3758 lower_32_bits(wptr_gpu_addr)); 3759 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3760 upper_32_bits(wptr_gpu_addr)); 3761 3762 mdelay(1); 3763 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3764 3765 rb_addr = ring->gpu_addr >> 8; 3766 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3767 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3768 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3769 3770 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3771 mutex_unlock(&adev->srbm_mutex); 3772 } 3773 /* Switch to pipe 0 */ 3774 mutex_lock(&adev->srbm_mutex); 3775 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3776 mutex_unlock(&adev->srbm_mutex); 3777 3778 /* start the ring */ 3779 gfx_v11_0_cp_gfx_start(adev); 3780 3781 return 0; 3782 } 3783 3784 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3785 { 3786 u32 data; 3787 3788 if (adev->gfx.rs64_enable) { 3789 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3791 enable ? 0 : 1); 3792 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3793 enable ? 0 : 1); 3794 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3795 enable ? 0 : 1); 3796 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3797 enable ? 0 : 1); 3798 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3799 enable ? 0 : 1); 3800 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3801 enable ? 1 : 0); 3802 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3803 enable ? 1 : 0); 3804 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3805 enable ? 1 : 0); 3806 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3807 enable ? 1 : 0); 3808 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3809 enable ? 0 : 1); 3810 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3811 } else { 3812 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3813 3814 if (enable) { 3815 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3816 if (!adev->enable_mes_kiq) 3817 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3818 MEC_ME2_HALT, 0); 3819 } else { 3820 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3821 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3822 } 3823 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3824 } 3825 3826 udelay(50); 3827 } 3828 3829 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3830 { 3831 const struct gfx_firmware_header_v1_0 *mec_hdr; 3832 const __le32 *fw_data; 3833 unsigned i, fw_size; 3834 u32 *fw = NULL; 3835 int r; 3836 3837 if (!adev->gfx.mec_fw) 3838 return -EINVAL; 3839 3840 gfx_v11_0_cp_compute_enable(adev, false); 3841 3842 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3843 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3844 3845 fw_data = (const __le32 *) 3846 (adev->gfx.mec_fw->data + 3847 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3848 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3849 3850 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3851 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3852 &adev->gfx.mec.mec_fw_obj, 3853 &adev->gfx.mec.mec_fw_gpu_addr, 3854 (void **)&fw); 3855 if (r) { 3856 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3857 gfx_v11_0_mec_fini(adev); 3858 return r; 3859 } 3860 3861 memcpy(fw, fw_data, fw_size); 3862 3863 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3864 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3865 3866 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3867 3868 /* MEC1 */ 3869 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3870 3871 for (i = 0; i < mec_hdr->jt_size; i++) 3872 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3873 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3874 3875 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3876 3877 return 0; 3878 } 3879 3880 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3881 { 3882 const struct gfx_firmware_header_v2_0 *mec_hdr; 3883 const __le32 *fw_ucode, *fw_data; 3884 u32 tmp, fw_ucode_size, fw_data_size; 3885 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3886 u32 *fw_ucode_ptr, *fw_data_ptr; 3887 int r; 3888 3889 if (!adev->gfx.mec_fw) 3890 return -EINVAL; 3891 3892 gfx_v11_0_cp_compute_enable(adev, false); 3893 3894 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3895 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3896 3897 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3898 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3899 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3900 3901 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3902 le32_to_cpu(mec_hdr->data_offset_bytes)); 3903 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3904 3905 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3906 64 * 1024, 3907 AMDGPU_GEM_DOMAIN_VRAM | 3908 AMDGPU_GEM_DOMAIN_GTT, 3909 &adev->gfx.mec.mec_fw_obj, 3910 &adev->gfx.mec.mec_fw_gpu_addr, 3911 (void **)&fw_ucode_ptr); 3912 if (r) { 3913 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3914 gfx_v11_0_mec_fini(adev); 3915 return r; 3916 } 3917 3918 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3919 64 * 1024, 3920 AMDGPU_GEM_DOMAIN_VRAM | 3921 AMDGPU_GEM_DOMAIN_GTT, 3922 &adev->gfx.mec.mec_fw_data_obj, 3923 &adev->gfx.mec.mec_fw_data_gpu_addr, 3924 (void **)&fw_data_ptr); 3925 if (r) { 3926 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3927 gfx_v11_0_mec_fini(adev); 3928 return r; 3929 } 3930 3931 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3932 memcpy(fw_data_ptr, fw_data, fw_data_size); 3933 3934 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3935 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3936 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3937 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3938 3939 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3940 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3941 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3942 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3943 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3944 3945 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3946 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3947 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3948 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3949 3950 mutex_lock(&adev->srbm_mutex); 3951 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3952 soc21_grbm_select(adev, 1, i, 0, 0); 3953 3954 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3955 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3956 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3957 3958 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3959 mec_hdr->ucode_start_addr_lo >> 2 | 3960 mec_hdr->ucode_start_addr_hi << 30); 3961 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3962 mec_hdr->ucode_start_addr_hi >> 2); 3963 3964 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3965 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3966 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3967 } 3968 mutex_unlock(&adev->srbm_mutex); 3969 soc21_grbm_select(adev, 0, 0, 0, 0); 3970 3971 /* Trigger an invalidation of the L1 instruction caches */ 3972 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3973 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3974 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3975 3976 /* Wait for invalidation complete */ 3977 for (i = 0; i < usec_timeout; i++) { 3978 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3979 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3980 INVALIDATE_DCACHE_COMPLETE)) 3981 break; 3982 udelay(1); 3983 } 3984 3985 if (i >= usec_timeout) { 3986 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3987 return -EINVAL; 3988 } 3989 3990 /* Trigger an invalidation of the L1 instruction caches */ 3991 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3992 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3993 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3994 3995 /* Wait for invalidation complete */ 3996 for (i = 0; i < usec_timeout; i++) { 3997 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3998 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3999 INVALIDATE_CACHE_COMPLETE)) 4000 break; 4001 udelay(1); 4002 } 4003 4004 if (i >= usec_timeout) { 4005 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4006 return -EINVAL; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 4013 { 4014 uint32_t tmp; 4015 struct amdgpu_device *adev = ring->adev; 4016 4017 /* tell RLC which is KIQ queue */ 4018 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4019 tmp &= 0xffffff00; 4020 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4021 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 4022 } 4023 4024 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 4025 { 4026 /* set graphics engine doorbell range */ 4027 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 4028 (adev->doorbell_index.gfx_ring0 * 2) << 2); 4029 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 4030 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 4031 4032 /* set compute engine doorbell range */ 4033 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4034 (adev->doorbell_index.kiq * 2) << 2); 4035 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4036 (adev->doorbell_index.userqueue_end * 2) << 2); 4037 } 4038 4039 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 4040 struct v11_gfx_mqd *mqd, 4041 struct amdgpu_mqd_prop *prop) 4042 { 4043 bool priority = 0; 4044 u32 tmp; 4045 4046 /* set up default queue priority level 4047 * 0x0 = low priority, 0x1 = high priority 4048 */ 4049 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 4050 priority = 1; 4051 4052 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 4053 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 4054 mqd->cp_gfx_hqd_queue_priority = tmp; 4055 } 4056 4057 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 4058 struct amdgpu_mqd_prop *prop) 4059 { 4060 struct v11_gfx_mqd *mqd = m; 4061 uint64_t hqd_gpu_addr, wb_gpu_addr; 4062 uint32_t tmp; 4063 uint32_t rb_bufsz; 4064 4065 /* set up gfx hqd wptr */ 4066 mqd->cp_gfx_hqd_wptr = 0; 4067 mqd->cp_gfx_hqd_wptr_hi = 0; 4068 4069 /* set the pointer to the MQD */ 4070 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 4071 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4072 4073 /* set up mqd control */ 4074 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4075 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4076 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4077 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4078 mqd->cp_gfx_mqd_control = tmp; 4079 4080 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4081 tmp = regCP_GFX_HQD_VMID_DEFAULT; 4082 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4083 mqd->cp_gfx_hqd_vmid = 0; 4084 4085 /* set up gfx queue priority */ 4086 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4087 4088 /* set up time quantum */ 4089 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4090 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4091 mqd->cp_gfx_hqd_quantum = tmp; 4092 4093 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4094 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4095 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4096 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4097 4098 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4099 wb_gpu_addr = prop->rptr_gpu_addr; 4100 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4101 mqd->cp_gfx_hqd_rptr_addr_hi = 4102 upper_32_bits(wb_gpu_addr) & 0xffff; 4103 4104 /* set up rb_wptr_poll addr */ 4105 wb_gpu_addr = prop->wptr_gpu_addr; 4106 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4107 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4108 4109 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4110 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4111 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4112 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4113 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4114 #ifdef __BIG_ENDIAN 4115 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4116 #endif 4117 mqd->cp_gfx_hqd_cntl = tmp; 4118 4119 /* set up cp_doorbell_control */ 4120 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4121 if (prop->use_doorbell) { 4122 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4123 DOORBELL_OFFSET, prop->doorbell_index); 4124 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4125 DOORBELL_EN, 1); 4126 } else 4127 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4128 DOORBELL_EN, 0); 4129 mqd->cp_rb_doorbell_control = tmp; 4130 4131 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4132 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4133 4134 /* active the queue */ 4135 mqd->cp_gfx_hqd_active = 1; 4136 4137 /* set gfx UQ items */ 4138 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 4139 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 4140 mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr); 4141 mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr); 4142 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 4143 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 4144 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4145 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4146 4147 return 0; 4148 } 4149 4150 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 4151 { 4152 struct amdgpu_device *adev = ring->adev; 4153 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4154 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4155 4156 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4157 memset((void *)mqd, 0, sizeof(*mqd)); 4158 mutex_lock(&adev->srbm_mutex); 4159 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4160 amdgpu_ring_init_mqd(ring); 4161 soc21_grbm_select(adev, 0, 0, 0, 0); 4162 mutex_unlock(&adev->srbm_mutex); 4163 if (adev->gfx.me.mqd_backup[mqd_idx]) 4164 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4165 } else { 4166 /* restore mqd with the backup copy */ 4167 if (adev->gfx.me.mqd_backup[mqd_idx]) 4168 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4169 /* reset the ring */ 4170 ring->wptr = 0; 4171 *ring->wptr_cpu_addr = 0; 4172 amdgpu_ring_clear_ring(ring); 4173 } 4174 4175 return 0; 4176 } 4177 4178 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4179 { 4180 int r, i; 4181 4182 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4183 r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 4184 if (r) 4185 return r; 4186 } 4187 4188 r = amdgpu_gfx_enable_kgq(adev, 0); 4189 if (r) 4190 return r; 4191 4192 return gfx_v11_0_cp_gfx_start(adev); 4193 } 4194 4195 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4196 struct amdgpu_mqd_prop *prop) 4197 { 4198 struct v11_compute_mqd *mqd = m; 4199 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4200 uint32_t tmp; 4201 4202 mqd->header = 0xC0310800; 4203 mqd->compute_pipelinestat_enable = 0x00000001; 4204 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4205 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4206 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4207 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4208 mqd->compute_misc_reserved = 0x00000007; 4209 4210 eop_base_addr = prop->eop_gpu_addr >> 8; 4211 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4212 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4213 4214 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4215 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4216 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4217 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4218 4219 mqd->cp_hqd_eop_control = tmp; 4220 4221 /* enable doorbell? */ 4222 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4223 4224 if (prop->use_doorbell) { 4225 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4226 DOORBELL_OFFSET, prop->doorbell_index); 4227 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4228 DOORBELL_EN, 1); 4229 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4230 DOORBELL_SOURCE, 0); 4231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4232 DOORBELL_HIT, 0); 4233 } else { 4234 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4235 DOORBELL_EN, 0); 4236 } 4237 4238 mqd->cp_hqd_pq_doorbell_control = tmp; 4239 4240 /* disable the queue if it's active */ 4241 mqd->cp_hqd_dequeue_request = 0; 4242 mqd->cp_hqd_pq_rptr = 0; 4243 mqd->cp_hqd_pq_wptr_lo = 0; 4244 mqd->cp_hqd_pq_wptr_hi = 0; 4245 4246 /* set the pointer to the MQD */ 4247 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4248 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4249 4250 /* set MQD vmid to 0 */ 4251 tmp = regCP_MQD_CONTROL_DEFAULT; 4252 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4253 mqd->cp_mqd_control = tmp; 4254 4255 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4256 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4257 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4258 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4259 4260 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4261 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4262 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4263 (order_base_2(prop->queue_size / 4) - 1)); 4264 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4265 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4266 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4267 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4268 prop->allow_tunneling); 4269 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4270 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4271 mqd->cp_hqd_pq_control = tmp; 4272 4273 /* set the wb address whether it's enabled or not */ 4274 wb_gpu_addr = prop->rptr_gpu_addr; 4275 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4276 mqd->cp_hqd_pq_rptr_report_addr_hi = 4277 upper_32_bits(wb_gpu_addr) & 0xffff; 4278 4279 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4280 wb_gpu_addr = prop->wptr_gpu_addr; 4281 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4282 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4283 4284 tmp = 0; 4285 /* enable the doorbell if requested */ 4286 if (prop->use_doorbell) { 4287 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4288 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4289 DOORBELL_OFFSET, prop->doorbell_index); 4290 4291 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4292 DOORBELL_EN, 1); 4293 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4294 DOORBELL_SOURCE, 0); 4295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4296 DOORBELL_HIT, 0); 4297 } 4298 4299 mqd->cp_hqd_pq_doorbell_control = tmp; 4300 4301 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4302 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4303 4304 /* set the vmid for the queue */ 4305 mqd->cp_hqd_vmid = 0; 4306 4307 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4308 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4309 mqd->cp_hqd_persistent_state = tmp; 4310 4311 /* set MIN_IB_AVAIL_SIZE */ 4312 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4313 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4314 mqd->cp_hqd_ib_control = tmp; 4315 4316 /* set static priority for a compute queue/ring */ 4317 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4318 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4319 4320 mqd->cp_hqd_active = prop->hqd_active; 4321 4322 /* set UQ fenceaddress */ 4323 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4324 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4325 4326 return 0; 4327 } 4328 4329 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4330 { 4331 struct amdgpu_device *adev = ring->adev; 4332 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4333 int j; 4334 4335 /* inactivate the queue */ 4336 if (amdgpu_sriov_vf(adev)) 4337 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4338 4339 /* disable wptr polling */ 4340 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4341 4342 /* write the EOP addr */ 4343 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4344 mqd->cp_hqd_eop_base_addr_lo); 4345 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4346 mqd->cp_hqd_eop_base_addr_hi); 4347 4348 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4349 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4350 mqd->cp_hqd_eop_control); 4351 4352 /* enable doorbell? */ 4353 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4354 mqd->cp_hqd_pq_doorbell_control); 4355 4356 /* disable the queue if it's active */ 4357 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4358 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4359 for (j = 0; j < adev->usec_timeout; j++) { 4360 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4361 break; 4362 udelay(1); 4363 } 4364 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4365 mqd->cp_hqd_dequeue_request); 4366 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4367 mqd->cp_hqd_pq_rptr); 4368 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4369 mqd->cp_hqd_pq_wptr_lo); 4370 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4371 mqd->cp_hqd_pq_wptr_hi); 4372 } 4373 4374 /* set the pointer to the MQD */ 4375 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4376 mqd->cp_mqd_base_addr_lo); 4377 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4378 mqd->cp_mqd_base_addr_hi); 4379 4380 /* set MQD vmid to 0 */ 4381 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4382 mqd->cp_mqd_control); 4383 4384 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4385 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4386 mqd->cp_hqd_pq_base_lo); 4387 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4388 mqd->cp_hqd_pq_base_hi); 4389 4390 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4391 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4392 mqd->cp_hqd_pq_control); 4393 4394 /* set the wb address whether it's enabled or not */ 4395 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4396 mqd->cp_hqd_pq_rptr_report_addr_lo); 4397 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4398 mqd->cp_hqd_pq_rptr_report_addr_hi); 4399 4400 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4401 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4402 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4403 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4404 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4405 4406 /* enable the doorbell if requested */ 4407 if (ring->use_doorbell) { 4408 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4409 (adev->doorbell_index.kiq * 2) << 2); 4410 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4411 (adev->doorbell_index.userqueue_end * 2) << 2); 4412 } 4413 4414 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4415 mqd->cp_hqd_pq_doorbell_control); 4416 4417 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4418 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4419 mqd->cp_hqd_pq_wptr_lo); 4420 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4421 mqd->cp_hqd_pq_wptr_hi); 4422 4423 /* set the vmid for the queue */ 4424 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4425 4426 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4427 mqd->cp_hqd_persistent_state); 4428 4429 /* activate the queue */ 4430 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4431 mqd->cp_hqd_active); 4432 4433 if (ring->use_doorbell) 4434 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4435 4436 return 0; 4437 } 4438 4439 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4440 { 4441 struct amdgpu_device *adev = ring->adev; 4442 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4443 4444 gfx_v11_0_kiq_setting(ring); 4445 4446 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4447 /* reset MQD to a clean status */ 4448 if (adev->gfx.kiq[0].mqd_backup) 4449 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4450 4451 /* reset ring buffer */ 4452 ring->wptr = 0; 4453 amdgpu_ring_clear_ring(ring); 4454 4455 mutex_lock(&adev->srbm_mutex); 4456 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4457 gfx_v11_0_kiq_init_register(ring); 4458 soc21_grbm_select(adev, 0, 0, 0, 0); 4459 mutex_unlock(&adev->srbm_mutex); 4460 } else { 4461 memset((void *)mqd, 0, sizeof(*mqd)); 4462 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4463 amdgpu_ring_clear_ring(ring); 4464 mutex_lock(&adev->srbm_mutex); 4465 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4466 amdgpu_ring_init_mqd(ring); 4467 gfx_v11_0_kiq_init_register(ring); 4468 soc21_grbm_select(adev, 0, 0, 0, 0); 4469 mutex_unlock(&adev->srbm_mutex); 4470 4471 if (adev->gfx.kiq[0].mqd_backup) 4472 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4473 } 4474 4475 return 0; 4476 } 4477 4478 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 4479 { 4480 struct amdgpu_device *adev = ring->adev; 4481 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4482 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4483 4484 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4485 memset((void *)mqd, 0, sizeof(*mqd)); 4486 mutex_lock(&adev->srbm_mutex); 4487 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4488 amdgpu_ring_init_mqd(ring); 4489 soc21_grbm_select(adev, 0, 0, 0, 0); 4490 mutex_unlock(&adev->srbm_mutex); 4491 4492 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4493 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4494 } else { 4495 /* restore MQD to a clean status */ 4496 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4497 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4498 /* reset ring buffer */ 4499 ring->wptr = 0; 4500 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4501 amdgpu_ring_clear_ring(ring); 4502 } 4503 4504 return 0; 4505 } 4506 4507 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4508 { 4509 gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 4510 return 0; 4511 } 4512 4513 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4514 { 4515 int i, r; 4516 4517 if (!amdgpu_async_gfx_ring) 4518 gfx_v11_0_cp_compute_enable(adev, true); 4519 4520 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4521 r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 4522 if (r) 4523 return r; 4524 } 4525 4526 return amdgpu_gfx_enable_kcq(adev, 0); 4527 } 4528 4529 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4530 { 4531 int r, i; 4532 struct amdgpu_ring *ring; 4533 4534 if (!(adev->flags & AMD_IS_APU)) 4535 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4536 4537 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4538 /* legacy firmware loading */ 4539 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4540 if (r) 4541 return r; 4542 4543 if (adev->gfx.rs64_enable) 4544 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4545 else 4546 r = gfx_v11_0_cp_compute_load_microcode(adev); 4547 if (r) 4548 return r; 4549 } 4550 4551 gfx_v11_0_cp_set_doorbell_range(adev); 4552 4553 if (amdgpu_async_gfx_ring) { 4554 gfx_v11_0_cp_compute_enable(adev, true); 4555 gfx_v11_0_cp_gfx_enable(adev, true); 4556 } 4557 4558 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4559 r = amdgpu_mes_kiq_hw_init(adev); 4560 else 4561 r = gfx_v11_0_kiq_resume(adev); 4562 if (r) 4563 return r; 4564 4565 r = gfx_v11_0_kcq_resume(adev); 4566 if (r) 4567 return r; 4568 4569 if (!amdgpu_async_gfx_ring) { 4570 r = gfx_v11_0_cp_gfx_resume(adev); 4571 if (r) 4572 return r; 4573 } else { 4574 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4575 if (r) 4576 return r; 4577 } 4578 4579 if (adev->gfx.disable_kq) { 4580 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4581 ring = &adev->gfx.gfx_ring[i]; 4582 /* we don't want to set ring->ready */ 4583 r = amdgpu_ring_test_ring(ring); 4584 if (r) 4585 return r; 4586 } 4587 if (amdgpu_async_gfx_ring) 4588 amdgpu_gfx_disable_kgq(adev, 0); 4589 } else { 4590 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4591 ring = &adev->gfx.gfx_ring[i]; 4592 r = amdgpu_ring_test_helper(ring); 4593 if (r) 4594 return r; 4595 } 4596 } 4597 4598 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4599 ring = &adev->gfx.compute_ring[i]; 4600 r = amdgpu_ring_test_helper(ring); 4601 if (r) 4602 return r; 4603 } 4604 4605 return 0; 4606 } 4607 4608 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4609 { 4610 gfx_v11_0_cp_gfx_enable(adev, enable); 4611 gfx_v11_0_cp_compute_enable(adev, enable); 4612 } 4613 4614 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4615 { 4616 int r; 4617 bool value; 4618 4619 r = adev->gfxhub.funcs->gart_enable(adev); 4620 if (r) 4621 return r; 4622 4623 adev->hdp.funcs->flush_hdp(adev, NULL); 4624 4625 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4626 false : true; 4627 4628 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4629 /* TODO investigate why this and the hdp flush above is needed, 4630 * are we missing a flush somewhere else? */ 4631 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4632 4633 return 0; 4634 } 4635 4636 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4637 { 4638 u32 tmp; 4639 4640 /* select RS64 */ 4641 if (adev->gfx.rs64_enable) { 4642 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4643 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4644 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4645 4646 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4647 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4648 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4649 } 4650 4651 if (amdgpu_emu_mode == 1) 4652 msleep(100); 4653 } 4654 4655 static int get_gb_addr_config(struct amdgpu_device * adev) 4656 { 4657 u32 gb_addr_config; 4658 4659 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4660 if (gb_addr_config == 0) 4661 return -EINVAL; 4662 4663 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4664 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4665 4666 adev->gfx.config.gb_addr_config = gb_addr_config; 4667 4668 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4669 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4670 GB_ADDR_CONFIG, NUM_PIPES); 4671 4672 adev->gfx.config.max_tile_pipes = 4673 adev->gfx.config.gb_addr_config_fields.num_pipes; 4674 4675 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4676 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4677 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4678 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4679 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4680 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4681 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4682 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4683 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4684 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4685 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4686 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4687 4688 return 0; 4689 } 4690 4691 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4692 { 4693 uint32_t data; 4694 4695 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4696 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4697 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4698 4699 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4700 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4701 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4702 } 4703 4704 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4705 { 4706 int r; 4707 struct amdgpu_device *adev = ip_block->adev; 4708 4709 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4710 adev->gfx.cleaner_shader_ptr); 4711 4712 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4713 if (adev->gfx.imu.funcs) { 4714 /* RLC autoload sequence 1: Program rlc ram */ 4715 if (adev->gfx.imu.funcs->program_rlc_ram) 4716 adev->gfx.imu.funcs->program_rlc_ram(adev); 4717 /* rlc autoload firmware */ 4718 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4719 if (r) 4720 return r; 4721 } 4722 } else { 4723 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4724 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4725 if (adev->gfx.imu.funcs->load_microcode) 4726 adev->gfx.imu.funcs->load_microcode(adev); 4727 if (adev->gfx.imu.funcs->setup_imu) 4728 adev->gfx.imu.funcs->setup_imu(adev); 4729 if (adev->gfx.imu.funcs->start_imu) 4730 adev->gfx.imu.funcs->start_imu(adev); 4731 } 4732 4733 /* disable gpa mode in backdoor loading */ 4734 gfx_v11_0_disable_gpa_mode(adev); 4735 } 4736 } 4737 4738 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4739 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4740 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4741 if (r) { 4742 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4743 return r; 4744 } 4745 } 4746 4747 adev->gfx.is_poweron = true; 4748 4749 if(get_gb_addr_config(adev)) 4750 DRM_WARN("Invalid gb_addr_config !\n"); 4751 4752 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4753 adev->gfx.rs64_enable) 4754 gfx_v11_0_config_gfx_rs64(adev); 4755 4756 r = gfx_v11_0_gfxhub_enable(adev); 4757 if (r) 4758 return r; 4759 4760 if (!amdgpu_emu_mode) 4761 gfx_v11_0_init_golden_registers(adev); 4762 4763 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4764 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4765 /** 4766 * For gfx 11, rlc firmware loading relies on smu firmware is 4767 * loaded firstly, so in direct type, it has to load smc ucode 4768 * here before rlc. 4769 */ 4770 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4771 if (r) 4772 return r; 4773 } 4774 4775 gfx_v11_0_constants_init(adev); 4776 4777 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4778 gfx_v11_0_select_cp_fw_arch(adev); 4779 4780 if (adev->nbio.funcs->gc_doorbell_init) 4781 adev->nbio.funcs->gc_doorbell_init(adev); 4782 4783 r = gfx_v11_0_rlc_resume(adev); 4784 if (r) 4785 return r; 4786 4787 /* 4788 * init golden registers and rlc resume may override some registers, 4789 * reconfig them here 4790 */ 4791 gfx_v11_0_tcp_harvest(adev); 4792 4793 r = gfx_v11_0_cp_resume(adev); 4794 if (r) 4795 return r; 4796 4797 /* get IMU version from HW if it's not set */ 4798 if (!adev->gfx.imu_fw_version) 4799 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4800 4801 return r; 4802 } 4803 4804 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 4805 bool enable) 4806 { 4807 if (adev->gfx.disable_kq) { 4808 unsigned int irq_type; 4809 int m, p, r; 4810 4811 for (m = 0; m < adev->gfx.me.num_me; m++) { 4812 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 4813 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4814 if (enable) 4815 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4816 irq_type); 4817 else 4818 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4819 irq_type); 4820 if (r) 4821 return r; 4822 } 4823 } 4824 4825 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 4826 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 4827 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4828 + (m * adev->gfx.mec.num_pipe_per_mec) 4829 + p; 4830 if (enable) 4831 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4832 irq_type); 4833 else 4834 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4835 irq_type); 4836 if (r) 4837 return r; 4838 } 4839 } 4840 } 4841 return 0; 4842 } 4843 4844 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 4845 { 4846 struct amdgpu_device *adev = ip_block->adev; 4847 4848 cancel_delayed_work_sync(&adev->gfx.idle_work); 4849 4850 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4851 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4852 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4853 gfx_v11_0_set_userq_eop_interrupts(adev, false); 4854 4855 if (!adev->no_hw_access) { 4856 if (amdgpu_async_gfx_ring && 4857 !adev->gfx.disable_kq) { 4858 if (amdgpu_gfx_disable_kgq(adev, 0)) 4859 DRM_ERROR("KGQ disable failed\n"); 4860 } 4861 4862 if (amdgpu_gfx_disable_kcq(adev, 0)) 4863 DRM_ERROR("KCQ disable failed\n"); 4864 4865 amdgpu_mes_kiq_hw_fini(adev); 4866 } 4867 4868 if (amdgpu_sriov_vf(adev)) 4869 /* Remove the steps disabling CPG and clearing KIQ position, 4870 * so that CP could perform IDLE-SAVE during switch. Those 4871 * steps are necessary to avoid a DMAR error in gfx9 but it is 4872 * not reproduced on gfx11. 4873 */ 4874 return 0; 4875 4876 gfx_v11_0_cp_enable(adev, false); 4877 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4878 4879 adev->gfxhub.funcs->gart_disable(adev); 4880 4881 adev->gfx.is_poweron = false; 4882 4883 return 0; 4884 } 4885 4886 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 4887 { 4888 return gfx_v11_0_hw_fini(ip_block); 4889 } 4890 4891 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 4892 { 4893 return gfx_v11_0_hw_init(ip_block); 4894 } 4895 4896 static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 4897 { 4898 struct amdgpu_device *adev = ip_block->adev; 4899 4900 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4901 GRBM_STATUS, GUI_ACTIVE)) 4902 return false; 4903 else 4904 return true; 4905 } 4906 4907 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4908 { 4909 unsigned i; 4910 u32 tmp; 4911 struct amdgpu_device *adev = ip_block->adev; 4912 4913 for (i = 0; i < adev->usec_timeout; i++) { 4914 /* read MC_STATUS */ 4915 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4916 GRBM_STATUS__GUI_ACTIVE_MASK; 4917 4918 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4919 return 0; 4920 udelay(1); 4921 } 4922 return -ETIMEDOUT; 4923 } 4924 4925 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4926 bool req) 4927 { 4928 u32 i, tmp, val; 4929 4930 for (i = 0; i < adev->usec_timeout; i++) { 4931 /* Request with MeId=2, PipeId=0 */ 4932 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4933 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4934 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4935 4936 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4937 if (req) { 4938 if (val == tmp) 4939 break; 4940 } else { 4941 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4942 REQUEST, 1); 4943 4944 /* unlocked or locked by firmware */ 4945 if (val != tmp) 4946 break; 4947 } 4948 udelay(1); 4949 } 4950 4951 if (i >= adev->usec_timeout) 4952 return -EINVAL; 4953 4954 return 0; 4955 } 4956 4957 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 4958 { 4959 u32 grbm_soft_reset = 0; 4960 u32 tmp; 4961 int r, i, j, k; 4962 struct amdgpu_device *adev = ip_block->adev; 4963 4964 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4965 4966 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4967 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4968 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4969 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4970 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4971 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4972 4973 mutex_lock(&adev->srbm_mutex); 4974 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4975 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4976 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4977 soc21_grbm_select(adev, i, k, j, 0); 4978 4979 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4980 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4981 } 4982 } 4983 } 4984 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4985 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4986 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4987 soc21_grbm_select(adev, i, k, j, 0); 4988 4989 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4990 } 4991 } 4992 } 4993 soc21_grbm_select(adev, 0, 0, 0, 0); 4994 mutex_unlock(&adev->srbm_mutex); 4995 4996 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4997 mutex_lock(&adev->gfx.reset_sem_mutex); 4998 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 4999 if (r) { 5000 mutex_unlock(&adev->gfx.reset_sem_mutex); 5001 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 5002 return r; 5003 } 5004 5005 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 5006 5007 // Read CP_VMID_RESET register three times. 5008 // to get sufficient time for GFX_HQD_ACTIVE reach 0 5009 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5010 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5011 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5012 5013 /* release the gfx mutex */ 5014 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 5015 mutex_unlock(&adev->gfx.reset_sem_mutex); 5016 if (r) { 5017 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 5018 return r; 5019 } 5020 5021 for (i = 0; i < adev->usec_timeout; i++) { 5022 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 5023 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 5024 break; 5025 udelay(1); 5026 } 5027 if (i >= adev->usec_timeout) { 5028 printk("Failed to wait all pipes clean\n"); 5029 return -EINVAL; 5030 } 5031 5032 /********** trigger soft reset ***********/ 5033 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5034 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5035 SOFT_RESET_CP, 1); 5036 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5037 SOFT_RESET_GFX, 1); 5038 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5039 SOFT_RESET_CPF, 1); 5040 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5041 SOFT_RESET_CPC, 1); 5042 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5043 SOFT_RESET_CPG, 1); 5044 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5045 /********** exit soft reset ***********/ 5046 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5047 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5048 SOFT_RESET_CP, 0); 5049 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5050 SOFT_RESET_GFX, 0); 5051 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5052 SOFT_RESET_CPF, 0); 5053 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5054 SOFT_RESET_CPC, 0); 5055 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5056 SOFT_RESET_CPG, 0); 5057 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5058 5059 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 5060 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 5061 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 5062 5063 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 5064 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 5065 5066 for (i = 0; i < adev->usec_timeout; i++) { 5067 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 5068 break; 5069 udelay(1); 5070 } 5071 if (i >= adev->usec_timeout) { 5072 printk("Failed to wait CP_VMID_RESET to 0\n"); 5073 return -EINVAL; 5074 } 5075 5076 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5077 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5078 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5079 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5080 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5081 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5082 5083 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5084 5085 return gfx_v11_0_cp_resume(adev); 5086 } 5087 5088 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 5089 { 5090 int i, r; 5091 struct amdgpu_device *adev = ip_block->adev; 5092 struct amdgpu_ring *ring; 5093 long tmo = msecs_to_jiffies(1000); 5094 5095 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5096 ring = &adev->gfx.gfx_ring[i]; 5097 r = amdgpu_ring_test_ib(ring, tmo); 5098 if (r) 5099 return true; 5100 } 5101 5102 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5103 ring = &adev->gfx.compute_ring[i]; 5104 r = amdgpu_ring_test_ib(ring, tmo); 5105 if (r) 5106 return true; 5107 } 5108 5109 return false; 5110 } 5111 5112 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5113 { 5114 struct amdgpu_device *adev = ip_block->adev; 5115 /** 5116 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 5117 */ 5118 return amdgpu_mes_resume(adev); 5119 } 5120 5121 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5122 { 5123 uint64_t clock; 5124 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5125 5126 if (amdgpu_sriov_vf(adev)) { 5127 amdgpu_gfx_off_ctrl(adev, false); 5128 mutex_lock(&adev->gfx.gpu_clock_mutex); 5129 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5130 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5131 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5132 if (clock_counter_hi_pre != clock_counter_hi_after) 5133 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5134 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5135 amdgpu_gfx_off_ctrl(adev, true); 5136 } else { 5137 preempt_disable(); 5138 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5139 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5140 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5141 if (clock_counter_hi_pre != clock_counter_hi_after) 5142 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5143 preempt_enable(); 5144 } 5145 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5146 5147 return clock; 5148 } 5149 5150 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5151 uint32_t vmid, 5152 uint32_t gds_base, uint32_t gds_size, 5153 uint32_t gws_base, uint32_t gws_size, 5154 uint32_t oa_base, uint32_t oa_size) 5155 { 5156 struct amdgpu_device *adev = ring->adev; 5157 5158 /* GDS Base */ 5159 gfx_v11_0_write_data_to_reg(ring, 0, false, 5160 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5161 gds_base); 5162 5163 /* GDS Size */ 5164 gfx_v11_0_write_data_to_reg(ring, 0, false, 5165 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5166 gds_size); 5167 5168 /* GWS */ 5169 gfx_v11_0_write_data_to_reg(ring, 0, false, 5170 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5171 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5172 5173 /* OA */ 5174 gfx_v11_0_write_data_to_reg(ring, 0, false, 5175 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5176 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5177 } 5178 5179 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5180 { 5181 struct amdgpu_device *adev = ip_block->adev; 5182 5183 if (amdgpu_disable_kq == 1) 5184 adev->gfx.disable_kq = true; 5185 5186 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5187 5188 if (adev->gfx.disable_kq) { 5189 /* We need one GFX ring temporarily to set up 5190 * the clear state. 5191 */ 5192 adev->gfx.num_gfx_rings = 1; 5193 adev->gfx.num_compute_rings = 0; 5194 } else { 5195 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5196 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5197 AMDGPU_MAX_COMPUTE_RINGS); 5198 } 5199 5200 gfx_v11_0_set_kiq_pm4_funcs(adev); 5201 gfx_v11_0_set_ring_funcs(adev); 5202 gfx_v11_0_set_irq_funcs(adev); 5203 gfx_v11_0_set_gds_init(adev); 5204 gfx_v11_0_set_rlc_funcs(adev); 5205 gfx_v11_0_set_mqd_funcs(adev); 5206 gfx_v11_0_set_imu_funcs(adev); 5207 5208 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5209 5210 return gfx_v11_0_init_microcode(adev); 5211 } 5212 5213 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) 5214 { 5215 struct amdgpu_device *adev = ip_block->adev; 5216 int r; 5217 5218 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5219 if (r) 5220 return r; 5221 5222 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5223 if (r) 5224 return r; 5225 5226 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5227 if (r) 5228 return r; 5229 5230 r = gfx_v11_0_set_userq_eop_interrupts(adev, true); 5231 if (r) 5232 return r; 5233 5234 return 0; 5235 } 5236 5237 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5238 { 5239 uint32_t rlc_cntl; 5240 5241 /* if RLC is not enabled, do nothing */ 5242 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5243 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5244 } 5245 5246 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5247 { 5248 uint32_t data; 5249 unsigned i; 5250 5251 data = RLC_SAFE_MODE__CMD_MASK; 5252 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5253 5254 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5255 5256 /* wait for RLC_SAFE_MODE */ 5257 for (i = 0; i < adev->usec_timeout; i++) { 5258 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5259 RLC_SAFE_MODE, CMD)) 5260 break; 5261 udelay(1); 5262 } 5263 } 5264 5265 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5266 { 5267 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5268 } 5269 5270 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5271 bool enable) 5272 { 5273 uint32_t def, data; 5274 5275 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5276 return; 5277 5278 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5279 5280 if (enable) 5281 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5282 else 5283 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5284 5285 if (def != data) 5286 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5287 } 5288 5289 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5290 bool enable) 5291 { 5292 uint32_t def, data; 5293 5294 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5295 return; 5296 5297 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5298 5299 if (enable) 5300 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5301 else 5302 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5303 5304 if (def != data) 5305 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5306 } 5307 5308 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5309 bool enable) 5310 { 5311 uint32_t def, data; 5312 5313 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5314 return; 5315 5316 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5317 5318 if (enable) 5319 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5320 else 5321 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5322 5323 if (def != data) 5324 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5325 } 5326 5327 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5328 bool enable) 5329 { 5330 uint32_t data, def; 5331 5332 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5333 return; 5334 5335 /* It is disabled by HW by default */ 5336 if (enable) { 5337 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5338 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5339 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5340 5341 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5342 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5343 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5344 5345 if (def != data) 5346 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5347 } 5348 } else { 5349 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5350 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5351 5352 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5353 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5354 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5355 5356 if (def != data) 5357 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5358 } 5359 } 5360 } 5361 5362 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5363 bool enable) 5364 { 5365 uint32_t def, data; 5366 5367 if (!(adev->cg_flags & 5368 (AMD_CG_SUPPORT_GFX_CGCG | 5369 AMD_CG_SUPPORT_GFX_CGLS | 5370 AMD_CG_SUPPORT_GFX_3D_CGCG | 5371 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5372 return; 5373 5374 if (enable) { 5375 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5376 5377 /* unset CGCG override */ 5378 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5379 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5380 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5381 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5382 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5383 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5384 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5385 5386 /* update CGCG override bits */ 5387 if (def != data) 5388 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5389 5390 /* enable cgcg FSM(0x0000363F) */ 5391 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5392 5393 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5394 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5395 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5396 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5397 } 5398 5399 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5400 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5401 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5402 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5403 } 5404 5405 if (def != data) 5406 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5407 5408 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5409 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5410 5411 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5412 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5413 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5414 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5415 } 5416 5417 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5418 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5419 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5420 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5421 } 5422 5423 if (def != data) 5424 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5425 5426 /* set IDLE_POLL_COUNT(0x00900100) */ 5427 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5428 5429 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5430 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5431 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5432 5433 if (def != data) 5434 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5435 5436 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5437 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5438 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5439 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5440 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5441 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5442 5443 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5444 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5445 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5446 5447 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5448 if (adev->sdma.num_instances > 1) { 5449 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5450 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5451 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5452 } 5453 } else { 5454 /* Program RLC_CGCG_CGLS_CTRL */ 5455 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5456 5457 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5458 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5459 5460 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5461 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5462 5463 if (def != data) 5464 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5465 5466 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5467 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5468 5469 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5470 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5471 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5472 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5473 5474 if (def != data) 5475 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5476 5477 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5478 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5479 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5480 5481 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5482 if (adev->sdma.num_instances > 1) { 5483 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5484 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5485 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5486 } 5487 } 5488 } 5489 5490 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5491 bool enable) 5492 { 5493 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5494 5495 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5496 5497 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5498 5499 gfx_v11_0_update_repeater_fgcg(adev, enable); 5500 5501 gfx_v11_0_update_sram_fgcg(adev, enable); 5502 5503 gfx_v11_0_update_perf_clk(adev, enable); 5504 5505 if (adev->cg_flags & 5506 (AMD_CG_SUPPORT_GFX_MGCG | 5507 AMD_CG_SUPPORT_GFX_CGLS | 5508 AMD_CG_SUPPORT_GFX_CGCG | 5509 AMD_CG_SUPPORT_GFX_3D_CGCG | 5510 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5511 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5512 5513 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5514 5515 return 0; 5516 } 5517 5518 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5519 { 5520 u32 reg, pre_data, data; 5521 5522 amdgpu_gfx_off_ctrl(adev, false); 5523 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5524 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5525 pre_data = RREG32_NO_KIQ(reg); 5526 else 5527 pre_data = RREG32(reg); 5528 5529 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5530 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5531 5532 if (pre_data != data) { 5533 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5534 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5535 } else 5536 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5537 } 5538 amdgpu_gfx_off_ctrl(adev, true); 5539 5540 if (ring 5541 && amdgpu_sriov_is_pp_one_vf(adev) 5542 && (pre_data != data) 5543 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5544 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5545 amdgpu_ring_emit_wreg(ring, reg, data); 5546 } 5547 } 5548 5549 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5550 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5551 .set_safe_mode = gfx_v11_0_set_safe_mode, 5552 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5553 .init = gfx_v11_0_rlc_init, 5554 .get_csb_size = gfx_v11_0_get_csb_size, 5555 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5556 .resume = gfx_v11_0_rlc_resume, 5557 .stop = gfx_v11_0_rlc_stop, 5558 .reset = gfx_v11_0_rlc_reset, 5559 .start = gfx_v11_0_rlc_start, 5560 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5561 }; 5562 5563 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5564 { 5565 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5566 5567 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5568 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5569 else 5570 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5571 5572 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5573 5574 // Program RLC_PG_DELAY3 for CGPG hysteresis 5575 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5576 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5577 case IP_VERSION(11, 0, 1): 5578 case IP_VERSION(11, 0, 4): 5579 case IP_VERSION(11, 5, 0): 5580 case IP_VERSION(11, 5, 1): 5581 case IP_VERSION(11, 5, 2): 5582 case IP_VERSION(11, 5, 3): 5583 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5584 break; 5585 default: 5586 break; 5587 } 5588 } 5589 } 5590 5591 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5592 { 5593 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5594 5595 gfx_v11_cntl_power_gating(adev, enable); 5596 5597 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5598 } 5599 5600 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5601 enum amd_powergating_state state) 5602 { 5603 struct amdgpu_device *adev = ip_block->adev; 5604 bool enable = (state == AMD_PG_STATE_GATE); 5605 5606 if (amdgpu_sriov_vf(adev)) 5607 return 0; 5608 5609 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5610 case IP_VERSION(11, 0, 0): 5611 case IP_VERSION(11, 0, 2): 5612 case IP_VERSION(11, 0, 3): 5613 amdgpu_gfx_off_ctrl(adev, enable); 5614 break; 5615 case IP_VERSION(11, 0, 1): 5616 case IP_VERSION(11, 0, 4): 5617 case IP_VERSION(11, 5, 0): 5618 case IP_VERSION(11, 5, 1): 5619 case IP_VERSION(11, 5, 2): 5620 case IP_VERSION(11, 5, 3): 5621 if (!enable) 5622 amdgpu_gfx_off_ctrl(adev, false); 5623 5624 gfx_v11_cntl_pg(adev, enable); 5625 5626 if (enable) 5627 amdgpu_gfx_off_ctrl(adev, true); 5628 5629 break; 5630 default: 5631 break; 5632 } 5633 5634 return 0; 5635 } 5636 5637 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5638 enum amd_clockgating_state state) 5639 { 5640 struct amdgpu_device *adev = ip_block->adev; 5641 5642 if (amdgpu_sriov_vf(adev)) 5643 return 0; 5644 5645 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5646 case IP_VERSION(11, 0, 0): 5647 case IP_VERSION(11, 0, 1): 5648 case IP_VERSION(11, 0, 2): 5649 case IP_VERSION(11, 0, 3): 5650 case IP_VERSION(11, 0, 4): 5651 case IP_VERSION(11, 5, 0): 5652 case IP_VERSION(11, 5, 1): 5653 case IP_VERSION(11, 5, 2): 5654 case IP_VERSION(11, 5, 3): 5655 gfx_v11_0_update_gfx_clock_gating(adev, 5656 state == AMD_CG_STATE_GATE); 5657 break; 5658 default: 5659 break; 5660 } 5661 5662 return 0; 5663 } 5664 5665 static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 5666 { 5667 struct amdgpu_device *adev = ip_block->adev; 5668 int data; 5669 5670 /* AMD_CG_SUPPORT_GFX_MGCG */ 5671 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5672 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5673 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5674 5675 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5676 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5677 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5678 5679 /* AMD_CG_SUPPORT_GFX_FGCG */ 5680 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5681 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5682 5683 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5684 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5685 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5686 5687 /* AMD_CG_SUPPORT_GFX_CGCG */ 5688 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5689 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5690 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5691 5692 /* AMD_CG_SUPPORT_GFX_CGLS */ 5693 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5694 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5695 5696 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5697 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5698 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5699 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5700 5701 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5702 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5703 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5704 } 5705 5706 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5707 { 5708 /* gfx11 is 32bit rptr*/ 5709 return *(uint32_t *)ring->rptr_cpu_addr; 5710 } 5711 5712 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5713 { 5714 struct amdgpu_device *adev = ring->adev; 5715 u64 wptr; 5716 5717 /* XXX check if swapping is necessary on BE */ 5718 if (ring->use_doorbell) { 5719 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5720 } else { 5721 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5722 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5723 } 5724 5725 return wptr; 5726 } 5727 5728 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5729 { 5730 struct amdgpu_device *adev = ring->adev; 5731 5732 if (ring->use_doorbell) { 5733 /* XXX check if swapping is necessary on BE */ 5734 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5735 ring->wptr); 5736 WDOORBELL64(ring->doorbell_index, ring->wptr); 5737 } else { 5738 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5739 lower_32_bits(ring->wptr)); 5740 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5741 upper_32_bits(ring->wptr)); 5742 } 5743 } 5744 5745 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5746 { 5747 /* gfx11 hardware is 32bit rptr */ 5748 return *(uint32_t *)ring->rptr_cpu_addr; 5749 } 5750 5751 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5752 { 5753 u64 wptr; 5754 5755 /* XXX check if swapping is necessary on BE */ 5756 if (ring->use_doorbell) 5757 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5758 else 5759 BUG(); 5760 return wptr; 5761 } 5762 5763 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5764 { 5765 struct amdgpu_device *adev = ring->adev; 5766 5767 /* XXX check if swapping is necessary on BE */ 5768 if (ring->use_doorbell) { 5769 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5770 ring->wptr); 5771 WDOORBELL64(ring->doorbell_index, ring->wptr); 5772 } else { 5773 BUG(); /* only DOORBELL method supported on gfx11 now */ 5774 } 5775 } 5776 5777 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5778 { 5779 struct amdgpu_device *adev = ring->adev; 5780 u32 ref_and_mask, reg_mem_engine; 5781 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5782 5783 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5784 switch (ring->me) { 5785 case 1: 5786 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5787 break; 5788 case 2: 5789 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5790 break; 5791 default: 5792 return; 5793 } 5794 reg_mem_engine = 0; 5795 } else { 5796 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5797 reg_mem_engine = 1; /* pfp */ 5798 } 5799 5800 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5801 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5802 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5803 ref_and_mask, ref_and_mask, 0x20); 5804 } 5805 5806 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5807 struct amdgpu_job *job, 5808 struct amdgpu_ib *ib, 5809 uint32_t flags) 5810 { 5811 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5812 u32 header, control = 0; 5813 5814 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5815 5816 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5817 5818 control |= ib->length_dw | (vmid << 24); 5819 5820 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5821 control |= INDIRECT_BUFFER_PRE_ENB(1); 5822 5823 if (flags & AMDGPU_IB_PREEMPTED) 5824 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5825 5826 if (vmid) 5827 gfx_v11_0_ring_emit_de_meta(ring, 5828 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5829 } 5830 5831 amdgpu_ring_write(ring, header); 5832 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5833 amdgpu_ring_write(ring, 5834 #ifdef __BIG_ENDIAN 5835 (2 << 0) | 5836 #endif 5837 lower_32_bits(ib->gpu_addr)); 5838 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5839 amdgpu_ring_write(ring, control); 5840 } 5841 5842 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5843 struct amdgpu_job *job, 5844 struct amdgpu_ib *ib, 5845 uint32_t flags) 5846 { 5847 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5848 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5849 5850 /* Currently, there is a high possibility to get wave ID mismatch 5851 * between ME and GDS, leading to a hw deadlock, because ME generates 5852 * different wave IDs than the GDS expects. This situation happens 5853 * randomly when at least 5 compute pipes use GDS ordered append. 5854 * The wave IDs generated by ME are also wrong after suspend/resume. 5855 * Those are probably bugs somewhere else in the kernel driver. 5856 * 5857 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5858 * GDS to 0 for this ring (me/pipe). 5859 */ 5860 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5861 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5862 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5863 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5864 } 5865 5866 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5867 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5868 amdgpu_ring_write(ring, 5869 #ifdef __BIG_ENDIAN 5870 (2 << 0) | 5871 #endif 5872 lower_32_bits(ib->gpu_addr)); 5873 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5874 amdgpu_ring_write(ring, control); 5875 } 5876 5877 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5878 u64 seq, unsigned flags) 5879 { 5880 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5881 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5882 5883 /* RELEASE_MEM - flush caches, send int */ 5884 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5885 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5886 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5887 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5888 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5889 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5890 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5891 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5892 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5893 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5894 5895 /* 5896 * the address should be Qword aligned if 64bit write, Dword 5897 * aligned if only send 32bit data low (discard data high) 5898 */ 5899 if (write64bit) 5900 BUG_ON(addr & 0x7); 5901 else 5902 BUG_ON(addr & 0x3); 5903 amdgpu_ring_write(ring, lower_32_bits(addr)); 5904 amdgpu_ring_write(ring, upper_32_bits(addr)); 5905 amdgpu_ring_write(ring, lower_32_bits(seq)); 5906 amdgpu_ring_write(ring, upper_32_bits(seq)); 5907 amdgpu_ring_write(ring, 0); 5908 } 5909 5910 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5911 { 5912 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5913 uint32_t seq = ring->fence_drv.sync_seq; 5914 uint64_t addr = ring->fence_drv.gpu_addr; 5915 5916 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5917 upper_32_bits(addr), seq, 0xffffffff, 4); 5918 } 5919 5920 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5921 uint16_t pasid, uint32_t flush_type, 5922 bool all_hub, uint8_t dst_sel) 5923 { 5924 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5925 amdgpu_ring_write(ring, 5926 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5927 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5928 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5929 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5930 } 5931 5932 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5933 unsigned vmid, uint64_t pd_addr) 5934 { 5935 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5936 5937 /* compute doesn't have PFP */ 5938 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5939 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5940 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5941 amdgpu_ring_write(ring, 0x0); 5942 } 5943 5944 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5945 * changed in any way. 5946 */ 5947 ring->set_q_mode_offs = 0; 5948 ring->set_q_mode_ptr = NULL; 5949 } 5950 5951 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5952 u64 seq, unsigned int flags) 5953 { 5954 struct amdgpu_device *adev = ring->adev; 5955 5956 /* we only allocate 32bit for each seq wb address */ 5957 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5958 5959 /* write fence seq to the "addr" */ 5960 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5961 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5962 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5963 amdgpu_ring_write(ring, lower_32_bits(addr)); 5964 amdgpu_ring_write(ring, upper_32_bits(addr)); 5965 amdgpu_ring_write(ring, lower_32_bits(seq)); 5966 5967 if (flags & AMDGPU_FENCE_FLAG_INT) { 5968 /* set register to trigger INT */ 5969 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5970 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5971 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5972 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5973 amdgpu_ring_write(ring, 0); 5974 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5975 } 5976 } 5977 5978 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5979 uint32_t flags) 5980 { 5981 uint32_t dw2 = 0; 5982 5983 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5984 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5985 /* set load_global_config & load_global_uconfig */ 5986 dw2 |= 0x8001; 5987 /* set load_cs_sh_regs */ 5988 dw2 |= 0x01000000; 5989 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5990 dw2 |= 0x10002; 5991 } 5992 5993 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5994 amdgpu_ring_write(ring, dw2); 5995 amdgpu_ring_write(ring, 0); 5996 } 5997 5998 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5999 uint64_t addr) 6000 { 6001 unsigned ret; 6002 6003 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6004 amdgpu_ring_write(ring, lower_32_bits(addr)); 6005 amdgpu_ring_write(ring, upper_32_bits(addr)); 6006 /* discard following DWs if *cond_exec_gpu_addr==0 */ 6007 amdgpu_ring_write(ring, 0); 6008 ret = ring->wptr & ring->buf_mask; 6009 /* patch dummy value later */ 6010 amdgpu_ring_write(ring, 0); 6011 6012 return ret; 6013 } 6014 6015 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 6016 u64 shadow_va, u64 csa_va, 6017 u64 gds_va, bool init_shadow, 6018 int vmid) 6019 { 6020 struct amdgpu_device *adev = ring->adev; 6021 unsigned int offs, end; 6022 6023 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 6024 return; 6025 6026 /* 6027 * The logic here isn't easy to understand because we need to keep state 6028 * accross multiple executions of the function as well as between the 6029 * CPU and GPU. The general idea is that the newly written GPU command 6030 * has a condition on the previous one and only executed if really 6031 * necessary. 6032 */ 6033 6034 /* 6035 * The dw in the NOP controls if the next SET_Q_MODE packet should be 6036 * executed or not. Reserve 64bits just to be on the save side. 6037 */ 6038 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 6039 offs = ring->wptr & ring->buf_mask; 6040 6041 /* 6042 * We start with skipping the prefix SET_Q_MODE and always executing 6043 * the postfix SET_Q_MODE packet. This is changed below with a 6044 * WRITE_DATA command when the postfix executed. 6045 */ 6046 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 6047 amdgpu_ring_write(ring, 0); 6048 6049 if (ring->set_q_mode_offs) { 6050 uint64_t addr; 6051 6052 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6053 addr += ring->set_q_mode_offs << 2; 6054 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 6055 } 6056 6057 /* 6058 * When the postfix SET_Q_MODE packet executes we need to make sure that the 6059 * next prefix SET_Q_MODE packet executes as well. 6060 */ 6061 if (!shadow_va) { 6062 uint64_t addr; 6063 6064 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6065 addr += offs << 2; 6066 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6067 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 6068 amdgpu_ring_write(ring, lower_32_bits(addr)); 6069 amdgpu_ring_write(ring, upper_32_bits(addr)); 6070 amdgpu_ring_write(ring, 0x1); 6071 } 6072 6073 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 6074 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 6075 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 6076 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 6077 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 6078 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 6079 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 6080 amdgpu_ring_write(ring, shadow_va ? 6081 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 6082 amdgpu_ring_write(ring, init_shadow ? 6083 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 6084 6085 if (ring->set_q_mode_offs) 6086 amdgpu_ring_patch_cond_exec(ring, end); 6087 6088 if (shadow_va) { 6089 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 6090 6091 /* 6092 * If the tokens match try to skip the last postfix SET_Q_MODE 6093 * packet to avoid saving/restoring the state all the time. 6094 */ 6095 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 6096 *ring->set_q_mode_ptr = 0; 6097 6098 ring->set_q_mode_token = token; 6099 } else { 6100 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 6101 } 6102 6103 ring->set_q_mode_offs = offs; 6104 } 6105 6106 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 6107 { 6108 int i, r = 0; 6109 struct amdgpu_device *adev = ring->adev; 6110 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6111 struct amdgpu_ring *kiq_ring = &kiq->ring; 6112 unsigned long flags; 6113 6114 if (adev->enable_mes) 6115 return -EINVAL; 6116 6117 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6118 return -EINVAL; 6119 6120 spin_lock_irqsave(&kiq->ring_lock, flags); 6121 6122 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 6123 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6124 return -ENOMEM; 6125 } 6126 6127 /* assert preemption condition */ 6128 amdgpu_ring_set_preempt_cond_exec(ring, false); 6129 6130 /* assert IB preemption, emit the trailing fence */ 6131 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 6132 ring->trail_fence_gpu_addr, 6133 ++ring->trail_seq); 6134 amdgpu_ring_commit(kiq_ring); 6135 6136 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6137 6138 /* poll the trailing fence */ 6139 for (i = 0; i < adev->usec_timeout; i++) { 6140 if (ring->trail_seq == 6141 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 6142 break; 6143 udelay(1); 6144 } 6145 6146 if (i >= adev->usec_timeout) { 6147 r = -EINVAL; 6148 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 6149 } 6150 6151 /* deassert preemption condition */ 6152 amdgpu_ring_set_preempt_cond_exec(ring, true); 6153 return r; 6154 } 6155 6156 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6157 { 6158 struct amdgpu_device *adev = ring->adev; 6159 struct v10_de_ib_state de_payload = {0}; 6160 uint64_t offset, gds_addr, de_payload_gpu_addr; 6161 void *de_payload_cpu_addr; 6162 int cnt; 6163 6164 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6165 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6166 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6167 6168 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6169 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6170 PAGE_SIZE); 6171 6172 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6173 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6174 6175 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6176 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6177 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6178 WRITE_DATA_DST_SEL(8) | 6179 WR_CONFIRM) | 6180 WRITE_DATA_CACHE_POLICY(0)); 6181 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6182 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6183 6184 if (resume) 6185 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6186 sizeof(de_payload) >> 2); 6187 else 6188 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6189 sizeof(de_payload) >> 2); 6190 } 6191 6192 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6193 bool secure) 6194 { 6195 uint32_t v = secure ? FRAME_TMZ : 0; 6196 6197 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6198 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6199 } 6200 6201 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6202 uint32_t reg_val_offs) 6203 { 6204 struct amdgpu_device *adev = ring->adev; 6205 6206 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6207 amdgpu_ring_write(ring, 0 | /* src: register*/ 6208 (5 << 8) | /* dst: memory */ 6209 (1 << 20)); /* write confirm */ 6210 amdgpu_ring_write(ring, reg); 6211 amdgpu_ring_write(ring, 0); 6212 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6213 reg_val_offs * 4)); 6214 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6215 reg_val_offs * 4)); 6216 } 6217 6218 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6219 uint32_t val) 6220 { 6221 uint32_t cmd = 0; 6222 6223 switch (ring->funcs->type) { 6224 case AMDGPU_RING_TYPE_GFX: 6225 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6226 break; 6227 case AMDGPU_RING_TYPE_KIQ: 6228 cmd = (1 << 16); /* no inc addr */ 6229 break; 6230 default: 6231 cmd = WR_CONFIRM; 6232 break; 6233 } 6234 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6235 amdgpu_ring_write(ring, cmd); 6236 amdgpu_ring_write(ring, reg); 6237 amdgpu_ring_write(ring, 0); 6238 amdgpu_ring_write(ring, val); 6239 } 6240 6241 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6242 uint32_t val, uint32_t mask) 6243 { 6244 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6245 } 6246 6247 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6248 uint32_t reg0, uint32_t reg1, 6249 uint32_t ref, uint32_t mask) 6250 { 6251 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6252 6253 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6254 ref, mask, 0x20); 6255 } 6256 6257 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 6258 unsigned vmid) 6259 { 6260 struct amdgpu_device *adev = ring->adev; 6261 uint32_t value = 0; 6262 6263 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6264 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6265 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6266 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6267 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 6268 WREG32_SOC15(GC, 0, regSQ_CMD, value); 6269 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 6270 } 6271 6272 static void 6273 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6274 uint32_t me, uint32_t pipe, 6275 enum amdgpu_interrupt_state state) 6276 { 6277 uint32_t cp_int_cntl, cp_int_cntl_reg; 6278 6279 if (!me) { 6280 switch (pipe) { 6281 case 0: 6282 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6283 break; 6284 case 1: 6285 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6286 break; 6287 default: 6288 DRM_DEBUG("invalid pipe %d\n", pipe); 6289 return; 6290 } 6291 } else { 6292 DRM_DEBUG("invalid me %d\n", me); 6293 return; 6294 } 6295 6296 switch (state) { 6297 case AMDGPU_IRQ_STATE_DISABLE: 6298 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6299 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6300 TIME_STAMP_INT_ENABLE, 0); 6301 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6302 GENERIC0_INT_ENABLE, 0); 6303 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6304 break; 6305 case AMDGPU_IRQ_STATE_ENABLE: 6306 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6307 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6308 TIME_STAMP_INT_ENABLE, 1); 6309 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6310 GENERIC0_INT_ENABLE, 1); 6311 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6312 break; 6313 default: 6314 break; 6315 } 6316 } 6317 6318 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6319 int me, int pipe, 6320 enum amdgpu_interrupt_state state) 6321 { 6322 u32 mec_int_cntl, mec_int_cntl_reg; 6323 6324 /* 6325 * amdgpu controls only the first MEC. That's why this function only 6326 * handles the setting of interrupts for this specific MEC. All other 6327 * pipes' interrupts are set by amdkfd. 6328 */ 6329 6330 if (me == 1) { 6331 switch (pipe) { 6332 case 0: 6333 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6334 break; 6335 case 1: 6336 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6337 break; 6338 case 2: 6339 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6340 break; 6341 case 3: 6342 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6343 break; 6344 default: 6345 DRM_DEBUG("invalid pipe %d\n", pipe); 6346 return; 6347 } 6348 } else { 6349 DRM_DEBUG("invalid me %d\n", me); 6350 return; 6351 } 6352 6353 switch (state) { 6354 case AMDGPU_IRQ_STATE_DISABLE: 6355 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6356 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6357 TIME_STAMP_INT_ENABLE, 0); 6358 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6359 GENERIC0_INT_ENABLE, 0); 6360 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6361 break; 6362 case AMDGPU_IRQ_STATE_ENABLE: 6363 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6364 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6365 TIME_STAMP_INT_ENABLE, 1); 6366 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6367 GENERIC0_INT_ENABLE, 1); 6368 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6369 break; 6370 default: 6371 break; 6372 } 6373 } 6374 6375 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6376 struct amdgpu_irq_src *src, 6377 unsigned type, 6378 enum amdgpu_interrupt_state state) 6379 { 6380 switch (type) { 6381 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6382 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6383 break; 6384 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6385 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6386 break; 6387 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6388 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6389 break; 6390 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6391 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6392 break; 6393 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6394 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6395 break; 6396 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6397 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6398 break; 6399 default: 6400 break; 6401 } 6402 return 0; 6403 } 6404 6405 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6406 struct amdgpu_irq_src *source, 6407 struct amdgpu_iv_entry *entry) 6408 { 6409 u32 doorbell_offset = entry->src_data[0]; 6410 u8 me_id, pipe_id, queue_id; 6411 struct amdgpu_ring *ring; 6412 int i; 6413 6414 DRM_DEBUG("IH: CP EOP\n"); 6415 6416 if (adev->enable_mes && doorbell_offset) { 6417 struct amdgpu_userq_fence_driver *fence_drv = NULL; 6418 struct xarray *xa = &adev->userq_xa; 6419 unsigned long flags; 6420 6421 xa_lock_irqsave(xa, flags); 6422 fence_drv = xa_load(xa, doorbell_offset); 6423 if (fence_drv) 6424 amdgpu_userq_fence_driver_process(fence_drv); 6425 xa_unlock_irqrestore(xa, flags); 6426 } else { 6427 me_id = (entry->ring_id & 0x0c) >> 2; 6428 pipe_id = (entry->ring_id & 0x03) >> 0; 6429 queue_id = (entry->ring_id & 0x70) >> 4; 6430 6431 switch (me_id) { 6432 case 0: 6433 if (pipe_id == 0) 6434 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6435 else 6436 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6437 break; 6438 case 1: 6439 case 2: 6440 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6441 ring = &adev->gfx.compute_ring[i]; 6442 /* Per-queue interrupt is supported for MEC starting from VI. 6443 * The interrupt can only be enabled/disabled per pipe instead 6444 * of per queue. 6445 */ 6446 if ((ring->me == me_id) && 6447 (ring->pipe == pipe_id) && 6448 (ring->queue == queue_id)) 6449 amdgpu_fence_process(ring); 6450 } 6451 break; 6452 } 6453 } 6454 6455 return 0; 6456 } 6457 6458 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6459 struct amdgpu_irq_src *source, 6460 unsigned int type, 6461 enum amdgpu_interrupt_state state) 6462 { 6463 u32 cp_int_cntl_reg, cp_int_cntl; 6464 int i, j; 6465 6466 switch (state) { 6467 case AMDGPU_IRQ_STATE_DISABLE: 6468 case AMDGPU_IRQ_STATE_ENABLE: 6469 for (i = 0; i < adev->gfx.me.num_me; i++) { 6470 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6471 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6472 6473 if (cp_int_cntl_reg) { 6474 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6475 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6476 PRIV_REG_INT_ENABLE, 6477 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6478 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6479 } 6480 } 6481 } 6482 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6483 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6484 /* MECs start at 1 */ 6485 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6486 6487 if (cp_int_cntl_reg) { 6488 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6489 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6490 PRIV_REG_INT_ENABLE, 6491 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6492 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6493 } 6494 } 6495 } 6496 break; 6497 default: 6498 break; 6499 } 6500 6501 return 0; 6502 } 6503 6504 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6505 struct amdgpu_irq_src *source, 6506 unsigned type, 6507 enum amdgpu_interrupt_state state) 6508 { 6509 u32 cp_int_cntl_reg, cp_int_cntl; 6510 int i, j; 6511 6512 switch (state) { 6513 case AMDGPU_IRQ_STATE_DISABLE: 6514 case AMDGPU_IRQ_STATE_ENABLE: 6515 for (i = 0; i < adev->gfx.me.num_me; i++) { 6516 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6517 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6518 6519 if (cp_int_cntl_reg) { 6520 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6521 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6522 OPCODE_ERROR_INT_ENABLE, 6523 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6524 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6525 } 6526 } 6527 } 6528 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6529 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6530 /* MECs start at 1 */ 6531 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6532 6533 if (cp_int_cntl_reg) { 6534 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6535 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6536 OPCODE_ERROR_INT_ENABLE, 6537 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6538 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6539 } 6540 } 6541 } 6542 break; 6543 default: 6544 break; 6545 } 6546 return 0; 6547 } 6548 6549 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6550 struct amdgpu_irq_src *source, 6551 unsigned int type, 6552 enum amdgpu_interrupt_state state) 6553 { 6554 u32 cp_int_cntl_reg, cp_int_cntl; 6555 int i, j; 6556 6557 switch (state) { 6558 case AMDGPU_IRQ_STATE_DISABLE: 6559 case AMDGPU_IRQ_STATE_ENABLE: 6560 for (i = 0; i < adev->gfx.me.num_me; i++) { 6561 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6562 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6563 6564 if (cp_int_cntl_reg) { 6565 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6566 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6567 PRIV_INSTR_INT_ENABLE, 6568 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6569 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6570 } 6571 } 6572 } 6573 break; 6574 default: 6575 break; 6576 } 6577 6578 return 0; 6579 } 6580 6581 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6582 struct amdgpu_iv_entry *entry) 6583 { 6584 u8 me_id, pipe_id, queue_id; 6585 struct amdgpu_ring *ring; 6586 int i; 6587 6588 me_id = (entry->ring_id & 0x0c) >> 2; 6589 pipe_id = (entry->ring_id & 0x03) >> 0; 6590 queue_id = (entry->ring_id & 0x70) >> 4; 6591 6592 if (!adev->gfx.disable_kq) { 6593 switch (me_id) { 6594 case 0: 6595 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6596 ring = &adev->gfx.gfx_ring[i]; 6597 if (ring->me == me_id && ring->pipe == pipe_id && 6598 ring->queue == queue_id) 6599 drm_sched_fault(&ring->sched); 6600 } 6601 break; 6602 case 1: 6603 case 2: 6604 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6605 ring = &adev->gfx.compute_ring[i]; 6606 if (ring->me == me_id && ring->pipe == pipe_id && 6607 ring->queue == queue_id) 6608 drm_sched_fault(&ring->sched); 6609 } 6610 break; 6611 default: 6612 BUG(); 6613 break; 6614 } 6615 } 6616 } 6617 6618 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6619 struct amdgpu_irq_src *source, 6620 struct amdgpu_iv_entry *entry) 6621 { 6622 DRM_ERROR("Illegal register access in command stream\n"); 6623 gfx_v11_0_handle_priv_fault(adev, entry); 6624 return 0; 6625 } 6626 6627 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6628 struct amdgpu_irq_src *source, 6629 struct amdgpu_iv_entry *entry) 6630 { 6631 DRM_ERROR("Illegal opcode in command stream \n"); 6632 gfx_v11_0_handle_priv_fault(adev, entry); 6633 return 0; 6634 } 6635 6636 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6637 struct amdgpu_irq_src *source, 6638 struct amdgpu_iv_entry *entry) 6639 { 6640 DRM_ERROR("Illegal instruction in command stream\n"); 6641 gfx_v11_0_handle_priv_fault(adev, entry); 6642 return 0; 6643 } 6644 6645 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6646 struct amdgpu_irq_src *source, 6647 struct amdgpu_iv_entry *entry) 6648 { 6649 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6650 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6651 6652 return 0; 6653 } 6654 6655 #if 0 6656 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6657 struct amdgpu_irq_src *src, 6658 unsigned int type, 6659 enum amdgpu_interrupt_state state) 6660 { 6661 uint32_t tmp, target; 6662 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6663 6664 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6665 target += ring->pipe; 6666 6667 switch (type) { 6668 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6669 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6670 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6671 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6672 GENERIC2_INT_ENABLE, 0); 6673 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6674 6675 tmp = RREG32_SOC15_IP(GC, target); 6676 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6677 GENERIC2_INT_ENABLE, 0); 6678 WREG32_SOC15_IP(GC, target, tmp); 6679 } else { 6680 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6681 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6682 GENERIC2_INT_ENABLE, 1); 6683 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6684 6685 tmp = RREG32_SOC15_IP(GC, target); 6686 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6687 GENERIC2_INT_ENABLE, 1); 6688 WREG32_SOC15_IP(GC, target, tmp); 6689 } 6690 break; 6691 default: 6692 BUG(); /* kiq only support GENERIC2_INT now */ 6693 break; 6694 } 6695 return 0; 6696 } 6697 #endif 6698 6699 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6700 { 6701 const unsigned int gcr_cntl = 6702 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6703 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6704 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6705 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6706 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6707 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6708 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6709 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6710 6711 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6712 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6713 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6714 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6715 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6716 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6717 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6718 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6719 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6720 } 6721 6722 static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev) 6723 { 6724 /* Disable the pipe reset until the CPFW fully support it.*/ 6725 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 6726 return false; 6727 } 6728 6729 6730 static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring) 6731 { 6732 struct amdgpu_device *adev = ring->adev; 6733 uint32_t reset_pipe = 0, clean_pipe = 0; 6734 int r; 6735 6736 if (!gfx_v11_pipe_reset_support(adev)) 6737 return -EOPNOTSUPP; 6738 6739 gfx_v11_0_set_safe_mode(adev, 0); 6740 mutex_lock(&adev->srbm_mutex); 6741 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6742 6743 switch (ring->pipe) { 6744 case 0: 6745 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6746 PFP_PIPE0_RESET, 1); 6747 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6748 ME_PIPE0_RESET, 1); 6749 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6750 PFP_PIPE0_RESET, 0); 6751 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6752 ME_PIPE0_RESET, 0); 6753 break; 6754 case 1: 6755 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6756 PFP_PIPE1_RESET, 1); 6757 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6758 ME_PIPE1_RESET, 1); 6759 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6760 PFP_PIPE1_RESET, 0); 6761 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6762 ME_PIPE1_RESET, 0); 6763 break; 6764 default: 6765 break; 6766 } 6767 6768 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 6769 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 6770 6771 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 6772 RS64_FW_UC_START_ADDR_LO; 6773 soc21_grbm_select(adev, 0, 0, 0, 0); 6774 mutex_unlock(&adev->srbm_mutex); 6775 gfx_v11_0_unset_safe_mode(adev, 0); 6776 6777 dev_info(adev->dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring->name, 6778 r == 0 ? "successfully" : "failed"); 6779 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 6780 * so the pipe reset status relies on the later gfx ring test result. 6781 */ 6782 return 0; 6783 } 6784 6785 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 6786 { 6787 struct amdgpu_device *adev = ring->adev; 6788 int r; 6789 6790 if (amdgpu_sriov_vf(adev)) 6791 return -EINVAL; 6792 6793 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 6794 if (r) { 6795 6796 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 6797 r = gfx_v11_reset_gfx_pipe(ring); 6798 if (r) 6799 return r; 6800 } 6801 6802 r = gfx_v11_0_kgq_init_queue(ring, true); 6803 if (r) { 6804 dev_err(adev->dev, "failed to init kgq\n"); 6805 return r; 6806 } 6807 6808 r = amdgpu_mes_map_legacy_queue(adev, ring); 6809 if (r) { 6810 dev_err(adev->dev, "failed to remap kgq\n"); 6811 return r; 6812 } 6813 6814 return amdgpu_ring_test_ring(ring); 6815 } 6816 6817 static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring) 6818 { 6819 6820 struct amdgpu_device *adev = ring->adev; 6821 uint32_t reset_pipe = 0, clean_pipe = 0; 6822 int r; 6823 6824 if (!gfx_v11_pipe_reset_support(adev)) 6825 return -EOPNOTSUPP; 6826 6827 gfx_v11_0_set_safe_mode(adev, 0); 6828 mutex_lock(&adev->srbm_mutex); 6829 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6830 6831 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 6832 clean_pipe = reset_pipe; 6833 6834 if (adev->gfx.rs64_enable) { 6835 6836 switch (ring->pipe) { 6837 case 0: 6838 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6839 MEC_PIPE0_RESET, 1); 6840 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6841 MEC_PIPE0_RESET, 0); 6842 break; 6843 case 1: 6844 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6845 MEC_PIPE1_RESET, 1); 6846 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6847 MEC_PIPE1_RESET, 0); 6848 break; 6849 case 2: 6850 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6851 MEC_PIPE2_RESET, 1); 6852 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6853 MEC_PIPE2_RESET, 0); 6854 break; 6855 case 3: 6856 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6857 MEC_PIPE3_RESET, 1); 6858 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6859 MEC_PIPE3_RESET, 0); 6860 break; 6861 default: 6862 break; 6863 } 6864 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 6865 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 6866 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 6867 RS64_FW_UC_START_ADDR_LO; 6868 } else { 6869 if (ring->me == 1) { 6870 switch (ring->pipe) { 6871 case 0: 6872 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6873 MEC_ME1_PIPE0_RESET, 1); 6874 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6875 MEC_ME1_PIPE0_RESET, 0); 6876 break; 6877 case 1: 6878 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6879 MEC_ME1_PIPE1_RESET, 1); 6880 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6881 MEC_ME1_PIPE1_RESET, 0); 6882 break; 6883 case 2: 6884 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6885 MEC_ME1_PIPE2_RESET, 1); 6886 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6887 MEC_ME1_PIPE2_RESET, 0); 6888 break; 6889 case 3: 6890 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6891 MEC_ME1_PIPE3_RESET, 1); 6892 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6893 MEC_ME1_PIPE3_RESET, 0); 6894 break; 6895 default: 6896 break; 6897 } 6898 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 6899 } else { 6900 switch (ring->pipe) { 6901 case 0: 6902 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6903 MEC_ME2_PIPE0_RESET, 1); 6904 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6905 MEC_ME2_PIPE0_RESET, 0); 6906 break; 6907 case 1: 6908 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6909 MEC_ME2_PIPE1_RESET, 1); 6910 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6911 MEC_ME2_PIPE1_RESET, 0); 6912 break; 6913 case 2: 6914 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6915 MEC_ME2_PIPE2_RESET, 1); 6916 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6917 MEC_ME2_PIPE2_RESET, 0); 6918 break; 6919 case 3: 6920 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6921 MEC_ME2_PIPE3_RESET, 1); 6922 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6923 MEC_ME2_PIPE3_RESET, 0); 6924 break; 6925 default: 6926 break; 6927 } 6928 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 6929 } 6930 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 6931 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 6932 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 6933 } 6934 6935 soc21_grbm_select(adev, 0, 0, 0, 0); 6936 mutex_unlock(&adev->srbm_mutex); 6937 gfx_v11_0_unset_safe_mode(adev, 0); 6938 6939 dev_info(adev->dev, "The ring %s pipe resets to MEC FW start PC: %s\n", ring->name, 6940 r == 0 ? "successfully" : "failed"); 6941 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 6942 * reset status relies on the compute ring test result. 6943 */ 6944 return 0; 6945 } 6946 6947 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 6948 { 6949 struct amdgpu_device *adev = ring->adev; 6950 int r = 0; 6951 6952 if (amdgpu_sriov_vf(adev)) 6953 return -EINVAL; 6954 6955 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 6956 if (r) { 6957 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 6958 r = gfx_v11_0_reset_compute_pipe(ring); 6959 if (r) 6960 return r; 6961 } 6962 6963 r = gfx_v11_0_kcq_init_queue(ring, true); 6964 if (r) { 6965 dev_err(adev->dev, "fail to init kcq\n"); 6966 return r; 6967 } 6968 r = amdgpu_mes_map_legacy_queue(adev, ring); 6969 if (r) { 6970 dev_err(adev->dev, "failed to remap kcq\n"); 6971 return r; 6972 } 6973 6974 return amdgpu_ring_test_ring(ring); 6975 } 6976 6977 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 6978 { 6979 struct amdgpu_device *adev = ip_block->adev; 6980 uint32_t i, j, k, reg, index = 0; 6981 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6982 6983 if (!adev->gfx.ip_dump_core) 6984 return; 6985 6986 for (i = 0; i < reg_count; i++) 6987 drm_printf(p, "%-50s \t 0x%08x\n", 6988 gc_reg_list_11_0[i].reg_name, 6989 adev->gfx.ip_dump_core[i]); 6990 6991 /* print compute queue registers for all instances */ 6992 if (!adev->gfx.ip_dump_compute_queues) 6993 return; 6994 6995 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6996 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6997 adev->gfx.mec.num_mec, 6998 adev->gfx.mec.num_pipe_per_mec, 6999 adev->gfx.mec.num_queue_per_pipe); 7000 7001 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7002 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7003 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7004 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 7005 for (reg = 0; reg < reg_count; reg++) { 7006 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 7007 drm_printf(p, "%-50s \t 0x%08x\n", 7008 "regCP_MEC_ME2_HEADER_DUMP", 7009 adev->gfx.ip_dump_compute_queues[index + reg]); 7010 else 7011 drm_printf(p, "%-50s \t 0x%08x\n", 7012 gc_cp_reg_list_11[reg].reg_name, 7013 adev->gfx.ip_dump_compute_queues[index + reg]); 7014 } 7015 index += reg_count; 7016 } 7017 } 7018 } 7019 7020 /* print gfx queue registers for all instances */ 7021 if (!adev->gfx.ip_dump_gfx_queues) 7022 return; 7023 7024 index = 0; 7025 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7026 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 7027 adev->gfx.me.num_me, 7028 adev->gfx.me.num_pipe_per_me, 7029 adev->gfx.me.num_queue_per_pipe); 7030 7031 for (i = 0; i < adev->gfx.me.num_me; i++) { 7032 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7033 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7034 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 7035 for (reg = 0; reg < reg_count; reg++) { 7036 drm_printf(p, "%-50s \t 0x%08x\n", 7037 gc_gfx_queue_reg_list_11[reg].reg_name, 7038 adev->gfx.ip_dump_gfx_queues[index + reg]); 7039 } 7040 index += reg_count; 7041 } 7042 } 7043 } 7044 } 7045 7046 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 7047 { 7048 struct amdgpu_device *adev = ip_block->adev; 7049 uint32_t i, j, k, reg, index = 0; 7050 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 7051 7052 if (!adev->gfx.ip_dump_core) 7053 return; 7054 7055 amdgpu_gfx_off_ctrl(adev, false); 7056 for (i = 0; i < reg_count; i++) 7057 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 7058 amdgpu_gfx_off_ctrl(adev, true); 7059 7060 /* dump compute queue registers for all instances */ 7061 if (!adev->gfx.ip_dump_compute_queues) 7062 return; 7063 7064 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 7065 amdgpu_gfx_off_ctrl(adev, false); 7066 mutex_lock(&adev->srbm_mutex); 7067 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7068 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7069 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7070 /* ME0 is for GFX so start from 1 for CP */ 7071 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 7072 for (reg = 0; reg < reg_count; reg++) { 7073 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 7074 adev->gfx.ip_dump_compute_queues[index + reg] = 7075 RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME2_HEADER_DUMP)); 7076 else 7077 adev->gfx.ip_dump_compute_queues[index + reg] = 7078 RREG32(SOC15_REG_ENTRY_OFFSET( 7079 gc_cp_reg_list_11[reg])); 7080 } 7081 index += reg_count; 7082 } 7083 } 7084 } 7085 soc21_grbm_select(adev, 0, 0, 0, 0); 7086 mutex_unlock(&adev->srbm_mutex); 7087 amdgpu_gfx_off_ctrl(adev, true); 7088 7089 /* dump gfx queue registers for all instances */ 7090 if (!adev->gfx.ip_dump_gfx_queues) 7091 return; 7092 7093 index = 0; 7094 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7095 amdgpu_gfx_off_ctrl(adev, false); 7096 mutex_lock(&adev->srbm_mutex); 7097 for (i = 0; i < adev->gfx.me.num_me; i++) { 7098 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7099 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7100 soc21_grbm_select(adev, i, j, k, 0); 7101 7102 for (reg = 0; reg < reg_count; reg++) { 7103 adev->gfx.ip_dump_gfx_queues[index + reg] = 7104 RREG32(SOC15_REG_ENTRY_OFFSET( 7105 gc_gfx_queue_reg_list_11[reg])); 7106 } 7107 index += reg_count; 7108 } 7109 } 7110 } 7111 soc21_grbm_select(adev, 0, 0, 0, 0); 7112 mutex_unlock(&adev->srbm_mutex); 7113 amdgpu_gfx_off_ctrl(adev, true); 7114 } 7115 7116 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 7117 { 7118 /* Emit the cleaner shader */ 7119 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 7120 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 7121 } 7122 7123 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 7124 { 7125 amdgpu_gfx_profile_ring_begin_use(ring); 7126 7127 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 7128 } 7129 7130 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 7131 { 7132 amdgpu_gfx_profile_ring_end_use(ring); 7133 7134 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 7135 } 7136 7137 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 7138 .name = "gfx_v11_0", 7139 .early_init = gfx_v11_0_early_init, 7140 .late_init = gfx_v11_0_late_init, 7141 .sw_init = gfx_v11_0_sw_init, 7142 .sw_fini = gfx_v11_0_sw_fini, 7143 .hw_init = gfx_v11_0_hw_init, 7144 .hw_fini = gfx_v11_0_hw_fini, 7145 .suspend = gfx_v11_0_suspend, 7146 .resume = gfx_v11_0_resume, 7147 .is_idle = gfx_v11_0_is_idle, 7148 .wait_for_idle = gfx_v11_0_wait_for_idle, 7149 .soft_reset = gfx_v11_0_soft_reset, 7150 .check_soft_reset = gfx_v11_0_check_soft_reset, 7151 .post_soft_reset = gfx_v11_0_post_soft_reset, 7152 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 7153 .set_powergating_state = gfx_v11_0_set_powergating_state, 7154 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 7155 .dump_ip_state = gfx_v11_ip_dump, 7156 .print_ip_state = gfx_v11_ip_print, 7157 }; 7158 7159 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 7160 .type = AMDGPU_RING_TYPE_GFX, 7161 .align_mask = 0xff, 7162 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7163 .support_64bit_ptrs = true, 7164 .secure_submission_supported = true, 7165 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 7166 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 7167 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 7168 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 7169 5 + /* update_spm_vmid */ 7170 5 + /* COND_EXEC */ 7171 22 + /* SET_Q_PREEMPTION_MODE */ 7172 7 + /* PIPELINE_SYNC */ 7173 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7174 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7175 4 + /* VM_FLUSH */ 7176 8 + /* FENCE for VM_FLUSH */ 7177 20 + /* GDS switch */ 7178 5 + /* COND_EXEC */ 7179 7 + /* HDP_flush */ 7180 4 + /* VGT_flush */ 7181 31 + /* DE_META */ 7182 3 + /* CNTX_CTRL */ 7183 5 + /* HDP_INVL */ 7184 22 + /* SET_Q_PREEMPTION_MODE */ 7185 8 + 8 + /* FENCE x2 */ 7186 8 + /* gfx_v11_0_emit_mem_sync */ 7187 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7188 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 7189 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 7190 .emit_fence = gfx_v11_0_ring_emit_fence, 7191 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7192 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7193 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7194 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7195 .test_ring = gfx_v11_0_ring_test_ring, 7196 .test_ib = gfx_v11_0_ring_test_ib, 7197 .insert_nop = gfx_v11_ring_insert_nop, 7198 .pad_ib = amdgpu_ring_generic_pad_ib, 7199 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 7200 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 7201 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 7202 .preempt_ib = gfx_v11_0_ring_preempt_ib, 7203 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 7204 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7205 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7206 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7207 .soft_recovery = gfx_v11_0_ring_soft_recovery, 7208 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7209 .reset = gfx_v11_0_reset_kgq, 7210 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7211 .begin_use = gfx_v11_0_ring_begin_use, 7212 .end_use = gfx_v11_0_ring_end_use, 7213 }; 7214 7215 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 7216 .type = AMDGPU_RING_TYPE_COMPUTE, 7217 .align_mask = 0xff, 7218 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7219 .support_64bit_ptrs = true, 7220 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7221 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7222 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7223 .emit_frame_size = 7224 5 + /* update_spm_vmid */ 7225 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7226 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7227 5 + /* hdp invalidate */ 7228 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7229 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7230 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7231 2 + /* gfx_v11_0_ring_emit_vm_flush */ 7232 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 7233 8 + /* gfx_v11_0_emit_mem_sync */ 7234 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7235 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7236 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7237 .emit_fence = gfx_v11_0_ring_emit_fence, 7238 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7239 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7240 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7241 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7242 .test_ring = gfx_v11_0_ring_test_ring, 7243 .test_ib = gfx_v11_0_ring_test_ib, 7244 .insert_nop = gfx_v11_ring_insert_nop, 7245 .pad_ib = amdgpu_ring_generic_pad_ib, 7246 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7247 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7248 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7249 .soft_recovery = gfx_v11_0_ring_soft_recovery, 7250 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7251 .reset = gfx_v11_0_reset_kcq, 7252 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7253 .begin_use = gfx_v11_0_ring_begin_use, 7254 .end_use = gfx_v11_0_ring_end_use, 7255 }; 7256 7257 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 7258 .type = AMDGPU_RING_TYPE_KIQ, 7259 .align_mask = 0xff, 7260 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7261 .support_64bit_ptrs = true, 7262 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7263 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7264 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7265 .emit_frame_size = 7266 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7267 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7268 5 + /*hdp invalidate */ 7269 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7270 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7271 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7272 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7273 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7274 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7275 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 7276 .test_ring = gfx_v11_0_ring_test_ring, 7277 .test_ib = gfx_v11_0_ring_test_ib, 7278 .insert_nop = amdgpu_ring_insert_nop, 7279 .pad_ib = amdgpu_ring_generic_pad_ib, 7280 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7281 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7282 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7283 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7284 }; 7285 7286 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7287 { 7288 int i; 7289 7290 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7291 7292 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7293 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7294 7295 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7296 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7297 } 7298 7299 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7300 .set = gfx_v11_0_set_eop_interrupt_state, 7301 .process = gfx_v11_0_eop_irq, 7302 }; 7303 7304 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7305 .set = gfx_v11_0_set_priv_reg_fault_state, 7306 .process = gfx_v11_0_priv_reg_irq, 7307 }; 7308 7309 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7310 .set = gfx_v11_0_set_bad_op_fault_state, 7311 .process = gfx_v11_0_bad_op_irq, 7312 }; 7313 7314 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7315 .set = gfx_v11_0_set_priv_inst_fault_state, 7316 .process = gfx_v11_0_priv_inst_irq, 7317 }; 7318 7319 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7320 .process = gfx_v11_0_rlc_gc_fed_irq, 7321 }; 7322 7323 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7324 { 7325 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7326 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7327 7328 adev->gfx.priv_reg_irq.num_types = 1; 7329 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7330 7331 adev->gfx.bad_op_irq.num_types = 1; 7332 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7333 7334 adev->gfx.priv_inst_irq.num_types = 1; 7335 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7336 7337 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7338 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7339 7340 } 7341 7342 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7343 { 7344 if (adev->flags & AMD_IS_APU) 7345 adev->gfx.imu.mode = MISSION_MODE; 7346 else 7347 adev->gfx.imu.mode = DEBUG_MODE; 7348 7349 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7350 } 7351 7352 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7353 { 7354 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7355 } 7356 7357 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7358 { 7359 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7360 adev->gfx.config.max_sh_per_se * 7361 adev->gfx.config.max_shader_engines; 7362 7363 adev->gds.gds_size = 0x1000; 7364 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7365 adev->gds.gws_size = 64; 7366 adev->gds.oa_size = 16; 7367 } 7368 7369 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7370 { 7371 /* set gfx eng mqd */ 7372 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7373 sizeof(struct v11_gfx_mqd); 7374 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7375 gfx_v11_0_gfx_mqd_init; 7376 /* set compute eng mqd */ 7377 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7378 sizeof(struct v11_compute_mqd); 7379 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7380 gfx_v11_0_compute_mqd_init; 7381 } 7382 7383 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7384 u32 bitmap) 7385 { 7386 u32 data; 7387 7388 if (!bitmap) 7389 return; 7390 7391 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7392 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7393 7394 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7395 } 7396 7397 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7398 { 7399 u32 data, wgp_bitmask; 7400 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7401 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7402 7403 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7404 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7405 7406 wgp_bitmask = 7407 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7408 7409 return (~data) & wgp_bitmask; 7410 } 7411 7412 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7413 { 7414 u32 wgp_idx, wgp_active_bitmap; 7415 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7416 7417 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7418 cu_active_bitmap = 0; 7419 7420 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7421 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7422 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7423 if (wgp_active_bitmap & (1 << wgp_idx)) 7424 cu_active_bitmap |= cu_bitmap_per_wgp; 7425 } 7426 7427 return cu_active_bitmap; 7428 } 7429 7430 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7431 struct amdgpu_cu_info *cu_info) 7432 { 7433 int i, j, k, counter, active_cu_number = 0; 7434 u32 mask, bitmap; 7435 unsigned disable_masks[8 * 2]; 7436 7437 if (!adev || !cu_info) 7438 return -EINVAL; 7439 7440 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 7441 7442 mutex_lock(&adev->grbm_idx_mutex); 7443 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7444 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7445 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7446 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7447 continue; 7448 mask = 1; 7449 counter = 0; 7450 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7451 if (i < 8 && j < 2) 7452 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7453 adev, disable_masks[i * 2 + j]); 7454 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7455 7456 /** 7457 * GFX11 could support more than 4 SEs, while the bitmap 7458 * in cu_info struct is 4x4 and ioctl interface struct 7459 * drm_amdgpu_info_device should keep stable. 7460 * So we use last two columns of bitmap to store cu mask for 7461 * SEs 4 to 7, the layout of the bitmap is as below: 7462 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7463 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7464 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7465 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7466 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7467 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7468 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7469 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7470 */ 7471 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7472 7473 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7474 if (bitmap & mask) 7475 counter++; 7476 7477 mask <<= 1; 7478 } 7479 active_cu_number += counter; 7480 } 7481 } 7482 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7483 mutex_unlock(&adev->grbm_idx_mutex); 7484 7485 cu_info->number = active_cu_number; 7486 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7487 7488 return 0; 7489 } 7490 7491 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7492 { 7493 .type = AMD_IP_BLOCK_TYPE_GFX, 7494 .major = 11, 7495 .minor = 0, 7496 .rev = 0, 7497 .funcs = &gfx_v11_0_ip_funcs, 7498 }; 7499