1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v11_0.h" 33 #include "soc21.h" 34 #include "nvd.h" 35 36 #include "gc/gc_11_0_0_offset.h" 37 #include "gc/gc_11_0_0_sh_mask.h" 38 #include "smuio/smuio_13_0_6_offset.h" 39 #include "smuio/smuio_13_0_6_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx11.h" 45 #include "v11_structs.h" 46 #include "gfx_v11_0.h" 47 #include "gfx_v11_0_cleaner_shader.h" 48 #include "gfx_v11_0_3.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 #include "mes_userqueue.h" 52 #include "amdgpu_userq_fence.h" 53 54 #define GFX11_NUM_GFX_RINGS 1 55 #define GFX11_MEC_HPD_SIZE 2048 56 57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 59 60 #define regCGTT_WD_CLK_CTRL 0x5086 61 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 63 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 64 #define regPC_CONFIG_CNTL_1 0x194d 65 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 66 67 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 68 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 69 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 70 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 71 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 72 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 73 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 74 75 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 76 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 77 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 78 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 79 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 80 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 81 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 82 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 83 84 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_kicker.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 104 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 105 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 106 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 107 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 108 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 109 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 110 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 111 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 112 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 113 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 114 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 115 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 116 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 117 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 118 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 119 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 120 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 121 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 122 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 123 124 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 125 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 127 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 158 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 159 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 160 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 161 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 162 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 163 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 164 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 165 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 166 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 167 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 168 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 169 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 170 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 171 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 172 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 182 /* cp header registers */ 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 191 /* SE status registers */ 192 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 193 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 194 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 195 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 196 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 197 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 198 }; 199 200 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 201 /* compute registers */ 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 241 /* cp header registers */ 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 }; 251 252 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 253 /* gfx queue registers */ 254 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 255 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 256 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 257 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 258 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 259 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 260 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 261 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 262 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 263 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 264 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 265 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 266 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 267 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 268 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 269 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 270 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 271 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 272 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 273 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 274 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 275 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 276 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 277 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 278 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 279 /* cp header registers */ 280 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 281 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 282 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 283 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 284 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 285 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 286 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 287 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 288 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 289 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 290 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 291 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 292 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 293 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 294 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 295 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 296 }; 297 298 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 299 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 300 }; 301 302 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 303 { 304 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 313 }; 314 315 #define DEFAULT_SH_MEM_CONFIG \ 316 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 317 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 318 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 319 320 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 321 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 322 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 323 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 324 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 325 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 326 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 327 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 328 struct amdgpu_cu_info *cu_info); 329 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 330 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 331 u32 sh_num, u32 instance, int xcc_id); 332 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 333 334 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 335 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 336 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 337 uint32_t val); 338 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 339 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 340 uint16_t pasid, uint32_t flush_type, 341 bool all_hub, uint8_t dst_sel); 342 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 343 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 344 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 345 bool enable); 346 347 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 348 { 349 struct amdgpu_device *adev = kiq_ring->adev; 350 u64 shader_mc_addr; 351 352 /* Cleaner shader MC address */ 353 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 354 355 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 356 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 357 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 358 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 359 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 360 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 361 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 362 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 363 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 364 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 365 } 366 367 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 368 struct amdgpu_ring *ring) 369 { 370 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 371 uint64_t wptr_addr = ring->wptr_gpu_addr; 372 uint32_t me = 0, eng_sel = 0; 373 374 switch (ring->funcs->type) { 375 case AMDGPU_RING_TYPE_COMPUTE: 376 me = 1; 377 eng_sel = 0; 378 break; 379 case AMDGPU_RING_TYPE_GFX: 380 me = 0; 381 eng_sel = 4; 382 break; 383 case AMDGPU_RING_TYPE_MES: 384 me = 2; 385 eng_sel = 5; 386 break; 387 default: 388 WARN_ON(1); 389 } 390 391 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 392 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 394 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 395 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 396 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 397 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 398 PACKET3_MAP_QUEUES_ME((me)) | 399 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 400 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 401 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 402 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 403 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 404 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 405 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 406 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 407 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 408 } 409 410 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 411 struct amdgpu_ring *ring, 412 enum amdgpu_unmap_queues_action action, 413 u64 gpu_addr, u64 seq) 414 { 415 struct amdgpu_device *adev = kiq_ring->adev; 416 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 417 418 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 419 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 420 return; 421 } 422 423 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 424 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 425 PACKET3_UNMAP_QUEUES_ACTION(action) | 426 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 427 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 428 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 429 amdgpu_ring_write(kiq_ring, 430 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 431 432 if (action == PREEMPT_QUEUES_NO_UNMAP) { 433 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 434 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 435 amdgpu_ring_write(kiq_ring, seq); 436 } else { 437 amdgpu_ring_write(kiq_ring, 0); 438 amdgpu_ring_write(kiq_ring, 0); 439 amdgpu_ring_write(kiq_ring, 0); 440 } 441 } 442 443 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 444 struct amdgpu_ring *ring, 445 u64 addr, 446 u64 seq) 447 { 448 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 449 450 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 451 amdgpu_ring_write(kiq_ring, 452 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 453 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 454 PACKET3_QUERY_STATUS_COMMAND(2)); 455 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 456 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 457 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 458 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 459 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 460 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 461 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 462 } 463 464 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 465 uint16_t pasid, uint32_t flush_type, 466 bool all_hub) 467 { 468 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 469 } 470 471 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 472 .kiq_set_resources = gfx11_kiq_set_resources, 473 .kiq_map_queues = gfx11_kiq_map_queues, 474 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 475 .kiq_query_status = gfx11_kiq_query_status, 476 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 477 .set_resources_size = 8, 478 .map_queues_size = 7, 479 .unmap_queues_size = 6, 480 .query_status_size = 7, 481 .invalidate_tlbs_size = 2, 482 }; 483 484 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 485 { 486 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 487 } 488 489 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 490 { 491 if (amdgpu_sriov_vf(adev)) 492 return; 493 494 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 495 case IP_VERSION(11, 0, 1): 496 case IP_VERSION(11, 0, 4): 497 soc15_program_register_sequence(adev, 498 golden_settings_gc_11_0_1, 499 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 500 break; 501 default: 502 break; 503 } 504 soc15_program_register_sequence(adev, 505 golden_settings_gc_11_0, 506 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 507 508 } 509 510 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 511 bool wc, uint32_t reg, uint32_t val) 512 { 513 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 514 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 515 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 516 amdgpu_ring_write(ring, reg); 517 amdgpu_ring_write(ring, 0); 518 amdgpu_ring_write(ring, val); 519 } 520 521 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 522 int mem_space, int opt, uint32_t addr0, 523 uint32_t addr1, uint32_t ref, uint32_t mask, 524 uint32_t inv) 525 { 526 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 527 amdgpu_ring_write(ring, 528 /* memory (1) or register (0) */ 529 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 530 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 531 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 532 WAIT_REG_MEM_ENGINE(eng_sel))); 533 534 if (mem_space) 535 BUG_ON(addr0 & 0x3); /* Dword align */ 536 amdgpu_ring_write(ring, addr0); 537 amdgpu_ring_write(ring, addr1); 538 amdgpu_ring_write(ring, ref); 539 amdgpu_ring_write(ring, mask); 540 amdgpu_ring_write(ring, inv); /* poll interval */ 541 } 542 543 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 544 { 545 /* Header itself is a NOP packet */ 546 if (num_nop == 1) { 547 amdgpu_ring_write(ring, ring->funcs->nop); 548 return; 549 } 550 551 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 552 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 553 554 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 555 amdgpu_ring_insert_nop(ring, num_nop - 1); 556 } 557 558 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 559 { 560 struct amdgpu_device *adev = ring->adev; 561 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 562 uint32_t tmp = 0; 563 unsigned i; 564 int r; 565 566 WREG32(scratch, 0xCAFEDEAD); 567 r = amdgpu_ring_alloc(ring, 5); 568 if (r) { 569 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 570 ring->idx, r); 571 return r; 572 } 573 574 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 575 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 576 } else { 577 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 578 amdgpu_ring_write(ring, scratch - 579 PACKET3_SET_UCONFIG_REG_START); 580 amdgpu_ring_write(ring, 0xDEADBEEF); 581 } 582 amdgpu_ring_commit(ring); 583 584 for (i = 0; i < adev->usec_timeout; i++) { 585 tmp = RREG32(scratch); 586 if (tmp == 0xDEADBEEF) 587 break; 588 if (amdgpu_emu_mode == 1) 589 msleep(1); 590 else 591 udelay(1); 592 } 593 594 if (i >= adev->usec_timeout) 595 r = -ETIMEDOUT; 596 return r; 597 } 598 599 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 600 { 601 struct amdgpu_device *adev = ring->adev; 602 struct amdgpu_ib ib; 603 struct dma_fence *f = NULL; 604 unsigned index; 605 uint64_t gpu_addr; 606 uint32_t *cpu_ptr; 607 long r; 608 609 /* MES KIQ fw hasn't indirect buffer support for now */ 610 if (adev->enable_mes_kiq && 611 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 612 return 0; 613 614 memset(&ib, 0, sizeof(ib)); 615 616 r = amdgpu_device_wb_get(adev, &index); 617 if (r) 618 return r; 619 620 gpu_addr = adev->wb.gpu_addr + (index * 4); 621 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 622 cpu_ptr = &adev->wb.wb[index]; 623 624 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 625 if (r) { 626 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 627 goto err1; 628 } 629 630 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 631 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 632 ib.ptr[2] = lower_32_bits(gpu_addr); 633 ib.ptr[3] = upper_32_bits(gpu_addr); 634 ib.ptr[4] = 0xDEADBEEF; 635 ib.length_dw = 5; 636 637 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 638 if (r) 639 goto err2; 640 641 r = dma_fence_wait_timeout(f, false, timeout); 642 if (r == 0) { 643 r = -ETIMEDOUT; 644 goto err2; 645 } else if (r < 0) { 646 goto err2; 647 } 648 649 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 650 r = 0; 651 else 652 r = -EINVAL; 653 err2: 654 amdgpu_ib_free(&ib, NULL); 655 dma_fence_put(f); 656 err1: 657 amdgpu_device_wb_free(adev, index); 658 return r; 659 } 660 661 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 662 { 663 amdgpu_ucode_release(&adev->gfx.pfp_fw); 664 amdgpu_ucode_release(&adev->gfx.me_fw); 665 amdgpu_ucode_release(&adev->gfx.rlc_fw); 666 amdgpu_ucode_release(&adev->gfx.mec_fw); 667 668 kfree(adev->gfx.rlc.register_list_format); 669 } 670 671 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 672 { 673 const struct psp_firmware_header_v1_0 *toc_hdr; 674 int err = 0; 675 676 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 677 AMDGPU_UCODE_REQUIRED, 678 "amdgpu/%s_toc.bin", ucode_prefix); 679 if (err) 680 goto out; 681 682 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 683 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 684 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 685 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 686 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 687 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 688 return 0; 689 out: 690 amdgpu_ucode_release(&adev->psp.toc_fw); 691 return err; 692 } 693 694 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 695 { 696 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 697 case IP_VERSION(11, 0, 0): 698 case IP_VERSION(11, 0, 2): 699 case IP_VERSION(11, 0, 3): 700 if ((adev->gfx.me_fw_version >= 1505) && 701 (adev->gfx.pfp_fw_version >= 1600) && 702 (adev->gfx.mec_fw_version >= 512)) { 703 if (amdgpu_sriov_vf(adev)) 704 adev->gfx.cp_gfx_shadow = true; 705 else 706 adev->gfx.cp_gfx_shadow = false; 707 } 708 break; 709 default: 710 adev->gfx.cp_gfx_shadow = false; 711 break; 712 } 713 } 714 715 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 716 { 717 char ucode_prefix[25]; 718 int err; 719 const struct rlc_firmware_header_v2_0 *rlc_hdr; 720 uint16_t version_major; 721 uint16_t version_minor; 722 723 DRM_DEBUG("\n"); 724 725 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 726 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 727 AMDGPU_UCODE_REQUIRED, 728 "amdgpu/%s_pfp.bin", ucode_prefix); 729 if (err) 730 goto out; 731 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 732 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 733 (union amdgpu_firmware_header *) 734 adev->gfx.pfp_fw->data, 2, 0); 735 if (adev->gfx.rs64_enable) { 736 dev_info(adev->dev, "CP RS64 enable\n"); 737 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 738 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 739 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 740 } else { 741 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 742 } 743 744 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 745 AMDGPU_UCODE_REQUIRED, 746 "amdgpu/%s_me.bin", ucode_prefix); 747 if (err) 748 goto out; 749 if (adev->gfx.rs64_enable) { 750 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 751 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 752 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 753 } else { 754 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 755 } 756 757 if (!amdgpu_sriov_vf(adev)) { 758 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 759 adev->pdev->revision == 0xCE) 760 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 761 AMDGPU_UCODE_REQUIRED, 762 "amdgpu/gc_11_0_0_rlc_1.bin"); 763 else if (amdgpu_is_kicker_fw(adev)) 764 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 765 AMDGPU_UCODE_REQUIRED, 766 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 767 else 768 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 769 AMDGPU_UCODE_REQUIRED, 770 "amdgpu/%s_rlc.bin", ucode_prefix); 771 if (err) 772 goto out; 773 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 774 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 775 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 776 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 777 if (err) 778 goto out; 779 } 780 781 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 782 AMDGPU_UCODE_REQUIRED, 783 "amdgpu/%s_mec.bin", ucode_prefix); 784 if (err) 785 goto out; 786 if (adev->gfx.rs64_enable) { 787 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 788 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 789 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 790 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 791 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 792 } else { 793 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 794 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 795 } 796 797 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 798 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 799 800 /* only one MEC for gfx 11.0.0. */ 801 adev->gfx.mec2_fw = NULL; 802 803 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 804 805 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 806 err = adev->gfx.imu.funcs->init_microcode(adev); 807 if (err) 808 DRM_ERROR("Failed to init imu firmware!\n"); 809 return err; 810 } 811 812 out: 813 if (err) { 814 amdgpu_ucode_release(&adev->gfx.pfp_fw); 815 amdgpu_ucode_release(&adev->gfx.me_fw); 816 amdgpu_ucode_release(&adev->gfx.rlc_fw); 817 amdgpu_ucode_release(&adev->gfx.mec_fw); 818 } 819 820 return err; 821 } 822 823 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 824 { 825 u32 count = 0; 826 const struct cs_section_def *sect = NULL; 827 const struct cs_extent_def *ext = NULL; 828 829 /* begin clear state */ 830 count += 2; 831 /* context control state */ 832 count += 3; 833 834 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 835 for (ext = sect->section; ext->extent != NULL; ++ext) { 836 if (sect->id == SECT_CONTEXT) 837 count += 2 + ext->reg_count; 838 else 839 return 0; 840 } 841 } 842 843 /* set PA_SC_TILE_STEERING_OVERRIDE */ 844 count += 3; 845 /* end clear state */ 846 count += 2; 847 /* clear state */ 848 count += 2; 849 850 return count; 851 } 852 853 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 854 { 855 u32 count = 0; 856 int ctx_reg_offset; 857 858 if (adev->gfx.rlc.cs_data == NULL) 859 return; 860 if (buffer == NULL) 861 return; 862 863 count = amdgpu_gfx_csb_preamble_start(buffer); 864 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 865 866 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 867 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 868 buffer[count++] = cpu_to_le32(ctx_reg_offset); 869 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 870 871 amdgpu_gfx_csb_preamble_end(buffer, count); 872 } 873 874 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 875 { 876 /* clear state block */ 877 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 878 &adev->gfx.rlc.clear_state_gpu_addr, 879 (void **)&adev->gfx.rlc.cs_ptr); 880 881 /* jump table block */ 882 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 883 &adev->gfx.rlc.cp_table_gpu_addr, 884 (void **)&adev->gfx.rlc.cp_table_ptr); 885 } 886 887 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 888 { 889 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 890 891 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 892 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 893 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 894 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 895 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 896 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 897 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 898 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 899 adev->gfx.rlc.rlcg_reg_access_supported = true; 900 } 901 902 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 903 { 904 const struct cs_section_def *cs_data; 905 int r; 906 907 adev->gfx.rlc.cs_data = gfx11_cs_data; 908 909 cs_data = adev->gfx.rlc.cs_data; 910 911 if (cs_data) { 912 /* init clear state block */ 913 r = amdgpu_gfx_rlc_init_csb(adev); 914 if (r) 915 return r; 916 } 917 918 /* init spm vmid with 0xf */ 919 if (adev->gfx.rlc.funcs->update_spm_vmid) 920 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 921 922 return 0; 923 } 924 925 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 926 { 927 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 928 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 929 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 930 } 931 932 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 933 { 934 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 935 936 amdgpu_gfx_graphics_queue_acquire(adev); 937 } 938 939 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 940 { 941 int r; 942 u32 *hpd; 943 size_t mec_hpd_size; 944 945 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 946 947 /* take ownership of the relevant compute queues */ 948 amdgpu_gfx_compute_queue_acquire(adev); 949 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 950 951 if (mec_hpd_size) { 952 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 953 AMDGPU_GEM_DOMAIN_GTT, 954 &adev->gfx.mec.hpd_eop_obj, 955 &adev->gfx.mec.hpd_eop_gpu_addr, 956 (void **)&hpd); 957 if (r) { 958 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 959 gfx_v11_0_mec_fini(adev); 960 return r; 961 } 962 963 memset(hpd, 0, mec_hpd_size); 964 965 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 966 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 967 } 968 969 return 0; 970 } 971 972 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 973 { 974 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 975 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 976 (address << SQ_IND_INDEX__INDEX__SHIFT)); 977 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 978 } 979 980 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 981 uint32_t thread, uint32_t regno, 982 uint32_t num, uint32_t *out) 983 { 984 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 985 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 986 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 987 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 988 (SQ_IND_INDEX__AUTO_INCR_MASK)); 989 while (num--) 990 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 991 } 992 993 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 994 { 995 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 996 * field when performing a select_se_sh so it should be 997 * zero here */ 998 WARN_ON(simd != 0); 999 1000 /* type 3 wave data */ 1001 dst[(*no_fields)++] = 3; 1002 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1003 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1004 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1005 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1006 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1007 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1008 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1009 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1010 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1011 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1012 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1013 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1014 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1015 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1016 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1017 } 1018 1019 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1020 uint32_t wave, uint32_t start, 1021 uint32_t size, uint32_t *dst) 1022 { 1023 WARN_ON(simd != 0); 1024 1025 wave_read_regs( 1026 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1027 dst); 1028 } 1029 1030 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1031 uint32_t wave, uint32_t thread, 1032 uint32_t start, uint32_t size, 1033 uint32_t *dst) 1034 { 1035 wave_read_regs( 1036 adev, wave, thread, 1037 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1038 } 1039 1040 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1041 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1042 { 1043 soc21_grbm_select(adev, me, pipe, q, vm); 1044 } 1045 1046 /* all sizes are in bytes */ 1047 #define MQD_SHADOW_BASE_SIZE 73728 1048 #define MQD_SHADOW_BASE_ALIGNMENT 256 1049 #define MQD_FWWORKAREA_SIZE 484 1050 #define MQD_FWWORKAREA_ALIGNMENT 256 1051 1052 static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 1053 struct amdgpu_gfx_shadow_info *shadow_info) 1054 { 1055 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1056 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1057 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1058 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1059 } 1060 1061 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1062 struct amdgpu_gfx_shadow_info *shadow_info, 1063 bool skip_check) 1064 { 1065 if (adev->gfx.cp_gfx_shadow || skip_check) { 1066 gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 1067 return 0; 1068 } else { 1069 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1070 return -ENOTSUPP; 1071 } 1072 } 1073 1074 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1075 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1076 .select_se_sh = &gfx_v11_0_select_se_sh, 1077 .read_wave_data = &gfx_v11_0_read_wave_data, 1078 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1079 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1080 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1081 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1082 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1083 }; 1084 1085 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1086 { 1087 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1088 case IP_VERSION(11, 0, 0): 1089 case IP_VERSION(11, 0, 2): 1090 adev->gfx.config.max_hw_contexts = 8; 1091 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1092 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1093 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1094 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1095 break; 1096 case IP_VERSION(11, 0, 3): 1097 adev->gfx.ras = &gfx_v11_0_3_ras; 1098 adev->gfx.config.max_hw_contexts = 8; 1099 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1100 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1101 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1102 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1103 break; 1104 case IP_VERSION(11, 0, 1): 1105 case IP_VERSION(11, 0, 4): 1106 case IP_VERSION(11, 5, 0): 1107 case IP_VERSION(11, 5, 1): 1108 case IP_VERSION(11, 5, 2): 1109 case IP_VERSION(11, 5, 3): 1110 adev->gfx.config.max_hw_contexts = 8; 1111 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1112 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1113 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1114 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1115 break; 1116 default: 1117 BUG(); 1118 break; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1125 int me, int pipe, int queue) 1126 { 1127 struct amdgpu_ring *ring; 1128 unsigned int irq_type; 1129 unsigned int hw_prio; 1130 1131 ring = &adev->gfx.gfx_ring[ring_id]; 1132 1133 ring->me = me; 1134 ring->pipe = pipe; 1135 ring->queue = queue; 1136 1137 ring->ring_obj = NULL; 1138 ring->use_doorbell = true; 1139 if (adev->gfx.disable_kq) { 1140 ring->no_scheduler = true; 1141 ring->no_user_submission = true; 1142 } 1143 1144 if (!ring_id) 1145 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1146 else 1147 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1148 ring->vm_hub = AMDGPU_GFXHUB(0); 1149 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1150 1151 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1152 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1153 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1154 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1155 hw_prio, NULL); 1156 } 1157 1158 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1159 int mec, int pipe, int queue) 1160 { 1161 int r; 1162 unsigned irq_type; 1163 struct amdgpu_ring *ring; 1164 unsigned int hw_prio; 1165 1166 ring = &adev->gfx.compute_ring[ring_id]; 1167 1168 /* mec0 is me1 */ 1169 ring->me = mec + 1; 1170 ring->pipe = pipe; 1171 ring->queue = queue; 1172 1173 ring->ring_obj = NULL; 1174 ring->use_doorbell = true; 1175 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1176 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1177 + (ring_id * GFX11_MEC_HPD_SIZE); 1178 ring->vm_hub = AMDGPU_GFXHUB(0); 1179 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1180 1181 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1182 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1183 + ring->pipe; 1184 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1185 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1186 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1187 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1188 hw_prio, NULL); 1189 if (r) 1190 return r; 1191 1192 return 0; 1193 } 1194 1195 static struct { 1196 SOC21_FIRMWARE_ID id; 1197 unsigned int offset; 1198 unsigned int size; 1199 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1200 1201 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1202 { 1203 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1204 1205 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1206 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1207 rlc_autoload_info[ucode->id].id = ucode->id; 1208 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1209 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1210 1211 ucode++; 1212 } 1213 } 1214 1215 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1216 { 1217 uint32_t total_size = 0; 1218 SOC21_FIRMWARE_ID id; 1219 1220 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1221 1222 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1223 total_size += rlc_autoload_info[id].size; 1224 1225 /* In case the offset in rlc toc ucode is aligned */ 1226 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1227 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1228 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1229 1230 return total_size; 1231 } 1232 1233 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1234 { 1235 int r; 1236 uint32_t total_size; 1237 1238 total_size = gfx_v11_0_calc_toc_total_size(adev); 1239 1240 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1241 AMDGPU_GEM_DOMAIN_VRAM | 1242 AMDGPU_GEM_DOMAIN_GTT, 1243 &adev->gfx.rlc.rlc_autoload_bo, 1244 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1245 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1246 1247 if (r) { 1248 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1249 return r; 1250 } 1251 1252 return 0; 1253 } 1254 1255 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1256 SOC21_FIRMWARE_ID id, 1257 const void *fw_data, 1258 uint32_t fw_size, 1259 uint32_t *fw_autoload_mask) 1260 { 1261 uint32_t toc_offset; 1262 uint32_t toc_fw_size; 1263 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1264 1265 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1266 return; 1267 1268 toc_offset = rlc_autoload_info[id].offset; 1269 toc_fw_size = rlc_autoload_info[id].size; 1270 1271 if (fw_size == 0) 1272 fw_size = toc_fw_size; 1273 1274 if (fw_size > toc_fw_size) 1275 fw_size = toc_fw_size; 1276 1277 memcpy(ptr + toc_offset, fw_data, fw_size); 1278 1279 if (fw_size < toc_fw_size) 1280 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1281 1282 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1283 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1284 } 1285 1286 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1287 uint32_t *fw_autoload_mask) 1288 { 1289 void *data; 1290 uint32_t size; 1291 uint64_t *toc_ptr; 1292 1293 *(uint64_t *)fw_autoload_mask |= 0x1; 1294 1295 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1296 1297 data = adev->psp.toc.start_addr; 1298 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1299 1300 toc_ptr = (uint64_t *)data + size / 8 - 1; 1301 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1302 1303 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1304 data, size, fw_autoload_mask); 1305 } 1306 1307 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1308 uint32_t *fw_autoload_mask) 1309 { 1310 const __le32 *fw_data; 1311 uint32_t fw_size; 1312 const struct gfx_firmware_header_v1_0 *cp_hdr; 1313 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1314 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1315 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1316 uint16_t version_major, version_minor; 1317 1318 if (adev->gfx.rs64_enable) { 1319 /* pfp ucode */ 1320 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1321 adev->gfx.pfp_fw->data; 1322 /* instruction */ 1323 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1324 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1325 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1326 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1327 fw_data, fw_size, fw_autoload_mask); 1328 /* data */ 1329 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1330 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1331 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1332 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1333 fw_data, fw_size, fw_autoload_mask); 1334 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1335 fw_data, fw_size, fw_autoload_mask); 1336 /* me ucode */ 1337 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1338 adev->gfx.me_fw->data; 1339 /* instruction */ 1340 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1341 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1342 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1343 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1344 fw_data, fw_size, fw_autoload_mask); 1345 /* data */ 1346 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1347 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1348 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1349 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1350 fw_data, fw_size, fw_autoload_mask); 1351 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1352 fw_data, fw_size, fw_autoload_mask); 1353 /* mec ucode */ 1354 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1355 adev->gfx.mec_fw->data; 1356 /* instruction */ 1357 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1358 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1359 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1360 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1361 fw_data, fw_size, fw_autoload_mask); 1362 /* data */ 1363 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1364 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1365 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1366 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1367 fw_data, fw_size, fw_autoload_mask); 1368 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1369 fw_data, fw_size, fw_autoload_mask); 1370 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1371 fw_data, fw_size, fw_autoload_mask); 1372 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1373 fw_data, fw_size, fw_autoload_mask); 1374 } else { 1375 /* pfp ucode */ 1376 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1377 adev->gfx.pfp_fw->data; 1378 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1379 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1380 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1381 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1382 fw_data, fw_size, fw_autoload_mask); 1383 1384 /* me ucode */ 1385 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1386 adev->gfx.me_fw->data; 1387 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1388 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1389 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1391 fw_data, fw_size, fw_autoload_mask); 1392 1393 /* mec ucode */ 1394 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1395 adev->gfx.mec_fw->data; 1396 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1397 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1398 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1399 cp_hdr->jt_size * 4; 1400 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1401 fw_data, fw_size, fw_autoload_mask); 1402 } 1403 1404 /* rlc ucode */ 1405 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1406 adev->gfx.rlc_fw->data; 1407 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1408 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1409 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1410 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1411 fw_data, fw_size, fw_autoload_mask); 1412 1413 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1414 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1415 if (version_major == 2) { 1416 if (version_minor >= 2) { 1417 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1418 1419 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1420 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1421 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1422 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1423 fw_data, fw_size, fw_autoload_mask); 1424 1425 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1426 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1427 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1428 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1429 fw_data, fw_size, fw_autoload_mask); 1430 } 1431 } 1432 } 1433 1434 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1435 uint32_t *fw_autoload_mask) 1436 { 1437 const __le32 *fw_data; 1438 uint32_t fw_size; 1439 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1440 1441 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1442 adev->sdma.instance[0].fw->data; 1443 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1444 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1445 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1446 1447 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1448 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1449 1450 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1451 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1452 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1453 1454 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1455 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1456 } 1457 1458 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1459 uint32_t *fw_autoload_mask) 1460 { 1461 const __le32 *fw_data; 1462 unsigned fw_size; 1463 const struct mes_firmware_header_v1_0 *mes_hdr; 1464 int pipe, ucode_id, data_id; 1465 1466 for (pipe = 0; pipe < 2; pipe++) { 1467 if (pipe==0) { 1468 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1469 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1470 } else { 1471 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1472 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1473 } 1474 1475 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1476 adev->mes.fw[pipe]->data; 1477 1478 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1479 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1480 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1481 1482 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1483 ucode_id, fw_data, fw_size, fw_autoload_mask); 1484 1485 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1486 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1487 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1488 1489 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1490 data_id, fw_data, fw_size, fw_autoload_mask); 1491 } 1492 } 1493 1494 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1495 { 1496 uint32_t rlc_g_offset, rlc_g_size; 1497 uint64_t gpu_addr; 1498 uint32_t autoload_fw_id[2]; 1499 1500 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1501 1502 /* RLC autoload sequence 2: copy ucode */ 1503 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1504 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1505 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1506 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1507 1508 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1509 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1510 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1511 1512 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1513 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1514 1515 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1516 1517 /* RLC autoload sequence 3: load IMU fw */ 1518 if (adev->gfx.imu.funcs->load_microcode) 1519 adev->gfx.imu.funcs->load_microcode(adev); 1520 /* RLC autoload sequence 4 init IMU fw */ 1521 if (adev->gfx.imu.funcs->setup_imu) 1522 adev->gfx.imu.funcs->setup_imu(adev); 1523 if (adev->gfx.imu.funcs->start_imu) 1524 adev->gfx.imu.funcs->start_imu(adev); 1525 1526 /* RLC autoload sequence 5 disable gpa mode */ 1527 gfx_v11_0_disable_gpa_mode(adev); 1528 1529 return 0; 1530 } 1531 1532 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1533 { 1534 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1535 uint32_t *ptr; 1536 uint32_t inst; 1537 1538 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1539 if (!ptr) { 1540 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1541 adev->gfx.ip_dump_core = NULL; 1542 } else { 1543 adev->gfx.ip_dump_core = ptr; 1544 } 1545 1546 /* Allocate memory for compute queue registers for all the instances */ 1547 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1548 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1549 adev->gfx.mec.num_queue_per_pipe; 1550 1551 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1552 if (!ptr) { 1553 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1554 adev->gfx.ip_dump_compute_queues = NULL; 1555 } else { 1556 adev->gfx.ip_dump_compute_queues = ptr; 1557 } 1558 1559 /* Allocate memory for gfx queue registers for all the instances */ 1560 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1561 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1562 adev->gfx.me.num_queue_per_pipe; 1563 1564 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1565 if (!ptr) { 1566 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1567 adev->gfx.ip_dump_gfx_queues = NULL; 1568 } else { 1569 adev->gfx.ip_dump_gfx_queues = ptr; 1570 } 1571 } 1572 1573 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1574 { 1575 int i, j, k, r, ring_id; 1576 int xcc_id = 0; 1577 struct amdgpu_device *adev = ip_block->adev; 1578 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1579 1580 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1581 1582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1583 case IP_VERSION(11, 0, 0): 1584 case IP_VERSION(11, 0, 1): 1585 case IP_VERSION(11, 0, 2): 1586 case IP_VERSION(11, 0, 3): 1587 case IP_VERSION(11, 0, 4): 1588 case IP_VERSION(11, 5, 0): 1589 case IP_VERSION(11, 5, 1): 1590 case IP_VERSION(11, 5, 2): 1591 case IP_VERSION(11, 5, 3): 1592 adev->gfx.me.num_me = 1; 1593 adev->gfx.me.num_pipe_per_me = 1; 1594 adev->gfx.me.num_queue_per_pipe = 2; 1595 adev->gfx.mec.num_mec = 1; 1596 adev->gfx.mec.num_pipe_per_mec = 4; 1597 adev->gfx.mec.num_queue_per_pipe = 4; 1598 break; 1599 default: 1600 adev->gfx.me.num_me = 1; 1601 adev->gfx.me.num_pipe_per_me = 1; 1602 adev->gfx.me.num_queue_per_pipe = 1; 1603 adev->gfx.mec.num_mec = 1; 1604 adev->gfx.mec.num_pipe_per_mec = 4; 1605 adev->gfx.mec.num_queue_per_pipe = 8; 1606 break; 1607 } 1608 1609 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1610 case IP_VERSION(11, 0, 0): 1611 case IP_VERSION(11, 0, 2): 1612 case IP_VERSION(11, 0, 3): 1613 if (!adev->gfx.disable_uq && 1614 adev->gfx.me_fw_version >= 2420 && 1615 adev->gfx.pfp_fw_version >= 2580 && 1616 adev->gfx.mec_fw_version >= 2650 && 1617 adev->mes.fw_version[0] >= 120) { 1618 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1619 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1620 } 1621 break; 1622 case IP_VERSION(11, 0, 1): 1623 case IP_VERSION(11, 0, 4): 1624 case IP_VERSION(11, 5, 0): 1625 case IP_VERSION(11, 5, 1): 1626 case IP_VERSION(11, 5, 2): 1627 case IP_VERSION(11, 5, 3): 1628 /* add firmware version checks here */ 1629 if (0 && !adev->gfx.disable_uq) { 1630 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1631 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1632 } 1633 break; 1634 default: 1635 break; 1636 } 1637 1638 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1639 case IP_VERSION(11, 0, 0): 1640 case IP_VERSION(11, 0, 2): 1641 case IP_VERSION(11, 0, 3): 1642 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1643 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1644 if (adev->gfx.me_fw_version >= 2280 && 1645 adev->gfx.pfp_fw_version >= 2370 && 1646 adev->gfx.mec_fw_version >= 2450 && 1647 adev->mes.fw_version[0] >= 99) { 1648 adev->gfx.enable_cleaner_shader = true; 1649 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1650 if (r) { 1651 adev->gfx.enable_cleaner_shader = false; 1652 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1653 } 1654 } 1655 break; 1656 case IP_VERSION(11, 5, 0): 1657 case IP_VERSION(11, 5, 1): 1658 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1659 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1660 if (adev->gfx.mec_fw_version >= 26 && 1661 adev->mes.fw_version[0] >= 114) { 1662 adev->gfx.enable_cleaner_shader = true; 1663 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1664 if (r) { 1665 adev->gfx.enable_cleaner_shader = false; 1666 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1667 } 1668 } 1669 break; 1670 case IP_VERSION(11, 5, 2): 1671 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1672 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1673 if (adev->gfx.me_fw_version >= 12 && 1674 adev->gfx.pfp_fw_version >= 15 && 1675 adev->gfx.mec_fw_version >= 15) { 1676 adev->gfx.enable_cleaner_shader = true; 1677 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1678 if (r) { 1679 adev->gfx.enable_cleaner_shader = false; 1680 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1681 } 1682 } 1683 break; 1684 case IP_VERSION(11, 5, 3): 1685 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1686 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1687 if (adev->gfx.me_fw_version >= 7 && 1688 adev->gfx.pfp_fw_version >= 8 && 1689 adev->gfx.mec_fw_version >= 8) { 1690 adev->gfx.enable_cleaner_shader = true; 1691 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1692 if (r) { 1693 adev->gfx.enable_cleaner_shader = false; 1694 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1695 } 1696 } 1697 break; 1698 default: 1699 adev->gfx.enable_cleaner_shader = false; 1700 break; 1701 } 1702 1703 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1704 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1705 amdgpu_sriov_is_pp_one_vf(adev)) 1706 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1707 1708 /* EOP Event */ 1709 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1710 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1711 &adev->gfx.eop_irq); 1712 if (r) 1713 return r; 1714 1715 /* Bad opcode Event */ 1716 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1717 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1718 &adev->gfx.bad_op_irq); 1719 if (r) 1720 return r; 1721 1722 /* Privileged reg */ 1723 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1724 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1725 &adev->gfx.priv_reg_irq); 1726 if (r) 1727 return r; 1728 1729 /* Privileged inst */ 1730 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1731 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1732 &adev->gfx.priv_inst_irq); 1733 if (r) 1734 return r; 1735 1736 /* FED error */ 1737 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1738 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1739 &adev->gfx.rlc_gc_fed_irq); 1740 if (r) 1741 return r; 1742 1743 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1744 1745 gfx_v11_0_me_init(adev); 1746 1747 r = gfx_v11_0_rlc_init(adev); 1748 if (r) { 1749 DRM_ERROR("Failed to init rlc BOs!\n"); 1750 return r; 1751 } 1752 1753 r = gfx_v11_0_mec_init(adev); 1754 if (r) { 1755 DRM_ERROR("Failed to init MEC BOs!\n"); 1756 return r; 1757 } 1758 1759 if (adev->gfx.num_gfx_rings) { 1760 ring_id = 0; 1761 /* set up the gfx ring */ 1762 for (i = 0; i < adev->gfx.me.num_me; i++) { 1763 for (j = 0; j < num_queue_per_pipe; j++) { 1764 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1765 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1766 continue; 1767 1768 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1769 i, k, j); 1770 if (r) 1771 return r; 1772 ring_id++; 1773 } 1774 } 1775 } 1776 } 1777 1778 if (adev->gfx.num_compute_rings) { 1779 ring_id = 0; 1780 /* set up the compute queues - allocate horizontally across pipes */ 1781 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1782 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1783 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1784 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1785 k, j)) 1786 continue; 1787 1788 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1789 i, k, j); 1790 if (r) 1791 return r; 1792 1793 ring_id++; 1794 } 1795 } 1796 } 1797 } 1798 1799 adev->gfx.gfx_supported_reset = 1800 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1801 adev->gfx.compute_supported_reset = 1802 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1803 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1804 case IP_VERSION(11, 0, 0): 1805 case IP_VERSION(11, 0, 2): 1806 case IP_VERSION(11, 0, 3): 1807 if ((adev->gfx.me_fw_version >= 2280) && 1808 (adev->gfx.mec_fw_version >= 2410) && 1809 !amdgpu_sriov_vf(adev)) { 1810 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1811 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1812 } 1813 break; 1814 default: 1815 if (!amdgpu_sriov_vf(adev)) { 1816 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1817 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1818 } 1819 break; 1820 } 1821 1822 if (!adev->enable_mes_kiq) { 1823 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1824 if (r) { 1825 DRM_ERROR("Failed to init KIQ BOs!\n"); 1826 return r; 1827 } 1828 1829 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1830 if (r) 1831 return r; 1832 } 1833 1834 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1835 if (r) 1836 return r; 1837 1838 /* allocate visible FB for rlc auto-loading fw */ 1839 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1840 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1841 if (r) 1842 return r; 1843 } 1844 1845 r = gfx_v11_0_gpu_early_init(adev); 1846 if (r) 1847 return r; 1848 1849 if (amdgpu_gfx_ras_sw_init(adev)) { 1850 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1851 return -EINVAL; 1852 } 1853 1854 gfx_v11_0_alloc_ip_dump(adev); 1855 1856 r = amdgpu_gfx_sysfs_init(adev); 1857 if (r) 1858 return r; 1859 1860 return 0; 1861 } 1862 1863 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1864 { 1865 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1866 &adev->gfx.pfp.pfp_fw_gpu_addr, 1867 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1868 1869 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1870 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1871 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1872 } 1873 1874 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1875 { 1876 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1877 &adev->gfx.me.me_fw_gpu_addr, 1878 (void **)&adev->gfx.me.me_fw_ptr); 1879 1880 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1881 &adev->gfx.me.me_fw_data_gpu_addr, 1882 (void **)&adev->gfx.me.me_fw_data_ptr); 1883 } 1884 1885 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1886 { 1887 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1888 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1889 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1890 } 1891 1892 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1893 { 1894 int i; 1895 struct amdgpu_device *adev = ip_block->adev; 1896 1897 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1898 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1899 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1900 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1901 1902 amdgpu_gfx_mqd_sw_fini(adev, 0); 1903 1904 if (!adev->enable_mes_kiq) { 1905 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1906 amdgpu_gfx_kiq_fini(adev, 0); 1907 } 1908 1909 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1910 1911 gfx_v11_0_pfp_fini(adev); 1912 gfx_v11_0_me_fini(adev); 1913 gfx_v11_0_rlc_fini(adev); 1914 gfx_v11_0_mec_fini(adev); 1915 1916 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1917 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1918 1919 gfx_v11_0_free_microcode(adev); 1920 1921 amdgpu_gfx_sysfs_fini(adev); 1922 1923 kfree(adev->gfx.ip_dump_core); 1924 kfree(adev->gfx.ip_dump_compute_queues); 1925 kfree(adev->gfx.ip_dump_gfx_queues); 1926 1927 return 0; 1928 } 1929 1930 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1931 u32 sh_num, u32 instance, int xcc_id) 1932 { 1933 u32 data; 1934 1935 if (instance == 0xffffffff) 1936 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1937 INSTANCE_BROADCAST_WRITES, 1); 1938 else 1939 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1940 instance); 1941 1942 if (se_num == 0xffffffff) 1943 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1944 1); 1945 else 1946 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1947 1948 if (sh_num == 0xffffffff) 1949 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1950 1); 1951 else 1952 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1953 1954 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1955 } 1956 1957 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1958 { 1959 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1960 1961 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1962 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1963 CC_GC_SA_UNIT_DISABLE, 1964 SA_DISABLE); 1965 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1966 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1967 GC_USER_SA_UNIT_DISABLE, 1968 SA_DISABLE); 1969 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1970 adev->gfx.config.max_shader_engines); 1971 1972 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1973 } 1974 1975 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1976 { 1977 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1978 u32 rb_mask; 1979 1980 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1981 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1982 CC_RB_BACKEND_DISABLE, 1983 BACKEND_DISABLE); 1984 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1985 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1986 GC_USER_RB_BACKEND_DISABLE, 1987 BACKEND_DISABLE); 1988 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1989 adev->gfx.config.max_shader_engines); 1990 1991 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1992 } 1993 1994 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1995 { 1996 u32 rb_bitmap_per_sa; 1997 u32 rb_bitmap_width_per_sa; 1998 u32 max_sa; 1999 u32 active_sa_bitmap; 2000 u32 global_active_rb_bitmap; 2001 u32 active_rb_bitmap = 0; 2002 u32 i; 2003 2004 /* query sa bitmap from SA_UNIT_DISABLE registers */ 2005 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 2006 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 2007 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 2008 2009 /* generate active rb bitmap according to active sa bitmap */ 2010 max_sa = adev->gfx.config.max_shader_engines * 2011 adev->gfx.config.max_sh_per_se; 2012 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 2013 adev->gfx.config.max_sh_per_se; 2014 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 2015 2016 for (i = 0; i < max_sa; i++) { 2017 if (active_sa_bitmap & (1 << i)) 2018 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 2019 } 2020 2021 active_rb_bitmap &= global_active_rb_bitmap; 2022 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 2023 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 2024 } 2025 2026 #define DEFAULT_SH_MEM_BASES (0x6000) 2027 #define LDS_APP_BASE 0x1 2028 #define SCRATCH_APP_BASE 0x2 2029 2030 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 2031 { 2032 int i; 2033 uint32_t sh_mem_bases; 2034 uint32_t data; 2035 2036 /* 2037 * Configure apertures: 2038 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2039 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2040 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2041 */ 2042 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 2043 SCRATCH_APP_BASE; 2044 2045 mutex_lock(&adev->srbm_mutex); 2046 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2047 soc21_grbm_select(adev, 0, 0, 0, i); 2048 /* CP and shaders */ 2049 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2050 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 2051 2052 /* Enable trap for each kfd vmid. */ 2053 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 2054 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 2055 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 2056 } 2057 soc21_grbm_select(adev, 0, 0, 0, 0); 2058 mutex_unlock(&adev->srbm_mutex); 2059 2060 /* 2061 * Initialize all compute VMIDs to have no GDS, GWS, or OA 2062 * access. These should be enabled by FW for target VMIDs. 2063 */ 2064 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2065 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 2066 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 2067 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 2068 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 2069 } 2070 } 2071 2072 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 2073 { 2074 int vmid; 2075 2076 /* 2077 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2078 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2079 * the driver can enable them for graphics. VMID0 should maintain 2080 * access so that HWS firmware can save/restore entries. 2081 */ 2082 for (vmid = 1; vmid < 16; vmid++) { 2083 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 2084 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 2085 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 2086 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 2087 } 2088 } 2089 2090 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 2091 { 2092 /* TODO: harvest feature to be added later. */ 2093 } 2094 2095 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2096 { 2097 /* TCCs are global (not instanced). */ 2098 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2099 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2100 2101 adev->gfx.config.tcc_disabled_mask = 2102 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2103 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2104 } 2105 2106 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2107 { 2108 u32 tmp; 2109 int i; 2110 2111 if (!amdgpu_sriov_vf(adev)) 2112 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2113 2114 gfx_v11_0_setup_rb(adev); 2115 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2116 gfx_v11_0_get_tcc_info(adev); 2117 adev->gfx.config.pa_sc_tile_steering_override = 0; 2118 2119 /* Set whether texture coordinate truncation is conformant. */ 2120 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2121 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2122 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2123 2124 /* XXX SH_MEM regs */ 2125 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2126 mutex_lock(&adev->srbm_mutex); 2127 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2128 soc21_grbm_select(adev, 0, 0, 0, i); 2129 /* CP and shaders */ 2130 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2131 if (i != 0) { 2132 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2133 (adev->gmc.private_aperture_start >> 48)); 2134 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2135 (adev->gmc.shared_aperture_start >> 48)); 2136 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2137 } 2138 } 2139 soc21_grbm_select(adev, 0, 0, 0, 0); 2140 2141 mutex_unlock(&adev->srbm_mutex); 2142 2143 gfx_v11_0_init_compute_vmid(adev); 2144 gfx_v11_0_init_gds_vmid(adev); 2145 } 2146 2147 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2148 int me, int pipe) 2149 { 2150 if (me != 0) 2151 return 0; 2152 2153 switch (pipe) { 2154 case 0: 2155 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2156 case 1: 2157 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2158 default: 2159 return 0; 2160 } 2161 } 2162 2163 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2164 int me, int pipe) 2165 { 2166 /* 2167 * amdgpu controls only the first MEC. That's why this function only 2168 * handles the setting of interrupts for this specific MEC. All other 2169 * pipes' interrupts are set by amdkfd. 2170 */ 2171 if (me != 1) 2172 return 0; 2173 2174 switch (pipe) { 2175 case 0: 2176 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2177 case 1: 2178 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2179 case 2: 2180 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2181 case 3: 2182 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2183 default: 2184 return 0; 2185 } 2186 } 2187 2188 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2189 bool enable) 2190 { 2191 u32 tmp, cp_int_cntl_reg; 2192 int i, j; 2193 2194 if (amdgpu_sriov_vf(adev)) 2195 return; 2196 2197 for (i = 0; i < adev->gfx.me.num_me; i++) { 2198 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2199 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2200 2201 if (cp_int_cntl_reg) { 2202 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2203 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2204 enable ? 1 : 0); 2205 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2206 enable ? 1 : 0); 2207 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2208 enable ? 1 : 0); 2209 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2210 enable ? 1 : 0); 2211 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2212 } 2213 } 2214 } 2215 } 2216 2217 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2218 { 2219 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2220 2221 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2222 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2223 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2224 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2225 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2226 2227 return 0; 2228 } 2229 2230 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2231 { 2232 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2233 2234 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2235 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2236 } 2237 2238 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2239 { 2240 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2241 udelay(50); 2242 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2243 udelay(50); 2244 } 2245 2246 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2247 bool enable) 2248 { 2249 uint32_t rlc_pg_cntl; 2250 2251 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2252 2253 if (!enable) { 2254 /* RLC_PG_CNTL[23] = 0 (default) 2255 * RLC will wait for handshake acks with SMU 2256 * GFXOFF will be enabled 2257 * RLC_PG_CNTL[23] = 1 2258 * RLC will not issue any message to SMU 2259 * hence no handshake between SMU & RLC 2260 * GFXOFF will be disabled 2261 */ 2262 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2263 } else 2264 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2265 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2266 } 2267 2268 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2269 { 2270 /* TODO: enable rlc & smu handshake until smu 2271 * and gfxoff feature works as expected */ 2272 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2273 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2274 2275 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2276 udelay(50); 2277 } 2278 2279 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2280 { 2281 uint32_t tmp; 2282 2283 /* enable Save Restore Machine */ 2284 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2285 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2286 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2287 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2288 } 2289 2290 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2291 { 2292 const struct rlc_firmware_header_v2_0 *hdr; 2293 const __le32 *fw_data; 2294 unsigned i, fw_size; 2295 2296 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2297 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2298 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2299 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2300 2301 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2302 RLCG_UCODE_LOADING_START_ADDRESS); 2303 2304 for (i = 0; i < fw_size; i++) 2305 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2306 le32_to_cpup(fw_data++)); 2307 2308 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2309 } 2310 2311 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2312 { 2313 const struct rlc_firmware_header_v2_2 *hdr; 2314 const __le32 *fw_data; 2315 unsigned i, fw_size; 2316 u32 tmp; 2317 2318 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2319 2320 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2321 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2322 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2323 2324 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2325 2326 for (i = 0; i < fw_size; i++) { 2327 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2328 msleep(1); 2329 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2330 le32_to_cpup(fw_data++)); 2331 } 2332 2333 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2334 2335 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2336 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2337 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2338 2339 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2340 for (i = 0; i < fw_size; i++) { 2341 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2342 msleep(1); 2343 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2344 le32_to_cpup(fw_data++)); 2345 } 2346 2347 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2348 2349 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2350 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2351 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2352 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2353 } 2354 2355 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2356 { 2357 const struct rlc_firmware_header_v2_3 *hdr; 2358 const __le32 *fw_data; 2359 unsigned i, fw_size; 2360 u32 tmp; 2361 2362 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2363 2364 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2365 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2366 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2367 2368 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2369 2370 for (i = 0; i < fw_size; i++) { 2371 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2372 msleep(1); 2373 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2374 le32_to_cpup(fw_data++)); 2375 } 2376 2377 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2378 2379 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2380 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2381 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2382 2383 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2384 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2385 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2386 2387 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2388 2389 for (i = 0; i < fw_size; i++) { 2390 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2391 msleep(1); 2392 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2393 le32_to_cpup(fw_data++)); 2394 } 2395 2396 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2397 2398 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2399 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2400 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2401 } 2402 2403 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2404 { 2405 const struct rlc_firmware_header_v2_0 *hdr; 2406 uint16_t version_major; 2407 uint16_t version_minor; 2408 2409 if (!adev->gfx.rlc_fw) 2410 return -EINVAL; 2411 2412 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2413 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2414 2415 version_major = le16_to_cpu(hdr->header.header_version_major); 2416 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2417 2418 if (version_major == 2) { 2419 gfx_v11_0_load_rlcg_microcode(adev); 2420 if (amdgpu_dpm == 1) { 2421 if (version_minor >= 2) 2422 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2423 if (version_minor == 3) 2424 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2425 } 2426 2427 return 0; 2428 } 2429 2430 return -EINVAL; 2431 } 2432 2433 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2434 { 2435 int r; 2436 2437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2438 gfx_v11_0_init_csb(adev); 2439 2440 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2441 gfx_v11_0_rlc_enable_srm(adev); 2442 } else { 2443 if (amdgpu_sriov_vf(adev)) { 2444 gfx_v11_0_init_csb(adev); 2445 return 0; 2446 } 2447 2448 adev->gfx.rlc.funcs->stop(adev); 2449 2450 /* disable CG */ 2451 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2452 2453 /* disable PG */ 2454 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2455 2456 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2457 /* legacy rlc firmware loading */ 2458 r = gfx_v11_0_rlc_load_microcode(adev); 2459 if (r) 2460 return r; 2461 } 2462 2463 gfx_v11_0_init_csb(adev); 2464 2465 adev->gfx.rlc.funcs->start(adev); 2466 } 2467 return 0; 2468 } 2469 2470 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2471 { 2472 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2473 uint32_t tmp; 2474 int i; 2475 2476 /* Trigger an invalidation of the L1 instruction caches */ 2477 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2478 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2479 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2480 2481 /* Wait for invalidation complete */ 2482 for (i = 0; i < usec_timeout; i++) { 2483 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2484 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2485 INVALIDATE_CACHE_COMPLETE)) 2486 break; 2487 udelay(1); 2488 } 2489 2490 if (i >= usec_timeout) { 2491 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2492 return -EINVAL; 2493 } 2494 2495 if (amdgpu_emu_mode == 1) 2496 amdgpu_device_flush_hdp(adev, NULL); 2497 2498 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2499 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2500 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2501 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2502 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2503 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2504 2505 /* Program me ucode address into intruction cache address register */ 2506 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2507 lower_32_bits(addr) & 0xFFFFF000); 2508 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2509 upper_32_bits(addr)); 2510 2511 return 0; 2512 } 2513 2514 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2515 { 2516 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2517 uint32_t tmp; 2518 int i; 2519 2520 /* Trigger an invalidation of the L1 instruction caches */ 2521 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2522 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2523 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2524 2525 /* Wait for invalidation complete */ 2526 for (i = 0; i < usec_timeout; i++) { 2527 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2528 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2529 INVALIDATE_CACHE_COMPLETE)) 2530 break; 2531 udelay(1); 2532 } 2533 2534 if (i >= usec_timeout) { 2535 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2536 return -EINVAL; 2537 } 2538 2539 if (amdgpu_emu_mode == 1) 2540 amdgpu_device_flush_hdp(adev, NULL); 2541 2542 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2543 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2544 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2545 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2546 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2547 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2548 2549 /* Program pfp ucode address into intruction cache address register */ 2550 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2551 lower_32_bits(addr) & 0xFFFFF000); 2552 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2553 upper_32_bits(addr)); 2554 2555 return 0; 2556 } 2557 2558 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2559 { 2560 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2561 uint32_t tmp; 2562 int i; 2563 2564 /* Trigger an invalidation of the L1 instruction caches */ 2565 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2566 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2567 2568 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2569 2570 /* Wait for invalidation complete */ 2571 for (i = 0; i < usec_timeout; i++) { 2572 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2573 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2574 INVALIDATE_CACHE_COMPLETE)) 2575 break; 2576 udelay(1); 2577 } 2578 2579 if (i >= usec_timeout) { 2580 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2581 return -EINVAL; 2582 } 2583 2584 if (amdgpu_emu_mode == 1) 2585 amdgpu_device_flush_hdp(adev, NULL); 2586 2587 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2588 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2589 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2590 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2591 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2592 2593 /* Program mec1 ucode address into intruction cache address register */ 2594 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2595 lower_32_bits(addr) & 0xFFFFF000); 2596 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2597 upper_32_bits(addr)); 2598 2599 return 0; 2600 } 2601 2602 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2603 { 2604 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2605 uint32_t tmp; 2606 unsigned i, pipe_id; 2607 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2608 2609 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2610 adev->gfx.pfp_fw->data; 2611 2612 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2613 lower_32_bits(addr)); 2614 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2615 upper_32_bits(addr)); 2616 2617 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2618 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2619 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2620 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2621 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2622 2623 /* 2624 * Programming any of the CP_PFP_IC_BASE registers 2625 * forces invalidation of the ME L1 I$. Wait for the 2626 * invalidation complete 2627 */ 2628 for (i = 0; i < usec_timeout; i++) { 2629 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2630 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2631 INVALIDATE_CACHE_COMPLETE)) 2632 break; 2633 udelay(1); 2634 } 2635 2636 if (i >= usec_timeout) { 2637 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2638 return -EINVAL; 2639 } 2640 2641 /* Prime the L1 instruction caches */ 2642 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2643 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2644 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2645 /* Waiting for cache primed*/ 2646 for (i = 0; i < usec_timeout; i++) { 2647 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2648 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2649 ICACHE_PRIMED)) 2650 break; 2651 udelay(1); 2652 } 2653 2654 if (i >= usec_timeout) { 2655 dev_err(adev->dev, "failed to prime instruction cache\n"); 2656 return -EINVAL; 2657 } 2658 2659 mutex_lock(&adev->srbm_mutex); 2660 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2661 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2662 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2663 (pfp_hdr->ucode_start_addr_hi << 30) | 2664 (pfp_hdr->ucode_start_addr_lo >> 2)); 2665 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2666 pfp_hdr->ucode_start_addr_hi >> 2); 2667 2668 /* 2669 * Program CP_ME_CNTL to reset given PIPE to take 2670 * effect of CP_PFP_PRGRM_CNTR_START. 2671 */ 2672 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2673 if (pipe_id == 0) 2674 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2675 PFP_PIPE0_RESET, 1); 2676 else 2677 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2678 PFP_PIPE1_RESET, 1); 2679 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2680 2681 /* Clear pfp pipe0 reset bit. */ 2682 if (pipe_id == 0) 2683 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2684 PFP_PIPE0_RESET, 0); 2685 else 2686 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2687 PFP_PIPE1_RESET, 0); 2688 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2689 2690 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2691 lower_32_bits(addr2)); 2692 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2693 upper_32_bits(addr2)); 2694 } 2695 soc21_grbm_select(adev, 0, 0, 0, 0); 2696 mutex_unlock(&adev->srbm_mutex); 2697 2698 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2699 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2700 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2701 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2702 2703 /* Invalidate the data caches */ 2704 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2705 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2706 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2707 2708 for (i = 0; i < usec_timeout; i++) { 2709 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2710 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2711 INVALIDATE_DCACHE_COMPLETE)) 2712 break; 2713 udelay(1); 2714 } 2715 2716 if (i >= usec_timeout) { 2717 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2718 return -EINVAL; 2719 } 2720 2721 return 0; 2722 } 2723 2724 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2725 { 2726 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2727 uint32_t tmp; 2728 unsigned i, pipe_id; 2729 const struct gfx_firmware_header_v2_0 *me_hdr; 2730 2731 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2732 adev->gfx.me_fw->data; 2733 2734 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2735 lower_32_bits(addr)); 2736 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2737 upper_32_bits(addr)); 2738 2739 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2740 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2741 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2742 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2743 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2744 2745 /* 2746 * Programming any of the CP_ME_IC_BASE registers 2747 * forces invalidation of the ME L1 I$. Wait for the 2748 * invalidation complete 2749 */ 2750 for (i = 0; i < usec_timeout; i++) { 2751 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2752 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2753 INVALIDATE_CACHE_COMPLETE)) 2754 break; 2755 udelay(1); 2756 } 2757 2758 if (i >= usec_timeout) { 2759 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2760 return -EINVAL; 2761 } 2762 2763 /* Prime the instruction caches */ 2764 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2765 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2766 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2767 2768 /* Waiting for instruction cache primed*/ 2769 for (i = 0; i < usec_timeout; i++) { 2770 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2771 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2772 ICACHE_PRIMED)) 2773 break; 2774 udelay(1); 2775 } 2776 2777 if (i >= usec_timeout) { 2778 dev_err(adev->dev, "failed to prime instruction cache\n"); 2779 return -EINVAL; 2780 } 2781 2782 mutex_lock(&adev->srbm_mutex); 2783 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2784 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2785 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2786 (me_hdr->ucode_start_addr_hi << 30) | 2787 (me_hdr->ucode_start_addr_lo >> 2) ); 2788 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2789 me_hdr->ucode_start_addr_hi>>2); 2790 2791 /* 2792 * Program CP_ME_CNTL to reset given PIPE to take 2793 * effect of CP_PFP_PRGRM_CNTR_START. 2794 */ 2795 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2796 if (pipe_id == 0) 2797 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2798 ME_PIPE0_RESET, 1); 2799 else 2800 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2801 ME_PIPE1_RESET, 1); 2802 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2803 2804 /* Clear pfp pipe0 reset bit. */ 2805 if (pipe_id == 0) 2806 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2807 ME_PIPE0_RESET, 0); 2808 else 2809 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2810 ME_PIPE1_RESET, 0); 2811 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2812 2813 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2814 lower_32_bits(addr2)); 2815 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2816 upper_32_bits(addr2)); 2817 } 2818 soc21_grbm_select(adev, 0, 0, 0, 0); 2819 mutex_unlock(&adev->srbm_mutex); 2820 2821 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2822 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2823 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2824 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2825 2826 /* Invalidate the data caches */ 2827 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2828 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2829 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2830 2831 for (i = 0; i < usec_timeout; i++) { 2832 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2833 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2834 INVALIDATE_DCACHE_COMPLETE)) 2835 break; 2836 udelay(1); 2837 } 2838 2839 if (i >= usec_timeout) { 2840 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2841 return -EINVAL; 2842 } 2843 2844 return 0; 2845 } 2846 2847 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2848 { 2849 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2850 uint32_t tmp; 2851 unsigned i; 2852 const struct gfx_firmware_header_v2_0 *mec_hdr; 2853 2854 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2855 adev->gfx.mec_fw->data; 2856 2857 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2858 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2859 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2860 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2861 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2862 2863 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2864 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2865 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2866 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2867 2868 mutex_lock(&adev->srbm_mutex); 2869 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2870 soc21_grbm_select(adev, 1, i, 0, 0); 2871 2872 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2873 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2874 upper_32_bits(addr2)); 2875 2876 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2877 mec_hdr->ucode_start_addr_lo >> 2 | 2878 mec_hdr->ucode_start_addr_hi << 30); 2879 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2880 mec_hdr->ucode_start_addr_hi >> 2); 2881 2882 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2883 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2884 upper_32_bits(addr)); 2885 } 2886 mutex_unlock(&adev->srbm_mutex); 2887 soc21_grbm_select(adev, 0, 0, 0, 0); 2888 2889 /* Trigger an invalidation of the L1 instruction caches */ 2890 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2891 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2892 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2893 2894 /* Wait for invalidation complete */ 2895 for (i = 0; i < usec_timeout; i++) { 2896 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2897 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2898 INVALIDATE_DCACHE_COMPLETE)) 2899 break; 2900 udelay(1); 2901 } 2902 2903 if (i >= usec_timeout) { 2904 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2905 return -EINVAL; 2906 } 2907 2908 /* Trigger an invalidation of the L1 instruction caches */ 2909 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2910 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2911 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2912 2913 /* Wait for invalidation complete */ 2914 for (i = 0; i < usec_timeout; i++) { 2915 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2916 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2917 INVALIDATE_CACHE_COMPLETE)) 2918 break; 2919 udelay(1); 2920 } 2921 2922 if (i >= usec_timeout) { 2923 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2924 return -EINVAL; 2925 } 2926 2927 return 0; 2928 } 2929 2930 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2931 { 2932 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2933 const struct gfx_firmware_header_v2_0 *me_hdr; 2934 const struct gfx_firmware_header_v2_0 *mec_hdr; 2935 uint32_t pipe_id, tmp; 2936 2937 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2938 adev->gfx.mec_fw->data; 2939 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2940 adev->gfx.me_fw->data; 2941 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2942 adev->gfx.pfp_fw->data; 2943 2944 /* config pfp program start addr */ 2945 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2946 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2947 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2948 (pfp_hdr->ucode_start_addr_hi << 30) | 2949 (pfp_hdr->ucode_start_addr_lo >> 2)); 2950 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2951 pfp_hdr->ucode_start_addr_hi >> 2); 2952 } 2953 soc21_grbm_select(adev, 0, 0, 0, 0); 2954 2955 /* reset pfp pipe */ 2956 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2957 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2958 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2959 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2960 2961 /* clear pfp pipe reset */ 2962 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2963 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2964 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2965 2966 /* config me program start addr */ 2967 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2968 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2969 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2970 (me_hdr->ucode_start_addr_hi << 30) | 2971 (me_hdr->ucode_start_addr_lo >> 2) ); 2972 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2973 me_hdr->ucode_start_addr_hi>>2); 2974 } 2975 soc21_grbm_select(adev, 0, 0, 0, 0); 2976 2977 /* reset me pipe */ 2978 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2979 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2980 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2981 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2982 2983 /* clear me pipe reset */ 2984 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2985 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2986 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2987 2988 /* config mec program start addr */ 2989 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2990 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2991 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2992 mec_hdr->ucode_start_addr_lo >> 2 | 2993 mec_hdr->ucode_start_addr_hi << 30); 2994 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2995 mec_hdr->ucode_start_addr_hi >> 2); 2996 } 2997 soc21_grbm_select(adev, 0, 0, 0, 0); 2998 2999 /* reset mec pipe */ 3000 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3001 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 3002 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 3003 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 3004 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 3005 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3006 3007 /* clear mec pipe reset */ 3008 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 3009 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 3010 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 3011 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 3012 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3013 } 3014 3015 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 3016 { 3017 uint32_t cp_status; 3018 uint32_t bootload_status; 3019 int i, r; 3020 uint64_t addr, addr2; 3021 3022 for (i = 0; i < adev->usec_timeout; i++) { 3023 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 3024 3025 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 3026 IP_VERSION(11, 0, 1) || 3027 amdgpu_ip_version(adev, GC_HWIP, 0) == 3028 IP_VERSION(11, 0, 4) || 3029 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 3030 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 3031 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 3032 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) 3033 bootload_status = RREG32_SOC15(GC, 0, 3034 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 3035 else 3036 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 3037 3038 if ((cp_status == 0) && 3039 (REG_GET_FIELD(bootload_status, 3040 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 3041 break; 3042 } 3043 udelay(1); 3044 } 3045 3046 if (i >= adev->usec_timeout) { 3047 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 3048 return -ETIMEDOUT; 3049 } 3050 3051 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3052 if (adev->gfx.rs64_enable) { 3053 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3054 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 3055 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3056 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 3057 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 3058 if (r) 3059 return r; 3060 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3061 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 3062 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3063 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 3064 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 3065 if (r) 3066 return r; 3067 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3068 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 3069 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3070 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 3071 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 3072 if (r) 3073 return r; 3074 } else { 3075 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3076 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 3077 r = gfx_v11_0_config_me_cache(adev, addr); 3078 if (r) 3079 return r; 3080 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3081 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 3082 r = gfx_v11_0_config_pfp_cache(adev, addr); 3083 if (r) 3084 return r; 3085 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3086 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 3087 r = gfx_v11_0_config_mec_cache(adev, addr); 3088 if (r) 3089 return r; 3090 } 3091 } 3092 3093 return 0; 3094 } 3095 3096 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3097 { 3098 int i; 3099 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3100 3101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3102 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3103 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3104 3105 for (i = 0; i < adev->usec_timeout; i++) { 3106 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3107 break; 3108 udelay(1); 3109 } 3110 3111 if (i >= adev->usec_timeout) 3112 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3113 3114 return 0; 3115 } 3116 3117 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3118 { 3119 int r; 3120 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3121 const __le32 *fw_data; 3122 unsigned i, fw_size; 3123 3124 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3125 adev->gfx.pfp_fw->data; 3126 3127 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3128 3129 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3130 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3131 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3132 3133 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3135 &adev->gfx.pfp.pfp_fw_obj, 3136 &adev->gfx.pfp.pfp_fw_gpu_addr, 3137 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3138 if (r) { 3139 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3140 gfx_v11_0_pfp_fini(adev); 3141 return r; 3142 } 3143 3144 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3145 3146 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3147 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3148 3149 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3150 3151 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3152 3153 for (i = 0; i < pfp_hdr->jt_size; i++) 3154 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3155 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3156 3157 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3158 3159 return 0; 3160 } 3161 3162 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3163 { 3164 int r; 3165 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3166 const __le32 *fw_ucode, *fw_data; 3167 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3168 uint32_t tmp; 3169 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3170 3171 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3172 adev->gfx.pfp_fw->data; 3173 3174 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3175 3176 /* instruction */ 3177 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3178 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3179 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3180 /* data */ 3181 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3182 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3183 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3184 3185 /* 64kb align */ 3186 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3187 64 * 1024, 3188 AMDGPU_GEM_DOMAIN_VRAM | 3189 AMDGPU_GEM_DOMAIN_GTT, 3190 &adev->gfx.pfp.pfp_fw_obj, 3191 &adev->gfx.pfp.pfp_fw_gpu_addr, 3192 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3193 if (r) { 3194 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3195 gfx_v11_0_pfp_fini(adev); 3196 return r; 3197 } 3198 3199 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3200 64 * 1024, 3201 AMDGPU_GEM_DOMAIN_VRAM | 3202 AMDGPU_GEM_DOMAIN_GTT, 3203 &adev->gfx.pfp.pfp_fw_data_obj, 3204 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3205 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3206 if (r) { 3207 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3208 gfx_v11_0_pfp_fini(adev); 3209 return r; 3210 } 3211 3212 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3213 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3214 3215 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3216 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3217 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3218 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3219 3220 if (amdgpu_emu_mode == 1) 3221 amdgpu_device_flush_hdp(adev, NULL); 3222 3223 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3224 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3225 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3226 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3227 3228 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3229 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3230 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3231 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3232 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3233 3234 /* 3235 * Programming any of the CP_PFP_IC_BASE registers 3236 * forces invalidation of the ME L1 I$. Wait for the 3237 * invalidation complete 3238 */ 3239 for (i = 0; i < usec_timeout; i++) { 3240 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3241 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3242 INVALIDATE_CACHE_COMPLETE)) 3243 break; 3244 udelay(1); 3245 } 3246 3247 if (i >= usec_timeout) { 3248 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3249 return -EINVAL; 3250 } 3251 3252 /* Prime the L1 instruction caches */ 3253 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3254 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3255 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3256 /* Waiting for cache primed*/ 3257 for (i = 0; i < usec_timeout; i++) { 3258 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3259 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3260 ICACHE_PRIMED)) 3261 break; 3262 udelay(1); 3263 } 3264 3265 if (i >= usec_timeout) { 3266 dev_err(adev->dev, "failed to prime instruction cache\n"); 3267 return -EINVAL; 3268 } 3269 3270 mutex_lock(&adev->srbm_mutex); 3271 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3272 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3273 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3274 (pfp_hdr->ucode_start_addr_hi << 30) | 3275 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3276 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3277 pfp_hdr->ucode_start_addr_hi>>2); 3278 3279 /* 3280 * Program CP_ME_CNTL to reset given PIPE to take 3281 * effect of CP_PFP_PRGRM_CNTR_START. 3282 */ 3283 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3284 if (pipe_id == 0) 3285 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3286 PFP_PIPE0_RESET, 1); 3287 else 3288 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3289 PFP_PIPE1_RESET, 1); 3290 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3291 3292 /* Clear pfp pipe0 reset bit. */ 3293 if (pipe_id == 0) 3294 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3295 PFP_PIPE0_RESET, 0); 3296 else 3297 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3298 PFP_PIPE1_RESET, 0); 3299 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3300 3301 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3302 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3303 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3304 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3305 } 3306 soc21_grbm_select(adev, 0, 0, 0, 0); 3307 mutex_unlock(&adev->srbm_mutex); 3308 3309 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3310 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3311 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3312 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3313 3314 /* Invalidate the data caches */ 3315 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3316 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3317 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3318 3319 for (i = 0; i < usec_timeout; i++) { 3320 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3321 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3322 INVALIDATE_DCACHE_COMPLETE)) 3323 break; 3324 udelay(1); 3325 } 3326 3327 if (i >= usec_timeout) { 3328 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3329 return -EINVAL; 3330 } 3331 3332 return 0; 3333 } 3334 3335 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3336 { 3337 int r; 3338 const struct gfx_firmware_header_v1_0 *me_hdr; 3339 const __le32 *fw_data; 3340 unsigned i, fw_size; 3341 3342 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3343 adev->gfx.me_fw->data; 3344 3345 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3346 3347 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3348 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3349 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3350 3351 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3352 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3353 &adev->gfx.me.me_fw_obj, 3354 &adev->gfx.me.me_fw_gpu_addr, 3355 (void **)&adev->gfx.me.me_fw_ptr); 3356 if (r) { 3357 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3358 gfx_v11_0_me_fini(adev); 3359 return r; 3360 } 3361 3362 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3363 3364 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3365 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3366 3367 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3368 3369 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3370 3371 for (i = 0; i < me_hdr->jt_size; i++) 3372 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3373 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3374 3375 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3376 3377 return 0; 3378 } 3379 3380 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3381 { 3382 int r; 3383 const struct gfx_firmware_header_v2_0 *me_hdr; 3384 const __le32 *fw_ucode, *fw_data; 3385 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3386 uint32_t tmp; 3387 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3388 3389 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3390 adev->gfx.me_fw->data; 3391 3392 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3393 3394 /* instruction */ 3395 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3396 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3397 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3398 /* data */ 3399 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3400 le32_to_cpu(me_hdr->data_offset_bytes)); 3401 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3402 3403 /* 64kb align*/ 3404 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3405 64 * 1024, 3406 AMDGPU_GEM_DOMAIN_VRAM | 3407 AMDGPU_GEM_DOMAIN_GTT, 3408 &adev->gfx.me.me_fw_obj, 3409 &adev->gfx.me.me_fw_gpu_addr, 3410 (void **)&adev->gfx.me.me_fw_ptr); 3411 if (r) { 3412 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3413 gfx_v11_0_me_fini(adev); 3414 return r; 3415 } 3416 3417 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3418 64 * 1024, 3419 AMDGPU_GEM_DOMAIN_VRAM | 3420 AMDGPU_GEM_DOMAIN_GTT, 3421 &adev->gfx.me.me_fw_data_obj, 3422 &adev->gfx.me.me_fw_data_gpu_addr, 3423 (void **)&adev->gfx.me.me_fw_data_ptr); 3424 if (r) { 3425 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3426 gfx_v11_0_pfp_fini(adev); 3427 return r; 3428 } 3429 3430 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3431 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3432 3433 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3434 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3435 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3436 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3437 3438 if (amdgpu_emu_mode == 1) 3439 amdgpu_device_flush_hdp(adev, NULL); 3440 3441 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3442 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3443 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3444 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3445 3446 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3447 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3448 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3449 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3450 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3451 3452 /* 3453 * Programming any of the CP_ME_IC_BASE registers 3454 * forces invalidation of the ME L1 I$. Wait for the 3455 * invalidation complete 3456 */ 3457 for (i = 0; i < usec_timeout; i++) { 3458 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3459 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3460 INVALIDATE_CACHE_COMPLETE)) 3461 break; 3462 udelay(1); 3463 } 3464 3465 if (i >= usec_timeout) { 3466 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3467 return -EINVAL; 3468 } 3469 3470 /* Prime the instruction caches */ 3471 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3472 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3473 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3474 3475 /* Waiting for instruction cache primed*/ 3476 for (i = 0; i < usec_timeout; i++) { 3477 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3478 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3479 ICACHE_PRIMED)) 3480 break; 3481 udelay(1); 3482 } 3483 3484 if (i >= usec_timeout) { 3485 dev_err(adev->dev, "failed to prime instruction cache\n"); 3486 return -EINVAL; 3487 } 3488 3489 mutex_lock(&adev->srbm_mutex); 3490 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3491 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3492 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3493 (me_hdr->ucode_start_addr_hi << 30) | 3494 (me_hdr->ucode_start_addr_lo >> 2) ); 3495 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3496 me_hdr->ucode_start_addr_hi>>2); 3497 3498 /* 3499 * Program CP_ME_CNTL to reset given PIPE to take 3500 * effect of CP_PFP_PRGRM_CNTR_START. 3501 */ 3502 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3503 if (pipe_id == 0) 3504 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3505 ME_PIPE0_RESET, 1); 3506 else 3507 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3508 ME_PIPE1_RESET, 1); 3509 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3510 3511 /* Clear pfp pipe0 reset bit. */ 3512 if (pipe_id == 0) 3513 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3514 ME_PIPE0_RESET, 0); 3515 else 3516 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3517 ME_PIPE1_RESET, 0); 3518 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3519 3520 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3521 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3522 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3523 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3524 } 3525 soc21_grbm_select(adev, 0, 0, 0, 0); 3526 mutex_unlock(&adev->srbm_mutex); 3527 3528 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3529 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3530 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3531 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3532 3533 /* Invalidate the data caches */ 3534 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3535 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3536 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3537 3538 for (i = 0; i < usec_timeout; i++) { 3539 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3540 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3541 INVALIDATE_DCACHE_COMPLETE)) 3542 break; 3543 udelay(1); 3544 } 3545 3546 if (i >= usec_timeout) { 3547 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3548 return -EINVAL; 3549 } 3550 3551 return 0; 3552 } 3553 3554 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3555 { 3556 int r; 3557 3558 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3559 return -EINVAL; 3560 3561 gfx_v11_0_cp_gfx_enable(adev, false); 3562 3563 if (adev->gfx.rs64_enable) 3564 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3565 else 3566 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3567 if (r) { 3568 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3569 return r; 3570 } 3571 3572 if (adev->gfx.rs64_enable) 3573 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3574 else 3575 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3576 if (r) { 3577 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3578 return r; 3579 } 3580 3581 return 0; 3582 } 3583 3584 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3585 { 3586 struct amdgpu_ring *ring; 3587 const struct cs_section_def *sect = NULL; 3588 const struct cs_extent_def *ext = NULL; 3589 int r, i; 3590 int ctx_reg_offset; 3591 3592 /* init the CP */ 3593 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3594 adev->gfx.config.max_hw_contexts - 1); 3595 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3596 3597 if (!amdgpu_async_gfx_ring) 3598 gfx_v11_0_cp_gfx_enable(adev, true); 3599 3600 ring = &adev->gfx.gfx_ring[0]; 3601 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3602 if (r) { 3603 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3604 return r; 3605 } 3606 3607 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3608 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3609 3610 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3611 amdgpu_ring_write(ring, 0x80000000); 3612 amdgpu_ring_write(ring, 0x80000000); 3613 3614 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3615 for (ext = sect->section; ext->extent != NULL; ++ext) { 3616 if (sect->id == SECT_CONTEXT) { 3617 amdgpu_ring_write(ring, 3618 PACKET3(PACKET3_SET_CONTEXT_REG, 3619 ext->reg_count)); 3620 amdgpu_ring_write(ring, ext->reg_index - 3621 PACKET3_SET_CONTEXT_REG_START); 3622 for (i = 0; i < ext->reg_count; i++) 3623 amdgpu_ring_write(ring, ext->extent[i]); 3624 } 3625 } 3626 } 3627 3628 ctx_reg_offset = 3629 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3630 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3631 amdgpu_ring_write(ring, ctx_reg_offset); 3632 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3633 3634 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3635 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3636 3637 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3638 amdgpu_ring_write(ring, 0); 3639 3640 amdgpu_ring_commit(ring); 3641 3642 /* submit cs packet to copy state 0 to next available state */ 3643 if (adev->gfx.num_gfx_rings > 1) { 3644 /* maximum supported gfx ring is 2 */ 3645 ring = &adev->gfx.gfx_ring[1]; 3646 r = amdgpu_ring_alloc(ring, 2); 3647 if (r) { 3648 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3649 return r; 3650 } 3651 3652 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3653 amdgpu_ring_write(ring, 0); 3654 3655 amdgpu_ring_commit(ring); 3656 } 3657 return 0; 3658 } 3659 3660 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3661 CP_PIPE_ID pipe) 3662 { 3663 u32 tmp; 3664 3665 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3666 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3667 3668 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3669 } 3670 3671 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3672 struct amdgpu_ring *ring) 3673 { 3674 u32 tmp; 3675 3676 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3677 if (ring->use_doorbell) { 3678 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3679 DOORBELL_OFFSET, ring->doorbell_index); 3680 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3681 DOORBELL_EN, 1); 3682 } else { 3683 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3684 DOORBELL_EN, 0); 3685 } 3686 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3687 3688 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3689 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3690 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3691 3692 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3693 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3694 } 3695 3696 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3697 { 3698 struct amdgpu_ring *ring; 3699 u32 tmp; 3700 u32 rb_bufsz; 3701 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3702 3703 /* Set the write pointer delay */ 3704 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3705 3706 /* set the RB to use vmid 0 */ 3707 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3708 3709 /* Init gfx ring 0 for pipe 0 */ 3710 mutex_lock(&adev->srbm_mutex); 3711 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3712 3713 /* Set ring buffer size */ 3714 ring = &adev->gfx.gfx_ring[0]; 3715 rb_bufsz = order_base_2(ring->ring_size / 8); 3716 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3717 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3718 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3719 3720 /* Initialize the ring buffer's write pointers */ 3721 ring->wptr = 0; 3722 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3723 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3724 3725 /* set the wb address whether it's enabled or not */ 3726 rptr_addr = ring->rptr_gpu_addr; 3727 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3728 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3729 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3730 3731 wptr_gpu_addr = ring->wptr_gpu_addr; 3732 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3733 lower_32_bits(wptr_gpu_addr)); 3734 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3735 upper_32_bits(wptr_gpu_addr)); 3736 3737 mdelay(1); 3738 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3739 3740 rb_addr = ring->gpu_addr >> 8; 3741 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3742 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3743 3744 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3745 3746 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3747 mutex_unlock(&adev->srbm_mutex); 3748 3749 /* Init gfx ring 1 for pipe 1 */ 3750 if (adev->gfx.num_gfx_rings > 1) { 3751 mutex_lock(&adev->srbm_mutex); 3752 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3753 /* maximum supported gfx ring is 2 */ 3754 ring = &adev->gfx.gfx_ring[1]; 3755 rb_bufsz = order_base_2(ring->ring_size / 8); 3756 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3757 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3758 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3759 /* Initialize the ring buffer's write pointers */ 3760 ring->wptr = 0; 3761 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3762 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3763 /* Set the wb address whether it's enabled or not */ 3764 rptr_addr = ring->rptr_gpu_addr; 3765 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3766 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3767 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3768 wptr_gpu_addr = ring->wptr_gpu_addr; 3769 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3770 lower_32_bits(wptr_gpu_addr)); 3771 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3772 upper_32_bits(wptr_gpu_addr)); 3773 3774 mdelay(1); 3775 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3776 3777 rb_addr = ring->gpu_addr >> 8; 3778 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3779 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3780 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3781 3782 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3783 mutex_unlock(&adev->srbm_mutex); 3784 } 3785 /* Switch to pipe 0 */ 3786 mutex_lock(&adev->srbm_mutex); 3787 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3788 mutex_unlock(&adev->srbm_mutex); 3789 3790 /* start the ring */ 3791 gfx_v11_0_cp_gfx_start(adev); 3792 3793 return 0; 3794 } 3795 3796 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3797 { 3798 u32 data; 3799 3800 if (adev->gfx.rs64_enable) { 3801 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3802 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3803 enable ? 0 : 1); 3804 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3805 enable ? 0 : 1); 3806 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3807 enable ? 0 : 1); 3808 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3809 enable ? 0 : 1); 3810 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3811 enable ? 0 : 1); 3812 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3813 enable ? 1 : 0); 3814 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3815 enable ? 1 : 0); 3816 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3817 enable ? 1 : 0); 3818 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3819 enable ? 1 : 0); 3820 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3821 enable ? 0 : 1); 3822 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3823 } else { 3824 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3825 3826 if (enable) { 3827 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3828 if (!adev->enable_mes_kiq) 3829 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3830 MEC_ME2_HALT, 0); 3831 } else { 3832 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3833 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3834 } 3835 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3836 } 3837 3838 udelay(50); 3839 } 3840 3841 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3842 { 3843 const struct gfx_firmware_header_v1_0 *mec_hdr; 3844 const __le32 *fw_data; 3845 unsigned i, fw_size; 3846 u32 *fw = NULL; 3847 int r; 3848 3849 if (!adev->gfx.mec_fw) 3850 return -EINVAL; 3851 3852 gfx_v11_0_cp_compute_enable(adev, false); 3853 3854 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3855 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3856 3857 fw_data = (const __le32 *) 3858 (adev->gfx.mec_fw->data + 3859 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3860 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3861 3862 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3863 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3864 &adev->gfx.mec.mec_fw_obj, 3865 &adev->gfx.mec.mec_fw_gpu_addr, 3866 (void **)&fw); 3867 if (r) { 3868 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3869 gfx_v11_0_mec_fini(adev); 3870 return r; 3871 } 3872 3873 memcpy(fw, fw_data, fw_size); 3874 3875 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3876 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3877 3878 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3879 3880 /* MEC1 */ 3881 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3882 3883 for (i = 0; i < mec_hdr->jt_size; i++) 3884 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3885 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3886 3887 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3888 3889 return 0; 3890 } 3891 3892 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3893 { 3894 const struct gfx_firmware_header_v2_0 *mec_hdr; 3895 const __le32 *fw_ucode, *fw_data; 3896 u32 tmp, fw_ucode_size, fw_data_size; 3897 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3898 u32 *fw_ucode_ptr, *fw_data_ptr; 3899 int r; 3900 3901 if (!adev->gfx.mec_fw) 3902 return -EINVAL; 3903 3904 gfx_v11_0_cp_compute_enable(adev, false); 3905 3906 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3907 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3908 3909 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3910 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3911 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3912 3913 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3914 le32_to_cpu(mec_hdr->data_offset_bytes)); 3915 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3916 3917 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3918 64 * 1024, 3919 AMDGPU_GEM_DOMAIN_VRAM | 3920 AMDGPU_GEM_DOMAIN_GTT, 3921 &adev->gfx.mec.mec_fw_obj, 3922 &adev->gfx.mec.mec_fw_gpu_addr, 3923 (void **)&fw_ucode_ptr); 3924 if (r) { 3925 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3926 gfx_v11_0_mec_fini(adev); 3927 return r; 3928 } 3929 3930 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3931 64 * 1024, 3932 AMDGPU_GEM_DOMAIN_VRAM | 3933 AMDGPU_GEM_DOMAIN_GTT, 3934 &adev->gfx.mec.mec_fw_data_obj, 3935 &adev->gfx.mec.mec_fw_data_gpu_addr, 3936 (void **)&fw_data_ptr); 3937 if (r) { 3938 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3939 gfx_v11_0_mec_fini(adev); 3940 return r; 3941 } 3942 3943 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3944 memcpy(fw_data_ptr, fw_data, fw_data_size); 3945 3946 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3947 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3948 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3949 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3950 3951 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3952 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3953 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3954 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3955 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3956 3957 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3958 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3959 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3960 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3961 3962 mutex_lock(&adev->srbm_mutex); 3963 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3964 soc21_grbm_select(adev, 1, i, 0, 0); 3965 3966 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3967 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3968 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3969 3970 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3971 mec_hdr->ucode_start_addr_lo >> 2 | 3972 mec_hdr->ucode_start_addr_hi << 30); 3973 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3974 mec_hdr->ucode_start_addr_hi >> 2); 3975 3976 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3977 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3978 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3979 } 3980 mutex_unlock(&adev->srbm_mutex); 3981 soc21_grbm_select(adev, 0, 0, 0, 0); 3982 3983 /* Trigger an invalidation of the L1 instruction caches */ 3984 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3985 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3986 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3987 3988 /* Wait for invalidation complete */ 3989 for (i = 0; i < usec_timeout; i++) { 3990 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3991 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3992 INVALIDATE_DCACHE_COMPLETE)) 3993 break; 3994 udelay(1); 3995 } 3996 3997 if (i >= usec_timeout) { 3998 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3999 return -EINVAL; 4000 } 4001 4002 /* Trigger an invalidation of the L1 instruction caches */ 4003 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4004 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 4005 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 4006 4007 /* Wait for invalidation complete */ 4008 for (i = 0; i < usec_timeout; i++) { 4009 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4010 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 4011 INVALIDATE_CACHE_COMPLETE)) 4012 break; 4013 udelay(1); 4014 } 4015 4016 if (i >= usec_timeout) { 4017 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4018 return -EINVAL; 4019 } 4020 4021 return 0; 4022 } 4023 4024 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 4025 { 4026 uint32_t tmp; 4027 struct amdgpu_device *adev = ring->adev; 4028 4029 /* tell RLC which is KIQ queue */ 4030 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4031 tmp &= 0xffffff00; 4032 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4033 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 4034 } 4035 4036 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 4037 { 4038 /* set graphics engine doorbell range */ 4039 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 4040 (adev->doorbell_index.gfx_ring0 * 2) << 2); 4041 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 4042 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 4043 4044 /* set compute engine doorbell range */ 4045 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4046 (adev->doorbell_index.kiq * 2) << 2); 4047 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4048 (adev->doorbell_index.userqueue_end * 2) << 2); 4049 } 4050 4051 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 4052 struct v11_gfx_mqd *mqd, 4053 struct amdgpu_mqd_prop *prop) 4054 { 4055 bool priority = 0; 4056 u32 tmp; 4057 4058 /* set up default queue priority level 4059 * 0x0 = low priority, 0x1 = high priority 4060 */ 4061 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 4062 priority = 1; 4063 4064 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 4065 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 4066 mqd->cp_gfx_hqd_queue_priority = tmp; 4067 } 4068 4069 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 4070 struct amdgpu_mqd_prop *prop) 4071 { 4072 struct v11_gfx_mqd *mqd = m; 4073 uint64_t hqd_gpu_addr, wb_gpu_addr; 4074 uint32_t tmp; 4075 uint32_t rb_bufsz; 4076 4077 /* set up gfx hqd wptr */ 4078 mqd->cp_gfx_hqd_wptr = 0; 4079 mqd->cp_gfx_hqd_wptr_hi = 0; 4080 4081 /* set the pointer to the MQD */ 4082 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 4083 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4084 4085 /* set up mqd control */ 4086 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4087 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4088 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4089 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4090 mqd->cp_gfx_mqd_control = tmp; 4091 4092 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4093 tmp = regCP_GFX_HQD_VMID_DEFAULT; 4094 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4095 mqd->cp_gfx_hqd_vmid = 0; 4096 4097 /* set up gfx queue priority */ 4098 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4099 4100 /* set up time quantum */ 4101 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4102 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4103 mqd->cp_gfx_hqd_quantum = tmp; 4104 4105 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4106 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4107 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4108 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4109 4110 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4111 wb_gpu_addr = prop->rptr_gpu_addr; 4112 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4113 mqd->cp_gfx_hqd_rptr_addr_hi = 4114 upper_32_bits(wb_gpu_addr) & 0xffff; 4115 4116 /* set up rb_wptr_poll addr */ 4117 wb_gpu_addr = prop->wptr_gpu_addr; 4118 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4119 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4120 4121 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4122 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4123 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4124 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4125 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4126 #ifdef __BIG_ENDIAN 4127 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4128 #endif 4129 if (prop->tmz_queue) 4130 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 4131 if (!prop->kernel_queue) 4132 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 4133 mqd->cp_gfx_hqd_cntl = tmp; 4134 4135 /* set up cp_doorbell_control */ 4136 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4137 if (prop->use_doorbell) { 4138 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4139 DOORBELL_OFFSET, prop->doorbell_index); 4140 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4141 DOORBELL_EN, 1); 4142 } else 4143 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4144 DOORBELL_EN, 0); 4145 mqd->cp_rb_doorbell_control = tmp; 4146 4147 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4148 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4149 4150 /* active the queue */ 4151 mqd->cp_gfx_hqd_active = 1; 4152 4153 /* set gfx UQ items */ 4154 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 4155 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 4156 mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr); 4157 mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr); 4158 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 4159 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 4160 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4161 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4162 4163 return 0; 4164 } 4165 4166 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 4167 { 4168 struct amdgpu_device *adev = ring->adev; 4169 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4170 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4171 4172 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4173 memset((void *)mqd, 0, sizeof(*mqd)); 4174 mutex_lock(&adev->srbm_mutex); 4175 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4176 amdgpu_ring_init_mqd(ring); 4177 soc21_grbm_select(adev, 0, 0, 0, 0); 4178 mutex_unlock(&adev->srbm_mutex); 4179 if (adev->gfx.me.mqd_backup[mqd_idx]) 4180 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4181 } else { 4182 /* restore mqd with the backup copy */ 4183 if (adev->gfx.me.mqd_backup[mqd_idx]) 4184 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4185 /* reset the ring */ 4186 ring->wptr = 0; 4187 *ring->wptr_cpu_addr = 0; 4188 amdgpu_ring_clear_ring(ring); 4189 } 4190 4191 return 0; 4192 } 4193 4194 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4195 { 4196 int r, i; 4197 4198 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4199 r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 4200 if (r) 4201 return r; 4202 } 4203 4204 r = amdgpu_gfx_enable_kgq(adev, 0); 4205 if (r) 4206 return r; 4207 4208 return gfx_v11_0_cp_gfx_start(adev); 4209 } 4210 4211 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4212 struct amdgpu_mqd_prop *prop) 4213 { 4214 struct v11_compute_mqd *mqd = m; 4215 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4216 uint32_t tmp; 4217 4218 mqd->header = 0xC0310800; 4219 mqd->compute_pipelinestat_enable = 0x00000001; 4220 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4221 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4222 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4223 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4224 mqd->compute_misc_reserved = 0x00000007; 4225 4226 eop_base_addr = prop->eop_gpu_addr >> 8; 4227 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4228 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4229 4230 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4231 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4232 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4233 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4234 4235 mqd->cp_hqd_eop_control = tmp; 4236 4237 /* enable doorbell? */ 4238 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4239 4240 if (prop->use_doorbell) { 4241 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4242 DOORBELL_OFFSET, prop->doorbell_index); 4243 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4244 DOORBELL_EN, 1); 4245 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4246 DOORBELL_SOURCE, 0); 4247 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4248 DOORBELL_HIT, 0); 4249 } else { 4250 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4251 DOORBELL_EN, 0); 4252 } 4253 4254 mqd->cp_hqd_pq_doorbell_control = tmp; 4255 4256 /* disable the queue if it's active */ 4257 mqd->cp_hqd_dequeue_request = 0; 4258 mqd->cp_hqd_pq_rptr = 0; 4259 mqd->cp_hqd_pq_wptr_lo = 0; 4260 mqd->cp_hqd_pq_wptr_hi = 0; 4261 4262 /* set the pointer to the MQD */ 4263 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4264 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4265 4266 /* set MQD vmid to 0 */ 4267 tmp = regCP_MQD_CONTROL_DEFAULT; 4268 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4269 mqd->cp_mqd_control = tmp; 4270 4271 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4272 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4273 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4274 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4275 4276 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4277 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4278 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4279 (order_base_2(prop->queue_size / 4) - 1)); 4280 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4281 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4282 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4283 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4284 prop->allow_tunneling); 4285 if (prop->kernel_queue) { 4286 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4287 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4288 } 4289 if (prop->tmz_queue) 4290 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 4291 mqd->cp_hqd_pq_control = tmp; 4292 4293 /* set the wb address whether it's enabled or not */ 4294 wb_gpu_addr = prop->rptr_gpu_addr; 4295 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4296 mqd->cp_hqd_pq_rptr_report_addr_hi = 4297 upper_32_bits(wb_gpu_addr) & 0xffff; 4298 4299 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4300 wb_gpu_addr = prop->wptr_gpu_addr; 4301 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4302 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4303 4304 tmp = 0; 4305 /* enable the doorbell if requested */ 4306 if (prop->use_doorbell) { 4307 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4308 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4309 DOORBELL_OFFSET, prop->doorbell_index); 4310 4311 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4312 DOORBELL_EN, 1); 4313 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4314 DOORBELL_SOURCE, 0); 4315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4316 DOORBELL_HIT, 0); 4317 } 4318 4319 mqd->cp_hqd_pq_doorbell_control = tmp; 4320 4321 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4322 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4323 4324 /* set the vmid for the queue */ 4325 mqd->cp_hqd_vmid = 0; 4326 4327 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4328 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4329 mqd->cp_hqd_persistent_state = tmp; 4330 4331 /* set MIN_IB_AVAIL_SIZE */ 4332 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4333 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4334 mqd->cp_hqd_ib_control = tmp; 4335 4336 /* set static priority for a compute queue/ring */ 4337 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4338 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4339 4340 mqd->cp_hqd_active = prop->hqd_active; 4341 4342 /* set UQ fenceaddress */ 4343 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4344 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4345 4346 return 0; 4347 } 4348 4349 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4350 { 4351 struct amdgpu_device *adev = ring->adev; 4352 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4353 int j; 4354 4355 /* inactivate the queue */ 4356 if (amdgpu_sriov_vf(adev)) 4357 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4358 4359 /* disable wptr polling */ 4360 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4361 4362 /* write the EOP addr */ 4363 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4364 mqd->cp_hqd_eop_base_addr_lo); 4365 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4366 mqd->cp_hqd_eop_base_addr_hi); 4367 4368 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4369 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4370 mqd->cp_hqd_eop_control); 4371 4372 /* enable doorbell? */ 4373 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4374 mqd->cp_hqd_pq_doorbell_control); 4375 4376 /* disable the queue if it's active */ 4377 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4378 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4379 for (j = 0; j < adev->usec_timeout; j++) { 4380 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4381 break; 4382 udelay(1); 4383 } 4384 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4385 mqd->cp_hqd_dequeue_request); 4386 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4387 mqd->cp_hqd_pq_rptr); 4388 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4389 mqd->cp_hqd_pq_wptr_lo); 4390 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4391 mqd->cp_hqd_pq_wptr_hi); 4392 } 4393 4394 /* set the pointer to the MQD */ 4395 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4396 mqd->cp_mqd_base_addr_lo); 4397 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4398 mqd->cp_mqd_base_addr_hi); 4399 4400 /* set MQD vmid to 0 */ 4401 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4402 mqd->cp_mqd_control); 4403 4404 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4405 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4406 mqd->cp_hqd_pq_base_lo); 4407 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4408 mqd->cp_hqd_pq_base_hi); 4409 4410 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4411 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4412 mqd->cp_hqd_pq_control); 4413 4414 /* set the wb address whether it's enabled or not */ 4415 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4416 mqd->cp_hqd_pq_rptr_report_addr_lo); 4417 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4418 mqd->cp_hqd_pq_rptr_report_addr_hi); 4419 4420 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4421 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4422 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4423 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4424 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4425 4426 /* enable the doorbell if requested */ 4427 if (ring->use_doorbell) { 4428 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4429 (adev->doorbell_index.kiq * 2) << 2); 4430 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4431 (adev->doorbell_index.userqueue_end * 2) << 2); 4432 } 4433 4434 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4435 mqd->cp_hqd_pq_doorbell_control); 4436 4437 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4438 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4439 mqd->cp_hqd_pq_wptr_lo); 4440 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4441 mqd->cp_hqd_pq_wptr_hi); 4442 4443 /* set the vmid for the queue */ 4444 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4445 4446 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4447 mqd->cp_hqd_persistent_state); 4448 4449 /* activate the queue */ 4450 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4451 mqd->cp_hqd_active); 4452 4453 if (ring->use_doorbell) 4454 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4455 4456 return 0; 4457 } 4458 4459 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4460 { 4461 struct amdgpu_device *adev = ring->adev; 4462 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4463 4464 gfx_v11_0_kiq_setting(ring); 4465 4466 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4467 /* reset MQD to a clean status */ 4468 if (adev->gfx.kiq[0].mqd_backup) 4469 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4470 4471 /* reset ring buffer */ 4472 ring->wptr = 0; 4473 amdgpu_ring_clear_ring(ring); 4474 4475 mutex_lock(&adev->srbm_mutex); 4476 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4477 gfx_v11_0_kiq_init_register(ring); 4478 soc21_grbm_select(adev, 0, 0, 0, 0); 4479 mutex_unlock(&adev->srbm_mutex); 4480 } else { 4481 memset((void *)mqd, 0, sizeof(*mqd)); 4482 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4483 amdgpu_ring_clear_ring(ring); 4484 mutex_lock(&adev->srbm_mutex); 4485 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4486 amdgpu_ring_init_mqd(ring); 4487 gfx_v11_0_kiq_init_register(ring); 4488 soc21_grbm_select(adev, 0, 0, 0, 0); 4489 mutex_unlock(&adev->srbm_mutex); 4490 4491 if (adev->gfx.kiq[0].mqd_backup) 4492 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4493 } 4494 4495 return 0; 4496 } 4497 4498 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 4499 { 4500 struct amdgpu_device *adev = ring->adev; 4501 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4502 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4503 4504 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4505 memset((void *)mqd, 0, sizeof(*mqd)); 4506 mutex_lock(&adev->srbm_mutex); 4507 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4508 amdgpu_ring_init_mqd(ring); 4509 soc21_grbm_select(adev, 0, 0, 0, 0); 4510 mutex_unlock(&adev->srbm_mutex); 4511 4512 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4513 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4514 } else { 4515 /* restore MQD to a clean status */ 4516 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4517 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4518 /* reset ring buffer */ 4519 ring->wptr = 0; 4520 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4521 amdgpu_ring_clear_ring(ring); 4522 } 4523 4524 return 0; 4525 } 4526 4527 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4528 { 4529 gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 4530 return 0; 4531 } 4532 4533 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4534 { 4535 int i, r; 4536 4537 if (!amdgpu_async_gfx_ring) 4538 gfx_v11_0_cp_compute_enable(adev, true); 4539 4540 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4541 r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 4542 if (r) 4543 return r; 4544 } 4545 4546 return amdgpu_gfx_enable_kcq(adev, 0); 4547 } 4548 4549 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4550 { 4551 int r, i; 4552 struct amdgpu_ring *ring; 4553 4554 if (!(adev->flags & AMD_IS_APU)) 4555 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4556 4557 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4558 /* legacy firmware loading */ 4559 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4560 if (r) 4561 return r; 4562 4563 if (adev->gfx.rs64_enable) 4564 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4565 else 4566 r = gfx_v11_0_cp_compute_load_microcode(adev); 4567 if (r) 4568 return r; 4569 } 4570 4571 gfx_v11_0_cp_set_doorbell_range(adev); 4572 4573 if (amdgpu_async_gfx_ring) { 4574 gfx_v11_0_cp_compute_enable(adev, true); 4575 gfx_v11_0_cp_gfx_enable(adev, true); 4576 } 4577 4578 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4579 r = amdgpu_mes_kiq_hw_init(adev); 4580 else 4581 r = gfx_v11_0_kiq_resume(adev); 4582 if (r) 4583 return r; 4584 4585 r = gfx_v11_0_kcq_resume(adev); 4586 if (r) 4587 return r; 4588 4589 if (!amdgpu_async_gfx_ring) { 4590 r = gfx_v11_0_cp_gfx_resume(adev); 4591 if (r) 4592 return r; 4593 } else { 4594 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4595 if (r) 4596 return r; 4597 } 4598 4599 if (adev->gfx.disable_kq) { 4600 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4601 ring = &adev->gfx.gfx_ring[i]; 4602 /* we don't want to set ring->ready */ 4603 r = amdgpu_ring_test_ring(ring); 4604 if (r) 4605 return r; 4606 } 4607 if (amdgpu_async_gfx_ring) 4608 amdgpu_gfx_disable_kgq(adev, 0); 4609 } else { 4610 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4611 ring = &adev->gfx.gfx_ring[i]; 4612 r = amdgpu_ring_test_helper(ring); 4613 if (r) 4614 return r; 4615 } 4616 } 4617 4618 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4619 ring = &adev->gfx.compute_ring[i]; 4620 r = amdgpu_ring_test_helper(ring); 4621 if (r) 4622 return r; 4623 } 4624 4625 return 0; 4626 } 4627 4628 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4629 { 4630 gfx_v11_0_cp_gfx_enable(adev, enable); 4631 gfx_v11_0_cp_compute_enable(adev, enable); 4632 } 4633 4634 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4635 { 4636 int r; 4637 bool value; 4638 4639 r = adev->gfxhub.funcs->gart_enable(adev); 4640 if (r) 4641 return r; 4642 4643 amdgpu_device_flush_hdp(adev, NULL); 4644 4645 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 4646 4647 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4648 /* TODO investigate why this and the hdp flush above is needed, 4649 * are we missing a flush somewhere else? */ 4650 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4651 4652 return 0; 4653 } 4654 4655 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4656 { 4657 u32 tmp; 4658 4659 /* select RS64 */ 4660 if (adev->gfx.rs64_enable) { 4661 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4662 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4663 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4664 4665 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4666 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4667 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4668 } 4669 4670 if (amdgpu_emu_mode == 1) 4671 msleep(100); 4672 } 4673 4674 static int get_gb_addr_config(struct amdgpu_device * adev) 4675 { 4676 u32 gb_addr_config; 4677 4678 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4679 if (gb_addr_config == 0) 4680 return -EINVAL; 4681 4682 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4683 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4684 4685 adev->gfx.config.gb_addr_config = gb_addr_config; 4686 4687 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4688 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4689 GB_ADDR_CONFIG, NUM_PIPES); 4690 4691 adev->gfx.config.max_tile_pipes = 4692 adev->gfx.config.gb_addr_config_fields.num_pipes; 4693 4694 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4695 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4696 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4697 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4698 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4699 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4700 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4701 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4702 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4703 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4704 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4705 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4706 4707 return 0; 4708 } 4709 4710 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4711 { 4712 uint32_t data; 4713 4714 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4715 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4716 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4717 4718 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4719 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4720 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4721 } 4722 4723 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4724 { 4725 int r; 4726 struct amdgpu_device *adev = ip_block->adev; 4727 4728 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4729 adev->gfx.cleaner_shader_ptr); 4730 4731 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4732 if (adev->gfx.imu.funcs) { 4733 /* RLC autoload sequence 1: Program rlc ram */ 4734 if (adev->gfx.imu.funcs->program_rlc_ram) 4735 adev->gfx.imu.funcs->program_rlc_ram(adev); 4736 /* rlc autoload firmware */ 4737 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4738 if (r) 4739 return r; 4740 } 4741 } else { 4742 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4743 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4744 if (adev->gfx.imu.funcs->load_microcode) 4745 adev->gfx.imu.funcs->load_microcode(adev); 4746 if (adev->gfx.imu.funcs->setup_imu) 4747 adev->gfx.imu.funcs->setup_imu(adev); 4748 if (adev->gfx.imu.funcs->start_imu) 4749 adev->gfx.imu.funcs->start_imu(adev); 4750 } 4751 4752 /* disable gpa mode in backdoor loading */ 4753 gfx_v11_0_disable_gpa_mode(adev); 4754 } 4755 } 4756 4757 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4758 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4759 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4760 if (r) { 4761 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4762 return r; 4763 } 4764 } 4765 4766 adev->gfx.is_poweron = true; 4767 4768 if(get_gb_addr_config(adev)) 4769 DRM_WARN("Invalid gb_addr_config !\n"); 4770 4771 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4772 adev->gfx.rs64_enable) 4773 gfx_v11_0_config_gfx_rs64(adev); 4774 4775 r = gfx_v11_0_gfxhub_enable(adev); 4776 if (r) 4777 return r; 4778 4779 if (!amdgpu_emu_mode) 4780 gfx_v11_0_init_golden_registers(adev); 4781 4782 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4783 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4784 /** 4785 * For gfx 11, rlc firmware loading relies on smu firmware is 4786 * loaded firstly, so in direct type, it has to load smc ucode 4787 * here before rlc. 4788 */ 4789 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4790 if (r) 4791 return r; 4792 } 4793 4794 gfx_v11_0_constants_init(adev); 4795 4796 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4797 gfx_v11_0_select_cp_fw_arch(adev); 4798 4799 if (adev->nbio.funcs->gc_doorbell_init) 4800 adev->nbio.funcs->gc_doorbell_init(adev); 4801 4802 r = gfx_v11_0_rlc_resume(adev); 4803 if (r) 4804 return r; 4805 4806 /* 4807 * init golden registers and rlc resume may override some registers, 4808 * reconfig them here 4809 */ 4810 gfx_v11_0_tcp_harvest(adev); 4811 4812 r = gfx_v11_0_cp_resume(adev); 4813 if (r) 4814 return r; 4815 4816 /* get IMU version from HW if it's not set */ 4817 if (!adev->gfx.imu_fw_version) 4818 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4819 4820 return r; 4821 } 4822 4823 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 4824 bool enable) 4825 { 4826 unsigned int irq_type; 4827 int m, p, r; 4828 4829 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 4830 for (m = 0; m < adev->gfx.me.num_me; m++) { 4831 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 4832 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4833 if (enable) 4834 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4835 irq_type); 4836 else 4837 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4838 irq_type); 4839 if (r) 4840 return r; 4841 } 4842 } 4843 } 4844 4845 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 4846 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 4847 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 4848 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4849 + (m * adev->gfx.mec.num_pipe_per_mec) 4850 + p; 4851 if (enable) 4852 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4853 irq_type); 4854 else 4855 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4856 irq_type); 4857 if (r) 4858 return r; 4859 } 4860 } 4861 } 4862 4863 return 0; 4864 } 4865 4866 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 4867 { 4868 struct amdgpu_device *adev = ip_block->adev; 4869 4870 cancel_delayed_work_sync(&adev->gfx.idle_work); 4871 4872 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4873 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4874 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4875 gfx_v11_0_set_userq_eop_interrupts(adev, false); 4876 4877 if (!adev->no_hw_access) { 4878 if (amdgpu_async_gfx_ring && 4879 !adev->gfx.disable_kq) { 4880 if (amdgpu_gfx_disable_kgq(adev, 0)) 4881 DRM_ERROR("KGQ disable failed\n"); 4882 } 4883 4884 if (amdgpu_gfx_disable_kcq(adev, 0)) 4885 DRM_ERROR("KCQ disable failed\n"); 4886 4887 amdgpu_mes_kiq_hw_fini(adev); 4888 } 4889 4890 if (amdgpu_sriov_vf(adev)) 4891 /* Remove the steps disabling CPG and clearing KIQ position, 4892 * so that CP could perform IDLE-SAVE during switch. Those 4893 * steps are necessary to avoid a DMAR error in gfx9 but it is 4894 * not reproduced on gfx11. 4895 */ 4896 return 0; 4897 4898 gfx_v11_0_cp_enable(adev, false); 4899 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4900 4901 adev->gfxhub.funcs->gart_disable(adev); 4902 4903 adev->gfx.is_poweron = false; 4904 4905 return 0; 4906 } 4907 4908 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 4909 { 4910 return gfx_v11_0_hw_fini(ip_block); 4911 } 4912 4913 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 4914 { 4915 return gfx_v11_0_hw_init(ip_block); 4916 } 4917 4918 static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 4919 { 4920 struct amdgpu_device *adev = ip_block->adev; 4921 4922 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4923 GRBM_STATUS, GUI_ACTIVE)) 4924 return false; 4925 else 4926 return true; 4927 } 4928 4929 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4930 { 4931 unsigned i; 4932 u32 tmp; 4933 struct amdgpu_device *adev = ip_block->adev; 4934 4935 for (i = 0; i < adev->usec_timeout; i++) { 4936 /* read MC_STATUS */ 4937 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4938 GRBM_STATUS__GUI_ACTIVE_MASK; 4939 4940 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4941 return 0; 4942 udelay(1); 4943 } 4944 return -ETIMEDOUT; 4945 } 4946 4947 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4948 bool req) 4949 { 4950 u32 i, tmp, val; 4951 4952 for (i = 0; i < adev->usec_timeout; i++) { 4953 /* Request with MeId=2, PipeId=0 */ 4954 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4955 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4956 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4957 4958 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4959 if (req) { 4960 if (val == tmp) 4961 break; 4962 } else { 4963 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4964 REQUEST, 1); 4965 4966 /* unlocked or locked by firmware */ 4967 if (val != tmp) 4968 break; 4969 } 4970 udelay(1); 4971 } 4972 4973 if (i >= adev->usec_timeout) 4974 return -EINVAL; 4975 4976 return 0; 4977 } 4978 4979 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 4980 { 4981 u32 grbm_soft_reset = 0; 4982 u32 tmp; 4983 int r, i, j, k; 4984 struct amdgpu_device *adev = ip_block->adev; 4985 4986 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4987 4988 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4989 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4990 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4991 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4992 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4993 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4994 4995 mutex_lock(&adev->srbm_mutex); 4996 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4997 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4998 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4999 soc21_grbm_select(adev, i, k, j, 0); 5000 5001 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 5002 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 5003 } 5004 } 5005 } 5006 for (i = 0; i < adev->gfx.me.num_me; ++i) { 5007 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 5008 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 5009 soc21_grbm_select(adev, i, k, j, 0); 5010 5011 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 5012 } 5013 } 5014 } 5015 soc21_grbm_select(adev, 0, 0, 0, 0); 5016 mutex_unlock(&adev->srbm_mutex); 5017 5018 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 5019 mutex_lock(&adev->gfx.reset_sem_mutex); 5020 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 5021 if (r) { 5022 mutex_unlock(&adev->gfx.reset_sem_mutex); 5023 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 5024 return r; 5025 } 5026 5027 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 5028 5029 // Read CP_VMID_RESET register three times. 5030 // to get sufficient time for GFX_HQD_ACTIVE reach 0 5031 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5032 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5033 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5034 5035 /* release the gfx mutex */ 5036 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 5037 mutex_unlock(&adev->gfx.reset_sem_mutex); 5038 if (r) { 5039 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 5040 return r; 5041 } 5042 5043 for (i = 0; i < adev->usec_timeout; i++) { 5044 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 5045 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 5046 break; 5047 udelay(1); 5048 } 5049 if (i >= adev->usec_timeout) { 5050 printk("Failed to wait all pipes clean\n"); 5051 return -EINVAL; 5052 } 5053 5054 /********** trigger soft reset ***********/ 5055 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5056 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5057 SOFT_RESET_CP, 1); 5058 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5059 SOFT_RESET_GFX, 1); 5060 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5061 SOFT_RESET_CPF, 1); 5062 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5063 SOFT_RESET_CPC, 1); 5064 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5065 SOFT_RESET_CPG, 1); 5066 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5067 /********** exit soft reset ***********/ 5068 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5069 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5070 SOFT_RESET_CP, 0); 5071 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5072 SOFT_RESET_GFX, 0); 5073 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5074 SOFT_RESET_CPF, 0); 5075 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5076 SOFT_RESET_CPC, 0); 5077 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5078 SOFT_RESET_CPG, 0); 5079 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5080 5081 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 5082 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 5083 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 5084 5085 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 5086 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 5087 5088 for (i = 0; i < adev->usec_timeout; i++) { 5089 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 5090 break; 5091 udelay(1); 5092 } 5093 if (i >= adev->usec_timeout) { 5094 printk("Failed to wait CP_VMID_RESET to 0\n"); 5095 return -EINVAL; 5096 } 5097 5098 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5099 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5100 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5101 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5102 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5103 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5104 5105 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5106 5107 return gfx_v11_0_cp_resume(adev); 5108 } 5109 5110 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 5111 { 5112 int i, r; 5113 struct amdgpu_device *adev = ip_block->adev; 5114 struct amdgpu_ring *ring; 5115 long tmo = msecs_to_jiffies(1000); 5116 5117 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5118 ring = &adev->gfx.gfx_ring[i]; 5119 r = amdgpu_ring_test_ib(ring, tmo); 5120 if (r) 5121 return true; 5122 } 5123 5124 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5125 ring = &adev->gfx.compute_ring[i]; 5126 r = amdgpu_ring_test_ib(ring, tmo); 5127 if (r) 5128 return true; 5129 } 5130 5131 return false; 5132 } 5133 5134 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5135 { 5136 struct amdgpu_device *adev = ip_block->adev; 5137 /** 5138 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 5139 */ 5140 return amdgpu_mes_resume(adev); 5141 } 5142 5143 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5144 { 5145 uint64_t clock; 5146 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5147 5148 if (amdgpu_sriov_vf(adev)) { 5149 amdgpu_gfx_off_ctrl(adev, false); 5150 mutex_lock(&adev->gfx.gpu_clock_mutex); 5151 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5152 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5153 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5154 if (clock_counter_hi_pre != clock_counter_hi_after) 5155 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5156 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5157 amdgpu_gfx_off_ctrl(adev, true); 5158 } else { 5159 preempt_disable(); 5160 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5161 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5162 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5163 if (clock_counter_hi_pre != clock_counter_hi_after) 5164 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5165 preempt_enable(); 5166 } 5167 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5168 5169 return clock; 5170 } 5171 5172 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5173 uint32_t vmid, 5174 uint32_t gds_base, uint32_t gds_size, 5175 uint32_t gws_base, uint32_t gws_size, 5176 uint32_t oa_base, uint32_t oa_size) 5177 { 5178 struct amdgpu_device *adev = ring->adev; 5179 5180 /* GDS Base */ 5181 gfx_v11_0_write_data_to_reg(ring, 0, false, 5182 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5183 gds_base); 5184 5185 /* GDS Size */ 5186 gfx_v11_0_write_data_to_reg(ring, 0, false, 5187 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5188 gds_size); 5189 5190 /* GWS */ 5191 gfx_v11_0_write_data_to_reg(ring, 0, false, 5192 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5193 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5194 5195 /* OA */ 5196 gfx_v11_0_write_data_to_reg(ring, 0, false, 5197 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5198 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5199 } 5200 5201 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5202 { 5203 struct amdgpu_device *adev = ip_block->adev; 5204 5205 switch (amdgpu_user_queue) { 5206 case -1: 5207 case 0: 5208 default: 5209 adev->gfx.disable_kq = false; 5210 adev->gfx.disable_uq = true; 5211 break; 5212 case 1: 5213 adev->gfx.disable_kq = false; 5214 adev->gfx.disable_uq = false; 5215 break; 5216 case 2: 5217 adev->gfx.disable_kq = true; 5218 adev->gfx.disable_uq = false; 5219 break; 5220 } 5221 5222 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5223 5224 if (adev->gfx.disable_kq) { 5225 /* We need one GFX ring temporarily to set up 5226 * the clear state. 5227 */ 5228 adev->gfx.num_gfx_rings = 1; 5229 adev->gfx.num_compute_rings = 0; 5230 } else { 5231 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5232 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5233 AMDGPU_MAX_COMPUTE_RINGS); 5234 } 5235 5236 gfx_v11_0_set_kiq_pm4_funcs(adev); 5237 gfx_v11_0_set_ring_funcs(adev); 5238 gfx_v11_0_set_irq_funcs(adev); 5239 gfx_v11_0_set_gds_init(adev); 5240 gfx_v11_0_set_rlc_funcs(adev); 5241 gfx_v11_0_set_mqd_funcs(adev); 5242 gfx_v11_0_set_imu_funcs(adev); 5243 5244 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5245 5246 return gfx_v11_0_init_microcode(adev); 5247 } 5248 5249 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) 5250 { 5251 struct amdgpu_device *adev = ip_block->adev; 5252 int r; 5253 5254 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5255 if (r) 5256 return r; 5257 5258 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5259 if (r) 5260 return r; 5261 5262 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5263 if (r) 5264 return r; 5265 5266 r = gfx_v11_0_set_userq_eop_interrupts(adev, true); 5267 if (r) 5268 return r; 5269 5270 return 0; 5271 } 5272 5273 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5274 { 5275 uint32_t rlc_cntl; 5276 5277 /* if RLC is not enabled, do nothing */ 5278 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5279 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5280 } 5281 5282 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5283 { 5284 uint32_t data; 5285 unsigned i; 5286 5287 data = RLC_SAFE_MODE__CMD_MASK; 5288 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5289 5290 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5291 5292 /* wait for RLC_SAFE_MODE */ 5293 for (i = 0; i < adev->usec_timeout; i++) { 5294 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5295 RLC_SAFE_MODE, CMD)) 5296 break; 5297 udelay(1); 5298 } 5299 } 5300 5301 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5302 { 5303 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5304 } 5305 5306 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5307 bool enable) 5308 { 5309 uint32_t def, data; 5310 5311 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5312 return; 5313 5314 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5315 5316 if (enable) 5317 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5318 else 5319 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5320 5321 if (def != data) 5322 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5323 } 5324 5325 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5326 bool enable) 5327 { 5328 uint32_t def, data; 5329 5330 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5331 return; 5332 5333 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5334 5335 if (enable) 5336 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5337 else 5338 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5339 5340 if (def != data) 5341 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5342 } 5343 5344 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5345 bool enable) 5346 { 5347 uint32_t def, data; 5348 5349 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5350 return; 5351 5352 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5353 5354 if (enable) 5355 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5356 else 5357 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5358 5359 if (def != data) 5360 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5361 } 5362 5363 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5364 bool enable) 5365 { 5366 uint32_t data, def; 5367 5368 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5369 return; 5370 5371 /* It is disabled by HW by default */ 5372 if (enable) { 5373 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5374 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5375 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5376 5377 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5378 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5379 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5380 5381 if (def != data) 5382 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5383 } 5384 } else { 5385 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5386 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5387 5388 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5389 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5390 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5391 5392 if (def != data) 5393 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5394 } 5395 } 5396 } 5397 5398 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5399 bool enable) 5400 { 5401 uint32_t def, data; 5402 5403 if (!(adev->cg_flags & 5404 (AMD_CG_SUPPORT_GFX_CGCG | 5405 AMD_CG_SUPPORT_GFX_CGLS | 5406 AMD_CG_SUPPORT_GFX_3D_CGCG | 5407 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5408 return; 5409 5410 if (enable) { 5411 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5412 5413 /* unset CGCG override */ 5414 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5415 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5416 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5417 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5418 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5419 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5420 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5421 5422 /* update CGCG override bits */ 5423 if (def != data) 5424 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5425 5426 /* enable cgcg FSM(0x0000363F) */ 5427 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5428 5429 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5430 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5431 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5432 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5433 } 5434 5435 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5436 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5437 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5438 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5439 } 5440 5441 if (def != data) 5442 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5443 5444 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5445 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5446 5447 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5448 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5449 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5450 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5451 } 5452 5453 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5454 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5455 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5456 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5457 } 5458 5459 if (def != data) 5460 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5461 5462 /* set IDLE_POLL_COUNT(0x00900100) */ 5463 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5464 5465 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5466 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5467 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5468 5469 if (def != data) 5470 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5471 5472 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5473 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5474 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5475 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5476 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5477 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5478 5479 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5480 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5481 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5482 5483 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5484 if (adev->sdma.num_instances > 1) { 5485 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5486 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5487 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5488 } 5489 } else { 5490 /* Program RLC_CGCG_CGLS_CTRL */ 5491 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5492 5493 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5494 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5495 5496 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5497 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5498 5499 if (def != data) 5500 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5501 5502 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5503 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5504 5505 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5506 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5507 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5508 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5509 5510 if (def != data) 5511 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5512 5513 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5514 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5515 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5516 5517 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5518 if (adev->sdma.num_instances > 1) { 5519 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5520 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5521 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5522 } 5523 } 5524 } 5525 5526 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5527 bool enable) 5528 { 5529 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5530 5531 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5532 5533 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5534 5535 gfx_v11_0_update_repeater_fgcg(adev, enable); 5536 5537 gfx_v11_0_update_sram_fgcg(adev, enable); 5538 5539 gfx_v11_0_update_perf_clk(adev, enable); 5540 5541 if (adev->cg_flags & 5542 (AMD_CG_SUPPORT_GFX_MGCG | 5543 AMD_CG_SUPPORT_GFX_CGLS | 5544 AMD_CG_SUPPORT_GFX_CGCG | 5545 AMD_CG_SUPPORT_GFX_3D_CGCG | 5546 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5547 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5548 5549 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5550 5551 return 0; 5552 } 5553 5554 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5555 { 5556 u32 reg, pre_data, data; 5557 5558 amdgpu_gfx_off_ctrl(adev, false); 5559 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5560 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5561 pre_data = RREG32_NO_KIQ(reg); 5562 else 5563 pre_data = RREG32(reg); 5564 5565 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5566 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5567 5568 if (pre_data != data) { 5569 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5570 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5571 } else 5572 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5573 } 5574 amdgpu_gfx_off_ctrl(adev, true); 5575 5576 if (ring 5577 && amdgpu_sriov_is_pp_one_vf(adev) 5578 && (pre_data != data) 5579 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5580 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5581 amdgpu_ring_emit_wreg(ring, reg, data); 5582 } 5583 } 5584 5585 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5586 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5587 .set_safe_mode = gfx_v11_0_set_safe_mode, 5588 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5589 .init = gfx_v11_0_rlc_init, 5590 .get_csb_size = gfx_v11_0_get_csb_size, 5591 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5592 .resume = gfx_v11_0_rlc_resume, 5593 .stop = gfx_v11_0_rlc_stop, 5594 .reset = gfx_v11_0_rlc_reset, 5595 .start = gfx_v11_0_rlc_start, 5596 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5597 }; 5598 5599 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5600 { 5601 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5602 5603 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5604 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5605 else 5606 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5607 5608 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5609 5610 // Program RLC_PG_DELAY3 for CGPG hysteresis 5611 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5612 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5613 case IP_VERSION(11, 0, 1): 5614 case IP_VERSION(11, 0, 4): 5615 case IP_VERSION(11, 5, 0): 5616 case IP_VERSION(11, 5, 1): 5617 case IP_VERSION(11, 5, 2): 5618 case IP_VERSION(11, 5, 3): 5619 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5620 break; 5621 default: 5622 break; 5623 } 5624 } 5625 } 5626 5627 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5628 { 5629 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5630 5631 gfx_v11_cntl_power_gating(adev, enable); 5632 5633 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5634 } 5635 5636 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5637 enum amd_powergating_state state) 5638 { 5639 struct amdgpu_device *adev = ip_block->adev; 5640 bool enable = (state == AMD_PG_STATE_GATE); 5641 5642 if (amdgpu_sriov_vf(adev)) 5643 return 0; 5644 5645 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5646 case IP_VERSION(11, 0, 0): 5647 case IP_VERSION(11, 0, 2): 5648 case IP_VERSION(11, 0, 3): 5649 amdgpu_gfx_off_ctrl(adev, enable); 5650 break; 5651 case IP_VERSION(11, 0, 1): 5652 case IP_VERSION(11, 0, 4): 5653 case IP_VERSION(11, 5, 0): 5654 case IP_VERSION(11, 5, 1): 5655 case IP_VERSION(11, 5, 2): 5656 case IP_VERSION(11, 5, 3): 5657 if (!enable) 5658 amdgpu_gfx_off_ctrl(adev, false); 5659 5660 gfx_v11_cntl_pg(adev, enable); 5661 5662 if (enable) 5663 amdgpu_gfx_off_ctrl(adev, true); 5664 5665 break; 5666 default: 5667 break; 5668 } 5669 5670 return 0; 5671 } 5672 5673 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5674 enum amd_clockgating_state state) 5675 { 5676 struct amdgpu_device *adev = ip_block->adev; 5677 5678 if (amdgpu_sriov_vf(adev)) 5679 return 0; 5680 5681 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5682 case IP_VERSION(11, 0, 0): 5683 case IP_VERSION(11, 0, 1): 5684 case IP_VERSION(11, 0, 2): 5685 case IP_VERSION(11, 0, 3): 5686 case IP_VERSION(11, 0, 4): 5687 case IP_VERSION(11, 5, 0): 5688 case IP_VERSION(11, 5, 1): 5689 case IP_VERSION(11, 5, 2): 5690 case IP_VERSION(11, 5, 3): 5691 gfx_v11_0_update_gfx_clock_gating(adev, 5692 state == AMD_CG_STATE_GATE); 5693 break; 5694 default: 5695 break; 5696 } 5697 5698 return 0; 5699 } 5700 5701 static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 5702 { 5703 struct amdgpu_device *adev = ip_block->adev; 5704 int data; 5705 5706 /* AMD_CG_SUPPORT_GFX_MGCG */ 5707 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5708 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5709 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5710 5711 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5712 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5713 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5714 5715 /* AMD_CG_SUPPORT_GFX_FGCG */ 5716 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5717 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5718 5719 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5720 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5721 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5722 5723 /* AMD_CG_SUPPORT_GFX_CGCG */ 5724 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5725 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5726 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5727 5728 /* AMD_CG_SUPPORT_GFX_CGLS */ 5729 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5730 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5731 5732 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5733 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5734 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5735 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5736 5737 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5738 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5739 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5740 } 5741 5742 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5743 { 5744 /* gfx11 is 32bit rptr*/ 5745 return *(uint32_t *)ring->rptr_cpu_addr; 5746 } 5747 5748 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5749 { 5750 struct amdgpu_device *adev = ring->adev; 5751 u64 wptr; 5752 5753 /* XXX check if swapping is necessary on BE */ 5754 if (ring->use_doorbell) { 5755 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5756 } else { 5757 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5758 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5759 } 5760 5761 return wptr; 5762 } 5763 5764 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5765 { 5766 struct amdgpu_device *adev = ring->adev; 5767 5768 if (ring->use_doorbell) { 5769 /* XXX check if swapping is necessary on BE */ 5770 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5771 ring->wptr); 5772 WDOORBELL64(ring->doorbell_index, ring->wptr); 5773 } else { 5774 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5775 lower_32_bits(ring->wptr)); 5776 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5777 upper_32_bits(ring->wptr)); 5778 } 5779 } 5780 5781 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5782 { 5783 /* gfx11 hardware is 32bit rptr */ 5784 return *(uint32_t *)ring->rptr_cpu_addr; 5785 } 5786 5787 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5788 { 5789 u64 wptr; 5790 5791 /* XXX check if swapping is necessary on BE */ 5792 if (ring->use_doorbell) 5793 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5794 else 5795 BUG(); 5796 return wptr; 5797 } 5798 5799 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5800 { 5801 struct amdgpu_device *adev = ring->adev; 5802 5803 /* XXX check if swapping is necessary on BE */ 5804 if (ring->use_doorbell) { 5805 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5806 ring->wptr); 5807 WDOORBELL64(ring->doorbell_index, ring->wptr); 5808 } else { 5809 BUG(); /* only DOORBELL method supported on gfx11 now */ 5810 } 5811 } 5812 5813 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5814 { 5815 struct amdgpu_device *adev = ring->adev; 5816 u32 ref_and_mask, reg_mem_engine; 5817 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5818 5819 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5820 switch (ring->me) { 5821 case 1: 5822 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5823 break; 5824 case 2: 5825 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5826 break; 5827 default: 5828 return; 5829 } 5830 reg_mem_engine = 0; 5831 } else { 5832 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5833 reg_mem_engine = 1; /* pfp */ 5834 } 5835 5836 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5837 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5838 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5839 ref_and_mask, ref_and_mask, 0x20); 5840 } 5841 5842 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5843 struct amdgpu_job *job, 5844 struct amdgpu_ib *ib, 5845 uint32_t flags) 5846 { 5847 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5848 u32 header, control = 0; 5849 5850 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5851 5852 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5853 5854 control |= ib->length_dw | (vmid << 24); 5855 5856 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5857 control |= INDIRECT_BUFFER_PRE_ENB(1); 5858 5859 if (flags & AMDGPU_IB_PREEMPTED) 5860 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5861 5862 if (vmid) 5863 gfx_v11_0_ring_emit_de_meta(ring, 5864 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5865 } 5866 5867 amdgpu_ring_write(ring, header); 5868 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5869 amdgpu_ring_write(ring, 5870 #ifdef __BIG_ENDIAN 5871 (2 << 0) | 5872 #endif 5873 lower_32_bits(ib->gpu_addr)); 5874 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5875 amdgpu_ring_write(ring, control); 5876 } 5877 5878 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5879 struct amdgpu_job *job, 5880 struct amdgpu_ib *ib, 5881 uint32_t flags) 5882 { 5883 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5884 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5885 5886 /* Currently, there is a high possibility to get wave ID mismatch 5887 * between ME and GDS, leading to a hw deadlock, because ME generates 5888 * different wave IDs than the GDS expects. This situation happens 5889 * randomly when at least 5 compute pipes use GDS ordered append. 5890 * The wave IDs generated by ME are also wrong after suspend/resume. 5891 * Those are probably bugs somewhere else in the kernel driver. 5892 * 5893 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5894 * GDS to 0 for this ring (me/pipe). 5895 */ 5896 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5897 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5898 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5899 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5900 } 5901 5902 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5903 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5904 amdgpu_ring_write(ring, 5905 #ifdef __BIG_ENDIAN 5906 (2 << 0) | 5907 #endif 5908 lower_32_bits(ib->gpu_addr)); 5909 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5910 amdgpu_ring_write(ring, control); 5911 } 5912 5913 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5914 u64 seq, unsigned flags) 5915 { 5916 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5917 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5918 5919 /* RELEASE_MEM - flush caches, send int */ 5920 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5921 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5922 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5923 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5924 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5925 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5926 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5927 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5928 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5929 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5930 5931 /* 5932 * the address should be Qword aligned if 64bit write, Dword 5933 * aligned if only send 32bit data low (discard data high) 5934 */ 5935 if (write64bit) 5936 BUG_ON(addr & 0x7); 5937 else 5938 BUG_ON(addr & 0x3); 5939 amdgpu_ring_write(ring, lower_32_bits(addr)); 5940 amdgpu_ring_write(ring, upper_32_bits(addr)); 5941 amdgpu_ring_write(ring, lower_32_bits(seq)); 5942 amdgpu_ring_write(ring, upper_32_bits(seq)); 5943 amdgpu_ring_write(ring, 0); 5944 } 5945 5946 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5947 { 5948 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5949 uint32_t seq = ring->fence_drv.sync_seq; 5950 uint64_t addr = ring->fence_drv.gpu_addr; 5951 5952 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5953 upper_32_bits(addr), seq, 0xffffffff, 4); 5954 } 5955 5956 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5957 uint16_t pasid, uint32_t flush_type, 5958 bool all_hub, uint8_t dst_sel) 5959 { 5960 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5961 amdgpu_ring_write(ring, 5962 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5963 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5964 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5965 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5966 } 5967 5968 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5969 unsigned vmid, uint64_t pd_addr) 5970 { 5971 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5972 5973 /* compute doesn't have PFP */ 5974 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5975 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5976 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5977 amdgpu_ring_write(ring, 0x0); 5978 } 5979 5980 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5981 * changed in any way. 5982 */ 5983 ring->set_q_mode_offs = 0; 5984 ring->set_q_mode_ptr = NULL; 5985 } 5986 5987 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5988 u64 seq, unsigned int flags) 5989 { 5990 struct amdgpu_device *adev = ring->adev; 5991 5992 /* we only allocate 32bit for each seq wb address */ 5993 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5994 5995 /* write fence seq to the "addr" */ 5996 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5997 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5998 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5999 amdgpu_ring_write(ring, lower_32_bits(addr)); 6000 amdgpu_ring_write(ring, upper_32_bits(addr)); 6001 amdgpu_ring_write(ring, lower_32_bits(seq)); 6002 6003 if (flags & AMDGPU_FENCE_FLAG_INT) { 6004 /* set register to trigger INT */ 6005 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6006 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6007 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 6008 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 6009 amdgpu_ring_write(ring, 0); 6010 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 6011 } 6012 } 6013 6014 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 6015 uint32_t flags) 6016 { 6017 uint32_t dw2 = 0; 6018 6019 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6020 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6021 /* set load_global_config & load_global_uconfig */ 6022 dw2 |= 0x8001; 6023 /* set load_cs_sh_regs */ 6024 dw2 |= 0x01000000; 6025 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 6026 dw2 |= 0x10002; 6027 } 6028 6029 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6030 amdgpu_ring_write(ring, dw2); 6031 amdgpu_ring_write(ring, 0); 6032 } 6033 6034 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 6035 uint64_t addr) 6036 { 6037 unsigned ret; 6038 6039 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6040 amdgpu_ring_write(ring, lower_32_bits(addr)); 6041 amdgpu_ring_write(ring, upper_32_bits(addr)); 6042 /* discard following DWs if *cond_exec_gpu_addr==0 */ 6043 amdgpu_ring_write(ring, 0); 6044 ret = ring->wptr & ring->buf_mask; 6045 /* patch dummy value later */ 6046 amdgpu_ring_write(ring, 0); 6047 6048 return ret; 6049 } 6050 6051 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 6052 u64 shadow_va, u64 csa_va, 6053 u64 gds_va, bool init_shadow, 6054 int vmid) 6055 { 6056 struct amdgpu_device *adev = ring->adev; 6057 unsigned int offs, end; 6058 6059 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 6060 return; 6061 6062 /* 6063 * The logic here isn't easy to understand because we need to keep state 6064 * accross multiple executions of the function as well as between the 6065 * CPU and GPU. The general idea is that the newly written GPU command 6066 * has a condition on the previous one and only executed if really 6067 * necessary. 6068 */ 6069 6070 /* 6071 * The dw in the NOP controls if the next SET_Q_MODE packet should be 6072 * executed or not. Reserve 64bits just to be on the save side. 6073 */ 6074 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 6075 offs = ring->wptr & ring->buf_mask; 6076 6077 /* 6078 * We start with skipping the prefix SET_Q_MODE and always executing 6079 * the postfix SET_Q_MODE packet. This is changed below with a 6080 * WRITE_DATA command when the postfix executed. 6081 */ 6082 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 6083 amdgpu_ring_write(ring, 0); 6084 6085 if (ring->set_q_mode_offs) { 6086 uint64_t addr; 6087 6088 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6089 addr += ring->set_q_mode_offs << 2; 6090 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 6091 } 6092 6093 /* 6094 * When the postfix SET_Q_MODE packet executes we need to make sure that the 6095 * next prefix SET_Q_MODE packet executes as well. 6096 */ 6097 if (!shadow_va) { 6098 uint64_t addr; 6099 6100 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6101 addr += offs << 2; 6102 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6103 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 6104 amdgpu_ring_write(ring, lower_32_bits(addr)); 6105 amdgpu_ring_write(ring, upper_32_bits(addr)); 6106 amdgpu_ring_write(ring, 0x1); 6107 } 6108 6109 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 6110 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 6111 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 6112 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 6113 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 6114 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 6115 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 6116 amdgpu_ring_write(ring, shadow_va ? 6117 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 6118 amdgpu_ring_write(ring, init_shadow ? 6119 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 6120 6121 if (ring->set_q_mode_offs) 6122 amdgpu_ring_patch_cond_exec(ring, end); 6123 6124 if (shadow_va) { 6125 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 6126 6127 /* 6128 * If the tokens match try to skip the last postfix SET_Q_MODE 6129 * packet to avoid saving/restoring the state all the time. 6130 */ 6131 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 6132 *ring->set_q_mode_ptr = 0; 6133 6134 ring->set_q_mode_token = token; 6135 } else { 6136 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 6137 } 6138 6139 ring->set_q_mode_offs = offs; 6140 } 6141 6142 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 6143 { 6144 int i, r = 0; 6145 struct amdgpu_device *adev = ring->adev; 6146 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6147 struct amdgpu_ring *kiq_ring = &kiq->ring; 6148 unsigned long flags; 6149 6150 if (adev->enable_mes) 6151 return -EINVAL; 6152 6153 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6154 return -EINVAL; 6155 6156 spin_lock_irqsave(&kiq->ring_lock, flags); 6157 6158 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 6159 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6160 return -ENOMEM; 6161 } 6162 6163 /* assert preemption condition */ 6164 amdgpu_ring_set_preempt_cond_exec(ring, false); 6165 6166 /* assert IB preemption, emit the trailing fence */ 6167 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 6168 ring->trail_fence_gpu_addr, 6169 ++ring->trail_seq); 6170 amdgpu_ring_commit(kiq_ring); 6171 6172 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6173 6174 /* poll the trailing fence */ 6175 for (i = 0; i < adev->usec_timeout; i++) { 6176 if (ring->trail_seq == 6177 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 6178 break; 6179 udelay(1); 6180 } 6181 6182 if (i >= adev->usec_timeout) { 6183 r = -EINVAL; 6184 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 6185 } 6186 6187 /* deassert preemption condition */ 6188 amdgpu_ring_set_preempt_cond_exec(ring, true); 6189 return r; 6190 } 6191 6192 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6193 { 6194 struct amdgpu_device *adev = ring->adev; 6195 struct v10_de_ib_state de_payload = {0}; 6196 uint64_t offset, gds_addr, de_payload_gpu_addr; 6197 void *de_payload_cpu_addr; 6198 int cnt; 6199 6200 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6201 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6202 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6203 6204 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6205 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6206 PAGE_SIZE); 6207 6208 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6209 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6210 6211 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6212 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6213 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6214 WRITE_DATA_DST_SEL(8) | 6215 WR_CONFIRM) | 6216 WRITE_DATA_CACHE_POLICY(0)); 6217 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6218 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6219 6220 if (resume) 6221 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6222 sizeof(de_payload) >> 2); 6223 else 6224 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6225 sizeof(de_payload) >> 2); 6226 } 6227 6228 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6229 bool secure) 6230 { 6231 uint32_t v = secure ? FRAME_TMZ : 0; 6232 6233 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6234 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6235 } 6236 6237 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6238 uint32_t reg_val_offs) 6239 { 6240 struct amdgpu_device *adev = ring->adev; 6241 6242 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6243 amdgpu_ring_write(ring, 0 | /* src: register*/ 6244 (5 << 8) | /* dst: memory */ 6245 (1 << 20)); /* write confirm */ 6246 amdgpu_ring_write(ring, reg); 6247 amdgpu_ring_write(ring, 0); 6248 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6249 reg_val_offs * 4)); 6250 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6251 reg_val_offs * 4)); 6252 } 6253 6254 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6255 uint32_t val) 6256 { 6257 uint32_t cmd = 0; 6258 6259 switch (ring->funcs->type) { 6260 case AMDGPU_RING_TYPE_GFX: 6261 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6262 break; 6263 case AMDGPU_RING_TYPE_KIQ: 6264 cmd = (1 << 16); /* no inc addr */ 6265 break; 6266 default: 6267 cmd = WR_CONFIRM; 6268 break; 6269 } 6270 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6271 amdgpu_ring_write(ring, cmd); 6272 amdgpu_ring_write(ring, reg); 6273 amdgpu_ring_write(ring, 0); 6274 amdgpu_ring_write(ring, val); 6275 } 6276 6277 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6278 uint32_t val, uint32_t mask) 6279 { 6280 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6281 } 6282 6283 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6284 uint32_t reg0, uint32_t reg1, 6285 uint32_t ref, uint32_t mask) 6286 { 6287 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6288 6289 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6290 ref, mask, 0x20); 6291 } 6292 6293 static void 6294 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6295 uint32_t me, uint32_t pipe, 6296 enum amdgpu_interrupt_state state) 6297 { 6298 uint32_t cp_int_cntl, cp_int_cntl_reg; 6299 6300 if (!me) { 6301 switch (pipe) { 6302 case 0: 6303 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6304 break; 6305 case 1: 6306 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6307 break; 6308 default: 6309 DRM_DEBUG("invalid pipe %d\n", pipe); 6310 return; 6311 } 6312 } else { 6313 DRM_DEBUG("invalid me %d\n", me); 6314 return; 6315 } 6316 6317 switch (state) { 6318 case AMDGPU_IRQ_STATE_DISABLE: 6319 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6320 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6321 TIME_STAMP_INT_ENABLE, 0); 6322 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6323 GENERIC0_INT_ENABLE, 0); 6324 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6325 break; 6326 case AMDGPU_IRQ_STATE_ENABLE: 6327 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6328 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6329 TIME_STAMP_INT_ENABLE, 1); 6330 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6331 GENERIC0_INT_ENABLE, 1); 6332 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6333 break; 6334 default: 6335 break; 6336 } 6337 } 6338 6339 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6340 int me, int pipe, 6341 enum amdgpu_interrupt_state state) 6342 { 6343 u32 mec_int_cntl, mec_int_cntl_reg; 6344 6345 /* 6346 * amdgpu controls only the first MEC. That's why this function only 6347 * handles the setting of interrupts for this specific MEC. All other 6348 * pipes' interrupts are set by amdkfd. 6349 */ 6350 6351 if (me == 1) { 6352 switch (pipe) { 6353 case 0: 6354 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6355 break; 6356 case 1: 6357 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6358 break; 6359 case 2: 6360 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6361 break; 6362 case 3: 6363 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6364 break; 6365 default: 6366 DRM_DEBUG("invalid pipe %d\n", pipe); 6367 return; 6368 } 6369 } else { 6370 DRM_DEBUG("invalid me %d\n", me); 6371 return; 6372 } 6373 6374 switch (state) { 6375 case AMDGPU_IRQ_STATE_DISABLE: 6376 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6377 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6378 TIME_STAMP_INT_ENABLE, 0); 6379 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6380 GENERIC0_INT_ENABLE, 0); 6381 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6382 break; 6383 case AMDGPU_IRQ_STATE_ENABLE: 6384 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6385 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6386 TIME_STAMP_INT_ENABLE, 1); 6387 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6388 GENERIC0_INT_ENABLE, 1); 6389 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6390 break; 6391 default: 6392 break; 6393 } 6394 } 6395 6396 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6397 struct amdgpu_irq_src *src, 6398 unsigned type, 6399 enum amdgpu_interrupt_state state) 6400 { 6401 switch (type) { 6402 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6403 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6404 break; 6405 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6406 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6407 break; 6408 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6409 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6410 break; 6411 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6412 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6413 break; 6414 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6415 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6416 break; 6417 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6418 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6419 break; 6420 default: 6421 break; 6422 } 6423 return 0; 6424 } 6425 6426 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6427 struct amdgpu_irq_src *source, 6428 struct amdgpu_iv_entry *entry) 6429 { 6430 u32 doorbell_offset = entry->src_data[0]; 6431 u8 me_id, pipe_id, queue_id; 6432 struct amdgpu_ring *ring; 6433 int i; 6434 6435 DRM_DEBUG("IH: CP EOP\n"); 6436 6437 if (adev->enable_mes && doorbell_offset) { 6438 struct amdgpu_userq_fence_driver *fence_drv = NULL; 6439 struct xarray *xa = &adev->userq_xa; 6440 unsigned long flags; 6441 6442 xa_lock_irqsave(xa, flags); 6443 fence_drv = xa_load(xa, doorbell_offset); 6444 if (fence_drv) 6445 amdgpu_userq_fence_driver_process(fence_drv); 6446 xa_unlock_irqrestore(xa, flags); 6447 } else { 6448 me_id = (entry->ring_id & 0x0c) >> 2; 6449 pipe_id = (entry->ring_id & 0x03) >> 0; 6450 queue_id = (entry->ring_id & 0x70) >> 4; 6451 6452 switch (me_id) { 6453 case 0: 6454 if (pipe_id == 0) 6455 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6456 else 6457 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6458 break; 6459 case 1: 6460 case 2: 6461 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6462 ring = &adev->gfx.compute_ring[i]; 6463 /* Per-queue interrupt is supported for MEC starting from VI. 6464 * The interrupt can only be enabled/disabled per pipe instead 6465 * of per queue. 6466 */ 6467 if ((ring->me == me_id) && 6468 (ring->pipe == pipe_id) && 6469 (ring->queue == queue_id)) 6470 amdgpu_fence_process(ring); 6471 } 6472 break; 6473 } 6474 } 6475 6476 return 0; 6477 } 6478 6479 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6480 struct amdgpu_irq_src *source, 6481 unsigned int type, 6482 enum amdgpu_interrupt_state state) 6483 { 6484 u32 cp_int_cntl_reg, cp_int_cntl; 6485 int i, j; 6486 6487 switch (state) { 6488 case AMDGPU_IRQ_STATE_DISABLE: 6489 case AMDGPU_IRQ_STATE_ENABLE: 6490 for (i = 0; i < adev->gfx.me.num_me; i++) { 6491 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6492 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6493 6494 if (cp_int_cntl_reg) { 6495 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6496 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6497 PRIV_REG_INT_ENABLE, 6498 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6499 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6500 } 6501 } 6502 } 6503 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6504 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6505 /* MECs start at 1 */ 6506 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6507 6508 if (cp_int_cntl_reg) { 6509 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6510 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6511 PRIV_REG_INT_ENABLE, 6512 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6513 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6514 } 6515 } 6516 } 6517 break; 6518 default: 6519 break; 6520 } 6521 6522 return 0; 6523 } 6524 6525 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6526 struct amdgpu_irq_src *source, 6527 unsigned type, 6528 enum amdgpu_interrupt_state state) 6529 { 6530 u32 cp_int_cntl_reg, cp_int_cntl; 6531 int i, j; 6532 6533 switch (state) { 6534 case AMDGPU_IRQ_STATE_DISABLE: 6535 case AMDGPU_IRQ_STATE_ENABLE: 6536 for (i = 0; i < adev->gfx.me.num_me; i++) { 6537 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6538 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6539 6540 if (cp_int_cntl_reg) { 6541 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6542 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6543 OPCODE_ERROR_INT_ENABLE, 6544 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6545 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6546 } 6547 } 6548 } 6549 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6550 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6551 /* MECs start at 1 */ 6552 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6553 6554 if (cp_int_cntl_reg) { 6555 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6556 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6557 OPCODE_ERROR_INT_ENABLE, 6558 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6559 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6560 } 6561 } 6562 } 6563 break; 6564 default: 6565 break; 6566 } 6567 return 0; 6568 } 6569 6570 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6571 struct amdgpu_irq_src *source, 6572 unsigned int type, 6573 enum amdgpu_interrupt_state state) 6574 { 6575 u32 cp_int_cntl_reg, cp_int_cntl; 6576 int i, j; 6577 6578 switch (state) { 6579 case AMDGPU_IRQ_STATE_DISABLE: 6580 case AMDGPU_IRQ_STATE_ENABLE: 6581 for (i = 0; i < adev->gfx.me.num_me; i++) { 6582 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6583 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6584 6585 if (cp_int_cntl_reg) { 6586 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6587 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6588 PRIV_INSTR_INT_ENABLE, 6589 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6590 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6591 } 6592 } 6593 } 6594 break; 6595 default: 6596 break; 6597 } 6598 6599 return 0; 6600 } 6601 6602 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6603 struct amdgpu_iv_entry *entry) 6604 { 6605 u8 me_id, pipe_id, queue_id; 6606 struct amdgpu_ring *ring; 6607 int i; 6608 6609 me_id = (entry->ring_id & 0x0c) >> 2; 6610 pipe_id = (entry->ring_id & 0x03) >> 0; 6611 queue_id = (entry->ring_id & 0x70) >> 4; 6612 6613 if (!adev->gfx.disable_kq) { 6614 switch (me_id) { 6615 case 0: 6616 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6617 ring = &adev->gfx.gfx_ring[i]; 6618 if (ring->me == me_id && ring->pipe == pipe_id && 6619 ring->queue == queue_id) 6620 drm_sched_fault(&ring->sched); 6621 } 6622 break; 6623 case 1: 6624 case 2: 6625 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6626 ring = &adev->gfx.compute_ring[i]; 6627 if (ring->me == me_id && ring->pipe == pipe_id && 6628 ring->queue == queue_id) 6629 drm_sched_fault(&ring->sched); 6630 } 6631 break; 6632 default: 6633 BUG(); 6634 break; 6635 } 6636 } 6637 } 6638 6639 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6640 struct amdgpu_irq_src *source, 6641 struct amdgpu_iv_entry *entry) 6642 { 6643 DRM_ERROR("Illegal register access in command stream\n"); 6644 gfx_v11_0_handle_priv_fault(adev, entry); 6645 return 0; 6646 } 6647 6648 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6649 struct amdgpu_irq_src *source, 6650 struct amdgpu_iv_entry *entry) 6651 { 6652 DRM_ERROR("Illegal opcode in command stream \n"); 6653 gfx_v11_0_handle_priv_fault(adev, entry); 6654 return 0; 6655 } 6656 6657 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6658 struct amdgpu_irq_src *source, 6659 struct amdgpu_iv_entry *entry) 6660 { 6661 DRM_ERROR("Illegal instruction in command stream\n"); 6662 gfx_v11_0_handle_priv_fault(adev, entry); 6663 return 0; 6664 } 6665 6666 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6667 struct amdgpu_irq_src *source, 6668 struct amdgpu_iv_entry *entry) 6669 { 6670 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6671 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6672 6673 return 0; 6674 } 6675 6676 #if 0 6677 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6678 struct amdgpu_irq_src *src, 6679 unsigned int type, 6680 enum amdgpu_interrupt_state state) 6681 { 6682 uint32_t tmp, target; 6683 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6684 6685 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6686 target += ring->pipe; 6687 6688 switch (type) { 6689 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6690 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6691 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6692 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6693 GENERIC2_INT_ENABLE, 0); 6694 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6695 6696 tmp = RREG32_SOC15_IP(GC, target); 6697 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6698 GENERIC2_INT_ENABLE, 0); 6699 WREG32_SOC15_IP(GC, target, tmp); 6700 } else { 6701 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6702 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6703 GENERIC2_INT_ENABLE, 1); 6704 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6705 6706 tmp = RREG32_SOC15_IP(GC, target); 6707 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6708 GENERIC2_INT_ENABLE, 1); 6709 WREG32_SOC15_IP(GC, target, tmp); 6710 } 6711 break; 6712 default: 6713 BUG(); /* kiq only support GENERIC2_INT now */ 6714 break; 6715 } 6716 return 0; 6717 } 6718 #endif 6719 6720 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6721 { 6722 const unsigned int gcr_cntl = 6723 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6724 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6725 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6726 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6727 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6728 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6729 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6730 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6731 6732 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6733 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6734 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6735 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6736 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6737 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6738 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6739 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6740 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6741 } 6742 6743 static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev) 6744 { 6745 /* Disable the pipe reset until the CPFW fully support it.*/ 6746 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 6747 return false; 6748 } 6749 6750 6751 static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring) 6752 { 6753 struct amdgpu_device *adev = ring->adev; 6754 uint32_t reset_pipe = 0, clean_pipe = 0; 6755 int r; 6756 6757 if (!gfx_v11_pipe_reset_support(adev)) 6758 return -EOPNOTSUPP; 6759 6760 gfx_v11_0_set_safe_mode(adev, 0); 6761 mutex_lock(&adev->srbm_mutex); 6762 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6763 6764 switch (ring->pipe) { 6765 case 0: 6766 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6767 PFP_PIPE0_RESET, 1); 6768 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6769 ME_PIPE0_RESET, 1); 6770 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6771 PFP_PIPE0_RESET, 0); 6772 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6773 ME_PIPE0_RESET, 0); 6774 break; 6775 case 1: 6776 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6777 PFP_PIPE1_RESET, 1); 6778 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6779 ME_PIPE1_RESET, 1); 6780 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6781 PFP_PIPE1_RESET, 0); 6782 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6783 ME_PIPE1_RESET, 0); 6784 break; 6785 default: 6786 break; 6787 } 6788 6789 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 6790 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 6791 6792 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 6793 RS64_FW_UC_START_ADDR_LO; 6794 soc21_grbm_select(adev, 0, 0, 0, 0); 6795 mutex_unlock(&adev->srbm_mutex); 6796 gfx_v11_0_unset_safe_mode(adev, 0); 6797 6798 dev_info(adev->dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring->name, 6799 r == 0 ? "successfully" : "failed"); 6800 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 6801 * so the pipe reset status relies on the later gfx ring test result. 6802 */ 6803 return 0; 6804 } 6805 6806 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, 6807 unsigned int vmid, 6808 struct amdgpu_fence *timedout_fence) 6809 { 6810 struct amdgpu_device *adev = ring->adev; 6811 int r; 6812 6813 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6814 6815 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 6816 if (r) { 6817 6818 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 6819 r = gfx_v11_reset_gfx_pipe(ring); 6820 if (r) 6821 return r; 6822 } 6823 6824 r = gfx_v11_0_kgq_init_queue(ring, true); 6825 if (r) { 6826 dev_err(adev->dev, "failed to init kgq\n"); 6827 return r; 6828 } 6829 6830 r = amdgpu_mes_map_legacy_queue(adev, ring); 6831 if (r) { 6832 dev_err(adev->dev, "failed to remap kgq\n"); 6833 return r; 6834 } 6835 6836 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 6837 } 6838 6839 static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring) 6840 { 6841 6842 struct amdgpu_device *adev = ring->adev; 6843 uint32_t reset_pipe = 0, clean_pipe = 0; 6844 int r; 6845 6846 if (!gfx_v11_pipe_reset_support(adev)) 6847 return -EOPNOTSUPP; 6848 6849 gfx_v11_0_set_safe_mode(adev, 0); 6850 mutex_lock(&adev->srbm_mutex); 6851 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6852 6853 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 6854 clean_pipe = reset_pipe; 6855 6856 if (adev->gfx.rs64_enable) { 6857 6858 switch (ring->pipe) { 6859 case 0: 6860 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6861 MEC_PIPE0_RESET, 1); 6862 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6863 MEC_PIPE0_RESET, 0); 6864 break; 6865 case 1: 6866 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6867 MEC_PIPE1_RESET, 1); 6868 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6869 MEC_PIPE1_RESET, 0); 6870 break; 6871 case 2: 6872 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6873 MEC_PIPE2_RESET, 1); 6874 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6875 MEC_PIPE2_RESET, 0); 6876 break; 6877 case 3: 6878 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6879 MEC_PIPE3_RESET, 1); 6880 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6881 MEC_PIPE3_RESET, 0); 6882 break; 6883 default: 6884 break; 6885 } 6886 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 6887 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 6888 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 6889 RS64_FW_UC_START_ADDR_LO; 6890 } else { 6891 if (ring->me == 1) { 6892 switch (ring->pipe) { 6893 case 0: 6894 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6895 MEC_ME1_PIPE0_RESET, 1); 6896 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6897 MEC_ME1_PIPE0_RESET, 0); 6898 break; 6899 case 1: 6900 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6901 MEC_ME1_PIPE1_RESET, 1); 6902 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6903 MEC_ME1_PIPE1_RESET, 0); 6904 break; 6905 case 2: 6906 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6907 MEC_ME1_PIPE2_RESET, 1); 6908 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6909 MEC_ME1_PIPE2_RESET, 0); 6910 break; 6911 case 3: 6912 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6913 MEC_ME1_PIPE3_RESET, 1); 6914 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6915 MEC_ME1_PIPE3_RESET, 0); 6916 break; 6917 default: 6918 break; 6919 } 6920 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 6921 } else { 6922 switch (ring->pipe) { 6923 case 0: 6924 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6925 MEC_ME2_PIPE0_RESET, 1); 6926 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6927 MEC_ME2_PIPE0_RESET, 0); 6928 break; 6929 case 1: 6930 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6931 MEC_ME2_PIPE1_RESET, 1); 6932 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6933 MEC_ME2_PIPE1_RESET, 0); 6934 break; 6935 case 2: 6936 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6937 MEC_ME2_PIPE2_RESET, 1); 6938 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6939 MEC_ME2_PIPE2_RESET, 0); 6940 break; 6941 case 3: 6942 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6943 MEC_ME2_PIPE3_RESET, 1); 6944 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6945 MEC_ME2_PIPE3_RESET, 0); 6946 break; 6947 default: 6948 break; 6949 } 6950 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 6951 } 6952 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 6953 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 6954 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 6955 } 6956 6957 soc21_grbm_select(adev, 0, 0, 0, 0); 6958 mutex_unlock(&adev->srbm_mutex); 6959 gfx_v11_0_unset_safe_mode(adev, 0); 6960 6961 dev_info(adev->dev, "The ring %s pipe resets to MEC FW start PC: %s\n", ring->name, 6962 r == 0 ? "successfully" : "failed"); 6963 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 6964 * reset status relies on the compute ring test result. 6965 */ 6966 return 0; 6967 } 6968 6969 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, 6970 unsigned int vmid, 6971 struct amdgpu_fence *timedout_fence) 6972 { 6973 struct amdgpu_device *adev = ring->adev; 6974 int r = 0; 6975 6976 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6977 6978 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 6979 if (r) { 6980 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 6981 r = gfx_v11_0_reset_compute_pipe(ring); 6982 if (r) 6983 return r; 6984 } 6985 6986 r = gfx_v11_0_kcq_init_queue(ring, true); 6987 if (r) { 6988 dev_err(adev->dev, "fail to init kcq\n"); 6989 return r; 6990 } 6991 r = amdgpu_mes_map_legacy_queue(adev, ring); 6992 if (r) { 6993 dev_err(adev->dev, "failed to remap kcq\n"); 6994 return r; 6995 } 6996 6997 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 6998 } 6999 7000 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 7001 { 7002 struct amdgpu_device *adev = ip_block->adev; 7003 uint32_t i, j, k, reg, index = 0; 7004 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 7005 7006 if (!adev->gfx.ip_dump_core) 7007 return; 7008 7009 for (i = 0; i < reg_count; i++) 7010 drm_printf(p, "%-50s \t 0x%08x\n", 7011 gc_reg_list_11_0[i].reg_name, 7012 adev->gfx.ip_dump_core[i]); 7013 7014 /* print compute queue registers for all instances */ 7015 if (!adev->gfx.ip_dump_compute_queues) 7016 return; 7017 7018 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 7019 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 7020 adev->gfx.mec.num_mec, 7021 adev->gfx.mec.num_pipe_per_mec, 7022 adev->gfx.mec.num_queue_per_pipe); 7023 7024 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7025 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7026 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7027 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 7028 for (reg = 0; reg < reg_count; reg++) { 7029 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 7030 drm_printf(p, "%-50s \t 0x%08x\n", 7031 "regCP_MEC_ME2_HEADER_DUMP", 7032 adev->gfx.ip_dump_compute_queues[index + reg]); 7033 else 7034 drm_printf(p, "%-50s \t 0x%08x\n", 7035 gc_cp_reg_list_11[reg].reg_name, 7036 adev->gfx.ip_dump_compute_queues[index + reg]); 7037 } 7038 index += reg_count; 7039 } 7040 } 7041 } 7042 7043 /* print gfx queue registers for all instances */ 7044 if (!adev->gfx.ip_dump_gfx_queues) 7045 return; 7046 7047 index = 0; 7048 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7049 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 7050 adev->gfx.me.num_me, 7051 adev->gfx.me.num_pipe_per_me, 7052 adev->gfx.me.num_queue_per_pipe); 7053 7054 for (i = 0; i < adev->gfx.me.num_me; i++) { 7055 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7056 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7057 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 7058 for (reg = 0; reg < reg_count; reg++) { 7059 drm_printf(p, "%-50s \t 0x%08x\n", 7060 gc_gfx_queue_reg_list_11[reg].reg_name, 7061 adev->gfx.ip_dump_gfx_queues[index + reg]); 7062 } 7063 index += reg_count; 7064 } 7065 } 7066 } 7067 } 7068 7069 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 7070 { 7071 struct amdgpu_device *adev = ip_block->adev; 7072 uint32_t i, j, k, reg, index = 0; 7073 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 7074 7075 if (!adev->gfx.ip_dump_core) 7076 return; 7077 7078 amdgpu_gfx_off_ctrl(adev, false); 7079 for (i = 0; i < reg_count; i++) 7080 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 7081 amdgpu_gfx_off_ctrl(adev, true); 7082 7083 /* dump compute queue registers for all instances */ 7084 if (!adev->gfx.ip_dump_compute_queues) 7085 return; 7086 7087 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 7088 amdgpu_gfx_off_ctrl(adev, false); 7089 mutex_lock(&adev->srbm_mutex); 7090 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7091 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7092 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7093 /* ME0 is for GFX so start from 1 for CP */ 7094 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 7095 for (reg = 0; reg < reg_count; reg++) { 7096 if (i && 7097 gc_cp_reg_list_11[reg].reg_offset == 7098 regCP_MEC_ME1_HEADER_DUMP) 7099 adev->gfx.ip_dump_compute_queues[index + reg] = 7100 RREG32(SOC15_REG_OFFSET(GC, 0, 7101 regCP_MEC_ME2_HEADER_DUMP)); 7102 else 7103 adev->gfx.ip_dump_compute_queues[index + reg] = 7104 RREG32(SOC15_REG_ENTRY_OFFSET( 7105 gc_cp_reg_list_11[reg])); 7106 } 7107 index += reg_count; 7108 } 7109 } 7110 } 7111 soc21_grbm_select(adev, 0, 0, 0, 0); 7112 mutex_unlock(&adev->srbm_mutex); 7113 amdgpu_gfx_off_ctrl(adev, true); 7114 7115 /* dump gfx queue registers for all instances */ 7116 if (!adev->gfx.ip_dump_gfx_queues) 7117 return; 7118 7119 index = 0; 7120 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7121 amdgpu_gfx_off_ctrl(adev, false); 7122 mutex_lock(&adev->srbm_mutex); 7123 for (i = 0; i < adev->gfx.me.num_me; i++) { 7124 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7125 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7126 soc21_grbm_select(adev, i, j, k, 0); 7127 7128 for (reg = 0; reg < reg_count; reg++) { 7129 adev->gfx.ip_dump_gfx_queues[index + reg] = 7130 RREG32(SOC15_REG_ENTRY_OFFSET( 7131 gc_gfx_queue_reg_list_11[reg])); 7132 } 7133 index += reg_count; 7134 } 7135 } 7136 } 7137 soc21_grbm_select(adev, 0, 0, 0, 0); 7138 mutex_unlock(&adev->srbm_mutex); 7139 amdgpu_gfx_off_ctrl(adev, true); 7140 } 7141 7142 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 7143 { 7144 /* Emit the cleaner shader */ 7145 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 7146 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 7147 } 7148 7149 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 7150 { 7151 amdgpu_gfx_profile_ring_begin_use(ring); 7152 7153 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 7154 } 7155 7156 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 7157 { 7158 amdgpu_gfx_profile_ring_end_use(ring); 7159 7160 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 7161 } 7162 7163 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 7164 .name = "gfx_v11_0", 7165 .early_init = gfx_v11_0_early_init, 7166 .late_init = gfx_v11_0_late_init, 7167 .sw_init = gfx_v11_0_sw_init, 7168 .sw_fini = gfx_v11_0_sw_fini, 7169 .hw_init = gfx_v11_0_hw_init, 7170 .hw_fini = gfx_v11_0_hw_fini, 7171 .suspend = gfx_v11_0_suspend, 7172 .resume = gfx_v11_0_resume, 7173 .is_idle = gfx_v11_0_is_idle, 7174 .wait_for_idle = gfx_v11_0_wait_for_idle, 7175 .soft_reset = gfx_v11_0_soft_reset, 7176 .check_soft_reset = gfx_v11_0_check_soft_reset, 7177 .post_soft_reset = gfx_v11_0_post_soft_reset, 7178 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 7179 .set_powergating_state = gfx_v11_0_set_powergating_state, 7180 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 7181 .dump_ip_state = gfx_v11_ip_dump, 7182 .print_ip_state = gfx_v11_ip_print, 7183 }; 7184 7185 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 7186 .type = AMDGPU_RING_TYPE_GFX, 7187 .align_mask = 0xff, 7188 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7189 .support_64bit_ptrs = true, 7190 .secure_submission_supported = true, 7191 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 7192 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 7193 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 7194 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 7195 5 + /* update_spm_vmid */ 7196 5 + /* COND_EXEC */ 7197 22 + /* SET_Q_PREEMPTION_MODE */ 7198 7 + /* PIPELINE_SYNC */ 7199 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7200 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7201 4 + /* VM_FLUSH */ 7202 8 + /* FENCE for VM_FLUSH */ 7203 20 + /* GDS switch */ 7204 5 + /* COND_EXEC */ 7205 7 + /* HDP_flush */ 7206 4 + /* VGT_flush */ 7207 31 + /* DE_META */ 7208 3 + /* CNTX_CTRL */ 7209 5 + /* HDP_INVL */ 7210 22 + /* SET_Q_PREEMPTION_MODE */ 7211 8 + 8 + /* FENCE x2 */ 7212 8 + /* gfx_v11_0_emit_mem_sync */ 7213 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7214 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 7215 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 7216 .emit_fence = gfx_v11_0_ring_emit_fence, 7217 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7218 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7219 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7220 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7221 .test_ring = gfx_v11_0_ring_test_ring, 7222 .test_ib = gfx_v11_0_ring_test_ib, 7223 .insert_nop = gfx_v11_ring_insert_nop, 7224 .pad_ib = amdgpu_ring_generic_pad_ib, 7225 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 7226 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 7227 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 7228 .preempt_ib = gfx_v11_0_ring_preempt_ib, 7229 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 7230 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7231 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7232 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7233 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7234 .reset = gfx_v11_0_reset_kgq, 7235 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7236 .begin_use = gfx_v11_0_ring_begin_use, 7237 .end_use = gfx_v11_0_ring_end_use, 7238 }; 7239 7240 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 7241 .type = AMDGPU_RING_TYPE_COMPUTE, 7242 .align_mask = 0xff, 7243 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7244 .support_64bit_ptrs = true, 7245 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7246 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7247 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7248 .emit_frame_size = 7249 5 + /* update_spm_vmid */ 7250 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7251 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7252 5 + /* hdp invalidate */ 7253 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7254 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7255 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7256 2 + /* gfx_v11_0_ring_emit_vm_flush */ 7257 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 7258 8 + /* gfx_v11_0_emit_mem_sync */ 7259 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7260 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7261 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7262 .emit_fence = gfx_v11_0_ring_emit_fence, 7263 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7264 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7265 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7266 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7267 .test_ring = gfx_v11_0_ring_test_ring, 7268 .test_ib = gfx_v11_0_ring_test_ib, 7269 .insert_nop = gfx_v11_ring_insert_nop, 7270 .pad_ib = amdgpu_ring_generic_pad_ib, 7271 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7272 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7273 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7274 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7275 .reset = gfx_v11_0_reset_kcq, 7276 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7277 .begin_use = gfx_v11_0_ring_begin_use, 7278 .end_use = gfx_v11_0_ring_end_use, 7279 }; 7280 7281 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 7282 .type = AMDGPU_RING_TYPE_KIQ, 7283 .align_mask = 0xff, 7284 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7285 .support_64bit_ptrs = true, 7286 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7287 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7288 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7289 .emit_frame_size = 7290 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7291 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7292 5 + /*hdp invalidate */ 7293 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7294 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7295 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7296 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7297 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7298 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7299 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 7300 .test_ring = gfx_v11_0_ring_test_ring, 7301 .test_ib = gfx_v11_0_ring_test_ib, 7302 .insert_nop = amdgpu_ring_insert_nop, 7303 .pad_ib = amdgpu_ring_generic_pad_ib, 7304 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7305 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7306 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7307 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7308 }; 7309 7310 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7311 { 7312 int i; 7313 7314 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7315 7316 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7317 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7318 7319 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7320 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7321 } 7322 7323 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7324 .set = gfx_v11_0_set_eop_interrupt_state, 7325 .process = gfx_v11_0_eop_irq, 7326 }; 7327 7328 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7329 .set = gfx_v11_0_set_priv_reg_fault_state, 7330 .process = gfx_v11_0_priv_reg_irq, 7331 }; 7332 7333 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7334 .set = gfx_v11_0_set_bad_op_fault_state, 7335 .process = gfx_v11_0_bad_op_irq, 7336 }; 7337 7338 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7339 .set = gfx_v11_0_set_priv_inst_fault_state, 7340 .process = gfx_v11_0_priv_inst_irq, 7341 }; 7342 7343 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7344 .process = gfx_v11_0_rlc_gc_fed_irq, 7345 }; 7346 7347 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7348 { 7349 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7350 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7351 7352 adev->gfx.priv_reg_irq.num_types = 1; 7353 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7354 7355 adev->gfx.bad_op_irq.num_types = 1; 7356 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7357 7358 adev->gfx.priv_inst_irq.num_types = 1; 7359 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7360 7361 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7362 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7363 7364 } 7365 7366 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7367 { 7368 if (adev->flags & AMD_IS_APU) 7369 adev->gfx.imu.mode = MISSION_MODE; 7370 else 7371 adev->gfx.imu.mode = DEBUG_MODE; 7372 7373 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7374 } 7375 7376 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7377 { 7378 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7379 } 7380 7381 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7382 { 7383 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7384 adev->gfx.config.max_sh_per_se * 7385 adev->gfx.config.max_shader_engines; 7386 7387 adev->gds.gds_size = 0x1000; 7388 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7389 adev->gds.gws_size = 64; 7390 adev->gds.oa_size = 16; 7391 } 7392 7393 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7394 { 7395 /* set gfx eng mqd */ 7396 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7397 sizeof(struct v11_gfx_mqd); 7398 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7399 gfx_v11_0_gfx_mqd_init; 7400 /* set compute eng mqd */ 7401 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7402 sizeof(struct v11_compute_mqd); 7403 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7404 gfx_v11_0_compute_mqd_init; 7405 } 7406 7407 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7408 u32 bitmap) 7409 { 7410 u32 data; 7411 7412 if (!bitmap) 7413 return; 7414 7415 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7416 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7417 7418 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7419 } 7420 7421 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7422 { 7423 u32 data, wgp_bitmask; 7424 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7425 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7426 7427 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7428 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7429 7430 wgp_bitmask = 7431 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7432 7433 return (~data) & wgp_bitmask; 7434 } 7435 7436 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7437 { 7438 u32 wgp_idx, wgp_active_bitmap; 7439 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7440 7441 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7442 cu_active_bitmap = 0; 7443 7444 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7445 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7446 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7447 if (wgp_active_bitmap & (1 << wgp_idx)) 7448 cu_active_bitmap |= cu_bitmap_per_wgp; 7449 } 7450 7451 return cu_active_bitmap; 7452 } 7453 7454 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7455 struct amdgpu_cu_info *cu_info) 7456 { 7457 int i, j, k, counter, active_cu_number = 0; 7458 u32 mask, bitmap; 7459 unsigned disable_masks[8 * 2]; 7460 7461 if (!adev || !cu_info) 7462 return -EINVAL; 7463 7464 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 7465 7466 mutex_lock(&adev->grbm_idx_mutex); 7467 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7468 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7469 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7470 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7471 continue; 7472 mask = 1; 7473 counter = 0; 7474 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7475 if (i < 8 && j < 2) 7476 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7477 adev, disable_masks[i * 2 + j]); 7478 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7479 7480 /** 7481 * GFX11 could support more than 4 SEs, while the bitmap 7482 * in cu_info struct is 4x4 and ioctl interface struct 7483 * drm_amdgpu_info_device should keep stable. 7484 * So we use last two columns of bitmap to store cu mask for 7485 * SEs 4 to 7, the layout of the bitmap is as below: 7486 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7487 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7488 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7489 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7490 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7491 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7492 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7493 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7494 */ 7495 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7496 7497 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7498 if (bitmap & mask) 7499 counter++; 7500 7501 mask <<= 1; 7502 } 7503 active_cu_number += counter; 7504 } 7505 } 7506 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7507 mutex_unlock(&adev->grbm_idx_mutex); 7508 7509 cu_info->number = active_cu_number; 7510 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7511 7512 return 0; 7513 } 7514 7515 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7516 { 7517 .type = AMD_IP_BLOCK_TYPE_GFX, 7518 .major = 11, 7519 .minor = 0, 7520 .rev = 0, 7521 .funcs = &gfx_v11_0_ip_funcs, 7522 }; 7523