1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v11_0.h" 33 #include "soc21.h" 34 #include "nvd.h" 35 36 #include "gc/gc_11_0_0_offset.h" 37 #include "gc/gc_11_0_0_sh_mask.h" 38 #include "smuio/smuio_13_0_6_offset.h" 39 #include "smuio/smuio_13_0_6_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx11.h" 45 #include "v11_structs.h" 46 #include "gfx_v11_0.h" 47 #include "gfx_v11_0_cleaner_shader.h" 48 #include "gfx_v11_0_3.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 #include "mes_userqueue.h" 52 #include "amdgpu_userq_fence.h" 53 54 #define GFX11_NUM_GFX_RINGS 1 55 #define GFX11_MEC_HPD_SIZE 2048 56 57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 59 60 #define regCGTT_WD_CLK_CTRL 0x5086 61 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 63 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 64 #define regPC_CONFIG_CNTL_1 0x194d 65 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 66 67 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 68 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 69 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 70 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 71 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00a00000 72 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 73 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 74 75 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 76 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 77 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 78 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 79 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 80 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 81 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 82 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 83 84 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_kicker.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 104 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 105 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 106 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 107 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 108 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 109 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 110 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 111 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 112 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 113 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 114 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 115 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 116 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 117 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 118 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 119 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 120 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 121 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 122 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 123 MODULE_FIRMWARE("amdgpu/gc_11_5_4_pfp.bin"); 124 MODULE_FIRMWARE("amdgpu/gc_11_5_4_me.bin"); 125 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mec.bin"); 126 MODULE_FIRMWARE("amdgpu/gc_11_5_4_rlc.bin"); 127 128 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 129 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 130 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 131 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 162 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 163 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 164 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 165 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 166 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 167 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 168 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 169 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 170 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 171 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 172 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 173 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 174 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 175 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 176 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 186 /* cp header registers */ 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 195 /* SE status registers */ 196 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 197 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 198 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 199 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 200 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 201 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 202 }; 203 204 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 205 /* compute registers */ 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 245 /* cp header registers */ 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 252 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 253 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 254 }; 255 256 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 257 /* gfx queue registers */ 258 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 259 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 260 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 261 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 262 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 263 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 264 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 265 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 266 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 267 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 268 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 269 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 270 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 271 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 272 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 273 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 274 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 275 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 276 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 277 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 278 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 279 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 280 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 281 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 282 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 283 /* cp header registers */ 284 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 285 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 286 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 287 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 288 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 289 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 290 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 291 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 292 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 293 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 294 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 295 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 296 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 297 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 298 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 299 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 300 }; 301 302 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 303 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 304 }; 305 306 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 307 { 308 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 317 }; 318 319 #define DEFAULT_SH_MEM_CONFIG \ 320 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 321 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 322 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 323 324 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 325 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 326 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 327 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 328 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 329 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 330 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 331 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 332 struct amdgpu_cu_info *cu_info); 333 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 334 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 335 u32 sh_num, u32 instance, int xcc_id); 336 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 337 338 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 339 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 340 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 341 uint32_t val); 342 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 343 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 344 uint16_t pasid, uint32_t flush_type, 345 bool all_hub, uint8_t dst_sel); 346 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 347 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 348 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 349 bool enable); 350 351 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 352 { 353 struct amdgpu_device *adev = kiq_ring->adev; 354 u64 shader_mc_addr; 355 356 /* Cleaner shader MC address */ 357 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 358 359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 360 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 361 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 362 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 363 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 364 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 365 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 366 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 367 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 368 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 369 } 370 371 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 372 struct amdgpu_ring *ring) 373 { 374 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 375 uint64_t wptr_addr = ring->wptr_gpu_addr; 376 uint32_t me = 0, eng_sel = 0; 377 378 switch (ring->funcs->type) { 379 case AMDGPU_RING_TYPE_COMPUTE: 380 me = 1; 381 eng_sel = 0; 382 break; 383 case AMDGPU_RING_TYPE_GFX: 384 me = 0; 385 eng_sel = 4; 386 break; 387 case AMDGPU_RING_TYPE_MES: 388 me = 2; 389 eng_sel = 5; 390 break; 391 default: 392 WARN_ON(1); 393 } 394 395 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 396 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 397 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 398 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 399 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 400 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 401 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 402 PACKET3_MAP_QUEUES_ME((me)) | 403 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 404 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 405 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 406 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 407 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 408 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 409 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 410 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 411 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 412 } 413 414 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 415 struct amdgpu_ring *ring, 416 enum amdgpu_unmap_queues_action action, 417 u64 gpu_addr, u64 seq) 418 { 419 struct amdgpu_device *adev = kiq_ring->adev; 420 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 421 422 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 423 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 424 gpu_addr, seq, 0); 425 return; 426 } 427 428 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 429 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 430 PACKET3_UNMAP_QUEUES_ACTION(action) | 431 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 432 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 433 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 434 amdgpu_ring_write(kiq_ring, 435 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 436 437 if (action == PREEMPT_QUEUES_NO_UNMAP) { 438 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 439 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 440 amdgpu_ring_write(kiq_ring, seq); 441 } else { 442 amdgpu_ring_write(kiq_ring, 0); 443 amdgpu_ring_write(kiq_ring, 0); 444 amdgpu_ring_write(kiq_ring, 0); 445 } 446 } 447 448 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 449 struct amdgpu_ring *ring, 450 u64 addr, 451 u64 seq) 452 { 453 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 454 455 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 456 amdgpu_ring_write(kiq_ring, 457 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 458 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 459 PACKET3_QUERY_STATUS_COMMAND(2)); 460 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 461 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 462 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 463 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 464 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 465 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 466 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 467 } 468 469 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 470 uint16_t pasid, uint32_t flush_type, 471 bool all_hub) 472 { 473 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 474 } 475 476 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 477 .kiq_set_resources = gfx11_kiq_set_resources, 478 .kiq_map_queues = gfx11_kiq_map_queues, 479 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 480 .kiq_query_status = gfx11_kiq_query_status, 481 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 482 .set_resources_size = 8, 483 .map_queues_size = 7, 484 .unmap_queues_size = 6, 485 .query_status_size = 7, 486 .invalidate_tlbs_size = 2, 487 }; 488 489 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 490 { 491 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 492 } 493 494 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 495 { 496 if (amdgpu_sriov_vf(adev)) 497 return; 498 499 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 500 case IP_VERSION(11, 0, 1): 501 case IP_VERSION(11, 0, 4): 502 soc15_program_register_sequence(adev, 503 golden_settings_gc_11_0_1, 504 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 505 break; 506 default: 507 break; 508 } 509 soc15_program_register_sequence(adev, 510 golden_settings_gc_11_0, 511 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 512 513 } 514 515 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 516 bool wc, uint32_t reg, uint32_t val) 517 { 518 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 519 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 520 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 521 amdgpu_ring_write(ring, reg); 522 amdgpu_ring_write(ring, 0); 523 amdgpu_ring_write(ring, val); 524 } 525 526 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 527 int mem_space, int opt, uint32_t addr0, 528 uint32_t addr1, uint32_t ref, uint32_t mask, 529 uint32_t inv) 530 { 531 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 532 amdgpu_ring_write(ring, 533 /* memory (1) or register (0) */ 534 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 535 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 536 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 537 WAIT_REG_MEM_ENGINE(eng_sel))); 538 539 if (mem_space) 540 BUG_ON(addr0 & 0x3); /* Dword align */ 541 amdgpu_ring_write(ring, addr0); 542 amdgpu_ring_write(ring, addr1); 543 amdgpu_ring_write(ring, ref); 544 amdgpu_ring_write(ring, mask); 545 amdgpu_ring_write(ring, inv); /* poll interval */ 546 } 547 548 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 549 { 550 /* Header itself is a NOP packet */ 551 if (num_nop == 1) { 552 amdgpu_ring_write(ring, ring->funcs->nop); 553 return; 554 } 555 556 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 557 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 558 559 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 560 amdgpu_ring_insert_nop(ring, num_nop - 1); 561 } 562 563 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 564 { 565 struct amdgpu_device *adev = ring->adev; 566 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 567 uint32_t tmp = 0; 568 unsigned i; 569 int r; 570 571 WREG32(scratch, 0xCAFEDEAD); 572 r = amdgpu_ring_alloc(ring, 5); 573 if (r) { 574 drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", 575 ring->idx, r); 576 return r; 577 } 578 579 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 580 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 581 } else { 582 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 583 amdgpu_ring_write(ring, scratch - 584 PACKET3_SET_UCONFIG_REG_START); 585 amdgpu_ring_write(ring, 0xDEADBEEF); 586 } 587 amdgpu_ring_commit(ring); 588 589 for (i = 0; i < adev->usec_timeout; i++) { 590 tmp = RREG32(scratch); 591 if (tmp == 0xDEADBEEF) 592 break; 593 if (amdgpu_emu_mode == 1) 594 msleep(1); 595 else 596 udelay(1); 597 } 598 599 if (i >= adev->usec_timeout) 600 r = -ETIMEDOUT; 601 return r; 602 } 603 604 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 605 { 606 struct amdgpu_device *adev = ring->adev; 607 struct amdgpu_ib ib; 608 struct dma_fence *f = NULL; 609 unsigned index; 610 uint64_t gpu_addr; 611 uint32_t *cpu_ptr; 612 long r; 613 614 /* MES KIQ fw hasn't indirect buffer support for now */ 615 if (adev->enable_mes_kiq && 616 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 617 return 0; 618 619 memset(&ib, 0, sizeof(ib)); 620 621 r = amdgpu_device_wb_get(adev, &index); 622 if (r) 623 return r; 624 625 gpu_addr = adev->wb.gpu_addr + (index * 4); 626 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 627 cpu_ptr = &adev->wb.wb[index]; 628 629 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 630 if (r) { 631 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 632 goto err1; 633 } 634 635 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 636 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 637 ib.ptr[2] = lower_32_bits(gpu_addr); 638 ib.ptr[3] = upper_32_bits(gpu_addr); 639 ib.ptr[4] = 0xDEADBEEF; 640 ib.length_dw = 5; 641 642 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 643 if (r) 644 goto err2; 645 646 r = dma_fence_wait_timeout(f, false, timeout); 647 if (r == 0) { 648 r = -ETIMEDOUT; 649 goto err2; 650 } else if (r < 0) { 651 goto err2; 652 } 653 654 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 655 r = 0; 656 else 657 r = -EINVAL; 658 err2: 659 amdgpu_ib_free(&ib, NULL); 660 dma_fence_put(f); 661 err1: 662 amdgpu_device_wb_free(adev, index); 663 return r; 664 } 665 666 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 667 { 668 amdgpu_ucode_release(&adev->gfx.pfp_fw); 669 amdgpu_ucode_release(&adev->gfx.me_fw); 670 amdgpu_ucode_release(&adev->gfx.rlc_fw); 671 amdgpu_ucode_release(&adev->gfx.mec_fw); 672 673 kfree(adev->gfx.rlc.register_list_format); 674 } 675 676 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 677 { 678 const struct psp_firmware_header_v1_0 *toc_hdr; 679 int err = 0; 680 681 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 682 AMDGPU_UCODE_REQUIRED, 683 "amdgpu/%s_toc.bin", ucode_prefix); 684 if (err) 685 goto out; 686 687 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 688 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 689 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 690 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 691 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 692 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 693 return 0; 694 out: 695 amdgpu_ucode_release(&adev->psp.toc_fw); 696 return err; 697 } 698 699 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 700 { 701 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 702 case IP_VERSION(11, 0, 0): 703 case IP_VERSION(11, 0, 2): 704 case IP_VERSION(11, 0, 3): 705 if ((adev->gfx.me_fw_version >= 1505) && 706 (adev->gfx.pfp_fw_version >= 1600) && 707 (adev->gfx.mec_fw_version >= 512)) { 708 if (amdgpu_sriov_vf(adev)) 709 adev->gfx.cp_gfx_shadow = true; 710 else 711 adev->gfx.cp_gfx_shadow = false; 712 } 713 break; 714 default: 715 adev->gfx.cp_gfx_shadow = false; 716 break; 717 } 718 } 719 720 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 721 { 722 char ucode_prefix[25]; 723 int err; 724 const struct rlc_firmware_header_v2_0 *rlc_hdr; 725 uint16_t version_major; 726 uint16_t version_minor; 727 728 DRM_DEBUG("\n"); 729 730 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 731 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 732 AMDGPU_UCODE_REQUIRED, 733 "amdgpu/%s_pfp.bin", ucode_prefix); 734 if (err) 735 goto out; 736 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 737 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 738 (union amdgpu_firmware_header *) 739 adev->gfx.pfp_fw->data, 2, 0); 740 if (adev->gfx.rs64_enable) { 741 dev_info(adev->dev, "CP RS64 enable\n"); 742 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 743 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 744 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 745 } else { 746 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 747 } 748 749 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 750 AMDGPU_UCODE_REQUIRED, 751 "amdgpu/%s_me.bin", ucode_prefix); 752 if (err) 753 goto out; 754 if (adev->gfx.rs64_enable) { 755 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 756 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 757 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 758 } else { 759 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 760 } 761 762 if (!amdgpu_sriov_vf(adev)) { 763 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 764 adev->pdev->revision == 0xCE) 765 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 766 AMDGPU_UCODE_REQUIRED, 767 "amdgpu/gc_11_0_0_rlc_1.bin"); 768 else if (amdgpu_is_kicker_fw(adev)) 769 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 770 AMDGPU_UCODE_REQUIRED, 771 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 772 else 773 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 774 AMDGPU_UCODE_REQUIRED, 775 "amdgpu/%s_rlc.bin", ucode_prefix); 776 if (err) 777 goto out; 778 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 779 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 780 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 781 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 782 if (err) 783 goto out; 784 } 785 786 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 787 AMDGPU_UCODE_REQUIRED, 788 "amdgpu/%s_mec.bin", ucode_prefix); 789 if (err) 790 goto out; 791 if (adev->gfx.rs64_enable) { 792 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 793 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 794 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 795 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 796 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 797 } else { 798 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 799 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 800 } 801 802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 803 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 804 805 /* only one MEC for gfx 11.0.0. */ 806 adev->gfx.mec2_fw = NULL; 807 808 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 809 810 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 811 err = adev->gfx.imu.funcs->init_microcode(adev); 812 if (err) 813 DRM_ERROR("Failed to init imu firmware!\n"); 814 return err; 815 } 816 817 out: 818 if (err) { 819 amdgpu_ucode_release(&adev->gfx.pfp_fw); 820 amdgpu_ucode_release(&adev->gfx.me_fw); 821 amdgpu_ucode_release(&adev->gfx.rlc_fw); 822 amdgpu_ucode_release(&adev->gfx.mec_fw); 823 } 824 825 return err; 826 } 827 828 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 829 { 830 u32 count = 0; 831 const struct cs_section_def *sect = NULL; 832 const struct cs_extent_def *ext = NULL; 833 834 /* begin clear state */ 835 count += 2; 836 /* context control state */ 837 count += 3; 838 839 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 840 for (ext = sect->section; ext->extent != NULL; ++ext) { 841 if (sect->id == SECT_CONTEXT) 842 count += 2 + ext->reg_count; 843 else 844 return 0; 845 } 846 } 847 848 /* set PA_SC_TILE_STEERING_OVERRIDE */ 849 count += 3; 850 /* end clear state */ 851 count += 2; 852 /* clear state */ 853 count += 2; 854 855 return count; 856 } 857 858 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 859 { 860 u32 count = 0; 861 int ctx_reg_offset; 862 863 if (adev->gfx.rlc.cs_data == NULL) 864 return; 865 if (buffer == NULL) 866 return; 867 868 count = amdgpu_gfx_csb_preamble_start(buffer); 869 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 870 871 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 872 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 873 buffer[count++] = cpu_to_le32(ctx_reg_offset); 874 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 875 876 amdgpu_gfx_csb_preamble_end(buffer, count); 877 } 878 879 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 880 { 881 /* clear state block */ 882 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 883 &adev->gfx.rlc.clear_state_gpu_addr, 884 (void **)&adev->gfx.rlc.cs_ptr); 885 886 /* jump table block */ 887 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 888 &adev->gfx.rlc.cp_table_gpu_addr, 889 (void **)&adev->gfx.rlc.cp_table_ptr); 890 } 891 892 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 893 { 894 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 895 896 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 897 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 898 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 899 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 900 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 901 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 902 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 903 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 904 adev->gfx.rlc.rlcg_reg_access_supported = true; 905 } 906 907 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 908 { 909 const struct cs_section_def *cs_data; 910 int r; 911 912 adev->gfx.rlc.cs_data = gfx11_cs_data; 913 914 cs_data = adev->gfx.rlc.cs_data; 915 916 if (cs_data) { 917 /* init clear state block */ 918 r = amdgpu_gfx_rlc_init_csb(adev); 919 if (r) 920 return r; 921 } 922 923 /* init spm vmid with 0xf */ 924 if (adev->gfx.rlc.funcs->update_spm_vmid) 925 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 926 927 return 0; 928 } 929 930 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 931 { 932 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 933 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 934 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 935 } 936 937 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 938 { 939 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 940 941 amdgpu_gfx_graphics_queue_acquire(adev); 942 } 943 944 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 945 { 946 int r; 947 u32 *hpd; 948 size_t mec_hpd_size; 949 950 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 951 952 /* take ownership of the relevant compute queues */ 953 amdgpu_gfx_compute_queue_acquire(adev); 954 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 955 956 if (mec_hpd_size) { 957 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 958 AMDGPU_GEM_DOMAIN_GTT, 959 &adev->gfx.mec.hpd_eop_obj, 960 &adev->gfx.mec.hpd_eop_gpu_addr, 961 (void **)&hpd); 962 if (r) { 963 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 964 gfx_v11_0_mec_fini(adev); 965 return r; 966 } 967 968 memset(hpd, 0, mec_hpd_size); 969 970 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 971 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 972 } 973 974 return 0; 975 } 976 977 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 978 { 979 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 980 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 981 (address << SQ_IND_INDEX__INDEX__SHIFT)); 982 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 983 } 984 985 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 986 uint32_t thread, uint32_t regno, 987 uint32_t num, uint32_t *out) 988 { 989 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 990 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 991 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 992 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 993 (SQ_IND_INDEX__AUTO_INCR_MASK)); 994 while (num--) 995 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 996 } 997 998 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 999 { 1000 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1001 * field when performing a select_se_sh so it should be 1002 * zero here */ 1003 WARN_ON(simd != 0); 1004 1005 /* type 3 wave data */ 1006 dst[(*no_fields)++] = 3; 1007 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1008 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1009 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1010 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1011 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1012 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1013 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1014 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1015 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1016 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1017 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1018 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1019 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1020 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1021 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1022 } 1023 1024 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1025 uint32_t wave, uint32_t start, 1026 uint32_t size, uint32_t *dst) 1027 { 1028 WARN_ON(simd != 0); 1029 1030 wave_read_regs( 1031 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1032 dst); 1033 } 1034 1035 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1036 uint32_t wave, uint32_t thread, 1037 uint32_t start, uint32_t size, 1038 uint32_t *dst) 1039 { 1040 wave_read_regs( 1041 adev, wave, thread, 1042 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1043 } 1044 1045 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1046 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1047 { 1048 soc21_grbm_select(adev, me, pipe, q, vm); 1049 } 1050 1051 /* all sizes are in bytes */ 1052 #define MQD_SHADOW_BASE_SIZE 73728 1053 #define MQD_SHADOW_BASE_ALIGNMENT 256 1054 #define MQD_FWWORKAREA_SIZE 484 1055 #define MQD_FWWORKAREA_ALIGNMENT 256 1056 1057 static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 1058 struct amdgpu_gfx_shadow_info *shadow_info) 1059 { 1060 /* for gfx */ 1061 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1062 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1063 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1064 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1065 /* for compute */ 1066 shadow_info->eop_size = GFX11_MEC_HPD_SIZE; 1067 shadow_info->eop_alignment = 256; 1068 } 1069 1070 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1071 struct amdgpu_gfx_shadow_info *shadow_info, 1072 bool skip_check) 1073 { 1074 if (adev->gfx.cp_gfx_shadow || skip_check) { 1075 gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 1076 return 0; 1077 } else { 1078 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1079 return -ENOTSUPP; 1080 } 1081 } 1082 1083 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1084 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1085 .select_se_sh = &gfx_v11_0_select_se_sh, 1086 .read_wave_data = &gfx_v11_0_read_wave_data, 1087 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1088 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1089 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1090 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1091 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1092 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 1093 }; 1094 1095 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1096 { 1097 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1098 case IP_VERSION(11, 0, 0): 1099 case IP_VERSION(11, 0, 2): 1100 adev->gfx.config.max_hw_contexts = 8; 1101 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1102 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1103 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1104 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1105 break; 1106 case IP_VERSION(11, 0, 3): 1107 adev->gfx.ras = &gfx_v11_0_3_ras; 1108 adev->gfx.config.max_hw_contexts = 8; 1109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1111 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1113 break; 1114 case IP_VERSION(11, 0, 1): 1115 case IP_VERSION(11, 0, 4): 1116 case IP_VERSION(11, 5, 0): 1117 case IP_VERSION(11, 5, 1): 1118 case IP_VERSION(11, 5, 2): 1119 case IP_VERSION(11, 5, 3): 1120 case IP_VERSION(11, 5, 4): 1121 adev->gfx.config.max_hw_contexts = 8; 1122 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1123 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1124 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1125 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1126 break; 1127 default: 1128 BUG(); 1129 break; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1136 int me, int pipe, int queue) 1137 { 1138 struct amdgpu_ring *ring; 1139 unsigned int irq_type; 1140 unsigned int hw_prio; 1141 1142 ring = &adev->gfx.gfx_ring[ring_id]; 1143 1144 ring->me = me; 1145 ring->pipe = pipe; 1146 ring->queue = queue; 1147 1148 ring->ring_obj = NULL; 1149 ring->use_doorbell = true; 1150 if (adev->gfx.disable_kq) { 1151 ring->no_scheduler = true; 1152 ring->no_user_submission = true; 1153 } 1154 1155 if (!ring_id) 1156 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1157 else 1158 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1159 ring->vm_hub = AMDGPU_GFXHUB(0); 1160 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1161 1162 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1163 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1164 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1165 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1166 hw_prio, NULL); 1167 } 1168 1169 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1170 int mec, int pipe, int queue) 1171 { 1172 int r; 1173 unsigned irq_type; 1174 struct amdgpu_ring *ring; 1175 unsigned int hw_prio; 1176 1177 ring = &adev->gfx.compute_ring[ring_id]; 1178 1179 /* mec0 is me1 */ 1180 ring->me = mec + 1; 1181 ring->pipe = pipe; 1182 ring->queue = queue; 1183 1184 ring->ring_obj = NULL; 1185 ring->use_doorbell = true; 1186 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1187 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1188 + (ring_id * GFX11_MEC_HPD_SIZE); 1189 ring->vm_hub = AMDGPU_GFXHUB(0); 1190 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1191 1192 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1193 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1194 + ring->pipe; 1195 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1196 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1197 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1198 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1199 hw_prio, NULL); 1200 if (r) 1201 return r; 1202 1203 return 0; 1204 } 1205 1206 static struct { 1207 SOC21_FIRMWARE_ID id; 1208 unsigned int offset; 1209 unsigned int size; 1210 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1211 1212 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1213 { 1214 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1215 1216 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1217 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1218 rlc_autoload_info[ucode->id].id = ucode->id; 1219 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1220 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1221 1222 ucode++; 1223 } 1224 } 1225 1226 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1227 { 1228 uint32_t total_size = 0; 1229 SOC21_FIRMWARE_ID id; 1230 1231 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1232 1233 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1234 total_size += rlc_autoload_info[id].size; 1235 1236 /* In case the offset in rlc toc ucode is aligned */ 1237 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1238 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1239 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1240 1241 return total_size; 1242 } 1243 1244 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1245 { 1246 int r; 1247 uint32_t total_size; 1248 1249 total_size = gfx_v11_0_calc_toc_total_size(adev); 1250 1251 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1252 AMDGPU_GEM_DOMAIN_VRAM | 1253 AMDGPU_GEM_DOMAIN_GTT, 1254 &adev->gfx.rlc.rlc_autoload_bo, 1255 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1256 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1257 1258 if (r) { 1259 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1260 return r; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1267 SOC21_FIRMWARE_ID id, 1268 const void *fw_data, 1269 uint32_t fw_size, 1270 uint32_t *fw_autoload_mask) 1271 { 1272 uint32_t toc_offset; 1273 uint32_t toc_fw_size; 1274 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1275 1276 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1277 return; 1278 1279 toc_offset = rlc_autoload_info[id].offset; 1280 toc_fw_size = rlc_autoload_info[id].size; 1281 1282 if (fw_size == 0) 1283 fw_size = toc_fw_size; 1284 1285 if (fw_size > toc_fw_size) 1286 fw_size = toc_fw_size; 1287 1288 memcpy(ptr + toc_offset, fw_data, fw_size); 1289 1290 if (fw_size < toc_fw_size) 1291 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1292 1293 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1294 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1295 } 1296 1297 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1298 uint32_t *fw_autoload_mask) 1299 { 1300 void *data; 1301 uint32_t size; 1302 uint64_t *toc_ptr; 1303 1304 *(uint64_t *)fw_autoload_mask |= 0x1; 1305 1306 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1307 1308 data = adev->psp.toc.start_addr; 1309 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1310 1311 toc_ptr = (uint64_t *)data + size / 8 - 1; 1312 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1313 1314 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1315 data, size, fw_autoload_mask); 1316 } 1317 1318 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1319 uint32_t *fw_autoload_mask) 1320 { 1321 const __le32 *fw_data; 1322 uint32_t fw_size; 1323 const struct gfx_firmware_header_v1_0 *cp_hdr; 1324 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1325 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1326 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1327 uint16_t version_major, version_minor; 1328 1329 if (adev->gfx.rs64_enable) { 1330 /* pfp ucode */ 1331 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1332 adev->gfx.pfp_fw->data; 1333 /* instruction */ 1334 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1335 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1336 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1337 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1338 fw_data, fw_size, fw_autoload_mask); 1339 /* data */ 1340 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1341 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1342 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1343 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1344 fw_data, fw_size, fw_autoload_mask); 1345 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1346 fw_data, fw_size, fw_autoload_mask); 1347 /* me ucode */ 1348 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1349 adev->gfx.me_fw->data; 1350 /* instruction */ 1351 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1352 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1353 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1354 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1355 fw_data, fw_size, fw_autoload_mask); 1356 /* data */ 1357 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1358 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1359 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1360 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1361 fw_data, fw_size, fw_autoload_mask); 1362 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1363 fw_data, fw_size, fw_autoload_mask); 1364 /* mec ucode */ 1365 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1366 adev->gfx.mec_fw->data; 1367 /* instruction */ 1368 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1369 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1370 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1371 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1372 fw_data, fw_size, fw_autoload_mask); 1373 /* data */ 1374 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1375 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1376 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1377 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1378 fw_data, fw_size, fw_autoload_mask); 1379 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1380 fw_data, fw_size, fw_autoload_mask); 1381 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1382 fw_data, fw_size, fw_autoload_mask); 1383 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1384 fw_data, fw_size, fw_autoload_mask); 1385 } else { 1386 /* pfp ucode */ 1387 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1388 adev->gfx.pfp_fw->data; 1389 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1390 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1391 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1392 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1393 fw_data, fw_size, fw_autoload_mask); 1394 1395 /* me ucode */ 1396 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1397 adev->gfx.me_fw->data; 1398 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1399 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1400 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1401 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1402 fw_data, fw_size, fw_autoload_mask); 1403 1404 /* mec ucode */ 1405 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1406 adev->gfx.mec_fw->data; 1407 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1408 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1409 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1410 cp_hdr->jt_size * 4; 1411 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1412 fw_data, fw_size, fw_autoload_mask); 1413 } 1414 1415 /* rlc ucode */ 1416 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1417 adev->gfx.rlc_fw->data; 1418 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1419 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1420 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1421 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1422 fw_data, fw_size, fw_autoload_mask); 1423 1424 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1425 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1426 if (version_major == 2) { 1427 if (version_minor >= 2) { 1428 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1429 1430 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1431 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1432 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1433 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1434 fw_data, fw_size, fw_autoload_mask); 1435 1436 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1437 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1438 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1439 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1440 fw_data, fw_size, fw_autoload_mask); 1441 } 1442 } 1443 } 1444 1445 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1446 uint32_t *fw_autoload_mask) 1447 { 1448 const __le32 *fw_data; 1449 uint32_t fw_size; 1450 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1451 1452 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1453 adev->sdma.instance[0].fw->data; 1454 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1455 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1456 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1457 1458 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1459 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1460 1461 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1462 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1463 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1464 1465 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1466 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1467 } 1468 1469 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1470 uint32_t *fw_autoload_mask) 1471 { 1472 const __le32 *fw_data; 1473 unsigned fw_size; 1474 const struct mes_firmware_header_v1_0 *mes_hdr; 1475 int pipe, ucode_id, data_id; 1476 1477 for (pipe = 0; pipe < 2; pipe++) { 1478 if (pipe==0) { 1479 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1480 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1481 } else { 1482 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1483 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1484 } 1485 1486 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1487 adev->mes.fw[pipe]->data; 1488 1489 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1490 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1491 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1492 1493 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1494 ucode_id, fw_data, fw_size, fw_autoload_mask); 1495 1496 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1497 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1498 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1499 1500 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1501 data_id, fw_data, fw_size, fw_autoload_mask); 1502 } 1503 } 1504 1505 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1506 { 1507 uint32_t rlc_g_offset, rlc_g_size; 1508 uint64_t gpu_addr; 1509 uint32_t autoload_fw_id[2]; 1510 1511 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1512 1513 /* RLC autoload sequence 2: copy ucode */ 1514 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1515 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1516 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1517 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1518 1519 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1520 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1521 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1522 1523 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1524 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1525 1526 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1527 1528 /* RLC autoload sequence 3: load IMU fw */ 1529 if (adev->gfx.imu.funcs->load_microcode) 1530 adev->gfx.imu.funcs->load_microcode(adev); 1531 /* RLC autoload sequence 4 init IMU fw */ 1532 if (adev->gfx.imu.funcs->setup_imu) 1533 adev->gfx.imu.funcs->setup_imu(adev); 1534 if (adev->gfx.imu.funcs->start_imu) 1535 adev->gfx.imu.funcs->start_imu(adev); 1536 1537 /* RLC autoload sequence 5 disable gpa mode */ 1538 gfx_v11_0_disable_gpa_mode(adev); 1539 1540 return 0; 1541 } 1542 1543 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1544 { 1545 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1546 uint32_t *ptr; 1547 uint32_t inst; 1548 1549 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1550 if (!ptr) { 1551 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1552 adev->gfx.ip_dump_core = NULL; 1553 } else { 1554 adev->gfx.ip_dump_core = ptr; 1555 } 1556 1557 /* Allocate memory for compute queue registers for all the instances */ 1558 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1559 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1560 adev->gfx.mec.num_queue_per_pipe; 1561 1562 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1563 if (!ptr) { 1564 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1565 adev->gfx.ip_dump_compute_queues = NULL; 1566 } else { 1567 adev->gfx.ip_dump_compute_queues = ptr; 1568 } 1569 1570 /* Allocate memory for gfx queue registers for all the instances */ 1571 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1572 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1573 adev->gfx.me.num_queue_per_pipe; 1574 1575 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1576 if (!ptr) { 1577 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1578 adev->gfx.ip_dump_gfx_queues = NULL; 1579 } else { 1580 adev->gfx.ip_dump_gfx_queues = ptr; 1581 } 1582 } 1583 1584 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1585 { 1586 int i, j, k, r, ring_id; 1587 int xcc_id = 0; 1588 struct amdgpu_device *adev = ip_block->adev; 1589 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1590 1591 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1592 1593 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1594 case IP_VERSION(11, 0, 0): 1595 case IP_VERSION(11, 0, 1): 1596 case IP_VERSION(11, 0, 2): 1597 case IP_VERSION(11, 0, 3): 1598 case IP_VERSION(11, 0, 4): 1599 case IP_VERSION(11, 5, 0): 1600 case IP_VERSION(11, 5, 1): 1601 case IP_VERSION(11, 5, 2): 1602 case IP_VERSION(11, 5, 3): 1603 case IP_VERSION(11, 5, 4): 1604 adev->gfx.me.num_me = 1; 1605 adev->gfx.me.num_pipe_per_me = 1; 1606 adev->gfx.me.num_queue_per_pipe = 2; 1607 adev->gfx.mec.num_mec = 1; 1608 adev->gfx.mec.num_pipe_per_mec = 4; 1609 adev->gfx.mec.num_queue_per_pipe = 4; 1610 break; 1611 default: 1612 adev->gfx.me.num_me = 1; 1613 adev->gfx.me.num_pipe_per_me = 1; 1614 adev->gfx.me.num_queue_per_pipe = 1; 1615 adev->gfx.mec.num_mec = 1; 1616 adev->gfx.mec.num_pipe_per_mec = 4; 1617 adev->gfx.mec.num_queue_per_pipe = 8; 1618 break; 1619 } 1620 1621 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1622 case IP_VERSION(11, 0, 0): 1623 case IP_VERSION(11, 0, 2): 1624 case IP_VERSION(11, 0, 3): 1625 if (!adev->gfx.disable_uq && 1626 adev->gfx.me_fw_version >= 2420 && 1627 adev->gfx.pfp_fw_version >= 2580 && 1628 adev->gfx.mec_fw_version >= 2650 && 1629 adev->mes.fw_version[0] >= 120) { 1630 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1631 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1632 } 1633 break; 1634 case IP_VERSION(11, 0, 1): 1635 case IP_VERSION(11, 0, 4): 1636 case IP_VERSION(11, 5, 0): 1637 case IP_VERSION(11, 5, 1): 1638 case IP_VERSION(11, 5, 2): 1639 case IP_VERSION(11, 5, 3): 1640 /* add firmware version checks here */ 1641 if (0 && !adev->gfx.disable_uq) { 1642 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1643 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1644 } 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1651 case IP_VERSION(11, 0, 0): 1652 case IP_VERSION(11, 0, 2): 1653 case IP_VERSION(11, 0, 3): 1654 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1655 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1656 if (adev->gfx.me_fw_version >= 2280 && 1657 adev->gfx.pfp_fw_version >= 2370 && 1658 adev->gfx.mec_fw_version >= 2450 && 1659 adev->mes.fw_version[0] >= 99) { 1660 adev->gfx.enable_cleaner_shader = true; 1661 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1662 if (r) { 1663 adev->gfx.enable_cleaner_shader = false; 1664 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1665 } 1666 } 1667 break; 1668 case IP_VERSION(11, 0, 1): 1669 case IP_VERSION(11, 0, 4): 1670 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1671 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1672 if (adev->gfx.pfp_fw_version >= 102 && 1673 adev->gfx.mec_fw_version >= 66 && 1674 adev->mes.fw_version[0] >= 128) { 1675 adev->gfx.enable_cleaner_shader = true; 1676 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1677 if (r) { 1678 adev->gfx.enable_cleaner_shader = false; 1679 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1680 } 1681 } 1682 break; 1683 case IP_VERSION(11, 5, 0): 1684 case IP_VERSION(11, 5, 1): 1685 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1686 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1687 if (adev->gfx.mec_fw_version >= 26 && 1688 adev->mes.fw_version[0] >= 114) { 1689 adev->gfx.enable_cleaner_shader = true; 1690 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1691 if (r) { 1692 adev->gfx.enable_cleaner_shader = false; 1693 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1694 } 1695 } 1696 break; 1697 case IP_VERSION(11, 5, 2): 1698 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1699 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1700 if (adev->gfx.me_fw_version >= 12 && 1701 adev->gfx.pfp_fw_version >= 15 && 1702 adev->gfx.mec_fw_version >= 15) { 1703 adev->gfx.enable_cleaner_shader = true; 1704 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1705 if (r) { 1706 adev->gfx.enable_cleaner_shader = false; 1707 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1708 } 1709 } 1710 break; 1711 case IP_VERSION(11, 5, 3): 1712 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1713 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1714 if (adev->gfx.me_fw_version >= 7 && 1715 adev->gfx.pfp_fw_version >= 8 && 1716 adev->gfx.mec_fw_version >= 8) { 1717 adev->gfx.enable_cleaner_shader = true; 1718 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1719 if (r) { 1720 adev->gfx.enable_cleaner_shader = false; 1721 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1722 } 1723 } 1724 break; 1725 default: 1726 adev->gfx.enable_cleaner_shader = false; 1727 break; 1728 } 1729 1730 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1731 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1732 amdgpu_sriov_is_pp_one_vf(adev)) 1733 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1734 1735 /* EOP Event */ 1736 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1737 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1738 &adev->gfx.eop_irq); 1739 if (r) 1740 return r; 1741 1742 /* Bad opcode Event */ 1743 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1744 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1745 &adev->gfx.bad_op_irq); 1746 if (r) 1747 return r; 1748 1749 /* Privileged reg */ 1750 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1751 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1752 &adev->gfx.priv_reg_irq); 1753 if (r) 1754 return r; 1755 1756 /* Privileged inst */ 1757 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1758 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1759 &adev->gfx.priv_inst_irq); 1760 if (r) 1761 return r; 1762 1763 /* FED error */ 1764 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1765 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1766 &adev->gfx.rlc_gc_fed_irq); 1767 if (r) 1768 return r; 1769 1770 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1771 1772 gfx_v11_0_me_init(adev); 1773 1774 r = gfx_v11_0_rlc_init(adev); 1775 if (r) { 1776 DRM_ERROR("Failed to init rlc BOs!\n"); 1777 return r; 1778 } 1779 1780 r = gfx_v11_0_mec_init(adev); 1781 if (r) { 1782 DRM_ERROR("Failed to init MEC BOs!\n"); 1783 return r; 1784 } 1785 1786 if (adev->gfx.num_gfx_rings) { 1787 ring_id = 0; 1788 /* set up the gfx ring */ 1789 for (i = 0; i < adev->gfx.me.num_me; i++) { 1790 for (j = 0; j < num_queue_per_pipe; j++) { 1791 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1792 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1793 continue; 1794 1795 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1796 i, k, j); 1797 if (r) 1798 return r; 1799 ring_id++; 1800 } 1801 } 1802 } 1803 } 1804 1805 if (adev->gfx.num_compute_rings) { 1806 ring_id = 0; 1807 /* set up the compute queues - allocate horizontally across pipes */ 1808 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1809 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1810 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1811 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1812 k, j)) 1813 continue; 1814 1815 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1816 i, k, j); 1817 if (r) 1818 return r; 1819 1820 ring_id++; 1821 } 1822 } 1823 } 1824 } 1825 1826 adev->gfx.gfx_supported_reset = 1827 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1828 adev->gfx.compute_supported_reset = 1829 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1830 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1831 case IP_VERSION(11, 0, 0): 1832 case IP_VERSION(11, 0, 2): 1833 case IP_VERSION(11, 0, 3): 1834 if ((adev->gfx.me_fw_version >= 2280) && 1835 (adev->gfx.mec_fw_version >= 2410) && 1836 !amdgpu_sriov_vf(adev) && 1837 !adev->debug_disable_gpu_ring_reset) { 1838 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1839 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1840 } 1841 break; 1842 default: 1843 if (!amdgpu_sriov_vf(adev) && 1844 !adev->debug_disable_gpu_ring_reset) { 1845 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1846 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1847 } 1848 break; 1849 } 1850 1851 if (!adev->enable_mes_kiq) { 1852 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1853 if (r) { 1854 DRM_ERROR("Failed to init KIQ BOs!\n"); 1855 return r; 1856 } 1857 1858 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1859 if (r) 1860 return r; 1861 } 1862 1863 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1864 if (r) 1865 return r; 1866 1867 /* allocate visible FB for rlc auto-loading fw */ 1868 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1869 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1870 if (r) 1871 return r; 1872 } 1873 1874 r = gfx_v11_0_gpu_early_init(adev); 1875 if (r) 1876 return r; 1877 1878 if (amdgpu_gfx_ras_sw_init(adev)) { 1879 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1880 return -EINVAL; 1881 } 1882 1883 gfx_v11_0_alloc_ip_dump(adev); 1884 1885 r = amdgpu_gfx_sysfs_init(adev); 1886 if (r) 1887 return r; 1888 1889 return 0; 1890 } 1891 1892 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1893 { 1894 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1895 &adev->gfx.pfp.pfp_fw_gpu_addr, 1896 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1897 1898 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1899 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1900 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1901 } 1902 1903 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1904 { 1905 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1906 &adev->gfx.me.me_fw_gpu_addr, 1907 (void **)&adev->gfx.me.me_fw_ptr); 1908 1909 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1910 &adev->gfx.me.me_fw_data_gpu_addr, 1911 (void **)&adev->gfx.me.me_fw_data_ptr); 1912 } 1913 1914 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1915 { 1916 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1917 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1918 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1919 } 1920 1921 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1922 { 1923 int i; 1924 struct amdgpu_device *adev = ip_block->adev; 1925 1926 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1927 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1928 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1929 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1930 1931 amdgpu_gfx_mqd_sw_fini(adev, 0); 1932 1933 if (!adev->enable_mes_kiq) { 1934 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1935 amdgpu_gfx_kiq_fini(adev, 0); 1936 } 1937 1938 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1939 1940 gfx_v11_0_pfp_fini(adev); 1941 gfx_v11_0_me_fini(adev); 1942 gfx_v11_0_rlc_fini(adev); 1943 gfx_v11_0_mec_fini(adev); 1944 1945 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1946 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1947 1948 gfx_v11_0_free_microcode(adev); 1949 1950 amdgpu_gfx_sysfs_fini(adev); 1951 1952 kfree(adev->gfx.ip_dump_core); 1953 kfree(adev->gfx.ip_dump_compute_queues); 1954 kfree(adev->gfx.ip_dump_gfx_queues); 1955 1956 return 0; 1957 } 1958 1959 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1960 u32 sh_num, u32 instance, int xcc_id) 1961 { 1962 u32 data; 1963 1964 if (instance == 0xffffffff) 1965 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1966 INSTANCE_BROADCAST_WRITES, 1); 1967 else 1968 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1969 instance); 1970 1971 if (se_num == 0xffffffff) 1972 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1973 1); 1974 else 1975 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1976 1977 if (sh_num == 0xffffffff) 1978 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1979 1); 1980 else 1981 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1982 1983 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1984 } 1985 1986 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1987 { 1988 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1989 1990 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1991 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1992 CC_GC_SA_UNIT_DISABLE, 1993 SA_DISABLE); 1994 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1995 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1996 GC_USER_SA_UNIT_DISABLE, 1997 SA_DISABLE); 1998 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1999 adev->gfx.config.max_shader_engines); 2000 2001 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 2002 } 2003 2004 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2005 { 2006 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 2007 u32 rb_mask; 2008 2009 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 2010 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 2011 CC_RB_BACKEND_DISABLE, 2012 BACKEND_DISABLE); 2013 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 2014 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 2015 GC_USER_RB_BACKEND_DISABLE, 2016 BACKEND_DISABLE); 2017 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 2018 adev->gfx.config.max_shader_engines); 2019 2020 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 2021 } 2022 2023 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 2024 { 2025 u32 rb_bitmap_per_sa; 2026 u32 rb_bitmap_width_per_sa; 2027 u32 max_sa; 2028 u32 active_sa_bitmap; 2029 u32 global_active_rb_bitmap; 2030 u32 active_rb_bitmap = 0; 2031 u32 i; 2032 2033 /* query sa bitmap from SA_UNIT_DISABLE registers */ 2034 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 2035 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 2036 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 2037 2038 /* generate active rb bitmap according to active sa bitmap */ 2039 max_sa = adev->gfx.config.max_shader_engines * 2040 adev->gfx.config.max_sh_per_se; 2041 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 2042 adev->gfx.config.max_sh_per_se; 2043 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 2044 2045 for (i = 0; i < max_sa; i++) { 2046 if (active_sa_bitmap & (1 << i)) 2047 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 2048 } 2049 2050 active_rb_bitmap &= global_active_rb_bitmap; 2051 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 2052 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 2053 } 2054 2055 #define DEFAULT_SH_MEM_BASES (0x6000) 2056 #define LDS_APP_BASE 0x1 2057 #define SCRATCH_APP_BASE 0x2 2058 2059 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 2060 { 2061 int i; 2062 uint32_t sh_mem_bases; 2063 uint32_t data; 2064 2065 /* 2066 * Configure apertures: 2067 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2068 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2069 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2070 */ 2071 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 2072 SCRATCH_APP_BASE; 2073 2074 mutex_lock(&adev->srbm_mutex); 2075 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2076 soc21_grbm_select(adev, 0, 0, 0, i); 2077 /* CP and shaders */ 2078 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2079 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 2080 2081 /* Enable trap for each kfd vmid. */ 2082 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 2083 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 2084 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 2085 } 2086 soc21_grbm_select(adev, 0, 0, 0, 0); 2087 mutex_unlock(&adev->srbm_mutex); 2088 2089 /* 2090 * Initialize all compute VMIDs to have no GDS, GWS, or OA 2091 * access. These should be enabled by FW for target VMIDs. 2092 */ 2093 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2094 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 2095 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 2096 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 2097 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 2098 } 2099 } 2100 2101 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 2102 { 2103 int vmid; 2104 2105 /* 2106 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2107 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2108 * the driver can enable them for graphics. VMID0 should maintain 2109 * access so that HWS firmware can save/restore entries. 2110 */ 2111 for (vmid = 1; vmid < 16; vmid++) { 2112 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 2113 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 2114 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 2115 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 2116 } 2117 } 2118 2119 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 2120 { 2121 /* TODO: harvest feature to be added later. */ 2122 } 2123 2124 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2125 { 2126 /* TCCs are global (not instanced). */ 2127 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2128 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2129 2130 adev->gfx.config.tcc_disabled_mask = 2131 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2132 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2133 } 2134 2135 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2136 { 2137 u32 tmp; 2138 int i; 2139 2140 if (!amdgpu_sriov_vf(adev)) 2141 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2142 2143 gfx_v11_0_setup_rb(adev); 2144 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2145 gfx_v11_0_get_tcc_info(adev); 2146 adev->gfx.config.pa_sc_tile_steering_override = 0; 2147 2148 /* Set whether texture coordinate truncation is conformant. */ 2149 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2150 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2151 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2152 2153 /* XXX SH_MEM regs */ 2154 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2155 mutex_lock(&adev->srbm_mutex); 2156 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2157 soc21_grbm_select(adev, 0, 0, 0, i); 2158 /* CP and shaders */ 2159 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2160 if (i != 0) { 2161 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2162 (adev->gmc.private_aperture_start >> 48)); 2163 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2164 (adev->gmc.shared_aperture_start >> 48)); 2165 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2166 } 2167 } 2168 soc21_grbm_select(adev, 0, 0, 0, 0); 2169 2170 mutex_unlock(&adev->srbm_mutex); 2171 2172 gfx_v11_0_init_compute_vmid(adev); 2173 gfx_v11_0_init_gds_vmid(adev); 2174 } 2175 2176 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2177 int me, int pipe) 2178 { 2179 if (me != 0) 2180 return 0; 2181 2182 switch (pipe) { 2183 case 0: 2184 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2185 case 1: 2186 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2187 default: 2188 return 0; 2189 } 2190 } 2191 2192 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2193 int me, int pipe) 2194 { 2195 /* 2196 * amdgpu controls only the first MEC. That's why this function only 2197 * handles the setting of interrupts for this specific MEC. All other 2198 * pipes' interrupts are set by amdkfd. 2199 */ 2200 if (me != 1) 2201 return 0; 2202 2203 switch (pipe) { 2204 case 0: 2205 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2206 case 1: 2207 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2208 case 2: 2209 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2210 case 3: 2211 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2212 default: 2213 return 0; 2214 } 2215 } 2216 2217 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2218 bool enable) 2219 { 2220 u32 tmp, cp_int_cntl_reg; 2221 int i, j; 2222 2223 if (amdgpu_sriov_vf(adev)) 2224 return; 2225 2226 for (i = 0; i < adev->gfx.me.num_me; i++) { 2227 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2228 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2229 2230 if (cp_int_cntl_reg) { 2231 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2232 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2233 enable ? 1 : 0); 2234 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2235 enable ? 1 : 0); 2236 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2237 enable ? 1 : 0); 2238 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2239 enable ? 1 : 0); 2240 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2241 } 2242 } 2243 } 2244 } 2245 2246 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2247 { 2248 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2249 2250 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2251 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2252 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2253 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2254 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2255 2256 return 0; 2257 } 2258 2259 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2260 { 2261 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2262 2263 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2264 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2265 } 2266 2267 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2268 { 2269 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2270 udelay(50); 2271 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2272 udelay(50); 2273 } 2274 2275 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2276 bool enable) 2277 { 2278 uint32_t rlc_pg_cntl; 2279 2280 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2281 2282 if (!enable) { 2283 /* RLC_PG_CNTL[23] = 0 (default) 2284 * RLC will wait for handshake acks with SMU 2285 * GFXOFF will be enabled 2286 * RLC_PG_CNTL[23] = 1 2287 * RLC will not issue any message to SMU 2288 * hence no handshake between SMU & RLC 2289 * GFXOFF will be disabled 2290 */ 2291 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2292 } else 2293 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2294 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2295 } 2296 2297 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2298 { 2299 /* TODO: enable rlc & smu handshake until smu 2300 * and gfxoff feature works as expected */ 2301 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2302 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2303 2304 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2305 udelay(50); 2306 } 2307 2308 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2309 { 2310 uint32_t tmp; 2311 2312 /* enable Save Restore Machine */ 2313 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2314 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2315 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2316 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2317 } 2318 2319 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2320 { 2321 const struct rlc_firmware_header_v2_0 *hdr; 2322 const __le32 *fw_data; 2323 unsigned i, fw_size; 2324 2325 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2326 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2327 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2328 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2329 2330 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2331 RLCG_UCODE_LOADING_START_ADDRESS); 2332 2333 for (i = 0; i < fw_size; i++) 2334 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2335 le32_to_cpup(fw_data++)); 2336 2337 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2338 } 2339 2340 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2341 { 2342 const struct rlc_firmware_header_v2_2 *hdr; 2343 const __le32 *fw_data; 2344 unsigned i, fw_size; 2345 u32 tmp; 2346 2347 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2348 2349 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2350 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2351 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2352 2353 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2354 2355 for (i = 0; i < fw_size; i++) { 2356 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2357 msleep(1); 2358 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2359 le32_to_cpup(fw_data++)); 2360 } 2361 2362 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2363 2364 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2365 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2366 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2367 2368 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2369 for (i = 0; i < fw_size; i++) { 2370 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2371 msleep(1); 2372 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2373 le32_to_cpup(fw_data++)); 2374 } 2375 2376 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2377 2378 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2379 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2380 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2381 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2382 } 2383 2384 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2385 { 2386 const struct rlc_firmware_header_v2_3 *hdr; 2387 const __le32 *fw_data; 2388 unsigned i, fw_size; 2389 u32 tmp; 2390 2391 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2392 2393 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2394 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2395 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2396 2397 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2398 2399 for (i = 0; i < fw_size; i++) { 2400 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2401 msleep(1); 2402 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2403 le32_to_cpup(fw_data++)); 2404 } 2405 2406 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2407 2408 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2409 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2410 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2411 2412 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2413 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2414 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2415 2416 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2417 2418 for (i = 0; i < fw_size; i++) { 2419 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2420 msleep(1); 2421 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2422 le32_to_cpup(fw_data++)); 2423 } 2424 2425 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2426 2427 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2428 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2429 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2430 } 2431 2432 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2433 { 2434 const struct rlc_firmware_header_v2_0 *hdr; 2435 uint16_t version_major; 2436 uint16_t version_minor; 2437 2438 if (!adev->gfx.rlc_fw) 2439 return -EINVAL; 2440 2441 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2442 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2443 2444 version_major = le16_to_cpu(hdr->header.header_version_major); 2445 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2446 2447 if (version_major == 2) { 2448 gfx_v11_0_load_rlcg_microcode(adev); 2449 if (amdgpu_dpm == 1) { 2450 if (version_minor >= 2) 2451 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2452 if (version_minor == 3) 2453 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2454 } 2455 2456 return 0; 2457 } 2458 2459 return -EINVAL; 2460 } 2461 2462 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2463 { 2464 int r; 2465 2466 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2467 gfx_v11_0_init_csb(adev); 2468 2469 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2470 gfx_v11_0_rlc_enable_srm(adev); 2471 } else { 2472 if (amdgpu_sriov_vf(adev)) { 2473 gfx_v11_0_init_csb(adev); 2474 return 0; 2475 } 2476 2477 adev->gfx.rlc.funcs->stop(adev); 2478 2479 /* disable CG */ 2480 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2481 2482 /* disable PG */ 2483 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2484 2485 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2486 /* legacy rlc firmware loading */ 2487 r = gfx_v11_0_rlc_load_microcode(adev); 2488 if (r) 2489 return r; 2490 } 2491 2492 gfx_v11_0_init_csb(adev); 2493 2494 adev->gfx.rlc.funcs->start(adev); 2495 } 2496 return 0; 2497 } 2498 2499 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2500 { 2501 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2502 uint32_t tmp; 2503 int i; 2504 2505 /* Trigger an invalidation of the L1 instruction caches */ 2506 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2507 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2508 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2509 2510 /* Wait for invalidation complete */ 2511 for (i = 0; i < usec_timeout; i++) { 2512 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2513 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2514 INVALIDATE_CACHE_COMPLETE)) 2515 break; 2516 udelay(1); 2517 } 2518 2519 if (i >= usec_timeout) { 2520 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2521 return -EINVAL; 2522 } 2523 2524 if (amdgpu_emu_mode == 1) 2525 amdgpu_device_flush_hdp(adev, NULL); 2526 2527 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2528 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2529 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2530 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2531 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2532 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2533 2534 /* Program me ucode address into intruction cache address register */ 2535 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2536 lower_32_bits(addr) & 0xFFFFF000); 2537 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2538 upper_32_bits(addr)); 2539 2540 return 0; 2541 } 2542 2543 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2544 { 2545 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2546 uint32_t tmp; 2547 int i; 2548 2549 /* Trigger an invalidation of the L1 instruction caches */ 2550 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2551 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2552 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2553 2554 /* Wait for invalidation complete */ 2555 for (i = 0; i < usec_timeout; i++) { 2556 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2557 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2558 INVALIDATE_CACHE_COMPLETE)) 2559 break; 2560 udelay(1); 2561 } 2562 2563 if (i >= usec_timeout) { 2564 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2565 return -EINVAL; 2566 } 2567 2568 if (amdgpu_emu_mode == 1) 2569 amdgpu_device_flush_hdp(adev, NULL); 2570 2571 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2572 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2573 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2574 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2575 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2576 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2577 2578 /* Program pfp ucode address into intruction cache address register */ 2579 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2580 lower_32_bits(addr) & 0xFFFFF000); 2581 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2582 upper_32_bits(addr)); 2583 2584 return 0; 2585 } 2586 2587 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2588 { 2589 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2590 uint32_t tmp; 2591 int i; 2592 2593 /* Trigger an invalidation of the L1 instruction caches */ 2594 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2595 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2596 2597 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2598 2599 /* Wait for invalidation complete */ 2600 for (i = 0; i < usec_timeout; i++) { 2601 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2602 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2603 INVALIDATE_CACHE_COMPLETE)) 2604 break; 2605 udelay(1); 2606 } 2607 2608 if (i >= usec_timeout) { 2609 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2610 return -EINVAL; 2611 } 2612 2613 if (amdgpu_emu_mode == 1) 2614 amdgpu_device_flush_hdp(adev, NULL); 2615 2616 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2617 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2618 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2619 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2620 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2621 2622 /* Program mec1 ucode address into intruction cache address register */ 2623 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2624 lower_32_bits(addr) & 0xFFFFF000); 2625 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2626 upper_32_bits(addr)); 2627 2628 return 0; 2629 } 2630 2631 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2632 { 2633 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2634 uint32_t tmp; 2635 unsigned i, pipe_id; 2636 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2637 2638 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2639 adev->gfx.pfp_fw->data; 2640 2641 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2642 lower_32_bits(addr)); 2643 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2644 upper_32_bits(addr)); 2645 2646 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2647 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2648 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2649 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2650 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2651 2652 /* 2653 * Programming any of the CP_PFP_IC_BASE registers 2654 * forces invalidation of the ME L1 I$. Wait for the 2655 * invalidation complete 2656 */ 2657 for (i = 0; i < usec_timeout; i++) { 2658 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2659 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2660 INVALIDATE_CACHE_COMPLETE)) 2661 break; 2662 udelay(1); 2663 } 2664 2665 if (i >= usec_timeout) { 2666 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2667 return -EINVAL; 2668 } 2669 2670 /* Prime the L1 instruction caches */ 2671 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2672 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2673 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2674 /* Waiting for cache primed*/ 2675 for (i = 0; i < usec_timeout; i++) { 2676 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2677 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2678 ICACHE_PRIMED)) 2679 break; 2680 udelay(1); 2681 } 2682 2683 if (i >= usec_timeout) { 2684 dev_err(adev->dev, "failed to prime instruction cache\n"); 2685 return -EINVAL; 2686 } 2687 2688 mutex_lock(&adev->srbm_mutex); 2689 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2690 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2691 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2692 (pfp_hdr->ucode_start_addr_hi << 30) | 2693 (pfp_hdr->ucode_start_addr_lo >> 2)); 2694 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2695 pfp_hdr->ucode_start_addr_hi >> 2); 2696 2697 /* 2698 * Program CP_ME_CNTL to reset given PIPE to take 2699 * effect of CP_PFP_PRGRM_CNTR_START. 2700 */ 2701 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2702 if (pipe_id == 0) 2703 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2704 PFP_PIPE0_RESET, 1); 2705 else 2706 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2707 PFP_PIPE1_RESET, 1); 2708 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2709 2710 /* Clear pfp pipe0 reset bit. */ 2711 if (pipe_id == 0) 2712 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2713 PFP_PIPE0_RESET, 0); 2714 else 2715 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2716 PFP_PIPE1_RESET, 0); 2717 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2718 2719 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2720 lower_32_bits(addr2)); 2721 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2722 upper_32_bits(addr2)); 2723 } 2724 soc21_grbm_select(adev, 0, 0, 0, 0); 2725 mutex_unlock(&adev->srbm_mutex); 2726 2727 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2728 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2729 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2730 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2731 2732 /* Invalidate the data caches */ 2733 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2734 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2735 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2736 2737 for (i = 0; i < usec_timeout; i++) { 2738 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2739 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2740 INVALIDATE_DCACHE_COMPLETE)) 2741 break; 2742 udelay(1); 2743 } 2744 2745 if (i >= usec_timeout) { 2746 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2747 return -EINVAL; 2748 } 2749 2750 return 0; 2751 } 2752 2753 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2754 { 2755 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2756 uint32_t tmp; 2757 unsigned i, pipe_id; 2758 const struct gfx_firmware_header_v2_0 *me_hdr; 2759 2760 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2761 adev->gfx.me_fw->data; 2762 2763 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2764 lower_32_bits(addr)); 2765 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2766 upper_32_bits(addr)); 2767 2768 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2769 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2770 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2771 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2772 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2773 2774 /* 2775 * Programming any of the CP_ME_IC_BASE registers 2776 * forces invalidation of the ME L1 I$. Wait for the 2777 * invalidation complete 2778 */ 2779 for (i = 0; i < usec_timeout; i++) { 2780 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2781 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2782 INVALIDATE_CACHE_COMPLETE)) 2783 break; 2784 udelay(1); 2785 } 2786 2787 if (i >= usec_timeout) { 2788 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2789 return -EINVAL; 2790 } 2791 2792 /* Prime the instruction caches */ 2793 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2794 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2795 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2796 2797 /* Waiting for instruction cache primed*/ 2798 for (i = 0; i < usec_timeout; i++) { 2799 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2800 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2801 ICACHE_PRIMED)) 2802 break; 2803 udelay(1); 2804 } 2805 2806 if (i >= usec_timeout) { 2807 dev_err(adev->dev, "failed to prime instruction cache\n"); 2808 return -EINVAL; 2809 } 2810 2811 mutex_lock(&adev->srbm_mutex); 2812 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2813 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2814 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2815 (me_hdr->ucode_start_addr_hi << 30) | 2816 (me_hdr->ucode_start_addr_lo >> 2) ); 2817 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2818 me_hdr->ucode_start_addr_hi>>2); 2819 2820 /* 2821 * Program CP_ME_CNTL to reset given PIPE to take 2822 * effect of CP_PFP_PRGRM_CNTR_START. 2823 */ 2824 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2825 if (pipe_id == 0) 2826 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2827 ME_PIPE0_RESET, 1); 2828 else 2829 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2830 ME_PIPE1_RESET, 1); 2831 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2832 2833 /* Clear pfp pipe0 reset bit. */ 2834 if (pipe_id == 0) 2835 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2836 ME_PIPE0_RESET, 0); 2837 else 2838 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2839 ME_PIPE1_RESET, 0); 2840 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2841 2842 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2843 lower_32_bits(addr2)); 2844 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2845 upper_32_bits(addr2)); 2846 } 2847 soc21_grbm_select(adev, 0, 0, 0, 0); 2848 mutex_unlock(&adev->srbm_mutex); 2849 2850 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2851 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2852 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2853 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2854 2855 /* Invalidate the data caches */ 2856 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2857 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2858 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2859 2860 for (i = 0; i < usec_timeout; i++) { 2861 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2862 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2863 INVALIDATE_DCACHE_COMPLETE)) 2864 break; 2865 udelay(1); 2866 } 2867 2868 if (i >= usec_timeout) { 2869 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2870 return -EINVAL; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2877 { 2878 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2879 uint32_t tmp; 2880 unsigned i; 2881 const struct gfx_firmware_header_v2_0 *mec_hdr; 2882 2883 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2884 adev->gfx.mec_fw->data; 2885 2886 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2887 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2888 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2889 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2890 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2891 2892 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2893 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2894 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2895 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2896 2897 mutex_lock(&adev->srbm_mutex); 2898 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2899 soc21_grbm_select(adev, 1, i, 0, 0); 2900 2901 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2902 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2903 upper_32_bits(addr2)); 2904 2905 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2906 mec_hdr->ucode_start_addr_lo >> 2 | 2907 mec_hdr->ucode_start_addr_hi << 30); 2908 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2909 mec_hdr->ucode_start_addr_hi >> 2); 2910 2911 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2912 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2913 upper_32_bits(addr)); 2914 } 2915 mutex_unlock(&adev->srbm_mutex); 2916 soc21_grbm_select(adev, 0, 0, 0, 0); 2917 2918 /* Trigger an invalidation of the L1 instruction caches */ 2919 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2920 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2921 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2922 2923 /* Wait for invalidation complete */ 2924 for (i = 0; i < usec_timeout; i++) { 2925 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2926 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2927 INVALIDATE_DCACHE_COMPLETE)) 2928 break; 2929 udelay(1); 2930 } 2931 2932 if (i >= usec_timeout) { 2933 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2934 return -EINVAL; 2935 } 2936 2937 /* Trigger an invalidation of the L1 instruction caches */ 2938 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2939 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2940 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2941 2942 /* Wait for invalidation complete */ 2943 for (i = 0; i < usec_timeout; i++) { 2944 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2945 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2946 INVALIDATE_CACHE_COMPLETE)) 2947 break; 2948 udelay(1); 2949 } 2950 2951 if (i >= usec_timeout) { 2952 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2953 return -EINVAL; 2954 } 2955 2956 return 0; 2957 } 2958 2959 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2960 { 2961 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2962 const struct gfx_firmware_header_v2_0 *me_hdr; 2963 const struct gfx_firmware_header_v2_0 *mec_hdr; 2964 uint32_t pipe_id, tmp; 2965 2966 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2967 adev->gfx.mec_fw->data; 2968 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2969 adev->gfx.me_fw->data; 2970 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2971 adev->gfx.pfp_fw->data; 2972 2973 /* config pfp program start addr */ 2974 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2975 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2976 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2977 (pfp_hdr->ucode_start_addr_hi << 30) | 2978 (pfp_hdr->ucode_start_addr_lo >> 2)); 2979 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2980 pfp_hdr->ucode_start_addr_hi >> 2); 2981 } 2982 soc21_grbm_select(adev, 0, 0, 0, 0); 2983 2984 /* reset pfp pipe */ 2985 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2986 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2987 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2988 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2989 2990 /* clear pfp pipe reset */ 2991 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2992 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2993 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2994 2995 /* config me program start addr */ 2996 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2997 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2998 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2999 (me_hdr->ucode_start_addr_hi << 30) | 3000 (me_hdr->ucode_start_addr_lo >> 2) ); 3001 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3002 me_hdr->ucode_start_addr_hi>>2); 3003 } 3004 soc21_grbm_select(adev, 0, 0, 0, 0); 3005 3006 /* reset me pipe */ 3007 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3008 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 3009 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 3010 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3011 3012 /* clear me pipe reset */ 3013 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 3014 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 3015 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3016 3017 /* config mec program start addr */ 3018 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 3019 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 3020 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3021 mec_hdr->ucode_start_addr_lo >> 2 | 3022 mec_hdr->ucode_start_addr_hi << 30); 3023 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3024 mec_hdr->ucode_start_addr_hi >> 2); 3025 } 3026 soc21_grbm_select(adev, 0, 0, 0, 0); 3027 3028 /* reset mec pipe */ 3029 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3030 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 3031 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 3032 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 3033 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 3034 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3035 3036 /* clear mec pipe reset */ 3037 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 3038 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 3039 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 3040 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 3041 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 3042 } 3043 3044 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 3045 { 3046 uint32_t cp_status; 3047 uint32_t bootload_status; 3048 int i, r; 3049 uint64_t addr, addr2; 3050 3051 for (i = 0; i < adev->usec_timeout; i++) { 3052 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 3053 3054 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 3055 IP_VERSION(11, 0, 1) || 3056 amdgpu_ip_version(adev, GC_HWIP, 0) == 3057 IP_VERSION(11, 0, 4) || 3058 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 3059 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 3060 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 3061 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) || 3062 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 3063 bootload_status = RREG32_SOC15(GC, 0, 3064 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 3065 else 3066 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 3067 3068 if ((cp_status == 0) && 3069 (REG_GET_FIELD(bootload_status, 3070 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 3071 break; 3072 } 3073 udelay(1); 3074 } 3075 3076 if (i >= adev->usec_timeout) { 3077 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 3078 return -ETIMEDOUT; 3079 } 3080 3081 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3082 if (adev->gfx.rs64_enable) { 3083 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3084 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 3085 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3086 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 3087 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 3088 if (r) 3089 return r; 3090 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3091 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 3092 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3093 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 3094 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 3095 if (r) 3096 return r; 3097 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3098 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 3099 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 3100 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 3101 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 3102 if (r) 3103 return r; 3104 } else { 3105 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3106 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 3107 r = gfx_v11_0_config_me_cache(adev, addr); 3108 if (r) 3109 return r; 3110 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3111 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 3112 r = gfx_v11_0_config_pfp_cache(adev, addr); 3113 if (r) 3114 return r; 3115 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 3116 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 3117 r = gfx_v11_0_config_mec_cache(adev, addr); 3118 if (r) 3119 return r; 3120 } 3121 } 3122 3123 return 0; 3124 } 3125 3126 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3127 { 3128 int i; 3129 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3130 3131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3134 3135 for (i = 0; i < adev->usec_timeout; i++) { 3136 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3137 break; 3138 udelay(1); 3139 } 3140 3141 if (i >= adev->usec_timeout) 3142 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3143 3144 return 0; 3145 } 3146 3147 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3148 { 3149 int r; 3150 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3151 const __le32 *fw_data; 3152 unsigned i, fw_size; 3153 3154 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3155 adev->gfx.pfp_fw->data; 3156 3157 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3158 3159 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3160 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3161 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3162 3163 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3164 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3165 &adev->gfx.pfp.pfp_fw_obj, 3166 &adev->gfx.pfp.pfp_fw_gpu_addr, 3167 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3168 if (r) { 3169 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3170 gfx_v11_0_pfp_fini(adev); 3171 return r; 3172 } 3173 3174 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3175 3176 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3177 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3178 3179 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3180 3181 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3182 3183 for (i = 0; i < pfp_hdr->jt_size; i++) 3184 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3185 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3186 3187 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3193 { 3194 int r; 3195 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3196 const __le32 *fw_ucode, *fw_data; 3197 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3198 uint32_t tmp; 3199 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3200 3201 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3202 adev->gfx.pfp_fw->data; 3203 3204 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3205 3206 /* instruction */ 3207 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3208 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3209 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3210 /* data */ 3211 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3212 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3213 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3214 3215 /* 64kb align */ 3216 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3217 64 * 1024, 3218 AMDGPU_GEM_DOMAIN_VRAM | 3219 AMDGPU_GEM_DOMAIN_GTT, 3220 &adev->gfx.pfp.pfp_fw_obj, 3221 &adev->gfx.pfp.pfp_fw_gpu_addr, 3222 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3223 if (r) { 3224 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3225 gfx_v11_0_pfp_fini(adev); 3226 return r; 3227 } 3228 3229 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3230 64 * 1024, 3231 AMDGPU_GEM_DOMAIN_VRAM | 3232 AMDGPU_GEM_DOMAIN_GTT, 3233 &adev->gfx.pfp.pfp_fw_data_obj, 3234 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3235 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3236 if (r) { 3237 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3238 gfx_v11_0_pfp_fini(adev); 3239 return r; 3240 } 3241 3242 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3243 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3244 3245 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3246 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3247 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3248 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3249 3250 if (amdgpu_emu_mode == 1) 3251 amdgpu_device_flush_hdp(adev, NULL); 3252 3253 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3254 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3255 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3256 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3257 3258 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3259 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3260 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3261 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3262 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3263 3264 /* 3265 * Programming any of the CP_PFP_IC_BASE registers 3266 * forces invalidation of the ME L1 I$. Wait for the 3267 * invalidation complete 3268 */ 3269 for (i = 0; i < usec_timeout; i++) { 3270 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3271 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3272 INVALIDATE_CACHE_COMPLETE)) 3273 break; 3274 udelay(1); 3275 } 3276 3277 if (i >= usec_timeout) { 3278 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3279 return -EINVAL; 3280 } 3281 3282 /* Prime the L1 instruction caches */ 3283 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3284 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3285 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3286 /* Waiting for cache primed*/ 3287 for (i = 0; i < usec_timeout; i++) { 3288 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3289 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3290 ICACHE_PRIMED)) 3291 break; 3292 udelay(1); 3293 } 3294 3295 if (i >= usec_timeout) { 3296 dev_err(adev->dev, "failed to prime instruction cache\n"); 3297 return -EINVAL; 3298 } 3299 3300 mutex_lock(&adev->srbm_mutex); 3301 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3302 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3303 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3304 (pfp_hdr->ucode_start_addr_hi << 30) | 3305 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3306 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3307 pfp_hdr->ucode_start_addr_hi>>2); 3308 3309 /* 3310 * Program CP_ME_CNTL to reset given PIPE to take 3311 * effect of CP_PFP_PRGRM_CNTR_START. 3312 */ 3313 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3314 if (pipe_id == 0) 3315 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3316 PFP_PIPE0_RESET, 1); 3317 else 3318 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3319 PFP_PIPE1_RESET, 1); 3320 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3321 3322 /* Clear pfp pipe0 reset bit. */ 3323 if (pipe_id == 0) 3324 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3325 PFP_PIPE0_RESET, 0); 3326 else 3327 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3328 PFP_PIPE1_RESET, 0); 3329 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3330 3331 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3332 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3333 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3334 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3335 } 3336 soc21_grbm_select(adev, 0, 0, 0, 0); 3337 mutex_unlock(&adev->srbm_mutex); 3338 3339 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3340 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3341 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3342 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3343 3344 /* Invalidate the data caches */ 3345 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3346 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3347 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3348 3349 for (i = 0; i < usec_timeout; i++) { 3350 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3351 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3352 INVALIDATE_DCACHE_COMPLETE)) 3353 break; 3354 udelay(1); 3355 } 3356 3357 if (i >= usec_timeout) { 3358 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3359 return -EINVAL; 3360 } 3361 3362 return 0; 3363 } 3364 3365 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3366 { 3367 int r; 3368 const struct gfx_firmware_header_v1_0 *me_hdr; 3369 const __le32 *fw_data; 3370 unsigned i, fw_size; 3371 3372 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3373 adev->gfx.me_fw->data; 3374 3375 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3376 3377 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3378 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3379 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3380 3381 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3382 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3383 &adev->gfx.me.me_fw_obj, 3384 &adev->gfx.me.me_fw_gpu_addr, 3385 (void **)&adev->gfx.me.me_fw_ptr); 3386 if (r) { 3387 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3388 gfx_v11_0_me_fini(adev); 3389 return r; 3390 } 3391 3392 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3393 3394 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3395 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3396 3397 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3398 3399 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3400 3401 for (i = 0; i < me_hdr->jt_size; i++) 3402 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3403 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3404 3405 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3406 3407 return 0; 3408 } 3409 3410 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3411 { 3412 int r; 3413 const struct gfx_firmware_header_v2_0 *me_hdr; 3414 const __le32 *fw_ucode, *fw_data; 3415 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3416 uint32_t tmp; 3417 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3418 3419 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3420 adev->gfx.me_fw->data; 3421 3422 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3423 3424 /* instruction */ 3425 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3426 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3427 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3428 /* data */ 3429 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3430 le32_to_cpu(me_hdr->data_offset_bytes)); 3431 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3432 3433 /* 64kb align*/ 3434 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3435 64 * 1024, 3436 AMDGPU_GEM_DOMAIN_VRAM | 3437 AMDGPU_GEM_DOMAIN_GTT, 3438 &adev->gfx.me.me_fw_obj, 3439 &adev->gfx.me.me_fw_gpu_addr, 3440 (void **)&adev->gfx.me.me_fw_ptr); 3441 if (r) { 3442 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3443 gfx_v11_0_me_fini(adev); 3444 return r; 3445 } 3446 3447 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3448 64 * 1024, 3449 AMDGPU_GEM_DOMAIN_VRAM | 3450 AMDGPU_GEM_DOMAIN_GTT, 3451 &adev->gfx.me.me_fw_data_obj, 3452 &adev->gfx.me.me_fw_data_gpu_addr, 3453 (void **)&adev->gfx.me.me_fw_data_ptr); 3454 if (r) { 3455 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3456 gfx_v11_0_pfp_fini(adev); 3457 return r; 3458 } 3459 3460 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3461 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3462 3463 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3464 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3465 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3466 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3467 3468 if (amdgpu_emu_mode == 1) 3469 amdgpu_device_flush_hdp(adev, NULL); 3470 3471 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3472 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3473 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3474 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3475 3476 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3477 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3478 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3479 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3480 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3481 3482 /* 3483 * Programming any of the CP_ME_IC_BASE registers 3484 * forces invalidation of the ME L1 I$. Wait for the 3485 * invalidation complete 3486 */ 3487 for (i = 0; i < usec_timeout; i++) { 3488 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3489 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3490 INVALIDATE_CACHE_COMPLETE)) 3491 break; 3492 udelay(1); 3493 } 3494 3495 if (i >= usec_timeout) { 3496 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3497 return -EINVAL; 3498 } 3499 3500 /* Prime the instruction caches */ 3501 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3502 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3503 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3504 3505 /* Waiting for instruction cache primed*/ 3506 for (i = 0; i < usec_timeout; i++) { 3507 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3508 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3509 ICACHE_PRIMED)) 3510 break; 3511 udelay(1); 3512 } 3513 3514 if (i >= usec_timeout) { 3515 dev_err(adev->dev, "failed to prime instruction cache\n"); 3516 return -EINVAL; 3517 } 3518 3519 mutex_lock(&adev->srbm_mutex); 3520 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3521 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3522 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3523 (me_hdr->ucode_start_addr_hi << 30) | 3524 (me_hdr->ucode_start_addr_lo >> 2) ); 3525 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3526 me_hdr->ucode_start_addr_hi>>2); 3527 3528 /* 3529 * Program CP_ME_CNTL to reset given PIPE to take 3530 * effect of CP_PFP_PRGRM_CNTR_START. 3531 */ 3532 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3533 if (pipe_id == 0) 3534 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3535 ME_PIPE0_RESET, 1); 3536 else 3537 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3538 ME_PIPE1_RESET, 1); 3539 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3540 3541 /* Clear pfp pipe0 reset bit. */ 3542 if (pipe_id == 0) 3543 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3544 ME_PIPE0_RESET, 0); 3545 else 3546 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3547 ME_PIPE1_RESET, 0); 3548 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3549 3550 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3551 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3552 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3553 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3554 } 3555 soc21_grbm_select(adev, 0, 0, 0, 0); 3556 mutex_unlock(&adev->srbm_mutex); 3557 3558 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3559 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3560 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3561 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3562 3563 /* Invalidate the data caches */ 3564 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3565 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3566 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3567 3568 for (i = 0; i < usec_timeout; i++) { 3569 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3570 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3571 INVALIDATE_DCACHE_COMPLETE)) 3572 break; 3573 udelay(1); 3574 } 3575 3576 if (i >= usec_timeout) { 3577 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3578 return -EINVAL; 3579 } 3580 3581 return 0; 3582 } 3583 3584 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3585 { 3586 int r; 3587 3588 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3589 return -EINVAL; 3590 3591 gfx_v11_0_cp_gfx_enable(adev, false); 3592 3593 if (adev->gfx.rs64_enable) 3594 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3595 else 3596 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3597 if (r) { 3598 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3599 return r; 3600 } 3601 3602 if (adev->gfx.rs64_enable) 3603 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3604 else 3605 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3606 if (r) { 3607 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3608 return r; 3609 } 3610 3611 return 0; 3612 } 3613 3614 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3615 { 3616 struct amdgpu_ring *ring; 3617 const struct cs_section_def *sect = NULL; 3618 const struct cs_extent_def *ext = NULL; 3619 int r, i; 3620 int ctx_reg_offset; 3621 3622 /* init the CP */ 3623 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3624 adev->gfx.config.max_hw_contexts - 1); 3625 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3626 3627 if (!amdgpu_async_gfx_ring) 3628 gfx_v11_0_cp_gfx_enable(adev, true); 3629 3630 ring = &adev->gfx.gfx_ring[0]; 3631 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3632 if (r) { 3633 drm_err(&adev->ddev, "cp failed to lock ring (%d).\n", r); 3634 return r; 3635 } 3636 3637 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3638 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3639 3640 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3641 amdgpu_ring_write(ring, 0x80000000); 3642 amdgpu_ring_write(ring, 0x80000000); 3643 3644 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3645 for (ext = sect->section; ext->extent != NULL; ++ext) { 3646 if (sect->id == SECT_CONTEXT) { 3647 amdgpu_ring_write(ring, 3648 PACKET3(PACKET3_SET_CONTEXT_REG, 3649 ext->reg_count)); 3650 amdgpu_ring_write(ring, ext->reg_index - 3651 PACKET3_SET_CONTEXT_REG_START); 3652 for (i = 0; i < ext->reg_count; i++) 3653 amdgpu_ring_write(ring, ext->extent[i]); 3654 } 3655 } 3656 } 3657 3658 ctx_reg_offset = 3659 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3660 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3661 amdgpu_ring_write(ring, ctx_reg_offset); 3662 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3663 3664 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3665 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3666 3667 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3668 amdgpu_ring_write(ring, 0); 3669 3670 amdgpu_ring_commit(ring); 3671 3672 /* submit cs packet to copy state 0 to next available state */ 3673 if (adev->gfx.num_gfx_rings > 1) { 3674 /* maximum supported gfx ring is 2 */ 3675 ring = &adev->gfx.gfx_ring[1]; 3676 r = amdgpu_ring_alloc(ring, 2); 3677 if (r) { 3678 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 3679 return r; 3680 } 3681 3682 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3683 amdgpu_ring_write(ring, 0); 3684 3685 amdgpu_ring_commit(ring); 3686 } 3687 return 0; 3688 } 3689 3690 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3691 CP_PIPE_ID pipe) 3692 { 3693 u32 tmp; 3694 3695 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3696 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3697 3698 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3699 } 3700 3701 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3702 struct amdgpu_ring *ring) 3703 { 3704 u32 tmp; 3705 3706 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3707 if (ring->use_doorbell) { 3708 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3709 DOORBELL_OFFSET, ring->doorbell_index); 3710 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3711 DOORBELL_EN, 1); 3712 } else { 3713 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3714 DOORBELL_EN, 0); 3715 } 3716 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3717 3718 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3719 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3720 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3721 3722 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3723 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3724 } 3725 3726 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3727 { 3728 struct amdgpu_ring *ring; 3729 u32 tmp; 3730 u32 rb_bufsz; 3731 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3732 3733 /* Set the write pointer delay */ 3734 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3735 3736 /* set the RB to use vmid 0 */ 3737 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3738 3739 /* Init gfx ring 0 for pipe 0 */ 3740 mutex_lock(&adev->srbm_mutex); 3741 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3742 3743 /* Set ring buffer size */ 3744 ring = &adev->gfx.gfx_ring[0]; 3745 rb_bufsz = order_base_2(ring->ring_size / 8); 3746 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3747 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3748 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3749 3750 /* Initialize the ring buffer's write pointers */ 3751 ring->wptr = 0; 3752 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3753 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3754 3755 /* set the wb address whether it's enabled or not */ 3756 rptr_addr = ring->rptr_gpu_addr; 3757 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3758 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3759 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3760 3761 wptr_gpu_addr = ring->wptr_gpu_addr; 3762 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3763 lower_32_bits(wptr_gpu_addr)); 3764 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3765 upper_32_bits(wptr_gpu_addr)); 3766 3767 mdelay(1); 3768 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3769 3770 rb_addr = ring->gpu_addr >> 8; 3771 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3772 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3773 3774 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3775 3776 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3777 mutex_unlock(&adev->srbm_mutex); 3778 3779 /* Init gfx ring 1 for pipe 1 */ 3780 if (adev->gfx.num_gfx_rings > 1) { 3781 mutex_lock(&adev->srbm_mutex); 3782 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3783 /* maximum supported gfx ring is 2 */ 3784 ring = &adev->gfx.gfx_ring[1]; 3785 rb_bufsz = order_base_2(ring->ring_size / 8); 3786 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3787 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3788 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3789 /* Initialize the ring buffer's write pointers */ 3790 ring->wptr = 0; 3791 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3792 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3793 /* Set the wb address whether it's enabled or not */ 3794 rptr_addr = ring->rptr_gpu_addr; 3795 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3796 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3797 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3798 wptr_gpu_addr = ring->wptr_gpu_addr; 3799 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3800 lower_32_bits(wptr_gpu_addr)); 3801 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3802 upper_32_bits(wptr_gpu_addr)); 3803 3804 mdelay(1); 3805 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3806 3807 rb_addr = ring->gpu_addr >> 8; 3808 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3809 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3810 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3811 3812 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3813 mutex_unlock(&adev->srbm_mutex); 3814 } 3815 /* Switch to pipe 0 */ 3816 mutex_lock(&adev->srbm_mutex); 3817 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3818 mutex_unlock(&adev->srbm_mutex); 3819 3820 /* start the ring */ 3821 gfx_v11_0_cp_gfx_start(adev); 3822 3823 return 0; 3824 } 3825 3826 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3827 { 3828 u32 data; 3829 3830 if (adev->gfx.rs64_enable) { 3831 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3832 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3833 enable ? 0 : 1); 3834 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3835 enable ? 0 : 1); 3836 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3837 enable ? 0 : 1); 3838 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3839 enable ? 0 : 1); 3840 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3841 enable ? 0 : 1); 3842 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3843 enable ? 1 : 0); 3844 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3845 enable ? 1 : 0); 3846 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3847 enable ? 1 : 0); 3848 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3849 enable ? 1 : 0); 3850 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3851 enable ? 0 : 1); 3852 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3853 } else { 3854 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3855 3856 if (enable) { 3857 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3858 if (!adev->enable_mes_kiq) 3859 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3860 MEC_ME2_HALT, 0); 3861 } else { 3862 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3863 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3864 } 3865 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3866 } 3867 3868 udelay(50); 3869 } 3870 3871 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3872 { 3873 const struct gfx_firmware_header_v1_0 *mec_hdr; 3874 const __le32 *fw_data; 3875 unsigned i, fw_size; 3876 u32 *fw = NULL; 3877 int r; 3878 3879 if (!adev->gfx.mec_fw) 3880 return -EINVAL; 3881 3882 gfx_v11_0_cp_compute_enable(adev, false); 3883 3884 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3885 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3886 3887 fw_data = (const __le32 *) 3888 (adev->gfx.mec_fw->data + 3889 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3890 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3891 3892 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3893 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3894 &adev->gfx.mec.mec_fw_obj, 3895 &adev->gfx.mec.mec_fw_gpu_addr, 3896 (void **)&fw); 3897 if (r) { 3898 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3899 gfx_v11_0_mec_fini(adev); 3900 return r; 3901 } 3902 3903 memcpy(fw, fw_data, fw_size); 3904 3905 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3906 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3907 3908 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3909 3910 /* MEC1 */ 3911 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3912 3913 for (i = 0; i < mec_hdr->jt_size; i++) 3914 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3915 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3916 3917 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3918 3919 return 0; 3920 } 3921 3922 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3923 { 3924 const struct gfx_firmware_header_v2_0 *mec_hdr; 3925 const __le32 *fw_ucode, *fw_data; 3926 u32 tmp, fw_ucode_size, fw_data_size; 3927 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3928 u32 *fw_ucode_ptr, *fw_data_ptr; 3929 int r; 3930 3931 if (!adev->gfx.mec_fw) 3932 return -EINVAL; 3933 3934 gfx_v11_0_cp_compute_enable(adev, false); 3935 3936 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3937 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3938 3939 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3940 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3941 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3942 3943 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3944 le32_to_cpu(mec_hdr->data_offset_bytes)); 3945 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3946 3947 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3948 64 * 1024, 3949 AMDGPU_GEM_DOMAIN_VRAM | 3950 AMDGPU_GEM_DOMAIN_GTT, 3951 &adev->gfx.mec.mec_fw_obj, 3952 &adev->gfx.mec.mec_fw_gpu_addr, 3953 (void **)&fw_ucode_ptr); 3954 if (r) { 3955 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3956 gfx_v11_0_mec_fini(adev); 3957 return r; 3958 } 3959 3960 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3961 64 * 1024, 3962 AMDGPU_GEM_DOMAIN_VRAM | 3963 AMDGPU_GEM_DOMAIN_GTT, 3964 &adev->gfx.mec.mec_fw_data_obj, 3965 &adev->gfx.mec.mec_fw_data_gpu_addr, 3966 (void **)&fw_data_ptr); 3967 if (r) { 3968 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3969 gfx_v11_0_mec_fini(adev); 3970 return r; 3971 } 3972 3973 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3974 memcpy(fw_data_ptr, fw_data, fw_data_size); 3975 3976 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3977 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3978 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3979 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3980 3981 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3982 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3983 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3984 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3985 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3986 3987 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3988 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3989 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3990 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3991 3992 mutex_lock(&adev->srbm_mutex); 3993 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3994 soc21_grbm_select(adev, 1, i, 0, 0); 3995 3996 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3997 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3998 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3999 4000 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 4001 mec_hdr->ucode_start_addr_lo >> 2 | 4002 mec_hdr->ucode_start_addr_hi << 30); 4003 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 4004 mec_hdr->ucode_start_addr_hi >> 2); 4005 4006 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 4007 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 4008 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 4009 } 4010 mutex_unlock(&adev->srbm_mutex); 4011 soc21_grbm_select(adev, 0, 0, 0, 0); 4012 4013 /* Trigger an invalidation of the L1 instruction caches */ 4014 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 4015 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 4016 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 4017 4018 /* Wait for invalidation complete */ 4019 for (i = 0; i < usec_timeout; i++) { 4020 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 4021 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 4022 INVALIDATE_DCACHE_COMPLETE)) 4023 break; 4024 udelay(1); 4025 } 4026 4027 if (i >= usec_timeout) { 4028 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4029 return -EINVAL; 4030 } 4031 4032 /* Trigger an invalidation of the L1 instruction caches */ 4033 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4034 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 4035 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 4036 4037 /* Wait for invalidation complete */ 4038 for (i = 0; i < usec_timeout; i++) { 4039 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 4040 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 4041 INVALIDATE_CACHE_COMPLETE)) 4042 break; 4043 udelay(1); 4044 } 4045 4046 if (i >= usec_timeout) { 4047 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 4048 return -EINVAL; 4049 } 4050 4051 return 0; 4052 } 4053 4054 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 4055 { 4056 uint32_t tmp; 4057 struct amdgpu_device *adev = ring->adev; 4058 4059 /* tell RLC which is KIQ queue */ 4060 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4061 tmp &= 0xffffff00; 4062 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4063 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 4064 } 4065 4066 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 4067 { 4068 /* set graphics engine doorbell range */ 4069 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 4070 (adev->doorbell_index.gfx_ring0 * 2) << 2); 4071 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 4072 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 4073 4074 /* set compute engine doorbell range */ 4075 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4076 (adev->doorbell_index.kiq * 2) << 2); 4077 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4078 (adev->doorbell_index.userqueue_end * 2) << 2); 4079 } 4080 4081 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 4082 struct v11_gfx_mqd *mqd, 4083 struct amdgpu_mqd_prop *prop) 4084 { 4085 bool priority = 0; 4086 u32 tmp; 4087 4088 /* set up default queue priority level 4089 * 0x0 = low priority, 0x1 = high priority 4090 */ 4091 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 4092 priority = 1; 4093 4094 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 4095 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 4096 mqd->cp_gfx_hqd_queue_priority = tmp; 4097 } 4098 4099 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 4100 struct amdgpu_mqd_prop *prop) 4101 { 4102 struct v11_gfx_mqd *mqd = m; 4103 uint64_t hqd_gpu_addr, wb_gpu_addr; 4104 uint32_t tmp; 4105 uint32_t rb_bufsz; 4106 4107 /* set up gfx hqd wptr */ 4108 mqd->cp_gfx_hqd_wptr = 0; 4109 mqd->cp_gfx_hqd_wptr_hi = 0; 4110 4111 /* set the pointer to the MQD */ 4112 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 4113 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4114 4115 /* set up mqd control */ 4116 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 4117 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 4118 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 4119 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 4120 mqd->cp_gfx_mqd_control = tmp; 4121 4122 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 4123 tmp = regCP_GFX_HQD_VMID_DEFAULT; 4124 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4125 mqd->cp_gfx_hqd_vmid = 0; 4126 4127 /* set up gfx queue priority */ 4128 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4129 4130 /* set up time quantum */ 4131 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 4132 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4133 mqd->cp_gfx_hqd_quantum = tmp; 4134 4135 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4136 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4137 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4138 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4139 4140 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4141 wb_gpu_addr = prop->rptr_gpu_addr; 4142 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4143 mqd->cp_gfx_hqd_rptr_addr_hi = 4144 upper_32_bits(wb_gpu_addr) & 0xffff; 4145 4146 /* set up rb_wptr_poll addr */ 4147 wb_gpu_addr = prop->wptr_gpu_addr; 4148 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4149 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4150 4151 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4152 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4153 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 4154 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4155 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4156 #ifdef __BIG_ENDIAN 4157 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4158 #endif 4159 if (prop->tmz_queue) 4160 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 4161 if (!prop->kernel_queue) 4162 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 4163 mqd->cp_gfx_hqd_cntl = tmp; 4164 4165 /* set up cp_doorbell_control */ 4166 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 4167 if (prop->use_doorbell) { 4168 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4169 DOORBELL_OFFSET, prop->doorbell_index); 4170 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4171 DOORBELL_EN, 1); 4172 } else 4173 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4174 DOORBELL_EN, 0); 4175 mqd->cp_rb_doorbell_control = tmp; 4176 4177 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4178 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 4179 4180 /* active the queue */ 4181 mqd->cp_gfx_hqd_active = 1; 4182 4183 /* set gfx UQ items */ 4184 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 4185 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 4186 mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr); 4187 mqd->gds_bkup_base_hi = upper_32_bits(prop->gds_bkup_addr); 4188 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 4189 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 4190 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4191 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4192 4193 return 0; 4194 } 4195 4196 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 4197 { 4198 struct amdgpu_device *adev = ring->adev; 4199 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4200 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4201 4202 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4203 memset((void *)mqd, 0, sizeof(*mqd)); 4204 mutex_lock(&adev->srbm_mutex); 4205 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4206 amdgpu_ring_init_mqd(ring); 4207 soc21_grbm_select(adev, 0, 0, 0, 0); 4208 mutex_unlock(&adev->srbm_mutex); 4209 if (adev->gfx.me.mqd_backup[mqd_idx]) 4210 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4211 } else { 4212 /* restore mqd with the backup copy */ 4213 if (adev->gfx.me.mqd_backup[mqd_idx]) 4214 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4215 /* reset the ring */ 4216 ring->wptr = 0; 4217 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4218 amdgpu_ring_clear_ring(ring); 4219 } 4220 4221 return 0; 4222 } 4223 4224 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4225 { 4226 int r, i; 4227 4228 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4229 r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 4230 if (r) 4231 return r; 4232 } 4233 4234 r = amdgpu_gfx_enable_kgq(adev, 0); 4235 if (r) 4236 return r; 4237 4238 return gfx_v11_0_cp_gfx_start(adev); 4239 } 4240 4241 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4242 struct amdgpu_mqd_prop *prop) 4243 { 4244 struct v11_compute_mqd *mqd = m; 4245 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4246 uint32_t tmp; 4247 4248 mqd->header = 0xC0310800; 4249 mqd->compute_pipelinestat_enable = 0x00000001; 4250 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4251 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4252 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4253 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4254 mqd->compute_misc_reserved = 0x00000007; 4255 4256 eop_base_addr = prop->eop_gpu_addr >> 8; 4257 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4258 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4259 4260 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4261 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 4262 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4263 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4264 4265 mqd->cp_hqd_eop_control = tmp; 4266 4267 /* enable doorbell? */ 4268 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4269 4270 if (prop->use_doorbell) { 4271 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4272 DOORBELL_OFFSET, prop->doorbell_index); 4273 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4274 DOORBELL_EN, 1); 4275 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4276 DOORBELL_SOURCE, 0); 4277 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4278 DOORBELL_HIT, 0); 4279 } else { 4280 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4281 DOORBELL_EN, 0); 4282 } 4283 4284 mqd->cp_hqd_pq_doorbell_control = tmp; 4285 4286 /* disable the queue if it's active */ 4287 mqd->cp_hqd_dequeue_request = 0; 4288 mqd->cp_hqd_pq_rptr = 0; 4289 mqd->cp_hqd_pq_wptr_lo = 0; 4290 mqd->cp_hqd_pq_wptr_hi = 0; 4291 4292 /* set the pointer to the MQD */ 4293 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4294 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4295 4296 /* set MQD vmid to 0 */ 4297 tmp = regCP_MQD_CONTROL_DEFAULT; 4298 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4299 mqd->cp_mqd_control = tmp; 4300 4301 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4302 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4303 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4304 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4305 4306 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4307 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 4308 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4309 (order_base_2(prop->queue_size / 4) - 1)); 4310 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4311 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4312 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4313 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4314 prop->allow_tunneling); 4315 if (prop->kernel_queue) { 4316 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4318 } 4319 if (prop->tmz_queue) 4320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 4321 mqd->cp_hqd_pq_control = tmp; 4322 4323 /* set the wb address whether it's enabled or not */ 4324 wb_gpu_addr = prop->rptr_gpu_addr; 4325 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4326 mqd->cp_hqd_pq_rptr_report_addr_hi = 4327 upper_32_bits(wb_gpu_addr) & 0xffff; 4328 4329 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4330 wb_gpu_addr = prop->wptr_gpu_addr; 4331 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4332 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4333 4334 tmp = 0; 4335 /* enable the doorbell if requested */ 4336 if (prop->use_doorbell) { 4337 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 4338 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4339 DOORBELL_OFFSET, prop->doorbell_index); 4340 4341 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4342 DOORBELL_EN, 1); 4343 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4344 DOORBELL_SOURCE, 0); 4345 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4346 DOORBELL_HIT, 0); 4347 } 4348 4349 mqd->cp_hqd_pq_doorbell_control = tmp; 4350 4351 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4352 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 4353 4354 /* set the vmid for the queue */ 4355 mqd->cp_hqd_vmid = 0; 4356 4357 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 4358 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4359 mqd->cp_hqd_persistent_state = tmp; 4360 4361 /* set MIN_IB_AVAIL_SIZE */ 4362 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 4363 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4364 mqd->cp_hqd_ib_control = tmp; 4365 4366 /* set static priority for a compute queue/ring */ 4367 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4368 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4369 4370 mqd->cp_hqd_active = prop->hqd_active; 4371 4372 /* set UQ fenceaddress */ 4373 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4374 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4375 4376 return 0; 4377 } 4378 4379 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4380 { 4381 struct amdgpu_device *adev = ring->adev; 4382 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4383 int j; 4384 4385 /* inactivate the queue */ 4386 if (amdgpu_sriov_vf(adev)) 4387 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4388 4389 /* disable wptr polling */ 4390 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4391 4392 /* write the EOP addr */ 4393 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4394 mqd->cp_hqd_eop_base_addr_lo); 4395 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4396 mqd->cp_hqd_eop_base_addr_hi); 4397 4398 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4399 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4400 mqd->cp_hqd_eop_control); 4401 4402 /* enable doorbell? */ 4403 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4404 mqd->cp_hqd_pq_doorbell_control); 4405 4406 /* disable the queue if it's active */ 4407 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4408 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4409 for (j = 0; j < adev->usec_timeout; j++) { 4410 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4411 break; 4412 udelay(1); 4413 } 4414 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4415 mqd->cp_hqd_dequeue_request); 4416 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4417 mqd->cp_hqd_pq_rptr); 4418 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4419 mqd->cp_hqd_pq_wptr_lo); 4420 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4421 mqd->cp_hqd_pq_wptr_hi); 4422 } 4423 4424 /* set the pointer to the MQD */ 4425 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4426 mqd->cp_mqd_base_addr_lo); 4427 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4428 mqd->cp_mqd_base_addr_hi); 4429 4430 /* set MQD vmid to 0 */ 4431 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4432 mqd->cp_mqd_control); 4433 4434 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4435 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4436 mqd->cp_hqd_pq_base_lo); 4437 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4438 mqd->cp_hqd_pq_base_hi); 4439 4440 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4441 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4442 mqd->cp_hqd_pq_control); 4443 4444 /* set the wb address whether it's enabled or not */ 4445 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4446 mqd->cp_hqd_pq_rptr_report_addr_lo); 4447 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4448 mqd->cp_hqd_pq_rptr_report_addr_hi); 4449 4450 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4451 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4452 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4453 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4454 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4455 4456 /* enable the doorbell if requested */ 4457 if (ring->use_doorbell) { 4458 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4459 (adev->doorbell_index.kiq * 2) << 2); 4460 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4461 (adev->doorbell_index.userqueue_end * 2) << 2); 4462 } 4463 4464 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4465 mqd->cp_hqd_pq_doorbell_control); 4466 4467 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4468 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4469 mqd->cp_hqd_pq_wptr_lo); 4470 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4471 mqd->cp_hqd_pq_wptr_hi); 4472 4473 /* set the vmid for the queue */ 4474 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4475 4476 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4477 mqd->cp_hqd_persistent_state); 4478 4479 /* activate the queue */ 4480 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4481 mqd->cp_hqd_active); 4482 4483 if (ring->use_doorbell) 4484 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4485 4486 return 0; 4487 } 4488 4489 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4490 { 4491 struct amdgpu_device *adev = ring->adev; 4492 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4493 4494 gfx_v11_0_kiq_setting(ring); 4495 4496 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4497 /* reset MQD to a clean status */ 4498 if (adev->gfx.kiq[0].mqd_backup) 4499 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4500 4501 /* reset ring buffer */ 4502 ring->wptr = 0; 4503 amdgpu_ring_clear_ring(ring); 4504 4505 mutex_lock(&adev->srbm_mutex); 4506 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4507 gfx_v11_0_kiq_init_register(ring); 4508 soc21_grbm_select(adev, 0, 0, 0, 0); 4509 mutex_unlock(&adev->srbm_mutex); 4510 } else { 4511 memset((void *)mqd, 0, sizeof(*mqd)); 4512 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4513 amdgpu_ring_clear_ring(ring); 4514 mutex_lock(&adev->srbm_mutex); 4515 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4516 amdgpu_ring_init_mqd(ring); 4517 gfx_v11_0_kiq_init_register(ring); 4518 soc21_grbm_select(adev, 0, 0, 0, 0); 4519 mutex_unlock(&adev->srbm_mutex); 4520 4521 if (adev->gfx.kiq[0].mqd_backup) 4522 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4523 } 4524 4525 return 0; 4526 } 4527 4528 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 4529 { 4530 struct amdgpu_device *adev = ring->adev; 4531 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4532 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4533 4534 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4535 memset((void *)mqd, 0, sizeof(*mqd)); 4536 mutex_lock(&adev->srbm_mutex); 4537 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4538 amdgpu_ring_init_mqd(ring); 4539 soc21_grbm_select(adev, 0, 0, 0, 0); 4540 mutex_unlock(&adev->srbm_mutex); 4541 4542 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4543 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4544 } else { 4545 /* restore MQD to a clean status */ 4546 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4547 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4548 /* reset ring buffer */ 4549 ring->wptr = 0; 4550 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4551 amdgpu_ring_clear_ring(ring); 4552 } 4553 4554 return 0; 4555 } 4556 4557 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4558 { 4559 gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 4560 return 0; 4561 } 4562 4563 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4564 { 4565 int i, r; 4566 4567 if (!amdgpu_async_gfx_ring) 4568 gfx_v11_0_cp_compute_enable(adev, true); 4569 4570 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4571 r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 4572 if (r) 4573 return r; 4574 } 4575 4576 return amdgpu_gfx_enable_kcq(adev, 0); 4577 } 4578 4579 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4580 { 4581 int r, i; 4582 struct amdgpu_ring *ring; 4583 4584 if (!(adev->flags & AMD_IS_APU)) 4585 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4586 4587 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4588 /* legacy firmware loading */ 4589 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4590 if (r) 4591 return r; 4592 4593 if (adev->gfx.rs64_enable) 4594 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4595 else 4596 r = gfx_v11_0_cp_compute_load_microcode(adev); 4597 if (r) 4598 return r; 4599 } 4600 4601 gfx_v11_0_cp_set_doorbell_range(adev); 4602 4603 if (amdgpu_async_gfx_ring) { 4604 gfx_v11_0_cp_compute_enable(adev, true); 4605 gfx_v11_0_cp_gfx_enable(adev, true); 4606 } 4607 4608 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4609 r = amdgpu_mes_kiq_hw_init(adev, 0); 4610 else 4611 r = gfx_v11_0_kiq_resume(adev); 4612 if (r) 4613 return r; 4614 4615 r = gfx_v11_0_kcq_resume(adev); 4616 if (r) 4617 return r; 4618 4619 if (!amdgpu_async_gfx_ring) { 4620 r = gfx_v11_0_cp_gfx_resume(adev); 4621 if (r) 4622 return r; 4623 } else { 4624 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4625 if (r) 4626 return r; 4627 } 4628 4629 if (adev->gfx.disable_kq) { 4630 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4631 ring = &adev->gfx.gfx_ring[i]; 4632 /* we don't want to set ring->ready */ 4633 r = amdgpu_ring_test_ring(ring); 4634 if (r) 4635 return r; 4636 } 4637 if (amdgpu_async_gfx_ring) 4638 amdgpu_gfx_disable_kgq(adev, 0); 4639 } else { 4640 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4641 ring = &adev->gfx.gfx_ring[i]; 4642 r = amdgpu_ring_test_helper(ring); 4643 if (r) 4644 return r; 4645 } 4646 } 4647 4648 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4649 ring = &adev->gfx.compute_ring[i]; 4650 r = amdgpu_ring_test_helper(ring); 4651 if (r) 4652 return r; 4653 } 4654 4655 return 0; 4656 } 4657 4658 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4659 { 4660 gfx_v11_0_cp_gfx_enable(adev, enable); 4661 gfx_v11_0_cp_compute_enable(adev, enable); 4662 } 4663 4664 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4665 { 4666 int r; 4667 bool value; 4668 4669 r = adev->gfxhub.funcs->gart_enable(adev); 4670 if (r) 4671 return r; 4672 4673 amdgpu_device_flush_hdp(adev, NULL); 4674 4675 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 4676 4677 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4678 /* TODO investigate why this and the hdp flush above is needed, 4679 * are we missing a flush somewhere else? */ 4680 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4681 4682 return 0; 4683 } 4684 4685 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4686 { 4687 u32 tmp; 4688 4689 /* select RS64 */ 4690 if (adev->gfx.rs64_enable) { 4691 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4692 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4693 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4694 4695 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4696 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4697 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4698 } 4699 4700 if (amdgpu_emu_mode == 1) 4701 msleep(100); 4702 } 4703 4704 static int get_gb_addr_config(struct amdgpu_device * adev) 4705 { 4706 u32 gb_addr_config; 4707 4708 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4709 if (gb_addr_config == 0) 4710 return -EINVAL; 4711 4712 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4713 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4714 4715 adev->gfx.config.gb_addr_config = gb_addr_config; 4716 4717 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4718 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4719 GB_ADDR_CONFIG, NUM_PIPES); 4720 4721 adev->gfx.config.max_tile_pipes = 4722 adev->gfx.config.gb_addr_config_fields.num_pipes; 4723 4724 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4725 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4726 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4727 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4728 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4729 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4730 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4731 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4732 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4733 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4734 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4735 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4736 4737 return 0; 4738 } 4739 4740 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4741 { 4742 uint32_t data; 4743 4744 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4745 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4746 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4747 4748 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4749 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4750 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4751 } 4752 4753 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4754 { 4755 int r; 4756 struct amdgpu_device *adev = ip_block->adev; 4757 4758 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4759 adev->gfx.cleaner_shader_ptr); 4760 4761 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4762 if (adev->gfx.imu.funcs) { 4763 /* RLC autoload sequence 1: Program rlc ram */ 4764 if (adev->gfx.imu.funcs->program_rlc_ram) 4765 adev->gfx.imu.funcs->program_rlc_ram(adev); 4766 /* rlc autoload firmware */ 4767 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4768 if (r) 4769 return r; 4770 } 4771 } else { 4772 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4773 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4774 if (adev->gfx.imu.funcs->load_microcode) 4775 adev->gfx.imu.funcs->load_microcode(adev); 4776 if (adev->gfx.imu.funcs->setup_imu) 4777 adev->gfx.imu.funcs->setup_imu(adev); 4778 if (adev->gfx.imu.funcs->start_imu) 4779 adev->gfx.imu.funcs->start_imu(adev); 4780 } 4781 4782 /* disable gpa mode in backdoor loading */ 4783 gfx_v11_0_disable_gpa_mode(adev); 4784 } 4785 } 4786 4787 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4788 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4789 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4790 if (r) { 4791 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4792 return r; 4793 } 4794 } 4795 4796 adev->gfx.is_poweron = true; 4797 4798 if(get_gb_addr_config(adev)) 4799 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 4800 4801 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4802 adev->gfx.rs64_enable) 4803 gfx_v11_0_config_gfx_rs64(adev); 4804 4805 r = gfx_v11_0_gfxhub_enable(adev); 4806 if (r) 4807 return r; 4808 4809 if (!amdgpu_emu_mode) 4810 gfx_v11_0_init_golden_registers(adev); 4811 4812 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4813 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4814 /** 4815 * For gfx 11, rlc firmware loading relies on smu firmware is 4816 * loaded firstly, so in direct type, it has to load smc ucode 4817 * here before rlc. 4818 */ 4819 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4820 if (r) 4821 return r; 4822 } 4823 4824 gfx_v11_0_constants_init(adev); 4825 4826 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4827 gfx_v11_0_select_cp_fw_arch(adev); 4828 4829 if (adev->nbio.funcs->gc_doorbell_init) 4830 adev->nbio.funcs->gc_doorbell_init(adev); 4831 4832 r = gfx_v11_0_rlc_resume(adev); 4833 if (r) 4834 return r; 4835 4836 /* 4837 * init golden registers and rlc resume may override some registers, 4838 * reconfig them here 4839 */ 4840 gfx_v11_0_tcp_harvest(adev); 4841 4842 r = gfx_v11_0_cp_resume(adev); 4843 if (r) 4844 return r; 4845 4846 /* get IMU version from HW if it's not set */ 4847 if (!adev->gfx.imu_fw_version) 4848 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4849 4850 return r; 4851 } 4852 4853 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 4854 bool enable) 4855 { 4856 unsigned int irq_type; 4857 int m, p, r; 4858 4859 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 4860 for (m = 0; m < adev->gfx.me.num_me; m++) { 4861 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 4862 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 4863 if (enable) 4864 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4865 irq_type); 4866 else 4867 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4868 irq_type); 4869 if (r) 4870 return r; 4871 } 4872 } 4873 } 4874 4875 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 4876 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 4877 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 4878 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4879 + (m * adev->gfx.mec.num_pipe_per_mec) 4880 + p; 4881 if (enable) 4882 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 4883 irq_type); 4884 else 4885 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 4886 irq_type); 4887 if (r) 4888 return r; 4889 } 4890 } 4891 } 4892 4893 return 0; 4894 } 4895 4896 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 4897 { 4898 struct amdgpu_device *adev = ip_block->adev; 4899 4900 cancel_delayed_work_sync(&adev->gfx.idle_work); 4901 4902 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4903 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4904 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4905 gfx_v11_0_set_userq_eop_interrupts(adev, false); 4906 4907 if (!adev->no_hw_access) { 4908 if (amdgpu_async_gfx_ring && 4909 !adev->gfx.disable_kq) { 4910 if (amdgpu_gfx_disable_kgq(adev, 0)) 4911 DRM_ERROR("KGQ disable failed\n"); 4912 } 4913 4914 if (amdgpu_gfx_disable_kcq(adev, 0)) 4915 DRM_ERROR("KCQ disable failed\n"); 4916 4917 amdgpu_mes_kiq_hw_fini(adev, 0); 4918 } 4919 4920 if (amdgpu_sriov_vf(adev)) 4921 /* Remove the steps disabling CPG and clearing KIQ position, 4922 * so that CP could perform IDLE-SAVE during switch. Those 4923 * steps are necessary to avoid a DMAR error in gfx9 but it is 4924 * not reproduced on gfx11. 4925 */ 4926 return 0; 4927 4928 gfx_v11_0_cp_enable(adev, false); 4929 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4930 4931 adev->gfxhub.funcs->gart_disable(adev); 4932 4933 adev->gfx.is_poweron = false; 4934 4935 return 0; 4936 } 4937 4938 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 4939 { 4940 return gfx_v11_0_hw_fini(ip_block); 4941 } 4942 4943 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 4944 { 4945 return gfx_v11_0_hw_init(ip_block); 4946 } 4947 4948 static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 4949 { 4950 struct amdgpu_device *adev = ip_block->adev; 4951 4952 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4953 GRBM_STATUS, GUI_ACTIVE)) 4954 return false; 4955 else 4956 return true; 4957 } 4958 4959 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4960 { 4961 unsigned i; 4962 u32 tmp; 4963 struct amdgpu_device *adev = ip_block->adev; 4964 4965 for (i = 0; i < adev->usec_timeout; i++) { 4966 /* read MC_STATUS */ 4967 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4968 GRBM_STATUS__GUI_ACTIVE_MASK; 4969 4970 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4971 return 0; 4972 udelay(1); 4973 } 4974 return -ETIMEDOUT; 4975 } 4976 4977 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4978 bool req) 4979 { 4980 u32 i, tmp, val; 4981 4982 for (i = 0; i < adev->usec_timeout; i++) { 4983 /* Request with MeId=2, PipeId=0 */ 4984 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4985 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4986 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4987 4988 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4989 if (req) { 4990 if (val == tmp) 4991 break; 4992 } else { 4993 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4994 REQUEST, 1); 4995 4996 /* unlocked or locked by firmware */ 4997 if (val != tmp) 4998 break; 4999 } 5000 udelay(1); 5001 } 5002 5003 if (i >= adev->usec_timeout) 5004 return -EINVAL; 5005 5006 return 0; 5007 } 5008 5009 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 5010 { 5011 u32 grbm_soft_reset = 0; 5012 u32 tmp; 5013 int r, i, j, k; 5014 struct amdgpu_device *adev = ip_block->adev; 5015 5016 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5017 5018 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5019 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 5020 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 5021 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 5022 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 5023 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5024 5025 mutex_lock(&adev->srbm_mutex); 5026 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 5027 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 5028 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 5029 soc21_grbm_select(adev, i, k, j, 0); 5030 5031 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 5032 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 5033 } 5034 } 5035 } 5036 for (i = 0; i < adev->gfx.me.num_me; ++i) { 5037 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 5038 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 5039 soc21_grbm_select(adev, i, k, j, 0); 5040 5041 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 5042 } 5043 } 5044 } 5045 soc21_grbm_select(adev, 0, 0, 0, 0); 5046 mutex_unlock(&adev->srbm_mutex); 5047 5048 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 5049 mutex_lock(&adev->gfx.reset_sem_mutex); 5050 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 5051 if (r) { 5052 mutex_unlock(&adev->gfx.reset_sem_mutex); 5053 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 5054 return r; 5055 } 5056 5057 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 5058 5059 // Read CP_VMID_RESET register three times. 5060 // to get sufficient time for GFX_HQD_ACTIVE reach 0 5061 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5062 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5063 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 5064 5065 /* release the gfx mutex */ 5066 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 5067 mutex_unlock(&adev->gfx.reset_sem_mutex); 5068 if (r) { 5069 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 5070 return r; 5071 } 5072 5073 for (i = 0; i < adev->usec_timeout; i++) { 5074 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 5075 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 5076 break; 5077 udelay(1); 5078 } 5079 if (i >= adev->usec_timeout) { 5080 printk("Failed to wait all pipes clean\n"); 5081 return -EINVAL; 5082 } 5083 5084 /********** trigger soft reset ***********/ 5085 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5086 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5087 SOFT_RESET_CP, 1); 5088 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5089 SOFT_RESET_GFX, 1); 5090 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5091 SOFT_RESET_CPF, 1); 5092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5093 SOFT_RESET_CPC, 1); 5094 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5095 SOFT_RESET_CPG, 1); 5096 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5097 /********** exit soft reset ***********/ 5098 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 5099 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5100 SOFT_RESET_CP, 0); 5101 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5102 SOFT_RESET_GFX, 0); 5103 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5104 SOFT_RESET_CPF, 0); 5105 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5106 SOFT_RESET_CPC, 0); 5107 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5108 SOFT_RESET_CPG, 0); 5109 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 5110 5111 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 5112 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 5113 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 5114 5115 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 5116 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 5117 5118 for (i = 0; i < adev->usec_timeout; i++) { 5119 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 5120 break; 5121 udelay(1); 5122 } 5123 if (i >= adev->usec_timeout) { 5124 printk("Failed to wait CP_VMID_RESET to 0\n"); 5125 return -EINVAL; 5126 } 5127 5128 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5129 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5130 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5131 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5132 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5133 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 5134 5135 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5136 5137 return gfx_v11_0_cp_resume(adev); 5138 } 5139 5140 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 5141 { 5142 int i, r; 5143 struct amdgpu_device *adev = ip_block->adev; 5144 struct amdgpu_ring *ring; 5145 long tmo = msecs_to_jiffies(1000); 5146 5147 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5148 ring = &adev->gfx.gfx_ring[i]; 5149 r = amdgpu_ring_test_ib(ring, tmo); 5150 if (r) 5151 return true; 5152 } 5153 5154 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5155 ring = &adev->gfx.compute_ring[i]; 5156 r = amdgpu_ring_test_ib(ring, tmo); 5157 if (r) 5158 return true; 5159 } 5160 5161 return false; 5162 } 5163 5164 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5165 { 5166 struct amdgpu_device *adev = ip_block->adev; 5167 /** 5168 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 5169 */ 5170 return amdgpu_mes_resume(adev); 5171 } 5172 5173 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5174 { 5175 uint64_t clock; 5176 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5177 5178 if (amdgpu_sriov_vf(adev)) { 5179 amdgpu_gfx_off_ctrl(adev, false); 5180 mutex_lock(&adev->gfx.gpu_clock_mutex); 5181 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5182 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5183 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5184 if (clock_counter_hi_pre != clock_counter_hi_after) 5185 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5186 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5187 amdgpu_gfx_off_ctrl(adev, true); 5188 } else { 5189 preempt_disable(); 5190 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5191 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5192 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5193 if (clock_counter_hi_pre != clock_counter_hi_after) 5194 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5195 preempt_enable(); 5196 } 5197 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5198 5199 return clock; 5200 } 5201 5202 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5203 uint32_t vmid, 5204 uint32_t gds_base, uint32_t gds_size, 5205 uint32_t gws_base, uint32_t gws_size, 5206 uint32_t oa_base, uint32_t oa_size) 5207 { 5208 struct amdgpu_device *adev = ring->adev; 5209 5210 /* GDS Base */ 5211 gfx_v11_0_write_data_to_reg(ring, 0, false, 5212 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5213 gds_base); 5214 5215 /* GDS Size */ 5216 gfx_v11_0_write_data_to_reg(ring, 0, false, 5217 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5218 gds_size); 5219 5220 /* GWS */ 5221 gfx_v11_0_write_data_to_reg(ring, 0, false, 5222 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5223 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5224 5225 /* OA */ 5226 gfx_v11_0_write_data_to_reg(ring, 0, false, 5227 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5228 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5229 } 5230 5231 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5232 { 5233 struct amdgpu_device *adev = ip_block->adev; 5234 5235 switch (amdgpu_user_queue) { 5236 case -1: 5237 case 0: 5238 default: 5239 adev->gfx.disable_kq = false; 5240 adev->gfx.disable_uq = true; 5241 break; 5242 case 1: 5243 adev->gfx.disable_kq = false; 5244 adev->gfx.disable_uq = false; 5245 break; 5246 case 2: 5247 adev->gfx.disable_kq = true; 5248 adev->gfx.disable_uq = false; 5249 break; 5250 } 5251 5252 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5253 5254 if (adev->gfx.disable_kq) { 5255 /* We need one GFX ring temporarily to set up 5256 * the clear state. 5257 */ 5258 adev->gfx.num_gfx_rings = 1; 5259 adev->gfx.num_compute_rings = 0; 5260 } else { 5261 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5262 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5263 AMDGPU_MAX_COMPUTE_RINGS); 5264 } 5265 5266 gfx_v11_0_set_kiq_pm4_funcs(adev); 5267 gfx_v11_0_set_ring_funcs(adev); 5268 gfx_v11_0_set_irq_funcs(adev); 5269 gfx_v11_0_set_gds_init(adev); 5270 gfx_v11_0_set_rlc_funcs(adev); 5271 gfx_v11_0_set_mqd_funcs(adev); 5272 gfx_v11_0_set_imu_funcs(adev); 5273 5274 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5275 5276 return gfx_v11_0_init_microcode(adev); 5277 } 5278 5279 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) 5280 { 5281 struct amdgpu_device *adev = ip_block->adev; 5282 int r; 5283 5284 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5285 if (r) 5286 return r; 5287 5288 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5289 if (r) 5290 return r; 5291 5292 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5293 if (r) 5294 return r; 5295 5296 r = gfx_v11_0_set_userq_eop_interrupts(adev, true); 5297 if (r) 5298 return r; 5299 5300 return 0; 5301 } 5302 5303 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5304 { 5305 uint32_t rlc_cntl; 5306 5307 /* if RLC is not enabled, do nothing */ 5308 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5309 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5310 } 5311 5312 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5313 { 5314 uint32_t data; 5315 unsigned i; 5316 5317 data = RLC_SAFE_MODE__CMD_MASK; 5318 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5319 5320 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5321 5322 /* wait for RLC_SAFE_MODE */ 5323 for (i = 0; i < adev->usec_timeout; i++) { 5324 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5325 RLC_SAFE_MODE, CMD)) 5326 break; 5327 udelay(1); 5328 } 5329 } 5330 5331 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5332 { 5333 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5334 } 5335 5336 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5337 bool enable) 5338 { 5339 uint32_t def, data; 5340 5341 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5342 return; 5343 5344 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5345 5346 if (enable) 5347 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5348 else 5349 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5350 5351 if (def != data) 5352 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5353 } 5354 5355 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5356 bool enable) 5357 { 5358 uint32_t def, data; 5359 5360 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5361 return; 5362 5363 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5364 5365 if (enable) 5366 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5367 else 5368 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5369 5370 if (def != data) 5371 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5372 } 5373 5374 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5375 bool enable) 5376 { 5377 uint32_t def, data; 5378 5379 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5380 return; 5381 5382 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5383 5384 if (enable) 5385 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5386 else 5387 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5388 5389 if (def != data) 5390 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5391 } 5392 5393 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5394 bool enable) 5395 { 5396 uint32_t data, def; 5397 5398 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5399 return; 5400 5401 /* It is disabled by HW by default */ 5402 if (enable) { 5403 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5404 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5405 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5406 5407 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5408 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5409 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5410 5411 if (def != data) 5412 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5413 } 5414 } else { 5415 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5416 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5417 5418 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5419 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5420 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5421 5422 if (def != data) 5423 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5424 } 5425 } 5426 } 5427 5428 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5429 bool enable) 5430 { 5431 uint32_t def, data; 5432 5433 if (!(adev->cg_flags & 5434 (AMD_CG_SUPPORT_GFX_CGCG | 5435 AMD_CG_SUPPORT_GFX_CGLS | 5436 AMD_CG_SUPPORT_GFX_3D_CGCG | 5437 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5438 return; 5439 5440 if (enable) { 5441 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5442 5443 /* unset CGCG override */ 5444 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5445 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5446 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5447 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5448 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5449 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5450 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5451 5452 /* update CGCG override bits */ 5453 if (def != data) 5454 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5455 5456 /* enable cgcg FSM(0x0000363F) */ 5457 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5458 5459 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5460 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5461 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5462 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5463 } 5464 5465 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5466 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5467 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5468 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5469 } 5470 5471 if (def != data) 5472 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5473 5474 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5475 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5476 5477 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5478 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5479 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5480 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5481 } 5482 5483 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5484 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5485 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5486 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5487 } 5488 5489 if (def != data) 5490 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5491 5492 /* set IDLE_POLL_COUNT(0x00900100) */ 5493 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5494 5495 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5496 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5497 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5498 5499 if (def != data) 5500 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5501 5502 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5503 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5504 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5505 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5506 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5507 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5508 5509 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5510 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5511 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5512 5513 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5514 if (adev->sdma.num_instances > 1) { 5515 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5516 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5517 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5518 } 5519 } else { 5520 /* Program RLC_CGCG_CGLS_CTRL */ 5521 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5522 5523 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5524 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5525 5526 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5527 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5528 5529 if (def != data) 5530 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5531 5532 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5533 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5534 5535 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5536 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5537 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5538 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5539 5540 if (def != data) 5541 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5542 5543 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5544 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5545 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5546 5547 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5548 if (adev->sdma.num_instances > 1) { 5549 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5550 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5551 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5552 } 5553 } 5554 } 5555 5556 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5557 bool enable) 5558 { 5559 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5560 5561 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5562 5563 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5564 5565 gfx_v11_0_update_repeater_fgcg(adev, enable); 5566 5567 gfx_v11_0_update_sram_fgcg(adev, enable); 5568 5569 gfx_v11_0_update_perf_clk(adev, enable); 5570 5571 if (adev->cg_flags & 5572 (AMD_CG_SUPPORT_GFX_MGCG | 5573 AMD_CG_SUPPORT_GFX_CGLS | 5574 AMD_CG_SUPPORT_GFX_CGCG | 5575 AMD_CG_SUPPORT_GFX_3D_CGCG | 5576 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5577 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5578 5579 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5580 5581 return 0; 5582 } 5583 5584 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 5585 struct amdgpu_ring *ring, unsigned vmid) 5586 { 5587 u32 reg, pre_data, data; 5588 5589 amdgpu_gfx_off_ctrl(adev, false); 5590 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5591 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5592 pre_data = RREG32_NO_KIQ(reg); 5593 else 5594 pre_data = RREG32(reg); 5595 5596 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5597 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5598 5599 if (pre_data != data) { 5600 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5601 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5602 } else 5603 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5604 } 5605 amdgpu_gfx_off_ctrl(adev, true); 5606 5607 if (ring 5608 && amdgpu_sriov_is_pp_one_vf(adev) 5609 && (pre_data != data) 5610 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5611 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5612 amdgpu_ring_emit_wreg(ring, reg, data); 5613 } 5614 } 5615 5616 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5617 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5618 .set_safe_mode = gfx_v11_0_set_safe_mode, 5619 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5620 .init = gfx_v11_0_rlc_init, 5621 .get_csb_size = gfx_v11_0_get_csb_size, 5622 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5623 .resume = gfx_v11_0_rlc_resume, 5624 .stop = gfx_v11_0_rlc_stop, 5625 .reset = gfx_v11_0_rlc_reset, 5626 .start = gfx_v11_0_rlc_start, 5627 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5628 }; 5629 5630 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5631 { 5632 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5633 5634 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5635 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5636 else 5637 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5638 5639 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5640 5641 // Program RLC_PG_DELAY3 for CGPG hysteresis 5642 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5643 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5644 case IP_VERSION(11, 0, 1): 5645 case IP_VERSION(11, 0, 4): 5646 case IP_VERSION(11, 5, 0): 5647 case IP_VERSION(11, 5, 1): 5648 case IP_VERSION(11, 5, 2): 5649 case IP_VERSION(11, 5, 3): 5650 case IP_VERSION(11, 5, 4): 5651 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5652 break; 5653 default: 5654 break; 5655 } 5656 } 5657 } 5658 5659 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5660 { 5661 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5662 5663 gfx_v11_cntl_power_gating(adev, enable); 5664 5665 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5666 } 5667 5668 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5669 enum amd_powergating_state state) 5670 { 5671 struct amdgpu_device *adev = ip_block->adev; 5672 bool enable = (state == AMD_PG_STATE_GATE); 5673 5674 if (amdgpu_sriov_vf(adev)) 5675 return 0; 5676 5677 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5678 case IP_VERSION(11, 0, 0): 5679 case IP_VERSION(11, 0, 2): 5680 case IP_VERSION(11, 0, 3): 5681 amdgpu_gfx_off_ctrl(adev, enable); 5682 break; 5683 case IP_VERSION(11, 0, 1): 5684 case IP_VERSION(11, 0, 4): 5685 case IP_VERSION(11, 5, 0): 5686 case IP_VERSION(11, 5, 1): 5687 case IP_VERSION(11, 5, 2): 5688 case IP_VERSION(11, 5, 3): 5689 case IP_VERSION(11, 5, 4): 5690 if (!enable) 5691 amdgpu_gfx_off_ctrl(adev, false); 5692 5693 gfx_v11_cntl_pg(adev, enable); 5694 5695 if (enable) 5696 amdgpu_gfx_off_ctrl(adev, true); 5697 5698 break; 5699 default: 5700 break; 5701 } 5702 5703 return 0; 5704 } 5705 5706 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5707 enum amd_clockgating_state state) 5708 { 5709 struct amdgpu_device *adev = ip_block->adev; 5710 5711 if (amdgpu_sriov_vf(adev)) 5712 return 0; 5713 5714 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5715 case IP_VERSION(11, 0, 0): 5716 case IP_VERSION(11, 0, 1): 5717 case IP_VERSION(11, 0, 2): 5718 case IP_VERSION(11, 0, 3): 5719 case IP_VERSION(11, 0, 4): 5720 case IP_VERSION(11, 5, 0): 5721 case IP_VERSION(11, 5, 1): 5722 case IP_VERSION(11, 5, 2): 5723 case IP_VERSION(11, 5, 3): 5724 case IP_VERSION(11, 5, 4): 5725 gfx_v11_0_update_gfx_clock_gating(adev, 5726 state == AMD_CG_STATE_GATE); 5727 break; 5728 default: 5729 break; 5730 } 5731 5732 return 0; 5733 } 5734 5735 static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 5736 { 5737 struct amdgpu_device *adev = ip_block->adev; 5738 int data; 5739 5740 /* AMD_CG_SUPPORT_GFX_MGCG */ 5741 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5742 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5743 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5744 5745 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5746 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5747 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5748 5749 /* AMD_CG_SUPPORT_GFX_FGCG */ 5750 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5751 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5752 5753 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5754 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5755 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5756 5757 /* AMD_CG_SUPPORT_GFX_CGCG */ 5758 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5759 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5760 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5761 5762 /* AMD_CG_SUPPORT_GFX_CGLS */ 5763 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5764 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5765 5766 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5767 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5768 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5769 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5770 5771 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5772 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5773 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5774 } 5775 5776 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5777 { 5778 /* gfx11 is 32bit rptr*/ 5779 return *(uint32_t *)ring->rptr_cpu_addr; 5780 } 5781 5782 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5783 { 5784 struct amdgpu_device *adev = ring->adev; 5785 u64 wptr; 5786 5787 /* XXX check if swapping is necessary on BE */ 5788 if (ring->use_doorbell) { 5789 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5790 } else { 5791 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5792 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5793 } 5794 5795 return wptr; 5796 } 5797 5798 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5799 { 5800 struct amdgpu_device *adev = ring->adev; 5801 5802 if (ring->use_doorbell) { 5803 /* XXX check if swapping is necessary on BE */ 5804 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5805 ring->wptr); 5806 WDOORBELL64(ring->doorbell_index, ring->wptr); 5807 } else { 5808 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5809 lower_32_bits(ring->wptr)); 5810 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5811 upper_32_bits(ring->wptr)); 5812 } 5813 } 5814 5815 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5816 { 5817 /* gfx11 hardware is 32bit rptr */ 5818 return *(uint32_t *)ring->rptr_cpu_addr; 5819 } 5820 5821 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5822 { 5823 u64 wptr; 5824 5825 /* XXX check if swapping is necessary on BE */ 5826 if (ring->use_doorbell) 5827 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5828 else 5829 BUG(); 5830 return wptr; 5831 } 5832 5833 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5834 { 5835 struct amdgpu_device *adev = ring->adev; 5836 5837 /* XXX check if swapping is necessary on BE */ 5838 if (ring->use_doorbell) { 5839 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5840 ring->wptr); 5841 WDOORBELL64(ring->doorbell_index, ring->wptr); 5842 } else { 5843 BUG(); /* only DOORBELL method supported on gfx11 now */ 5844 } 5845 } 5846 5847 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5848 { 5849 struct amdgpu_device *adev = ring->adev; 5850 u32 ref_and_mask, reg_mem_engine; 5851 5852 if (!adev->gfx.funcs->get_hdp_flush_mask) { 5853 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 5854 return; 5855 } 5856 5857 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 5858 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5859 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5860 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5861 ref_and_mask, ref_and_mask, 0x20); 5862 } 5863 5864 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5865 struct amdgpu_job *job, 5866 struct amdgpu_ib *ib, 5867 uint32_t flags) 5868 { 5869 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5870 u32 header, control = 0; 5871 5872 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5873 5874 control |= ib->length_dw | (vmid << 24); 5875 5876 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5877 control |= INDIRECT_BUFFER_PRE_ENB(1); 5878 5879 if (flags & AMDGPU_IB_PREEMPTED) 5880 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5881 5882 if (vmid && !ring->adev->gfx.rs64_enable) 5883 gfx_v11_0_ring_emit_de_meta(ring, 5884 !amdgpu_sriov_vf(ring->adev) && (flags & AMDGPU_IB_PREEMPTED)); 5885 } 5886 5887 amdgpu_ring_write(ring, header); 5888 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5889 amdgpu_ring_write(ring, 5890 #ifdef __BIG_ENDIAN 5891 (2 << 0) | 5892 #endif 5893 lower_32_bits(ib->gpu_addr)); 5894 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5895 amdgpu_ring_write(ring, control); 5896 } 5897 5898 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5899 struct amdgpu_job *job, 5900 struct amdgpu_ib *ib, 5901 uint32_t flags) 5902 { 5903 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5904 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5905 5906 /* Currently, there is a high possibility to get wave ID mismatch 5907 * between ME and GDS, leading to a hw deadlock, because ME generates 5908 * different wave IDs than the GDS expects. This situation happens 5909 * randomly when at least 5 compute pipes use GDS ordered append. 5910 * The wave IDs generated by ME are also wrong after suspend/resume. 5911 * Those are probably bugs somewhere else in the kernel driver. 5912 * 5913 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5914 * GDS to 0 for this ring (me/pipe). 5915 */ 5916 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5917 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5918 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5919 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5920 } 5921 5922 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5923 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5924 amdgpu_ring_write(ring, 5925 #ifdef __BIG_ENDIAN 5926 (2 << 0) | 5927 #endif 5928 lower_32_bits(ib->gpu_addr)); 5929 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5930 amdgpu_ring_write(ring, control); 5931 } 5932 5933 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5934 u64 seq, unsigned flags) 5935 { 5936 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5937 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5938 5939 /* RELEASE_MEM - flush caches, send int */ 5940 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5941 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5942 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5943 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5944 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5945 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5946 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5947 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5948 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5949 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5950 5951 /* 5952 * the address should be Qword aligned if 64bit write, Dword 5953 * aligned if only send 32bit data low (discard data high) 5954 */ 5955 if (write64bit) 5956 BUG_ON(addr & 0x7); 5957 else 5958 BUG_ON(addr & 0x3); 5959 amdgpu_ring_write(ring, lower_32_bits(addr)); 5960 amdgpu_ring_write(ring, upper_32_bits(addr)); 5961 amdgpu_ring_write(ring, lower_32_bits(seq)); 5962 amdgpu_ring_write(ring, upper_32_bits(seq)); 5963 amdgpu_ring_write(ring, 0); 5964 } 5965 5966 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5967 { 5968 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5969 uint32_t seq = ring->fence_drv.sync_seq; 5970 uint64_t addr = ring->fence_drv.gpu_addr; 5971 5972 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5973 upper_32_bits(addr), seq, 0xffffffff, 4); 5974 } 5975 5976 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5977 uint16_t pasid, uint32_t flush_type, 5978 bool all_hub, uint8_t dst_sel) 5979 { 5980 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5981 amdgpu_ring_write(ring, 5982 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5983 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5984 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5985 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5986 } 5987 5988 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5989 unsigned vmid, uint64_t pd_addr) 5990 { 5991 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5992 5993 /* compute doesn't have PFP */ 5994 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5995 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5996 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5997 amdgpu_ring_write(ring, 0x0); 5998 } 5999 6000 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 6001 * changed in any way. 6002 */ 6003 ring->set_q_mode_offs = 0; 6004 ring->set_q_mode_ptr = NULL; 6005 } 6006 6007 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 6008 u64 seq, unsigned int flags) 6009 { 6010 struct amdgpu_device *adev = ring->adev; 6011 6012 /* we only allocate 32bit for each seq wb address */ 6013 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 6014 6015 /* write fence seq to the "addr" */ 6016 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6017 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6018 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 6019 amdgpu_ring_write(ring, lower_32_bits(addr)); 6020 amdgpu_ring_write(ring, upper_32_bits(addr)); 6021 amdgpu_ring_write(ring, lower_32_bits(seq)); 6022 6023 if (flags & AMDGPU_FENCE_FLAG_INT) { 6024 /* set register to trigger INT */ 6025 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6026 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6027 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 6028 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 6029 amdgpu_ring_write(ring, 0); 6030 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 6031 } 6032 } 6033 6034 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 6035 uint32_t flags) 6036 { 6037 uint32_t dw2 = 0; 6038 6039 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6040 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6041 /* set load_global_config & load_global_uconfig */ 6042 dw2 |= 0x8001; 6043 /* set load_cs_sh_regs */ 6044 dw2 |= 0x01000000; 6045 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 6046 dw2 |= 0x10002; 6047 } 6048 6049 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6050 amdgpu_ring_write(ring, dw2); 6051 amdgpu_ring_write(ring, 0); 6052 } 6053 6054 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 6055 uint64_t addr) 6056 { 6057 unsigned ret; 6058 6059 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6060 amdgpu_ring_write(ring, lower_32_bits(addr)); 6061 amdgpu_ring_write(ring, upper_32_bits(addr)); 6062 /* discard following DWs if *cond_exec_gpu_addr==0 */ 6063 amdgpu_ring_write(ring, 0); 6064 ret = ring->wptr & ring->buf_mask; 6065 /* patch dummy value later */ 6066 amdgpu_ring_write(ring, 0); 6067 6068 return ret; 6069 } 6070 6071 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 6072 u64 shadow_va, u64 csa_va, 6073 u64 gds_va, bool init_shadow, 6074 int vmid) 6075 { 6076 struct amdgpu_device *adev = ring->adev; 6077 unsigned int offs, end; 6078 6079 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 6080 return; 6081 6082 /* 6083 * The logic here isn't easy to understand because we need to keep state 6084 * accross multiple executions of the function as well as between the 6085 * CPU and GPU. The general idea is that the newly written GPU command 6086 * has a condition on the previous one and only executed if really 6087 * necessary. 6088 */ 6089 6090 /* 6091 * The dw in the NOP controls if the next SET_Q_MODE packet should be 6092 * executed or not. Reserve 64bits just to be on the save side. 6093 */ 6094 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 6095 offs = ring->wptr & ring->buf_mask; 6096 6097 /* 6098 * We start with skipping the prefix SET_Q_MODE and always executing 6099 * the postfix SET_Q_MODE packet. This is changed below with a 6100 * WRITE_DATA command when the postfix executed. 6101 */ 6102 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 6103 amdgpu_ring_write(ring, 0); 6104 6105 if (ring->set_q_mode_offs) { 6106 uint64_t addr; 6107 6108 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6109 addr += ring->set_q_mode_offs << 2; 6110 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 6111 } 6112 6113 /* 6114 * When the postfix SET_Q_MODE packet executes we need to make sure that the 6115 * next prefix SET_Q_MODE packet executes as well. 6116 */ 6117 if (!shadow_va) { 6118 uint64_t addr; 6119 6120 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 6121 addr += offs << 2; 6122 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6123 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 6124 amdgpu_ring_write(ring, lower_32_bits(addr)); 6125 amdgpu_ring_write(ring, upper_32_bits(addr)); 6126 amdgpu_ring_write(ring, 0x1); 6127 } 6128 6129 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 6130 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 6131 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 6132 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 6133 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 6134 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 6135 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 6136 amdgpu_ring_write(ring, shadow_va ? 6137 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 6138 amdgpu_ring_write(ring, init_shadow ? 6139 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 6140 6141 if (ring->set_q_mode_offs) 6142 amdgpu_ring_patch_cond_exec(ring, end); 6143 6144 if (shadow_va) { 6145 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 6146 6147 /* 6148 * If the tokens match try to skip the last postfix SET_Q_MODE 6149 * packet to avoid saving/restoring the state all the time. 6150 */ 6151 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 6152 *ring->set_q_mode_ptr = 0; 6153 6154 ring->set_q_mode_token = token; 6155 } else { 6156 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 6157 } 6158 6159 ring->set_q_mode_offs = offs; 6160 } 6161 6162 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 6163 { 6164 int i, r = 0; 6165 struct amdgpu_device *adev = ring->adev; 6166 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6167 struct amdgpu_ring *kiq_ring = &kiq->ring; 6168 unsigned long flags; 6169 6170 if (adev->enable_mes) 6171 return -EINVAL; 6172 6173 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6174 return -EINVAL; 6175 6176 spin_lock_irqsave(&kiq->ring_lock, flags); 6177 6178 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 6179 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6180 return -ENOMEM; 6181 } 6182 6183 /* assert preemption condition */ 6184 amdgpu_ring_set_preempt_cond_exec(ring, false); 6185 6186 /* assert IB preemption, emit the trailing fence */ 6187 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 6188 ring->trail_fence_gpu_addr, 6189 ++ring->trail_seq); 6190 amdgpu_ring_commit(kiq_ring); 6191 6192 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6193 6194 /* poll the trailing fence */ 6195 for (i = 0; i < adev->usec_timeout; i++) { 6196 if (ring->trail_seq == 6197 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 6198 break; 6199 udelay(1); 6200 } 6201 6202 if (i >= adev->usec_timeout) { 6203 r = -EINVAL; 6204 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 6205 } 6206 6207 /* deassert preemption condition */ 6208 amdgpu_ring_set_preempt_cond_exec(ring, true); 6209 return r; 6210 } 6211 6212 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6213 { 6214 struct amdgpu_device *adev = ring->adev; 6215 struct v10_de_ib_state de_payload = {0}; 6216 uint64_t offset, gds_addr, de_payload_gpu_addr; 6217 void *de_payload_cpu_addr; 6218 int cnt; 6219 6220 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6221 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6222 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6223 6224 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6225 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6226 PAGE_SIZE); 6227 6228 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6229 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6230 6231 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6232 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6233 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6234 WRITE_DATA_DST_SEL(8) | 6235 WR_CONFIRM) | 6236 WRITE_DATA_CACHE_POLICY(0)); 6237 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6238 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6239 6240 if (resume) 6241 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6242 sizeof(de_payload) >> 2); 6243 else 6244 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6245 sizeof(de_payload) >> 2); 6246 } 6247 6248 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6249 bool secure) 6250 { 6251 uint32_t v = secure ? FRAME_TMZ : 0; 6252 6253 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6254 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6255 } 6256 6257 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6258 uint32_t reg_val_offs) 6259 { 6260 struct amdgpu_device *adev = ring->adev; 6261 6262 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6263 amdgpu_ring_write(ring, 0 | /* src: register*/ 6264 (5 << 8) | /* dst: memory */ 6265 (1 << 20)); /* write confirm */ 6266 amdgpu_ring_write(ring, reg); 6267 amdgpu_ring_write(ring, 0); 6268 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6269 reg_val_offs * 4)); 6270 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6271 reg_val_offs * 4)); 6272 } 6273 6274 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6275 uint32_t val) 6276 { 6277 uint32_t cmd = 0; 6278 6279 switch (ring->funcs->type) { 6280 case AMDGPU_RING_TYPE_GFX: 6281 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6282 break; 6283 case AMDGPU_RING_TYPE_KIQ: 6284 cmd = (1 << 16); /* no inc addr */ 6285 break; 6286 default: 6287 cmd = WR_CONFIRM; 6288 break; 6289 } 6290 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6291 amdgpu_ring_write(ring, cmd); 6292 amdgpu_ring_write(ring, reg); 6293 amdgpu_ring_write(ring, 0); 6294 amdgpu_ring_write(ring, val); 6295 } 6296 6297 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6298 uint32_t val, uint32_t mask) 6299 { 6300 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6301 } 6302 6303 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6304 uint32_t reg0, uint32_t reg1, 6305 uint32_t ref, uint32_t mask) 6306 { 6307 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6308 6309 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6310 ref, mask, 0x20); 6311 } 6312 6313 static void 6314 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6315 uint32_t me, uint32_t pipe, 6316 enum amdgpu_interrupt_state state) 6317 { 6318 uint32_t cp_int_cntl, cp_int_cntl_reg; 6319 6320 if (!me) { 6321 switch (pipe) { 6322 case 0: 6323 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6324 break; 6325 case 1: 6326 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6327 break; 6328 default: 6329 DRM_DEBUG("invalid pipe %d\n", pipe); 6330 return; 6331 } 6332 } else { 6333 DRM_DEBUG("invalid me %d\n", me); 6334 return; 6335 } 6336 6337 switch (state) { 6338 case AMDGPU_IRQ_STATE_DISABLE: 6339 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6340 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6341 TIME_STAMP_INT_ENABLE, 0); 6342 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6343 GENERIC0_INT_ENABLE, 0); 6344 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6345 break; 6346 case AMDGPU_IRQ_STATE_ENABLE: 6347 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6348 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6349 TIME_STAMP_INT_ENABLE, 1); 6350 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6351 GENERIC0_INT_ENABLE, 1); 6352 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6353 break; 6354 default: 6355 break; 6356 } 6357 } 6358 6359 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6360 int me, int pipe, 6361 enum amdgpu_interrupt_state state) 6362 { 6363 u32 mec_int_cntl, mec_int_cntl_reg; 6364 6365 /* 6366 * amdgpu controls only the first MEC. That's why this function only 6367 * handles the setting of interrupts for this specific MEC. All other 6368 * pipes' interrupts are set by amdkfd. 6369 */ 6370 6371 if (me == 1) { 6372 switch (pipe) { 6373 case 0: 6374 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6375 break; 6376 case 1: 6377 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6378 break; 6379 case 2: 6380 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6381 break; 6382 case 3: 6383 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6384 break; 6385 default: 6386 DRM_DEBUG("invalid pipe %d\n", pipe); 6387 return; 6388 } 6389 } else { 6390 DRM_DEBUG("invalid me %d\n", me); 6391 return; 6392 } 6393 6394 switch (state) { 6395 case AMDGPU_IRQ_STATE_DISABLE: 6396 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6397 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6398 TIME_STAMP_INT_ENABLE, 0); 6399 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6400 GENERIC0_INT_ENABLE, 0); 6401 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6402 break; 6403 case AMDGPU_IRQ_STATE_ENABLE: 6404 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6405 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6406 TIME_STAMP_INT_ENABLE, 1); 6407 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6408 GENERIC0_INT_ENABLE, 1); 6409 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6410 break; 6411 default: 6412 break; 6413 } 6414 } 6415 6416 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6417 struct amdgpu_irq_src *src, 6418 unsigned type, 6419 enum amdgpu_interrupt_state state) 6420 { 6421 switch (type) { 6422 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6423 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6424 break; 6425 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6426 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6427 break; 6428 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6429 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6430 break; 6431 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6432 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6433 break; 6434 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6435 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6436 break; 6437 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6438 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6439 break; 6440 default: 6441 break; 6442 } 6443 return 0; 6444 } 6445 6446 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6447 struct amdgpu_irq_src *source, 6448 struct amdgpu_iv_entry *entry) 6449 { 6450 u32 doorbell_offset = entry->src_data[0]; 6451 u8 me_id, pipe_id, queue_id; 6452 struct amdgpu_ring *ring; 6453 int i; 6454 6455 DRM_DEBUG("IH: CP EOP\n"); 6456 6457 if (adev->enable_mes && doorbell_offset) { 6458 struct amdgpu_userq_fence_driver *fence_drv = NULL; 6459 struct xarray *xa = &adev->userq_xa; 6460 unsigned long flags; 6461 6462 xa_lock_irqsave(xa, flags); 6463 fence_drv = xa_load(xa, doorbell_offset); 6464 if (fence_drv) 6465 amdgpu_userq_fence_driver_process(fence_drv); 6466 xa_unlock_irqrestore(xa, flags); 6467 } else { 6468 me_id = (entry->ring_id & 0x0c) >> 2; 6469 pipe_id = (entry->ring_id & 0x03) >> 0; 6470 queue_id = (entry->ring_id & 0x70) >> 4; 6471 6472 switch (me_id) { 6473 case 0: 6474 if (pipe_id == 0) 6475 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6476 else 6477 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6478 break; 6479 case 1: 6480 case 2: 6481 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6482 ring = &adev->gfx.compute_ring[i]; 6483 /* Per-queue interrupt is supported for MEC starting from VI. 6484 * The interrupt can only be enabled/disabled per pipe instead 6485 * of per queue. 6486 */ 6487 if ((ring->me == me_id) && 6488 (ring->pipe == pipe_id) && 6489 (ring->queue == queue_id)) 6490 amdgpu_fence_process(ring); 6491 } 6492 break; 6493 } 6494 } 6495 6496 return 0; 6497 } 6498 6499 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6500 struct amdgpu_irq_src *source, 6501 unsigned int type, 6502 enum amdgpu_interrupt_state state) 6503 { 6504 u32 cp_int_cntl_reg, cp_int_cntl; 6505 int i, j; 6506 6507 switch (state) { 6508 case AMDGPU_IRQ_STATE_DISABLE: 6509 case AMDGPU_IRQ_STATE_ENABLE: 6510 for (i = 0; i < adev->gfx.me.num_me; i++) { 6511 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6512 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6513 6514 if (cp_int_cntl_reg) { 6515 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6516 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6517 PRIV_REG_INT_ENABLE, 6518 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6519 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6520 } 6521 } 6522 } 6523 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6524 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6525 /* MECs start at 1 */ 6526 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6527 6528 if (cp_int_cntl_reg) { 6529 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6530 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6531 PRIV_REG_INT_ENABLE, 6532 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6533 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6534 } 6535 } 6536 } 6537 break; 6538 default: 6539 break; 6540 } 6541 6542 return 0; 6543 } 6544 6545 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6546 struct amdgpu_irq_src *source, 6547 unsigned type, 6548 enum amdgpu_interrupt_state state) 6549 { 6550 u32 cp_int_cntl_reg, cp_int_cntl; 6551 int i, j; 6552 6553 switch (state) { 6554 case AMDGPU_IRQ_STATE_DISABLE: 6555 case AMDGPU_IRQ_STATE_ENABLE: 6556 for (i = 0; i < adev->gfx.me.num_me; i++) { 6557 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6558 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6559 6560 if (cp_int_cntl_reg) { 6561 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6562 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6563 OPCODE_ERROR_INT_ENABLE, 6564 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6565 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6566 } 6567 } 6568 } 6569 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6570 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6571 /* MECs start at 1 */ 6572 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6573 6574 if (cp_int_cntl_reg) { 6575 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6576 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6577 OPCODE_ERROR_INT_ENABLE, 6578 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6579 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6580 } 6581 } 6582 } 6583 break; 6584 default: 6585 break; 6586 } 6587 return 0; 6588 } 6589 6590 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6591 struct amdgpu_irq_src *source, 6592 unsigned int type, 6593 enum amdgpu_interrupt_state state) 6594 { 6595 u32 cp_int_cntl_reg, cp_int_cntl; 6596 int i, j; 6597 6598 switch (state) { 6599 case AMDGPU_IRQ_STATE_DISABLE: 6600 case AMDGPU_IRQ_STATE_ENABLE: 6601 for (i = 0; i < adev->gfx.me.num_me; i++) { 6602 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6603 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6604 6605 if (cp_int_cntl_reg) { 6606 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6607 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6608 PRIV_INSTR_INT_ENABLE, 6609 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6610 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6611 } 6612 } 6613 } 6614 break; 6615 default: 6616 break; 6617 } 6618 6619 return 0; 6620 } 6621 6622 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6623 struct amdgpu_iv_entry *entry) 6624 { 6625 u8 me_id, pipe_id, queue_id; 6626 struct amdgpu_ring *ring; 6627 int i; 6628 6629 me_id = (entry->ring_id & 0x0c) >> 2; 6630 pipe_id = (entry->ring_id & 0x03) >> 0; 6631 queue_id = (entry->ring_id & 0x70) >> 4; 6632 6633 if (!adev->gfx.disable_kq) { 6634 switch (me_id) { 6635 case 0: 6636 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6637 ring = &adev->gfx.gfx_ring[i]; 6638 if (ring->me == me_id && ring->pipe == pipe_id && 6639 ring->queue == queue_id) 6640 drm_sched_fault(&ring->sched); 6641 } 6642 break; 6643 case 1: 6644 case 2: 6645 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6646 ring = &adev->gfx.compute_ring[i]; 6647 if (ring->me == me_id && ring->pipe == pipe_id && 6648 ring->queue == queue_id) 6649 drm_sched_fault(&ring->sched); 6650 } 6651 break; 6652 default: 6653 BUG(); 6654 break; 6655 } 6656 } 6657 } 6658 6659 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6660 struct amdgpu_irq_src *source, 6661 struct amdgpu_iv_entry *entry) 6662 { 6663 DRM_ERROR("Illegal register access in command stream\n"); 6664 gfx_v11_0_handle_priv_fault(adev, entry); 6665 return 0; 6666 } 6667 6668 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6669 struct amdgpu_irq_src *source, 6670 struct amdgpu_iv_entry *entry) 6671 { 6672 DRM_ERROR("Illegal opcode in command stream\n"); 6673 gfx_v11_0_handle_priv_fault(adev, entry); 6674 return 0; 6675 } 6676 6677 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6678 struct amdgpu_irq_src *source, 6679 struct amdgpu_iv_entry *entry) 6680 { 6681 DRM_ERROR("Illegal instruction in command stream\n"); 6682 gfx_v11_0_handle_priv_fault(adev, entry); 6683 return 0; 6684 } 6685 6686 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6687 struct amdgpu_irq_src *source, 6688 struct amdgpu_iv_entry *entry) 6689 { 6690 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6691 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6692 6693 return 0; 6694 } 6695 6696 #if 0 6697 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6698 struct amdgpu_irq_src *src, 6699 unsigned int type, 6700 enum amdgpu_interrupt_state state) 6701 { 6702 uint32_t tmp, target; 6703 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6704 6705 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6706 target += ring->pipe; 6707 6708 switch (type) { 6709 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6710 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6711 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6712 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6713 GENERIC2_INT_ENABLE, 0); 6714 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6715 6716 tmp = RREG32_SOC15_IP(GC, target); 6717 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6718 GENERIC2_INT_ENABLE, 0); 6719 WREG32_SOC15_IP(GC, target, tmp); 6720 } else { 6721 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6722 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6723 GENERIC2_INT_ENABLE, 1); 6724 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6725 6726 tmp = RREG32_SOC15_IP(GC, target); 6727 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6728 GENERIC2_INT_ENABLE, 1); 6729 WREG32_SOC15_IP(GC, target, tmp); 6730 } 6731 break; 6732 default: 6733 BUG(); /* kiq only support GENERIC2_INT now */ 6734 break; 6735 } 6736 return 0; 6737 } 6738 #endif 6739 6740 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6741 { 6742 const unsigned int gcr_cntl = 6743 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6744 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6745 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6746 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6747 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6748 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6749 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6750 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6751 6752 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6753 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6754 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6755 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6756 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6757 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6758 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6759 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6760 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6761 } 6762 6763 static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev) 6764 { 6765 /* Disable the pipe reset until the CPFW fully support it.*/ 6766 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 6767 return false; 6768 } 6769 6770 6771 static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring) 6772 { 6773 struct amdgpu_device *adev = ring->adev; 6774 uint32_t reset_pipe = 0, clean_pipe = 0; 6775 int r; 6776 6777 if (!gfx_v11_pipe_reset_support(adev)) 6778 return -EOPNOTSUPP; 6779 6780 gfx_v11_0_set_safe_mode(adev, 0); 6781 mutex_lock(&adev->srbm_mutex); 6782 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6783 6784 switch (ring->pipe) { 6785 case 0: 6786 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6787 PFP_PIPE0_RESET, 1); 6788 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6789 ME_PIPE0_RESET, 1); 6790 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6791 PFP_PIPE0_RESET, 0); 6792 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6793 ME_PIPE0_RESET, 0); 6794 break; 6795 case 1: 6796 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6797 PFP_PIPE1_RESET, 1); 6798 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 6799 ME_PIPE1_RESET, 1); 6800 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6801 PFP_PIPE1_RESET, 0); 6802 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 6803 ME_PIPE1_RESET, 0); 6804 break; 6805 default: 6806 break; 6807 } 6808 6809 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 6810 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 6811 6812 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 6813 RS64_FW_UC_START_ADDR_LO; 6814 soc21_grbm_select(adev, 0, 0, 0, 0); 6815 mutex_unlock(&adev->srbm_mutex); 6816 gfx_v11_0_unset_safe_mode(adev, 0); 6817 6818 dev_info(adev->dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring->name, 6819 r == 0 ? "successfully" : "failed"); 6820 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 6821 * so the pipe reset status relies on the later gfx ring test result. 6822 */ 6823 return 0; 6824 } 6825 6826 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, 6827 unsigned int vmid, 6828 struct amdgpu_fence *timedout_fence) 6829 { 6830 struct amdgpu_device *adev = ring->adev; 6831 bool use_mmio = false; 6832 int r; 6833 6834 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6835 6836 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); 6837 if (r) { 6838 6839 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 6840 r = gfx_v11_reset_gfx_pipe(ring); 6841 if (r) 6842 return r; 6843 } 6844 6845 if (use_mmio) { 6846 r = gfx_v11_0_kgq_init_queue(ring, true); 6847 if (r) { 6848 dev_err(adev->dev, "failed to init kgq\n"); 6849 return r; 6850 } 6851 6852 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 6853 if (r) { 6854 dev_err(adev->dev, "failed to remap kgq\n"); 6855 return r; 6856 } 6857 } 6858 6859 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 6860 } 6861 6862 static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring) 6863 { 6864 6865 struct amdgpu_device *adev = ring->adev; 6866 uint32_t reset_pipe = 0, clean_pipe = 0; 6867 int r; 6868 6869 if (!gfx_v11_pipe_reset_support(adev)) 6870 return -EOPNOTSUPP; 6871 6872 gfx_v11_0_set_safe_mode(adev, 0); 6873 mutex_lock(&adev->srbm_mutex); 6874 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6875 6876 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 6877 clean_pipe = reset_pipe; 6878 6879 if (adev->gfx.rs64_enable) { 6880 6881 switch (ring->pipe) { 6882 case 0: 6883 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6884 MEC_PIPE0_RESET, 1); 6885 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6886 MEC_PIPE0_RESET, 0); 6887 break; 6888 case 1: 6889 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6890 MEC_PIPE1_RESET, 1); 6891 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6892 MEC_PIPE1_RESET, 0); 6893 break; 6894 case 2: 6895 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6896 MEC_PIPE2_RESET, 1); 6897 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6898 MEC_PIPE2_RESET, 0); 6899 break; 6900 case 3: 6901 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 6902 MEC_PIPE3_RESET, 1); 6903 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 6904 MEC_PIPE3_RESET, 0); 6905 break; 6906 default: 6907 break; 6908 } 6909 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 6910 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 6911 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 6912 RS64_FW_UC_START_ADDR_LO; 6913 } else { 6914 if (ring->me == 1) { 6915 switch (ring->pipe) { 6916 case 0: 6917 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6918 MEC_ME1_PIPE0_RESET, 1); 6919 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6920 MEC_ME1_PIPE0_RESET, 0); 6921 break; 6922 case 1: 6923 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6924 MEC_ME1_PIPE1_RESET, 1); 6925 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6926 MEC_ME1_PIPE1_RESET, 0); 6927 break; 6928 case 2: 6929 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6930 MEC_ME1_PIPE2_RESET, 1); 6931 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6932 MEC_ME1_PIPE2_RESET, 0); 6933 break; 6934 case 3: 6935 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6936 MEC_ME1_PIPE3_RESET, 1); 6937 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6938 MEC_ME1_PIPE3_RESET, 0); 6939 break; 6940 default: 6941 break; 6942 } 6943 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 6944 } else { 6945 switch (ring->pipe) { 6946 case 0: 6947 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6948 MEC_ME2_PIPE0_RESET, 1); 6949 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6950 MEC_ME2_PIPE0_RESET, 0); 6951 break; 6952 case 1: 6953 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6954 MEC_ME2_PIPE1_RESET, 1); 6955 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6956 MEC_ME2_PIPE1_RESET, 0); 6957 break; 6958 case 2: 6959 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6960 MEC_ME2_PIPE2_RESET, 1); 6961 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6962 MEC_ME2_PIPE2_RESET, 0); 6963 break; 6964 case 3: 6965 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 6966 MEC_ME2_PIPE3_RESET, 1); 6967 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 6968 MEC_ME2_PIPE3_RESET, 0); 6969 break; 6970 default: 6971 break; 6972 } 6973 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 6974 } 6975 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 6976 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 6977 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 6978 } 6979 6980 soc21_grbm_select(adev, 0, 0, 0, 0); 6981 mutex_unlock(&adev->srbm_mutex); 6982 gfx_v11_0_unset_safe_mode(adev, 0); 6983 6984 dev_info(adev->dev, "The ring %s pipe resets to MEC FW start PC: %s\n", ring->name, 6985 r == 0 ? "successfully" : "failed"); 6986 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 6987 * reset status relies on the compute ring test result. 6988 */ 6989 return 0; 6990 } 6991 6992 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, 6993 unsigned int vmid, 6994 struct amdgpu_fence *timedout_fence) 6995 { 6996 struct amdgpu_device *adev = ring->adev; 6997 int r = 0; 6998 6999 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 7000 7001 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); 7002 if (r) { 7003 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 7004 r = gfx_v11_0_reset_compute_pipe(ring); 7005 if (r) 7006 return r; 7007 } 7008 7009 r = gfx_v11_0_kcq_init_queue(ring, true); 7010 if (r) { 7011 dev_err(adev->dev, "fail to init kcq\n"); 7012 return r; 7013 } 7014 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 7015 if (r) { 7016 dev_err(adev->dev, "failed to remap kcq\n"); 7017 return r; 7018 } 7019 7020 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 7021 } 7022 7023 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 7024 { 7025 struct amdgpu_device *adev = ip_block->adev; 7026 uint32_t i, j, k, reg, index = 0; 7027 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 7028 7029 if (!adev->gfx.ip_dump_core) 7030 return; 7031 7032 for (i = 0; i < reg_count; i++) 7033 drm_printf(p, "%-50s \t 0x%08x\n", 7034 gc_reg_list_11_0[i].reg_name, 7035 adev->gfx.ip_dump_core[i]); 7036 7037 /* print compute queue registers for all instances */ 7038 if (!adev->gfx.ip_dump_compute_queues) 7039 return; 7040 7041 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 7042 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 7043 adev->gfx.mec.num_mec, 7044 adev->gfx.mec.num_pipe_per_mec, 7045 adev->gfx.mec.num_queue_per_pipe); 7046 7047 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7048 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7049 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7050 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 7051 for (reg = 0; reg < reg_count; reg++) { 7052 if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP) 7053 drm_printf(p, "%-50s \t 0x%08x\n", 7054 "regCP_MEC_ME2_HEADER_DUMP", 7055 adev->gfx.ip_dump_compute_queues[index + reg]); 7056 else 7057 drm_printf(p, "%-50s \t 0x%08x\n", 7058 gc_cp_reg_list_11[reg].reg_name, 7059 adev->gfx.ip_dump_compute_queues[index + reg]); 7060 } 7061 index += reg_count; 7062 } 7063 } 7064 } 7065 7066 /* print gfx queue registers for all instances */ 7067 if (!adev->gfx.ip_dump_gfx_queues) 7068 return; 7069 7070 index = 0; 7071 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7072 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 7073 adev->gfx.me.num_me, 7074 adev->gfx.me.num_pipe_per_me, 7075 adev->gfx.me.num_queue_per_pipe); 7076 7077 for (i = 0; i < adev->gfx.me.num_me; i++) { 7078 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7079 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7080 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 7081 for (reg = 0; reg < reg_count; reg++) { 7082 drm_printf(p, "%-50s \t 0x%08x\n", 7083 gc_gfx_queue_reg_list_11[reg].reg_name, 7084 adev->gfx.ip_dump_gfx_queues[index + reg]); 7085 } 7086 index += reg_count; 7087 } 7088 } 7089 } 7090 } 7091 7092 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 7093 { 7094 struct amdgpu_device *adev = ip_block->adev; 7095 uint32_t i, j, k, reg, index = 0; 7096 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 7097 7098 if (!adev->gfx.ip_dump_core) 7099 return; 7100 7101 amdgpu_gfx_off_ctrl(adev, false); 7102 for (i = 0; i < reg_count; i++) 7103 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 7104 amdgpu_gfx_off_ctrl(adev, true); 7105 7106 /* dump compute queue registers for all instances */ 7107 if (!adev->gfx.ip_dump_compute_queues) 7108 return; 7109 7110 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 7111 amdgpu_gfx_off_ctrl(adev, false); 7112 mutex_lock(&adev->srbm_mutex); 7113 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 7114 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 7115 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 7116 /* ME0 is for GFX so start from 1 for CP */ 7117 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 7118 for (reg = 0; reg < reg_count; reg++) { 7119 if (i && 7120 gc_cp_reg_list_11[reg].reg_offset == 7121 regCP_MEC_ME1_HEADER_DUMP) 7122 adev->gfx.ip_dump_compute_queues[index + reg] = 7123 RREG32(SOC15_REG_OFFSET(GC, 0, 7124 regCP_MEC_ME2_HEADER_DUMP)); 7125 else 7126 adev->gfx.ip_dump_compute_queues[index + reg] = 7127 RREG32(SOC15_REG_ENTRY_OFFSET( 7128 gc_cp_reg_list_11[reg])); 7129 } 7130 index += reg_count; 7131 } 7132 } 7133 } 7134 soc21_grbm_select(adev, 0, 0, 0, 0); 7135 mutex_unlock(&adev->srbm_mutex); 7136 amdgpu_gfx_off_ctrl(adev, true); 7137 7138 /* dump gfx queue registers for all instances */ 7139 if (!adev->gfx.ip_dump_gfx_queues) 7140 return; 7141 7142 index = 0; 7143 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 7144 amdgpu_gfx_off_ctrl(adev, false); 7145 mutex_lock(&adev->srbm_mutex); 7146 for (i = 0; i < adev->gfx.me.num_me; i++) { 7147 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 7148 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 7149 soc21_grbm_select(adev, i, j, k, 0); 7150 7151 for (reg = 0; reg < reg_count; reg++) { 7152 adev->gfx.ip_dump_gfx_queues[index + reg] = 7153 RREG32(SOC15_REG_ENTRY_OFFSET( 7154 gc_gfx_queue_reg_list_11[reg])); 7155 } 7156 index += reg_count; 7157 } 7158 } 7159 } 7160 soc21_grbm_select(adev, 0, 0, 0, 0); 7161 mutex_unlock(&adev->srbm_mutex); 7162 amdgpu_gfx_off_ctrl(adev, true); 7163 } 7164 7165 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 7166 { 7167 /* Emit the cleaner shader */ 7168 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 7169 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 7170 } 7171 7172 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 7173 { 7174 amdgpu_gfx_profile_ring_begin_use(ring); 7175 7176 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 7177 } 7178 7179 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 7180 { 7181 amdgpu_gfx_profile_ring_end_use(ring); 7182 7183 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 7184 } 7185 7186 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 7187 .name = "gfx_v11_0", 7188 .early_init = gfx_v11_0_early_init, 7189 .late_init = gfx_v11_0_late_init, 7190 .sw_init = gfx_v11_0_sw_init, 7191 .sw_fini = gfx_v11_0_sw_fini, 7192 .hw_init = gfx_v11_0_hw_init, 7193 .hw_fini = gfx_v11_0_hw_fini, 7194 .suspend = gfx_v11_0_suspend, 7195 .resume = gfx_v11_0_resume, 7196 .is_idle = gfx_v11_0_is_idle, 7197 .wait_for_idle = gfx_v11_0_wait_for_idle, 7198 .soft_reset = gfx_v11_0_soft_reset, 7199 .check_soft_reset = gfx_v11_0_check_soft_reset, 7200 .post_soft_reset = gfx_v11_0_post_soft_reset, 7201 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 7202 .set_powergating_state = gfx_v11_0_set_powergating_state, 7203 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 7204 .dump_ip_state = gfx_v11_ip_dump, 7205 .print_ip_state = gfx_v11_ip_print, 7206 }; 7207 7208 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 7209 .type = AMDGPU_RING_TYPE_GFX, 7210 .align_mask = 0xff, 7211 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7212 .support_64bit_ptrs = true, 7213 .secure_submission_supported = true, 7214 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 7215 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 7216 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 7217 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 7218 5 + /* update_spm_vmid */ 7219 5 + /* COND_EXEC */ 7220 22 + /* SET_Q_PREEMPTION_MODE */ 7221 7 + /* PIPELINE_SYNC */ 7222 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7223 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7224 4 + /* VM_FLUSH */ 7225 8 + /* FENCE for VM_FLUSH */ 7226 20 + /* GDS switch */ 7227 5 + /* COND_EXEC */ 7228 7 + /* HDP_flush */ 7229 4 + /* VGT_flush */ 7230 31 + /* DE_META */ 7231 3 + /* CNTX_CTRL */ 7232 5 + /* HDP_INVL */ 7233 22 + /* SET_Q_PREEMPTION_MODE */ 7234 8 + 8 + /* FENCE x2 */ 7235 8 + /* gfx_v11_0_emit_mem_sync */ 7236 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7237 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 7238 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 7239 .emit_fence = gfx_v11_0_ring_emit_fence, 7240 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7241 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7242 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7243 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7244 .test_ring = gfx_v11_0_ring_test_ring, 7245 .test_ib = gfx_v11_0_ring_test_ib, 7246 .insert_nop = gfx_v11_ring_insert_nop, 7247 .pad_ib = amdgpu_ring_generic_pad_ib, 7248 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 7249 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 7250 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 7251 .preempt_ib = gfx_v11_0_ring_preempt_ib, 7252 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 7253 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7254 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7255 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7256 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7257 .reset = gfx_v11_0_reset_kgq, 7258 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7259 .begin_use = gfx_v11_0_ring_begin_use, 7260 .end_use = gfx_v11_0_ring_end_use, 7261 }; 7262 7263 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 7264 .type = AMDGPU_RING_TYPE_COMPUTE, 7265 .align_mask = 0xff, 7266 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7267 .support_64bit_ptrs = true, 7268 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7269 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7270 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7271 .emit_frame_size = 7272 5 + /* update_spm_vmid */ 7273 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7274 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7275 5 + /* hdp invalidate */ 7276 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7277 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7278 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7279 2 + /* gfx_v11_0_ring_emit_vm_flush */ 7280 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 7281 8 + /* gfx_v11_0_emit_mem_sync */ 7282 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 7283 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7284 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7285 .emit_fence = gfx_v11_0_ring_emit_fence, 7286 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 7287 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 7288 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 7289 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7290 .test_ring = gfx_v11_0_ring_test_ring, 7291 .test_ib = gfx_v11_0_ring_test_ib, 7292 .insert_nop = gfx_v11_ring_insert_nop, 7293 .pad_ib = amdgpu_ring_generic_pad_ib, 7294 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7295 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7296 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7297 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 7298 .reset = gfx_v11_0_reset_kcq, 7299 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 7300 .begin_use = gfx_v11_0_ring_begin_use, 7301 .end_use = gfx_v11_0_ring_end_use, 7302 }; 7303 7304 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 7305 .type = AMDGPU_RING_TYPE_KIQ, 7306 .align_mask = 0xff, 7307 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 7308 .support_64bit_ptrs = true, 7309 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 7310 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 7311 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 7312 .emit_frame_size = 7313 20 + /* gfx_v11_0_ring_emit_gds_switch */ 7314 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 7315 5 + /*hdp invalidate */ 7316 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 7317 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 7318 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 7319 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 7320 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 7321 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 7322 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 7323 .test_ring = gfx_v11_0_ring_test_ring, 7324 .test_ib = gfx_v11_0_ring_test_ib, 7325 .insert_nop = amdgpu_ring_insert_nop, 7326 .pad_ib = amdgpu_ring_generic_pad_ib, 7327 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7328 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7329 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7330 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7331 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 7332 }; 7333 7334 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7335 { 7336 int i; 7337 7338 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7339 7340 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7341 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7342 7343 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7344 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7345 } 7346 7347 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7348 .set = gfx_v11_0_set_eop_interrupt_state, 7349 .process = gfx_v11_0_eop_irq, 7350 }; 7351 7352 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7353 .set = gfx_v11_0_set_priv_reg_fault_state, 7354 .process = gfx_v11_0_priv_reg_irq, 7355 }; 7356 7357 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7358 .set = gfx_v11_0_set_bad_op_fault_state, 7359 .process = gfx_v11_0_bad_op_irq, 7360 }; 7361 7362 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7363 .set = gfx_v11_0_set_priv_inst_fault_state, 7364 .process = gfx_v11_0_priv_inst_irq, 7365 }; 7366 7367 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7368 .process = gfx_v11_0_rlc_gc_fed_irq, 7369 }; 7370 7371 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7372 { 7373 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7374 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7375 7376 adev->gfx.priv_reg_irq.num_types = 1; 7377 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7378 7379 adev->gfx.bad_op_irq.num_types = 1; 7380 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7381 7382 adev->gfx.priv_inst_irq.num_types = 1; 7383 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7384 7385 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7386 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7387 7388 } 7389 7390 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7391 { 7392 if (adev->flags & AMD_IS_APU) 7393 adev->gfx.imu.mode = MISSION_MODE; 7394 else 7395 adev->gfx.imu.mode = DEBUG_MODE; 7396 7397 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7398 } 7399 7400 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7401 { 7402 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7403 } 7404 7405 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7406 { 7407 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7408 adev->gfx.config.max_sh_per_se * 7409 adev->gfx.config.max_shader_engines; 7410 7411 adev->gds.gds_size = 0x1000; 7412 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7413 adev->gds.gws_size = 64; 7414 adev->gds.oa_size = 16; 7415 } 7416 7417 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7418 { 7419 /* set gfx eng mqd */ 7420 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7421 sizeof(struct v11_gfx_mqd); 7422 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7423 gfx_v11_0_gfx_mqd_init; 7424 /* set compute eng mqd */ 7425 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7426 sizeof(struct v11_compute_mqd); 7427 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7428 gfx_v11_0_compute_mqd_init; 7429 } 7430 7431 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7432 u32 bitmap) 7433 { 7434 u32 data; 7435 7436 if (!bitmap) 7437 return; 7438 7439 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7440 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7441 7442 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7443 } 7444 7445 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7446 { 7447 u32 data, wgp_bitmask; 7448 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7449 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7450 7451 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7452 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7453 7454 wgp_bitmask = 7455 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7456 7457 return (~data) & wgp_bitmask; 7458 } 7459 7460 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7461 { 7462 u32 wgp_idx, wgp_active_bitmap; 7463 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7464 7465 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7466 cu_active_bitmap = 0; 7467 7468 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7469 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7470 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7471 if (wgp_active_bitmap & (1 << wgp_idx)) 7472 cu_active_bitmap |= cu_bitmap_per_wgp; 7473 } 7474 7475 return cu_active_bitmap; 7476 } 7477 7478 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7479 struct amdgpu_cu_info *cu_info) 7480 { 7481 int i, j, k, counter, active_cu_number = 0; 7482 u32 mask, bitmap; 7483 unsigned disable_masks[8 * 2]; 7484 7485 if (!adev || !cu_info) 7486 return -EINVAL; 7487 7488 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 7489 7490 mutex_lock(&adev->grbm_idx_mutex); 7491 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7493 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7494 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7495 continue; 7496 mask = 1; 7497 counter = 0; 7498 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7499 if (i < 8 && j < 2) 7500 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7501 adev, disable_masks[i * 2 + j]); 7502 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7503 7504 /** 7505 * GFX11 could support more than 4 SEs, while the bitmap 7506 * in cu_info struct is 4x4 and ioctl interface struct 7507 * drm_amdgpu_info_device should keep stable. 7508 * So we use last two columns of bitmap to store cu mask for 7509 * SEs 4 to 7, the layout of the bitmap is as below: 7510 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7511 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7512 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7513 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7514 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7515 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7516 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7517 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7518 */ 7519 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7520 7521 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7522 if (bitmap & mask) 7523 counter++; 7524 7525 mask <<= 1; 7526 } 7527 active_cu_number += counter; 7528 } 7529 } 7530 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7531 mutex_unlock(&adev->grbm_idx_mutex); 7532 7533 cu_info->number = active_cu_number; 7534 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7535 7536 return 0; 7537 } 7538 7539 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7540 { 7541 .type = AMD_IP_BLOCK_TYPE_GFX, 7542 .major = 11, 7543 .minor = 0, 7544 .rev = 0, 7545 .funcs = &gfx_v11_0_ip_funcs, 7546 }; 7547