1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 2 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 #define regPC_CONFIG_CNTL_1 0x194d 64 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 96 97 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 98 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 99 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 100 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 131 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 132 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 133 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 134 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 135 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 136 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 137 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 138 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 139 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 140 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 141 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 142 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 143 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 144 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 145 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 155 /* cp header registers */ 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 160 /* SE status registers */ 161 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 162 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 163 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 164 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 165 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 166 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 167 }; 168 169 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 170 /* compute registers */ 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 210 }; 211 212 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 213 /* gfx queue registers */ 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 239 }; 240 241 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 242 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 243 }; 244 245 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 246 { 247 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 256 }; 257 258 #define DEFAULT_SH_MEM_CONFIG \ 259 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 260 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 261 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 262 263 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 264 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 265 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 266 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 267 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 268 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 269 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 270 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 271 struct amdgpu_cu_info *cu_info); 272 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 273 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 274 u32 sh_num, u32 instance, int xcc_id); 275 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 276 277 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 278 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 279 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 280 uint32_t val); 281 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 282 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 283 uint16_t pasid, uint32_t flush_type, 284 bool all_hub, uint8_t dst_sel); 285 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 286 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 287 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 288 bool enable); 289 290 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 291 { 292 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 293 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 294 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 295 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 296 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 297 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 298 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 299 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 301 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 302 } 303 304 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 305 struct amdgpu_ring *ring) 306 { 307 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 308 uint64_t wptr_addr = ring->wptr_gpu_addr; 309 uint32_t me = 0, eng_sel = 0; 310 311 switch (ring->funcs->type) { 312 case AMDGPU_RING_TYPE_COMPUTE: 313 me = 1; 314 eng_sel = 0; 315 break; 316 case AMDGPU_RING_TYPE_GFX: 317 me = 0; 318 eng_sel = 4; 319 break; 320 case AMDGPU_RING_TYPE_MES: 321 me = 2; 322 eng_sel = 5; 323 break; 324 default: 325 WARN_ON(1); 326 } 327 328 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 329 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 330 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 331 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 332 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 333 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 334 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 335 PACKET3_MAP_QUEUES_ME((me)) | 336 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 337 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 338 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 339 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 340 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 341 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 345 } 346 347 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 348 struct amdgpu_ring *ring, 349 enum amdgpu_unmap_queues_action action, 350 u64 gpu_addr, u64 seq) 351 { 352 struct amdgpu_device *adev = kiq_ring->adev; 353 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 354 355 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 356 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 357 return; 358 } 359 360 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 361 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 362 PACKET3_UNMAP_QUEUES_ACTION(action) | 363 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 364 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 365 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 366 amdgpu_ring_write(kiq_ring, 367 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 368 369 if (action == PREEMPT_QUEUES_NO_UNMAP) { 370 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 371 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 372 amdgpu_ring_write(kiq_ring, seq); 373 } else { 374 amdgpu_ring_write(kiq_ring, 0); 375 amdgpu_ring_write(kiq_ring, 0); 376 amdgpu_ring_write(kiq_ring, 0); 377 } 378 } 379 380 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 381 struct amdgpu_ring *ring, 382 u64 addr, 383 u64 seq) 384 { 385 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 386 387 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 388 amdgpu_ring_write(kiq_ring, 389 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 390 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 391 PACKET3_QUERY_STATUS_COMMAND(2)); 392 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 393 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 394 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 395 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 396 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 397 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 398 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 399 } 400 401 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 402 uint16_t pasid, uint32_t flush_type, 403 bool all_hub) 404 { 405 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 406 } 407 408 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 409 .kiq_set_resources = gfx11_kiq_set_resources, 410 .kiq_map_queues = gfx11_kiq_map_queues, 411 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 412 .kiq_query_status = gfx11_kiq_query_status, 413 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 414 .set_resources_size = 8, 415 .map_queues_size = 7, 416 .unmap_queues_size = 6, 417 .query_status_size = 7, 418 .invalidate_tlbs_size = 2, 419 }; 420 421 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 422 { 423 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 424 } 425 426 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 427 { 428 if (amdgpu_sriov_vf(adev)) 429 return; 430 431 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 432 case IP_VERSION(11, 0, 1): 433 case IP_VERSION(11, 0, 4): 434 soc15_program_register_sequence(adev, 435 golden_settings_gc_11_0_1, 436 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 437 break; 438 default: 439 break; 440 } 441 soc15_program_register_sequence(adev, 442 golden_settings_gc_11_0, 443 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 444 445 } 446 447 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 448 bool wc, uint32_t reg, uint32_t val) 449 { 450 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 451 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 452 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 453 amdgpu_ring_write(ring, reg); 454 amdgpu_ring_write(ring, 0); 455 amdgpu_ring_write(ring, val); 456 } 457 458 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 459 int mem_space, int opt, uint32_t addr0, 460 uint32_t addr1, uint32_t ref, uint32_t mask, 461 uint32_t inv) 462 { 463 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 464 amdgpu_ring_write(ring, 465 /* memory (1) or register (0) */ 466 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 467 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 468 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 469 WAIT_REG_MEM_ENGINE(eng_sel))); 470 471 if (mem_space) 472 BUG_ON(addr0 & 0x3); /* Dword align */ 473 amdgpu_ring_write(ring, addr0); 474 amdgpu_ring_write(ring, addr1); 475 amdgpu_ring_write(ring, ref); 476 amdgpu_ring_write(ring, mask); 477 amdgpu_ring_write(ring, inv); /* poll interval */ 478 } 479 480 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 481 { 482 struct amdgpu_device *adev = ring->adev; 483 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 484 uint32_t tmp = 0; 485 unsigned i; 486 int r; 487 488 WREG32(scratch, 0xCAFEDEAD); 489 r = amdgpu_ring_alloc(ring, 5); 490 if (r) { 491 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 492 ring->idx, r); 493 return r; 494 } 495 496 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 497 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 498 } else { 499 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 500 amdgpu_ring_write(ring, scratch - 501 PACKET3_SET_UCONFIG_REG_START); 502 amdgpu_ring_write(ring, 0xDEADBEEF); 503 } 504 amdgpu_ring_commit(ring); 505 506 for (i = 0; i < adev->usec_timeout; i++) { 507 tmp = RREG32(scratch); 508 if (tmp == 0xDEADBEEF) 509 break; 510 if (amdgpu_emu_mode == 1) 511 msleep(1); 512 else 513 udelay(1); 514 } 515 516 if (i >= adev->usec_timeout) 517 r = -ETIMEDOUT; 518 return r; 519 } 520 521 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 522 { 523 struct amdgpu_device *adev = ring->adev; 524 struct amdgpu_ib ib; 525 struct dma_fence *f = NULL; 526 unsigned index; 527 uint64_t gpu_addr; 528 volatile uint32_t *cpu_ptr; 529 long r; 530 531 /* MES KIQ fw hasn't indirect buffer support for now */ 532 if (adev->enable_mes_kiq && 533 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 534 return 0; 535 536 memset(&ib, 0, sizeof(ib)); 537 538 if (ring->is_mes_queue) { 539 uint32_t padding, offset; 540 541 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 542 padding = amdgpu_mes_ctx_get_offs(ring, 543 AMDGPU_MES_CTX_PADDING_OFFS); 544 545 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 546 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 547 548 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 549 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 550 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 551 } else { 552 r = amdgpu_device_wb_get(adev, &index); 553 if (r) 554 return r; 555 556 gpu_addr = adev->wb.gpu_addr + (index * 4); 557 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 558 cpu_ptr = &adev->wb.wb[index]; 559 560 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 561 if (r) { 562 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 563 goto err1; 564 } 565 } 566 567 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 568 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 569 ib.ptr[2] = lower_32_bits(gpu_addr); 570 ib.ptr[3] = upper_32_bits(gpu_addr); 571 ib.ptr[4] = 0xDEADBEEF; 572 ib.length_dw = 5; 573 574 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 575 if (r) 576 goto err2; 577 578 r = dma_fence_wait_timeout(f, false, timeout); 579 if (r == 0) { 580 r = -ETIMEDOUT; 581 goto err2; 582 } else if (r < 0) { 583 goto err2; 584 } 585 586 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 587 r = 0; 588 else 589 r = -EINVAL; 590 err2: 591 if (!ring->is_mes_queue) 592 amdgpu_ib_free(adev, &ib, NULL); 593 dma_fence_put(f); 594 err1: 595 if (!ring->is_mes_queue) 596 amdgpu_device_wb_free(adev, index); 597 return r; 598 } 599 600 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 601 { 602 amdgpu_ucode_release(&adev->gfx.pfp_fw); 603 amdgpu_ucode_release(&adev->gfx.me_fw); 604 amdgpu_ucode_release(&adev->gfx.rlc_fw); 605 amdgpu_ucode_release(&adev->gfx.mec_fw); 606 607 kfree(adev->gfx.rlc.register_list_format); 608 } 609 610 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 611 { 612 const struct psp_firmware_header_v1_0 *toc_hdr; 613 int err = 0; 614 char fw_name[40]; 615 616 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 617 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 618 if (err) 619 goto out; 620 621 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 622 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 623 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 624 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 625 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 626 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 627 return 0; 628 out: 629 amdgpu_ucode_release(&adev->psp.toc_fw); 630 return err; 631 } 632 633 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 634 { 635 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 636 case IP_VERSION(11, 0, 0): 637 case IP_VERSION(11, 0, 2): 638 case IP_VERSION(11, 0, 3): 639 if ((adev->gfx.me_fw_version >= 1505) && 640 (adev->gfx.pfp_fw_version >= 1600) && 641 (adev->gfx.mec_fw_version >= 512)) { 642 if (amdgpu_sriov_vf(adev)) 643 adev->gfx.cp_gfx_shadow = true; 644 else 645 adev->gfx.cp_gfx_shadow = false; 646 } 647 break; 648 default: 649 adev->gfx.cp_gfx_shadow = false; 650 break; 651 } 652 } 653 654 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 655 { 656 char fw_name[40]; 657 char ucode_prefix[25]; 658 int err; 659 const struct rlc_firmware_header_v2_0 *rlc_hdr; 660 uint16_t version_major; 661 uint16_t version_minor; 662 663 DRM_DEBUG("\n"); 664 665 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 666 667 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 668 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 669 if (err) 670 goto out; 671 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 672 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 673 (union amdgpu_firmware_header *) 674 adev->gfx.pfp_fw->data, 2, 0); 675 if (adev->gfx.rs64_enable) { 676 dev_info(adev->dev, "CP RS64 enable\n"); 677 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 678 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 679 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 680 } else { 681 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 682 } 683 684 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 685 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 686 if (err) 687 goto out; 688 if (adev->gfx.rs64_enable) { 689 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 690 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 691 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 692 } else { 693 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 694 } 695 696 if (!amdgpu_sriov_vf(adev)) { 697 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 698 adev->pdev->revision == 0xCE) 699 snprintf(fw_name, sizeof(fw_name), "amdgpu/gc_11_0_0_rlc_1.bin"); 700 else 701 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 702 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 703 if (err) 704 goto out; 705 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 706 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 707 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 708 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 709 if (err) 710 goto out; 711 } 712 713 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 714 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 715 if (err) 716 goto out; 717 if (adev->gfx.rs64_enable) { 718 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 719 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 720 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 721 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 722 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 723 } else { 724 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 725 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 726 } 727 728 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 729 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 730 731 /* only one MEC for gfx 11.0.0. */ 732 adev->gfx.mec2_fw = NULL; 733 734 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 735 736 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 737 err = adev->gfx.imu.funcs->init_microcode(adev); 738 if (err) 739 DRM_ERROR("Failed to init imu firmware!\n"); 740 return err; 741 } 742 743 out: 744 if (err) { 745 amdgpu_ucode_release(&adev->gfx.pfp_fw); 746 amdgpu_ucode_release(&adev->gfx.me_fw); 747 amdgpu_ucode_release(&adev->gfx.rlc_fw); 748 amdgpu_ucode_release(&adev->gfx.mec_fw); 749 } 750 751 return err; 752 } 753 754 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 755 { 756 u32 count = 0; 757 const struct cs_section_def *sect = NULL; 758 const struct cs_extent_def *ext = NULL; 759 760 /* begin clear state */ 761 count += 2; 762 /* context control state */ 763 count += 3; 764 765 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 766 for (ext = sect->section; ext->extent != NULL; ++ext) { 767 if (sect->id == SECT_CONTEXT) 768 count += 2 + ext->reg_count; 769 else 770 return 0; 771 } 772 } 773 774 /* set PA_SC_TILE_STEERING_OVERRIDE */ 775 count += 3; 776 /* end clear state */ 777 count += 2; 778 /* clear state */ 779 count += 2; 780 781 return count; 782 } 783 784 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 785 volatile u32 *buffer) 786 { 787 u32 count = 0, i; 788 const struct cs_section_def *sect = NULL; 789 const struct cs_extent_def *ext = NULL; 790 int ctx_reg_offset; 791 792 if (adev->gfx.rlc.cs_data == NULL) 793 return; 794 if (buffer == NULL) 795 return; 796 797 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 798 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 799 800 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 801 buffer[count++] = cpu_to_le32(0x80000000); 802 buffer[count++] = cpu_to_le32(0x80000000); 803 804 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 805 for (ext = sect->section; ext->extent != NULL; ++ext) { 806 if (sect->id == SECT_CONTEXT) { 807 buffer[count++] = 808 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 809 buffer[count++] = cpu_to_le32(ext->reg_index - 810 PACKET3_SET_CONTEXT_REG_START); 811 for (i = 0; i < ext->reg_count; i++) 812 buffer[count++] = cpu_to_le32(ext->extent[i]); 813 } else { 814 return; 815 } 816 } 817 } 818 819 ctx_reg_offset = 820 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 821 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 822 buffer[count++] = cpu_to_le32(ctx_reg_offset); 823 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 824 825 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 826 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 827 828 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 829 buffer[count++] = cpu_to_le32(0); 830 } 831 832 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 833 { 834 /* clear state block */ 835 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 836 &adev->gfx.rlc.clear_state_gpu_addr, 837 (void **)&adev->gfx.rlc.cs_ptr); 838 839 /* jump table block */ 840 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 841 &adev->gfx.rlc.cp_table_gpu_addr, 842 (void **)&adev->gfx.rlc.cp_table_ptr); 843 } 844 845 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 846 { 847 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 848 849 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 850 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 851 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 852 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 853 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 854 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 855 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 856 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 857 adev->gfx.rlc.rlcg_reg_access_supported = true; 858 } 859 860 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 861 { 862 const struct cs_section_def *cs_data; 863 int r; 864 865 adev->gfx.rlc.cs_data = gfx11_cs_data; 866 867 cs_data = adev->gfx.rlc.cs_data; 868 869 if (cs_data) { 870 /* init clear state block */ 871 r = amdgpu_gfx_rlc_init_csb(adev); 872 if (r) 873 return r; 874 } 875 876 /* init spm vmid with 0xf */ 877 if (adev->gfx.rlc.funcs->update_spm_vmid) 878 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 879 880 return 0; 881 } 882 883 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 884 { 885 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 886 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 887 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 888 } 889 890 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 891 { 892 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 893 894 amdgpu_gfx_graphics_queue_acquire(adev); 895 } 896 897 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 898 { 899 int r; 900 u32 *hpd; 901 size_t mec_hpd_size; 902 903 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 904 905 /* take ownership of the relevant compute queues */ 906 amdgpu_gfx_compute_queue_acquire(adev); 907 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 908 909 if (mec_hpd_size) { 910 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 911 AMDGPU_GEM_DOMAIN_GTT, 912 &adev->gfx.mec.hpd_eop_obj, 913 &adev->gfx.mec.hpd_eop_gpu_addr, 914 (void **)&hpd); 915 if (r) { 916 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 917 gfx_v11_0_mec_fini(adev); 918 return r; 919 } 920 921 memset(hpd, 0, mec_hpd_size); 922 923 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 924 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 925 } 926 927 return 0; 928 } 929 930 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 931 { 932 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 933 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 934 (address << SQ_IND_INDEX__INDEX__SHIFT)); 935 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 936 } 937 938 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 939 uint32_t thread, uint32_t regno, 940 uint32_t num, uint32_t *out) 941 { 942 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 943 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 944 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 945 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 946 (SQ_IND_INDEX__AUTO_INCR_MASK)); 947 while (num--) 948 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 949 } 950 951 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 952 { 953 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 954 * field when performing a select_se_sh so it should be 955 * zero here */ 956 WARN_ON(simd != 0); 957 958 /* type 3 wave data */ 959 dst[(*no_fields)++] = 3; 960 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 961 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 962 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 963 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 964 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 965 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 966 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 967 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 968 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 969 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 970 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 971 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 972 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 973 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 974 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 975 } 976 977 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 978 uint32_t wave, uint32_t start, 979 uint32_t size, uint32_t *dst) 980 { 981 WARN_ON(simd != 0); 982 983 wave_read_regs( 984 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 985 dst); 986 } 987 988 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 989 uint32_t wave, uint32_t thread, 990 uint32_t start, uint32_t size, 991 uint32_t *dst) 992 { 993 wave_read_regs( 994 adev, wave, thread, 995 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 996 } 997 998 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 999 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1000 { 1001 soc21_grbm_select(adev, me, pipe, q, vm); 1002 } 1003 1004 /* all sizes are in bytes */ 1005 #define MQD_SHADOW_BASE_SIZE 73728 1006 #define MQD_SHADOW_BASE_ALIGNMENT 256 1007 #define MQD_FWWORKAREA_SIZE 484 1008 #define MQD_FWWORKAREA_ALIGNMENT 256 1009 1010 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1011 struct amdgpu_gfx_shadow_info *shadow_info) 1012 { 1013 if (adev->gfx.cp_gfx_shadow) { 1014 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1015 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1016 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1017 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1018 return 0; 1019 } else { 1020 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1021 return -ENOTSUPP; 1022 } 1023 } 1024 1025 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1026 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1027 .select_se_sh = &gfx_v11_0_select_se_sh, 1028 .read_wave_data = &gfx_v11_0_read_wave_data, 1029 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1030 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1031 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1032 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1033 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1034 }; 1035 1036 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1037 { 1038 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1039 case IP_VERSION(11, 0, 0): 1040 case IP_VERSION(11, 0, 2): 1041 adev->gfx.config.max_hw_contexts = 8; 1042 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1043 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1044 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1045 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1046 break; 1047 case IP_VERSION(11, 0, 3): 1048 adev->gfx.ras = &gfx_v11_0_3_ras; 1049 adev->gfx.config.max_hw_contexts = 8; 1050 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1051 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1052 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1053 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1054 break; 1055 case IP_VERSION(11, 0, 1): 1056 case IP_VERSION(11, 0, 4): 1057 case IP_VERSION(11, 5, 0): 1058 case IP_VERSION(11, 5, 1): 1059 adev->gfx.config.max_hw_contexts = 8; 1060 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1061 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1062 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1063 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1064 break; 1065 default: 1066 BUG(); 1067 break; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1074 int me, int pipe, int queue) 1075 { 1076 struct amdgpu_ring *ring; 1077 unsigned int irq_type; 1078 unsigned int hw_prio; 1079 1080 ring = &adev->gfx.gfx_ring[ring_id]; 1081 1082 ring->me = me; 1083 ring->pipe = pipe; 1084 ring->queue = queue; 1085 1086 ring->ring_obj = NULL; 1087 ring->use_doorbell = true; 1088 1089 if (!ring_id) 1090 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1091 else 1092 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1093 ring->vm_hub = AMDGPU_GFXHUB(0); 1094 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1095 1096 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1097 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1098 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1099 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1100 hw_prio, NULL); 1101 } 1102 1103 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1104 int mec, int pipe, int queue) 1105 { 1106 int r; 1107 unsigned irq_type; 1108 struct amdgpu_ring *ring; 1109 unsigned int hw_prio; 1110 1111 ring = &adev->gfx.compute_ring[ring_id]; 1112 1113 /* mec0 is me1 */ 1114 ring->me = mec + 1; 1115 ring->pipe = pipe; 1116 ring->queue = queue; 1117 1118 ring->ring_obj = NULL; 1119 ring->use_doorbell = true; 1120 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1121 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1122 + (ring_id * GFX11_MEC_HPD_SIZE); 1123 ring->vm_hub = AMDGPU_GFXHUB(0); 1124 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1125 1126 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1127 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1128 + ring->pipe; 1129 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1130 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1131 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1132 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1133 hw_prio, NULL); 1134 if (r) 1135 return r; 1136 1137 return 0; 1138 } 1139 1140 static struct { 1141 SOC21_FIRMWARE_ID id; 1142 unsigned int offset; 1143 unsigned int size; 1144 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1145 1146 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1147 { 1148 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1149 1150 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1151 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1152 rlc_autoload_info[ucode->id].id = ucode->id; 1153 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1154 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1155 1156 ucode++; 1157 } 1158 } 1159 1160 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1161 { 1162 uint32_t total_size = 0; 1163 SOC21_FIRMWARE_ID id; 1164 1165 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1166 1167 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1168 total_size += rlc_autoload_info[id].size; 1169 1170 /* In case the offset in rlc toc ucode is aligned */ 1171 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1172 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1173 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1174 1175 return total_size; 1176 } 1177 1178 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1179 { 1180 int r; 1181 uint32_t total_size; 1182 1183 total_size = gfx_v11_0_calc_toc_total_size(adev); 1184 1185 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1186 AMDGPU_GEM_DOMAIN_VRAM | 1187 AMDGPU_GEM_DOMAIN_GTT, 1188 &adev->gfx.rlc.rlc_autoload_bo, 1189 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1190 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1191 1192 if (r) { 1193 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1194 return r; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1201 SOC21_FIRMWARE_ID id, 1202 const void *fw_data, 1203 uint32_t fw_size, 1204 uint32_t *fw_autoload_mask) 1205 { 1206 uint32_t toc_offset; 1207 uint32_t toc_fw_size; 1208 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1209 1210 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1211 return; 1212 1213 toc_offset = rlc_autoload_info[id].offset; 1214 toc_fw_size = rlc_autoload_info[id].size; 1215 1216 if (fw_size == 0) 1217 fw_size = toc_fw_size; 1218 1219 if (fw_size > toc_fw_size) 1220 fw_size = toc_fw_size; 1221 1222 memcpy(ptr + toc_offset, fw_data, fw_size); 1223 1224 if (fw_size < toc_fw_size) 1225 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1226 1227 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1228 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1229 } 1230 1231 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1232 uint32_t *fw_autoload_mask) 1233 { 1234 void *data; 1235 uint32_t size; 1236 uint64_t *toc_ptr; 1237 1238 *(uint64_t *)fw_autoload_mask |= 0x1; 1239 1240 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1241 1242 data = adev->psp.toc.start_addr; 1243 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1244 1245 toc_ptr = (uint64_t *)data + size / 8 - 1; 1246 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1247 1248 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1249 data, size, fw_autoload_mask); 1250 } 1251 1252 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1253 uint32_t *fw_autoload_mask) 1254 { 1255 const __le32 *fw_data; 1256 uint32_t fw_size; 1257 const struct gfx_firmware_header_v1_0 *cp_hdr; 1258 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1259 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1260 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1261 uint16_t version_major, version_minor; 1262 1263 if (adev->gfx.rs64_enable) { 1264 /* pfp ucode */ 1265 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1266 adev->gfx.pfp_fw->data; 1267 /* instruction */ 1268 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1269 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1270 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1271 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1272 fw_data, fw_size, fw_autoload_mask); 1273 /* data */ 1274 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1275 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1276 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1277 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1278 fw_data, fw_size, fw_autoload_mask); 1279 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1280 fw_data, fw_size, fw_autoload_mask); 1281 /* me ucode */ 1282 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1283 adev->gfx.me_fw->data; 1284 /* instruction */ 1285 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1286 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1287 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1288 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1289 fw_data, fw_size, fw_autoload_mask); 1290 /* data */ 1291 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1292 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1293 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1294 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1295 fw_data, fw_size, fw_autoload_mask); 1296 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1297 fw_data, fw_size, fw_autoload_mask); 1298 /* mec ucode */ 1299 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1300 adev->gfx.mec_fw->data; 1301 /* instruction */ 1302 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1303 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1304 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1305 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1306 fw_data, fw_size, fw_autoload_mask); 1307 /* data */ 1308 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1309 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1310 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1311 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1312 fw_data, fw_size, fw_autoload_mask); 1313 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1314 fw_data, fw_size, fw_autoload_mask); 1315 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1316 fw_data, fw_size, fw_autoload_mask); 1317 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1318 fw_data, fw_size, fw_autoload_mask); 1319 } else { 1320 /* pfp ucode */ 1321 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1322 adev->gfx.pfp_fw->data; 1323 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1324 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1325 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1326 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1327 fw_data, fw_size, fw_autoload_mask); 1328 1329 /* me ucode */ 1330 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1331 adev->gfx.me_fw->data; 1332 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1333 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1334 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1335 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1336 fw_data, fw_size, fw_autoload_mask); 1337 1338 /* mec ucode */ 1339 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1340 adev->gfx.mec_fw->data; 1341 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1342 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1343 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1344 cp_hdr->jt_size * 4; 1345 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1346 fw_data, fw_size, fw_autoload_mask); 1347 } 1348 1349 /* rlc ucode */ 1350 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1351 adev->gfx.rlc_fw->data; 1352 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1353 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1354 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1355 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1356 fw_data, fw_size, fw_autoload_mask); 1357 1358 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1359 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1360 if (version_major == 2) { 1361 if (version_minor >= 2) { 1362 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1363 1364 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1365 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1366 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1367 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1368 fw_data, fw_size, fw_autoload_mask); 1369 1370 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1371 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1372 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1373 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1374 fw_data, fw_size, fw_autoload_mask); 1375 } 1376 } 1377 } 1378 1379 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1380 uint32_t *fw_autoload_mask) 1381 { 1382 const __le32 *fw_data; 1383 uint32_t fw_size; 1384 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1385 1386 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1387 adev->sdma.instance[0].fw->data; 1388 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1389 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1390 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1391 1392 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1393 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1394 1395 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1396 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1397 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1398 1399 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1400 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1401 } 1402 1403 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1404 uint32_t *fw_autoload_mask) 1405 { 1406 const __le32 *fw_data; 1407 unsigned fw_size; 1408 const struct mes_firmware_header_v1_0 *mes_hdr; 1409 int pipe, ucode_id, data_id; 1410 1411 for (pipe = 0; pipe < 2; pipe++) { 1412 if (pipe==0) { 1413 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1414 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1415 } else { 1416 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1417 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1418 } 1419 1420 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1421 adev->mes.fw[pipe]->data; 1422 1423 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1424 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1425 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1426 1427 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1428 ucode_id, fw_data, fw_size, fw_autoload_mask); 1429 1430 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1431 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1432 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1433 1434 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1435 data_id, fw_data, fw_size, fw_autoload_mask); 1436 } 1437 } 1438 1439 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1440 { 1441 uint32_t rlc_g_offset, rlc_g_size; 1442 uint64_t gpu_addr; 1443 uint32_t autoload_fw_id[2]; 1444 1445 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1446 1447 /* RLC autoload sequence 2: copy ucode */ 1448 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1449 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1450 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1451 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1452 1453 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1454 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1455 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1456 1457 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1458 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1459 1460 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1461 1462 /* RLC autoload sequence 3: load IMU fw */ 1463 if (adev->gfx.imu.funcs->load_microcode) 1464 adev->gfx.imu.funcs->load_microcode(adev); 1465 /* RLC autoload sequence 4 init IMU fw */ 1466 if (adev->gfx.imu.funcs->setup_imu) 1467 adev->gfx.imu.funcs->setup_imu(adev); 1468 if (adev->gfx.imu.funcs->start_imu) 1469 adev->gfx.imu.funcs->start_imu(adev); 1470 1471 /* RLC autoload sequence 5 disable gpa mode */ 1472 gfx_v11_0_disable_gpa_mode(adev); 1473 1474 return 0; 1475 } 1476 1477 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1478 { 1479 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1480 uint32_t *ptr; 1481 uint32_t inst; 1482 1483 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1484 if (ptr == NULL) { 1485 DRM_ERROR("Failed to allocate memory for IP Dump\n"); 1486 adev->gfx.ip_dump_core = NULL; 1487 } else { 1488 adev->gfx.ip_dump_core = ptr; 1489 } 1490 1491 /* Allocate memory for compute queue registers for all the instances */ 1492 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1493 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1494 adev->gfx.mec.num_queue_per_pipe; 1495 1496 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1497 if (ptr == NULL) { 1498 DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n"); 1499 adev->gfx.ip_dump_cp_queues = NULL; 1500 } else { 1501 adev->gfx.ip_dump_cp_queues = ptr; 1502 } 1503 1504 /* Allocate memory for gfx queue registers for all the instances */ 1505 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1506 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1507 adev->gfx.me.num_queue_per_pipe; 1508 1509 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1510 if (ptr == NULL) { 1511 DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n"); 1512 adev->gfx.ip_dump_gfx_queues = NULL; 1513 } else { 1514 adev->gfx.ip_dump_gfx_queues = ptr; 1515 } 1516 } 1517 1518 static int gfx_v11_0_sw_init(void *handle) 1519 { 1520 int i, j, k, r, ring_id = 0; 1521 int xcc_id = 0; 1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1523 1524 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1525 case IP_VERSION(11, 0, 0): 1526 case IP_VERSION(11, 0, 2): 1527 case IP_VERSION(11, 0, 3): 1528 adev->gfx.me.num_me = 1; 1529 adev->gfx.me.num_pipe_per_me = 2; 1530 adev->gfx.me.num_queue_per_pipe = 1; 1531 adev->gfx.mec.num_mec = 2; 1532 adev->gfx.mec.num_pipe_per_mec = 4; 1533 adev->gfx.mec.num_queue_per_pipe = 4; 1534 break; 1535 case IP_VERSION(11, 0, 1): 1536 case IP_VERSION(11, 0, 4): 1537 case IP_VERSION(11, 5, 0): 1538 case IP_VERSION(11, 5, 1): 1539 adev->gfx.me.num_me = 1; 1540 adev->gfx.me.num_pipe_per_me = 2; 1541 adev->gfx.me.num_queue_per_pipe = 1; 1542 adev->gfx.mec.num_mec = 1; 1543 adev->gfx.mec.num_pipe_per_mec = 4; 1544 adev->gfx.mec.num_queue_per_pipe = 4; 1545 break; 1546 default: 1547 adev->gfx.me.num_me = 1; 1548 adev->gfx.me.num_pipe_per_me = 1; 1549 adev->gfx.me.num_queue_per_pipe = 1; 1550 adev->gfx.mec.num_mec = 1; 1551 adev->gfx.mec.num_pipe_per_mec = 4; 1552 adev->gfx.mec.num_queue_per_pipe = 8; 1553 break; 1554 } 1555 1556 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1557 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1558 amdgpu_sriov_is_pp_one_vf(adev)) 1559 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1560 1561 /* EOP Event */ 1562 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1563 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1564 &adev->gfx.eop_irq); 1565 if (r) 1566 return r; 1567 1568 /* Privileged reg */ 1569 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1570 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1571 &adev->gfx.priv_reg_irq); 1572 if (r) 1573 return r; 1574 1575 /* Privileged inst */ 1576 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1577 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1578 &adev->gfx.priv_inst_irq); 1579 if (r) 1580 return r; 1581 1582 /* FED error */ 1583 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1584 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1585 &adev->gfx.rlc_gc_fed_irq); 1586 if (r) 1587 return r; 1588 1589 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1590 1591 gfx_v11_0_me_init(adev); 1592 1593 r = gfx_v11_0_rlc_init(adev); 1594 if (r) { 1595 DRM_ERROR("Failed to init rlc BOs!\n"); 1596 return r; 1597 } 1598 1599 r = gfx_v11_0_mec_init(adev); 1600 if (r) { 1601 DRM_ERROR("Failed to init MEC BOs!\n"); 1602 return r; 1603 } 1604 1605 /* set up the gfx ring */ 1606 for (i = 0; i < adev->gfx.me.num_me; i++) { 1607 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1608 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1609 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1610 continue; 1611 1612 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1613 i, k, j); 1614 if (r) 1615 return r; 1616 ring_id++; 1617 } 1618 } 1619 } 1620 1621 ring_id = 0; 1622 /* set up the compute queues - allocate horizontally across pipes */ 1623 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1624 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1625 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1626 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1627 k, j)) 1628 continue; 1629 1630 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1631 i, k, j); 1632 if (r) 1633 return r; 1634 1635 ring_id++; 1636 } 1637 } 1638 } 1639 1640 if (!adev->enable_mes_kiq) { 1641 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1642 if (r) { 1643 DRM_ERROR("Failed to init KIQ BOs!\n"); 1644 return r; 1645 } 1646 1647 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1648 if (r) 1649 return r; 1650 } 1651 1652 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1653 if (r) 1654 return r; 1655 1656 /* allocate visible FB for rlc auto-loading fw */ 1657 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1658 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1659 if (r) 1660 return r; 1661 } 1662 1663 r = gfx_v11_0_gpu_early_init(adev); 1664 if (r) 1665 return r; 1666 1667 if (amdgpu_gfx_ras_sw_init(adev)) { 1668 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1669 return -EINVAL; 1670 } 1671 1672 gfx_v11_0_alloc_ip_dump(adev); 1673 1674 return 0; 1675 } 1676 1677 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1678 { 1679 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1680 &adev->gfx.pfp.pfp_fw_gpu_addr, 1681 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1682 1683 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1684 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1685 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1686 } 1687 1688 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1689 { 1690 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1691 &adev->gfx.me.me_fw_gpu_addr, 1692 (void **)&adev->gfx.me.me_fw_ptr); 1693 1694 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1695 &adev->gfx.me.me_fw_data_gpu_addr, 1696 (void **)&adev->gfx.me.me_fw_data_ptr); 1697 } 1698 1699 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1700 { 1701 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1702 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1703 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1704 } 1705 1706 static int gfx_v11_0_sw_fini(void *handle) 1707 { 1708 int i; 1709 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1710 1711 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1712 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1713 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1714 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1715 1716 amdgpu_gfx_mqd_sw_fini(adev, 0); 1717 1718 if (!adev->enable_mes_kiq) { 1719 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1720 amdgpu_gfx_kiq_fini(adev, 0); 1721 } 1722 1723 gfx_v11_0_pfp_fini(adev); 1724 gfx_v11_0_me_fini(adev); 1725 gfx_v11_0_rlc_fini(adev); 1726 gfx_v11_0_mec_fini(adev); 1727 1728 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1729 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1730 1731 gfx_v11_0_free_microcode(adev); 1732 1733 kfree(adev->gfx.ip_dump_core); 1734 kfree(adev->gfx.ip_dump_cp_queues); 1735 kfree(adev->gfx.ip_dump_gfx_queues); 1736 1737 return 0; 1738 } 1739 1740 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1741 u32 sh_num, u32 instance, int xcc_id) 1742 { 1743 u32 data; 1744 1745 if (instance == 0xffffffff) 1746 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1747 INSTANCE_BROADCAST_WRITES, 1); 1748 else 1749 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1750 instance); 1751 1752 if (se_num == 0xffffffff) 1753 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1754 1); 1755 else 1756 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1757 1758 if (sh_num == 0xffffffff) 1759 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1760 1); 1761 else 1762 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1763 1764 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1765 } 1766 1767 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1768 { 1769 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1770 1771 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1772 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1773 CC_GC_SA_UNIT_DISABLE, 1774 SA_DISABLE); 1775 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1776 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1777 GC_USER_SA_UNIT_DISABLE, 1778 SA_DISABLE); 1779 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1780 adev->gfx.config.max_shader_engines); 1781 1782 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1783 } 1784 1785 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1786 { 1787 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1788 u32 rb_mask; 1789 1790 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1791 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1792 CC_RB_BACKEND_DISABLE, 1793 BACKEND_DISABLE); 1794 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1795 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1796 GC_USER_RB_BACKEND_DISABLE, 1797 BACKEND_DISABLE); 1798 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1799 adev->gfx.config.max_shader_engines); 1800 1801 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1802 } 1803 1804 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1805 { 1806 u32 rb_bitmap_width_per_sa; 1807 u32 max_sa; 1808 u32 active_sa_bitmap; 1809 u32 global_active_rb_bitmap; 1810 u32 active_rb_bitmap = 0; 1811 u32 i; 1812 1813 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1814 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1815 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1816 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1817 1818 /* generate active rb bitmap according to active sa bitmap */ 1819 max_sa = adev->gfx.config.max_shader_engines * 1820 adev->gfx.config.max_sh_per_se; 1821 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1822 adev->gfx.config.max_sh_per_se; 1823 for (i = 0; i < max_sa; i++) { 1824 if (active_sa_bitmap & (1 << i)) 1825 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1826 } 1827 1828 active_rb_bitmap &= global_active_rb_bitmap; 1829 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1830 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1831 } 1832 1833 #define DEFAULT_SH_MEM_BASES (0x6000) 1834 #define LDS_APP_BASE 0x1 1835 #define SCRATCH_APP_BASE 0x2 1836 1837 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1838 { 1839 int i; 1840 uint32_t sh_mem_bases; 1841 uint32_t data; 1842 1843 /* 1844 * Configure apertures: 1845 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1846 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1847 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1848 */ 1849 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1850 SCRATCH_APP_BASE; 1851 1852 mutex_lock(&adev->srbm_mutex); 1853 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1854 soc21_grbm_select(adev, 0, 0, 0, i); 1855 /* CP and shaders */ 1856 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1857 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1858 1859 /* Enable trap for each kfd vmid. */ 1860 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1861 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1862 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1863 } 1864 soc21_grbm_select(adev, 0, 0, 0, 0); 1865 mutex_unlock(&adev->srbm_mutex); 1866 1867 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1868 acccess. These should be enabled by FW for target VMIDs. */ 1869 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1870 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1871 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1872 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1873 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1874 } 1875 } 1876 1877 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1878 { 1879 int vmid; 1880 1881 /* 1882 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1883 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1884 * the driver can enable them for graphics. VMID0 should maintain 1885 * access so that HWS firmware can save/restore entries. 1886 */ 1887 for (vmid = 1; vmid < 16; vmid++) { 1888 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1889 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1890 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1891 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1892 } 1893 } 1894 1895 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1896 { 1897 /* TODO: harvest feature to be added later. */ 1898 } 1899 1900 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1901 { 1902 /* TCCs are global (not instanced). */ 1903 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1904 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1905 1906 adev->gfx.config.tcc_disabled_mask = 1907 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1908 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1909 } 1910 1911 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1912 { 1913 u32 tmp; 1914 int i; 1915 1916 if (!amdgpu_sriov_vf(adev)) 1917 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1918 1919 gfx_v11_0_setup_rb(adev); 1920 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1921 gfx_v11_0_get_tcc_info(adev); 1922 adev->gfx.config.pa_sc_tile_steering_override = 0; 1923 1924 /* Set whether texture coordinate truncation is conformant. */ 1925 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1926 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1927 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1928 1929 /* XXX SH_MEM regs */ 1930 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1931 mutex_lock(&adev->srbm_mutex); 1932 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1933 soc21_grbm_select(adev, 0, 0, 0, i); 1934 /* CP and shaders */ 1935 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1936 if (i != 0) { 1937 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1938 (adev->gmc.private_aperture_start >> 48)); 1939 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1940 (adev->gmc.shared_aperture_start >> 48)); 1941 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1942 } 1943 } 1944 soc21_grbm_select(adev, 0, 0, 0, 0); 1945 1946 mutex_unlock(&adev->srbm_mutex); 1947 1948 gfx_v11_0_init_compute_vmid(adev); 1949 gfx_v11_0_init_gds_vmid(adev); 1950 } 1951 1952 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1953 bool enable) 1954 { 1955 u32 tmp; 1956 1957 if (amdgpu_sriov_vf(adev)) 1958 return; 1959 1960 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1961 1962 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1963 enable ? 1 : 0); 1964 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1965 enable ? 1 : 0); 1966 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1967 enable ? 1 : 0); 1968 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1969 enable ? 1 : 0); 1970 1971 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1972 } 1973 1974 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1975 { 1976 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1977 1978 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1979 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1980 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1981 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1982 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1983 1984 return 0; 1985 } 1986 1987 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1988 { 1989 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1990 1991 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1992 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1993 } 1994 1995 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1996 { 1997 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1998 udelay(50); 1999 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2000 udelay(50); 2001 } 2002 2003 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2004 bool enable) 2005 { 2006 uint32_t rlc_pg_cntl; 2007 2008 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2009 2010 if (!enable) { 2011 /* RLC_PG_CNTL[23] = 0 (default) 2012 * RLC will wait for handshake acks with SMU 2013 * GFXOFF will be enabled 2014 * RLC_PG_CNTL[23] = 1 2015 * RLC will not issue any message to SMU 2016 * hence no handshake between SMU & RLC 2017 * GFXOFF will be disabled 2018 */ 2019 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2020 } else 2021 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2022 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2023 } 2024 2025 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2026 { 2027 /* TODO: enable rlc & smu handshake until smu 2028 * and gfxoff feature works as expected */ 2029 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2030 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2031 2032 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2033 udelay(50); 2034 } 2035 2036 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2037 { 2038 uint32_t tmp; 2039 2040 /* enable Save Restore Machine */ 2041 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2042 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2043 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2044 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2045 } 2046 2047 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2048 { 2049 const struct rlc_firmware_header_v2_0 *hdr; 2050 const __le32 *fw_data; 2051 unsigned i, fw_size; 2052 2053 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2054 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2055 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2056 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2057 2058 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2059 RLCG_UCODE_LOADING_START_ADDRESS); 2060 2061 for (i = 0; i < fw_size; i++) 2062 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2063 le32_to_cpup(fw_data++)); 2064 2065 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2066 } 2067 2068 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2069 { 2070 const struct rlc_firmware_header_v2_2 *hdr; 2071 const __le32 *fw_data; 2072 unsigned i, fw_size; 2073 u32 tmp; 2074 2075 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2076 2077 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2078 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2079 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2080 2081 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2082 2083 for (i = 0; i < fw_size; i++) { 2084 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2085 msleep(1); 2086 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2087 le32_to_cpup(fw_data++)); 2088 } 2089 2090 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2091 2092 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2093 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2094 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2095 2096 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2097 for (i = 0; i < fw_size; i++) { 2098 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2099 msleep(1); 2100 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2101 le32_to_cpup(fw_data++)); 2102 } 2103 2104 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2105 2106 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2107 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2108 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2109 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2110 } 2111 2112 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2113 { 2114 const struct rlc_firmware_header_v2_3 *hdr; 2115 const __le32 *fw_data; 2116 unsigned i, fw_size; 2117 u32 tmp; 2118 2119 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2120 2121 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2122 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2123 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2124 2125 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2126 2127 for (i = 0; i < fw_size; i++) { 2128 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2129 msleep(1); 2130 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2131 le32_to_cpup(fw_data++)); 2132 } 2133 2134 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2135 2136 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2137 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2138 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2139 2140 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2141 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2142 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2143 2144 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2145 2146 for (i = 0; i < fw_size; i++) { 2147 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2148 msleep(1); 2149 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2150 le32_to_cpup(fw_data++)); 2151 } 2152 2153 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2154 2155 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2156 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2157 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2158 } 2159 2160 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2161 { 2162 const struct rlc_firmware_header_v2_0 *hdr; 2163 uint16_t version_major; 2164 uint16_t version_minor; 2165 2166 if (!adev->gfx.rlc_fw) 2167 return -EINVAL; 2168 2169 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2170 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2171 2172 version_major = le16_to_cpu(hdr->header.header_version_major); 2173 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2174 2175 if (version_major == 2) { 2176 gfx_v11_0_load_rlcg_microcode(adev); 2177 if (amdgpu_dpm == 1) { 2178 if (version_minor >= 2) 2179 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2180 if (version_minor == 3) 2181 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2182 } 2183 2184 return 0; 2185 } 2186 2187 return -EINVAL; 2188 } 2189 2190 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2191 { 2192 int r; 2193 2194 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2195 gfx_v11_0_init_csb(adev); 2196 2197 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2198 gfx_v11_0_rlc_enable_srm(adev); 2199 } else { 2200 if (amdgpu_sriov_vf(adev)) { 2201 gfx_v11_0_init_csb(adev); 2202 return 0; 2203 } 2204 2205 adev->gfx.rlc.funcs->stop(adev); 2206 2207 /* disable CG */ 2208 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2209 2210 /* disable PG */ 2211 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2212 2213 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2214 /* legacy rlc firmware loading */ 2215 r = gfx_v11_0_rlc_load_microcode(adev); 2216 if (r) 2217 return r; 2218 } 2219 2220 gfx_v11_0_init_csb(adev); 2221 2222 adev->gfx.rlc.funcs->start(adev); 2223 } 2224 return 0; 2225 } 2226 2227 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2228 { 2229 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2230 uint32_t tmp; 2231 int i; 2232 2233 /* Trigger an invalidation of the L1 instruction caches */ 2234 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2235 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2236 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2237 2238 /* Wait for invalidation complete */ 2239 for (i = 0; i < usec_timeout; i++) { 2240 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2241 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2242 INVALIDATE_CACHE_COMPLETE)) 2243 break; 2244 udelay(1); 2245 } 2246 2247 if (i >= usec_timeout) { 2248 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2249 return -EINVAL; 2250 } 2251 2252 if (amdgpu_emu_mode == 1) 2253 adev->hdp.funcs->flush_hdp(adev, NULL); 2254 2255 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2256 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2257 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2258 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2259 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2260 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2261 2262 /* Program me ucode address into intruction cache address register */ 2263 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2264 lower_32_bits(addr) & 0xFFFFF000); 2265 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2266 upper_32_bits(addr)); 2267 2268 return 0; 2269 } 2270 2271 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2272 { 2273 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2274 uint32_t tmp; 2275 int i; 2276 2277 /* Trigger an invalidation of the L1 instruction caches */ 2278 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2279 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2280 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2281 2282 /* Wait for invalidation complete */ 2283 for (i = 0; i < usec_timeout; i++) { 2284 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2285 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2286 INVALIDATE_CACHE_COMPLETE)) 2287 break; 2288 udelay(1); 2289 } 2290 2291 if (i >= usec_timeout) { 2292 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2293 return -EINVAL; 2294 } 2295 2296 if (amdgpu_emu_mode == 1) 2297 adev->hdp.funcs->flush_hdp(adev, NULL); 2298 2299 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2300 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2301 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2302 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2303 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2304 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2305 2306 /* Program pfp ucode address into intruction cache address register */ 2307 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2308 lower_32_bits(addr) & 0xFFFFF000); 2309 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2310 upper_32_bits(addr)); 2311 2312 return 0; 2313 } 2314 2315 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2316 { 2317 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2318 uint32_t tmp; 2319 int i; 2320 2321 /* Trigger an invalidation of the L1 instruction caches */ 2322 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2323 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2324 2325 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2326 2327 /* Wait for invalidation complete */ 2328 for (i = 0; i < usec_timeout; i++) { 2329 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2330 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2331 INVALIDATE_CACHE_COMPLETE)) 2332 break; 2333 udelay(1); 2334 } 2335 2336 if (i >= usec_timeout) { 2337 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2338 return -EINVAL; 2339 } 2340 2341 if (amdgpu_emu_mode == 1) 2342 adev->hdp.funcs->flush_hdp(adev, NULL); 2343 2344 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2345 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2346 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2347 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2348 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2349 2350 /* Program mec1 ucode address into intruction cache address register */ 2351 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2352 lower_32_bits(addr) & 0xFFFFF000); 2353 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2354 upper_32_bits(addr)); 2355 2356 return 0; 2357 } 2358 2359 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2360 { 2361 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2362 uint32_t tmp; 2363 unsigned i, pipe_id; 2364 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2365 2366 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2367 adev->gfx.pfp_fw->data; 2368 2369 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2370 lower_32_bits(addr)); 2371 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2372 upper_32_bits(addr)); 2373 2374 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2375 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2376 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2377 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2378 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2379 2380 /* 2381 * Programming any of the CP_PFP_IC_BASE registers 2382 * forces invalidation of the ME L1 I$. Wait for the 2383 * invalidation complete 2384 */ 2385 for (i = 0; i < usec_timeout; i++) { 2386 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2387 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2388 INVALIDATE_CACHE_COMPLETE)) 2389 break; 2390 udelay(1); 2391 } 2392 2393 if (i >= usec_timeout) { 2394 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2395 return -EINVAL; 2396 } 2397 2398 /* Prime the L1 instruction caches */ 2399 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2400 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2401 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2402 /* Waiting for cache primed*/ 2403 for (i = 0; i < usec_timeout; i++) { 2404 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2405 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2406 ICACHE_PRIMED)) 2407 break; 2408 udelay(1); 2409 } 2410 2411 if (i >= usec_timeout) { 2412 dev_err(adev->dev, "failed to prime instruction cache\n"); 2413 return -EINVAL; 2414 } 2415 2416 mutex_lock(&adev->srbm_mutex); 2417 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2418 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2419 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2420 (pfp_hdr->ucode_start_addr_hi << 30) | 2421 (pfp_hdr->ucode_start_addr_lo >> 2)); 2422 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2423 pfp_hdr->ucode_start_addr_hi >> 2); 2424 2425 /* 2426 * Program CP_ME_CNTL to reset given PIPE to take 2427 * effect of CP_PFP_PRGRM_CNTR_START. 2428 */ 2429 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2430 if (pipe_id == 0) 2431 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2432 PFP_PIPE0_RESET, 1); 2433 else 2434 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2435 PFP_PIPE1_RESET, 1); 2436 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2437 2438 /* Clear pfp pipe0 reset bit. */ 2439 if (pipe_id == 0) 2440 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2441 PFP_PIPE0_RESET, 0); 2442 else 2443 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2444 PFP_PIPE1_RESET, 0); 2445 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2446 2447 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2448 lower_32_bits(addr2)); 2449 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2450 upper_32_bits(addr2)); 2451 } 2452 soc21_grbm_select(adev, 0, 0, 0, 0); 2453 mutex_unlock(&adev->srbm_mutex); 2454 2455 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2456 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2457 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2458 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2459 2460 /* Invalidate the data caches */ 2461 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2462 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2463 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2464 2465 for (i = 0; i < usec_timeout; i++) { 2466 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2467 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2468 INVALIDATE_DCACHE_COMPLETE)) 2469 break; 2470 udelay(1); 2471 } 2472 2473 if (i >= usec_timeout) { 2474 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2475 return -EINVAL; 2476 } 2477 2478 return 0; 2479 } 2480 2481 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2482 { 2483 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2484 uint32_t tmp; 2485 unsigned i, pipe_id; 2486 const struct gfx_firmware_header_v2_0 *me_hdr; 2487 2488 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2489 adev->gfx.me_fw->data; 2490 2491 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2492 lower_32_bits(addr)); 2493 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2494 upper_32_bits(addr)); 2495 2496 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2497 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2498 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2499 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2500 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2501 2502 /* 2503 * Programming any of the CP_ME_IC_BASE registers 2504 * forces invalidation of the ME L1 I$. Wait for the 2505 * invalidation complete 2506 */ 2507 for (i = 0; i < usec_timeout; i++) { 2508 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2509 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2510 INVALIDATE_CACHE_COMPLETE)) 2511 break; 2512 udelay(1); 2513 } 2514 2515 if (i >= usec_timeout) { 2516 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2517 return -EINVAL; 2518 } 2519 2520 /* Prime the instruction caches */ 2521 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2522 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2523 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2524 2525 /* Waiting for instruction cache primed*/ 2526 for (i = 0; i < usec_timeout; i++) { 2527 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2528 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2529 ICACHE_PRIMED)) 2530 break; 2531 udelay(1); 2532 } 2533 2534 if (i >= usec_timeout) { 2535 dev_err(adev->dev, "failed to prime instruction cache\n"); 2536 return -EINVAL; 2537 } 2538 2539 mutex_lock(&adev->srbm_mutex); 2540 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2541 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2542 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2543 (me_hdr->ucode_start_addr_hi << 30) | 2544 (me_hdr->ucode_start_addr_lo >> 2) ); 2545 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2546 me_hdr->ucode_start_addr_hi>>2); 2547 2548 /* 2549 * Program CP_ME_CNTL to reset given PIPE to take 2550 * effect of CP_PFP_PRGRM_CNTR_START. 2551 */ 2552 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2553 if (pipe_id == 0) 2554 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2555 ME_PIPE0_RESET, 1); 2556 else 2557 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2558 ME_PIPE1_RESET, 1); 2559 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2560 2561 /* Clear pfp pipe0 reset bit. */ 2562 if (pipe_id == 0) 2563 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2564 ME_PIPE0_RESET, 0); 2565 else 2566 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2567 ME_PIPE1_RESET, 0); 2568 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2569 2570 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2571 lower_32_bits(addr2)); 2572 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2573 upper_32_bits(addr2)); 2574 } 2575 soc21_grbm_select(adev, 0, 0, 0, 0); 2576 mutex_unlock(&adev->srbm_mutex); 2577 2578 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2579 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2580 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2581 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2582 2583 /* Invalidate the data caches */ 2584 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2585 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2586 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2587 2588 for (i = 0; i < usec_timeout; i++) { 2589 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2590 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2591 INVALIDATE_DCACHE_COMPLETE)) 2592 break; 2593 udelay(1); 2594 } 2595 2596 if (i >= usec_timeout) { 2597 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2598 return -EINVAL; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2605 { 2606 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2607 uint32_t tmp; 2608 unsigned i; 2609 const struct gfx_firmware_header_v2_0 *mec_hdr; 2610 2611 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2612 adev->gfx.mec_fw->data; 2613 2614 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2615 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2616 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2617 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2618 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2619 2620 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2621 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2622 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2623 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2624 2625 mutex_lock(&adev->srbm_mutex); 2626 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2627 soc21_grbm_select(adev, 1, i, 0, 0); 2628 2629 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2630 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2631 upper_32_bits(addr2)); 2632 2633 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2634 mec_hdr->ucode_start_addr_lo >> 2 | 2635 mec_hdr->ucode_start_addr_hi << 30); 2636 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2637 mec_hdr->ucode_start_addr_hi >> 2); 2638 2639 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2640 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2641 upper_32_bits(addr)); 2642 } 2643 mutex_unlock(&adev->srbm_mutex); 2644 soc21_grbm_select(adev, 0, 0, 0, 0); 2645 2646 /* Trigger an invalidation of the L1 instruction caches */ 2647 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2648 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2649 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2650 2651 /* Wait for invalidation complete */ 2652 for (i = 0; i < usec_timeout; i++) { 2653 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2654 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2655 INVALIDATE_DCACHE_COMPLETE)) 2656 break; 2657 udelay(1); 2658 } 2659 2660 if (i >= usec_timeout) { 2661 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2662 return -EINVAL; 2663 } 2664 2665 /* Trigger an invalidation of the L1 instruction caches */ 2666 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2667 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2668 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2669 2670 /* Wait for invalidation complete */ 2671 for (i = 0; i < usec_timeout; i++) { 2672 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2673 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2674 INVALIDATE_CACHE_COMPLETE)) 2675 break; 2676 udelay(1); 2677 } 2678 2679 if (i >= usec_timeout) { 2680 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2681 return -EINVAL; 2682 } 2683 2684 return 0; 2685 } 2686 2687 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2688 { 2689 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2690 const struct gfx_firmware_header_v2_0 *me_hdr; 2691 const struct gfx_firmware_header_v2_0 *mec_hdr; 2692 uint32_t pipe_id, tmp; 2693 2694 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2695 adev->gfx.mec_fw->data; 2696 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2697 adev->gfx.me_fw->data; 2698 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2699 adev->gfx.pfp_fw->data; 2700 2701 /* config pfp program start addr */ 2702 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2703 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2704 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2705 (pfp_hdr->ucode_start_addr_hi << 30) | 2706 (pfp_hdr->ucode_start_addr_lo >> 2)); 2707 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2708 pfp_hdr->ucode_start_addr_hi >> 2); 2709 } 2710 soc21_grbm_select(adev, 0, 0, 0, 0); 2711 2712 /* reset pfp pipe */ 2713 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2714 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2715 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2716 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2717 2718 /* clear pfp pipe reset */ 2719 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2720 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2721 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2722 2723 /* config me program start addr */ 2724 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2725 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2726 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2727 (me_hdr->ucode_start_addr_hi << 30) | 2728 (me_hdr->ucode_start_addr_lo >> 2) ); 2729 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2730 me_hdr->ucode_start_addr_hi>>2); 2731 } 2732 soc21_grbm_select(adev, 0, 0, 0, 0); 2733 2734 /* reset me pipe */ 2735 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2736 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2737 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2738 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2739 2740 /* clear me pipe reset */ 2741 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2742 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2743 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2744 2745 /* config mec program start addr */ 2746 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2747 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2748 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2749 mec_hdr->ucode_start_addr_lo >> 2 | 2750 mec_hdr->ucode_start_addr_hi << 30); 2751 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2752 mec_hdr->ucode_start_addr_hi >> 2); 2753 } 2754 soc21_grbm_select(adev, 0, 0, 0, 0); 2755 2756 /* reset mec pipe */ 2757 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2758 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2759 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2760 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2761 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2762 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2763 2764 /* clear mec pipe reset */ 2765 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2766 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2767 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2768 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2769 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2770 } 2771 2772 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2773 { 2774 uint32_t cp_status; 2775 uint32_t bootload_status; 2776 int i, r; 2777 uint64_t addr, addr2; 2778 2779 for (i = 0; i < adev->usec_timeout; i++) { 2780 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2781 2782 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2783 IP_VERSION(11, 0, 1) || 2784 amdgpu_ip_version(adev, GC_HWIP, 0) == 2785 IP_VERSION(11, 0, 4) || 2786 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 2787 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1)) 2788 bootload_status = RREG32_SOC15(GC, 0, 2789 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2790 else 2791 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2792 2793 if ((cp_status == 0) && 2794 (REG_GET_FIELD(bootload_status, 2795 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2796 break; 2797 } 2798 udelay(1); 2799 } 2800 2801 if (i >= adev->usec_timeout) { 2802 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2803 return -ETIMEDOUT; 2804 } 2805 2806 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2807 if (adev->gfx.rs64_enable) { 2808 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2809 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2810 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2811 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2812 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2813 if (r) 2814 return r; 2815 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2816 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2817 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2818 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2819 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2820 if (r) 2821 return r; 2822 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2823 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2824 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2825 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2826 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2827 if (r) 2828 return r; 2829 } else { 2830 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2831 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2832 r = gfx_v11_0_config_me_cache(adev, addr); 2833 if (r) 2834 return r; 2835 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2836 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2837 r = gfx_v11_0_config_pfp_cache(adev, addr); 2838 if (r) 2839 return r; 2840 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2841 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2842 r = gfx_v11_0_config_mec_cache(adev, addr); 2843 if (r) 2844 return r; 2845 } 2846 } 2847 2848 return 0; 2849 } 2850 2851 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2852 { 2853 int i; 2854 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2855 2856 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2857 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2858 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2859 2860 for (i = 0; i < adev->usec_timeout; i++) { 2861 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2862 break; 2863 udelay(1); 2864 } 2865 2866 if (i >= adev->usec_timeout) 2867 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2868 2869 return 0; 2870 } 2871 2872 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2873 { 2874 int r; 2875 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2876 const __le32 *fw_data; 2877 unsigned i, fw_size; 2878 2879 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2880 adev->gfx.pfp_fw->data; 2881 2882 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2883 2884 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2885 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2886 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2887 2888 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2889 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2890 &adev->gfx.pfp.pfp_fw_obj, 2891 &adev->gfx.pfp.pfp_fw_gpu_addr, 2892 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2893 if (r) { 2894 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2895 gfx_v11_0_pfp_fini(adev); 2896 return r; 2897 } 2898 2899 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2900 2901 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2902 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2903 2904 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2905 2906 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2907 2908 for (i = 0; i < pfp_hdr->jt_size; i++) 2909 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2910 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2911 2912 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2913 2914 return 0; 2915 } 2916 2917 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2918 { 2919 int r; 2920 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2921 const __le32 *fw_ucode, *fw_data; 2922 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2923 uint32_t tmp; 2924 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2925 2926 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2927 adev->gfx.pfp_fw->data; 2928 2929 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2930 2931 /* instruction */ 2932 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2933 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2934 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2935 /* data */ 2936 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2937 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2938 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2939 2940 /* 64kb align */ 2941 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2942 64 * 1024, 2943 AMDGPU_GEM_DOMAIN_VRAM | 2944 AMDGPU_GEM_DOMAIN_GTT, 2945 &adev->gfx.pfp.pfp_fw_obj, 2946 &adev->gfx.pfp.pfp_fw_gpu_addr, 2947 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2948 if (r) { 2949 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2950 gfx_v11_0_pfp_fini(adev); 2951 return r; 2952 } 2953 2954 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2955 64 * 1024, 2956 AMDGPU_GEM_DOMAIN_VRAM | 2957 AMDGPU_GEM_DOMAIN_GTT, 2958 &adev->gfx.pfp.pfp_fw_data_obj, 2959 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2960 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2961 if (r) { 2962 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2963 gfx_v11_0_pfp_fini(adev); 2964 return r; 2965 } 2966 2967 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2968 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2969 2970 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2971 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2972 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2973 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2974 2975 if (amdgpu_emu_mode == 1) 2976 adev->hdp.funcs->flush_hdp(adev, NULL); 2977 2978 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2979 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2980 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2981 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2982 2983 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2984 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2985 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2986 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2987 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2988 2989 /* 2990 * Programming any of the CP_PFP_IC_BASE registers 2991 * forces invalidation of the ME L1 I$. Wait for the 2992 * invalidation complete 2993 */ 2994 for (i = 0; i < usec_timeout; i++) { 2995 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2996 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2997 INVALIDATE_CACHE_COMPLETE)) 2998 break; 2999 udelay(1); 3000 } 3001 3002 if (i >= usec_timeout) { 3003 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3004 return -EINVAL; 3005 } 3006 3007 /* Prime the L1 instruction caches */ 3008 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3009 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3010 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3011 /* Waiting for cache primed*/ 3012 for (i = 0; i < usec_timeout; i++) { 3013 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3014 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3015 ICACHE_PRIMED)) 3016 break; 3017 udelay(1); 3018 } 3019 3020 if (i >= usec_timeout) { 3021 dev_err(adev->dev, "failed to prime instruction cache\n"); 3022 return -EINVAL; 3023 } 3024 3025 mutex_lock(&adev->srbm_mutex); 3026 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3027 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3028 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3029 (pfp_hdr->ucode_start_addr_hi << 30) | 3030 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3031 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3032 pfp_hdr->ucode_start_addr_hi>>2); 3033 3034 /* 3035 * Program CP_ME_CNTL to reset given PIPE to take 3036 * effect of CP_PFP_PRGRM_CNTR_START. 3037 */ 3038 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3039 if (pipe_id == 0) 3040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3041 PFP_PIPE0_RESET, 1); 3042 else 3043 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3044 PFP_PIPE1_RESET, 1); 3045 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3046 3047 /* Clear pfp pipe0 reset bit. */ 3048 if (pipe_id == 0) 3049 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3050 PFP_PIPE0_RESET, 0); 3051 else 3052 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3053 PFP_PIPE1_RESET, 0); 3054 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3055 3056 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3057 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3058 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3059 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3060 } 3061 soc21_grbm_select(adev, 0, 0, 0, 0); 3062 mutex_unlock(&adev->srbm_mutex); 3063 3064 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3065 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3066 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3067 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3068 3069 /* Invalidate the data caches */ 3070 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3071 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3072 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3073 3074 for (i = 0; i < usec_timeout; i++) { 3075 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3076 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3077 INVALIDATE_DCACHE_COMPLETE)) 3078 break; 3079 udelay(1); 3080 } 3081 3082 if (i >= usec_timeout) { 3083 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3084 return -EINVAL; 3085 } 3086 3087 return 0; 3088 } 3089 3090 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3091 { 3092 int r; 3093 const struct gfx_firmware_header_v1_0 *me_hdr; 3094 const __le32 *fw_data; 3095 unsigned i, fw_size; 3096 3097 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3098 adev->gfx.me_fw->data; 3099 3100 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3101 3102 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3103 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3104 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3105 3106 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3107 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3108 &adev->gfx.me.me_fw_obj, 3109 &adev->gfx.me.me_fw_gpu_addr, 3110 (void **)&adev->gfx.me.me_fw_ptr); 3111 if (r) { 3112 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3113 gfx_v11_0_me_fini(adev); 3114 return r; 3115 } 3116 3117 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3118 3119 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3120 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3121 3122 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3123 3124 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3125 3126 for (i = 0; i < me_hdr->jt_size; i++) 3127 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3128 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3129 3130 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3131 3132 return 0; 3133 } 3134 3135 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3136 { 3137 int r; 3138 const struct gfx_firmware_header_v2_0 *me_hdr; 3139 const __le32 *fw_ucode, *fw_data; 3140 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3141 uint32_t tmp; 3142 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3143 3144 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3145 adev->gfx.me_fw->data; 3146 3147 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3148 3149 /* instruction */ 3150 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3151 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3152 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3153 /* data */ 3154 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3155 le32_to_cpu(me_hdr->data_offset_bytes)); 3156 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3157 3158 /* 64kb align*/ 3159 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3160 64 * 1024, 3161 AMDGPU_GEM_DOMAIN_VRAM | 3162 AMDGPU_GEM_DOMAIN_GTT, 3163 &adev->gfx.me.me_fw_obj, 3164 &adev->gfx.me.me_fw_gpu_addr, 3165 (void **)&adev->gfx.me.me_fw_ptr); 3166 if (r) { 3167 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3168 gfx_v11_0_me_fini(adev); 3169 return r; 3170 } 3171 3172 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3173 64 * 1024, 3174 AMDGPU_GEM_DOMAIN_VRAM | 3175 AMDGPU_GEM_DOMAIN_GTT, 3176 &adev->gfx.me.me_fw_data_obj, 3177 &adev->gfx.me.me_fw_data_gpu_addr, 3178 (void **)&adev->gfx.me.me_fw_data_ptr); 3179 if (r) { 3180 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3181 gfx_v11_0_pfp_fini(adev); 3182 return r; 3183 } 3184 3185 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3186 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3187 3188 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3189 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3190 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3191 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3192 3193 if (amdgpu_emu_mode == 1) 3194 adev->hdp.funcs->flush_hdp(adev, NULL); 3195 3196 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3197 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3198 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3199 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3200 3201 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3202 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3203 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3204 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3205 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3206 3207 /* 3208 * Programming any of the CP_ME_IC_BASE registers 3209 * forces invalidation of the ME L1 I$. Wait for the 3210 * invalidation complete 3211 */ 3212 for (i = 0; i < usec_timeout; i++) { 3213 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3214 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3215 INVALIDATE_CACHE_COMPLETE)) 3216 break; 3217 udelay(1); 3218 } 3219 3220 if (i >= usec_timeout) { 3221 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3222 return -EINVAL; 3223 } 3224 3225 /* Prime the instruction caches */ 3226 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3227 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3228 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3229 3230 /* Waiting for instruction cache primed*/ 3231 for (i = 0; i < usec_timeout; i++) { 3232 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3233 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3234 ICACHE_PRIMED)) 3235 break; 3236 udelay(1); 3237 } 3238 3239 if (i >= usec_timeout) { 3240 dev_err(adev->dev, "failed to prime instruction cache\n"); 3241 return -EINVAL; 3242 } 3243 3244 mutex_lock(&adev->srbm_mutex); 3245 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3246 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3247 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3248 (me_hdr->ucode_start_addr_hi << 30) | 3249 (me_hdr->ucode_start_addr_lo >> 2) ); 3250 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3251 me_hdr->ucode_start_addr_hi>>2); 3252 3253 /* 3254 * Program CP_ME_CNTL to reset given PIPE to take 3255 * effect of CP_PFP_PRGRM_CNTR_START. 3256 */ 3257 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3258 if (pipe_id == 0) 3259 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3260 ME_PIPE0_RESET, 1); 3261 else 3262 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3263 ME_PIPE1_RESET, 1); 3264 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3265 3266 /* Clear pfp pipe0 reset bit. */ 3267 if (pipe_id == 0) 3268 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3269 ME_PIPE0_RESET, 0); 3270 else 3271 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3272 ME_PIPE1_RESET, 0); 3273 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3274 3275 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3276 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3277 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3278 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3279 } 3280 soc21_grbm_select(adev, 0, 0, 0, 0); 3281 mutex_unlock(&adev->srbm_mutex); 3282 3283 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3284 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3285 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3286 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3287 3288 /* Invalidate the data caches */ 3289 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3290 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3291 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3292 3293 for (i = 0; i < usec_timeout; i++) { 3294 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3295 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3296 INVALIDATE_DCACHE_COMPLETE)) 3297 break; 3298 udelay(1); 3299 } 3300 3301 if (i >= usec_timeout) { 3302 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3303 return -EINVAL; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3310 { 3311 int r; 3312 3313 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3314 return -EINVAL; 3315 3316 gfx_v11_0_cp_gfx_enable(adev, false); 3317 3318 if (adev->gfx.rs64_enable) 3319 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3320 else 3321 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3322 if (r) { 3323 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3324 return r; 3325 } 3326 3327 if (adev->gfx.rs64_enable) 3328 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3329 else 3330 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3331 if (r) { 3332 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3333 return r; 3334 } 3335 3336 return 0; 3337 } 3338 3339 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3340 { 3341 struct amdgpu_ring *ring; 3342 const struct cs_section_def *sect = NULL; 3343 const struct cs_extent_def *ext = NULL; 3344 int r, i; 3345 int ctx_reg_offset; 3346 3347 /* init the CP */ 3348 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3349 adev->gfx.config.max_hw_contexts - 1); 3350 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3351 3352 if (!amdgpu_async_gfx_ring) 3353 gfx_v11_0_cp_gfx_enable(adev, true); 3354 3355 ring = &adev->gfx.gfx_ring[0]; 3356 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3357 if (r) { 3358 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3359 return r; 3360 } 3361 3362 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3363 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3364 3365 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3366 amdgpu_ring_write(ring, 0x80000000); 3367 amdgpu_ring_write(ring, 0x80000000); 3368 3369 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3370 for (ext = sect->section; ext->extent != NULL; ++ext) { 3371 if (sect->id == SECT_CONTEXT) { 3372 amdgpu_ring_write(ring, 3373 PACKET3(PACKET3_SET_CONTEXT_REG, 3374 ext->reg_count)); 3375 amdgpu_ring_write(ring, ext->reg_index - 3376 PACKET3_SET_CONTEXT_REG_START); 3377 for (i = 0; i < ext->reg_count; i++) 3378 amdgpu_ring_write(ring, ext->extent[i]); 3379 } 3380 } 3381 } 3382 3383 ctx_reg_offset = 3384 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3385 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3386 amdgpu_ring_write(ring, ctx_reg_offset); 3387 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3388 3389 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3390 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3391 3392 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3393 amdgpu_ring_write(ring, 0); 3394 3395 amdgpu_ring_commit(ring); 3396 3397 /* submit cs packet to copy state 0 to next available state */ 3398 if (adev->gfx.num_gfx_rings > 1) { 3399 /* maximum supported gfx ring is 2 */ 3400 ring = &adev->gfx.gfx_ring[1]; 3401 r = amdgpu_ring_alloc(ring, 2); 3402 if (r) { 3403 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3404 return r; 3405 } 3406 3407 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3408 amdgpu_ring_write(ring, 0); 3409 3410 amdgpu_ring_commit(ring); 3411 } 3412 return 0; 3413 } 3414 3415 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3416 CP_PIPE_ID pipe) 3417 { 3418 u32 tmp; 3419 3420 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3421 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3422 3423 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3424 } 3425 3426 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3427 struct amdgpu_ring *ring) 3428 { 3429 u32 tmp; 3430 3431 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3432 if (ring->use_doorbell) { 3433 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3434 DOORBELL_OFFSET, ring->doorbell_index); 3435 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3436 DOORBELL_EN, 1); 3437 } else { 3438 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3439 DOORBELL_EN, 0); 3440 } 3441 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3442 3443 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3444 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3445 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3446 3447 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3448 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3449 } 3450 3451 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3452 { 3453 struct amdgpu_ring *ring; 3454 u32 tmp; 3455 u32 rb_bufsz; 3456 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3457 3458 /* Set the write pointer delay */ 3459 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3460 3461 /* set the RB to use vmid 0 */ 3462 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3463 3464 /* Init gfx ring 0 for pipe 0 */ 3465 mutex_lock(&adev->srbm_mutex); 3466 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3467 3468 /* Set ring buffer size */ 3469 ring = &adev->gfx.gfx_ring[0]; 3470 rb_bufsz = order_base_2(ring->ring_size / 8); 3471 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3472 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3473 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3474 3475 /* Initialize the ring buffer's write pointers */ 3476 ring->wptr = 0; 3477 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3478 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3479 3480 /* set the wb address wether it's enabled or not */ 3481 rptr_addr = ring->rptr_gpu_addr; 3482 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3483 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3484 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3485 3486 wptr_gpu_addr = ring->wptr_gpu_addr; 3487 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3488 lower_32_bits(wptr_gpu_addr)); 3489 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3490 upper_32_bits(wptr_gpu_addr)); 3491 3492 mdelay(1); 3493 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3494 3495 rb_addr = ring->gpu_addr >> 8; 3496 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3497 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3498 3499 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3500 3501 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3502 mutex_unlock(&adev->srbm_mutex); 3503 3504 /* Init gfx ring 1 for pipe 1 */ 3505 if (adev->gfx.num_gfx_rings > 1) { 3506 mutex_lock(&adev->srbm_mutex); 3507 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3508 /* maximum supported gfx ring is 2 */ 3509 ring = &adev->gfx.gfx_ring[1]; 3510 rb_bufsz = order_base_2(ring->ring_size / 8); 3511 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3512 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3513 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3514 /* Initialize the ring buffer's write pointers */ 3515 ring->wptr = 0; 3516 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3517 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3518 /* Set the wb address wether it's enabled or not */ 3519 rptr_addr = ring->rptr_gpu_addr; 3520 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3521 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3522 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3523 wptr_gpu_addr = ring->wptr_gpu_addr; 3524 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3525 lower_32_bits(wptr_gpu_addr)); 3526 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3527 upper_32_bits(wptr_gpu_addr)); 3528 3529 mdelay(1); 3530 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3531 3532 rb_addr = ring->gpu_addr >> 8; 3533 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3534 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3535 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3536 3537 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3538 mutex_unlock(&adev->srbm_mutex); 3539 } 3540 /* Switch to pipe 0 */ 3541 mutex_lock(&adev->srbm_mutex); 3542 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3543 mutex_unlock(&adev->srbm_mutex); 3544 3545 /* start the ring */ 3546 gfx_v11_0_cp_gfx_start(adev); 3547 3548 return 0; 3549 } 3550 3551 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3552 { 3553 u32 data; 3554 3555 if (adev->gfx.rs64_enable) { 3556 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3557 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3558 enable ? 0 : 1); 3559 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3560 enable ? 0 : 1); 3561 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3562 enable ? 0 : 1); 3563 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3564 enable ? 0 : 1); 3565 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3566 enable ? 0 : 1); 3567 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3568 enable ? 1 : 0); 3569 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3570 enable ? 1 : 0); 3571 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3572 enable ? 1 : 0); 3573 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3574 enable ? 1 : 0); 3575 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3576 enable ? 0 : 1); 3577 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3578 } else { 3579 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3580 3581 if (enable) { 3582 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3583 if (!adev->enable_mes_kiq) 3584 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3585 MEC_ME2_HALT, 0); 3586 } else { 3587 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3588 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3589 } 3590 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3591 } 3592 3593 udelay(50); 3594 } 3595 3596 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3597 { 3598 const struct gfx_firmware_header_v1_0 *mec_hdr; 3599 const __le32 *fw_data; 3600 unsigned i, fw_size; 3601 u32 *fw = NULL; 3602 int r; 3603 3604 if (!adev->gfx.mec_fw) 3605 return -EINVAL; 3606 3607 gfx_v11_0_cp_compute_enable(adev, false); 3608 3609 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3610 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3611 3612 fw_data = (const __le32 *) 3613 (adev->gfx.mec_fw->data + 3614 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3615 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3616 3617 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3618 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3619 &adev->gfx.mec.mec_fw_obj, 3620 &adev->gfx.mec.mec_fw_gpu_addr, 3621 (void **)&fw); 3622 if (r) { 3623 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3624 gfx_v11_0_mec_fini(adev); 3625 return r; 3626 } 3627 3628 memcpy(fw, fw_data, fw_size); 3629 3630 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3631 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3632 3633 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3634 3635 /* MEC1 */ 3636 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3637 3638 for (i = 0; i < mec_hdr->jt_size; i++) 3639 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3640 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3641 3642 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3643 3644 return 0; 3645 } 3646 3647 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3648 { 3649 const struct gfx_firmware_header_v2_0 *mec_hdr; 3650 const __le32 *fw_ucode, *fw_data; 3651 u32 tmp, fw_ucode_size, fw_data_size; 3652 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3653 u32 *fw_ucode_ptr, *fw_data_ptr; 3654 int r; 3655 3656 if (!adev->gfx.mec_fw) 3657 return -EINVAL; 3658 3659 gfx_v11_0_cp_compute_enable(adev, false); 3660 3661 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3662 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3663 3664 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3665 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3666 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3667 3668 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3669 le32_to_cpu(mec_hdr->data_offset_bytes)); 3670 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3671 3672 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3673 64 * 1024, 3674 AMDGPU_GEM_DOMAIN_VRAM | 3675 AMDGPU_GEM_DOMAIN_GTT, 3676 &adev->gfx.mec.mec_fw_obj, 3677 &adev->gfx.mec.mec_fw_gpu_addr, 3678 (void **)&fw_ucode_ptr); 3679 if (r) { 3680 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3681 gfx_v11_0_mec_fini(adev); 3682 return r; 3683 } 3684 3685 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3686 64 * 1024, 3687 AMDGPU_GEM_DOMAIN_VRAM | 3688 AMDGPU_GEM_DOMAIN_GTT, 3689 &adev->gfx.mec.mec_fw_data_obj, 3690 &adev->gfx.mec.mec_fw_data_gpu_addr, 3691 (void **)&fw_data_ptr); 3692 if (r) { 3693 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3694 gfx_v11_0_mec_fini(adev); 3695 return r; 3696 } 3697 3698 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3699 memcpy(fw_data_ptr, fw_data, fw_data_size); 3700 3701 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3702 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3703 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3704 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3705 3706 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3707 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3708 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3709 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3710 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3711 3712 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3713 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3714 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3715 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3716 3717 mutex_lock(&adev->srbm_mutex); 3718 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3719 soc21_grbm_select(adev, 1, i, 0, 0); 3720 3721 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3722 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3723 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3724 3725 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3726 mec_hdr->ucode_start_addr_lo >> 2 | 3727 mec_hdr->ucode_start_addr_hi << 30); 3728 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3729 mec_hdr->ucode_start_addr_hi >> 2); 3730 3731 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3732 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3733 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3734 } 3735 mutex_unlock(&adev->srbm_mutex); 3736 soc21_grbm_select(adev, 0, 0, 0, 0); 3737 3738 /* Trigger an invalidation of the L1 instruction caches */ 3739 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3740 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3741 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3742 3743 /* Wait for invalidation complete */ 3744 for (i = 0; i < usec_timeout; i++) { 3745 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3746 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3747 INVALIDATE_DCACHE_COMPLETE)) 3748 break; 3749 udelay(1); 3750 } 3751 3752 if (i >= usec_timeout) { 3753 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3754 return -EINVAL; 3755 } 3756 3757 /* Trigger an invalidation of the L1 instruction caches */ 3758 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3759 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3760 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3761 3762 /* Wait for invalidation complete */ 3763 for (i = 0; i < usec_timeout; i++) { 3764 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3765 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3766 INVALIDATE_CACHE_COMPLETE)) 3767 break; 3768 udelay(1); 3769 } 3770 3771 if (i >= usec_timeout) { 3772 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3773 return -EINVAL; 3774 } 3775 3776 return 0; 3777 } 3778 3779 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3780 { 3781 uint32_t tmp; 3782 struct amdgpu_device *adev = ring->adev; 3783 3784 /* tell RLC which is KIQ queue */ 3785 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3786 tmp &= 0xffffff00; 3787 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3788 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3789 tmp |= 0x80; 3790 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3791 } 3792 3793 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3794 { 3795 /* set graphics engine doorbell range */ 3796 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3797 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3798 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3799 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3800 3801 /* set compute engine doorbell range */ 3802 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3803 (adev->doorbell_index.kiq * 2) << 2); 3804 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3805 (adev->doorbell_index.userqueue_end * 2) << 2); 3806 } 3807 3808 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 3809 struct v11_gfx_mqd *mqd, 3810 struct amdgpu_mqd_prop *prop) 3811 { 3812 bool priority = 0; 3813 u32 tmp; 3814 3815 /* set up default queue priority level 3816 * 0x0 = low priority, 0x1 = high priority 3817 */ 3818 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 3819 priority = 1; 3820 3821 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3822 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 3823 mqd->cp_gfx_hqd_queue_priority = tmp; 3824 } 3825 3826 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3827 struct amdgpu_mqd_prop *prop) 3828 { 3829 struct v11_gfx_mqd *mqd = m; 3830 uint64_t hqd_gpu_addr, wb_gpu_addr; 3831 uint32_t tmp; 3832 uint32_t rb_bufsz; 3833 3834 /* set up gfx hqd wptr */ 3835 mqd->cp_gfx_hqd_wptr = 0; 3836 mqd->cp_gfx_hqd_wptr_hi = 0; 3837 3838 /* set the pointer to the MQD */ 3839 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3840 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3841 3842 /* set up mqd control */ 3843 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3844 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3845 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3846 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3847 mqd->cp_gfx_mqd_control = tmp; 3848 3849 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3850 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3851 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3852 mqd->cp_gfx_hqd_vmid = 0; 3853 3854 /* set up gfx queue priority */ 3855 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 3856 3857 /* set up time quantum */ 3858 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3859 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3860 mqd->cp_gfx_hqd_quantum = tmp; 3861 3862 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3863 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3864 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3865 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3866 3867 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3868 wb_gpu_addr = prop->rptr_gpu_addr; 3869 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3870 mqd->cp_gfx_hqd_rptr_addr_hi = 3871 upper_32_bits(wb_gpu_addr) & 0xffff; 3872 3873 /* set up rb_wptr_poll addr */ 3874 wb_gpu_addr = prop->wptr_gpu_addr; 3875 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3876 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3877 3878 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3879 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3880 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3881 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3882 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3883 #ifdef __BIG_ENDIAN 3884 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3885 #endif 3886 mqd->cp_gfx_hqd_cntl = tmp; 3887 3888 /* set up cp_doorbell_control */ 3889 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3890 if (prop->use_doorbell) { 3891 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3892 DOORBELL_OFFSET, prop->doorbell_index); 3893 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3894 DOORBELL_EN, 1); 3895 } else 3896 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3897 DOORBELL_EN, 0); 3898 mqd->cp_rb_doorbell_control = tmp; 3899 3900 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3901 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3902 3903 /* active the queue */ 3904 mqd->cp_gfx_hqd_active = 1; 3905 3906 return 0; 3907 } 3908 3909 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3910 { 3911 struct amdgpu_device *adev = ring->adev; 3912 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3913 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3914 3915 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3916 memset((void *)mqd, 0, sizeof(*mqd)); 3917 mutex_lock(&adev->srbm_mutex); 3918 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3919 amdgpu_ring_init_mqd(ring); 3920 soc21_grbm_select(adev, 0, 0, 0, 0); 3921 mutex_unlock(&adev->srbm_mutex); 3922 if (adev->gfx.me.mqd_backup[mqd_idx]) 3923 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3924 } else { 3925 /* restore mqd with the backup copy */ 3926 if (adev->gfx.me.mqd_backup[mqd_idx]) 3927 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3928 /* reset the ring */ 3929 ring->wptr = 0; 3930 *ring->wptr_cpu_addr = 0; 3931 amdgpu_ring_clear_ring(ring); 3932 } 3933 3934 return 0; 3935 } 3936 3937 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3938 { 3939 int r, i; 3940 struct amdgpu_ring *ring; 3941 3942 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3943 ring = &adev->gfx.gfx_ring[i]; 3944 3945 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3946 if (unlikely(r != 0)) 3947 return r; 3948 3949 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3950 if (!r) { 3951 r = gfx_v11_0_gfx_init_queue(ring); 3952 amdgpu_bo_kunmap(ring->mqd_obj); 3953 ring->mqd_ptr = NULL; 3954 } 3955 amdgpu_bo_unreserve(ring->mqd_obj); 3956 if (r) 3957 return r; 3958 } 3959 3960 r = amdgpu_gfx_enable_kgq(adev, 0); 3961 if (r) 3962 return r; 3963 3964 return gfx_v11_0_cp_gfx_start(adev); 3965 } 3966 3967 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3968 struct amdgpu_mqd_prop *prop) 3969 { 3970 struct v11_compute_mqd *mqd = m; 3971 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3972 uint32_t tmp; 3973 3974 mqd->header = 0xC0310800; 3975 mqd->compute_pipelinestat_enable = 0x00000001; 3976 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3977 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3978 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3979 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3980 mqd->compute_misc_reserved = 0x00000007; 3981 3982 eop_base_addr = prop->eop_gpu_addr >> 8; 3983 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3984 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3985 3986 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3987 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3988 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3989 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3990 3991 mqd->cp_hqd_eop_control = tmp; 3992 3993 /* enable doorbell? */ 3994 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3995 3996 if (prop->use_doorbell) { 3997 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3998 DOORBELL_OFFSET, prop->doorbell_index); 3999 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4000 DOORBELL_EN, 1); 4001 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4002 DOORBELL_SOURCE, 0); 4003 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4004 DOORBELL_HIT, 0); 4005 } else { 4006 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4007 DOORBELL_EN, 0); 4008 } 4009 4010 mqd->cp_hqd_pq_doorbell_control = tmp; 4011 4012 /* disable the queue if it's active */ 4013 mqd->cp_hqd_dequeue_request = 0; 4014 mqd->cp_hqd_pq_rptr = 0; 4015 mqd->cp_hqd_pq_wptr_lo = 0; 4016 mqd->cp_hqd_pq_wptr_hi = 0; 4017 4018 /* set the pointer to the MQD */ 4019 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4020 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4021 4022 /* set MQD vmid to 0 */ 4023 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4024 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4025 mqd->cp_mqd_control = tmp; 4026 4027 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4028 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4029 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4030 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4031 4032 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4033 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4034 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4035 (order_base_2(prop->queue_size / 4) - 1)); 4036 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4037 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4038 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4039 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4040 prop->allow_tunneling); 4041 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4042 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4043 mqd->cp_hqd_pq_control = tmp; 4044 4045 /* set the wb address whether it's enabled or not */ 4046 wb_gpu_addr = prop->rptr_gpu_addr; 4047 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4048 mqd->cp_hqd_pq_rptr_report_addr_hi = 4049 upper_32_bits(wb_gpu_addr) & 0xffff; 4050 4051 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4052 wb_gpu_addr = prop->wptr_gpu_addr; 4053 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4054 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4055 4056 tmp = 0; 4057 /* enable the doorbell if requested */ 4058 if (prop->use_doorbell) { 4059 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4061 DOORBELL_OFFSET, prop->doorbell_index); 4062 4063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4064 DOORBELL_EN, 1); 4065 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4066 DOORBELL_SOURCE, 0); 4067 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4068 DOORBELL_HIT, 0); 4069 } 4070 4071 mqd->cp_hqd_pq_doorbell_control = tmp; 4072 4073 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4074 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4075 4076 /* set the vmid for the queue */ 4077 mqd->cp_hqd_vmid = 0; 4078 4079 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4080 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4081 mqd->cp_hqd_persistent_state = tmp; 4082 4083 /* set MIN_IB_AVAIL_SIZE */ 4084 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4085 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4086 mqd->cp_hqd_ib_control = tmp; 4087 4088 /* set static priority for a compute queue/ring */ 4089 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4090 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4091 4092 mqd->cp_hqd_active = prop->hqd_active; 4093 4094 return 0; 4095 } 4096 4097 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4098 { 4099 struct amdgpu_device *adev = ring->adev; 4100 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4101 int j; 4102 4103 /* inactivate the queue */ 4104 if (amdgpu_sriov_vf(adev)) 4105 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4106 4107 /* disable wptr polling */ 4108 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4109 4110 /* write the EOP addr */ 4111 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4112 mqd->cp_hqd_eop_base_addr_lo); 4113 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4114 mqd->cp_hqd_eop_base_addr_hi); 4115 4116 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4117 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4118 mqd->cp_hqd_eop_control); 4119 4120 /* enable doorbell? */ 4121 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4122 mqd->cp_hqd_pq_doorbell_control); 4123 4124 /* disable the queue if it's active */ 4125 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4126 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4127 for (j = 0; j < adev->usec_timeout; j++) { 4128 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4129 break; 4130 udelay(1); 4131 } 4132 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4133 mqd->cp_hqd_dequeue_request); 4134 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4135 mqd->cp_hqd_pq_rptr); 4136 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4137 mqd->cp_hqd_pq_wptr_lo); 4138 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4139 mqd->cp_hqd_pq_wptr_hi); 4140 } 4141 4142 /* set the pointer to the MQD */ 4143 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4144 mqd->cp_mqd_base_addr_lo); 4145 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4146 mqd->cp_mqd_base_addr_hi); 4147 4148 /* set MQD vmid to 0 */ 4149 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4150 mqd->cp_mqd_control); 4151 4152 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4153 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4154 mqd->cp_hqd_pq_base_lo); 4155 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4156 mqd->cp_hqd_pq_base_hi); 4157 4158 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4159 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4160 mqd->cp_hqd_pq_control); 4161 4162 /* set the wb address whether it's enabled or not */ 4163 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4164 mqd->cp_hqd_pq_rptr_report_addr_lo); 4165 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4166 mqd->cp_hqd_pq_rptr_report_addr_hi); 4167 4168 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4169 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4170 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4171 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4172 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4173 4174 /* enable the doorbell if requested */ 4175 if (ring->use_doorbell) { 4176 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4177 (adev->doorbell_index.kiq * 2) << 2); 4178 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4179 (adev->doorbell_index.userqueue_end * 2) << 2); 4180 } 4181 4182 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4183 mqd->cp_hqd_pq_doorbell_control); 4184 4185 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4186 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4187 mqd->cp_hqd_pq_wptr_lo); 4188 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4189 mqd->cp_hqd_pq_wptr_hi); 4190 4191 /* set the vmid for the queue */ 4192 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4193 4194 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4195 mqd->cp_hqd_persistent_state); 4196 4197 /* activate the queue */ 4198 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4199 mqd->cp_hqd_active); 4200 4201 if (ring->use_doorbell) 4202 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4203 4204 return 0; 4205 } 4206 4207 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4208 { 4209 struct amdgpu_device *adev = ring->adev; 4210 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4211 4212 gfx_v11_0_kiq_setting(ring); 4213 4214 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4215 /* reset MQD to a clean status */ 4216 if (adev->gfx.kiq[0].mqd_backup) 4217 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4218 4219 /* reset ring buffer */ 4220 ring->wptr = 0; 4221 amdgpu_ring_clear_ring(ring); 4222 4223 mutex_lock(&adev->srbm_mutex); 4224 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4225 gfx_v11_0_kiq_init_register(ring); 4226 soc21_grbm_select(adev, 0, 0, 0, 0); 4227 mutex_unlock(&adev->srbm_mutex); 4228 } else { 4229 memset((void *)mqd, 0, sizeof(*mqd)); 4230 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4231 amdgpu_ring_clear_ring(ring); 4232 mutex_lock(&adev->srbm_mutex); 4233 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4234 amdgpu_ring_init_mqd(ring); 4235 gfx_v11_0_kiq_init_register(ring); 4236 soc21_grbm_select(adev, 0, 0, 0, 0); 4237 mutex_unlock(&adev->srbm_mutex); 4238 4239 if (adev->gfx.kiq[0].mqd_backup) 4240 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4241 } 4242 4243 return 0; 4244 } 4245 4246 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4247 { 4248 struct amdgpu_device *adev = ring->adev; 4249 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4250 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4251 4252 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4253 memset((void *)mqd, 0, sizeof(*mqd)); 4254 mutex_lock(&adev->srbm_mutex); 4255 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4256 amdgpu_ring_init_mqd(ring); 4257 soc21_grbm_select(adev, 0, 0, 0, 0); 4258 mutex_unlock(&adev->srbm_mutex); 4259 4260 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4261 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4262 } else { 4263 /* restore MQD to a clean status */ 4264 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4265 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4266 /* reset ring buffer */ 4267 ring->wptr = 0; 4268 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4269 amdgpu_ring_clear_ring(ring); 4270 } 4271 4272 return 0; 4273 } 4274 4275 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4276 { 4277 struct amdgpu_ring *ring; 4278 int r; 4279 4280 ring = &adev->gfx.kiq[0].ring; 4281 4282 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4283 if (unlikely(r != 0)) 4284 return r; 4285 4286 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4287 if (unlikely(r != 0)) { 4288 amdgpu_bo_unreserve(ring->mqd_obj); 4289 return r; 4290 } 4291 4292 gfx_v11_0_kiq_init_queue(ring); 4293 amdgpu_bo_kunmap(ring->mqd_obj); 4294 ring->mqd_ptr = NULL; 4295 amdgpu_bo_unreserve(ring->mqd_obj); 4296 ring->sched.ready = true; 4297 return 0; 4298 } 4299 4300 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4301 { 4302 struct amdgpu_ring *ring = NULL; 4303 int r = 0, i; 4304 4305 if (!amdgpu_async_gfx_ring) 4306 gfx_v11_0_cp_compute_enable(adev, true); 4307 4308 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4309 ring = &adev->gfx.compute_ring[i]; 4310 4311 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4312 if (unlikely(r != 0)) 4313 goto done; 4314 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4315 if (!r) { 4316 r = gfx_v11_0_kcq_init_queue(ring); 4317 amdgpu_bo_kunmap(ring->mqd_obj); 4318 ring->mqd_ptr = NULL; 4319 } 4320 amdgpu_bo_unreserve(ring->mqd_obj); 4321 if (r) 4322 goto done; 4323 } 4324 4325 r = amdgpu_gfx_enable_kcq(adev, 0); 4326 done: 4327 return r; 4328 } 4329 4330 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4331 { 4332 int r, i; 4333 struct amdgpu_ring *ring; 4334 4335 if (!(adev->flags & AMD_IS_APU)) 4336 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4337 4338 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4339 /* legacy firmware loading */ 4340 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4341 if (r) 4342 return r; 4343 4344 if (adev->gfx.rs64_enable) 4345 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4346 else 4347 r = gfx_v11_0_cp_compute_load_microcode(adev); 4348 if (r) 4349 return r; 4350 } 4351 4352 gfx_v11_0_cp_set_doorbell_range(adev); 4353 4354 if (amdgpu_async_gfx_ring) { 4355 gfx_v11_0_cp_compute_enable(adev, true); 4356 gfx_v11_0_cp_gfx_enable(adev, true); 4357 } 4358 4359 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4360 r = amdgpu_mes_kiq_hw_init(adev); 4361 else 4362 r = gfx_v11_0_kiq_resume(adev); 4363 if (r) 4364 return r; 4365 4366 r = gfx_v11_0_kcq_resume(adev); 4367 if (r) 4368 return r; 4369 4370 if (!amdgpu_async_gfx_ring) { 4371 r = gfx_v11_0_cp_gfx_resume(adev); 4372 if (r) 4373 return r; 4374 } else { 4375 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4376 if (r) 4377 return r; 4378 } 4379 4380 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4381 ring = &adev->gfx.gfx_ring[i]; 4382 r = amdgpu_ring_test_helper(ring); 4383 if (r) 4384 return r; 4385 } 4386 4387 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4388 ring = &adev->gfx.compute_ring[i]; 4389 r = amdgpu_ring_test_helper(ring); 4390 if (r) 4391 return r; 4392 } 4393 4394 return 0; 4395 } 4396 4397 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4398 { 4399 gfx_v11_0_cp_gfx_enable(adev, enable); 4400 gfx_v11_0_cp_compute_enable(adev, enable); 4401 } 4402 4403 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4404 { 4405 int r; 4406 bool value; 4407 4408 r = adev->gfxhub.funcs->gart_enable(adev); 4409 if (r) 4410 return r; 4411 4412 adev->hdp.funcs->flush_hdp(adev, NULL); 4413 4414 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4415 false : true; 4416 4417 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4418 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4419 4420 return 0; 4421 } 4422 4423 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4424 { 4425 u32 tmp; 4426 4427 /* select RS64 */ 4428 if (adev->gfx.rs64_enable) { 4429 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4430 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4431 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4432 4433 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4434 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4435 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4436 } 4437 4438 if (amdgpu_emu_mode == 1) 4439 msleep(100); 4440 } 4441 4442 static int get_gb_addr_config(struct amdgpu_device * adev) 4443 { 4444 u32 gb_addr_config; 4445 4446 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4447 if (gb_addr_config == 0) 4448 return -EINVAL; 4449 4450 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4451 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4452 4453 adev->gfx.config.gb_addr_config = gb_addr_config; 4454 4455 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4456 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4457 GB_ADDR_CONFIG, NUM_PIPES); 4458 4459 adev->gfx.config.max_tile_pipes = 4460 adev->gfx.config.gb_addr_config_fields.num_pipes; 4461 4462 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4463 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4464 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4465 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4466 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4467 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4468 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4469 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4470 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4471 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4472 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4473 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4474 4475 return 0; 4476 } 4477 4478 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4479 { 4480 uint32_t data; 4481 4482 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4483 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4484 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4485 4486 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4487 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4488 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4489 } 4490 4491 static int gfx_v11_0_hw_init(void *handle) 4492 { 4493 int r; 4494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4495 4496 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4497 if (adev->gfx.imu.funcs) { 4498 /* RLC autoload sequence 1: Program rlc ram */ 4499 if (adev->gfx.imu.funcs->program_rlc_ram) 4500 adev->gfx.imu.funcs->program_rlc_ram(adev); 4501 } 4502 /* rlc autoload firmware */ 4503 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4504 if (r) 4505 return r; 4506 } else { 4507 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4508 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4509 if (adev->gfx.imu.funcs->load_microcode) 4510 adev->gfx.imu.funcs->load_microcode(adev); 4511 if (adev->gfx.imu.funcs->setup_imu) 4512 adev->gfx.imu.funcs->setup_imu(adev); 4513 if (adev->gfx.imu.funcs->start_imu) 4514 adev->gfx.imu.funcs->start_imu(adev); 4515 } 4516 4517 /* disable gpa mode in backdoor loading */ 4518 gfx_v11_0_disable_gpa_mode(adev); 4519 } 4520 } 4521 4522 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4523 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4524 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4525 if (r) { 4526 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4527 return r; 4528 } 4529 } 4530 4531 adev->gfx.is_poweron = true; 4532 4533 if(get_gb_addr_config(adev)) 4534 DRM_WARN("Invalid gb_addr_config !\n"); 4535 4536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4537 adev->gfx.rs64_enable) 4538 gfx_v11_0_config_gfx_rs64(adev); 4539 4540 r = gfx_v11_0_gfxhub_enable(adev); 4541 if (r) 4542 return r; 4543 4544 if (!amdgpu_emu_mode) 4545 gfx_v11_0_init_golden_registers(adev); 4546 4547 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4548 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4549 /** 4550 * For gfx 11, rlc firmware loading relies on smu firmware is 4551 * loaded firstly, so in direct type, it has to load smc ucode 4552 * here before rlc. 4553 */ 4554 if (!(adev->flags & AMD_IS_APU)) { 4555 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4556 if (r) 4557 return r; 4558 } 4559 } 4560 4561 gfx_v11_0_constants_init(adev); 4562 4563 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4564 gfx_v11_0_select_cp_fw_arch(adev); 4565 4566 if (adev->nbio.funcs->gc_doorbell_init) 4567 adev->nbio.funcs->gc_doorbell_init(adev); 4568 4569 r = gfx_v11_0_rlc_resume(adev); 4570 if (r) 4571 return r; 4572 4573 /* 4574 * init golden registers and rlc resume may override some registers, 4575 * reconfig them here 4576 */ 4577 gfx_v11_0_tcp_harvest(adev); 4578 4579 r = gfx_v11_0_cp_resume(adev); 4580 if (r) 4581 return r; 4582 4583 /* get IMU version from HW if it's not set */ 4584 if (!adev->gfx.imu_fw_version) 4585 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4586 4587 return r; 4588 } 4589 4590 static int gfx_v11_0_hw_fini(void *handle) 4591 { 4592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4593 4594 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4595 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4596 4597 if (!adev->no_hw_access) { 4598 if (amdgpu_async_gfx_ring) { 4599 if (amdgpu_gfx_disable_kgq(adev, 0)) 4600 DRM_ERROR("KGQ disable failed\n"); 4601 } 4602 4603 if (amdgpu_gfx_disable_kcq(adev, 0)) 4604 DRM_ERROR("KCQ disable failed\n"); 4605 4606 amdgpu_mes_kiq_hw_fini(adev); 4607 } 4608 4609 if (amdgpu_sriov_vf(adev)) 4610 /* Remove the steps disabling CPG and clearing KIQ position, 4611 * so that CP could perform IDLE-SAVE during switch. Those 4612 * steps are necessary to avoid a DMAR error in gfx9 but it is 4613 * not reproduced on gfx11. 4614 */ 4615 return 0; 4616 4617 gfx_v11_0_cp_enable(adev, false); 4618 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4619 4620 adev->gfxhub.funcs->gart_disable(adev); 4621 4622 adev->gfx.is_poweron = false; 4623 4624 return 0; 4625 } 4626 4627 static int gfx_v11_0_suspend(void *handle) 4628 { 4629 return gfx_v11_0_hw_fini(handle); 4630 } 4631 4632 static int gfx_v11_0_resume(void *handle) 4633 { 4634 return gfx_v11_0_hw_init(handle); 4635 } 4636 4637 static bool gfx_v11_0_is_idle(void *handle) 4638 { 4639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4640 4641 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4642 GRBM_STATUS, GUI_ACTIVE)) 4643 return false; 4644 else 4645 return true; 4646 } 4647 4648 static int gfx_v11_0_wait_for_idle(void *handle) 4649 { 4650 unsigned i; 4651 u32 tmp; 4652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4653 4654 for (i = 0; i < adev->usec_timeout; i++) { 4655 /* read MC_STATUS */ 4656 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4657 GRBM_STATUS__GUI_ACTIVE_MASK; 4658 4659 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4660 return 0; 4661 udelay(1); 4662 } 4663 return -ETIMEDOUT; 4664 } 4665 4666 static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4667 int req) 4668 { 4669 u32 i, tmp, val; 4670 4671 for (i = 0; i < adev->usec_timeout; i++) { 4672 /* Request with MeId=2, PipeId=0 */ 4673 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4674 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4675 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4676 4677 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4678 if (req) { 4679 if (val == tmp) 4680 break; 4681 } else { 4682 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4683 REQUEST, 1); 4684 4685 /* unlocked or locked by firmware */ 4686 if (val != tmp) 4687 break; 4688 } 4689 udelay(1); 4690 } 4691 4692 if (i >= adev->usec_timeout) 4693 return -EINVAL; 4694 4695 return 0; 4696 } 4697 4698 static int gfx_v11_0_soft_reset(void *handle) 4699 { 4700 u32 grbm_soft_reset = 0; 4701 u32 tmp; 4702 int r, i, j, k; 4703 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4704 4705 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4706 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4707 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4708 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4709 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4710 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4711 4712 gfx_v11_0_set_safe_mode(adev, 0); 4713 4714 mutex_lock(&adev->srbm_mutex); 4715 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4716 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4717 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4718 soc21_grbm_select(adev, i, k, j, 0); 4719 4720 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4721 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4722 } 4723 } 4724 } 4725 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4726 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4727 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4728 soc21_grbm_select(adev, i, k, j, 0); 4729 4730 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4731 } 4732 } 4733 } 4734 soc21_grbm_select(adev, 0, 0, 0, 0); 4735 mutex_unlock(&adev->srbm_mutex); 4736 4737 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4738 r = gfx_v11_0_request_gfx_index_mutex(adev, 1); 4739 if (r) { 4740 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 4741 return r; 4742 } 4743 4744 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4745 4746 // Read CP_VMID_RESET register three times. 4747 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4748 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4749 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4750 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4751 4752 /* release the gfx mutex */ 4753 r = gfx_v11_0_request_gfx_index_mutex(adev, 0); 4754 if (r) { 4755 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 4756 return r; 4757 } 4758 4759 for (i = 0; i < adev->usec_timeout; i++) { 4760 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4761 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4762 break; 4763 udelay(1); 4764 } 4765 if (i >= adev->usec_timeout) { 4766 printk("Failed to wait all pipes clean\n"); 4767 return -EINVAL; 4768 } 4769 4770 /********** trigger soft reset ***********/ 4771 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4772 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4773 SOFT_RESET_CP, 1); 4774 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4775 SOFT_RESET_GFX, 1); 4776 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4777 SOFT_RESET_CPF, 1); 4778 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4779 SOFT_RESET_CPC, 1); 4780 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4781 SOFT_RESET_CPG, 1); 4782 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4783 /********** exit soft reset ***********/ 4784 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4785 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4786 SOFT_RESET_CP, 0); 4787 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4788 SOFT_RESET_GFX, 0); 4789 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4790 SOFT_RESET_CPF, 0); 4791 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4792 SOFT_RESET_CPC, 0); 4793 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4794 SOFT_RESET_CPG, 0); 4795 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4796 4797 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4798 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4799 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4800 4801 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4802 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4803 4804 for (i = 0; i < adev->usec_timeout; i++) { 4805 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4806 break; 4807 udelay(1); 4808 } 4809 if (i >= adev->usec_timeout) { 4810 printk("Failed to wait CP_VMID_RESET to 0\n"); 4811 return -EINVAL; 4812 } 4813 4814 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4815 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4816 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4817 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4818 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4819 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4820 4821 gfx_v11_0_unset_safe_mode(adev, 0); 4822 4823 return gfx_v11_0_cp_resume(adev); 4824 } 4825 4826 static bool gfx_v11_0_check_soft_reset(void *handle) 4827 { 4828 int i, r; 4829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4830 struct amdgpu_ring *ring; 4831 long tmo = msecs_to_jiffies(1000); 4832 4833 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4834 ring = &adev->gfx.gfx_ring[i]; 4835 r = amdgpu_ring_test_ib(ring, tmo); 4836 if (r) 4837 return true; 4838 } 4839 4840 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4841 ring = &adev->gfx.compute_ring[i]; 4842 r = amdgpu_ring_test_ib(ring, tmo); 4843 if (r) 4844 return true; 4845 } 4846 4847 return false; 4848 } 4849 4850 static int gfx_v11_0_post_soft_reset(void *handle) 4851 { 4852 /** 4853 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4854 */ 4855 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4856 } 4857 4858 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4859 { 4860 uint64_t clock; 4861 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4862 4863 if (amdgpu_sriov_vf(adev)) { 4864 amdgpu_gfx_off_ctrl(adev, false); 4865 mutex_lock(&adev->gfx.gpu_clock_mutex); 4866 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4867 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4868 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4869 if (clock_counter_hi_pre != clock_counter_hi_after) 4870 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4871 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4872 amdgpu_gfx_off_ctrl(adev, true); 4873 } else { 4874 preempt_disable(); 4875 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4876 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4877 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4878 if (clock_counter_hi_pre != clock_counter_hi_after) 4879 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4880 preempt_enable(); 4881 } 4882 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4883 4884 return clock; 4885 } 4886 4887 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4888 uint32_t vmid, 4889 uint32_t gds_base, uint32_t gds_size, 4890 uint32_t gws_base, uint32_t gws_size, 4891 uint32_t oa_base, uint32_t oa_size) 4892 { 4893 struct amdgpu_device *adev = ring->adev; 4894 4895 /* GDS Base */ 4896 gfx_v11_0_write_data_to_reg(ring, 0, false, 4897 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4898 gds_base); 4899 4900 /* GDS Size */ 4901 gfx_v11_0_write_data_to_reg(ring, 0, false, 4902 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4903 gds_size); 4904 4905 /* GWS */ 4906 gfx_v11_0_write_data_to_reg(ring, 0, false, 4907 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4908 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4909 4910 /* OA */ 4911 gfx_v11_0_write_data_to_reg(ring, 0, false, 4912 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4913 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4914 } 4915 4916 static int gfx_v11_0_early_init(void *handle) 4917 { 4918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4919 4920 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4921 4922 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4923 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4924 AMDGPU_MAX_COMPUTE_RINGS); 4925 4926 gfx_v11_0_set_kiq_pm4_funcs(adev); 4927 gfx_v11_0_set_ring_funcs(adev); 4928 gfx_v11_0_set_irq_funcs(adev); 4929 gfx_v11_0_set_gds_init(adev); 4930 gfx_v11_0_set_rlc_funcs(adev); 4931 gfx_v11_0_set_mqd_funcs(adev); 4932 gfx_v11_0_set_imu_funcs(adev); 4933 4934 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4935 4936 return gfx_v11_0_init_microcode(adev); 4937 } 4938 4939 static int gfx_v11_0_late_init(void *handle) 4940 { 4941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4942 int r; 4943 4944 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4945 if (r) 4946 return r; 4947 4948 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4949 if (r) 4950 return r; 4951 4952 return 0; 4953 } 4954 4955 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4956 { 4957 uint32_t rlc_cntl; 4958 4959 /* if RLC is not enabled, do nothing */ 4960 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4961 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4962 } 4963 4964 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4965 { 4966 uint32_t data; 4967 unsigned i; 4968 4969 data = RLC_SAFE_MODE__CMD_MASK; 4970 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4971 4972 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4973 4974 /* wait for RLC_SAFE_MODE */ 4975 for (i = 0; i < adev->usec_timeout; i++) { 4976 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4977 RLC_SAFE_MODE, CMD)) 4978 break; 4979 udelay(1); 4980 } 4981 } 4982 4983 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4984 { 4985 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4986 } 4987 4988 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4989 bool enable) 4990 { 4991 uint32_t def, data; 4992 4993 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4994 return; 4995 4996 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4997 4998 if (enable) 4999 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5000 else 5001 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5002 5003 if (def != data) 5004 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5005 } 5006 5007 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5008 bool enable) 5009 { 5010 uint32_t def, data; 5011 5012 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5013 return; 5014 5015 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5016 5017 if (enable) 5018 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5019 else 5020 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5021 5022 if (def != data) 5023 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5024 } 5025 5026 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5027 bool enable) 5028 { 5029 uint32_t def, data; 5030 5031 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5032 return; 5033 5034 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5035 5036 if (enable) 5037 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5038 else 5039 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5040 5041 if (def != data) 5042 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5043 } 5044 5045 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5046 bool enable) 5047 { 5048 uint32_t data, def; 5049 5050 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5051 return; 5052 5053 /* It is disabled by HW by default */ 5054 if (enable) { 5055 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5056 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5057 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5058 5059 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5060 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5061 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5062 5063 if (def != data) 5064 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5065 } 5066 } else { 5067 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5068 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5069 5070 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5071 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5072 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5073 5074 if (def != data) 5075 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5076 } 5077 } 5078 } 5079 5080 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5081 bool enable) 5082 { 5083 uint32_t def, data; 5084 5085 if (!(adev->cg_flags & 5086 (AMD_CG_SUPPORT_GFX_CGCG | 5087 AMD_CG_SUPPORT_GFX_CGLS | 5088 AMD_CG_SUPPORT_GFX_3D_CGCG | 5089 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5090 return; 5091 5092 if (enable) { 5093 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5094 5095 /* unset CGCG override */ 5096 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5097 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5098 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5099 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5100 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5101 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5102 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5103 5104 /* update CGCG override bits */ 5105 if (def != data) 5106 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5107 5108 /* enable cgcg FSM(0x0000363F) */ 5109 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5110 5111 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5112 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5113 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5114 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5115 } 5116 5117 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5118 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5119 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5120 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5121 } 5122 5123 if (def != data) 5124 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5125 5126 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5127 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5128 5129 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5130 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5131 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5132 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5133 } 5134 5135 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5136 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5137 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5138 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5139 } 5140 5141 if (def != data) 5142 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5143 5144 /* set IDLE_POLL_COUNT(0x00900100) */ 5145 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5146 5147 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5148 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5149 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5150 5151 if (def != data) 5152 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5153 5154 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5155 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5156 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5157 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5158 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5159 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5160 5161 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5162 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5163 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5164 5165 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5166 if (adev->sdma.num_instances > 1) { 5167 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5168 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5169 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5170 } 5171 } else { 5172 /* Program RLC_CGCG_CGLS_CTRL */ 5173 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5174 5175 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5176 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5177 5178 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5179 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5180 5181 if (def != data) 5182 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5183 5184 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5185 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5186 5187 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5188 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5189 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5190 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5191 5192 if (def != data) 5193 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5194 5195 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5196 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5197 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5198 5199 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5200 if (adev->sdma.num_instances > 1) { 5201 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5202 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5203 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5204 } 5205 } 5206 } 5207 5208 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5209 bool enable) 5210 { 5211 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5212 5213 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5214 5215 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5216 5217 gfx_v11_0_update_repeater_fgcg(adev, enable); 5218 5219 gfx_v11_0_update_sram_fgcg(adev, enable); 5220 5221 gfx_v11_0_update_perf_clk(adev, enable); 5222 5223 if (adev->cg_flags & 5224 (AMD_CG_SUPPORT_GFX_MGCG | 5225 AMD_CG_SUPPORT_GFX_CGLS | 5226 AMD_CG_SUPPORT_GFX_CGCG | 5227 AMD_CG_SUPPORT_GFX_3D_CGCG | 5228 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5229 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5230 5231 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5232 5233 return 0; 5234 } 5235 5236 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5237 { 5238 u32 reg, pre_data, data; 5239 5240 amdgpu_gfx_off_ctrl(adev, false); 5241 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5242 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5243 pre_data = RREG32_NO_KIQ(reg); 5244 else 5245 pre_data = RREG32(reg); 5246 5247 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5248 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5249 5250 if (pre_data != data) { 5251 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5252 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5253 } else 5254 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5255 } 5256 amdgpu_gfx_off_ctrl(adev, true); 5257 5258 if (ring 5259 && amdgpu_sriov_is_pp_one_vf(adev) 5260 && (pre_data != data) 5261 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5262 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5263 amdgpu_ring_emit_wreg(ring, reg, data); 5264 } 5265 } 5266 5267 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5268 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5269 .set_safe_mode = gfx_v11_0_set_safe_mode, 5270 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5271 .init = gfx_v11_0_rlc_init, 5272 .get_csb_size = gfx_v11_0_get_csb_size, 5273 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5274 .resume = gfx_v11_0_rlc_resume, 5275 .stop = gfx_v11_0_rlc_stop, 5276 .reset = gfx_v11_0_rlc_reset, 5277 .start = gfx_v11_0_rlc_start, 5278 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5279 }; 5280 5281 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5282 { 5283 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5284 5285 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5286 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5287 else 5288 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5289 5290 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5291 5292 // Program RLC_PG_DELAY3 for CGPG hysteresis 5293 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5294 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5295 case IP_VERSION(11, 0, 1): 5296 case IP_VERSION(11, 0, 4): 5297 case IP_VERSION(11, 5, 0): 5298 case IP_VERSION(11, 5, 1): 5299 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5300 break; 5301 default: 5302 break; 5303 } 5304 } 5305 } 5306 5307 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5308 { 5309 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5310 5311 gfx_v11_cntl_power_gating(adev, enable); 5312 5313 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5314 } 5315 5316 static int gfx_v11_0_set_powergating_state(void *handle, 5317 enum amd_powergating_state state) 5318 { 5319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5320 bool enable = (state == AMD_PG_STATE_GATE); 5321 5322 if (amdgpu_sriov_vf(adev)) 5323 return 0; 5324 5325 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5326 case IP_VERSION(11, 0, 0): 5327 case IP_VERSION(11, 0, 2): 5328 case IP_VERSION(11, 0, 3): 5329 amdgpu_gfx_off_ctrl(adev, enable); 5330 break; 5331 case IP_VERSION(11, 0, 1): 5332 case IP_VERSION(11, 0, 4): 5333 case IP_VERSION(11, 5, 0): 5334 case IP_VERSION(11, 5, 1): 5335 if (!enable) 5336 amdgpu_gfx_off_ctrl(adev, false); 5337 5338 gfx_v11_cntl_pg(adev, enable); 5339 5340 if (enable) 5341 amdgpu_gfx_off_ctrl(adev, true); 5342 5343 break; 5344 default: 5345 break; 5346 } 5347 5348 return 0; 5349 } 5350 5351 static int gfx_v11_0_set_clockgating_state(void *handle, 5352 enum amd_clockgating_state state) 5353 { 5354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5355 5356 if (amdgpu_sriov_vf(adev)) 5357 return 0; 5358 5359 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5360 case IP_VERSION(11, 0, 0): 5361 case IP_VERSION(11, 0, 1): 5362 case IP_VERSION(11, 0, 2): 5363 case IP_VERSION(11, 0, 3): 5364 case IP_VERSION(11, 0, 4): 5365 case IP_VERSION(11, 5, 0): 5366 case IP_VERSION(11, 5, 1): 5367 gfx_v11_0_update_gfx_clock_gating(adev, 5368 state == AMD_CG_STATE_GATE); 5369 break; 5370 default: 5371 break; 5372 } 5373 5374 return 0; 5375 } 5376 5377 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5378 { 5379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5380 int data; 5381 5382 /* AMD_CG_SUPPORT_GFX_MGCG */ 5383 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5384 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5385 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5386 5387 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5388 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5389 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5390 5391 /* AMD_CG_SUPPORT_GFX_FGCG */ 5392 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5393 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5394 5395 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5396 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5397 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5398 5399 /* AMD_CG_SUPPORT_GFX_CGCG */ 5400 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5401 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5402 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5403 5404 /* AMD_CG_SUPPORT_GFX_CGLS */ 5405 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5406 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5407 5408 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5409 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5410 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5411 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5412 5413 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5414 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5415 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5416 } 5417 5418 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5419 { 5420 /* gfx11 is 32bit rptr*/ 5421 return *(uint32_t *)ring->rptr_cpu_addr; 5422 } 5423 5424 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5425 { 5426 struct amdgpu_device *adev = ring->adev; 5427 u64 wptr; 5428 5429 /* XXX check if swapping is necessary on BE */ 5430 if (ring->use_doorbell) { 5431 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5432 } else { 5433 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5434 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5435 } 5436 5437 return wptr; 5438 } 5439 5440 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5441 { 5442 struct amdgpu_device *adev = ring->adev; 5443 5444 if (ring->use_doorbell) { 5445 /* XXX check if swapping is necessary on BE */ 5446 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5447 ring->wptr); 5448 WDOORBELL64(ring->doorbell_index, ring->wptr); 5449 } else { 5450 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5451 lower_32_bits(ring->wptr)); 5452 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5453 upper_32_bits(ring->wptr)); 5454 } 5455 } 5456 5457 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5458 { 5459 /* gfx11 hardware is 32bit rptr */ 5460 return *(uint32_t *)ring->rptr_cpu_addr; 5461 } 5462 5463 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5464 { 5465 u64 wptr; 5466 5467 /* XXX check if swapping is necessary on BE */ 5468 if (ring->use_doorbell) 5469 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5470 else 5471 BUG(); 5472 return wptr; 5473 } 5474 5475 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5476 { 5477 struct amdgpu_device *adev = ring->adev; 5478 5479 /* XXX check if swapping is necessary on BE */ 5480 if (ring->use_doorbell) { 5481 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5482 ring->wptr); 5483 WDOORBELL64(ring->doorbell_index, ring->wptr); 5484 } else { 5485 BUG(); /* only DOORBELL method supported on gfx11 now */ 5486 } 5487 } 5488 5489 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5490 { 5491 struct amdgpu_device *adev = ring->adev; 5492 u32 ref_and_mask, reg_mem_engine; 5493 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5494 5495 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5496 switch (ring->me) { 5497 case 1: 5498 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5499 break; 5500 case 2: 5501 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5502 break; 5503 default: 5504 return; 5505 } 5506 reg_mem_engine = 0; 5507 } else { 5508 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5509 reg_mem_engine = 1; /* pfp */ 5510 } 5511 5512 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5513 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5514 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5515 ref_and_mask, ref_and_mask, 0x20); 5516 } 5517 5518 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5519 struct amdgpu_job *job, 5520 struct amdgpu_ib *ib, 5521 uint32_t flags) 5522 { 5523 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5524 u32 header, control = 0; 5525 5526 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5527 5528 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5529 5530 control |= ib->length_dw | (vmid << 24); 5531 5532 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5533 control |= INDIRECT_BUFFER_PRE_ENB(1); 5534 5535 if (flags & AMDGPU_IB_PREEMPTED) 5536 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5537 5538 if (vmid) 5539 gfx_v11_0_ring_emit_de_meta(ring, 5540 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5541 } 5542 5543 if (ring->is_mes_queue) 5544 /* inherit vmid from mqd */ 5545 control |= 0x400000; 5546 5547 amdgpu_ring_write(ring, header); 5548 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5549 amdgpu_ring_write(ring, 5550 #ifdef __BIG_ENDIAN 5551 (2 << 0) | 5552 #endif 5553 lower_32_bits(ib->gpu_addr)); 5554 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5555 amdgpu_ring_write(ring, control); 5556 } 5557 5558 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5559 struct amdgpu_job *job, 5560 struct amdgpu_ib *ib, 5561 uint32_t flags) 5562 { 5563 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5564 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5565 5566 if (ring->is_mes_queue) 5567 /* inherit vmid from mqd */ 5568 control |= 0x40000000; 5569 5570 /* Currently, there is a high possibility to get wave ID mismatch 5571 * between ME and GDS, leading to a hw deadlock, because ME generates 5572 * different wave IDs than the GDS expects. This situation happens 5573 * randomly when at least 5 compute pipes use GDS ordered append. 5574 * The wave IDs generated by ME are also wrong after suspend/resume. 5575 * Those are probably bugs somewhere else in the kernel driver. 5576 * 5577 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5578 * GDS to 0 for this ring (me/pipe). 5579 */ 5580 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5581 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5582 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5583 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5584 } 5585 5586 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5587 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5588 amdgpu_ring_write(ring, 5589 #ifdef __BIG_ENDIAN 5590 (2 << 0) | 5591 #endif 5592 lower_32_bits(ib->gpu_addr)); 5593 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5594 amdgpu_ring_write(ring, control); 5595 } 5596 5597 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5598 u64 seq, unsigned flags) 5599 { 5600 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5601 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5602 5603 /* RELEASE_MEM - flush caches, send int */ 5604 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5605 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5606 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5607 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5608 PACKET3_RELEASE_MEM_GCR_GL2_US | 5609 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5610 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5611 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5612 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5613 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5614 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5615 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5616 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5617 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5618 5619 /* 5620 * the address should be Qword aligned if 64bit write, Dword 5621 * aligned if only send 32bit data low (discard data high) 5622 */ 5623 if (write64bit) 5624 BUG_ON(addr & 0x7); 5625 else 5626 BUG_ON(addr & 0x3); 5627 amdgpu_ring_write(ring, lower_32_bits(addr)); 5628 amdgpu_ring_write(ring, upper_32_bits(addr)); 5629 amdgpu_ring_write(ring, lower_32_bits(seq)); 5630 amdgpu_ring_write(ring, upper_32_bits(seq)); 5631 amdgpu_ring_write(ring, ring->is_mes_queue ? 5632 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5633 } 5634 5635 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5636 { 5637 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5638 uint32_t seq = ring->fence_drv.sync_seq; 5639 uint64_t addr = ring->fence_drv.gpu_addr; 5640 5641 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5642 upper_32_bits(addr), seq, 0xffffffff, 4); 5643 } 5644 5645 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5646 uint16_t pasid, uint32_t flush_type, 5647 bool all_hub, uint8_t dst_sel) 5648 { 5649 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5650 amdgpu_ring_write(ring, 5651 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5652 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5653 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5654 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5655 } 5656 5657 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5658 unsigned vmid, uint64_t pd_addr) 5659 { 5660 if (ring->is_mes_queue) 5661 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5662 else 5663 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5664 5665 /* compute doesn't have PFP */ 5666 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5667 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5668 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5669 amdgpu_ring_write(ring, 0x0); 5670 } 5671 5672 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5673 * changed in any way. 5674 */ 5675 ring->set_q_mode_offs = 0; 5676 ring->set_q_mode_ptr = NULL; 5677 } 5678 5679 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5680 u64 seq, unsigned int flags) 5681 { 5682 struct amdgpu_device *adev = ring->adev; 5683 5684 /* we only allocate 32bit for each seq wb address */ 5685 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5686 5687 /* write fence seq to the "addr" */ 5688 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5689 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5690 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5691 amdgpu_ring_write(ring, lower_32_bits(addr)); 5692 amdgpu_ring_write(ring, upper_32_bits(addr)); 5693 amdgpu_ring_write(ring, lower_32_bits(seq)); 5694 5695 if (flags & AMDGPU_FENCE_FLAG_INT) { 5696 /* set register to trigger INT */ 5697 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5698 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5699 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5700 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5701 amdgpu_ring_write(ring, 0); 5702 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5703 } 5704 } 5705 5706 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5707 uint32_t flags) 5708 { 5709 uint32_t dw2 = 0; 5710 5711 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5712 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5713 /* set load_global_config & load_global_uconfig */ 5714 dw2 |= 0x8001; 5715 /* set load_cs_sh_regs */ 5716 dw2 |= 0x01000000; 5717 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5718 dw2 |= 0x10002; 5719 } 5720 5721 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5722 amdgpu_ring_write(ring, dw2); 5723 amdgpu_ring_write(ring, 0); 5724 } 5725 5726 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5727 uint64_t addr) 5728 { 5729 unsigned ret; 5730 5731 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5732 amdgpu_ring_write(ring, lower_32_bits(addr)); 5733 amdgpu_ring_write(ring, upper_32_bits(addr)); 5734 /* discard following DWs if *cond_exec_gpu_addr==0 */ 5735 amdgpu_ring_write(ring, 0); 5736 ret = ring->wptr & ring->buf_mask; 5737 /* patch dummy value later */ 5738 amdgpu_ring_write(ring, 0); 5739 5740 return ret; 5741 } 5742 5743 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5744 u64 shadow_va, u64 csa_va, 5745 u64 gds_va, bool init_shadow, 5746 int vmid) 5747 { 5748 struct amdgpu_device *adev = ring->adev; 5749 unsigned int offs, end; 5750 5751 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 5752 return; 5753 5754 /* 5755 * The logic here isn't easy to understand because we need to keep state 5756 * accross multiple executions of the function as well as between the 5757 * CPU and GPU. The general idea is that the newly written GPU command 5758 * has a condition on the previous one and only executed if really 5759 * necessary. 5760 */ 5761 5762 /* 5763 * The dw in the NOP controls if the next SET_Q_MODE packet should be 5764 * executed or not. Reserve 64bits just to be on the save side. 5765 */ 5766 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 5767 offs = ring->wptr & ring->buf_mask; 5768 5769 /* 5770 * We start with skipping the prefix SET_Q_MODE and always executing 5771 * the postfix SET_Q_MODE packet. This is changed below with a 5772 * WRITE_DATA command when the postfix executed. 5773 */ 5774 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 5775 amdgpu_ring_write(ring, 0); 5776 5777 if (ring->set_q_mode_offs) { 5778 uint64_t addr; 5779 5780 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5781 addr += ring->set_q_mode_offs << 2; 5782 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 5783 } 5784 5785 /* 5786 * When the postfix SET_Q_MODE packet executes we need to make sure that the 5787 * next prefix SET_Q_MODE packet executes as well. 5788 */ 5789 if (!shadow_va) { 5790 uint64_t addr; 5791 5792 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5793 addr += offs << 2; 5794 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5795 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 5796 amdgpu_ring_write(ring, lower_32_bits(addr)); 5797 amdgpu_ring_write(ring, upper_32_bits(addr)); 5798 amdgpu_ring_write(ring, 0x1); 5799 } 5800 5801 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5802 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5803 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5804 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5805 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5806 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5807 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5808 amdgpu_ring_write(ring, shadow_va ? 5809 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5810 amdgpu_ring_write(ring, init_shadow ? 5811 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5812 5813 if (ring->set_q_mode_offs) 5814 amdgpu_ring_patch_cond_exec(ring, end); 5815 5816 if (shadow_va) { 5817 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 5818 5819 /* 5820 * If the tokens match try to skip the last postfix SET_Q_MODE 5821 * packet to avoid saving/restoring the state all the time. 5822 */ 5823 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 5824 *ring->set_q_mode_ptr = 0; 5825 5826 ring->set_q_mode_token = token; 5827 } else { 5828 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 5829 } 5830 5831 ring->set_q_mode_offs = offs; 5832 } 5833 5834 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5835 { 5836 int i, r = 0; 5837 struct amdgpu_device *adev = ring->adev; 5838 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5839 struct amdgpu_ring *kiq_ring = &kiq->ring; 5840 unsigned long flags; 5841 5842 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5843 return -EINVAL; 5844 5845 spin_lock_irqsave(&kiq->ring_lock, flags); 5846 5847 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5848 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5849 return -ENOMEM; 5850 } 5851 5852 /* assert preemption condition */ 5853 amdgpu_ring_set_preempt_cond_exec(ring, false); 5854 5855 /* assert IB preemption, emit the trailing fence */ 5856 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5857 ring->trail_fence_gpu_addr, 5858 ++ring->trail_seq); 5859 amdgpu_ring_commit(kiq_ring); 5860 5861 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5862 5863 /* poll the trailing fence */ 5864 for (i = 0; i < adev->usec_timeout; i++) { 5865 if (ring->trail_seq == 5866 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5867 break; 5868 udelay(1); 5869 } 5870 5871 if (i >= adev->usec_timeout) { 5872 r = -EINVAL; 5873 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5874 } 5875 5876 /* deassert preemption condition */ 5877 amdgpu_ring_set_preempt_cond_exec(ring, true); 5878 return r; 5879 } 5880 5881 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5882 { 5883 struct amdgpu_device *adev = ring->adev; 5884 struct v10_de_ib_state de_payload = {0}; 5885 uint64_t offset, gds_addr, de_payload_gpu_addr; 5886 void *de_payload_cpu_addr; 5887 int cnt; 5888 5889 if (ring->is_mes_queue) { 5890 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5891 gfx[0].gfx_meta_data) + 5892 offsetof(struct v10_gfx_meta_data, de_payload); 5893 de_payload_gpu_addr = 5894 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5895 de_payload_cpu_addr = 5896 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5897 5898 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5899 gfx[0].gds_backup) + 5900 offsetof(struct v10_gfx_meta_data, de_payload); 5901 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5902 } else { 5903 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5904 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5905 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5906 5907 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5908 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5909 PAGE_SIZE); 5910 } 5911 5912 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5913 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5914 5915 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5916 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5917 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5918 WRITE_DATA_DST_SEL(8) | 5919 WR_CONFIRM) | 5920 WRITE_DATA_CACHE_POLICY(0)); 5921 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5922 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5923 5924 if (resume) 5925 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5926 sizeof(de_payload) >> 2); 5927 else 5928 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5929 sizeof(de_payload) >> 2); 5930 } 5931 5932 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5933 bool secure) 5934 { 5935 uint32_t v = secure ? FRAME_TMZ : 0; 5936 5937 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5938 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5939 } 5940 5941 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5942 uint32_t reg_val_offs) 5943 { 5944 struct amdgpu_device *adev = ring->adev; 5945 5946 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5947 amdgpu_ring_write(ring, 0 | /* src: register*/ 5948 (5 << 8) | /* dst: memory */ 5949 (1 << 20)); /* write confirm */ 5950 amdgpu_ring_write(ring, reg); 5951 amdgpu_ring_write(ring, 0); 5952 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5953 reg_val_offs * 4)); 5954 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5955 reg_val_offs * 4)); 5956 } 5957 5958 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5959 uint32_t val) 5960 { 5961 uint32_t cmd = 0; 5962 5963 switch (ring->funcs->type) { 5964 case AMDGPU_RING_TYPE_GFX: 5965 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5966 break; 5967 case AMDGPU_RING_TYPE_KIQ: 5968 cmd = (1 << 16); /* no inc addr */ 5969 break; 5970 default: 5971 cmd = WR_CONFIRM; 5972 break; 5973 } 5974 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5975 amdgpu_ring_write(ring, cmd); 5976 amdgpu_ring_write(ring, reg); 5977 amdgpu_ring_write(ring, 0); 5978 amdgpu_ring_write(ring, val); 5979 } 5980 5981 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5982 uint32_t val, uint32_t mask) 5983 { 5984 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5985 } 5986 5987 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5988 uint32_t reg0, uint32_t reg1, 5989 uint32_t ref, uint32_t mask) 5990 { 5991 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5992 5993 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5994 ref, mask, 0x20); 5995 } 5996 5997 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5998 unsigned vmid) 5999 { 6000 struct amdgpu_device *adev = ring->adev; 6001 uint32_t value = 0; 6002 6003 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6004 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6005 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6006 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6007 WREG32_SOC15(GC, 0, regSQ_CMD, value); 6008 } 6009 6010 static void 6011 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6012 uint32_t me, uint32_t pipe, 6013 enum amdgpu_interrupt_state state) 6014 { 6015 uint32_t cp_int_cntl, cp_int_cntl_reg; 6016 6017 if (!me) { 6018 switch (pipe) { 6019 case 0: 6020 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6021 break; 6022 case 1: 6023 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6024 break; 6025 default: 6026 DRM_DEBUG("invalid pipe %d\n", pipe); 6027 return; 6028 } 6029 } else { 6030 DRM_DEBUG("invalid me %d\n", me); 6031 return; 6032 } 6033 6034 switch (state) { 6035 case AMDGPU_IRQ_STATE_DISABLE: 6036 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6037 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6038 TIME_STAMP_INT_ENABLE, 0); 6039 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6040 GENERIC0_INT_ENABLE, 0); 6041 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6042 break; 6043 case AMDGPU_IRQ_STATE_ENABLE: 6044 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6045 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6046 TIME_STAMP_INT_ENABLE, 1); 6047 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6048 GENERIC0_INT_ENABLE, 1); 6049 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6050 break; 6051 default: 6052 break; 6053 } 6054 } 6055 6056 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6057 int me, int pipe, 6058 enum amdgpu_interrupt_state state) 6059 { 6060 u32 mec_int_cntl, mec_int_cntl_reg; 6061 6062 /* 6063 * amdgpu controls only the first MEC. That's why this function only 6064 * handles the setting of interrupts for this specific MEC. All other 6065 * pipes' interrupts are set by amdkfd. 6066 */ 6067 6068 if (me == 1) { 6069 switch (pipe) { 6070 case 0: 6071 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6072 break; 6073 case 1: 6074 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6075 break; 6076 case 2: 6077 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6078 break; 6079 case 3: 6080 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6081 break; 6082 default: 6083 DRM_DEBUG("invalid pipe %d\n", pipe); 6084 return; 6085 } 6086 } else { 6087 DRM_DEBUG("invalid me %d\n", me); 6088 return; 6089 } 6090 6091 switch (state) { 6092 case AMDGPU_IRQ_STATE_DISABLE: 6093 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6094 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6095 TIME_STAMP_INT_ENABLE, 0); 6096 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6097 GENERIC0_INT_ENABLE, 0); 6098 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6099 break; 6100 case AMDGPU_IRQ_STATE_ENABLE: 6101 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6102 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6103 TIME_STAMP_INT_ENABLE, 1); 6104 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6105 GENERIC0_INT_ENABLE, 1); 6106 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6107 break; 6108 default: 6109 break; 6110 } 6111 } 6112 6113 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6114 struct amdgpu_irq_src *src, 6115 unsigned type, 6116 enum amdgpu_interrupt_state state) 6117 { 6118 switch (type) { 6119 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6120 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6121 break; 6122 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6123 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6124 break; 6125 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6126 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6127 break; 6128 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6129 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6130 break; 6131 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6132 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6133 break; 6134 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6135 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6136 break; 6137 default: 6138 break; 6139 } 6140 return 0; 6141 } 6142 6143 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6144 struct amdgpu_irq_src *source, 6145 struct amdgpu_iv_entry *entry) 6146 { 6147 int i; 6148 u8 me_id, pipe_id, queue_id; 6149 struct amdgpu_ring *ring; 6150 uint32_t mes_queue_id = entry->src_data[0]; 6151 6152 DRM_DEBUG("IH: CP EOP\n"); 6153 6154 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6155 struct amdgpu_mes_queue *queue; 6156 6157 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6158 6159 spin_lock(&adev->mes.queue_id_lock); 6160 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6161 if (queue) { 6162 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6163 amdgpu_fence_process(queue->ring); 6164 } 6165 spin_unlock(&adev->mes.queue_id_lock); 6166 } else { 6167 me_id = (entry->ring_id & 0x0c) >> 2; 6168 pipe_id = (entry->ring_id & 0x03) >> 0; 6169 queue_id = (entry->ring_id & 0x70) >> 4; 6170 6171 switch (me_id) { 6172 case 0: 6173 if (pipe_id == 0) 6174 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6175 else 6176 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6177 break; 6178 case 1: 6179 case 2: 6180 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6181 ring = &adev->gfx.compute_ring[i]; 6182 /* Per-queue interrupt is supported for MEC starting from VI. 6183 * The interrupt can only be enabled/disabled per pipe instead 6184 * of per queue. 6185 */ 6186 if ((ring->me == me_id) && 6187 (ring->pipe == pipe_id) && 6188 (ring->queue == queue_id)) 6189 amdgpu_fence_process(ring); 6190 } 6191 break; 6192 } 6193 } 6194 6195 return 0; 6196 } 6197 6198 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6199 struct amdgpu_irq_src *source, 6200 unsigned type, 6201 enum amdgpu_interrupt_state state) 6202 { 6203 switch (state) { 6204 case AMDGPU_IRQ_STATE_DISABLE: 6205 case AMDGPU_IRQ_STATE_ENABLE: 6206 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6207 PRIV_REG_INT_ENABLE, 6208 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6209 break; 6210 default: 6211 break; 6212 } 6213 6214 return 0; 6215 } 6216 6217 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6218 struct amdgpu_irq_src *source, 6219 unsigned type, 6220 enum amdgpu_interrupt_state state) 6221 { 6222 switch (state) { 6223 case AMDGPU_IRQ_STATE_DISABLE: 6224 case AMDGPU_IRQ_STATE_ENABLE: 6225 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6226 PRIV_INSTR_INT_ENABLE, 6227 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6228 break; 6229 default: 6230 break; 6231 } 6232 6233 return 0; 6234 } 6235 6236 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6237 struct amdgpu_iv_entry *entry) 6238 { 6239 u8 me_id, pipe_id, queue_id; 6240 struct amdgpu_ring *ring; 6241 int i; 6242 6243 me_id = (entry->ring_id & 0x0c) >> 2; 6244 pipe_id = (entry->ring_id & 0x03) >> 0; 6245 queue_id = (entry->ring_id & 0x70) >> 4; 6246 6247 switch (me_id) { 6248 case 0: 6249 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6250 ring = &adev->gfx.gfx_ring[i]; 6251 /* we only enabled 1 gfx queue per pipe for now */ 6252 if (ring->me == me_id && ring->pipe == pipe_id) 6253 drm_sched_fault(&ring->sched); 6254 } 6255 break; 6256 case 1: 6257 case 2: 6258 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6259 ring = &adev->gfx.compute_ring[i]; 6260 if (ring->me == me_id && ring->pipe == pipe_id && 6261 ring->queue == queue_id) 6262 drm_sched_fault(&ring->sched); 6263 } 6264 break; 6265 default: 6266 BUG(); 6267 break; 6268 } 6269 } 6270 6271 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6272 struct amdgpu_irq_src *source, 6273 struct amdgpu_iv_entry *entry) 6274 { 6275 DRM_ERROR("Illegal register access in command stream\n"); 6276 gfx_v11_0_handle_priv_fault(adev, entry); 6277 return 0; 6278 } 6279 6280 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6281 struct amdgpu_irq_src *source, 6282 struct amdgpu_iv_entry *entry) 6283 { 6284 DRM_ERROR("Illegal instruction in command stream\n"); 6285 gfx_v11_0_handle_priv_fault(adev, entry); 6286 return 0; 6287 } 6288 6289 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6290 struct amdgpu_irq_src *source, 6291 struct amdgpu_iv_entry *entry) 6292 { 6293 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6294 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6295 6296 return 0; 6297 } 6298 6299 #if 0 6300 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6301 struct amdgpu_irq_src *src, 6302 unsigned int type, 6303 enum amdgpu_interrupt_state state) 6304 { 6305 uint32_t tmp, target; 6306 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6307 6308 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6309 target += ring->pipe; 6310 6311 switch (type) { 6312 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6313 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6314 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6315 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6316 GENERIC2_INT_ENABLE, 0); 6317 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6318 6319 tmp = RREG32_SOC15_IP(GC, target); 6320 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6321 GENERIC2_INT_ENABLE, 0); 6322 WREG32_SOC15_IP(GC, target, tmp); 6323 } else { 6324 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6325 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6326 GENERIC2_INT_ENABLE, 1); 6327 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6328 6329 tmp = RREG32_SOC15_IP(GC, target); 6330 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6331 GENERIC2_INT_ENABLE, 1); 6332 WREG32_SOC15_IP(GC, target, tmp); 6333 } 6334 break; 6335 default: 6336 BUG(); /* kiq only support GENERIC2_INT now */ 6337 break; 6338 } 6339 return 0; 6340 } 6341 #endif 6342 6343 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6344 { 6345 const unsigned int gcr_cntl = 6346 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6347 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6348 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6349 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6350 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6351 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6352 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6353 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6354 6355 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6356 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6357 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6358 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6359 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6360 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6361 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6362 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6363 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6364 } 6365 6366 static void gfx_v11_ip_print(void *handle, struct drm_printer *p) 6367 { 6368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6369 uint32_t i, j, k, reg, index = 0; 6370 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6371 6372 if (!adev->gfx.ip_dump_core) 6373 return; 6374 6375 for (i = 0; i < reg_count; i++) 6376 drm_printf(p, "%-50s \t 0x%08x\n", 6377 gc_reg_list_11_0[i].reg_name, 6378 adev->gfx.ip_dump_core[i]); 6379 6380 /* print compute queue registers for all instances */ 6381 if (!adev->gfx.ip_dump_cp_queues) 6382 return; 6383 6384 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6385 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6386 adev->gfx.mec.num_mec, 6387 adev->gfx.mec.num_pipe_per_mec, 6388 adev->gfx.mec.num_queue_per_pipe); 6389 6390 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6391 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6392 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6393 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 6394 for (reg = 0; reg < reg_count; reg++) { 6395 drm_printf(p, "%-50s \t 0x%08x\n", 6396 gc_cp_reg_list_11[reg].reg_name, 6397 adev->gfx.ip_dump_cp_queues[index + reg]); 6398 } 6399 index += reg_count; 6400 } 6401 } 6402 } 6403 6404 /* print gfx queue registers for all instances */ 6405 if (!adev->gfx.ip_dump_gfx_queues) 6406 return; 6407 6408 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6409 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 6410 adev->gfx.me.num_me, 6411 adev->gfx.me.num_pipe_per_me, 6412 adev->gfx.me.num_queue_per_pipe); 6413 6414 for (i = 0; i < adev->gfx.me.num_me; i++) { 6415 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6416 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6417 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 6418 for (reg = 0; reg < reg_count; reg++) { 6419 drm_printf(p, "%-50s \t 0x%08x\n", 6420 gc_gfx_queue_reg_list_11[reg].reg_name, 6421 adev->gfx.ip_dump_gfx_queues[index + reg]); 6422 } 6423 index += reg_count; 6424 } 6425 } 6426 } 6427 } 6428 6429 static void gfx_v11_ip_dump(void *handle) 6430 { 6431 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6432 uint32_t i, j, k, reg, index = 0; 6433 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6434 6435 if (!adev->gfx.ip_dump_core) 6436 return; 6437 6438 amdgpu_gfx_off_ctrl(adev, false); 6439 for (i = 0; i < reg_count; i++) 6440 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 6441 amdgpu_gfx_off_ctrl(adev, true); 6442 6443 /* dump compute queue registers for all instances */ 6444 if (!adev->gfx.ip_dump_cp_queues) 6445 return; 6446 6447 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6448 amdgpu_gfx_off_ctrl(adev, false); 6449 mutex_lock(&adev->srbm_mutex); 6450 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6451 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6452 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6453 /* ME0 is for GFX so start from 1 for CP */ 6454 soc21_grbm_select(adev, 1+i, j, k, 0); 6455 for (reg = 0; reg < reg_count; reg++) { 6456 adev->gfx.ip_dump_cp_queues[index + reg] = 6457 RREG32(SOC15_REG_ENTRY_OFFSET( 6458 gc_cp_reg_list_11[reg])); 6459 } 6460 index += reg_count; 6461 } 6462 } 6463 } 6464 soc21_grbm_select(adev, 0, 0, 0, 0); 6465 mutex_unlock(&adev->srbm_mutex); 6466 amdgpu_gfx_off_ctrl(adev, true); 6467 6468 /* dump gfx queue registers for all instances */ 6469 if (!adev->gfx.ip_dump_gfx_queues) 6470 return; 6471 6472 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6473 amdgpu_gfx_off_ctrl(adev, false); 6474 mutex_lock(&adev->srbm_mutex); 6475 for (i = 0; i < adev->gfx.me.num_me; i++) { 6476 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6477 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6478 soc21_grbm_select(adev, i, j, k, 0); 6479 6480 for (reg = 0; reg < reg_count; reg++) { 6481 adev->gfx.ip_dump_gfx_queues[index + reg] = 6482 RREG32(SOC15_REG_ENTRY_OFFSET( 6483 gc_gfx_queue_reg_list_11[reg])); 6484 } 6485 index += reg_count; 6486 } 6487 } 6488 } 6489 soc21_grbm_select(adev, 0, 0, 0, 0); 6490 mutex_unlock(&adev->srbm_mutex); 6491 amdgpu_gfx_off_ctrl(adev, true); 6492 } 6493 6494 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6495 .name = "gfx_v11_0", 6496 .early_init = gfx_v11_0_early_init, 6497 .late_init = gfx_v11_0_late_init, 6498 .sw_init = gfx_v11_0_sw_init, 6499 .sw_fini = gfx_v11_0_sw_fini, 6500 .hw_init = gfx_v11_0_hw_init, 6501 .hw_fini = gfx_v11_0_hw_fini, 6502 .suspend = gfx_v11_0_suspend, 6503 .resume = gfx_v11_0_resume, 6504 .is_idle = gfx_v11_0_is_idle, 6505 .wait_for_idle = gfx_v11_0_wait_for_idle, 6506 .soft_reset = gfx_v11_0_soft_reset, 6507 .check_soft_reset = gfx_v11_0_check_soft_reset, 6508 .post_soft_reset = gfx_v11_0_post_soft_reset, 6509 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6510 .set_powergating_state = gfx_v11_0_set_powergating_state, 6511 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6512 .dump_ip_state = gfx_v11_ip_dump, 6513 .print_ip_state = gfx_v11_ip_print, 6514 }; 6515 6516 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6517 .type = AMDGPU_RING_TYPE_GFX, 6518 .align_mask = 0xff, 6519 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6520 .support_64bit_ptrs = true, 6521 .secure_submission_supported = true, 6522 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6523 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6524 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6525 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 6526 5 + /* update_spm_vmid */ 6527 5 + /* COND_EXEC */ 6528 22 + /* SET_Q_PREEMPTION_MODE */ 6529 7 + /* PIPELINE_SYNC */ 6530 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6531 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6532 4 + /* VM_FLUSH */ 6533 8 + /* FENCE for VM_FLUSH */ 6534 20 + /* GDS switch */ 6535 5 + /* COND_EXEC */ 6536 7 + /* HDP_flush */ 6537 4 + /* VGT_flush */ 6538 31 + /* DE_META */ 6539 3 + /* CNTX_CTRL */ 6540 5 + /* HDP_INVL */ 6541 22 + /* SET_Q_PREEMPTION_MODE */ 6542 8 + 8 + /* FENCE x2 */ 6543 8, /* gfx_v11_0_emit_mem_sync */ 6544 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6545 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6546 .emit_fence = gfx_v11_0_ring_emit_fence, 6547 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6548 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6549 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6550 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6551 .test_ring = gfx_v11_0_ring_test_ring, 6552 .test_ib = gfx_v11_0_ring_test_ib, 6553 .insert_nop = amdgpu_ring_insert_nop, 6554 .pad_ib = amdgpu_ring_generic_pad_ib, 6555 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6556 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6557 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6558 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6559 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6560 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6561 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6562 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6563 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6564 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6565 }; 6566 6567 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6568 .type = AMDGPU_RING_TYPE_COMPUTE, 6569 .align_mask = 0xff, 6570 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6571 .support_64bit_ptrs = true, 6572 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6573 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6574 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6575 .emit_frame_size = 6576 5 + /* update_spm_vmid */ 6577 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6578 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6579 5 + /* hdp invalidate */ 6580 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6581 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6582 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6583 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6584 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6585 8, /* gfx_v11_0_emit_mem_sync */ 6586 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6587 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6588 .emit_fence = gfx_v11_0_ring_emit_fence, 6589 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6590 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6591 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6592 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6593 .test_ring = gfx_v11_0_ring_test_ring, 6594 .test_ib = gfx_v11_0_ring_test_ib, 6595 .insert_nop = amdgpu_ring_insert_nop, 6596 .pad_ib = amdgpu_ring_generic_pad_ib, 6597 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6598 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6599 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6600 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6601 }; 6602 6603 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6604 .type = AMDGPU_RING_TYPE_KIQ, 6605 .align_mask = 0xff, 6606 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6607 .support_64bit_ptrs = true, 6608 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6609 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6610 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6611 .emit_frame_size = 6612 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6613 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6614 5 + /*hdp invalidate */ 6615 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6616 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6617 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6618 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6619 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6620 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6621 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6622 .test_ring = gfx_v11_0_ring_test_ring, 6623 .test_ib = gfx_v11_0_ring_test_ib, 6624 .insert_nop = amdgpu_ring_insert_nop, 6625 .pad_ib = amdgpu_ring_generic_pad_ib, 6626 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6627 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6628 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6629 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6630 }; 6631 6632 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6633 { 6634 int i; 6635 6636 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6637 6638 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6639 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6640 6641 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6642 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6643 } 6644 6645 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6646 .set = gfx_v11_0_set_eop_interrupt_state, 6647 .process = gfx_v11_0_eop_irq, 6648 }; 6649 6650 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6651 .set = gfx_v11_0_set_priv_reg_fault_state, 6652 .process = gfx_v11_0_priv_reg_irq, 6653 }; 6654 6655 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6656 .set = gfx_v11_0_set_priv_inst_fault_state, 6657 .process = gfx_v11_0_priv_inst_irq, 6658 }; 6659 6660 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6661 .process = gfx_v11_0_rlc_gc_fed_irq, 6662 }; 6663 6664 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6665 { 6666 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6667 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6668 6669 adev->gfx.priv_reg_irq.num_types = 1; 6670 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6671 6672 adev->gfx.priv_inst_irq.num_types = 1; 6673 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6674 6675 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6676 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6677 6678 } 6679 6680 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6681 { 6682 if (adev->flags & AMD_IS_APU) 6683 adev->gfx.imu.mode = MISSION_MODE; 6684 else 6685 adev->gfx.imu.mode = DEBUG_MODE; 6686 6687 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6688 } 6689 6690 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6691 { 6692 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6693 } 6694 6695 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6696 { 6697 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6698 adev->gfx.config.max_sh_per_se * 6699 adev->gfx.config.max_shader_engines; 6700 6701 adev->gds.gds_size = 0x1000; 6702 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6703 adev->gds.gws_size = 64; 6704 adev->gds.oa_size = 16; 6705 } 6706 6707 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6708 { 6709 /* set gfx eng mqd */ 6710 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6711 sizeof(struct v11_gfx_mqd); 6712 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6713 gfx_v11_0_gfx_mqd_init; 6714 /* set compute eng mqd */ 6715 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6716 sizeof(struct v11_compute_mqd); 6717 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6718 gfx_v11_0_compute_mqd_init; 6719 } 6720 6721 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6722 u32 bitmap) 6723 { 6724 u32 data; 6725 6726 if (!bitmap) 6727 return; 6728 6729 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6730 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6731 6732 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6733 } 6734 6735 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6736 { 6737 u32 data, wgp_bitmask; 6738 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6739 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6740 6741 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6742 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6743 6744 wgp_bitmask = 6745 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6746 6747 return (~data) & wgp_bitmask; 6748 } 6749 6750 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6751 { 6752 u32 wgp_idx, wgp_active_bitmap; 6753 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6754 6755 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6756 cu_active_bitmap = 0; 6757 6758 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6759 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6760 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6761 if (wgp_active_bitmap & (1 << wgp_idx)) 6762 cu_active_bitmap |= cu_bitmap_per_wgp; 6763 } 6764 6765 return cu_active_bitmap; 6766 } 6767 6768 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6769 struct amdgpu_cu_info *cu_info) 6770 { 6771 int i, j, k, counter, active_cu_number = 0; 6772 u32 mask, bitmap; 6773 unsigned disable_masks[8 * 2]; 6774 6775 if (!adev || !cu_info) 6776 return -EINVAL; 6777 6778 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6779 6780 mutex_lock(&adev->grbm_idx_mutex); 6781 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6782 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6783 bitmap = i * adev->gfx.config.max_sh_per_se + j; 6784 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 6785 continue; 6786 mask = 1; 6787 counter = 0; 6788 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6789 if (i < 8 && j < 2) 6790 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6791 adev, disable_masks[i * 2 + j]); 6792 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6793 6794 /** 6795 * GFX11 could support more than 4 SEs, while the bitmap 6796 * in cu_info struct is 4x4 and ioctl interface struct 6797 * drm_amdgpu_info_device should keep stable. 6798 * So we use last two columns of bitmap to store cu mask for 6799 * SEs 4 to 7, the layout of the bitmap is as below: 6800 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6801 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6802 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6803 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6804 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6805 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6806 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6807 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6808 */ 6809 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 6810 6811 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6812 if (bitmap & mask) 6813 counter++; 6814 6815 mask <<= 1; 6816 } 6817 active_cu_number += counter; 6818 } 6819 } 6820 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6821 mutex_unlock(&adev->grbm_idx_mutex); 6822 6823 cu_info->number = active_cu_number; 6824 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6825 6826 return 0; 6827 } 6828 6829 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6830 { 6831 .type = AMD_IP_BLOCK_TYPE_GFX, 6832 .major = 11, 6833 .minor = 0, 6834 .rev = 0, 6835 .funcs = &gfx_v11_0_ip_funcs, 6836 }; 6837