1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "clearstate_gfx11.h" 46 #include "v11_structs.h" 47 #include "gfx_v11_0.h" 48 #include "gfx_v11_0_cleaner_shader.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 #define regPC_CONFIG_CNTL_1 0x194d 64 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 92 MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin"); 93 MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin"); 94 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin"); 95 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin"); 96 MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin"); 97 MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin"); 98 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin"); 99 MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin"); 100 MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); 101 MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); 102 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); 103 MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); 104 105 static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 106 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 108 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 139 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 140 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 142 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 143 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 144 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 145 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 146 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 147 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 148 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 149 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 150 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 151 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 152 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 153 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 163 /* cp header registers */ 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 168 /* SE status registers */ 169 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 170 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 171 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 172 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3), 173 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4), 174 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5) 175 }; 176 177 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 178 /* compute registers */ 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS) 218 }; 219 220 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 221 /* gfx queue registers */ 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 234 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) 247 }; 248 249 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 250 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 254 { 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 264 }; 265 266 #define DEFAULT_SH_MEM_CONFIG \ 267 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 268 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 269 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 270 271 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 272 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 273 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 274 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 275 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 276 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 277 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 278 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 279 struct amdgpu_cu_info *cu_info); 280 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 281 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 282 u32 sh_num, u32 instance, int xcc_id); 283 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 284 285 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 286 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 287 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 288 uint32_t val); 289 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 290 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 291 uint16_t pasid, uint32_t flush_type, 292 bool all_hub, uint8_t dst_sel); 293 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 294 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 295 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 296 bool enable); 297 298 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 299 { 300 struct amdgpu_device *adev = kiq_ring->adev; 301 u64 shader_mc_addr; 302 303 /* Cleaner shader MC address */ 304 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 305 306 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 307 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 308 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 309 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 310 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 311 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 312 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 313 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 314 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 315 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 316 } 317 318 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 319 struct amdgpu_ring *ring) 320 { 321 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 322 uint64_t wptr_addr = ring->wptr_gpu_addr; 323 uint32_t me = 0, eng_sel = 0; 324 325 switch (ring->funcs->type) { 326 case AMDGPU_RING_TYPE_COMPUTE: 327 me = 1; 328 eng_sel = 0; 329 break; 330 case AMDGPU_RING_TYPE_GFX: 331 me = 0; 332 eng_sel = 4; 333 break; 334 case AMDGPU_RING_TYPE_MES: 335 me = 2; 336 eng_sel = 5; 337 break; 338 default: 339 WARN_ON(1); 340 } 341 342 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 343 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 344 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 345 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 346 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 347 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 348 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 349 PACKET3_MAP_QUEUES_ME((me)) | 350 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 351 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 352 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 353 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 354 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 355 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 356 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 357 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 358 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 359 } 360 361 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 362 struct amdgpu_ring *ring, 363 enum amdgpu_unmap_queues_action action, 364 u64 gpu_addr, u64 seq) 365 { 366 struct amdgpu_device *adev = kiq_ring->adev; 367 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 368 369 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 370 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 371 return; 372 } 373 374 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 375 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 376 PACKET3_UNMAP_QUEUES_ACTION(action) | 377 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 378 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 379 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 380 amdgpu_ring_write(kiq_ring, 381 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 382 383 if (action == PREEMPT_QUEUES_NO_UNMAP) { 384 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 385 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 386 amdgpu_ring_write(kiq_ring, seq); 387 } else { 388 amdgpu_ring_write(kiq_ring, 0); 389 amdgpu_ring_write(kiq_ring, 0); 390 amdgpu_ring_write(kiq_ring, 0); 391 } 392 } 393 394 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 395 struct amdgpu_ring *ring, 396 u64 addr, 397 u64 seq) 398 { 399 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 400 401 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 402 amdgpu_ring_write(kiq_ring, 403 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 404 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 405 PACKET3_QUERY_STATUS_COMMAND(2)); 406 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 407 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 408 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 409 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 410 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 411 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 412 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 413 } 414 415 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 416 uint16_t pasid, uint32_t flush_type, 417 bool all_hub) 418 { 419 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 420 } 421 422 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 423 .kiq_set_resources = gfx11_kiq_set_resources, 424 .kiq_map_queues = gfx11_kiq_map_queues, 425 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 426 .kiq_query_status = gfx11_kiq_query_status, 427 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 428 .set_resources_size = 8, 429 .map_queues_size = 7, 430 .unmap_queues_size = 6, 431 .query_status_size = 7, 432 .invalidate_tlbs_size = 2, 433 }; 434 435 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 436 { 437 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 438 } 439 440 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 441 { 442 if (amdgpu_sriov_vf(adev)) 443 return; 444 445 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 446 case IP_VERSION(11, 0, 1): 447 case IP_VERSION(11, 0, 4): 448 soc15_program_register_sequence(adev, 449 golden_settings_gc_11_0_1, 450 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 451 break; 452 default: 453 break; 454 } 455 soc15_program_register_sequence(adev, 456 golden_settings_gc_11_0, 457 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 458 459 } 460 461 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 462 bool wc, uint32_t reg, uint32_t val) 463 { 464 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 465 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 466 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 467 amdgpu_ring_write(ring, reg); 468 amdgpu_ring_write(ring, 0); 469 amdgpu_ring_write(ring, val); 470 } 471 472 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 473 int mem_space, int opt, uint32_t addr0, 474 uint32_t addr1, uint32_t ref, uint32_t mask, 475 uint32_t inv) 476 { 477 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 478 amdgpu_ring_write(ring, 479 /* memory (1) or register (0) */ 480 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 481 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 482 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 483 WAIT_REG_MEM_ENGINE(eng_sel))); 484 485 if (mem_space) 486 BUG_ON(addr0 & 0x3); /* Dword align */ 487 amdgpu_ring_write(ring, addr0); 488 amdgpu_ring_write(ring, addr1); 489 amdgpu_ring_write(ring, ref); 490 amdgpu_ring_write(ring, mask); 491 amdgpu_ring_write(ring, inv); /* poll interval */ 492 } 493 494 static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 495 { 496 /* Header itself is a NOP packet */ 497 if (num_nop == 1) { 498 amdgpu_ring_write(ring, ring->funcs->nop); 499 return; 500 } 501 502 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 503 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 504 505 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 506 amdgpu_ring_insert_nop(ring, num_nop - 1); 507 } 508 509 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 510 { 511 struct amdgpu_device *adev = ring->adev; 512 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 513 uint32_t tmp = 0; 514 unsigned i; 515 int r; 516 517 WREG32(scratch, 0xCAFEDEAD); 518 r = amdgpu_ring_alloc(ring, 5); 519 if (r) { 520 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 521 ring->idx, r); 522 return r; 523 } 524 525 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 526 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 527 } else { 528 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 529 amdgpu_ring_write(ring, scratch - 530 PACKET3_SET_UCONFIG_REG_START); 531 amdgpu_ring_write(ring, 0xDEADBEEF); 532 } 533 amdgpu_ring_commit(ring); 534 535 for (i = 0; i < adev->usec_timeout; i++) { 536 tmp = RREG32(scratch); 537 if (tmp == 0xDEADBEEF) 538 break; 539 if (amdgpu_emu_mode == 1) 540 msleep(1); 541 else 542 udelay(1); 543 } 544 545 if (i >= adev->usec_timeout) 546 r = -ETIMEDOUT; 547 return r; 548 } 549 550 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 551 { 552 struct amdgpu_device *adev = ring->adev; 553 struct amdgpu_ib ib; 554 struct dma_fence *f = NULL; 555 unsigned index; 556 uint64_t gpu_addr; 557 volatile uint32_t *cpu_ptr; 558 long r; 559 560 /* MES KIQ fw hasn't indirect buffer support for now */ 561 if (adev->enable_mes_kiq && 562 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 563 return 0; 564 565 memset(&ib, 0, sizeof(ib)); 566 567 if (ring->is_mes_queue) { 568 uint32_t padding, offset; 569 570 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 571 padding = amdgpu_mes_ctx_get_offs(ring, 572 AMDGPU_MES_CTX_PADDING_OFFS); 573 574 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 575 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 576 577 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 578 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 579 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 580 } else { 581 r = amdgpu_device_wb_get(adev, &index); 582 if (r) 583 return r; 584 585 gpu_addr = adev->wb.gpu_addr + (index * 4); 586 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 587 cpu_ptr = &adev->wb.wb[index]; 588 589 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 590 if (r) { 591 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 592 goto err1; 593 } 594 } 595 596 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 597 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 598 ib.ptr[2] = lower_32_bits(gpu_addr); 599 ib.ptr[3] = upper_32_bits(gpu_addr); 600 ib.ptr[4] = 0xDEADBEEF; 601 ib.length_dw = 5; 602 603 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 604 if (r) 605 goto err2; 606 607 r = dma_fence_wait_timeout(f, false, timeout); 608 if (r == 0) { 609 r = -ETIMEDOUT; 610 goto err2; 611 } else if (r < 0) { 612 goto err2; 613 } 614 615 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 616 r = 0; 617 else 618 r = -EINVAL; 619 err2: 620 if (!ring->is_mes_queue) 621 amdgpu_ib_free(&ib, NULL); 622 dma_fence_put(f); 623 err1: 624 if (!ring->is_mes_queue) 625 amdgpu_device_wb_free(adev, index); 626 return r; 627 } 628 629 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 630 { 631 amdgpu_ucode_release(&adev->gfx.pfp_fw); 632 amdgpu_ucode_release(&adev->gfx.me_fw); 633 amdgpu_ucode_release(&adev->gfx.rlc_fw); 634 amdgpu_ucode_release(&adev->gfx.mec_fw); 635 636 kfree(adev->gfx.rlc.register_list_format); 637 } 638 639 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 640 { 641 const struct psp_firmware_header_v1_0 *toc_hdr; 642 int err = 0; 643 644 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 645 AMDGPU_UCODE_REQUIRED, 646 "amdgpu/%s_toc.bin", ucode_prefix); 647 if (err) 648 goto out; 649 650 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 651 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 652 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 653 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 654 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 655 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 656 return 0; 657 out: 658 amdgpu_ucode_release(&adev->psp.toc_fw); 659 return err; 660 } 661 662 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 663 { 664 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 665 case IP_VERSION(11, 0, 0): 666 case IP_VERSION(11, 0, 2): 667 case IP_VERSION(11, 0, 3): 668 if ((adev->gfx.me_fw_version >= 1505) && 669 (adev->gfx.pfp_fw_version >= 1600) && 670 (adev->gfx.mec_fw_version >= 512)) { 671 if (amdgpu_sriov_vf(adev)) 672 adev->gfx.cp_gfx_shadow = true; 673 else 674 adev->gfx.cp_gfx_shadow = false; 675 } 676 break; 677 default: 678 adev->gfx.cp_gfx_shadow = false; 679 break; 680 } 681 } 682 683 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 684 { 685 char ucode_prefix[25]; 686 int err; 687 const struct rlc_firmware_header_v2_0 *rlc_hdr; 688 uint16_t version_major; 689 uint16_t version_minor; 690 691 DRM_DEBUG("\n"); 692 693 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 694 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 695 AMDGPU_UCODE_REQUIRED, 696 "amdgpu/%s_pfp.bin", ucode_prefix); 697 if (err) 698 goto out; 699 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 700 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 701 (union amdgpu_firmware_header *) 702 adev->gfx.pfp_fw->data, 2, 0); 703 if (adev->gfx.rs64_enable) { 704 dev_info(adev->dev, "CP RS64 enable\n"); 705 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 706 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 707 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 708 } else { 709 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 710 } 711 712 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 713 AMDGPU_UCODE_REQUIRED, 714 "amdgpu/%s_me.bin", ucode_prefix); 715 if (err) 716 goto out; 717 if (adev->gfx.rs64_enable) { 718 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 719 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 720 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 721 } else { 722 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 723 } 724 725 if (!amdgpu_sriov_vf(adev)) { 726 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 727 adev->pdev->revision == 0xCE) 728 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 729 AMDGPU_UCODE_REQUIRED, 730 "amdgpu/gc_11_0_0_rlc_1.bin"); 731 else 732 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 733 AMDGPU_UCODE_REQUIRED, 734 "amdgpu/%s_rlc.bin", ucode_prefix); 735 if (err) 736 goto out; 737 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 738 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 739 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 740 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 741 if (err) 742 goto out; 743 } 744 745 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 746 AMDGPU_UCODE_REQUIRED, 747 "amdgpu/%s_mec.bin", ucode_prefix); 748 if (err) 749 goto out; 750 if (adev->gfx.rs64_enable) { 751 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 752 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 753 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 754 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 755 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 756 } else { 757 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 758 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 759 } 760 761 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 762 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 763 764 /* only one MEC for gfx 11.0.0. */ 765 adev->gfx.mec2_fw = NULL; 766 767 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 768 769 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 770 err = adev->gfx.imu.funcs->init_microcode(adev); 771 if (err) 772 DRM_ERROR("Failed to init imu firmware!\n"); 773 return err; 774 } 775 776 out: 777 if (err) { 778 amdgpu_ucode_release(&adev->gfx.pfp_fw); 779 amdgpu_ucode_release(&adev->gfx.me_fw); 780 amdgpu_ucode_release(&adev->gfx.rlc_fw); 781 amdgpu_ucode_release(&adev->gfx.mec_fw); 782 } 783 784 return err; 785 } 786 787 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 788 { 789 u32 count = 0; 790 const struct cs_section_def *sect = NULL; 791 const struct cs_extent_def *ext = NULL; 792 793 /* begin clear state */ 794 count += 2; 795 /* context control state */ 796 count += 3; 797 798 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 799 for (ext = sect->section; ext->extent != NULL; ++ext) { 800 if (sect->id == SECT_CONTEXT) 801 count += 2 + ext->reg_count; 802 else 803 return 0; 804 } 805 } 806 807 /* set PA_SC_TILE_STEERING_OVERRIDE */ 808 count += 3; 809 /* end clear state */ 810 count += 2; 811 /* clear state */ 812 count += 2; 813 814 return count; 815 } 816 817 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 818 volatile u32 *buffer) 819 { 820 u32 count = 0, i; 821 const struct cs_section_def *sect = NULL; 822 const struct cs_extent_def *ext = NULL; 823 int ctx_reg_offset; 824 825 if (adev->gfx.rlc.cs_data == NULL) 826 return; 827 if (buffer == NULL) 828 return; 829 830 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 831 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 832 833 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 834 buffer[count++] = cpu_to_le32(0x80000000); 835 buffer[count++] = cpu_to_le32(0x80000000); 836 837 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 838 for (ext = sect->section; ext->extent != NULL; ++ext) { 839 if (sect->id == SECT_CONTEXT) { 840 buffer[count++] = 841 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 842 buffer[count++] = cpu_to_le32(ext->reg_index - 843 PACKET3_SET_CONTEXT_REG_START); 844 for (i = 0; i < ext->reg_count; i++) 845 buffer[count++] = cpu_to_le32(ext->extent[i]); 846 } else { 847 return; 848 } 849 } 850 } 851 852 ctx_reg_offset = 853 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 854 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 855 buffer[count++] = cpu_to_le32(ctx_reg_offset); 856 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 857 858 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 859 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 860 861 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 862 buffer[count++] = cpu_to_le32(0); 863 } 864 865 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 866 { 867 /* clear state block */ 868 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 869 &adev->gfx.rlc.clear_state_gpu_addr, 870 (void **)&adev->gfx.rlc.cs_ptr); 871 872 /* jump table block */ 873 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 874 &adev->gfx.rlc.cp_table_gpu_addr, 875 (void **)&adev->gfx.rlc.cp_table_ptr); 876 } 877 878 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 879 { 880 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 881 882 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 883 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 884 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 885 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 886 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 887 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 888 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 889 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 890 adev->gfx.rlc.rlcg_reg_access_supported = true; 891 } 892 893 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 894 { 895 const struct cs_section_def *cs_data; 896 int r; 897 898 adev->gfx.rlc.cs_data = gfx11_cs_data; 899 900 cs_data = adev->gfx.rlc.cs_data; 901 902 if (cs_data) { 903 /* init clear state block */ 904 r = amdgpu_gfx_rlc_init_csb(adev); 905 if (r) 906 return r; 907 } 908 909 /* init spm vmid with 0xf */ 910 if (adev->gfx.rlc.funcs->update_spm_vmid) 911 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 912 913 return 0; 914 } 915 916 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 917 { 918 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 919 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 920 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 921 } 922 923 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 924 { 925 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 926 927 amdgpu_gfx_graphics_queue_acquire(adev); 928 } 929 930 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 931 { 932 int r; 933 u32 *hpd; 934 size_t mec_hpd_size; 935 936 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 937 938 /* take ownership of the relevant compute queues */ 939 amdgpu_gfx_compute_queue_acquire(adev); 940 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 941 942 if (mec_hpd_size) { 943 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 944 AMDGPU_GEM_DOMAIN_GTT, 945 &adev->gfx.mec.hpd_eop_obj, 946 &adev->gfx.mec.hpd_eop_gpu_addr, 947 (void **)&hpd); 948 if (r) { 949 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 950 gfx_v11_0_mec_fini(adev); 951 return r; 952 } 953 954 memset(hpd, 0, mec_hpd_size); 955 956 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 957 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 958 } 959 960 return 0; 961 } 962 963 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 964 { 965 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 966 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 967 (address << SQ_IND_INDEX__INDEX__SHIFT)); 968 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 969 } 970 971 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 972 uint32_t thread, uint32_t regno, 973 uint32_t num, uint32_t *out) 974 { 975 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 976 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 977 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 978 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 979 (SQ_IND_INDEX__AUTO_INCR_MASK)); 980 while (num--) 981 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 982 } 983 984 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 985 { 986 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 987 * field when performing a select_se_sh so it should be 988 * zero here */ 989 WARN_ON(simd != 0); 990 991 /* type 3 wave data */ 992 dst[(*no_fields)++] = 3; 993 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 994 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 995 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 996 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 997 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 998 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 999 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1000 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1001 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1002 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1003 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1004 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1005 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1006 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1007 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1008 } 1009 1010 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1011 uint32_t wave, uint32_t start, 1012 uint32_t size, uint32_t *dst) 1013 { 1014 WARN_ON(simd != 0); 1015 1016 wave_read_regs( 1017 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1018 dst); 1019 } 1020 1021 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1022 uint32_t wave, uint32_t thread, 1023 uint32_t start, uint32_t size, 1024 uint32_t *dst) 1025 { 1026 wave_read_regs( 1027 adev, wave, thread, 1028 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1029 } 1030 1031 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1032 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1033 { 1034 soc21_grbm_select(adev, me, pipe, q, vm); 1035 } 1036 1037 /* all sizes are in bytes */ 1038 #define MQD_SHADOW_BASE_SIZE 73728 1039 #define MQD_SHADOW_BASE_ALIGNMENT 256 1040 #define MQD_FWWORKAREA_SIZE 484 1041 #define MQD_FWWORKAREA_ALIGNMENT 256 1042 1043 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 1044 struct amdgpu_gfx_shadow_info *shadow_info) 1045 { 1046 if (adev->gfx.cp_gfx_shadow) { 1047 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 1048 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 1049 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 1050 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 1051 return 0; 1052 } else { 1053 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 1054 return -ENOTSUPP; 1055 } 1056 } 1057 1058 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1059 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1060 .select_se_sh = &gfx_v11_0_select_se_sh, 1061 .read_wave_data = &gfx_v11_0_read_wave_data, 1062 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1063 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1064 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1065 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 1066 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 1067 }; 1068 1069 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1070 { 1071 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1072 case IP_VERSION(11, 0, 0): 1073 case IP_VERSION(11, 0, 2): 1074 adev->gfx.config.max_hw_contexts = 8; 1075 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1076 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1077 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1078 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1079 break; 1080 case IP_VERSION(11, 0, 3): 1081 adev->gfx.ras = &gfx_v11_0_3_ras; 1082 adev->gfx.config.max_hw_contexts = 8; 1083 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1084 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1085 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1086 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1087 break; 1088 case IP_VERSION(11, 0, 1): 1089 case IP_VERSION(11, 0, 4): 1090 case IP_VERSION(11, 5, 0): 1091 case IP_VERSION(11, 5, 1): 1092 case IP_VERSION(11, 5, 2): 1093 case IP_VERSION(11, 5, 3): 1094 adev->gfx.config.max_hw_contexts = 8; 1095 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1096 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1097 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1098 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1099 break; 1100 default: 1101 BUG(); 1102 break; 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1109 int me, int pipe, int queue) 1110 { 1111 struct amdgpu_ring *ring; 1112 unsigned int irq_type; 1113 unsigned int hw_prio; 1114 1115 ring = &adev->gfx.gfx_ring[ring_id]; 1116 1117 ring->me = me; 1118 ring->pipe = pipe; 1119 ring->queue = queue; 1120 1121 ring->ring_obj = NULL; 1122 ring->use_doorbell = true; 1123 1124 if (!ring_id) 1125 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1126 else 1127 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1128 ring->vm_hub = AMDGPU_GFXHUB(0); 1129 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1130 1131 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1132 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 1133 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1134 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1135 hw_prio, NULL); 1136 } 1137 1138 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1139 int mec, int pipe, int queue) 1140 { 1141 int r; 1142 unsigned irq_type; 1143 struct amdgpu_ring *ring; 1144 unsigned int hw_prio; 1145 1146 ring = &adev->gfx.compute_ring[ring_id]; 1147 1148 /* mec0 is me1 */ 1149 ring->me = mec + 1; 1150 ring->pipe = pipe; 1151 ring->queue = queue; 1152 1153 ring->ring_obj = NULL; 1154 ring->use_doorbell = true; 1155 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1156 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1157 + (ring_id * GFX11_MEC_HPD_SIZE); 1158 ring->vm_hub = AMDGPU_GFXHUB(0); 1159 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1160 1161 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1162 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1163 + ring->pipe; 1164 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1165 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1166 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1167 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1168 hw_prio, NULL); 1169 if (r) 1170 return r; 1171 1172 return 0; 1173 } 1174 1175 static struct { 1176 SOC21_FIRMWARE_ID id; 1177 unsigned int offset; 1178 unsigned int size; 1179 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1180 1181 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1182 { 1183 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1184 1185 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1186 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1187 rlc_autoload_info[ucode->id].id = ucode->id; 1188 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1189 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1190 1191 ucode++; 1192 } 1193 } 1194 1195 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1196 { 1197 uint32_t total_size = 0; 1198 SOC21_FIRMWARE_ID id; 1199 1200 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1201 1202 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1203 total_size += rlc_autoload_info[id].size; 1204 1205 /* In case the offset in rlc toc ucode is aligned */ 1206 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1207 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1208 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1209 1210 return total_size; 1211 } 1212 1213 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1214 { 1215 int r; 1216 uint32_t total_size; 1217 1218 total_size = gfx_v11_0_calc_toc_total_size(adev); 1219 1220 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1221 AMDGPU_GEM_DOMAIN_VRAM | 1222 AMDGPU_GEM_DOMAIN_GTT, 1223 &adev->gfx.rlc.rlc_autoload_bo, 1224 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1225 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1226 1227 if (r) { 1228 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1229 return r; 1230 } 1231 1232 return 0; 1233 } 1234 1235 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1236 SOC21_FIRMWARE_ID id, 1237 const void *fw_data, 1238 uint32_t fw_size, 1239 uint32_t *fw_autoload_mask) 1240 { 1241 uint32_t toc_offset; 1242 uint32_t toc_fw_size; 1243 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1244 1245 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1246 return; 1247 1248 toc_offset = rlc_autoload_info[id].offset; 1249 toc_fw_size = rlc_autoload_info[id].size; 1250 1251 if (fw_size == 0) 1252 fw_size = toc_fw_size; 1253 1254 if (fw_size > toc_fw_size) 1255 fw_size = toc_fw_size; 1256 1257 memcpy(ptr + toc_offset, fw_data, fw_size); 1258 1259 if (fw_size < toc_fw_size) 1260 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1261 1262 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1263 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1264 } 1265 1266 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1267 uint32_t *fw_autoload_mask) 1268 { 1269 void *data; 1270 uint32_t size; 1271 uint64_t *toc_ptr; 1272 1273 *(uint64_t *)fw_autoload_mask |= 0x1; 1274 1275 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1276 1277 data = adev->psp.toc.start_addr; 1278 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1279 1280 toc_ptr = (uint64_t *)data + size / 8 - 1; 1281 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1282 1283 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1284 data, size, fw_autoload_mask); 1285 } 1286 1287 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1288 uint32_t *fw_autoload_mask) 1289 { 1290 const __le32 *fw_data; 1291 uint32_t fw_size; 1292 const struct gfx_firmware_header_v1_0 *cp_hdr; 1293 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1294 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1295 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1296 uint16_t version_major, version_minor; 1297 1298 if (adev->gfx.rs64_enable) { 1299 /* pfp ucode */ 1300 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1301 adev->gfx.pfp_fw->data; 1302 /* instruction */ 1303 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1304 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1305 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1306 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1307 fw_data, fw_size, fw_autoload_mask); 1308 /* data */ 1309 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1310 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1311 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1312 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1313 fw_data, fw_size, fw_autoload_mask); 1314 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1315 fw_data, fw_size, fw_autoload_mask); 1316 /* me ucode */ 1317 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1318 adev->gfx.me_fw->data; 1319 /* instruction */ 1320 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1321 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1322 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1323 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1324 fw_data, fw_size, fw_autoload_mask); 1325 /* data */ 1326 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1327 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1328 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1329 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1330 fw_data, fw_size, fw_autoload_mask); 1331 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1332 fw_data, fw_size, fw_autoload_mask); 1333 /* mec ucode */ 1334 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1335 adev->gfx.mec_fw->data; 1336 /* instruction */ 1337 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1338 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1339 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1340 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1341 fw_data, fw_size, fw_autoload_mask); 1342 /* data */ 1343 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1344 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1345 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1346 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1347 fw_data, fw_size, fw_autoload_mask); 1348 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1349 fw_data, fw_size, fw_autoload_mask); 1350 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1351 fw_data, fw_size, fw_autoload_mask); 1352 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1353 fw_data, fw_size, fw_autoload_mask); 1354 } else { 1355 /* pfp ucode */ 1356 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1357 adev->gfx.pfp_fw->data; 1358 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1359 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1360 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1361 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1362 fw_data, fw_size, fw_autoload_mask); 1363 1364 /* me ucode */ 1365 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1366 adev->gfx.me_fw->data; 1367 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1368 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1369 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1370 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1371 fw_data, fw_size, fw_autoload_mask); 1372 1373 /* mec ucode */ 1374 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1375 adev->gfx.mec_fw->data; 1376 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1377 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1378 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1379 cp_hdr->jt_size * 4; 1380 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1381 fw_data, fw_size, fw_autoload_mask); 1382 } 1383 1384 /* rlc ucode */ 1385 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1386 adev->gfx.rlc_fw->data; 1387 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1388 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1389 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1391 fw_data, fw_size, fw_autoload_mask); 1392 1393 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1394 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1395 if (version_major == 2) { 1396 if (version_minor >= 2) { 1397 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1398 1399 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1400 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1401 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1402 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1403 fw_data, fw_size, fw_autoload_mask); 1404 1405 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1406 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1407 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1408 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1409 fw_data, fw_size, fw_autoload_mask); 1410 } 1411 } 1412 } 1413 1414 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1415 uint32_t *fw_autoload_mask) 1416 { 1417 const __le32 *fw_data; 1418 uint32_t fw_size; 1419 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1420 1421 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1422 adev->sdma.instance[0].fw->data; 1423 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1424 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1425 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1426 1427 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1428 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1429 1430 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1431 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1432 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1433 1434 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1435 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1436 } 1437 1438 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1439 uint32_t *fw_autoload_mask) 1440 { 1441 const __le32 *fw_data; 1442 unsigned fw_size; 1443 const struct mes_firmware_header_v1_0 *mes_hdr; 1444 int pipe, ucode_id, data_id; 1445 1446 for (pipe = 0; pipe < 2; pipe++) { 1447 if (pipe==0) { 1448 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1449 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1450 } else { 1451 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1452 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1453 } 1454 1455 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1456 adev->mes.fw[pipe]->data; 1457 1458 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1459 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1460 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1461 1462 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1463 ucode_id, fw_data, fw_size, fw_autoload_mask); 1464 1465 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1466 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1467 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1468 1469 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1470 data_id, fw_data, fw_size, fw_autoload_mask); 1471 } 1472 } 1473 1474 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1475 { 1476 uint32_t rlc_g_offset, rlc_g_size; 1477 uint64_t gpu_addr; 1478 uint32_t autoload_fw_id[2]; 1479 1480 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1481 1482 /* RLC autoload sequence 2: copy ucode */ 1483 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1484 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1485 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1486 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1487 1488 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1489 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1490 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1491 1492 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1493 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1494 1495 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1496 1497 /* RLC autoload sequence 3: load IMU fw */ 1498 if (adev->gfx.imu.funcs->load_microcode) 1499 adev->gfx.imu.funcs->load_microcode(adev); 1500 /* RLC autoload sequence 4 init IMU fw */ 1501 if (adev->gfx.imu.funcs->setup_imu) 1502 adev->gfx.imu.funcs->setup_imu(adev); 1503 if (adev->gfx.imu.funcs->start_imu) 1504 adev->gfx.imu.funcs->start_imu(adev); 1505 1506 /* RLC autoload sequence 5 disable gpa mode */ 1507 gfx_v11_0_disable_gpa_mode(adev); 1508 1509 return 0; 1510 } 1511 1512 static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) 1513 { 1514 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 1515 uint32_t *ptr; 1516 uint32_t inst; 1517 1518 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1519 if (!ptr) { 1520 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1521 adev->gfx.ip_dump_core = NULL; 1522 } else { 1523 adev->gfx.ip_dump_core = ptr; 1524 } 1525 1526 /* Allocate memory for compute queue registers for all the instances */ 1527 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 1528 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1529 adev->gfx.mec.num_queue_per_pipe; 1530 1531 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1532 if (!ptr) { 1533 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1534 adev->gfx.ip_dump_compute_queues = NULL; 1535 } else { 1536 adev->gfx.ip_dump_compute_queues = ptr; 1537 } 1538 1539 /* Allocate memory for gfx queue registers for all the instances */ 1540 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 1541 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1542 adev->gfx.me.num_queue_per_pipe; 1543 1544 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1545 if (!ptr) { 1546 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1547 adev->gfx.ip_dump_gfx_queues = NULL; 1548 } else { 1549 adev->gfx.ip_dump_gfx_queues = ptr; 1550 } 1551 } 1552 1553 static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1554 { 1555 int i, j, k, r, ring_id = 0; 1556 int xcc_id = 0; 1557 struct amdgpu_device *adev = ip_block->adev; 1558 1559 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1560 1561 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1562 case IP_VERSION(11, 0, 0): 1563 case IP_VERSION(11, 0, 2): 1564 case IP_VERSION(11, 0, 3): 1565 adev->gfx.me.num_me = 1; 1566 adev->gfx.me.num_pipe_per_me = 1; 1567 adev->gfx.me.num_queue_per_pipe = 1; 1568 adev->gfx.mec.num_mec = 2; 1569 adev->gfx.mec.num_pipe_per_mec = 4; 1570 adev->gfx.mec.num_queue_per_pipe = 4; 1571 break; 1572 case IP_VERSION(11, 0, 1): 1573 case IP_VERSION(11, 0, 4): 1574 case IP_VERSION(11, 5, 0): 1575 case IP_VERSION(11, 5, 1): 1576 case IP_VERSION(11, 5, 2): 1577 case IP_VERSION(11, 5, 3): 1578 adev->gfx.me.num_me = 1; 1579 adev->gfx.me.num_pipe_per_me = 1; 1580 adev->gfx.me.num_queue_per_pipe = 1; 1581 adev->gfx.mec.num_mec = 1; 1582 adev->gfx.mec.num_pipe_per_mec = 4; 1583 adev->gfx.mec.num_queue_per_pipe = 4; 1584 break; 1585 default: 1586 adev->gfx.me.num_me = 1; 1587 adev->gfx.me.num_pipe_per_me = 1; 1588 adev->gfx.me.num_queue_per_pipe = 1; 1589 adev->gfx.mec.num_mec = 1; 1590 adev->gfx.mec.num_pipe_per_mec = 4; 1591 adev->gfx.mec.num_queue_per_pipe = 8; 1592 break; 1593 } 1594 1595 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1596 case IP_VERSION(11, 0, 0): 1597 case IP_VERSION(11, 0, 2): 1598 case IP_VERSION(11, 0, 3): 1599 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1600 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1601 if (adev->gfx.me_fw_version >= 2280 && 1602 adev->gfx.pfp_fw_version >= 2370 && 1603 adev->gfx.mec_fw_version >= 2450 && 1604 adev->mes.fw_version[0] >= 99) { 1605 adev->gfx.enable_cleaner_shader = true; 1606 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1607 if (r) { 1608 adev->gfx.enable_cleaner_shader = false; 1609 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1610 } 1611 } 1612 break; 1613 default: 1614 adev->gfx.enable_cleaner_shader = false; 1615 break; 1616 } 1617 1618 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1619 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1620 amdgpu_sriov_is_pp_one_vf(adev)) 1621 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1622 1623 /* EOP Event */ 1624 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1625 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1626 &adev->gfx.eop_irq); 1627 if (r) 1628 return r; 1629 1630 /* Bad opcode Event */ 1631 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1632 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1633 &adev->gfx.bad_op_irq); 1634 if (r) 1635 return r; 1636 1637 /* Privileged reg */ 1638 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1639 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1640 &adev->gfx.priv_reg_irq); 1641 if (r) 1642 return r; 1643 1644 /* Privileged inst */ 1645 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1646 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1647 &adev->gfx.priv_inst_irq); 1648 if (r) 1649 return r; 1650 1651 /* FED error */ 1652 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1653 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1654 &adev->gfx.rlc_gc_fed_irq); 1655 if (r) 1656 return r; 1657 1658 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1659 1660 gfx_v11_0_me_init(adev); 1661 1662 r = gfx_v11_0_rlc_init(adev); 1663 if (r) { 1664 DRM_ERROR("Failed to init rlc BOs!\n"); 1665 return r; 1666 } 1667 1668 r = gfx_v11_0_mec_init(adev); 1669 if (r) { 1670 DRM_ERROR("Failed to init MEC BOs!\n"); 1671 return r; 1672 } 1673 1674 /* set up the gfx ring */ 1675 for (i = 0; i < adev->gfx.me.num_me; i++) { 1676 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1677 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1678 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1679 continue; 1680 1681 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1682 i, k, j); 1683 if (r) 1684 return r; 1685 ring_id++; 1686 } 1687 } 1688 } 1689 1690 ring_id = 0; 1691 /* set up the compute queues - allocate horizontally across pipes */ 1692 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1693 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1694 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1695 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1696 k, j)) 1697 continue; 1698 1699 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1700 i, k, j); 1701 if (r) 1702 return r; 1703 1704 ring_id++; 1705 } 1706 } 1707 } 1708 1709 adev->gfx.gfx_supported_reset = 1710 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1711 adev->gfx.compute_supported_reset = 1712 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1713 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1714 case IP_VERSION(11, 0, 0): 1715 case IP_VERSION(11, 0, 2): 1716 case IP_VERSION(11, 0, 3): 1717 if ((adev->gfx.me_fw_version >= 2280) && 1718 (adev->gfx.mec_fw_version >= 2410)) { 1719 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1720 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1721 } 1722 break; 1723 default: 1724 break; 1725 } 1726 1727 if (!adev->enable_mes_kiq) { 1728 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1729 if (r) { 1730 DRM_ERROR("Failed to init KIQ BOs!\n"); 1731 return r; 1732 } 1733 1734 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1735 if (r) 1736 return r; 1737 } 1738 1739 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1740 if (r) 1741 return r; 1742 1743 /* allocate visible FB for rlc auto-loading fw */ 1744 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1745 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1746 if (r) 1747 return r; 1748 } 1749 1750 r = gfx_v11_0_gpu_early_init(adev); 1751 if (r) 1752 return r; 1753 1754 if (amdgpu_gfx_ras_sw_init(adev)) { 1755 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1756 return -EINVAL; 1757 } 1758 1759 gfx_v11_0_alloc_ip_dump(adev); 1760 1761 r = amdgpu_gfx_sysfs_init(adev); 1762 if (r) 1763 return r; 1764 1765 return 0; 1766 } 1767 1768 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1769 { 1770 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1771 &adev->gfx.pfp.pfp_fw_gpu_addr, 1772 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1773 1774 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1775 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1776 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1777 } 1778 1779 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1780 { 1781 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1782 &adev->gfx.me.me_fw_gpu_addr, 1783 (void **)&adev->gfx.me.me_fw_ptr); 1784 1785 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1786 &adev->gfx.me.me_fw_data_gpu_addr, 1787 (void **)&adev->gfx.me.me_fw_data_ptr); 1788 } 1789 1790 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1791 { 1792 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1793 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1794 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1795 } 1796 1797 static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1798 { 1799 int i; 1800 struct amdgpu_device *adev = ip_block->adev; 1801 1802 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1803 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1804 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1805 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1806 1807 amdgpu_gfx_mqd_sw_fini(adev, 0); 1808 1809 if (!adev->enable_mes_kiq) { 1810 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1811 amdgpu_gfx_kiq_fini(adev, 0); 1812 } 1813 1814 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1815 1816 gfx_v11_0_pfp_fini(adev); 1817 gfx_v11_0_me_fini(adev); 1818 gfx_v11_0_rlc_fini(adev); 1819 gfx_v11_0_mec_fini(adev); 1820 1821 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1822 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1823 1824 gfx_v11_0_free_microcode(adev); 1825 1826 amdgpu_gfx_sysfs_fini(adev); 1827 1828 kfree(adev->gfx.ip_dump_core); 1829 kfree(adev->gfx.ip_dump_compute_queues); 1830 kfree(adev->gfx.ip_dump_gfx_queues); 1831 1832 return 0; 1833 } 1834 1835 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1836 u32 sh_num, u32 instance, int xcc_id) 1837 { 1838 u32 data; 1839 1840 if (instance == 0xffffffff) 1841 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1842 INSTANCE_BROADCAST_WRITES, 1); 1843 else 1844 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1845 instance); 1846 1847 if (se_num == 0xffffffff) 1848 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1849 1); 1850 else 1851 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1852 1853 if (sh_num == 0xffffffff) 1854 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1855 1); 1856 else 1857 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1858 1859 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1860 } 1861 1862 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1863 { 1864 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1865 1866 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1867 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1868 CC_GC_SA_UNIT_DISABLE, 1869 SA_DISABLE); 1870 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1871 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1872 GC_USER_SA_UNIT_DISABLE, 1873 SA_DISABLE); 1874 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1875 adev->gfx.config.max_shader_engines); 1876 1877 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1878 } 1879 1880 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1881 { 1882 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1883 u32 rb_mask; 1884 1885 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1886 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1887 CC_RB_BACKEND_DISABLE, 1888 BACKEND_DISABLE); 1889 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1890 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1891 GC_USER_RB_BACKEND_DISABLE, 1892 BACKEND_DISABLE); 1893 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1894 adev->gfx.config.max_shader_engines); 1895 1896 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1897 } 1898 1899 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1900 { 1901 u32 rb_bitmap_per_sa; 1902 u32 rb_bitmap_width_per_sa; 1903 u32 max_sa; 1904 u32 active_sa_bitmap; 1905 u32 global_active_rb_bitmap; 1906 u32 active_rb_bitmap = 0; 1907 u32 i; 1908 1909 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1910 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1911 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1912 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1913 1914 /* generate active rb bitmap according to active sa bitmap */ 1915 max_sa = adev->gfx.config.max_shader_engines * 1916 adev->gfx.config.max_sh_per_se; 1917 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1918 adev->gfx.config.max_sh_per_se; 1919 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1920 1921 for (i = 0; i < max_sa; i++) { 1922 if (active_sa_bitmap & (1 << i)) 1923 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1924 } 1925 1926 active_rb_bitmap &= global_active_rb_bitmap; 1927 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1928 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1929 } 1930 1931 #define DEFAULT_SH_MEM_BASES (0x6000) 1932 #define LDS_APP_BASE 0x1 1933 #define SCRATCH_APP_BASE 0x2 1934 1935 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1936 { 1937 int i; 1938 uint32_t sh_mem_bases; 1939 uint32_t data; 1940 1941 /* 1942 * Configure apertures: 1943 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1944 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1945 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1946 */ 1947 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1948 SCRATCH_APP_BASE; 1949 1950 mutex_lock(&adev->srbm_mutex); 1951 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1952 soc21_grbm_select(adev, 0, 0, 0, i); 1953 /* CP and shaders */ 1954 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1955 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1956 1957 /* Enable trap for each kfd vmid. */ 1958 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1959 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1960 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1961 } 1962 soc21_grbm_select(adev, 0, 0, 0, 0); 1963 mutex_unlock(&adev->srbm_mutex); 1964 1965 /* 1966 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1967 * access. These should be enabled by FW for target VMIDs. 1968 */ 1969 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1970 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1971 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1972 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1973 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1974 } 1975 } 1976 1977 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1978 { 1979 int vmid; 1980 1981 /* 1982 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1983 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1984 * the driver can enable them for graphics. VMID0 should maintain 1985 * access so that HWS firmware can save/restore entries. 1986 */ 1987 for (vmid = 1; vmid < 16; vmid++) { 1988 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1989 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1990 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1991 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1992 } 1993 } 1994 1995 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1996 { 1997 /* TODO: harvest feature to be added later. */ 1998 } 1999 2000 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 2001 { 2002 /* TCCs are global (not instanced). */ 2003 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 2004 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 2005 2006 adev->gfx.config.tcc_disabled_mask = 2007 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 2008 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 2009 } 2010 2011 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 2012 { 2013 u32 tmp; 2014 int i; 2015 2016 if (!amdgpu_sriov_vf(adev)) 2017 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2018 2019 gfx_v11_0_setup_rb(adev); 2020 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 2021 gfx_v11_0_get_tcc_info(adev); 2022 adev->gfx.config.pa_sc_tile_steering_override = 0; 2023 2024 /* Set whether texture coordinate truncation is conformant. */ 2025 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 2026 adev->gfx.config.ta_cntl2_truncate_coord_mode = 2027 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 2028 2029 /* XXX SH_MEM regs */ 2030 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2031 mutex_lock(&adev->srbm_mutex); 2032 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2033 soc21_grbm_select(adev, 0, 0, 0, i); 2034 /* CP and shaders */ 2035 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 2036 if (i != 0) { 2037 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2038 (adev->gmc.private_aperture_start >> 48)); 2039 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2040 (adev->gmc.shared_aperture_start >> 48)); 2041 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 2042 } 2043 } 2044 soc21_grbm_select(adev, 0, 0, 0, 0); 2045 2046 mutex_unlock(&adev->srbm_mutex); 2047 2048 gfx_v11_0_init_compute_vmid(adev); 2049 gfx_v11_0_init_gds_vmid(adev); 2050 } 2051 2052 static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev, 2053 int me, int pipe) 2054 { 2055 if (me != 0) 2056 return 0; 2057 2058 switch (pipe) { 2059 case 0: 2060 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 2061 case 1: 2062 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 2063 default: 2064 return 0; 2065 } 2066 } 2067 2068 static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev, 2069 int me, int pipe) 2070 { 2071 /* 2072 * amdgpu controls only the first MEC. That's why this function only 2073 * handles the setting of interrupts for this specific MEC. All other 2074 * pipes' interrupts are set by amdkfd. 2075 */ 2076 if (me != 1) 2077 return 0; 2078 2079 switch (pipe) { 2080 case 0: 2081 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 2082 case 1: 2083 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 2084 case 2: 2085 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 2086 case 3: 2087 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 2088 default: 2089 return 0; 2090 } 2091 } 2092 2093 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2094 bool enable) 2095 { 2096 u32 tmp, cp_int_cntl_reg; 2097 int i, j; 2098 2099 if (amdgpu_sriov_vf(adev)) 2100 return; 2101 2102 for (i = 0; i < adev->gfx.me.num_me; i++) { 2103 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 2104 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 2105 2106 if (cp_int_cntl_reg) { 2107 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 2108 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 2109 enable ? 1 : 0); 2110 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 2111 enable ? 1 : 0); 2112 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 2113 enable ? 1 : 0); 2114 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 2115 enable ? 1 : 0); 2116 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 2117 } 2118 } 2119 } 2120 } 2121 2122 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 2123 { 2124 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2125 2126 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 2127 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2128 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 2129 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2130 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 2131 2132 return 0; 2133 } 2134 2135 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 2136 { 2137 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 2138 2139 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2140 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 2141 } 2142 2143 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2144 { 2145 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2146 udelay(50); 2147 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2148 udelay(50); 2149 } 2150 2151 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2152 bool enable) 2153 { 2154 uint32_t rlc_pg_cntl; 2155 2156 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2157 2158 if (!enable) { 2159 /* RLC_PG_CNTL[23] = 0 (default) 2160 * RLC will wait for handshake acks with SMU 2161 * GFXOFF will be enabled 2162 * RLC_PG_CNTL[23] = 1 2163 * RLC will not issue any message to SMU 2164 * hence no handshake between SMU & RLC 2165 * GFXOFF will be disabled 2166 */ 2167 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2168 } else 2169 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2170 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2171 } 2172 2173 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2174 { 2175 /* TODO: enable rlc & smu handshake until smu 2176 * and gfxoff feature works as expected */ 2177 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2178 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2179 2180 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2181 udelay(50); 2182 } 2183 2184 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2185 { 2186 uint32_t tmp; 2187 2188 /* enable Save Restore Machine */ 2189 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2190 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2191 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2192 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2193 } 2194 2195 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2196 { 2197 const struct rlc_firmware_header_v2_0 *hdr; 2198 const __le32 *fw_data; 2199 unsigned i, fw_size; 2200 2201 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2202 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2203 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2204 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2205 2206 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2207 RLCG_UCODE_LOADING_START_ADDRESS); 2208 2209 for (i = 0; i < fw_size; i++) 2210 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2211 le32_to_cpup(fw_data++)); 2212 2213 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2214 } 2215 2216 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2217 { 2218 const struct rlc_firmware_header_v2_2 *hdr; 2219 const __le32 *fw_data; 2220 unsigned i, fw_size; 2221 u32 tmp; 2222 2223 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2224 2225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2226 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2227 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2228 2229 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2230 2231 for (i = 0; i < fw_size; i++) { 2232 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2233 msleep(1); 2234 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2235 le32_to_cpup(fw_data++)); 2236 } 2237 2238 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2239 2240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2241 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2242 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2243 2244 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2245 for (i = 0; i < fw_size; i++) { 2246 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2247 msleep(1); 2248 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2249 le32_to_cpup(fw_data++)); 2250 } 2251 2252 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2253 2254 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2255 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2256 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2257 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2258 } 2259 2260 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2261 { 2262 const struct rlc_firmware_header_v2_3 *hdr; 2263 const __le32 *fw_data; 2264 unsigned i, fw_size; 2265 u32 tmp; 2266 2267 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2268 2269 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2270 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2271 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2272 2273 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2274 2275 for (i = 0; i < fw_size; i++) { 2276 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2277 msleep(1); 2278 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2279 le32_to_cpup(fw_data++)); 2280 } 2281 2282 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2283 2284 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2285 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2286 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2287 2288 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2289 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2290 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2291 2292 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2293 2294 for (i = 0; i < fw_size; i++) { 2295 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2296 msleep(1); 2297 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2298 le32_to_cpup(fw_data++)); 2299 } 2300 2301 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2302 2303 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2304 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2305 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2306 } 2307 2308 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2309 { 2310 const struct rlc_firmware_header_v2_0 *hdr; 2311 uint16_t version_major; 2312 uint16_t version_minor; 2313 2314 if (!adev->gfx.rlc_fw) 2315 return -EINVAL; 2316 2317 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2318 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2319 2320 version_major = le16_to_cpu(hdr->header.header_version_major); 2321 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2322 2323 if (version_major == 2) { 2324 gfx_v11_0_load_rlcg_microcode(adev); 2325 if (amdgpu_dpm == 1) { 2326 if (version_minor >= 2) 2327 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2328 if (version_minor == 3) 2329 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2330 } 2331 2332 return 0; 2333 } 2334 2335 return -EINVAL; 2336 } 2337 2338 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2339 { 2340 int r; 2341 2342 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2343 gfx_v11_0_init_csb(adev); 2344 2345 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2346 gfx_v11_0_rlc_enable_srm(adev); 2347 } else { 2348 if (amdgpu_sriov_vf(adev)) { 2349 gfx_v11_0_init_csb(adev); 2350 return 0; 2351 } 2352 2353 adev->gfx.rlc.funcs->stop(adev); 2354 2355 /* disable CG */ 2356 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2357 2358 /* disable PG */ 2359 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2360 2361 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2362 /* legacy rlc firmware loading */ 2363 r = gfx_v11_0_rlc_load_microcode(adev); 2364 if (r) 2365 return r; 2366 } 2367 2368 gfx_v11_0_init_csb(adev); 2369 2370 adev->gfx.rlc.funcs->start(adev); 2371 } 2372 return 0; 2373 } 2374 2375 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2376 { 2377 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2378 uint32_t tmp; 2379 int i; 2380 2381 /* Trigger an invalidation of the L1 instruction caches */ 2382 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2383 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2384 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2385 2386 /* Wait for invalidation complete */ 2387 for (i = 0; i < usec_timeout; i++) { 2388 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2389 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2390 INVALIDATE_CACHE_COMPLETE)) 2391 break; 2392 udelay(1); 2393 } 2394 2395 if (i >= usec_timeout) { 2396 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2397 return -EINVAL; 2398 } 2399 2400 if (amdgpu_emu_mode == 1) 2401 adev->hdp.funcs->flush_hdp(adev, NULL); 2402 2403 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2404 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2405 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2406 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2407 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2408 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2409 2410 /* Program me ucode address into intruction cache address register */ 2411 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2412 lower_32_bits(addr) & 0xFFFFF000); 2413 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2414 upper_32_bits(addr)); 2415 2416 return 0; 2417 } 2418 2419 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2420 { 2421 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2422 uint32_t tmp; 2423 int i; 2424 2425 /* Trigger an invalidation of the L1 instruction caches */ 2426 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2427 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2428 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2429 2430 /* Wait for invalidation complete */ 2431 for (i = 0; i < usec_timeout; i++) { 2432 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2433 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2434 INVALIDATE_CACHE_COMPLETE)) 2435 break; 2436 udelay(1); 2437 } 2438 2439 if (i >= usec_timeout) { 2440 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2441 return -EINVAL; 2442 } 2443 2444 if (amdgpu_emu_mode == 1) 2445 adev->hdp.funcs->flush_hdp(adev, NULL); 2446 2447 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2448 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2449 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2450 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2451 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2452 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2453 2454 /* Program pfp ucode address into intruction cache address register */ 2455 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2456 lower_32_bits(addr) & 0xFFFFF000); 2457 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2458 upper_32_bits(addr)); 2459 2460 return 0; 2461 } 2462 2463 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2464 { 2465 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2466 uint32_t tmp; 2467 int i; 2468 2469 /* Trigger an invalidation of the L1 instruction caches */ 2470 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2471 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2472 2473 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2474 2475 /* Wait for invalidation complete */ 2476 for (i = 0; i < usec_timeout; i++) { 2477 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2478 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2479 INVALIDATE_CACHE_COMPLETE)) 2480 break; 2481 udelay(1); 2482 } 2483 2484 if (i >= usec_timeout) { 2485 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2486 return -EINVAL; 2487 } 2488 2489 if (amdgpu_emu_mode == 1) 2490 adev->hdp.funcs->flush_hdp(adev, NULL); 2491 2492 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2493 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2494 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2495 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2496 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2497 2498 /* Program mec1 ucode address into intruction cache address register */ 2499 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2500 lower_32_bits(addr) & 0xFFFFF000); 2501 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2502 upper_32_bits(addr)); 2503 2504 return 0; 2505 } 2506 2507 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2508 { 2509 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2510 uint32_t tmp; 2511 unsigned i, pipe_id; 2512 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2513 2514 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2515 adev->gfx.pfp_fw->data; 2516 2517 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2518 lower_32_bits(addr)); 2519 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2520 upper_32_bits(addr)); 2521 2522 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2523 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2524 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2525 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2526 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2527 2528 /* 2529 * Programming any of the CP_PFP_IC_BASE registers 2530 * forces invalidation of the ME L1 I$. Wait for the 2531 * invalidation complete 2532 */ 2533 for (i = 0; i < usec_timeout; i++) { 2534 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2535 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2536 INVALIDATE_CACHE_COMPLETE)) 2537 break; 2538 udelay(1); 2539 } 2540 2541 if (i >= usec_timeout) { 2542 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2543 return -EINVAL; 2544 } 2545 2546 /* Prime the L1 instruction caches */ 2547 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2548 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2549 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2550 /* Waiting for cache primed*/ 2551 for (i = 0; i < usec_timeout; i++) { 2552 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2553 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2554 ICACHE_PRIMED)) 2555 break; 2556 udelay(1); 2557 } 2558 2559 if (i >= usec_timeout) { 2560 dev_err(adev->dev, "failed to prime instruction cache\n"); 2561 return -EINVAL; 2562 } 2563 2564 mutex_lock(&adev->srbm_mutex); 2565 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2566 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2567 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2568 (pfp_hdr->ucode_start_addr_hi << 30) | 2569 (pfp_hdr->ucode_start_addr_lo >> 2)); 2570 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2571 pfp_hdr->ucode_start_addr_hi >> 2); 2572 2573 /* 2574 * Program CP_ME_CNTL to reset given PIPE to take 2575 * effect of CP_PFP_PRGRM_CNTR_START. 2576 */ 2577 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2578 if (pipe_id == 0) 2579 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2580 PFP_PIPE0_RESET, 1); 2581 else 2582 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2583 PFP_PIPE1_RESET, 1); 2584 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2585 2586 /* Clear pfp pipe0 reset bit. */ 2587 if (pipe_id == 0) 2588 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2589 PFP_PIPE0_RESET, 0); 2590 else 2591 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2592 PFP_PIPE1_RESET, 0); 2593 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2594 2595 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2596 lower_32_bits(addr2)); 2597 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2598 upper_32_bits(addr2)); 2599 } 2600 soc21_grbm_select(adev, 0, 0, 0, 0); 2601 mutex_unlock(&adev->srbm_mutex); 2602 2603 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2604 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2605 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2607 2608 /* Invalidate the data caches */ 2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2611 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2612 2613 for (i = 0; i < usec_timeout; i++) { 2614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2615 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2616 INVALIDATE_DCACHE_COMPLETE)) 2617 break; 2618 udelay(1); 2619 } 2620 2621 if (i >= usec_timeout) { 2622 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2623 return -EINVAL; 2624 } 2625 2626 return 0; 2627 } 2628 2629 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2630 { 2631 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2632 uint32_t tmp; 2633 unsigned i, pipe_id; 2634 const struct gfx_firmware_header_v2_0 *me_hdr; 2635 2636 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2637 adev->gfx.me_fw->data; 2638 2639 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2640 lower_32_bits(addr)); 2641 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2642 upper_32_bits(addr)); 2643 2644 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2645 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2646 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2647 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2648 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2649 2650 /* 2651 * Programming any of the CP_ME_IC_BASE registers 2652 * forces invalidation of the ME L1 I$. Wait for the 2653 * invalidation complete 2654 */ 2655 for (i = 0; i < usec_timeout; i++) { 2656 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2657 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2658 INVALIDATE_CACHE_COMPLETE)) 2659 break; 2660 udelay(1); 2661 } 2662 2663 if (i >= usec_timeout) { 2664 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2665 return -EINVAL; 2666 } 2667 2668 /* Prime the instruction caches */ 2669 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2670 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2671 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2672 2673 /* Waiting for instruction cache primed*/ 2674 for (i = 0; i < usec_timeout; i++) { 2675 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2676 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2677 ICACHE_PRIMED)) 2678 break; 2679 udelay(1); 2680 } 2681 2682 if (i >= usec_timeout) { 2683 dev_err(adev->dev, "failed to prime instruction cache\n"); 2684 return -EINVAL; 2685 } 2686 2687 mutex_lock(&adev->srbm_mutex); 2688 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2689 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2690 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2691 (me_hdr->ucode_start_addr_hi << 30) | 2692 (me_hdr->ucode_start_addr_lo >> 2) ); 2693 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2694 me_hdr->ucode_start_addr_hi>>2); 2695 2696 /* 2697 * Program CP_ME_CNTL to reset given PIPE to take 2698 * effect of CP_PFP_PRGRM_CNTR_START. 2699 */ 2700 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2701 if (pipe_id == 0) 2702 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2703 ME_PIPE0_RESET, 1); 2704 else 2705 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2706 ME_PIPE1_RESET, 1); 2707 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2708 2709 /* Clear pfp pipe0 reset bit. */ 2710 if (pipe_id == 0) 2711 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2712 ME_PIPE0_RESET, 0); 2713 else 2714 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2715 ME_PIPE1_RESET, 0); 2716 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2717 2718 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2719 lower_32_bits(addr2)); 2720 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2721 upper_32_bits(addr2)); 2722 } 2723 soc21_grbm_select(adev, 0, 0, 0, 0); 2724 mutex_unlock(&adev->srbm_mutex); 2725 2726 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2727 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2728 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2729 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2730 2731 /* Invalidate the data caches */ 2732 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2733 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2734 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2735 2736 for (i = 0; i < usec_timeout; i++) { 2737 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2738 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2739 INVALIDATE_DCACHE_COMPLETE)) 2740 break; 2741 udelay(1); 2742 } 2743 2744 if (i >= usec_timeout) { 2745 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2746 return -EINVAL; 2747 } 2748 2749 return 0; 2750 } 2751 2752 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2753 { 2754 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2755 uint32_t tmp; 2756 unsigned i; 2757 const struct gfx_firmware_header_v2_0 *mec_hdr; 2758 2759 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2760 adev->gfx.mec_fw->data; 2761 2762 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2763 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2764 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2765 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2766 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2767 2768 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2769 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2770 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2771 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2772 2773 mutex_lock(&adev->srbm_mutex); 2774 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2775 soc21_grbm_select(adev, 1, i, 0, 0); 2776 2777 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2778 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2779 upper_32_bits(addr2)); 2780 2781 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2782 mec_hdr->ucode_start_addr_lo >> 2 | 2783 mec_hdr->ucode_start_addr_hi << 30); 2784 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2785 mec_hdr->ucode_start_addr_hi >> 2); 2786 2787 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2788 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2789 upper_32_bits(addr)); 2790 } 2791 mutex_unlock(&adev->srbm_mutex); 2792 soc21_grbm_select(adev, 0, 0, 0, 0); 2793 2794 /* Trigger an invalidation of the L1 instruction caches */ 2795 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2796 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2797 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2798 2799 /* Wait for invalidation complete */ 2800 for (i = 0; i < usec_timeout; i++) { 2801 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2802 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2803 INVALIDATE_DCACHE_COMPLETE)) 2804 break; 2805 udelay(1); 2806 } 2807 2808 if (i >= usec_timeout) { 2809 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2810 return -EINVAL; 2811 } 2812 2813 /* Trigger an invalidation of the L1 instruction caches */ 2814 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2815 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2816 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2817 2818 /* Wait for invalidation complete */ 2819 for (i = 0; i < usec_timeout; i++) { 2820 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2821 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2822 INVALIDATE_CACHE_COMPLETE)) 2823 break; 2824 udelay(1); 2825 } 2826 2827 if (i >= usec_timeout) { 2828 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2829 return -EINVAL; 2830 } 2831 2832 return 0; 2833 } 2834 2835 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2836 { 2837 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2838 const struct gfx_firmware_header_v2_0 *me_hdr; 2839 const struct gfx_firmware_header_v2_0 *mec_hdr; 2840 uint32_t pipe_id, tmp; 2841 2842 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2843 adev->gfx.mec_fw->data; 2844 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2845 adev->gfx.me_fw->data; 2846 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2847 adev->gfx.pfp_fw->data; 2848 2849 /* config pfp program start addr */ 2850 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2851 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2852 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2853 (pfp_hdr->ucode_start_addr_hi << 30) | 2854 (pfp_hdr->ucode_start_addr_lo >> 2)); 2855 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2856 pfp_hdr->ucode_start_addr_hi >> 2); 2857 } 2858 soc21_grbm_select(adev, 0, 0, 0, 0); 2859 2860 /* reset pfp pipe */ 2861 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2862 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2863 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2864 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2865 2866 /* clear pfp pipe reset */ 2867 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2868 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2869 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2870 2871 /* config me program start addr */ 2872 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2873 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2874 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2875 (me_hdr->ucode_start_addr_hi << 30) | 2876 (me_hdr->ucode_start_addr_lo >> 2) ); 2877 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2878 me_hdr->ucode_start_addr_hi>>2); 2879 } 2880 soc21_grbm_select(adev, 0, 0, 0, 0); 2881 2882 /* reset me pipe */ 2883 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2884 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2885 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2886 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2887 2888 /* clear me pipe reset */ 2889 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2890 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2891 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2892 2893 /* config mec program start addr */ 2894 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2895 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2896 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2897 mec_hdr->ucode_start_addr_lo >> 2 | 2898 mec_hdr->ucode_start_addr_hi << 30); 2899 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2900 mec_hdr->ucode_start_addr_hi >> 2); 2901 } 2902 soc21_grbm_select(adev, 0, 0, 0, 0); 2903 2904 /* reset mec pipe */ 2905 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2906 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2907 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2908 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2909 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2910 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2911 2912 /* clear mec pipe reset */ 2913 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2914 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2915 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2916 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2917 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2918 } 2919 2920 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2921 { 2922 uint32_t cp_status; 2923 uint32_t bootload_status; 2924 int i, r; 2925 uint64_t addr, addr2; 2926 2927 for (i = 0; i < adev->usec_timeout; i++) { 2928 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2929 2930 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2931 IP_VERSION(11, 0, 1) || 2932 amdgpu_ip_version(adev, GC_HWIP, 0) == 2933 IP_VERSION(11, 0, 4) || 2934 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || 2935 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || 2936 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || 2937 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) 2938 bootload_status = RREG32_SOC15(GC, 0, 2939 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2940 else 2941 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2942 2943 if ((cp_status == 0) && 2944 (REG_GET_FIELD(bootload_status, 2945 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2946 break; 2947 } 2948 udelay(1); 2949 } 2950 2951 if (i >= adev->usec_timeout) { 2952 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2953 return -ETIMEDOUT; 2954 } 2955 2956 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2957 if (adev->gfx.rs64_enable) { 2958 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2959 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2960 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2961 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2962 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2963 if (r) 2964 return r; 2965 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2966 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2967 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2968 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2969 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2970 if (r) 2971 return r; 2972 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2973 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2974 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2975 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2976 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2977 if (r) 2978 return r; 2979 } else { 2980 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2981 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2982 r = gfx_v11_0_config_me_cache(adev, addr); 2983 if (r) 2984 return r; 2985 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2986 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2987 r = gfx_v11_0_config_pfp_cache(adev, addr); 2988 if (r) 2989 return r; 2990 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2991 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2992 r = gfx_v11_0_config_mec_cache(adev, addr); 2993 if (r) 2994 return r; 2995 } 2996 } 2997 2998 return 0; 2999 } 3000 3001 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3002 { 3003 int i; 3004 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3005 3006 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3007 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3008 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3009 3010 for (i = 0; i < adev->usec_timeout; i++) { 3011 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 3012 break; 3013 udelay(1); 3014 } 3015 3016 if (i >= adev->usec_timeout) 3017 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 3018 3019 return 0; 3020 } 3021 3022 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 3023 { 3024 int r; 3025 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3026 const __le32 *fw_data; 3027 unsigned i, fw_size; 3028 3029 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3030 adev->gfx.pfp_fw->data; 3031 3032 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3033 3034 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3035 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3036 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 3037 3038 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 3039 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3040 &adev->gfx.pfp.pfp_fw_obj, 3041 &adev->gfx.pfp.pfp_fw_gpu_addr, 3042 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3043 if (r) { 3044 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 3045 gfx_v11_0_pfp_fini(adev); 3046 return r; 3047 } 3048 3049 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 3050 3051 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3052 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3053 3054 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 3055 3056 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 3057 3058 for (i = 0; i < pfp_hdr->jt_size; i++) 3059 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 3060 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 3061 3062 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3063 3064 return 0; 3065 } 3066 3067 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 3068 { 3069 int r; 3070 const struct gfx_firmware_header_v2_0 *pfp_hdr; 3071 const __le32 *fw_ucode, *fw_data; 3072 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3073 uint32_t tmp; 3074 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3075 3076 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 3077 adev->gfx.pfp_fw->data; 3078 3079 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3080 3081 /* instruction */ 3082 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 3083 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 3084 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 3085 /* data */ 3086 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 3087 le32_to_cpu(pfp_hdr->data_offset_bytes)); 3088 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 3089 3090 /* 64kb align */ 3091 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3092 64 * 1024, 3093 AMDGPU_GEM_DOMAIN_VRAM | 3094 AMDGPU_GEM_DOMAIN_GTT, 3095 &adev->gfx.pfp.pfp_fw_obj, 3096 &adev->gfx.pfp.pfp_fw_gpu_addr, 3097 (void **)&adev->gfx.pfp.pfp_fw_ptr); 3098 if (r) { 3099 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 3100 gfx_v11_0_pfp_fini(adev); 3101 return r; 3102 } 3103 3104 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3105 64 * 1024, 3106 AMDGPU_GEM_DOMAIN_VRAM | 3107 AMDGPU_GEM_DOMAIN_GTT, 3108 &adev->gfx.pfp.pfp_fw_data_obj, 3109 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 3110 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 3111 if (r) { 3112 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 3113 gfx_v11_0_pfp_fini(adev); 3114 return r; 3115 } 3116 3117 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 3118 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 3119 3120 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 3121 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 3122 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 3123 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 3124 3125 if (amdgpu_emu_mode == 1) 3126 adev->hdp.funcs->flush_hdp(adev, NULL); 3127 3128 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 3129 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3130 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 3131 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 3132 3133 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 3134 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 3135 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 3136 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 3137 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 3138 3139 /* 3140 * Programming any of the CP_PFP_IC_BASE registers 3141 * forces invalidation of the ME L1 I$. Wait for the 3142 * invalidation complete 3143 */ 3144 for (i = 0; i < usec_timeout; i++) { 3145 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3146 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3147 INVALIDATE_CACHE_COMPLETE)) 3148 break; 3149 udelay(1); 3150 } 3151 3152 if (i >= usec_timeout) { 3153 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3154 return -EINVAL; 3155 } 3156 3157 /* Prime the L1 instruction caches */ 3158 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3159 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 3160 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 3161 /* Waiting for cache primed*/ 3162 for (i = 0; i < usec_timeout; i++) { 3163 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 3164 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 3165 ICACHE_PRIMED)) 3166 break; 3167 udelay(1); 3168 } 3169 3170 if (i >= usec_timeout) { 3171 dev_err(adev->dev, "failed to prime instruction cache\n"); 3172 return -EINVAL; 3173 } 3174 3175 mutex_lock(&adev->srbm_mutex); 3176 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3177 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3178 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3179 (pfp_hdr->ucode_start_addr_hi << 30) | 3180 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3181 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3182 pfp_hdr->ucode_start_addr_hi>>2); 3183 3184 /* 3185 * Program CP_ME_CNTL to reset given PIPE to take 3186 * effect of CP_PFP_PRGRM_CNTR_START. 3187 */ 3188 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3189 if (pipe_id == 0) 3190 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3191 PFP_PIPE0_RESET, 1); 3192 else 3193 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3194 PFP_PIPE1_RESET, 1); 3195 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3196 3197 /* Clear pfp pipe0 reset bit. */ 3198 if (pipe_id == 0) 3199 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3200 PFP_PIPE0_RESET, 0); 3201 else 3202 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3203 PFP_PIPE1_RESET, 0); 3204 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3205 3206 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3207 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3208 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3209 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3210 } 3211 soc21_grbm_select(adev, 0, 0, 0, 0); 3212 mutex_unlock(&adev->srbm_mutex); 3213 3214 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3215 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3216 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3217 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3218 3219 /* Invalidate the data caches */ 3220 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3221 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3222 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3223 3224 for (i = 0; i < usec_timeout; i++) { 3225 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3226 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3227 INVALIDATE_DCACHE_COMPLETE)) 3228 break; 3229 udelay(1); 3230 } 3231 3232 if (i >= usec_timeout) { 3233 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3234 return -EINVAL; 3235 } 3236 3237 return 0; 3238 } 3239 3240 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3241 { 3242 int r; 3243 const struct gfx_firmware_header_v1_0 *me_hdr; 3244 const __le32 *fw_data; 3245 unsigned i, fw_size; 3246 3247 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3248 adev->gfx.me_fw->data; 3249 3250 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3251 3252 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3253 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3254 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3255 3256 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3257 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3258 &adev->gfx.me.me_fw_obj, 3259 &adev->gfx.me.me_fw_gpu_addr, 3260 (void **)&adev->gfx.me.me_fw_ptr); 3261 if (r) { 3262 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3263 gfx_v11_0_me_fini(adev); 3264 return r; 3265 } 3266 3267 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3268 3269 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3270 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3271 3272 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3273 3274 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3275 3276 for (i = 0; i < me_hdr->jt_size; i++) 3277 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3278 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3279 3280 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3281 3282 return 0; 3283 } 3284 3285 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3286 { 3287 int r; 3288 const struct gfx_firmware_header_v2_0 *me_hdr; 3289 const __le32 *fw_ucode, *fw_data; 3290 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3291 uint32_t tmp; 3292 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3293 3294 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3295 adev->gfx.me_fw->data; 3296 3297 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3298 3299 /* instruction */ 3300 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3301 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3302 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3303 /* data */ 3304 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3305 le32_to_cpu(me_hdr->data_offset_bytes)); 3306 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3307 3308 /* 64kb align*/ 3309 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3310 64 * 1024, 3311 AMDGPU_GEM_DOMAIN_VRAM | 3312 AMDGPU_GEM_DOMAIN_GTT, 3313 &adev->gfx.me.me_fw_obj, 3314 &adev->gfx.me.me_fw_gpu_addr, 3315 (void **)&adev->gfx.me.me_fw_ptr); 3316 if (r) { 3317 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3318 gfx_v11_0_me_fini(adev); 3319 return r; 3320 } 3321 3322 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3323 64 * 1024, 3324 AMDGPU_GEM_DOMAIN_VRAM | 3325 AMDGPU_GEM_DOMAIN_GTT, 3326 &adev->gfx.me.me_fw_data_obj, 3327 &adev->gfx.me.me_fw_data_gpu_addr, 3328 (void **)&adev->gfx.me.me_fw_data_ptr); 3329 if (r) { 3330 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3331 gfx_v11_0_pfp_fini(adev); 3332 return r; 3333 } 3334 3335 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3336 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3337 3338 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3339 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3340 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3341 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3342 3343 if (amdgpu_emu_mode == 1) 3344 adev->hdp.funcs->flush_hdp(adev, NULL); 3345 3346 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3347 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3348 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3349 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3350 3351 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3352 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3353 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3354 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3355 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3356 3357 /* 3358 * Programming any of the CP_ME_IC_BASE registers 3359 * forces invalidation of the ME L1 I$. Wait for the 3360 * invalidation complete 3361 */ 3362 for (i = 0; i < usec_timeout; i++) { 3363 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3364 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3365 INVALIDATE_CACHE_COMPLETE)) 3366 break; 3367 udelay(1); 3368 } 3369 3370 if (i >= usec_timeout) { 3371 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3372 return -EINVAL; 3373 } 3374 3375 /* Prime the instruction caches */ 3376 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3377 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3378 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3379 3380 /* Waiting for instruction cache primed*/ 3381 for (i = 0; i < usec_timeout; i++) { 3382 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3383 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3384 ICACHE_PRIMED)) 3385 break; 3386 udelay(1); 3387 } 3388 3389 if (i >= usec_timeout) { 3390 dev_err(adev->dev, "failed to prime instruction cache\n"); 3391 return -EINVAL; 3392 } 3393 3394 mutex_lock(&adev->srbm_mutex); 3395 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3396 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3397 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3398 (me_hdr->ucode_start_addr_hi << 30) | 3399 (me_hdr->ucode_start_addr_lo >> 2) ); 3400 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3401 me_hdr->ucode_start_addr_hi>>2); 3402 3403 /* 3404 * Program CP_ME_CNTL to reset given PIPE to take 3405 * effect of CP_PFP_PRGRM_CNTR_START. 3406 */ 3407 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3408 if (pipe_id == 0) 3409 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3410 ME_PIPE0_RESET, 1); 3411 else 3412 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3413 ME_PIPE1_RESET, 1); 3414 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3415 3416 /* Clear pfp pipe0 reset bit. */ 3417 if (pipe_id == 0) 3418 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3419 ME_PIPE0_RESET, 0); 3420 else 3421 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3422 ME_PIPE1_RESET, 0); 3423 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3424 3425 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3426 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3427 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3428 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3429 } 3430 soc21_grbm_select(adev, 0, 0, 0, 0); 3431 mutex_unlock(&adev->srbm_mutex); 3432 3433 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3434 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3435 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3436 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3437 3438 /* Invalidate the data caches */ 3439 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3440 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3441 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3442 3443 for (i = 0; i < usec_timeout; i++) { 3444 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3445 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3446 INVALIDATE_DCACHE_COMPLETE)) 3447 break; 3448 udelay(1); 3449 } 3450 3451 if (i >= usec_timeout) { 3452 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3453 return -EINVAL; 3454 } 3455 3456 return 0; 3457 } 3458 3459 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3460 { 3461 int r; 3462 3463 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3464 return -EINVAL; 3465 3466 gfx_v11_0_cp_gfx_enable(adev, false); 3467 3468 if (adev->gfx.rs64_enable) 3469 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3470 else 3471 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3472 if (r) { 3473 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3474 return r; 3475 } 3476 3477 if (adev->gfx.rs64_enable) 3478 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3479 else 3480 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3481 if (r) { 3482 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3483 return r; 3484 } 3485 3486 return 0; 3487 } 3488 3489 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3490 { 3491 struct amdgpu_ring *ring; 3492 const struct cs_section_def *sect = NULL; 3493 const struct cs_extent_def *ext = NULL; 3494 int r, i; 3495 int ctx_reg_offset; 3496 3497 /* init the CP */ 3498 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3499 adev->gfx.config.max_hw_contexts - 1); 3500 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3501 3502 if (!amdgpu_async_gfx_ring) 3503 gfx_v11_0_cp_gfx_enable(adev, true); 3504 3505 ring = &adev->gfx.gfx_ring[0]; 3506 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3507 if (r) { 3508 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3509 return r; 3510 } 3511 3512 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3513 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3514 3515 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3516 amdgpu_ring_write(ring, 0x80000000); 3517 amdgpu_ring_write(ring, 0x80000000); 3518 3519 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3520 for (ext = sect->section; ext->extent != NULL; ++ext) { 3521 if (sect->id == SECT_CONTEXT) { 3522 amdgpu_ring_write(ring, 3523 PACKET3(PACKET3_SET_CONTEXT_REG, 3524 ext->reg_count)); 3525 amdgpu_ring_write(ring, ext->reg_index - 3526 PACKET3_SET_CONTEXT_REG_START); 3527 for (i = 0; i < ext->reg_count; i++) 3528 amdgpu_ring_write(ring, ext->extent[i]); 3529 } 3530 } 3531 } 3532 3533 ctx_reg_offset = 3534 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3535 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3536 amdgpu_ring_write(ring, ctx_reg_offset); 3537 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3538 3539 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3540 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3541 3542 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3543 amdgpu_ring_write(ring, 0); 3544 3545 amdgpu_ring_commit(ring); 3546 3547 /* submit cs packet to copy state 0 to next available state */ 3548 if (adev->gfx.num_gfx_rings > 1) { 3549 /* maximum supported gfx ring is 2 */ 3550 ring = &adev->gfx.gfx_ring[1]; 3551 r = amdgpu_ring_alloc(ring, 2); 3552 if (r) { 3553 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3554 return r; 3555 } 3556 3557 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3558 amdgpu_ring_write(ring, 0); 3559 3560 amdgpu_ring_commit(ring); 3561 } 3562 return 0; 3563 } 3564 3565 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3566 CP_PIPE_ID pipe) 3567 { 3568 u32 tmp; 3569 3570 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3571 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3572 3573 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3574 } 3575 3576 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3577 struct amdgpu_ring *ring) 3578 { 3579 u32 tmp; 3580 3581 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3582 if (ring->use_doorbell) { 3583 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3584 DOORBELL_OFFSET, ring->doorbell_index); 3585 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3586 DOORBELL_EN, 1); 3587 } else { 3588 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3589 DOORBELL_EN, 0); 3590 } 3591 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3592 3593 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3594 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3595 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3596 3597 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3598 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3599 } 3600 3601 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3602 { 3603 struct amdgpu_ring *ring; 3604 u32 tmp; 3605 u32 rb_bufsz; 3606 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3607 3608 /* Set the write pointer delay */ 3609 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3610 3611 /* set the RB to use vmid 0 */ 3612 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3613 3614 /* Init gfx ring 0 for pipe 0 */ 3615 mutex_lock(&adev->srbm_mutex); 3616 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3617 3618 /* Set ring buffer size */ 3619 ring = &adev->gfx.gfx_ring[0]; 3620 rb_bufsz = order_base_2(ring->ring_size / 8); 3621 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3622 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3623 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3624 3625 /* Initialize the ring buffer's write pointers */ 3626 ring->wptr = 0; 3627 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3628 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3629 3630 /* set the wb address whether it's enabled or not */ 3631 rptr_addr = ring->rptr_gpu_addr; 3632 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3633 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3634 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3635 3636 wptr_gpu_addr = ring->wptr_gpu_addr; 3637 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3638 lower_32_bits(wptr_gpu_addr)); 3639 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3640 upper_32_bits(wptr_gpu_addr)); 3641 3642 mdelay(1); 3643 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3644 3645 rb_addr = ring->gpu_addr >> 8; 3646 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3647 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3648 3649 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3650 3651 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3652 mutex_unlock(&adev->srbm_mutex); 3653 3654 /* Init gfx ring 1 for pipe 1 */ 3655 if (adev->gfx.num_gfx_rings > 1) { 3656 mutex_lock(&adev->srbm_mutex); 3657 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3658 /* maximum supported gfx ring is 2 */ 3659 ring = &adev->gfx.gfx_ring[1]; 3660 rb_bufsz = order_base_2(ring->ring_size / 8); 3661 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3662 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3663 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3664 /* Initialize the ring buffer's write pointers */ 3665 ring->wptr = 0; 3666 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3667 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3668 /* Set the wb address whether it's enabled or not */ 3669 rptr_addr = ring->rptr_gpu_addr; 3670 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3671 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3672 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3673 wptr_gpu_addr = ring->wptr_gpu_addr; 3674 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3675 lower_32_bits(wptr_gpu_addr)); 3676 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3677 upper_32_bits(wptr_gpu_addr)); 3678 3679 mdelay(1); 3680 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3681 3682 rb_addr = ring->gpu_addr >> 8; 3683 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3684 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3685 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3686 3687 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3688 mutex_unlock(&adev->srbm_mutex); 3689 } 3690 /* Switch to pipe 0 */ 3691 mutex_lock(&adev->srbm_mutex); 3692 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3693 mutex_unlock(&adev->srbm_mutex); 3694 3695 /* start the ring */ 3696 gfx_v11_0_cp_gfx_start(adev); 3697 3698 return 0; 3699 } 3700 3701 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3702 { 3703 u32 data; 3704 3705 if (adev->gfx.rs64_enable) { 3706 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3707 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3708 enable ? 0 : 1); 3709 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3710 enable ? 0 : 1); 3711 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3712 enable ? 0 : 1); 3713 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3714 enable ? 0 : 1); 3715 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3716 enable ? 0 : 1); 3717 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3718 enable ? 1 : 0); 3719 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3720 enable ? 1 : 0); 3721 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3722 enable ? 1 : 0); 3723 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3724 enable ? 1 : 0); 3725 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3726 enable ? 0 : 1); 3727 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3728 } else { 3729 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3730 3731 if (enable) { 3732 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3733 if (!adev->enable_mes_kiq) 3734 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3735 MEC_ME2_HALT, 0); 3736 } else { 3737 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3738 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3739 } 3740 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3741 } 3742 3743 udelay(50); 3744 } 3745 3746 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3747 { 3748 const struct gfx_firmware_header_v1_0 *mec_hdr; 3749 const __le32 *fw_data; 3750 unsigned i, fw_size; 3751 u32 *fw = NULL; 3752 int r; 3753 3754 if (!adev->gfx.mec_fw) 3755 return -EINVAL; 3756 3757 gfx_v11_0_cp_compute_enable(adev, false); 3758 3759 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3760 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3761 3762 fw_data = (const __le32 *) 3763 (adev->gfx.mec_fw->data + 3764 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3765 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3766 3767 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3768 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3769 &adev->gfx.mec.mec_fw_obj, 3770 &adev->gfx.mec.mec_fw_gpu_addr, 3771 (void **)&fw); 3772 if (r) { 3773 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3774 gfx_v11_0_mec_fini(adev); 3775 return r; 3776 } 3777 3778 memcpy(fw, fw_data, fw_size); 3779 3780 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3781 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3782 3783 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3784 3785 /* MEC1 */ 3786 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3787 3788 for (i = 0; i < mec_hdr->jt_size; i++) 3789 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3790 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3791 3792 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3793 3794 return 0; 3795 } 3796 3797 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3798 { 3799 const struct gfx_firmware_header_v2_0 *mec_hdr; 3800 const __le32 *fw_ucode, *fw_data; 3801 u32 tmp, fw_ucode_size, fw_data_size; 3802 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3803 u32 *fw_ucode_ptr, *fw_data_ptr; 3804 int r; 3805 3806 if (!adev->gfx.mec_fw) 3807 return -EINVAL; 3808 3809 gfx_v11_0_cp_compute_enable(adev, false); 3810 3811 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3812 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3813 3814 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3815 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3816 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3817 3818 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3819 le32_to_cpu(mec_hdr->data_offset_bytes)); 3820 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3821 3822 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3823 64 * 1024, 3824 AMDGPU_GEM_DOMAIN_VRAM | 3825 AMDGPU_GEM_DOMAIN_GTT, 3826 &adev->gfx.mec.mec_fw_obj, 3827 &adev->gfx.mec.mec_fw_gpu_addr, 3828 (void **)&fw_ucode_ptr); 3829 if (r) { 3830 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3831 gfx_v11_0_mec_fini(adev); 3832 return r; 3833 } 3834 3835 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3836 64 * 1024, 3837 AMDGPU_GEM_DOMAIN_VRAM | 3838 AMDGPU_GEM_DOMAIN_GTT, 3839 &adev->gfx.mec.mec_fw_data_obj, 3840 &adev->gfx.mec.mec_fw_data_gpu_addr, 3841 (void **)&fw_data_ptr); 3842 if (r) { 3843 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3844 gfx_v11_0_mec_fini(adev); 3845 return r; 3846 } 3847 3848 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3849 memcpy(fw_data_ptr, fw_data, fw_data_size); 3850 3851 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3852 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3853 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3854 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3855 3856 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3857 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3858 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3859 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3860 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3861 3862 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3863 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3864 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3865 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3866 3867 mutex_lock(&adev->srbm_mutex); 3868 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3869 soc21_grbm_select(adev, 1, i, 0, 0); 3870 3871 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3872 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3873 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3874 3875 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3876 mec_hdr->ucode_start_addr_lo >> 2 | 3877 mec_hdr->ucode_start_addr_hi << 30); 3878 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3879 mec_hdr->ucode_start_addr_hi >> 2); 3880 3881 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3882 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3883 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3884 } 3885 mutex_unlock(&adev->srbm_mutex); 3886 soc21_grbm_select(adev, 0, 0, 0, 0); 3887 3888 /* Trigger an invalidation of the L1 instruction caches */ 3889 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3890 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3891 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3892 3893 /* Wait for invalidation complete */ 3894 for (i = 0; i < usec_timeout; i++) { 3895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3896 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3897 INVALIDATE_DCACHE_COMPLETE)) 3898 break; 3899 udelay(1); 3900 } 3901 3902 if (i >= usec_timeout) { 3903 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3904 return -EINVAL; 3905 } 3906 3907 /* Trigger an invalidation of the L1 instruction caches */ 3908 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3909 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3910 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3911 3912 /* Wait for invalidation complete */ 3913 for (i = 0; i < usec_timeout; i++) { 3914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3915 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3916 INVALIDATE_CACHE_COMPLETE)) 3917 break; 3918 udelay(1); 3919 } 3920 3921 if (i >= usec_timeout) { 3922 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3923 return -EINVAL; 3924 } 3925 3926 return 0; 3927 } 3928 3929 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3930 { 3931 uint32_t tmp; 3932 struct amdgpu_device *adev = ring->adev; 3933 3934 /* tell RLC which is KIQ queue */ 3935 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3936 tmp &= 0xffffff00; 3937 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3938 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 3939 } 3940 3941 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3942 { 3943 /* set graphics engine doorbell range */ 3944 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3945 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3946 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3947 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3948 3949 /* set compute engine doorbell range */ 3950 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3951 (adev->doorbell_index.kiq * 2) << 2); 3952 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3953 (adev->doorbell_index.userqueue_end * 2) << 2); 3954 } 3955 3956 static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 3957 struct v11_gfx_mqd *mqd, 3958 struct amdgpu_mqd_prop *prop) 3959 { 3960 bool priority = 0; 3961 u32 tmp; 3962 3963 /* set up default queue priority level 3964 * 0x0 = low priority, 0x1 = high priority 3965 */ 3966 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 3967 priority = 1; 3968 3969 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3970 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 3971 mqd->cp_gfx_hqd_queue_priority = tmp; 3972 } 3973 3974 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3975 struct amdgpu_mqd_prop *prop) 3976 { 3977 struct v11_gfx_mqd *mqd = m; 3978 uint64_t hqd_gpu_addr, wb_gpu_addr; 3979 uint32_t tmp; 3980 uint32_t rb_bufsz; 3981 3982 /* set up gfx hqd wptr */ 3983 mqd->cp_gfx_hqd_wptr = 0; 3984 mqd->cp_gfx_hqd_wptr_hi = 0; 3985 3986 /* set the pointer to the MQD */ 3987 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3988 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3989 3990 /* set up mqd control */ 3991 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3992 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3993 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3994 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3995 mqd->cp_gfx_mqd_control = tmp; 3996 3997 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3998 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3999 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 4000 mqd->cp_gfx_hqd_vmid = 0; 4001 4002 /* set up gfx queue priority */ 4003 gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop); 4004 4005 /* set up time quantum */ 4006 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 4007 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 4008 mqd->cp_gfx_hqd_quantum = tmp; 4009 4010 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 4011 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4012 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 4013 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 4014 4015 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 4016 wb_gpu_addr = prop->rptr_gpu_addr; 4017 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 4018 mqd->cp_gfx_hqd_rptr_addr_hi = 4019 upper_32_bits(wb_gpu_addr) & 0xffff; 4020 4021 /* set up rb_wptr_poll addr */ 4022 wb_gpu_addr = prop->wptr_gpu_addr; 4023 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4024 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4025 4026 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 4027 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 4028 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 4029 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 4030 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 4031 #ifdef __BIG_ENDIAN 4032 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 4033 #endif 4034 mqd->cp_gfx_hqd_cntl = tmp; 4035 4036 /* set up cp_doorbell_control */ 4037 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 4038 if (prop->use_doorbell) { 4039 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4040 DOORBELL_OFFSET, prop->doorbell_index); 4041 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4042 DOORBELL_EN, 1); 4043 } else 4044 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4045 DOORBELL_EN, 0); 4046 mqd->cp_rb_doorbell_control = tmp; 4047 4048 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4049 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 4050 4051 /* active the queue */ 4052 mqd->cp_gfx_hqd_active = 1; 4053 4054 return 0; 4055 } 4056 4057 static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 4058 { 4059 struct amdgpu_device *adev = ring->adev; 4060 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 4061 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 4062 4063 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4064 memset((void *)mqd, 0, sizeof(*mqd)); 4065 mutex_lock(&adev->srbm_mutex); 4066 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4067 amdgpu_ring_init_mqd(ring); 4068 soc21_grbm_select(adev, 0, 0, 0, 0); 4069 mutex_unlock(&adev->srbm_mutex); 4070 if (adev->gfx.me.mqd_backup[mqd_idx]) 4071 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4072 } else { 4073 /* restore mqd with the backup copy */ 4074 if (adev->gfx.me.mqd_backup[mqd_idx]) 4075 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4076 /* reset the ring */ 4077 ring->wptr = 0; 4078 *ring->wptr_cpu_addr = 0; 4079 amdgpu_ring_clear_ring(ring); 4080 } 4081 4082 return 0; 4083 } 4084 4085 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 4086 { 4087 int r, i; 4088 struct amdgpu_ring *ring; 4089 4090 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4091 ring = &adev->gfx.gfx_ring[i]; 4092 4093 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4094 if (unlikely(r != 0)) 4095 return r; 4096 4097 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4098 if (!r) { 4099 r = gfx_v11_0_kgq_init_queue(ring, false); 4100 amdgpu_bo_kunmap(ring->mqd_obj); 4101 ring->mqd_ptr = NULL; 4102 } 4103 amdgpu_bo_unreserve(ring->mqd_obj); 4104 if (r) 4105 return r; 4106 } 4107 4108 r = amdgpu_gfx_enable_kgq(adev, 0); 4109 if (r) 4110 return r; 4111 4112 return gfx_v11_0_cp_gfx_start(adev); 4113 } 4114 4115 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4116 struct amdgpu_mqd_prop *prop) 4117 { 4118 struct v11_compute_mqd *mqd = m; 4119 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4120 uint32_t tmp; 4121 4122 mqd->header = 0xC0310800; 4123 mqd->compute_pipelinestat_enable = 0x00000001; 4124 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4125 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4126 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4127 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4128 mqd->compute_misc_reserved = 0x00000007; 4129 4130 eop_base_addr = prop->eop_gpu_addr >> 8; 4131 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4132 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4133 4134 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4135 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4136 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4137 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4138 4139 mqd->cp_hqd_eop_control = tmp; 4140 4141 /* enable doorbell? */ 4142 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4143 4144 if (prop->use_doorbell) { 4145 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4146 DOORBELL_OFFSET, prop->doorbell_index); 4147 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4148 DOORBELL_EN, 1); 4149 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4150 DOORBELL_SOURCE, 0); 4151 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4152 DOORBELL_HIT, 0); 4153 } else { 4154 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4155 DOORBELL_EN, 0); 4156 } 4157 4158 mqd->cp_hqd_pq_doorbell_control = tmp; 4159 4160 /* disable the queue if it's active */ 4161 mqd->cp_hqd_dequeue_request = 0; 4162 mqd->cp_hqd_pq_rptr = 0; 4163 mqd->cp_hqd_pq_wptr_lo = 0; 4164 mqd->cp_hqd_pq_wptr_hi = 0; 4165 4166 /* set the pointer to the MQD */ 4167 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4168 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4169 4170 /* set MQD vmid to 0 */ 4171 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4172 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4173 mqd->cp_mqd_control = tmp; 4174 4175 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4176 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4177 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4178 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4179 4180 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4181 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4183 (order_base_2(prop->queue_size / 4) - 1)); 4184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4185 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4188 prop->allow_tunneling); 4189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4190 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4191 mqd->cp_hqd_pq_control = tmp; 4192 4193 /* set the wb address whether it's enabled or not */ 4194 wb_gpu_addr = prop->rptr_gpu_addr; 4195 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4196 mqd->cp_hqd_pq_rptr_report_addr_hi = 4197 upper_32_bits(wb_gpu_addr) & 0xffff; 4198 4199 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4200 wb_gpu_addr = prop->wptr_gpu_addr; 4201 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4202 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4203 4204 tmp = 0; 4205 /* enable the doorbell if requested */ 4206 if (prop->use_doorbell) { 4207 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4209 DOORBELL_OFFSET, prop->doorbell_index); 4210 4211 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4212 DOORBELL_EN, 1); 4213 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4214 DOORBELL_SOURCE, 0); 4215 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4216 DOORBELL_HIT, 0); 4217 } 4218 4219 mqd->cp_hqd_pq_doorbell_control = tmp; 4220 4221 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4222 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4223 4224 /* set the vmid for the queue */ 4225 mqd->cp_hqd_vmid = 0; 4226 4227 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4228 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4229 mqd->cp_hqd_persistent_state = tmp; 4230 4231 /* set MIN_IB_AVAIL_SIZE */ 4232 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4233 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4234 mqd->cp_hqd_ib_control = tmp; 4235 4236 /* set static priority for a compute queue/ring */ 4237 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4238 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4239 4240 mqd->cp_hqd_active = prop->hqd_active; 4241 4242 return 0; 4243 } 4244 4245 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4246 { 4247 struct amdgpu_device *adev = ring->adev; 4248 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4249 int j; 4250 4251 /* inactivate the queue */ 4252 if (amdgpu_sriov_vf(adev)) 4253 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4254 4255 /* disable wptr polling */ 4256 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4257 4258 /* write the EOP addr */ 4259 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4260 mqd->cp_hqd_eop_base_addr_lo); 4261 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4262 mqd->cp_hqd_eop_base_addr_hi); 4263 4264 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4265 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4266 mqd->cp_hqd_eop_control); 4267 4268 /* enable doorbell? */ 4269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4270 mqd->cp_hqd_pq_doorbell_control); 4271 4272 /* disable the queue if it's active */ 4273 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4274 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4275 for (j = 0; j < adev->usec_timeout; j++) { 4276 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4277 break; 4278 udelay(1); 4279 } 4280 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4281 mqd->cp_hqd_dequeue_request); 4282 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4283 mqd->cp_hqd_pq_rptr); 4284 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4285 mqd->cp_hqd_pq_wptr_lo); 4286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4287 mqd->cp_hqd_pq_wptr_hi); 4288 } 4289 4290 /* set the pointer to the MQD */ 4291 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4292 mqd->cp_mqd_base_addr_lo); 4293 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4294 mqd->cp_mqd_base_addr_hi); 4295 4296 /* set MQD vmid to 0 */ 4297 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4298 mqd->cp_mqd_control); 4299 4300 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4301 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4302 mqd->cp_hqd_pq_base_lo); 4303 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4304 mqd->cp_hqd_pq_base_hi); 4305 4306 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4307 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4308 mqd->cp_hqd_pq_control); 4309 4310 /* set the wb address whether it's enabled or not */ 4311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4312 mqd->cp_hqd_pq_rptr_report_addr_lo); 4313 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4314 mqd->cp_hqd_pq_rptr_report_addr_hi); 4315 4316 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4317 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4318 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4320 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4321 4322 /* enable the doorbell if requested */ 4323 if (ring->use_doorbell) { 4324 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4325 (adev->doorbell_index.kiq * 2) << 2); 4326 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4327 (adev->doorbell_index.userqueue_end * 2) << 2); 4328 } 4329 4330 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4331 mqd->cp_hqd_pq_doorbell_control); 4332 4333 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4335 mqd->cp_hqd_pq_wptr_lo); 4336 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4337 mqd->cp_hqd_pq_wptr_hi); 4338 4339 /* set the vmid for the queue */ 4340 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4341 4342 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4343 mqd->cp_hqd_persistent_state); 4344 4345 /* activate the queue */ 4346 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4347 mqd->cp_hqd_active); 4348 4349 if (ring->use_doorbell) 4350 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4351 4352 return 0; 4353 } 4354 4355 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4356 { 4357 struct amdgpu_device *adev = ring->adev; 4358 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4359 4360 gfx_v11_0_kiq_setting(ring); 4361 4362 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4363 /* reset MQD to a clean status */ 4364 if (adev->gfx.kiq[0].mqd_backup) 4365 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4366 4367 /* reset ring buffer */ 4368 ring->wptr = 0; 4369 amdgpu_ring_clear_ring(ring); 4370 4371 mutex_lock(&adev->srbm_mutex); 4372 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4373 gfx_v11_0_kiq_init_register(ring); 4374 soc21_grbm_select(adev, 0, 0, 0, 0); 4375 mutex_unlock(&adev->srbm_mutex); 4376 } else { 4377 memset((void *)mqd, 0, sizeof(*mqd)); 4378 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4379 amdgpu_ring_clear_ring(ring); 4380 mutex_lock(&adev->srbm_mutex); 4381 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4382 amdgpu_ring_init_mqd(ring); 4383 gfx_v11_0_kiq_init_register(ring); 4384 soc21_grbm_select(adev, 0, 0, 0, 0); 4385 mutex_unlock(&adev->srbm_mutex); 4386 4387 if (adev->gfx.kiq[0].mqd_backup) 4388 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4389 } 4390 4391 return 0; 4392 } 4393 4394 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 4395 { 4396 struct amdgpu_device *adev = ring->adev; 4397 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4398 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4399 4400 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 4401 memset((void *)mqd, 0, sizeof(*mqd)); 4402 mutex_lock(&adev->srbm_mutex); 4403 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4404 amdgpu_ring_init_mqd(ring); 4405 soc21_grbm_select(adev, 0, 0, 0, 0); 4406 mutex_unlock(&adev->srbm_mutex); 4407 4408 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4409 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4410 } else { 4411 /* restore MQD to a clean status */ 4412 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4413 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4414 /* reset ring buffer */ 4415 ring->wptr = 0; 4416 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4417 amdgpu_ring_clear_ring(ring); 4418 } 4419 4420 return 0; 4421 } 4422 4423 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4424 { 4425 struct amdgpu_ring *ring; 4426 int r; 4427 4428 ring = &adev->gfx.kiq[0].ring; 4429 4430 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4431 if (unlikely(r != 0)) 4432 return r; 4433 4434 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4435 if (unlikely(r != 0)) { 4436 amdgpu_bo_unreserve(ring->mqd_obj); 4437 return r; 4438 } 4439 4440 gfx_v11_0_kiq_init_queue(ring); 4441 amdgpu_bo_kunmap(ring->mqd_obj); 4442 ring->mqd_ptr = NULL; 4443 amdgpu_bo_unreserve(ring->mqd_obj); 4444 ring->sched.ready = true; 4445 return 0; 4446 } 4447 4448 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4449 { 4450 struct amdgpu_ring *ring = NULL; 4451 int r = 0, i; 4452 4453 if (!amdgpu_async_gfx_ring) 4454 gfx_v11_0_cp_compute_enable(adev, true); 4455 4456 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4457 ring = &adev->gfx.compute_ring[i]; 4458 4459 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4460 if (unlikely(r != 0)) 4461 goto done; 4462 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4463 if (!r) { 4464 r = gfx_v11_0_kcq_init_queue(ring, false); 4465 amdgpu_bo_kunmap(ring->mqd_obj); 4466 ring->mqd_ptr = NULL; 4467 } 4468 amdgpu_bo_unreserve(ring->mqd_obj); 4469 if (r) 4470 goto done; 4471 } 4472 4473 r = amdgpu_gfx_enable_kcq(adev, 0); 4474 done: 4475 return r; 4476 } 4477 4478 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4479 { 4480 int r, i; 4481 struct amdgpu_ring *ring; 4482 4483 if (!(adev->flags & AMD_IS_APU)) 4484 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4485 4486 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4487 /* legacy firmware loading */ 4488 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4489 if (r) 4490 return r; 4491 4492 if (adev->gfx.rs64_enable) 4493 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4494 else 4495 r = gfx_v11_0_cp_compute_load_microcode(adev); 4496 if (r) 4497 return r; 4498 } 4499 4500 gfx_v11_0_cp_set_doorbell_range(adev); 4501 4502 if (amdgpu_async_gfx_ring) { 4503 gfx_v11_0_cp_compute_enable(adev, true); 4504 gfx_v11_0_cp_gfx_enable(adev, true); 4505 } 4506 4507 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4508 r = amdgpu_mes_kiq_hw_init(adev); 4509 else 4510 r = gfx_v11_0_kiq_resume(adev); 4511 if (r) 4512 return r; 4513 4514 r = gfx_v11_0_kcq_resume(adev); 4515 if (r) 4516 return r; 4517 4518 if (!amdgpu_async_gfx_ring) { 4519 r = gfx_v11_0_cp_gfx_resume(adev); 4520 if (r) 4521 return r; 4522 } else { 4523 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4524 if (r) 4525 return r; 4526 } 4527 4528 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4529 ring = &adev->gfx.gfx_ring[i]; 4530 r = amdgpu_ring_test_helper(ring); 4531 if (r) 4532 return r; 4533 } 4534 4535 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4536 ring = &adev->gfx.compute_ring[i]; 4537 r = amdgpu_ring_test_helper(ring); 4538 if (r) 4539 return r; 4540 } 4541 4542 return 0; 4543 } 4544 4545 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4546 { 4547 gfx_v11_0_cp_gfx_enable(adev, enable); 4548 gfx_v11_0_cp_compute_enable(adev, enable); 4549 } 4550 4551 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4552 { 4553 int r; 4554 bool value; 4555 4556 r = adev->gfxhub.funcs->gart_enable(adev); 4557 if (r) 4558 return r; 4559 4560 adev->hdp.funcs->flush_hdp(adev, NULL); 4561 4562 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4563 false : true; 4564 4565 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4566 /* TODO investigate why this and the hdp flush above is needed, 4567 * are we missing a flush somewhere else? */ 4568 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4569 4570 return 0; 4571 } 4572 4573 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4574 { 4575 u32 tmp; 4576 4577 /* select RS64 */ 4578 if (adev->gfx.rs64_enable) { 4579 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4580 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4581 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4582 4583 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4584 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4585 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4586 } 4587 4588 if (amdgpu_emu_mode == 1) 4589 msleep(100); 4590 } 4591 4592 static int get_gb_addr_config(struct amdgpu_device * adev) 4593 { 4594 u32 gb_addr_config; 4595 4596 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4597 if (gb_addr_config == 0) 4598 return -EINVAL; 4599 4600 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4601 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4602 4603 adev->gfx.config.gb_addr_config = gb_addr_config; 4604 4605 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4606 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4607 GB_ADDR_CONFIG, NUM_PIPES); 4608 4609 adev->gfx.config.max_tile_pipes = 4610 adev->gfx.config.gb_addr_config_fields.num_pipes; 4611 4612 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4613 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4614 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4615 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4616 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4617 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4618 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4619 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4620 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4621 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4622 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4623 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4624 4625 return 0; 4626 } 4627 4628 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4629 { 4630 uint32_t data; 4631 4632 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4633 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4634 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4635 4636 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4637 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4638 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4639 } 4640 4641 static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 4642 { 4643 int r; 4644 struct amdgpu_device *adev = ip_block->adev; 4645 4646 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 4647 adev->gfx.cleaner_shader_ptr); 4648 4649 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4650 if (adev->gfx.imu.funcs) { 4651 /* RLC autoload sequence 1: Program rlc ram */ 4652 if (adev->gfx.imu.funcs->program_rlc_ram) 4653 adev->gfx.imu.funcs->program_rlc_ram(adev); 4654 /* rlc autoload firmware */ 4655 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4656 if (r) 4657 return r; 4658 } 4659 } else { 4660 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4661 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4662 if (adev->gfx.imu.funcs->load_microcode) 4663 adev->gfx.imu.funcs->load_microcode(adev); 4664 if (adev->gfx.imu.funcs->setup_imu) 4665 adev->gfx.imu.funcs->setup_imu(adev); 4666 if (adev->gfx.imu.funcs->start_imu) 4667 adev->gfx.imu.funcs->start_imu(adev); 4668 } 4669 4670 /* disable gpa mode in backdoor loading */ 4671 gfx_v11_0_disable_gpa_mode(adev); 4672 } 4673 } 4674 4675 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4676 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4677 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4678 if (r) { 4679 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4680 return r; 4681 } 4682 } 4683 4684 adev->gfx.is_poweron = true; 4685 4686 if(get_gb_addr_config(adev)) 4687 DRM_WARN("Invalid gb_addr_config !\n"); 4688 4689 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4690 adev->gfx.rs64_enable) 4691 gfx_v11_0_config_gfx_rs64(adev); 4692 4693 r = gfx_v11_0_gfxhub_enable(adev); 4694 if (r) 4695 return r; 4696 4697 if (!amdgpu_emu_mode) 4698 gfx_v11_0_init_golden_registers(adev); 4699 4700 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4701 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4702 /** 4703 * For gfx 11, rlc firmware loading relies on smu firmware is 4704 * loaded firstly, so in direct type, it has to load smc ucode 4705 * here before rlc. 4706 */ 4707 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4708 if (r) 4709 return r; 4710 } 4711 4712 gfx_v11_0_constants_init(adev); 4713 4714 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4715 gfx_v11_0_select_cp_fw_arch(adev); 4716 4717 if (adev->nbio.funcs->gc_doorbell_init) 4718 adev->nbio.funcs->gc_doorbell_init(adev); 4719 4720 r = gfx_v11_0_rlc_resume(adev); 4721 if (r) 4722 return r; 4723 4724 /* 4725 * init golden registers and rlc resume may override some registers, 4726 * reconfig them here 4727 */ 4728 gfx_v11_0_tcp_harvest(adev); 4729 4730 r = gfx_v11_0_cp_resume(adev); 4731 if (r) 4732 return r; 4733 4734 /* get IMU version from HW if it's not set */ 4735 if (!adev->gfx.imu_fw_version) 4736 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4737 4738 return r; 4739 } 4740 4741 static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 4742 { 4743 struct amdgpu_device *adev = ip_block->adev; 4744 4745 cancel_delayed_work_sync(&adev->gfx.idle_work); 4746 4747 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4748 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4749 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 4750 4751 if (!adev->no_hw_access) { 4752 if (amdgpu_async_gfx_ring) { 4753 if (amdgpu_gfx_disable_kgq(adev, 0)) 4754 DRM_ERROR("KGQ disable failed\n"); 4755 } 4756 4757 if (amdgpu_gfx_disable_kcq(adev, 0)) 4758 DRM_ERROR("KCQ disable failed\n"); 4759 4760 amdgpu_mes_kiq_hw_fini(adev); 4761 } 4762 4763 if (amdgpu_sriov_vf(adev)) 4764 /* Remove the steps disabling CPG and clearing KIQ position, 4765 * so that CP could perform IDLE-SAVE during switch. Those 4766 * steps are necessary to avoid a DMAR error in gfx9 but it is 4767 * not reproduced on gfx11. 4768 */ 4769 return 0; 4770 4771 gfx_v11_0_cp_enable(adev, false); 4772 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4773 4774 adev->gfxhub.funcs->gart_disable(adev); 4775 4776 adev->gfx.is_poweron = false; 4777 4778 return 0; 4779 } 4780 4781 static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) 4782 { 4783 return gfx_v11_0_hw_fini(ip_block); 4784 } 4785 4786 static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) 4787 { 4788 return gfx_v11_0_hw_init(ip_block); 4789 } 4790 4791 static bool gfx_v11_0_is_idle(void *handle) 4792 { 4793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4794 4795 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4796 GRBM_STATUS, GUI_ACTIVE)) 4797 return false; 4798 else 4799 return true; 4800 } 4801 4802 static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 4803 { 4804 unsigned i; 4805 u32 tmp; 4806 struct amdgpu_device *adev = ip_block->adev; 4807 4808 for (i = 0; i < adev->usec_timeout; i++) { 4809 /* read MC_STATUS */ 4810 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4811 GRBM_STATUS__GUI_ACTIVE_MASK; 4812 4813 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4814 return 0; 4815 udelay(1); 4816 } 4817 return -ETIMEDOUT; 4818 } 4819 4820 int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4821 bool req) 4822 { 4823 u32 i, tmp, val; 4824 4825 for (i = 0; i < adev->usec_timeout; i++) { 4826 /* Request with MeId=2, PipeId=0 */ 4827 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4828 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4829 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4830 4831 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4832 if (req) { 4833 if (val == tmp) 4834 break; 4835 } else { 4836 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4837 REQUEST, 1); 4838 4839 /* unlocked or locked by firmware */ 4840 if (val != tmp) 4841 break; 4842 } 4843 udelay(1); 4844 } 4845 4846 if (i >= adev->usec_timeout) 4847 return -EINVAL; 4848 4849 return 0; 4850 } 4851 4852 static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) 4853 { 4854 u32 grbm_soft_reset = 0; 4855 u32 tmp; 4856 int r, i, j, k; 4857 struct amdgpu_device *adev = ip_block->adev; 4858 4859 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4860 4861 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4862 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4863 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4864 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4865 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4866 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4867 4868 mutex_lock(&adev->srbm_mutex); 4869 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4870 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4871 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4872 soc21_grbm_select(adev, i, k, j, 0); 4873 4874 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4875 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4876 } 4877 } 4878 } 4879 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4880 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4881 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4882 soc21_grbm_select(adev, i, k, j, 0); 4883 4884 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4885 } 4886 } 4887 } 4888 soc21_grbm_select(adev, 0, 0, 0, 0); 4889 mutex_unlock(&adev->srbm_mutex); 4890 4891 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4892 mutex_lock(&adev->gfx.reset_sem_mutex); 4893 r = gfx_v11_0_request_gfx_index_mutex(adev, true); 4894 if (r) { 4895 mutex_unlock(&adev->gfx.reset_sem_mutex); 4896 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 4897 return r; 4898 } 4899 4900 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4901 4902 // Read CP_VMID_RESET register three times. 4903 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4904 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4905 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4906 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4907 4908 /* release the gfx mutex */ 4909 r = gfx_v11_0_request_gfx_index_mutex(adev, false); 4910 mutex_unlock(&adev->gfx.reset_sem_mutex); 4911 if (r) { 4912 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 4913 return r; 4914 } 4915 4916 for (i = 0; i < adev->usec_timeout; i++) { 4917 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4918 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4919 break; 4920 udelay(1); 4921 } 4922 if (i >= adev->usec_timeout) { 4923 printk("Failed to wait all pipes clean\n"); 4924 return -EINVAL; 4925 } 4926 4927 /********** trigger soft reset ***********/ 4928 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4929 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4930 SOFT_RESET_CP, 1); 4931 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4932 SOFT_RESET_GFX, 1); 4933 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4934 SOFT_RESET_CPF, 1); 4935 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4936 SOFT_RESET_CPC, 1); 4937 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4938 SOFT_RESET_CPG, 1); 4939 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4940 /********** exit soft reset ***********/ 4941 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4942 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4943 SOFT_RESET_CP, 0); 4944 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4945 SOFT_RESET_GFX, 0); 4946 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4947 SOFT_RESET_CPF, 0); 4948 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4949 SOFT_RESET_CPC, 0); 4950 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4951 SOFT_RESET_CPG, 0); 4952 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4953 4954 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4955 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4956 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4957 4958 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4959 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4960 4961 for (i = 0; i < adev->usec_timeout; i++) { 4962 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4963 break; 4964 udelay(1); 4965 } 4966 if (i >= adev->usec_timeout) { 4967 printk("Failed to wait CP_VMID_RESET to 0\n"); 4968 return -EINVAL; 4969 } 4970 4971 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4972 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4973 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4974 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4975 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4976 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4977 4978 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4979 4980 return gfx_v11_0_cp_resume(adev); 4981 } 4982 4983 static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 4984 { 4985 int i, r; 4986 struct amdgpu_device *adev = ip_block->adev; 4987 struct amdgpu_ring *ring; 4988 long tmo = msecs_to_jiffies(1000); 4989 4990 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4991 ring = &adev->gfx.gfx_ring[i]; 4992 r = amdgpu_ring_test_ib(ring, tmo); 4993 if (r) 4994 return true; 4995 } 4996 4997 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4998 ring = &adev->gfx.compute_ring[i]; 4999 r = amdgpu_ring_test_ib(ring, tmo); 5000 if (r) 5001 return true; 5002 } 5003 5004 return false; 5005 } 5006 5007 static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 5008 { 5009 struct amdgpu_device *adev = ip_block->adev; 5010 /** 5011 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 5012 */ 5013 return amdgpu_mes_resume(adev); 5014 } 5015 5016 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5017 { 5018 uint64_t clock; 5019 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 5020 5021 if (amdgpu_sriov_vf(adev)) { 5022 amdgpu_gfx_off_ctrl(adev, false); 5023 mutex_lock(&adev->gfx.gpu_clock_mutex); 5024 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5025 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5026 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 5027 if (clock_counter_hi_pre != clock_counter_hi_after) 5028 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 5029 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5030 amdgpu_gfx_off_ctrl(adev, true); 5031 } else { 5032 preempt_disable(); 5033 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5034 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5035 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 5036 if (clock_counter_hi_pre != clock_counter_hi_after) 5037 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 5038 preempt_enable(); 5039 } 5040 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 5041 5042 return clock; 5043 } 5044 5045 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5046 uint32_t vmid, 5047 uint32_t gds_base, uint32_t gds_size, 5048 uint32_t gws_base, uint32_t gws_size, 5049 uint32_t oa_base, uint32_t oa_size) 5050 { 5051 struct amdgpu_device *adev = ring->adev; 5052 5053 /* GDS Base */ 5054 gfx_v11_0_write_data_to_reg(ring, 0, false, 5055 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 5056 gds_base); 5057 5058 /* GDS Size */ 5059 gfx_v11_0_write_data_to_reg(ring, 0, false, 5060 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 5061 gds_size); 5062 5063 /* GWS */ 5064 gfx_v11_0_write_data_to_reg(ring, 0, false, 5065 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 5066 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5067 5068 /* OA */ 5069 gfx_v11_0_write_data_to_reg(ring, 0, false, 5070 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 5071 (1 << (oa_size + oa_base)) - (1 << oa_base)); 5072 } 5073 5074 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) 5075 { 5076 struct amdgpu_device *adev = ip_block->adev; 5077 5078 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 5079 5080 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 5081 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 5082 AMDGPU_MAX_COMPUTE_RINGS); 5083 5084 gfx_v11_0_set_kiq_pm4_funcs(adev); 5085 gfx_v11_0_set_ring_funcs(adev); 5086 gfx_v11_0_set_irq_funcs(adev); 5087 gfx_v11_0_set_gds_init(adev); 5088 gfx_v11_0_set_rlc_funcs(adev); 5089 gfx_v11_0_set_mqd_funcs(adev); 5090 gfx_v11_0_set_imu_funcs(adev); 5091 5092 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 5093 5094 return gfx_v11_0_init_microcode(adev); 5095 } 5096 5097 static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) 5098 { 5099 struct amdgpu_device *adev = ip_block->adev; 5100 int r; 5101 5102 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5103 if (r) 5104 return r; 5105 5106 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5107 if (r) 5108 return r; 5109 5110 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 5111 if (r) 5112 return r; 5113 return 0; 5114 } 5115 5116 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 5117 { 5118 uint32_t rlc_cntl; 5119 5120 /* if RLC is not enabled, do nothing */ 5121 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 5122 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 5123 } 5124 5125 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 5126 { 5127 uint32_t data; 5128 unsigned i; 5129 5130 data = RLC_SAFE_MODE__CMD_MASK; 5131 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5132 5133 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 5134 5135 /* wait for RLC_SAFE_MODE */ 5136 for (i = 0; i < adev->usec_timeout; i++) { 5137 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 5138 RLC_SAFE_MODE, CMD)) 5139 break; 5140 udelay(1); 5141 } 5142 } 5143 5144 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 5145 { 5146 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5147 } 5148 5149 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5150 bool enable) 5151 { 5152 uint32_t def, data; 5153 5154 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5155 return; 5156 5157 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5158 5159 if (enable) 5160 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5161 else 5162 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5163 5164 if (def != data) 5165 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5166 } 5167 5168 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5169 bool enable) 5170 { 5171 uint32_t def, data; 5172 5173 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5174 return; 5175 5176 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5177 5178 if (enable) 5179 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5180 else 5181 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5182 5183 if (def != data) 5184 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5185 } 5186 5187 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5188 bool enable) 5189 { 5190 uint32_t def, data; 5191 5192 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5193 return; 5194 5195 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5196 5197 if (enable) 5198 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5199 else 5200 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5201 5202 if (def != data) 5203 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5204 } 5205 5206 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5207 bool enable) 5208 { 5209 uint32_t data, def; 5210 5211 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5212 return; 5213 5214 /* It is disabled by HW by default */ 5215 if (enable) { 5216 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5217 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5218 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5219 5220 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5221 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5222 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5223 5224 if (def != data) 5225 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5226 } 5227 } else { 5228 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5229 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5230 5231 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5232 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5233 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5234 5235 if (def != data) 5236 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5237 } 5238 } 5239 } 5240 5241 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5242 bool enable) 5243 { 5244 uint32_t def, data; 5245 5246 if (!(adev->cg_flags & 5247 (AMD_CG_SUPPORT_GFX_CGCG | 5248 AMD_CG_SUPPORT_GFX_CGLS | 5249 AMD_CG_SUPPORT_GFX_3D_CGCG | 5250 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5251 return; 5252 5253 if (enable) { 5254 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5255 5256 /* unset CGCG override */ 5257 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5258 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5259 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5260 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5261 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5262 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5263 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5264 5265 /* update CGCG override bits */ 5266 if (def != data) 5267 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5268 5269 /* enable cgcg FSM(0x0000363F) */ 5270 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5271 5272 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5273 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5274 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5275 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5276 } 5277 5278 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5279 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5280 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5281 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5282 } 5283 5284 if (def != data) 5285 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5286 5287 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5288 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5289 5290 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5291 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5292 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5293 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5294 } 5295 5296 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5297 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5298 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5299 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5300 } 5301 5302 if (def != data) 5303 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5304 5305 /* set IDLE_POLL_COUNT(0x00900100) */ 5306 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5307 5308 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5309 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5310 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5311 5312 if (def != data) 5313 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5314 5315 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5316 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5317 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5318 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5319 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5320 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5321 5322 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5323 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5324 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5325 5326 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5327 if (adev->sdma.num_instances > 1) { 5328 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5329 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5330 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5331 } 5332 } else { 5333 /* Program RLC_CGCG_CGLS_CTRL */ 5334 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5335 5336 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5337 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5338 5339 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5340 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5341 5342 if (def != data) 5343 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5344 5345 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5346 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5347 5348 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5349 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5350 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5351 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5352 5353 if (def != data) 5354 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5355 5356 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5357 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5358 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5359 5360 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5361 if (adev->sdma.num_instances > 1) { 5362 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5363 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5364 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5365 } 5366 } 5367 } 5368 5369 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5370 bool enable) 5371 { 5372 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5373 5374 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5375 5376 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5377 5378 gfx_v11_0_update_repeater_fgcg(adev, enable); 5379 5380 gfx_v11_0_update_sram_fgcg(adev, enable); 5381 5382 gfx_v11_0_update_perf_clk(adev, enable); 5383 5384 if (adev->cg_flags & 5385 (AMD_CG_SUPPORT_GFX_MGCG | 5386 AMD_CG_SUPPORT_GFX_CGLS | 5387 AMD_CG_SUPPORT_GFX_CGCG | 5388 AMD_CG_SUPPORT_GFX_3D_CGCG | 5389 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5390 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5391 5392 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5393 5394 return 0; 5395 } 5396 5397 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5398 { 5399 u32 reg, pre_data, data; 5400 5401 amdgpu_gfx_off_ctrl(adev, false); 5402 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5403 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 5404 pre_data = RREG32_NO_KIQ(reg); 5405 else 5406 pre_data = RREG32(reg); 5407 5408 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 5409 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5410 5411 if (pre_data != data) { 5412 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 5413 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5414 } else 5415 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5416 } 5417 amdgpu_gfx_off_ctrl(adev, true); 5418 5419 if (ring 5420 && amdgpu_sriov_is_pp_one_vf(adev) 5421 && (pre_data != data) 5422 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5423 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5424 amdgpu_ring_emit_wreg(ring, reg, data); 5425 } 5426 } 5427 5428 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5429 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5430 .set_safe_mode = gfx_v11_0_set_safe_mode, 5431 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5432 .init = gfx_v11_0_rlc_init, 5433 .get_csb_size = gfx_v11_0_get_csb_size, 5434 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5435 .resume = gfx_v11_0_rlc_resume, 5436 .stop = gfx_v11_0_rlc_stop, 5437 .reset = gfx_v11_0_rlc_reset, 5438 .start = gfx_v11_0_rlc_start, 5439 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5440 }; 5441 5442 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5443 { 5444 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5445 5446 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5447 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5448 else 5449 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5450 5451 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5452 5453 // Program RLC_PG_DELAY3 for CGPG hysteresis 5454 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5455 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5456 case IP_VERSION(11, 0, 1): 5457 case IP_VERSION(11, 0, 4): 5458 case IP_VERSION(11, 5, 0): 5459 case IP_VERSION(11, 5, 1): 5460 case IP_VERSION(11, 5, 2): 5461 case IP_VERSION(11, 5, 3): 5462 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5463 break; 5464 default: 5465 break; 5466 } 5467 } 5468 } 5469 5470 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5471 { 5472 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5473 5474 gfx_v11_cntl_power_gating(adev, enable); 5475 5476 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5477 } 5478 5479 static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 5480 enum amd_powergating_state state) 5481 { 5482 struct amdgpu_device *adev = ip_block->adev; 5483 bool enable = (state == AMD_PG_STATE_GATE); 5484 5485 if (amdgpu_sriov_vf(adev)) 5486 return 0; 5487 5488 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5489 case IP_VERSION(11, 0, 0): 5490 case IP_VERSION(11, 0, 2): 5491 case IP_VERSION(11, 0, 3): 5492 amdgpu_gfx_off_ctrl(adev, enable); 5493 break; 5494 case IP_VERSION(11, 0, 1): 5495 case IP_VERSION(11, 0, 4): 5496 case IP_VERSION(11, 5, 0): 5497 case IP_VERSION(11, 5, 1): 5498 case IP_VERSION(11, 5, 2): 5499 case IP_VERSION(11, 5, 3): 5500 if (!enable) 5501 amdgpu_gfx_off_ctrl(adev, false); 5502 5503 gfx_v11_cntl_pg(adev, enable); 5504 5505 if (enable) 5506 amdgpu_gfx_off_ctrl(adev, true); 5507 5508 break; 5509 default: 5510 break; 5511 } 5512 5513 return 0; 5514 } 5515 5516 static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5517 enum amd_clockgating_state state) 5518 { 5519 struct amdgpu_device *adev = ip_block->adev; 5520 5521 if (amdgpu_sriov_vf(adev)) 5522 return 0; 5523 5524 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5525 case IP_VERSION(11, 0, 0): 5526 case IP_VERSION(11, 0, 1): 5527 case IP_VERSION(11, 0, 2): 5528 case IP_VERSION(11, 0, 3): 5529 case IP_VERSION(11, 0, 4): 5530 case IP_VERSION(11, 5, 0): 5531 case IP_VERSION(11, 5, 1): 5532 case IP_VERSION(11, 5, 2): 5533 case IP_VERSION(11, 5, 3): 5534 gfx_v11_0_update_gfx_clock_gating(adev, 5535 state == AMD_CG_STATE_GATE); 5536 break; 5537 default: 5538 break; 5539 } 5540 5541 return 0; 5542 } 5543 5544 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5545 { 5546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5547 int data; 5548 5549 /* AMD_CG_SUPPORT_GFX_MGCG */ 5550 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5551 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5552 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5553 5554 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5555 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5556 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5557 5558 /* AMD_CG_SUPPORT_GFX_FGCG */ 5559 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5560 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5561 5562 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5563 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5564 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5565 5566 /* AMD_CG_SUPPORT_GFX_CGCG */ 5567 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5568 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5569 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5570 5571 /* AMD_CG_SUPPORT_GFX_CGLS */ 5572 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5573 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5574 5575 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5576 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5577 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5578 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5579 5580 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5581 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5582 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5583 } 5584 5585 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5586 { 5587 /* gfx11 is 32bit rptr*/ 5588 return *(uint32_t *)ring->rptr_cpu_addr; 5589 } 5590 5591 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5592 { 5593 struct amdgpu_device *adev = ring->adev; 5594 u64 wptr; 5595 5596 /* XXX check if swapping is necessary on BE */ 5597 if (ring->use_doorbell) { 5598 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5599 } else { 5600 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5601 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5602 } 5603 5604 return wptr; 5605 } 5606 5607 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5608 { 5609 struct amdgpu_device *adev = ring->adev; 5610 5611 if (ring->use_doorbell) { 5612 /* XXX check if swapping is necessary on BE */ 5613 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5614 ring->wptr); 5615 WDOORBELL64(ring->doorbell_index, ring->wptr); 5616 } else { 5617 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5618 lower_32_bits(ring->wptr)); 5619 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5620 upper_32_bits(ring->wptr)); 5621 } 5622 } 5623 5624 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5625 { 5626 /* gfx11 hardware is 32bit rptr */ 5627 return *(uint32_t *)ring->rptr_cpu_addr; 5628 } 5629 5630 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5631 { 5632 u64 wptr; 5633 5634 /* XXX check if swapping is necessary on BE */ 5635 if (ring->use_doorbell) 5636 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5637 else 5638 BUG(); 5639 return wptr; 5640 } 5641 5642 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5643 { 5644 struct amdgpu_device *adev = ring->adev; 5645 5646 /* XXX check if swapping is necessary on BE */ 5647 if (ring->use_doorbell) { 5648 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5649 ring->wptr); 5650 WDOORBELL64(ring->doorbell_index, ring->wptr); 5651 } else { 5652 BUG(); /* only DOORBELL method supported on gfx11 now */ 5653 } 5654 } 5655 5656 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5657 { 5658 struct amdgpu_device *adev = ring->adev; 5659 u32 ref_and_mask, reg_mem_engine; 5660 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5661 5662 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5663 switch (ring->me) { 5664 case 1: 5665 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5666 break; 5667 case 2: 5668 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5669 break; 5670 default: 5671 return; 5672 } 5673 reg_mem_engine = 0; 5674 } else { 5675 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 5676 reg_mem_engine = 1; /* pfp */ 5677 } 5678 5679 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5680 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5681 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5682 ref_and_mask, ref_and_mask, 0x20); 5683 } 5684 5685 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5686 struct amdgpu_job *job, 5687 struct amdgpu_ib *ib, 5688 uint32_t flags) 5689 { 5690 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5691 u32 header, control = 0; 5692 5693 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5694 5695 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5696 5697 control |= ib->length_dw | (vmid << 24); 5698 5699 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5700 control |= INDIRECT_BUFFER_PRE_ENB(1); 5701 5702 if (flags & AMDGPU_IB_PREEMPTED) 5703 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5704 5705 if (vmid) 5706 gfx_v11_0_ring_emit_de_meta(ring, 5707 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5708 } 5709 5710 if (ring->is_mes_queue) 5711 /* inherit vmid from mqd */ 5712 control |= 0x400000; 5713 5714 amdgpu_ring_write(ring, header); 5715 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5716 amdgpu_ring_write(ring, 5717 #ifdef __BIG_ENDIAN 5718 (2 << 0) | 5719 #endif 5720 lower_32_bits(ib->gpu_addr)); 5721 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5722 amdgpu_ring_write(ring, control); 5723 } 5724 5725 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5726 struct amdgpu_job *job, 5727 struct amdgpu_ib *ib, 5728 uint32_t flags) 5729 { 5730 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5731 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5732 5733 if (ring->is_mes_queue) 5734 /* inherit vmid from mqd */ 5735 control |= 0x40000000; 5736 5737 /* Currently, there is a high possibility to get wave ID mismatch 5738 * between ME and GDS, leading to a hw deadlock, because ME generates 5739 * different wave IDs than the GDS expects. This situation happens 5740 * randomly when at least 5 compute pipes use GDS ordered append. 5741 * The wave IDs generated by ME are also wrong after suspend/resume. 5742 * Those are probably bugs somewhere else in the kernel driver. 5743 * 5744 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5745 * GDS to 0 for this ring (me/pipe). 5746 */ 5747 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5748 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5749 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5750 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5751 } 5752 5753 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5754 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5755 amdgpu_ring_write(ring, 5756 #ifdef __BIG_ENDIAN 5757 (2 << 0) | 5758 #endif 5759 lower_32_bits(ib->gpu_addr)); 5760 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5761 amdgpu_ring_write(ring, control); 5762 } 5763 5764 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5765 u64 seq, unsigned flags) 5766 { 5767 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5768 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5769 5770 /* RELEASE_MEM - flush caches, send int */ 5771 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5772 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5773 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5774 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 5775 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5776 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5777 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5778 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5779 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5780 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5781 5782 /* 5783 * the address should be Qword aligned if 64bit write, Dword 5784 * aligned if only send 32bit data low (discard data high) 5785 */ 5786 if (write64bit) 5787 BUG_ON(addr & 0x7); 5788 else 5789 BUG_ON(addr & 0x3); 5790 amdgpu_ring_write(ring, lower_32_bits(addr)); 5791 amdgpu_ring_write(ring, upper_32_bits(addr)); 5792 amdgpu_ring_write(ring, lower_32_bits(seq)); 5793 amdgpu_ring_write(ring, upper_32_bits(seq)); 5794 amdgpu_ring_write(ring, ring->is_mes_queue ? 5795 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5796 } 5797 5798 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5799 { 5800 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5801 uint32_t seq = ring->fence_drv.sync_seq; 5802 uint64_t addr = ring->fence_drv.gpu_addr; 5803 5804 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5805 upper_32_bits(addr), seq, 0xffffffff, 4); 5806 } 5807 5808 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5809 uint16_t pasid, uint32_t flush_type, 5810 bool all_hub, uint8_t dst_sel) 5811 { 5812 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5813 amdgpu_ring_write(ring, 5814 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5815 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5816 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5817 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5818 } 5819 5820 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5821 unsigned vmid, uint64_t pd_addr) 5822 { 5823 if (ring->is_mes_queue) 5824 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5825 else 5826 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5827 5828 /* compute doesn't have PFP */ 5829 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5830 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5831 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5832 amdgpu_ring_write(ring, 0x0); 5833 } 5834 5835 /* Make sure that we can't skip the SET_Q_MODE packets when the VM 5836 * changed in any way. 5837 */ 5838 ring->set_q_mode_offs = 0; 5839 ring->set_q_mode_ptr = NULL; 5840 } 5841 5842 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5843 u64 seq, unsigned int flags) 5844 { 5845 struct amdgpu_device *adev = ring->adev; 5846 5847 /* we only allocate 32bit for each seq wb address */ 5848 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5849 5850 /* write fence seq to the "addr" */ 5851 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5852 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5853 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5854 amdgpu_ring_write(ring, lower_32_bits(addr)); 5855 amdgpu_ring_write(ring, upper_32_bits(addr)); 5856 amdgpu_ring_write(ring, lower_32_bits(seq)); 5857 5858 if (flags & AMDGPU_FENCE_FLAG_INT) { 5859 /* set register to trigger INT */ 5860 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5861 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5862 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5863 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5864 amdgpu_ring_write(ring, 0); 5865 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5866 } 5867 } 5868 5869 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5870 uint32_t flags) 5871 { 5872 uint32_t dw2 = 0; 5873 5874 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5875 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5876 /* set load_global_config & load_global_uconfig */ 5877 dw2 |= 0x8001; 5878 /* set load_cs_sh_regs */ 5879 dw2 |= 0x01000000; 5880 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5881 dw2 |= 0x10002; 5882 } 5883 5884 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5885 amdgpu_ring_write(ring, dw2); 5886 amdgpu_ring_write(ring, 0); 5887 } 5888 5889 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 5890 uint64_t addr) 5891 { 5892 unsigned ret; 5893 5894 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5895 amdgpu_ring_write(ring, lower_32_bits(addr)); 5896 amdgpu_ring_write(ring, upper_32_bits(addr)); 5897 /* discard following DWs if *cond_exec_gpu_addr==0 */ 5898 amdgpu_ring_write(ring, 0); 5899 ret = ring->wptr & ring->buf_mask; 5900 /* patch dummy value later */ 5901 amdgpu_ring_write(ring, 0); 5902 5903 return ret; 5904 } 5905 5906 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5907 u64 shadow_va, u64 csa_va, 5908 u64 gds_va, bool init_shadow, 5909 int vmid) 5910 { 5911 struct amdgpu_device *adev = ring->adev; 5912 unsigned int offs, end; 5913 5914 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) 5915 return; 5916 5917 /* 5918 * The logic here isn't easy to understand because we need to keep state 5919 * accross multiple executions of the function as well as between the 5920 * CPU and GPU. The general idea is that the newly written GPU command 5921 * has a condition on the previous one and only executed if really 5922 * necessary. 5923 */ 5924 5925 /* 5926 * The dw in the NOP controls if the next SET_Q_MODE packet should be 5927 * executed or not. Reserve 64bits just to be on the save side. 5928 */ 5929 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); 5930 offs = ring->wptr & ring->buf_mask; 5931 5932 /* 5933 * We start with skipping the prefix SET_Q_MODE and always executing 5934 * the postfix SET_Q_MODE packet. This is changed below with a 5935 * WRITE_DATA command when the postfix executed. 5936 */ 5937 amdgpu_ring_write(ring, shadow_va ? 1 : 0); 5938 amdgpu_ring_write(ring, 0); 5939 5940 if (ring->set_q_mode_offs) { 5941 uint64_t addr; 5942 5943 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5944 addr += ring->set_q_mode_offs << 2; 5945 end = gfx_v11_0_ring_emit_init_cond_exec(ring, addr); 5946 } 5947 5948 /* 5949 * When the postfix SET_Q_MODE packet executes we need to make sure that the 5950 * next prefix SET_Q_MODE packet executes as well. 5951 */ 5952 if (!shadow_va) { 5953 uint64_t addr; 5954 5955 addr = amdgpu_bo_gpu_offset(ring->ring_obj); 5956 addr += offs << 2; 5957 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5958 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 5959 amdgpu_ring_write(ring, lower_32_bits(addr)); 5960 amdgpu_ring_write(ring, upper_32_bits(addr)); 5961 amdgpu_ring_write(ring, 0x1); 5962 } 5963 5964 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5965 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5966 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5967 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5968 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5969 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5970 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5971 amdgpu_ring_write(ring, shadow_va ? 5972 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5973 amdgpu_ring_write(ring, init_shadow ? 5974 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5975 5976 if (ring->set_q_mode_offs) 5977 amdgpu_ring_patch_cond_exec(ring, end); 5978 5979 if (shadow_va) { 5980 uint64_t token = shadow_va ^ csa_va ^ gds_va ^ vmid; 5981 5982 /* 5983 * If the tokens match try to skip the last postfix SET_Q_MODE 5984 * packet to avoid saving/restoring the state all the time. 5985 */ 5986 if (ring->set_q_mode_ptr && ring->set_q_mode_token == token) 5987 *ring->set_q_mode_ptr = 0; 5988 5989 ring->set_q_mode_token = token; 5990 } else { 5991 ring->set_q_mode_ptr = &ring->ring[ring->set_q_mode_offs]; 5992 } 5993 5994 ring->set_q_mode_offs = offs; 5995 } 5996 5997 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5998 { 5999 int i, r = 0; 6000 struct amdgpu_device *adev = ring->adev; 6001 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 6002 struct amdgpu_ring *kiq_ring = &kiq->ring; 6003 unsigned long flags; 6004 6005 if (adev->enable_mes) 6006 return -EINVAL; 6007 6008 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 6009 return -EINVAL; 6010 6011 spin_lock_irqsave(&kiq->ring_lock, flags); 6012 6013 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 6014 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6015 return -ENOMEM; 6016 } 6017 6018 /* assert preemption condition */ 6019 amdgpu_ring_set_preempt_cond_exec(ring, false); 6020 6021 /* assert IB preemption, emit the trailing fence */ 6022 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 6023 ring->trail_fence_gpu_addr, 6024 ++ring->trail_seq); 6025 amdgpu_ring_commit(kiq_ring); 6026 6027 spin_unlock_irqrestore(&kiq->ring_lock, flags); 6028 6029 /* poll the trailing fence */ 6030 for (i = 0; i < adev->usec_timeout; i++) { 6031 if (ring->trail_seq == 6032 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 6033 break; 6034 udelay(1); 6035 } 6036 6037 if (i >= adev->usec_timeout) { 6038 r = -EINVAL; 6039 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 6040 } 6041 6042 /* deassert preemption condition */ 6043 amdgpu_ring_set_preempt_cond_exec(ring, true); 6044 return r; 6045 } 6046 6047 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 6048 { 6049 struct amdgpu_device *adev = ring->adev; 6050 struct v10_de_ib_state de_payload = {0}; 6051 uint64_t offset, gds_addr, de_payload_gpu_addr; 6052 void *de_payload_cpu_addr; 6053 int cnt; 6054 6055 if (ring->is_mes_queue) { 6056 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 6057 gfx[0].gfx_meta_data) + 6058 offsetof(struct v10_gfx_meta_data, de_payload); 6059 de_payload_gpu_addr = 6060 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 6061 de_payload_cpu_addr = 6062 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 6063 6064 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 6065 gfx[0].gds_backup) + 6066 offsetof(struct v10_gfx_meta_data, de_payload); 6067 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 6068 } else { 6069 offset = offsetof(struct v10_gfx_meta_data, de_payload); 6070 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 6071 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 6072 6073 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 6074 AMDGPU_CSA_SIZE - adev->gds.gds_size, 6075 PAGE_SIZE); 6076 } 6077 6078 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 6079 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 6080 6081 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 6082 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 6083 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 6084 WRITE_DATA_DST_SEL(8) | 6085 WR_CONFIRM) | 6086 WRITE_DATA_CACHE_POLICY(0)); 6087 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 6088 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 6089 6090 if (resume) 6091 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 6092 sizeof(de_payload) >> 2); 6093 else 6094 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 6095 sizeof(de_payload) >> 2); 6096 } 6097 6098 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 6099 bool secure) 6100 { 6101 uint32_t v = secure ? FRAME_TMZ : 0; 6102 6103 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 6104 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 6105 } 6106 6107 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 6108 uint32_t reg_val_offs) 6109 { 6110 struct amdgpu_device *adev = ring->adev; 6111 6112 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6113 amdgpu_ring_write(ring, 0 | /* src: register*/ 6114 (5 << 8) | /* dst: memory */ 6115 (1 << 20)); /* write confirm */ 6116 amdgpu_ring_write(ring, reg); 6117 amdgpu_ring_write(ring, 0); 6118 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6119 reg_val_offs * 4)); 6120 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6121 reg_val_offs * 4)); 6122 } 6123 6124 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6125 uint32_t val) 6126 { 6127 uint32_t cmd = 0; 6128 6129 switch (ring->funcs->type) { 6130 case AMDGPU_RING_TYPE_GFX: 6131 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 6132 break; 6133 case AMDGPU_RING_TYPE_KIQ: 6134 cmd = (1 << 16); /* no inc addr */ 6135 break; 6136 default: 6137 cmd = WR_CONFIRM; 6138 break; 6139 } 6140 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6141 amdgpu_ring_write(ring, cmd); 6142 amdgpu_ring_write(ring, reg); 6143 amdgpu_ring_write(ring, 0); 6144 amdgpu_ring_write(ring, val); 6145 } 6146 6147 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 6148 uint32_t val, uint32_t mask) 6149 { 6150 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 6151 } 6152 6153 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 6154 uint32_t reg0, uint32_t reg1, 6155 uint32_t ref, uint32_t mask) 6156 { 6157 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6158 6159 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 6160 ref, mask, 0x20); 6161 } 6162 6163 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 6164 unsigned vmid) 6165 { 6166 struct amdgpu_device *adev = ring->adev; 6167 uint32_t value = 0; 6168 6169 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 6170 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 6171 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 6172 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 6173 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 6174 WREG32_SOC15(GC, 0, regSQ_CMD, value); 6175 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 6176 } 6177 6178 static void 6179 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6180 uint32_t me, uint32_t pipe, 6181 enum amdgpu_interrupt_state state) 6182 { 6183 uint32_t cp_int_cntl, cp_int_cntl_reg; 6184 6185 if (!me) { 6186 switch (pipe) { 6187 case 0: 6188 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 6189 break; 6190 case 1: 6191 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 6192 break; 6193 default: 6194 DRM_DEBUG("invalid pipe %d\n", pipe); 6195 return; 6196 } 6197 } else { 6198 DRM_DEBUG("invalid me %d\n", me); 6199 return; 6200 } 6201 6202 switch (state) { 6203 case AMDGPU_IRQ_STATE_DISABLE: 6204 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6205 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6206 TIME_STAMP_INT_ENABLE, 0); 6207 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6208 GENERIC0_INT_ENABLE, 0); 6209 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6210 break; 6211 case AMDGPU_IRQ_STATE_ENABLE: 6212 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6213 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6214 TIME_STAMP_INT_ENABLE, 1); 6215 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6216 GENERIC0_INT_ENABLE, 1); 6217 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6218 break; 6219 default: 6220 break; 6221 } 6222 } 6223 6224 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6225 int me, int pipe, 6226 enum amdgpu_interrupt_state state) 6227 { 6228 u32 mec_int_cntl, mec_int_cntl_reg; 6229 6230 /* 6231 * amdgpu controls only the first MEC. That's why this function only 6232 * handles the setting of interrupts for this specific MEC. All other 6233 * pipes' interrupts are set by amdkfd. 6234 */ 6235 6236 if (me == 1) { 6237 switch (pipe) { 6238 case 0: 6239 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6240 break; 6241 case 1: 6242 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6243 break; 6244 case 2: 6245 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6246 break; 6247 case 3: 6248 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6249 break; 6250 default: 6251 DRM_DEBUG("invalid pipe %d\n", pipe); 6252 return; 6253 } 6254 } else { 6255 DRM_DEBUG("invalid me %d\n", me); 6256 return; 6257 } 6258 6259 switch (state) { 6260 case AMDGPU_IRQ_STATE_DISABLE: 6261 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6262 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6263 TIME_STAMP_INT_ENABLE, 0); 6264 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6265 GENERIC0_INT_ENABLE, 0); 6266 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6267 break; 6268 case AMDGPU_IRQ_STATE_ENABLE: 6269 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6270 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6271 TIME_STAMP_INT_ENABLE, 1); 6272 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6273 GENERIC0_INT_ENABLE, 1); 6274 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6275 break; 6276 default: 6277 break; 6278 } 6279 } 6280 6281 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6282 struct amdgpu_irq_src *src, 6283 unsigned type, 6284 enum amdgpu_interrupt_state state) 6285 { 6286 switch (type) { 6287 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6288 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6289 break; 6290 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6291 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6292 break; 6293 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6294 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6295 break; 6296 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6297 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6298 break; 6299 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6300 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6301 break; 6302 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6303 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6304 break; 6305 default: 6306 break; 6307 } 6308 return 0; 6309 } 6310 6311 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6312 struct amdgpu_irq_src *source, 6313 struct amdgpu_iv_entry *entry) 6314 { 6315 int i; 6316 u8 me_id, pipe_id, queue_id; 6317 struct amdgpu_ring *ring; 6318 uint32_t mes_queue_id = entry->src_data[0]; 6319 6320 DRM_DEBUG("IH: CP EOP\n"); 6321 6322 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6323 struct amdgpu_mes_queue *queue; 6324 6325 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6326 6327 spin_lock(&adev->mes.queue_id_lock); 6328 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6329 if (queue) { 6330 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6331 amdgpu_fence_process(queue->ring); 6332 } 6333 spin_unlock(&adev->mes.queue_id_lock); 6334 } else { 6335 me_id = (entry->ring_id & 0x0c) >> 2; 6336 pipe_id = (entry->ring_id & 0x03) >> 0; 6337 queue_id = (entry->ring_id & 0x70) >> 4; 6338 6339 switch (me_id) { 6340 case 0: 6341 if (pipe_id == 0) 6342 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6343 else 6344 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6345 break; 6346 case 1: 6347 case 2: 6348 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6349 ring = &adev->gfx.compute_ring[i]; 6350 /* Per-queue interrupt is supported for MEC starting from VI. 6351 * The interrupt can only be enabled/disabled per pipe instead 6352 * of per queue. 6353 */ 6354 if ((ring->me == me_id) && 6355 (ring->pipe == pipe_id) && 6356 (ring->queue == queue_id)) 6357 amdgpu_fence_process(ring); 6358 } 6359 break; 6360 } 6361 } 6362 6363 return 0; 6364 } 6365 6366 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6367 struct amdgpu_irq_src *source, 6368 unsigned int type, 6369 enum amdgpu_interrupt_state state) 6370 { 6371 u32 cp_int_cntl_reg, cp_int_cntl; 6372 int i, j; 6373 6374 switch (state) { 6375 case AMDGPU_IRQ_STATE_DISABLE: 6376 case AMDGPU_IRQ_STATE_ENABLE: 6377 for (i = 0; i < adev->gfx.me.num_me; i++) { 6378 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6379 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6380 6381 if (cp_int_cntl_reg) { 6382 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6383 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6384 PRIV_REG_INT_ENABLE, 6385 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6386 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6387 } 6388 } 6389 } 6390 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6391 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6392 /* MECs start at 1 */ 6393 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6394 6395 if (cp_int_cntl_reg) { 6396 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6397 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6398 PRIV_REG_INT_ENABLE, 6399 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6400 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6401 } 6402 } 6403 } 6404 break; 6405 default: 6406 break; 6407 } 6408 6409 return 0; 6410 } 6411 6412 static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev, 6413 struct amdgpu_irq_src *source, 6414 unsigned type, 6415 enum amdgpu_interrupt_state state) 6416 { 6417 u32 cp_int_cntl_reg, cp_int_cntl; 6418 int i, j; 6419 6420 switch (state) { 6421 case AMDGPU_IRQ_STATE_DISABLE: 6422 case AMDGPU_IRQ_STATE_ENABLE: 6423 for (i = 0; i < adev->gfx.me.num_me; i++) { 6424 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6425 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6426 6427 if (cp_int_cntl_reg) { 6428 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6429 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6430 OPCODE_ERROR_INT_ENABLE, 6431 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6432 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6433 } 6434 } 6435 } 6436 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6437 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6438 /* MECs start at 1 */ 6439 cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j); 6440 6441 if (cp_int_cntl_reg) { 6442 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6443 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6444 OPCODE_ERROR_INT_ENABLE, 6445 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6446 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6447 } 6448 } 6449 } 6450 break; 6451 default: 6452 break; 6453 } 6454 return 0; 6455 } 6456 6457 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6458 struct amdgpu_irq_src *source, 6459 unsigned int type, 6460 enum amdgpu_interrupt_state state) 6461 { 6462 u32 cp_int_cntl_reg, cp_int_cntl; 6463 int i, j; 6464 6465 switch (state) { 6466 case AMDGPU_IRQ_STATE_DISABLE: 6467 case AMDGPU_IRQ_STATE_ENABLE: 6468 for (i = 0; i < adev->gfx.me.num_me; i++) { 6469 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6470 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); 6471 6472 if (cp_int_cntl_reg) { 6473 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6474 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6475 PRIV_INSTR_INT_ENABLE, 6476 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6477 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6478 } 6479 } 6480 } 6481 break; 6482 default: 6483 break; 6484 } 6485 6486 return 0; 6487 } 6488 6489 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6490 struct amdgpu_iv_entry *entry) 6491 { 6492 u8 me_id, pipe_id, queue_id; 6493 struct amdgpu_ring *ring; 6494 int i; 6495 6496 me_id = (entry->ring_id & 0x0c) >> 2; 6497 pipe_id = (entry->ring_id & 0x03) >> 0; 6498 queue_id = (entry->ring_id & 0x70) >> 4; 6499 6500 switch (me_id) { 6501 case 0: 6502 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6503 ring = &adev->gfx.gfx_ring[i]; 6504 if (ring->me == me_id && ring->pipe == pipe_id && 6505 ring->queue == queue_id) 6506 drm_sched_fault(&ring->sched); 6507 } 6508 break; 6509 case 1: 6510 case 2: 6511 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6512 ring = &adev->gfx.compute_ring[i]; 6513 if (ring->me == me_id && ring->pipe == pipe_id && 6514 ring->queue == queue_id) 6515 drm_sched_fault(&ring->sched); 6516 } 6517 break; 6518 default: 6519 BUG(); 6520 break; 6521 } 6522 } 6523 6524 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6525 struct amdgpu_irq_src *source, 6526 struct amdgpu_iv_entry *entry) 6527 { 6528 DRM_ERROR("Illegal register access in command stream\n"); 6529 gfx_v11_0_handle_priv_fault(adev, entry); 6530 return 0; 6531 } 6532 6533 static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, 6534 struct amdgpu_irq_src *source, 6535 struct amdgpu_iv_entry *entry) 6536 { 6537 DRM_ERROR("Illegal opcode in command stream \n"); 6538 gfx_v11_0_handle_priv_fault(adev, entry); 6539 return 0; 6540 } 6541 6542 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6543 struct amdgpu_irq_src *source, 6544 struct amdgpu_iv_entry *entry) 6545 { 6546 DRM_ERROR("Illegal instruction in command stream\n"); 6547 gfx_v11_0_handle_priv_fault(adev, entry); 6548 return 0; 6549 } 6550 6551 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6552 struct amdgpu_irq_src *source, 6553 struct amdgpu_iv_entry *entry) 6554 { 6555 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6556 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6557 6558 return 0; 6559 } 6560 6561 #if 0 6562 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6563 struct amdgpu_irq_src *src, 6564 unsigned int type, 6565 enum amdgpu_interrupt_state state) 6566 { 6567 uint32_t tmp, target; 6568 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6569 6570 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6571 target += ring->pipe; 6572 6573 switch (type) { 6574 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6575 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6576 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6577 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6578 GENERIC2_INT_ENABLE, 0); 6579 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6580 6581 tmp = RREG32_SOC15_IP(GC, target); 6582 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6583 GENERIC2_INT_ENABLE, 0); 6584 WREG32_SOC15_IP(GC, target, tmp); 6585 } else { 6586 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6587 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6588 GENERIC2_INT_ENABLE, 1); 6589 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6590 6591 tmp = RREG32_SOC15_IP(GC, target); 6592 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6593 GENERIC2_INT_ENABLE, 1); 6594 WREG32_SOC15_IP(GC, target, tmp); 6595 } 6596 break; 6597 default: 6598 BUG(); /* kiq only support GENERIC2_INT now */ 6599 break; 6600 } 6601 return 0; 6602 } 6603 #endif 6604 6605 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6606 { 6607 const unsigned int gcr_cntl = 6608 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6609 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6610 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6611 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6612 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6613 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6614 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6615 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6616 6617 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6618 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6619 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6620 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6621 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6622 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6623 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6624 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6625 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6626 } 6627 6628 static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 6629 { 6630 struct amdgpu_device *adev = ring->adev; 6631 int r; 6632 6633 if (amdgpu_sriov_vf(adev)) 6634 return -EINVAL; 6635 6636 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 6637 if (r) 6638 return r; 6639 6640 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6641 if (unlikely(r != 0)) { 6642 dev_err(adev->dev, "fail to resv mqd_obj\n"); 6643 return r; 6644 } 6645 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6646 if (!r) { 6647 r = gfx_v11_0_kgq_init_queue(ring, true); 6648 amdgpu_bo_kunmap(ring->mqd_obj); 6649 ring->mqd_ptr = NULL; 6650 } 6651 amdgpu_bo_unreserve(ring->mqd_obj); 6652 if (r) { 6653 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 6654 return r; 6655 } 6656 6657 r = amdgpu_mes_map_legacy_queue(adev, ring); 6658 if (r) { 6659 dev_err(adev->dev, "failed to remap kgq\n"); 6660 return r; 6661 } 6662 6663 return amdgpu_ring_test_ring(ring); 6664 } 6665 6666 static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) 6667 { 6668 struct amdgpu_device *adev = ring->adev; 6669 int r = 0; 6670 6671 if (amdgpu_sriov_vf(adev)) 6672 return -EINVAL; 6673 6674 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 6675 if (r) { 6676 dev_err(adev->dev, "reset via MMIO failed %d\n", r); 6677 return r; 6678 } 6679 6680 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6681 if (unlikely(r != 0)) { 6682 dev_err(adev->dev, "fail to resv mqd_obj\n"); 6683 return r; 6684 } 6685 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6686 if (!r) { 6687 r = gfx_v11_0_kcq_init_queue(ring, true); 6688 amdgpu_bo_kunmap(ring->mqd_obj); 6689 ring->mqd_ptr = NULL; 6690 } 6691 amdgpu_bo_unreserve(ring->mqd_obj); 6692 if (r) { 6693 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 6694 return r; 6695 } 6696 r = amdgpu_mes_map_legacy_queue(adev, ring); 6697 if (r) { 6698 dev_err(adev->dev, "failed to remap kcq\n"); 6699 return r; 6700 } 6701 6702 return amdgpu_ring_test_ring(ring); 6703 } 6704 6705 static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 6706 { 6707 struct amdgpu_device *adev = ip_block->adev; 6708 uint32_t i, j, k, reg, index = 0; 6709 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6710 6711 if (!adev->gfx.ip_dump_core) 6712 return; 6713 6714 for (i = 0; i < reg_count; i++) 6715 drm_printf(p, "%-50s \t 0x%08x\n", 6716 gc_reg_list_11_0[i].reg_name, 6717 adev->gfx.ip_dump_core[i]); 6718 6719 /* print compute queue registers for all instances */ 6720 if (!adev->gfx.ip_dump_compute_queues) 6721 return; 6722 6723 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6724 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 6725 adev->gfx.mec.num_mec, 6726 adev->gfx.mec.num_pipe_per_mec, 6727 adev->gfx.mec.num_queue_per_pipe); 6728 6729 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6730 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6731 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6732 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 6733 for (reg = 0; reg < reg_count; reg++) { 6734 drm_printf(p, "%-50s \t 0x%08x\n", 6735 gc_cp_reg_list_11[reg].reg_name, 6736 adev->gfx.ip_dump_compute_queues[index + reg]); 6737 } 6738 index += reg_count; 6739 } 6740 } 6741 } 6742 6743 /* print gfx queue registers for all instances */ 6744 if (!adev->gfx.ip_dump_gfx_queues) 6745 return; 6746 6747 index = 0; 6748 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6749 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 6750 adev->gfx.me.num_me, 6751 adev->gfx.me.num_pipe_per_me, 6752 adev->gfx.me.num_queue_per_pipe); 6753 6754 for (i = 0; i < adev->gfx.me.num_me; i++) { 6755 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6756 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6757 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 6758 for (reg = 0; reg < reg_count; reg++) { 6759 drm_printf(p, "%-50s \t 0x%08x\n", 6760 gc_gfx_queue_reg_list_11[reg].reg_name, 6761 adev->gfx.ip_dump_gfx_queues[index + reg]); 6762 } 6763 index += reg_count; 6764 } 6765 } 6766 } 6767 } 6768 6769 static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 6770 { 6771 struct amdgpu_device *adev = ip_block->adev; 6772 uint32_t i, j, k, reg, index = 0; 6773 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); 6774 6775 if (!adev->gfx.ip_dump_core) 6776 return; 6777 6778 amdgpu_gfx_off_ctrl(adev, false); 6779 for (i = 0; i < reg_count; i++) 6780 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); 6781 amdgpu_gfx_off_ctrl(adev, true); 6782 6783 /* dump compute queue registers for all instances */ 6784 if (!adev->gfx.ip_dump_compute_queues) 6785 return; 6786 6787 reg_count = ARRAY_SIZE(gc_cp_reg_list_11); 6788 amdgpu_gfx_off_ctrl(adev, false); 6789 mutex_lock(&adev->srbm_mutex); 6790 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 6791 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 6792 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 6793 /* ME0 is for GFX so start from 1 for CP */ 6794 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 6795 for (reg = 0; reg < reg_count; reg++) { 6796 adev->gfx.ip_dump_compute_queues[index + reg] = 6797 RREG32(SOC15_REG_ENTRY_OFFSET( 6798 gc_cp_reg_list_11[reg])); 6799 } 6800 index += reg_count; 6801 } 6802 } 6803 } 6804 soc21_grbm_select(adev, 0, 0, 0, 0); 6805 mutex_unlock(&adev->srbm_mutex); 6806 amdgpu_gfx_off_ctrl(adev, true); 6807 6808 /* dump gfx queue registers for all instances */ 6809 if (!adev->gfx.ip_dump_gfx_queues) 6810 return; 6811 6812 index = 0; 6813 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11); 6814 amdgpu_gfx_off_ctrl(adev, false); 6815 mutex_lock(&adev->srbm_mutex); 6816 for (i = 0; i < adev->gfx.me.num_me; i++) { 6817 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 6818 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 6819 soc21_grbm_select(adev, i, j, k, 0); 6820 6821 for (reg = 0; reg < reg_count; reg++) { 6822 adev->gfx.ip_dump_gfx_queues[index + reg] = 6823 RREG32(SOC15_REG_ENTRY_OFFSET( 6824 gc_gfx_queue_reg_list_11[reg])); 6825 } 6826 index += reg_count; 6827 } 6828 } 6829 } 6830 soc21_grbm_select(adev, 0, 0, 0, 0); 6831 mutex_unlock(&adev->srbm_mutex); 6832 amdgpu_gfx_off_ctrl(adev, true); 6833 } 6834 6835 static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 6836 { 6837 /* Emit the cleaner shader */ 6838 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 6839 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 6840 } 6841 6842 static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring) 6843 { 6844 amdgpu_gfx_profile_ring_begin_use(ring); 6845 6846 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 6847 } 6848 6849 static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring) 6850 { 6851 amdgpu_gfx_profile_ring_end_use(ring); 6852 6853 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 6854 } 6855 6856 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6857 .name = "gfx_v11_0", 6858 .early_init = gfx_v11_0_early_init, 6859 .late_init = gfx_v11_0_late_init, 6860 .sw_init = gfx_v11_0_sw_init, 6861 .sw_fini = gfx_v11_0_sw_fini, 6862 .hw_init = gfx_v11_0_hw_init, 6863 .hw_fini = gfx_v11_0_hw_fini, 6864 .suspend = gfx_v11_0_suspend, 6865 .resume = gfx_v11_0_resume, 6866 .is_idle = gfx_v11_0_is_idle, 6867 .wait_for_idle = gfx_v11_0_wait_for_idle, 6868 .soft_reset = gfx_v11_0_soft_reset, 6869 .check_soft_reset = gfx_v11_0_check_soft_reset, 6870 .post_soft_reset = gfx_v11_0_post_soft_reset, 6871 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6872 .set_powergating_state = gfx_v11_0_set_powergating_state, 6873 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6874 .dump_ip_state = gfx_v11_ip_dump, 6875 .print_ip_state = gfx_v11_ip_print, 6876 }; 6877 6878 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6879 .type = AMDGPU_RING_TYPE_GFX, 6880 .align_mask = 0xff, 6881 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6882 .support_64bit_ptrs = true, 6883 .secure_submission_supported = true, 6884 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6885 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6886 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6887 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 6888 5 + /* update_spm_vmid */ 6889 5 + /* COND_EXEC */ 6890 22 + /* SET_Q_PREEMPTION_MODE */ 6891 7 + /* PIPELINE_SYNC */ 6892 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6893 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6894 4 + /* VM_FLUSH */ 6895 8 + /* FENCE for VM_FLUSH */ 6896 20 + /* GDS switch */ 6897 5 + /* COND_EXEC */ 6898 7 + /* HDP_flush */ 6899 4 + /* VGT_flush */ 6900 31 + /* DE_META */ 6901 3 + /* CNTX_CTRL */ 6902 5 + /* HDP_INVL */ 6903 22 + /* SET_Q_PREEMPTION_MODE */ 6904 8 + 8 + /* FENCE x2 */ 6905 8 + /* gfx_v11_0_emit_mem_sync */ 6906 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 6907 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6908 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6909 .emit_fence = gfx_v11_0_ring_emit_fence, 6910 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6911 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6912 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6913 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6914 .test_ring = gfx_v11_0_ring_test_ring, 6915 .test_ib = gfx_v11_0_ring_test_ib, 6916 .insert_nop = gfx_v11_ring_insert_nop, 6917 .pad_ib = amdgpu_ring_generic_pad_ib, 6918 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6919 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6920 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6921 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6922 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6923 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6924 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6925 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6926 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6927 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6928 .reset = gfx_v11_0_reset_kgq, 6929 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 6930 .begin_use = gfx_v11_0_ring_begin_use, 6931 .end_use = gfx_v11_0_ring_end_use, 6932 }; 6933 6934 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6935 .type = AMDGPU_RING_TYPE_COMPUTE, 6936 .align_mask = 0xff, 6937 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6938 .support_64bit_ptrs = true, 6939 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6940 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6941 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6942 .emit_frame_size = 6943 5 + /* update_spm_vmid */ 6944 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6945 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6946 5 + /* hdp invalidate */ 6947 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6948 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6949 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6950 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6951 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6952 8 + /* gfx_v11_0_emit_mem_sync */ 6953 2, /* gfx_v11_0_ring_emit_cleaner_shader */ 6954 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6955 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6956 .emit_fence = gfx_v11_0_ring_emit_fence, 6957 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6958 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6959 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6960 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6961 .test_ring = gfx_v11_0_ring_test_ring, 6962 .test_ib = gfx_v11_0_ring_test_ib, 6963 .insert_nop = gfx_v11_ring_insert_nop, 6964 .pad_ib = amdgpu_ring_generic_pad_ib, 6965 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6966 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6967 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6968 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6969 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6970 .reset = gfx_v11_0_reset_kcq, 6971 .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, 6972 .begin_use = gfx_v11_0_ring_begin_use, 6973 .end_use = gfx_v11_0_ring_end_use, 6974 }; 6975 6976 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6977 .type = AMDGPU_RING_TYPE_KIQ, 6978 .align_mask = 0xff, 6979 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6980 .support_64bit_ptrs = true, 6981 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6982 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6983 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6984 .emit_frame_size = 6985 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6986 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6987 5 + /*hdp invalidate */ 6988 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6989 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6990 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6991 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6992 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6993 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6994 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6995 .test_ring = gfx_v11_0_ring_test_ring, 6996 .test_ib = gfx_v11_0_ring_test_ib, 6997 .insert_nop = amdgpu_ring_insert_nop, 6998 .pad_ib = amdgpu_ring_generic_pad_ib, 6999 .emit_rreg = gfx_v11_0_ring_emit_rreg, 7000 .emit_wreg = gfx_v11_0_ring_emit_wreg, 7001 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 7002 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 7003 }; 7004 7005 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 7006 { 7007 int i; 7008 7009 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 7010 7011 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7012 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 7013 7014 for (i = 0; i < adev->gfx.num_compute_rings; i++) 7015 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 7016 } 7017 7018 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 7019 .set = gfx_v11_0_set_eop_interrupt_state, 7020 .process = gfx_v11_0_eop_irq, 7021 }; 7022 7023 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 7024 .set = gfx_v11_0_set_priv_reg_fault_state, 7025 .process = gfx_v11_0_priv_reg_irq, 7026 }; 7027 7028 static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = { 7029 .set = gfx_v11_0_set_bad_op_fault_state, 7030 .process = gfx_v11_0_bad_op_irq, 7031 }; 7032 7033 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 7034 .set = gfx_v11_0_set_priv_inst_fault_state, 7035 .process = gfx_v11_0_priv_inst_irq, 7036 }; 7037 7038 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 7039 .process = gfx_v11_0_rlc_gc_fed_irq, 7040 }; 7041 7042 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 7043 { 7044 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7045 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 7046 7047 adev->gfx.priv_reg_irq.num_types = 1; 7048 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 7049 7050 adev->gfx.bad_op_irq.num_types = 1; 7051 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; 7052 7053 adev->gfx.priv_inst_irq.num_types = 1; 7054 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 7055 7056 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 7057 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 7058 7059 } 7060 7061 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 7062 { 7063 if (adev->flags & AMD_IS_APU) 7064 adev->gfx.imu.mode = MISSION_MODE; 7065 else 7066 adev->gfx.imu.mode = DEBUG_MODE; 7067 7068 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 7069 } 7070 7071 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 7072 { 7073 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 7074 } 7075 7076 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 7077 { 7078 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 7079 adev->gfx.config.max_sh_per_se * 7080 adev->gfx.config.max_shader_engines; 7081 7082 adev->gds.gds_size = 0x1000; 7083 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 7084 adev->gds.gws_size = 64; 7085 adev->gds.oa_size = 16; 7086 } 7087 7088 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 7089 { 7090 /* set gfx eng mqd */ 7091 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 7092 sizeof(struct v11_gfx_mqd); 7093 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 7094 gfx_v11_0_gfx_mqd_init; 7095 /* set compute eng mqd */ 7096 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 7097 sizeof(struct v11_compute_mqd); 7098 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 7099 gfx_v11_0_compute_mqd_init; 7100 } 7101 7102 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 7103 u32 bitmap) 7104 { 7105 u32 data; 7106 7107 if (!bitmap) 7108 return; 7109 7110 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7111 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7112 7113 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 7114 } 7115 7116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 7117 { 7118 u32 data, wgp_bitmask; 7119 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 7120 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 7121 7122 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 7123 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 7124 7125 wgp_bitmask = 7126 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 7127 7128 return (~data) & wgp_bitmask; 7129 } 7130 7131 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 7132 { 7133 u32 wgp_idx, wgp_active_bitmap; 7134 u32 cu_bitmap_per_wgp, cu_active_bitmap; 7135 7136 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 7137 cu_active_bitmap = 0; 7138 7139 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 7140 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 7141 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 7142 if (wgp_active_bitmap & (1 << wgp_idx)) 7143 cu_active_bitmap |= cu_bitmap_per_wgp; 7144 } 7145 7146 return cu_active_bitmap; 7147 } 7148 7149 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 7150 struct amdgpu_cu_info *cu_info) 7151 { 7152 int i, j, k, counter, active_cu_number = 0; 7153 u32 mask, bitmap; 7154 unsigned disable_masks[8 * 2]; 7155 7156 if (!adev || !cu_info) 7157 return -EINVAL; 7158 7159 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 7160 7161 mutex_lock(&adev->grbm_idx_mutex); 7162 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7163 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7164 bitmap = i * adev->gfx.config.max_sh_per_se + j; 7165 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 7166 continue; 7167 mask = 1; 7168 counter = 0; 7169 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7170 if (i < 8 && j < 2) 7171 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 7172 adev, disable_masks[i * 2 + j]); 7173 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 7174 7175 /** 7176 * GFX11 could support more than 4 SEs, while the bitmap 7177 * in cu_info struct is 4x4 and ioctl interface struct 7178 * drm_amdgpu_info_device should keep stable. 7179 * So we use last two columns of bitmap to store cu mask for 7180 * SEs 4 to 7, the layout of the bitmap is as below: 7181 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 7182 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 7183 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 7184 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 7185 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 7186 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 7187 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 7188 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 7189 */ 7190 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 7191 7192 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 7193 if (bitmap & mask) 7194 counter++; 7195 7196 mask <<= 1; 7197 } 7198 active_cu_number += counter; 7199 } 7200 } 7201 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7202 mutex_unlock(&adev->grbm_idx_mutex); 7203 7204 cu_info->number = active_cu_number; 7205 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7206 7207 return 0; 7208 } 7209 7210 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 7211 { 7212 .type = AMD_IP_BLOCK_TYPE_GFX, 7213 .major = 11, 7214 .minor = 0, 7215 .rev = 0, 7216 .funcs = &gfx_v11_0_ip_funcs, 7217 }; 7218